From nadav.rotem at intel.com Mon Dec 5 00:29:10 2011 From: nadav.rotem at intel.com (Nadav Rotem) Date: Mon, 05 Dec 2011 06:29:10 -0000 Subject: [llvm-commits] [llvm] r145801 - in /llvm/trunk: docs/ include/llvm/ include/llvm/Target/ lib/Analysis/ lib/AsmParser/ lib/CodeGen/SelectionDAG/ lib/Transforms/InstCombine/ lib/Transforms/Scalar/ lib/VMCore/ test/CodeGen/X86/ test/Feature/ test/Transforms/InstCombine/ test/Transforms/InstSimplify/ unittests/VMCore/ Message-ID: <20111205062911.265551BE003@llvm.org> Author: nadav Date: Mon Dec 5 00:29:09 2011 New Revision: 145801 URL: http://llvm.org/viewvc/llvm-project?rev=145801&view=rev Log: Add support for vectors of pointers. Added: llvm/trunk/test/CodeGen/X86/pointer-vector.ll llvm/trunk/test/CodeGen/X86/vector-gep.ll llvm/trunk/test/Feature/const_pv.ll llvm/trunk/test/Feature/global_pv.ll llvm/trunk/test/Transforms/InstCombine/vector_gep1.ll llvm/trunk/test/Transforms/InstSimplify/vector_gep.ll Modified: llvm/trunk/docs/LangRef.html llvm/trunk/include/llvm/DerivedTypes.h llvm/trunk/include/llvm/Instructions.h llvm/trunk/include/llvm/Operator.h llvm/trunk/include/llvm/Target/TargetLowering.h llvm/trunk/include/llvm/Type.h llvm/trunk/lib/Analysis/ConstantFolding.cpp llvm/trunk/lib/Analysis/InstructionSimplify.cpp llvm/trunk/lib/Analysis/ValueTracking.cpp llvm/trunk/lib/AsmParser/LLParser.cpp llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp llvm/trunk/lib/Transforms/InstCombine/InstCombineCalls.cpp llvm/trunk/lib/Transforms/InstCombine/InstructionCombining.cpp llvm/trunk/lib/Transforms/Scalar/IndVarSimplify.cpp llvm/trunk/lib/Transforms/Scalar/ScalarReplAggregates.cpp llvm/trunk/lib/VMCore/Constants.cpp llvm/trunk/lib/VMCore/Instructions.cpp llvm/trunk/lib/VMCore/Type.cpp llvm/trunk/lib/VMCore/Verifier.cpp llvm/trunk/unittests/VMCore/InstructionsTest.cpp Modified: llvm/trunk/docs/LangRef.html URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/LangRef.html?rev=145801&r1=145800&r2=145801&view=diff ============================================================================== --- llvm/trunk/docs/LangRef.html (original) +++ llvm/trunk/docs/LangRef.html Mon Dec 5 00:29:09 2011 @@ -2189,8 +2189,8 @@

The number of elements is a constant integer value larger than 0; elementtype - may be any integer or floating point type. Vectors of size zero are not - allowed, and pointers are not allowed as the element type.

+ may be any integer or floating point type, or a pointer to these types. + Vectors of size zero are not allowed.

Examples:
@@ -2206,6 +2206,10 @@ + + + +
<2 x i64> Vector of 2 64-bit integer values.
<4 x i64*>Vector of 4 pointers to 64-bit integer values.
@@ -5069,6 +5073,7 @@ 
   <result> = getelementptr <pty>* <ptrval>{, <ty> <idx>}*
   <result> = getelementptr inbounds <pty>* <ptrval>{, <ty> <idx>}*
+  <result> = getelementptr <ptr vector> ptrval, <vector index type> idx
Overview:
@@ -5077,7 +5082,8 @@ It performs address calculation only and does not access memory.

Arguments:
-

The first argument is always a pointer, and forms the basis of the +

The first argument is always a pointer or a vector of pointers, + and forms the basis of the calculation. The remaining arguments are indices that indicate which of the elements of the aggregate object are indexed. The interpretation of each index is dependent on the type being indexed into. The first index always @@ -5162,7 +5168,9 @@ precise signed arithmetic are not an in bounds address of that allocated object. The in bounds addresses for an allocated object are all the addresses that point into the object, plus the address one - byte past the end.

+ byte past the end. + In cases where the base is a vector of pointers the inbounds keyword + applies to each of the computations element-wise.

If the inbounds keyword is not present, the offsets are added to the base address with silently-wrapping two's complement arithmetic. If the @@ -5189,6 +5197,13 @@ %iptr = getelementptr [10 x i32]* @arr, i16 0, i16 0 +

In cases where the pointer argument is a vector of pointers, only a + single index may be used, and the number of vector elements has to be + the same. For example:

+
+ %A = getelementptr <4 x i8*> %ptrs, <4 x i64> %offsets,
+
+ @@ -5561,13 +5576,16 @@
Overview:
-

The 'ptrtoint' instruction converts the pointer value to - the integer type ty2.

+

The 'ptrtoint' instruction converts the pointer or a vector of + pointers value to + the integer (or vector of integers) type ty2.

Arguments:

The 'ptrtoint' instruction takes a value to cast, which - must be a pointer value, and a type to cast it to - ty2, which must be an integer type.

+ must be a a value of type pointer or a vector of + pointers, and a type to cast it to + ty2, which must be an integer or a vector + of integers type.

Semantics:

The 'ptrtoint' instruction converts value to integer type @@ -5580,8 +5598,9 @@

Example:
-  %X = ptrtoint i32* %X to i8           ; yields truncation on 32-bit architecture
-  %Y = ptrtoint i32* %x to i64          ; yields zero extension on 32-bit architecture
+  %X = ptrtoint i32* %P to i8                         ; yields truncation on 32-bit architecture
+  %Y = ptrtoint i32* %P to i64                        ; yields zero extension on 32-bit architecture
+  %Z = ptrtoint <4 x i32*> %P to <4 x i64>; yields vector zero extension for a vector of addresses on 32-bit architecture
@@ -5620,6 +5639,7 @@ %X = inttoptr i32 255 to i32* ; yields zero extension on 64-bit architecture %Y = inttoptr i32 255 to i32* ; yields no-op on 32-bit architecture %Z = inttoptr i64 0 to i32* ; yields truncation on 32-bit architecture + %Z = inttoptr <4 x i32> %G to <4 x i8*>; yields truncation of vector G to four pointers @@ -5654,8 +5674,9 @@

The 'bitcast' instruction converts value to type ty2. It is always a no-op cast because no bits change with this conversion. The conversion is done as if the value had been - stored to memory and read back as type ty2. Pointer types may only - be converted to other pointer types with this instruction. To convert + stored to memory and read back as type ty2. + Pointer (or vector of pointers) types may only be converted to other pointer + (or vector of pointers) types with this instruction. To convert pointers to other types, use the inttoptr or ptrtoint instructions first.

@@ -5663,7 +5684,8 @@ 
   %X = bitcast i8 255 to i8              ; yields i8 :-1
   %Y = bitcast i32* %x to sint*          ; yields sint*:%x
-  %Z = bitcast <2 x int> %V to i64;      ; yields i64: %V
+  %Z = bitcast <2 x int> %V to i64;        ; yields i64: %V
+  %Z = bitcast <2 x i32*> %V to <2 x i64*> ; yields <2 x i64*>
@@ -5694,8 +5716,8 @@
Overview:

The 'icmp' instruction returns a boolean value or a vector of - boolean values based on comparison of its two integer, integer vector, or - pointer operands.

+ boolean values based on comparison of its two integer, integer vector, + pointer, or pointer vector operands.

Arguments:

The 'icmp' instruction takes three operands. The first operand is Modified: llvm/trunk/include/llvm/DerivedTypes.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/DerivedTypes.h?rev=145801&r1=145800&r2=145801&view=diff ============================================================================== --- llvm/trunk/include/llvm/DerivedTypes.h (original) +++ llvm/trunk/include/llvm/DerivedTypes.h Mon Dec 5 00:29:09 2011 @@ -374,6 +374,7 @@ /// static VectorType *getInteger(VectorType *VTy) { unsigned EltBits = VTy->getElementType()->getPrimitiveSizeInBits(); + assert(EltBits && "Element size must be of a non-zero size"); Type *EltTy = IntegerType::get(VTy->getContext(), EltBits); return VectorType::get(EltTy, VTy->getNumElements()); } @@ -408,6 +409,7 @@ unsigned getNumElements() const { return NumElements; } /// @brief Return the number of bits in the Vector type. + /// Returns zero when the vector is a vector of pointers. unsigned getBitWidth() const { return NumElements * getElementType()->getPrimitiveSizeInBits(); } Modified: llvm/trunk/include/llvm/Instructions.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Instructions.h?rev=145801&r1=145800&r2=145801&view=diff ============================================================================== --- llvm/trunk/include/llvm/Instructions.h (original) +++ llvm/trunk/include/llvm/Instructions.h Mon Dec 5 00:29:09 2011 @@ -776,6 +776,10 @@ static Type *getIndexedType(Type *Ptr, ArrayRef IdxList); static Type *getIndexedType(Type *Ptr, ArrayRef IdxList); + /// getIndexedType - Returns the address space used by the GEP pointer. + /// + static unsigned getAddressSpace(Value *Ptr); + inline op_iterator idx_begin() { return op_begin()+1; } inline const_op_iterator idx_begin() const { return op_begin()+1; } inline op_iterator idx_end() { return op_end(); } @@ -788,7 +792,7 @@ return getOperand(0); } static unsigned getPointerOperandIndex() { - return 0U; // get index for modifying correct operand + return 0U; // get index for modifying correct operand. } unsigned getPointerAddressSpace() const { @@ -797,10 +801,25 @@ /// getPointerOperandType - Method to return the pointer operand as a /// PointerType. - PointerType *getPointerOperandType() const { - return reinterpret_cast(getPointerOperand()->getType()); + Type *getPointerOperandType() const { + return getPointerOperand()->getType(); } + /// GetGEPReturnType - Returns the pointer type returned by the GEP + /// instruction, which may be a vector of pointers. + static Type *getGEPReturnType(Value *Ptr, ArrayRef IdxList) { + Type *PtrTy = PointerType::get(checkGEPType( + getIndexedType(Ptr->getType(), IdxList)), + getAddressSpace(Ptr)); + // Vector GEP + if (Ptr->getType()->isVectorTy()) { + unsigned NumElem = cast(Ptr->getType())->getNumElements(); + return VectorType::get(PtrTy, NumElem); + } + + // Scalar GEP + return PtrTy; + } unsigned getNumIndices() const { // Note: always non-negative return getNumOperands() - 1; @@ -847,10 +866,7 @@ unsigned Values, const Twine &NameStr, Instruction *InsertBefore) - : Instruction(PointerType::get(checkGEPType( - getIndexedType(Ptr->getType(), IdxList)), - cast(Ptr->getType()) - ->getAddressSpace()), + : Instruction(getGEPReturnType(Ptr, IdxList), GetElementPtr, OperandTraits::op_end(this) - Values, Values, InsertBefore) { @@ -861,10 +877,7 @@ unsigned Values, const Twine &NameStr, BasicBlock *InsertAtEnd) - : Instruction(PointerType::get(checkGEPType( - getIndexedType(Ptr->getType(), IdxList)), - cast(Ptr->getType()) - ->getAddressSpace()), + : Instruction(getGEPReturnType(Ptr, IdxList), GetElementPtr, OperandTraits::op_end(this) - Values, Values, InsertAtEnd) { @@ -905,7 +918,7 @@ "Both operands to ICmp instruction are not of the same type!"); // Check that the operands are the right type assert((getOperand(0)->getType()->isIntOrIntVectorTy() || - getOperand(0)->getType()->isPointerTy()) && + getOperand(0)->getType()->getScalarType()->isPointerTy()) && "Invalid operand types for ICmp instruction"); } @@ -945,7 +958,7 @@ "Both operands to ICmp instruction are not of the same type!"); // Check that the operands are the right type assert((getOperand(0)->getType()->isIntOrIntVectorTy() || - getOperand(0)->getType()->isPointerTy()) && + getOperand(0)->getType()->getScalarType()->isPointerTy()) && "Invalid operand types for ICmp instruction"); } Modified: llvm/trunk/include/llvm/Operator.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Operator.h?rev=145801&r1=145800&r2=145801&view=diff ============================================================================== --- llvm/trunk/include/llvm/Operator.h (original) +++ llvm/trunk/include/llvm/Operator.h Mon Dec 5 00:29:09 2011 @@ -261,8 +261,8 @@ /// getPointerOperandType - Method to return the pointer operand as a /// PointerType. - PointerType *getPointerOperandType() const { - return reinterpret_cast(getPointerOperand()->getType()); + Type *getPointerOperandType() const { + return getPointerOperand()->getType(); } unsigned getNumIndices() const { // Note: always non-negative Modified: llvm/trunk/include/llvm/Target/TargetLowering.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetLowering.h?rev=145801&r1=145800&r2=145801&view=diff ============================================================================== --- llvm/trunk/include/llvm/Target/TargetLowering.h (original) +++ llvm/trunk/include/llvm/Target/TargetLowering.h Mon Dec 5 00:29:09 2011 @@ -520,8 +520,19 @@ /// AllowUnknown is true, this will return MVT::Other for types with no EVT /// counterpart (e.g. structs), otherwise it will assert. EVT getValueType(Type *Ty, bool AllowUnknown = false) const { - EVT VT = EVT::getEVT(Ty, AllowUnknown); - return VT == MVT::iPTR ? PointerTy : VT; + // Lower scalar pointers to native pointer types. + if (Ty->isPointerTy()) return PointerTy; + + if (Ty->isVectorTy()) { + VectorType *VTy = cast(Ty); + Type *Elm = VTy->getElementType(); + // Lower vectors of pointers to native pointer types. + if (Elm->isPointerTy()) + Elm = EVT(PointerTy).getTypeForEVT(Ty->getContext()); + return EVT::getVectorVT(Ty->getContext(), EVT::getEVT(Elm, false), + VTy->getNumElements()); + } + return EVT::getEVT(Ty, AllowUnknown); } /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate Modified: llvm/trunk/include/llvm/Type.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Type.h?rev=145801&r1=145800&r2=145801&view=diff ============================================================================== --- llvm/trunk/include/llvm/Type.h (original) +++ llvm/trunk/include/llvm/Type.h Mon Dec 5 00:29:09 2011 @@ -273,6 +273,10 @@ /// otherwise return 'this'. Type *getScalarType(); + /// getNumElements - If this is a vector type, return the number of elements, + /// otherwise return zero. + unsigned getNumElements(); + //===--------------------------------------------------------------------===// // Type Iteration support. // Modified: llvm/trunk/lib/Analysis/ConstantFolding.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/ConstantFolding.cpp?rev=145801&r1=145800&r2=145801&view=diff ============================================================================== --- llvm/trunk/lib/Analysis/ConstantFolding.cpp (original) +++ llvm/trunk/lib/Analysis/ConstantFolding.cpp Mon Dec 5 00:29:09 2011 @@ -580,7 +580,8 @@ Type *ResultTy, const TargetData *TD, const TargetLibraryInfo *TLI) { Constant *Ptr = Ops[0]; - if (!TD || !cast(Ptr->getType())->getElementType()->isSized()) + if (!TD || !cast(Ptr->getType())->getElementType()->isSized() || + !Ptr->getType()->isPointerTy()) return 0; Type *IntPtrTy = TD->getIntPtrType(Ptr->getContext()); Modified: llvm/trunk/lib/Analysis/InstructionSimplify.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/InstructionSimplify.cpp?rev=145801&r1=145800&r2=145801&view=diff ============================================================================== --- llvm/trunk/lib/Analysis/InstructionSimplify.cpp (original) +++ llvm/trunk/lib/Analysis/InstructionSimplify.cpp Mon Dec 5 00:29:09 2011 @@ -1764,7 +1764,7 @@ // also a case of comparing two zero-extended values. if (RExt == CI && MaxRecurse) if (Value *V = SimplifyICmpInst(ICmpInst::getUnsignedPredicate(Pred), - SrcOp, Trunc, TD, TLI, DT, MaxRecurse-1)) + SrcOp, Trunc, TD, TLI, DT, MaxRecurse-1)) return V; // Otherwise the upper bits of LHS are zero while RHS has a non-zero bit @@ -2359,7 +2359,10 @@ Value *llvm::SimplifyGEPInst(ArrayRef Ops, const TargetData *TD, const DominatorTree *) { // The type of the GEP pointer operand. - PointerType *PtrTy = cast(Ops[0]->getType()); + PointerType *PtrTy = dyn_cast(Ops[0]->getType()); + // The GEP pointer operand is not a pointer, it's a vector of pointers. + if (!PtrTy) + return 0; // getelementptr P -> P. if (Ops.size() == 1) Modified: llvm/trunk/lib/Analysis/ValueTracking.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/ValueTracking.cpp?rev=145801&r1=145800&r2=145801&view=diff ============================================================================== --- llvm/trunk/lib/Analysis/ValueTracking.cpp (original) +++ llvm/trunk/lib/Analysis/ValueTracking.cpp Mon Dec 5 00:29:09 2011 @@ -63,13 +63,14 @@ assert(V && "No Value?"); assert(Depth <= MaxDepth && "Limit Search Depth"); unsigned BitWidth = Mask.getBitWidth(); - assert((V->getType()->isIntOrIntVectorTy() || V->getType()->isPointerTy()) - && "Not integer or pointer type!"); + assert((V->getType()->isIntOrIntVectorTy() || + V->getType()->getScalarType()->isPointerTy()) && + "Not integer or pointer type!"); assert((!TD || TD->getTypeSizeInBits(V->getType()->getScalarType()) == BitWidth) && (!V->getType()->isIntOrIntVectorTy() || V->getType()->getScalarSizeInBits() == BitWidth) && - KnownZero.getBitWidth() == BitWidth && + KnownZero.getBitWidth() == BitWidth && KnownOne.getBitWidth() == BitWidth && "V, Mask, KnownOne and KnownZero should have same BitWidth"); @@ -1557,7 +1558,8 @@ Value *llvm::GetPointerBaseWithConstantOffset(Value *Ptr, int64_t &Offset, const TargetData &TD) { Operator *PtrOp = dyn_cast(Ptr); - if (PtrOp == 0) return Ptr; + if (PtrOp == 0 || Ptr->getType()->isVectorTy()) + return Ptr; // Just look through bitcasts. if (PtrOp->getOpcode() == Instruction::BitCast) Modified: llvm/trunk/lib/AsmParser/LLParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/AsmParser/LLParser.cpp?rev=145801&r1=145800&r2=145801&view=diff ============================================================================== --- llvm/trunk/lib/AsmParser/LLParser.cpp (original) +++ llvm/trunk/lib/AsmParser/LLParser.cpp Mon Dec 5 00:29:09 2011 @@ -1607,7 +1607,8 @@ if ((unsigned)Size != Size) return Error(SizeLoc, "size too large for vector"); if (!VectorType::isValidElementType(EltTy)) - return Error(TypeLoc, "vector element type must be fp or integer"); + return Error(TypeLoc, + "vector element type must be fp, integer or a pointer to these types"); Result = VectorType::get(EltTy, unsigned(Size)); } else { if (!ArrayType::isValidElementType(EltTy)) @@ -1966,9 +1967,10 @@ return Error(ID.Loc, "constant vector must not be empty"); if (!Elts[0]->getType()->isIntegerTy() && - !Elts[0]->getType()->isFloatingPointTy()) + !Elts[0]->getType()->isFloatingPointTy() && + !Elts[0]->getType()->isPointerTy()) return Error(FirstEltLoc, - "vector elements must have integer or floating point type"); + "vector elements must have integer, pointer or floating point type"); // Verify that all the vector elements have the same type. for (unsigned i = 1, e = Elts.size(); i != e; ++i) @@ -2160,7 +2162,7 @@ } else { assert(Opc == Instruction::ICmp && "Unexpected opcode for CmpInst!"); if (!Val0->getType()->isIntOrIntVectorTy() && - !Val0->getType()->isPointerTy()) + !Val0->getType()->getScalarType()->isPointerTy()) return Error(ID.Loc, "icmp requires pointer or integer operands"); ID.ConstantVal = ConstantExpr::getICmp(Pred, Val0, Val1); } @@ -2294,7 +2296,8 @@ return true; if (Opc == Instruction::GetElementPtr) { - if (Elts.size() == 0 || !Elts[0]->getType()->isPointerTy()) + if (Elts.size() == 0 || + !Elts[0]->getType()->getScalarType()->isPointerTy()) return Error(ID.Loc, "getelementptr requires pointer operand"); ArrayRef Indices(Elts.begin() + 1, Elts.end()); @@ -3329,7 +3332,7 @@ } else { assert(Opc == Instruction::ICmp && "Unknown opcode for CmpInst!"); if (!LHS->getType()->isIntOrIntVectorTy() && - !LHS->getType()->isPointerTy()) + !LHS->getType()->getScalarType()->isPointerTy()) return Error(Loc, "icmp requires integer operands"); Inst = new ICmpInst(CmpInst::Predicate(Pred), LHS, RHS); } @@ -3877,13 +3880,15 @@ /// ParseGetElementPtr /// ::= 'getelementptr' 'inbounds'? TypeAndValue (',' TypeAndValue)* int LLParser::ParseGetElementPtr(Instruction *&Inst, PerFunctionState &PFS) { - Value *Ptr, *Val; LocTy Loc, EltLoc; + Value *Ptr = 0; + Value *Val = 0; + LocTy Loc, EltLoc; bool InBounds = EatIfPresent(lltok::kw_inbounds); if (ParseTypeAndValue(Ptr, Loc, PFS)) return true; - if (!Ptr->getType()->isPointerTy()) + if (!Ptr->getType()->getScalarType()->isPointerTy()) return Error(Loc, "base of getelementptr must be a pointer"); SmallVector Indices; @@ -3894,11 +3899,23 @@ break; } if (ParseTypeAndValue(Val, EltLoc, PFS)) return true; - if (!Val->getType()->isIntegerTy()) + if (!Val->getType()->getScalarType()->isIntegerTy()) return Error(EltLoc, "getelementptr index must be an integer"); + if (Val->getType()->isVectorTy() != Ptr->getType()->isVectorTy()) + return Error(EltLoc, "getelementptr index type missmatch"); + if (Val->getType()->isVectorTy()) { + unsigned ValNumEl = cast(Val->getType())->getNumElements(); + unsigned PtrNumEl = cast(Ptr->getType())->getNumElements(); + if (ValNumEl != PtrNumEl) + return Error(EltLoc, + "getelementptr vector index has a wrong number of elements"); + } Indices.push_back(Val); } + if (Val && Val->getType()->isVectorTy() && Indices.size() != 1) + return Error(EltLoc, "vector getelementptrs must have a single index"); + if (!GetElementPtrInst::getIndexedType(Ptr->getType(), Indices)) return Error(Loc, "invalid getelementptr indices"); Inst = GetElementPtrInst::Create(Ptr, Indices); Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp?rev=145801&r1=145800&r2=145801&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp Mon Dec 5 00:29:09 2011 @@ -3099,7 +3099,7 @@ unsigned Amt = ElementSize.logBase2(); IdxN = DAG.getNode(ISD::SHL, getCurDebugLoc(), N.getValueType(), IdxN, - DAG.getConstant(Amt, TLI.getPointerTy())); + DAG.getConstant(Amt, IdxN.getValueType())); } else { SDValue Scale = DAG.getConstant(ElementSize, TLI.getPointerTy()); IdxN = DAG.getNode(ISD::MUL, getCurDebugLoc(), Modified: llvm/trunk/lib/Transforms/InstCombine/InstCombineCalls.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/InstCombine/InstCombineCalls.cpp?rev=145801&r1=145800&r2=145801&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/InstCombine/InstCombineCalls.cpp (original) +++ llvm/trunk/lib/Transforms/InstCombine/InstCombineCalls.cpp Mon Dec 5 00:29:09 2011 @@ -265,6 +265,8 @@ // Get the current byte offset into the thing. Use the original // operand in case we're looking through a bitcast. SmallVector Ops(GEP->idx_begin(), GEP->idx_end()); + if (!GEP->getPointerOperandType()->isPointerTy()) + return 0; Offset = TD->getIndexedOffset(GEP->getPointerOperandType(), Ops); Op1 = GEP->getPointerOperand()->stripPointerCasts(); Modified: llvm/trunk/lib/Transforms/InstCombine/InstructionCombining.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/InstCombine/InstructionCombining.cpp?rev=145801&r1=145800&r2=145801&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/InstCombine/InstructionCombining.cpp (original) +++ llvm/trunk/lib/Transforms/InstCombine/InstructionCombining.cpp Mon Dec 5 00:29:09 2011 @@ -831,7 +831,8 @@ MadeChange = true; } - if ((*I)->getType() != IntPtrTy) { + Type *IndexTy = (*I)->getType(); + if (IndexTy != IntPtrTy && !IndexTy->isVectorTy()) { // If we are using a wider index than needed for this platform, shrink // it to what we need. If narrower, sign-extend it to what we need. // This explicit cast can make subsequent optimizations more obvious. @@ -914,7 +915,11 @@ // Handle gep(bitcast x) and gep(gep x, 0, 0, 0). Value *StrippedPtr = PtrOp->stripPointerCasts(); - PointerType *StrippedPtrTy =cast(StrippedPtr->getType()); + PointerType *StrippedPtrTy = dyn_cast(StrippedPtr->getType()); + // We do not handle pointer-vector geps here + if (!StrippedPtr) + return 0; + if (StrippedPtr != PtrOp && StrippedPtrTy->getAddressSpace() == GEP.getPointerAddressSpace()) { Modified: llvm/trunk/lib/Transforms/Scalar/IndVarSimplify.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/IndVarSimplify.cpp?rev=145801&r1=145800&r2=145801&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Scalar/IndVarSimplify.cpp (original) +++ llvm/trunk/lib/Transforms/Scalar/IndVarSimplify.cpp Mon Dec 5 00:29:09 2011 @@ -178,6 +178,11 @@ // base of a recurrence. This handles the case in which SCEV expansion // converts a pointer type recurrence into a nonrecurrent pointer base // indexed by an integer recurrence. + + // If the GEP base pointer is a vector of pointers, abort. + if (!FromPtr->getType()->isPointerTy() || !ToPtr->getType()->isPointerTy()) + return false; + const SCEV *FromBase = SE->getPointerBase(SE->getSCEV(FromPtr)); const SCEV *ToBase = SE->getPointerBase(SE->getSCEV(ToPtr)); if (FromBase == ToBase) Modified: llvm/trunk/lib/Transforms/Scalar/ScalarReplAggregates.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/ScalarReplAggregates.cpp?rev=145801&r1=145800&r2=145801&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Scalar/ScalarReplAggregates.cpp (original) +++ llvm/trunk/lib/Transforms/Scalar/ScalarReplAggregates.cpp Mon Dec 5 00:29:09 2011 @@ -453,6 +453,8 @@ // Compute the offset that this GEP adds to the pointer. SmallVector Indices(GEP->op_begin()+1, GEP->op_end()); + if (!GEP->getPointerOperandType()->isPointerTy()) + return false; uint64_t GEPOffset = TD.getIndexedOffset(GEP->getPointerOperandType(), Indices); // See if all uses can be converted. Modified: llvm/trunk/lib/VMCore/Constants.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/Constants.cpp?rev=145801&r1=145800&r2=145801&view=diff ============================================================================== --- llvm/trunk/lib/VMCore/Constants.cpp (original) +++ llvm/trunk/lib/VMCore/Constants.cpp Mon Dec 5 00:29:09 2011 @@ -1398,14 +1398,22 @@ } Constant *ConstantExpr::getPtrToInt(Constant *C, Type *DstTy) { - assert(C->getType()->isPointerTy() && "PtrToInt source must be pointer"); - assert(DstTy->isIntegerTy() && "PtrToInt destination must be integral"); + assert(C->getType()->getScalarType()->isPointerTy() && + "PtrToInt source must be pointer or pointer vector"); + assert(DstTy->getScalarType()->isIntegerTy() && + "PtrToInt destination must be integer or integer vector"); + assert(C->getType()->getNumElements() == DstTy->getNumElements() && + "Invalid cast between a different number of vector elements"); return getFoldedCast(Instruction::PtrToInt, C, DstTy); } Constant *ConstantExpr::getIntToPtr(Constant *C, Type *DstTy) { - assert(C->getType()->isIntegerTy() && "IntToPtr source must be integral"); - assert(DstTy->isPointerTy() && "IntToPtr destination must be a pointer"); + assert(C->getType()->getScalarType()->isIntegerTy() && + "IntToPtr source must be integer or integer vector"); + assert(DstTy->getScalarType()->isPointerTy() && + "IntToPtr destination must be a pointer or pointer vector"); + assert(C->getType()->getNumElements() == DstTy->getNumElements() && + "Invalid cast between a different number of vector elements"); return getFoldedCast(Instruction::IntToPtr, C, DstTy); } Modified: llvm/trunk/lib/VMCore/Instructions.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/Instructions.cpp?rev=145801&r1=145800&r2=145801&view=diff ============================================================================== --- llvm/trunk/lib/VMCore/Instructions.cpp (original) +++ llvm/trunk/lib/VMCore/Instructions.cpp Mon Dec 5 00:29:09 2011 @@ -1359,6 +1359,15 @@ /// template static Type *getIndexedTypeInternal(Type *Ptr, ArrayRef IdxList) { + if (Ptr->isVectorTy()) { + assert(IdxList.size() == 1 && + "GEP with vector pointers must have a single index"); + PointerType *PTy = dyn_cast( + cast(Ptr)->getElementType()); + assert(PTy && "Gep with invalid vector pointer found"); + return PTy->getElementType(); + } + PointerType *PTy = dyn_cast(Ptr); if (!PTy) return 0; // Type isn't a pointer type! Type *Agg = PTy->getElementType(); @@ -1366,7 +1375,7 @@ // Handle the special case of the empty set index set, which is always valid. if (IdxList.empty()) return Agg; - + // If there is at least one index, the top level type must be sized, otherwise // it cannot be 'stepped over'. if (!Agg->isSized()) @@ -1396,6 +1405,19 @@ return getIndexedTypeInternal(Ptr, IdxList); } +unsigned GetElementPtrInst::getAddressSpace(Value *Ptr) { + Type *Ty = Ptr->getType(); + + if (VectorType *VTy = dyn_cast(Ty)) + Ty = VTy->getElementType(); + + if (PointerType *PTy = dyn_cast(Ty)) + return PTy->getAddressSpace(); + + assert(false && "Invalid GEP pointer type"); + return 0; +} + /// hasAllZeroIndices - Return true if all of the indices of this GEP are /// zeros. If so, the result pointer and the first operand have the same /// value, just potentially different types. @@ -2654,9 +2676,15 @@ return SrcTy->isFPOrFPVectorTy() && DstTy->isIntOrIntVectorTy() && SrcLength == DstLength; case Instruction::PtrToInt: - return SrcTy->isPointerTy() && DstTy->isIntegerTy(); + if (SrcTy->getNumElements() != DstTy->getNumElements()) + return false; + return SrcTy->getScalarType()->isPointerTy() && + DstTy->getScalarType()->isIntegerTy(); case Instruction::IntToPtr: - return SrcTy->isIntegerTy() && DstTy->isPointerTy(); + if (SrcTy->getNumElements() != DstTy->getNumElements()) + return false; + return SrcTy->getScalarType()->isIntegerTy() && + DstTy->getScalarType()->isPointerTy(); case Instruction::BitCast: // BitCast implies a no-op cast of type only. No bits change. // However, you can't cast pointers to anything but pointers. Modified: llvm/trunk/lib/VMCore/Type.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/Type.cpp?rev=145801&r1=145800&r2=145801&view=diff ============================================================================== --- llvm/trunk/lib/VMCore/Type.cpp (original) +++ llvm/trunk/lib/VMCore/Type.cpp Mon Dec 5 00:29:09 2011 @@ -46,6 +46,14 @@ return this; } +/// getNumElements - If this is a vector type, return the number of elements, +/// otherwise return zero. +unsigned Type::getNumElements() { + if (VectorType *VTy = dyn_cast(this)) + return VTy->getNumElements(); + return 0; +} + /// isIntegerTy - Return true if this is an IntegerType of the specified width. bool Type::isIntegerTy(unsigned Bitwidth) const { return isIntegerTy() && cast(this)->getBitWidth() == Bitwidth; @@ -664,6 +672,8 @@ } bool VectorType::isValidElementType(Type *ElemTy) { + if (PointerType *PTy = dyn_cast(ElemTy)) + ElemTy = PTy->getElementType(); return ElemTy->isIntegerTy() || ElemTy->isFloatingPointTy(); } Modified: llvm/trunk/lib/VMCore/Verifier.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/Verifier.cpp?rev=145801&r1=145800&r2=145801&view=diff ============================================================================== --- llvm/trunk/lib/VMCore/Verifier.cpp (original) +++ llvm/trunk/lib/VMCore/Verifier.cpp Mon Dec 5 00:29:09 2011 @@ -1035,8 +1035,19 @@ Type *SrcTy = I.getOperand(0)->getType(); Type *DestTy = I.getType(); - Assert1(SrcTy->isPointerTy(), "PtrToInt source must be pointer", &I); - Assert1(DestTy->isIntegerTy(), "PtrToInt result must be integral", &I); + Assert1(SrcTy->getScalarType()->isPointerTy(), + "PtrToInt source must be pointer", &I); + Assert1(DestTy->getScalarType()->isIntegerTy(), + "PtrToInt result must be integral", &I); + Assert1(SrcTy->isVectorTy() == DestTy->isVectorTy(), + "PtrToInt type mismatch", &I); + + if (SrcTy->isVectorTy()) { + VectorType *VSrc = dyn_cast(SrcTy); + VectorType *VDest = dyn_cast(DestTy); + Assert1(VSrc->getNumElements() == VDest->getNumElements(), + "PtrToInt Vector width mismatch", &I); + } visitInstruction(I); } @@ -1046,9 +1057,18 @@ Type *SrcTy = I.getOperand(0)->getType(); Type *DestTy = I.getType(); - Assert1(SrcTy->isIntegerTy(), "IntToPtr source must be an integral", &I); - Assert1(DestTy->isPointerTy(), "IntToPtr result must be a pointer",&I); - + Assert1(SrcTy->getScalarType()->isIntegerTy(), + "IntToPtr source must be an integral", &I); + Assert1(DestTy->getScalarType()->isPointerTy(), + "IntToPtr result must be a pointer",&I); + Assert1(SrcTy->isVectorTy() == DestTy->isVectorTy(), + "IntToPtr type mismatch", &I); + if (SrcTy->isVectorTy()) { + VectorType *VSrc = dyn_cast(SrcTy); + VectorType *VDest = dyn_cast(DestTy); + Assert1(VSrc->getNumElements() == VDest->getNumElements(), + "IntToPtr Vector width mismatch", &I); + } visitInstruction(I); } @@ -1245,7 +1265,7 @@ Assert1(Op0Ty == Op1Ty, "Both operands to ICmp instruction are not of the same type!", &IC); // Check that the operands are the right type - Assert1(Op0Ty->isIntOrIntVectorTy() || Op0Ty->isPointerTy(), + Assert1(Op0Ty->isIntOrIntVectorTy() || Op0Ty->getScalarType()->isPointerTy(), "Invalid operand types for ICmp instruction", &IC); // Check that the predicate is valid. Assert1(IC.getPredicate() >= CmpInst::FIRST_ICMP_PREDICATE && @@ -1295,17 +1315,43 @@ } void Verifier::visitGetElementPtrInst(GetElementPtrInst &GEP) { - Assert1(cast(GEP.getOperand(0)->getType()) - ->getElementType()->isSized(), + Type *TargetTy = GEP.getPointerOperandType(); + if (VectorType *VTy = dyn_cast(TargetTy)) + TargetTy = VTy->getElementType(); + + Assert1(dyn_cast(TargetTy), + "GEP base pointer is not a vector or a vector of pointers", &GEP); + Assert1(cast(TargetTy)->getElementType()->isSized(), "GEP into unsized type!", &GEP); - + SmallVector Idxs(GEP.idx_begin(), GEP.idx_end()); Type *ElTy = - GetElementPtrInst::getIndexedType(GEP.getOperand(0)->getType(), Idxs); + GetElementPtrInst::getIndexedType(GEP.getPointerOperandType(), Idxs); Assert1(ElTy, "Invalid indices for GEP pointer type!", &GEP); - Assert2(GEP.getType()->isPointerTy() && - cast(GEP.getType())->getElementType() == ElTy, - "GEP is not of right type for indices!", &GEP, ElTy); + + if (GEP.getPointerOperandType()->isPointerTy()) { + // Validate GEPs with scalar indices. + Assert2(GEP.getType()->isPointerTy() && + cast(GEP.getType())->getElementType() == ElTy, + "GEP is not of right type for indices!", &GEP, ElTy); + } else { + // Validate GEPs with a vector index. + Assert1(Idxs.size() == 1, "Invalid number of indices!", &GEP); + Value *Index = Idxs[0]; + Type *IndexTy = Index->getType(); + Assert1(IndexTy->isVectorTy(), + "Vector GEP must have vector indices!", &GEP); + Assert1(GEP.getType()->isVectorTy(), + "Vector GEP must return a vector value", &GEP); + Type *ElemPtr = cast(GEP.getType())->getElementType(); + Assert1(ElemPtr->isPointerTy(), + "Vector GEP pointer operand is not a pointer!", &GEP); + unsigned IndexWidth = cast(IndexTy)->getNumElements(); + unsigned GepWidth = cast(GEP.getType())->getNumElements(); + Assert1(IndexWidth == GepWidth, "Invalid GEP index vector width", &GEP); + Assert1(ElTy == cast(ElemPtr)->getElementType(), + "Vector GEP type does not match pointer type!", &GEP); + } visitInstruction(GEP); } Added: llvm/trunk/test/CodeGen/X86/pointer-vector.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/pointer-vector.ll?rev=145801&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/X86/pointer-vector.ll (added) +++ llvm/trunk/test/CodeGen/X86/pointer-vector.ll Mon Dec 5 00:29:09 2011 @@ -0,0 +1,138 @@ +; RUN: llc < %s -march=x86 -mcpu=corei7 | FileCheck %s +; RUN: opt -instsimplify %s -disable-output + +;CHECK: SHUFF0 +define <8 x i32*> @SHUFF0(<4 x i32*> %ptrv) nounwind { +entry: + %G = shufflevector <4 x i32*> %ptrv, <4 x i32*> %ptrv, <8 x i32> +;CHECK: pshufd + ret <8 x i32*> %G +;CHECK: ret +} + +;CHECK: SHUFF1 +define <4 x i32*> @SHUFF1(<4 x i32*> %ptrv) nounwind { +entry: + %G = shufflevector <4 x i32*> %ptrv, <4 x i32*> %ptrv, <4 x i32> +;CHECK: pshufd + ret <4 x i32*> %G +;CHECK: ret +} + +;CHECK: SHUFF3 +define <4 x i8*> @SHUFF3(<4 x i8*> %ptrv) nounwind { +entry: + %G = shufflevector <4 x i8*> %ptrv, <4 x i8*> undef, <4 x i32> +;CHECK: pshufd + ret <4 x i8*> %G +;CHECK: ret +} + +;CHECK: LOAD0 +define <4 x i8*> @LOAD0(<4 x i8*>* %p) nounwind { +entry: + %G = load <4 x i8*>* %p +;CHECK: movaps + ret <4 x i8*> %G +;CHECK: ret +} + +;CHECK: LOAD1 +define <4 x i8*> @LOAD1(<4 x i8*>* %p) nounwind { +entry: + %G = load <4 x i8*>* %p +;CHECK: movdqa +;CHECK: pshufd +;CHECK: movdqa + %T = shufflevector <4 x i8*> %G, <4 x i8*> %G, <4 x i32> + store <4 x i8*> %T, <4 x i8*>* %p + ret <4 x i8*> %G +;CHECK: ret +} + +;CHECK: LOAD2 +define <4 x i8*> @LOAD2(<4 x i8*>* %p) nounwind { +entry: + %I = alloca <4 x i8*> +;CHECK: sub + %G = load <4 x i8*>* %p +;CHECK: movaps + store <4 x i8*> %G, <4 x i8*>* %I +;CHECK: movaps + %Z = load <4 x i8*>* %I + ret <4 x i8*> %Z +;CHECK: add +;CHECK: ret +} + +;CHECK: INT2PTR0 +define <4 x i32> @INT2PTR0(<4 x i8*>* %p) nounwind { +entry: + %G = load <4 x i8*>* %p +;CHECK: movl +;CHECK: movaps + %K = ptrtoint <4 x i8*> %G to <4 x i32> +;CHECK: ret + ret <4 x i32> %K +} + +;CHECK: INT2PTR1 +define <4 x i32*> @INT2PTR1(<4 x i8>* %p) nounwind { +entry: + %G = load <4 x i8>* %p +;CHECK: movl +;CHECK: movd +;CHECK: pshufb +;CHECK: pand + %K = inttoptr <4 x i8> %G to <4 x i32*> +;CHECK: ret + ret <4 x i32*> %K +} + +;CHECK: BITCAST0 +define <4 x i32*> @BITCAST0(<4 x i8*>* %p) nounwind { +entry: + %G = load <4 x i8*>* %p +;CHECK: movl + %T = bitcast <4 x i8*> %G to <4 x i32*> +;CHECK: movaps +;CHECK: ret + ret <4 x i32*> %T +} + +;CHECK: BITCAST1 +define <2 x i32*> @BITCAST1(<2 x i8*>* %p) nounwind { +entry: + %G = load <2 x i8*>* %p +;CHECK: movl +;CHECK: movd +;CHECK: pinsrd + %T = bitcast <2 x i8*> %G to <2 x i32*> +;CHECK: ret + ret <2 x i32*> %T +} + +;CHECK: ICMP0 +define <4 x i32> @ICMP0(<4 x i8*>* %p0, <4 x i8*>* %p1) nounwind { +entry: + %g0 = load <4 x i8*>* %p0 + %g1 = load <4 x i8*>* %p1 + %k = icmp sgt <4 x i8*> %g0, %g1 + ;CHECK: pcmpgtd + %j = select <4 x i1> %k, <4 x i32> , <4 x i32> + ret <4 x i32> %j + ;CHECK: ret +} + +;CHECK: ICMP1 +define <4 x i32> @ICMP1(<4 x i8*>* %p0, <4 x i8*>* %p1) nounwind { +entry: + %g0 = load <4 x i8*>* %p0 + %g1 = load <4 x i8*>* %p1 + %k = icmp eq <4 x i8*> %g0, %g1 + ;CHECK: pcmpeqd + %j = select <4 x i1> %k, <4 x i32> , <4 x i32> + ret <4 x i32> %j + ;CHECK: ret +} + Added: llvm/trunk/test/CodeGen/X86/vector-gep.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/vector-gep.ll?rev=145801&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/X86/vector-gep.ll (added) +++ llvm/trunk/test/CodeGen/X86/vector-gep.ll Mon Dec 5 00:29:09 2011 @@ -0,0 +1,77 @@ +; RUN: llc < %s -march=x86 -mcpu=corei7-avx | FileCheck %s +; RUN: opt -instsimplify %s -disable-output + +;CHECK: AGEP0 +define <4 x i32*> @AGEP0(i32* %ptr) nounwind { +entry: + %vecinit.i = insertelement <4 x i32*> undef, i32* %ptr, i32 0 + %vecinit2.i = insertelement <4 x i32*> %vecinit.i, i32* %ptr, i32 1 + %vecinit4.i = insertelement <4 x i32*> %vecinit2.i, i32* %ptr, i32 2 + %vecinit6.i = insertelement <4 x i32*> %vecinit4.i, i32* %ptr, i32 3 +;CHECK: pslld +;CHECK: padd + %A2 = getelementptr <4 x i32*> %vecinit6.i, <4 x i32> +;CHECK: pslld +;CHECK: padd + %A3 = getelementptr <4 x i32*> %A2, <4 x i32> + ret <4 x i32*> %A3 +;CHECK: ret +} + +;CHECK: AGEP1 +define i32 @AGEP1(<4 x i32*> %param) nounwind { +entry: +;CHECK: pslld +;CHECK: padd + %A2 = getelementptr <4 x i32*> %param, <4 x i32> + %k = extractelement <4 x i32*> %A2, i32 3 + %v = load i32* %k + ret i32 %v +;CHECK: ret +} + +;CHECK: AGEP2 +define i32 @AGEP2(<4 x i32*> %param, <4 x i32> %off) nounwind { +entry: +;CHECK: pslld +;CHECK: padd + %A2 = getelementptr <4 x i32*> %param, <4 x i32> %off + %k = extractelement <4 x i32*> %A2, i32 3 + %v = load i32* %k + ret i32 %v +;CHECK: ret +} + +;CHECK: AGEP3 +define <4 x i32*> @AGEP3(<4 x i32*> %param, <4 x i32> %off) nounwind { +entry: +;CHECK: pslld +;CHECK: padd + %A2 = getelementptr <4 x i32*> %param, <4 x i32> %off + %v = alloca i32 + %k = insertelement <4 x i32*> %A2, i32* %v, i32 3 + ret <4 x i32*> %k +;CHECK: ret +} + +;CHECK: AGEP4 +define <4 x i8*> @AGEP4(<4 x i8*> %param, <4 x i32> %off) nounwind { +entry: +;CHECK: pslld +;CHECK: padd + %A = getelementptr <4 x i8*> %param, <4 x i32> %off + ret <4 x i8*> %A +;CHECK: ret +} + +;CHECK: AGEP5 +define <4 x i8*> @AGEP5(<4 x i8*> %param, <4 x i8> %off) nounwind { +entry: +;CHECK: pslld +;CHECK: padd + %A = getelementptr <4 x i8*> %param, <4 x i8> %off + ret <4 x i8*> %A +;CHECK: ret +} + + Added: llvm/trunk/test/Feature/const_pv.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Feature/const_pv.ll?rev=145801&view=auto ============================================================================== --- llvm/trunk/test/Feature/const_pv.ll (added) +++ llvm/trunk/test/Feature/const_pv.ll Mon Dec 5 00:29:09 2011 @@ -0,0 +1,8 @@ +; RUN: llvm-as %s -disable-output + at G = constant <3 x i64> ptrtoint (<3 x i8*> to <3 x i64>) + + at G1 = global i8 zeroinitializer + at g = constant <2 x i8*> getelementptr (<2 x i8*> , <2 x i32> ) + + at t = constant <2 x i1> icmp ((<2 x i32> ptrtoint (<2 x i8*> zeroinitializer to <2 x i32>), <2 x i32> zeroinitializer ) + Added: llvm/trunk/test/Feature/global_pv.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Feature/global_pv.ll?rev=145801&view=auto ============================================================================== --- llvm/trunk/test/Feature/global_pv.ll (added) +++ llvm/trunk/test/Feature/global_pv.ll Mon Dec 5 00:29:09 2011 @@ -0,0 +1,14 @@ +; RUN: opt -instcombine -S -o - %s | llvm-as +; RUN: opt -instcombine -globalopt -S -o - %s | llvm-as + at G1 = global i32 zeroinitializer + at G2 = global i32 zeroinitializer + at g = global <2 x i32*> zeroinitializer +%0 = type { i32, void ()* } + at llvm.global_ctors = appending global [1 x %0] [%0 { i32 65535, void ()* @test }] +define internal void @test() { + %A = insertelement <2 x i32*> undef, i32* @G1, i32 0 + %B = insertelement <2 x i32*> %A, i32* @G2, i32 1 + store <2 x i32*> %B, <2 x i32*>* @g + ret void +} + Added: llvm/trunk/test/Transforms/InstCombine/vector_gep1.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstCombine/vector_gep1.ll?rev=145801&view=auto ============================================================================== --- llvm/trunk/test/Transforms/InstCombine/vector_gep1.ll (added) +++ llvm/trunk/test/Transforms/InstCombine/vector_gep1.ll Mon Dec 5 00:29:09 2011 @@ -0,0 +1,37 @@ +; RUN: opt -instcombine %s -disable-output +; RUN: opt -instsimplify %s -disable-output +target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128" +target triple = "x86_64-unknown-linux-gnu" + + at G1 = global i8 zeroinitializer + +define <2 x i1> @test(<2 x i8*> %a, <2 x i8*> %b) { + %A = icmp eq <2 x i8*> %a, %b + ret <2 x i1> %A +} + +define <2 x i1> @test2(<2 x i8*> %a) { + %A = inttoptr <2 x i32> to <2 x i8*> + %B = icmp ult <2 x i8*> %A, zeroinitializer + ret <2 x i1> %B +} + +define <2 x i1> @test3(<2 x i8*> %a) { + %g = getelementptr <2 x i8*> %a, <2 x i32> + %B = icmp ult <2 x i8*> %g, zeroinitializer + ret <2 x i1> %B +} + +define <1 x i1> @test4(<1 x i8*> %a) { + %g = getelementptr <1 x i8*> %a, <1 x i32> + %B = icmp ult <1 x i8*> %g, zeroinitializer + ret <1 x i1> %B +} + +define <2 x i1> @test5(<2 x i8*> %a) { + %w = getelementptr <2 x i8*> %a, <2 x i32> zeroinitializer + %e = getelementptr <2 x i8*> %w, <2 x i32> + %g = getelementptr <2 x i8*> %e, <2 x i32> + %B = icmp ult <2 x i8*> %g, zeroinitializer + ret <2 x i1> %B +} Added: llvm/trunk/test/Transforms/InstSimplify/vector_gep.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstSimplify/vector_gep.ll?rev=145801&view=auto ============================================================================== --- llvm/trunk/test/Transforms/InstSimplify/vector_gep.ll (added) +++ llvm/trunk/test/Transforms/InstSimplify/vector_gep.ll Mon Dec 5 00:29:09 2011 @@ -0,0 +1,8 @@ +;RUN: opt -instsimplify %s -disable-output +declare void @helper(<2 x i8*>) +define void @test(<2 x i8*> %a) { + %A = getelementptr <2 x i8*> %a, <2 x i32> + call void @helper(<2 x i8*> %A) + ret void +} + Modified: llvm/trunk/unittests/VMCore/InstructionsTest.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/unittests/VMCore/InstructionsTest.cpp?rev=145801&r1=145800&r2=145801&view=diff ============================================================================== --- llvm/trunk/unittests/VMCore/InstructionsTest.cpp (original) +++ llvm/trunk/unittests/VMCore/InstructionsTest.cpp Mon Dec 5 00:29:09 2011 @@ -13,6 +13,8 @@ #include "llvm/DerivedTypes.h" #include "llvm/LLVMContext.h" #include "llvm/ADT/STLExtras.h" +#include "llvm/Analysis/ValueTracking.h" +#include "llvm/Target/TargetData.h" #include "gtest/gtest.h" namespace llvm { @@ -129,5 +131,100 @@ EXPECT_EQ(CastInst::SExt, CastInst::getCastOpcode(c8, true, V8x64Ty, true)); } + + +TEST(InstructionsTest, VectorGep) { + LLVMContext &C(getGlobalContext()); + + // Type Definitions + PointerType *Ptri8Ty = PointerType::get(IntegerType::get(C, 8), 0); + PointerType *Ptri32Ty = PointerType::get(IntegerType::get(C, 8), 0); + + VectorType *V2xi8PTy = VectorType::get(Ptri8Ty, 2); + VectorType *V2xi32PTy = VectorType::get(Ptri32Ty, 2); + + // Test different aspects of the vector-of-pointers type + // and GEPs which use this type. + ConstantInt *Ci32a = ConstantInt::get(C, APInt(32, 1492)); + ConstantInt *Ci32b = ConstantInt::get(C, APInt(32, 1948)); + std::vector ConstVa(2, Ci32a); + std::vector ConstVb(2, Ci32b); + Constant *C2xi32a = ConstantVector::get(ConstVa); + Constant *C2xi32b = ConstantVector::get(ConstVb); + + CastInst *PtrVecA = new IntToPtrInst(C2xi32a, V2xi32PTy); + CastInst *PtrVecB = new IntToPtrInst(C2xi32b, V2xi32PTy); + + ICmpInst *ICmp0 = new ICmpInst(ICmpInst::ICMP_SGT, PtrVecA, PtrVecB); + ICmpInst *ICmp1 = new ICmpInst(ICmpInst::ICMP_ULT, PtrVecA, PtrVecB); + EXPECT_NE(ICmp0, ICmp1); // suppress warning. + + GetElementPtrInst *Gep0 = GetElementPtrInst::Create(PtrVecA, C2xi32a); + GetElementPtrInst *Gep1 = GetElementPtrInst::Create(PtrVecA, C2xi32b); + GetElementPtrInst *Gep2 = GetElementPtrInst::Create(PtrVecB, C2xi32a); + GetElementPtrInst *Gep3 = GetElementPtrInst::Create(PtrVecB, C2xi32b); + + CastInst *BTC0 = new BitCastInst(Gep0, V2xi8PTy); + CastInst *BTC1 = new BitCastInst(Gep1, V2xi8PTy); + CastInst *BTC2 = new BitCastInst(Gep2, V2xi8PTy); + CastInst *BTC3 = new BitCastInst(Gep3, V2xi8PTy); + + Value *S0 = BTC0->stripPointerCasts(); + Value *S1 = BTC1->stripPointerCasts(); + Value *S2 = BTC2->stripPointerCasts(); + Value *S3 = BTC3->stripPointerCasts(); + + EXPECT_NE(S0, Gep0); + EXPECT_NE(S1, Gep1); + EXPECT_NE(S2, Gep2); + EXPECT_NE(S3, Gep3); + + int64_t Offset; + TargetData TD("e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f3" + "2:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80" + ":128:128-n8:16:32:64-S128"); + // Make sure we don't crash + GetPointerBaseWithConstantOffset(Gep0, Offset, TD); + GetPointerBaseWithConstantOffset(Gep1, Offset, TD); + GetPointerBaseWithConstantOffset(Gep2, Offset, TD); + GetPointerBaseWithConstantOffset(Gep3, Offset, TD); + + // Gep of Geps + GetElementPtrInst *GepII0 = GetElementPtrInst::Create(Gep0, C2xi32b); + GetElementPtrInst *GepII1 = GetElementPtrInst::Create(Gep1, C2xi32a); + GetElementPtrInst *GepII2 = GetElementPtrInst::Create(Gep2, C2xi32b); + GetElementPtrInst *GepII3 = GetElementPtrInst::Create(Gep3, C2xi32a); + + EXPECT_EQ(GepII0->getNumIndices(), 1u); + EXPECT_EQ(GepII1->getNumIndices(), 1u); + EXPECT_EQ(GepII2->getNumIndices(), 1u); + EXPECT_EQ(GepII3->getNumIndices(), 1u); + + EXPECT_FALSE(GepII0->hasAllZeroIndices()); + EXPECT_FALSE(GepII1->hasAllZeroIndices()); + EXPECT_FALSE(GepII2->hasAllZeroIndices()); + EXPECT_FALSE(GepII3->hasAllZeroIndices()); + + delete GepII0; + delete GepII1; + delete GepII2; + delete GepII3; + + delete BTC0; + delete BTC1; + delete BTC2; + delete BTC3; + + delete Gep0; + delete Gep1; + delete Gep2; + delete Gep3; + + delete ICmp0; + delete ICmp1; + delete PtrVecA; + delete PtrVecB; +} + } // end anonymous namespace } // end namespace llvm From craig.topper at gmail.com Mon Dec 5 00:56:46 2011 From: craig.topper at gmail.com (Craig Topper) Date: Mon, 05 Dec 2011 06:56:46 -0000 Subject: [llvm-commits] [llvm] r145803 - /llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Message-ID: <20111205065646.B71721BE003@llvm.org> Author: ctopper Date: Mon Dec 5 00:56:46 2011 New Revision: 145803 URL: http://llvm.org/viewvc/llvm-project?rev=145803&view=rev Log: Clean up and optimizations to the X86 shuffle lowering code. No functional change. Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=145803&r1=145802&r2=145803&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original) +++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Mon Dec 5 00:56:46 2011 @@ -3323,11 +3323,9 @@ /// the reverse of what x86 shuffles want. x86 shuffles requires the lower /// half elements to come from vector 1 (which would equal the dest.) and /// the upper half to come from vector 2. -static bool isCommutedVSHUFPY(ShuffleVectorSDNode *N, bool HasAVX) { - EVT VT = N->getValueType(0); +static bool isCommutedVSHUFPYMask(const SmallVectorImpl &Mask, EVT VT, + bool HasAVX) { int NumElems = VT.getVectorNumElements(); - SmallVector Mask; - N->getMask(Mask); if (!HasAVX || VT.getSizeInBits() != 256) return false; @@ -3423,8 +3421,8 @@ /// CommuteVectorShuffleMask - Change values in a shuffle permute mask assuming /// the two vector operands have swapped position. -static void CommuteVectorShuffleMask(SmallVectorImpl &Mask, EVT VT) { - unsigned NumElems = VT.getVectorNumElements(); +static void CommuteVectorShuffleMask(SmallVectorImpl &Mask, + unsigned NumElems) { for (unsigned i = 0; i != NumElems; ++i) { int idx = Mask[i]; if (idx < 0) @@ -3485,12 +3483,6 @@ return true; } -static bool isCommutedSHUFP(ShuffleVectorSDNode *N) { - SmallVector M; - N->getMask(M); - return isCommutedSHUFPMask(M, N->getValueType(0)); -} - /// isMOVHLPSMask - Return true if the specified VECTOR_SHUFFLE operand /// specifies a shuffle of elements that is suitable for input to MOVHLPS. bool X86::isMOVHLPSMask(ShuffleVectorSDNode *N) { @@ -3975,21 +3967,18 @@ /// isMOVDDUPYMask - Return true if the specified VECTOR_SHUFFLE operand /// specifies a shuffle of elements that is suitable for input to 256-bit /// version of MOVDDUP. -static bool isMOVDDUPYMask(ShuffleVectorSDNode *N, - const X86Subtarget *Subtarget) { - EVT VT = N->getValueType(0); +static bool isMOVDDUPYMask(const SmallVectorImpl &Mask, EVT VT, + bool HasAVX) { int NumElts = VT.getVectorNumElements(); - bool V2IsUndef = N->getOperand(1).getOpcode() == ISD::UNDEF; - if (!Subtarget->hasAVX() || VT.getSizeInBits() != 256 || - !V2IsUndef || NumElts != 4) + if (!HasAVX || VT.getSizeInBits() != 256 || NumElts != 4) return false; for (int i = 0; i != NumElts/2; ++i) - if (!isUndefOrEqual(N->getMaskElt(i), 0)) + if (!isUndefOrEqual(Mask[i], 0)) return false; for (int i = NumElts/2; i != NumElts; ++i) - if (!isUndefOrEqual(N->getMaskElt(i), NumElts/2)) + if (!isUndefOrEqual(Mask[i], NumElts/2)) return false; return true; } @@ -6172,7 +6161,7 @@ // from X. if (NumHi == 3) { // Normalize it so the 3 elements come from V1. - CommuteVectorShuffleMask(PermMask, VT); + CommuteVectorShuffleMask(PermMask, 4); std::swap(V1, V2); } @@ -6603,6 +6592,7 @@ bool V1IsSplat = false; bool V2IsSplat = false; bool HasXMMInt = Subtarget->hasXMMInt(); + bool HasAVX = Subtarget->hasAVX(); bool HasAVX2 = Subtarget->hasAVX2(); MachineFunction &MF = DAG.getMachineFunction(); bool OptForSize = MF.getFunction()->hasFnAttr(Attribute::OptimizeForSize); @@ -6738,7 +6728,10 @@ Commuted = true; } - if (isCommutedMOVL(SVOp, V2IsSplat, V2IsUndef)) { + SmallVector M; + SVOp->getMask(M); + + if (isCommutedMOVLMask(M, VT, V2IsSplat, V2IsUndef)) { // Shuffling low element of v1 into undef, just return v1. if (V2IsUndef) return V1; @@ -6748,11 +6741,11 @@ return getMOVL(DAG, dl, VT, V2, V1); } - if (X86::isUNPCKLMask(SVOp, HasAVX2)) + if (isUNPCKLMask(M, VT, HasAVX2)) return getTargetShuffleNode(getUNPCKLOpcode(VT, HasAVX2), dl, VT, V1, V2, DAG); - if (X86::isUNPCKHMask(SVOp, HasAVX2)) + if (isUNPCKHMask(M, VT, HasAVX2)) return getTargetShuffleNode(getUNPCKHOpcode(VT, HasAVX2), dl, VT, V1, V2, DAG); @@ -6787,15 +6780,13 @@ } // Normalize the node to match x86 shuffle ops if needed - if (!V2IsUndef && (isCommutedSHUFP(SVOp) || - isCommutedVSHUFPY(SVOp, Subtarget->hasAVX()))) + if (!V2IsUndef && (isCommutedSHUFPMask(M, VT) || + isCommutedVSHUFPYMask(M, VT, HasAVX))) return CommuteVectorShuffle(SVOp, DAG); // The checks below are all present in isShuffleMaskLegal, but they are // inlined here right now to enable us to directly emit target specific // nodes, and remove one by one until they don't return Op anymore. - SmallVector M; - SVOp->getMask(M); if (isPALIGNRMask(M, VT, Subtarget->hasSSSE3orAVX())) return getTargetShuffleNode(X86ISD::PALIGN, dl, VT, V1, V2, @@ -6804,10 +6795,9 @@ if (ShuffleVectorSDNode::isSplatMask(&M[0], VT) && SVOp->getSplatIndex() == 0 && V2IsUndef) { - if (VT == MVT::v2f64) - return getTargetShuffleNode(X86ISD::UNPCKLP, dl, VT, V1, V1, DAG); - if (VT == MVT::v2i64) - return getTargetShuffleNode(X86ISD::PUNPCKL, dl, VT, V1, V1, DAG); + if (VT == MVT::v2f64 || VT == MVT::v2i64) + return getTargetShuffleNode(getUNPCKLOpcode(VT, HasAVX2), dl, VT, V1, V1, + DAG); } if (isPSHUFHWMask(M, VT)) @@ -6824,10 +6814,10 @@ return getTargetShuffleNode(getSHUFPOpcode(VT), dl, VT, V1, V2, X86::getShuffleSHUFImmediate(SVOp), DAG); - if (X86::isUNPCKL_v_undef_Mask(SVOp)) + if (isUNPCKL_v_undef_Mask(M, VT)) return getTargetShuffleNode(getUNPCKLOpcode(VT, HasAVX2), dl, VT, V1, V1, DAG); - if (X86::isUNPCKH_v_undef_Mask(SVOp)) + if (isUNPCKH_v_undef_Mask(M, VT)) return getTargetShuffleNode(getUNPCKHOpcode(VT, HasAVX2), dl, VT, V1, V1, DAG); @@ -6837,21 +6827,21 @@ // // Handle VMOVDDUPY permutations - if (isMOVDDUPYMask(SVOp, Subtarget)) + if (V2IsUndef && isMOVDDUPYMask(M, VT, HasAVX)) return getTargetShuffleNode(X86ISD::MOVDDUP, dl, VT, V1, DAG); // Handle VPERMILPS/D* permutations - if (isVPERMILPMask(M, VT, Subtarget->hasAVX())) + if (isVPERMILPMask(M, VT, HasAVX)) return getTargetShuffleNode(X86ISD::VPERMILP, dl, VT, V1, getShuffleVPERMILPImmediate(SVOp), DAG); // Handle VPERM2F128/VPERM2I128 permutations - if (isVPERM2X128Mask(M, VT, Subtarget->hasAVX())) + if (isVPERM2X128Mask(M, VT, HasAVX)) return getTargetShuffleNode(X86ISD::VPERM2X128, dl, VT, V1, V2, getShuffleVPERM2X128Immediate(SVOp), DAG); // Handle VSHUFPS/DY permutations - if (isVSHUFPYMask(M, VT, Subtarget->hasAVX())) + if (isVSHUFPYMask(M, VT, HasAVX)) return getTargetShuffleNode(getSHUFPOpcode(VT), dl, VT, V1, V2, getShuffleVSHUFPYImmediate(SVOp), DAG); @@ -14321,7 +14311,7 @@ /// set to A, RHS to B, and the routine returns 'true'. /// Note that the binary operation should have the property that if one of the /// operands is UNDEF then the result is UNDEF. -static bool isHorizontalBinOp(SDValue &LHS, SDValue &RHS, bool isCommutative) { +static bool isHorizontalBinOp(SDValue &LHS, SDValue &RHS, bool IsCommutative) { // Look for the following pattern: if // A = < float a0, float a1, float a2, float a3 > // B = < float b0, float b1, float b2, float b3 > @@ -14399,34 +14389,28 @@ // If A and B occur in reverse order in RHS, then "swap" them (which means // rewriting the mask). if (A != C) - for (unsigned i = 0; i != NumElts; ++i) { - unsigned Idx = RMask[i]; - if (Idx < NumElts) - RMask[i] += NumElts; - else if (Idx < 2*NumElts) - RMask[i] -= NumElts; - } + CommuteVectorShuffleMask(RMask, NumElts); // At this point LHS and RHS are equivalent to // LHS = VECTOR_SHUFFLE A, B, LMask // RHS = VECTOR_SHUFFLE A, B, RMask // Check that the masks correspond to performing a horizontal operation. for (unsigned i = 0; i != NumElts; ++i) { - unsigned LIdx = LMask[i], RIdx = RMask[i]; + int LIdx = LMask[i], RIdx = RMask[i]; // Ignore any UNDEF components. - if (LIdx >= 2*NumElts || RIdx >= 2*NumElts || - (!A.getNode() && (LIdx < NumElts || RIdx < NumElts)) || - (!B.getNode() && (LIdx >= NumElts || RIdx >= NumElts))) + if (LIdx < 0 || RIdx < 0 || + (!A.getNode() && (LIdx < (int)NumElts || RIdx < (int)NumElts)) || + (!B.getNode() && (LIdx >= (int)NumElts || RIdx >= (int)NumElts))) continue; // Check that successive elements are being operated on. If not, this is // not a horizontal operation. unsigned Src = (i/HalfLaneElts) % 2; // each lane is split between srcs unsigned LaneStart = (i/NumLaneElts) * NumLaneElts; - unsigned Index = 2*(i%HalfLaneElts) + NumElts*Src + LaneStart; + int Index = 2*(i%HalfLaneElts) + NumElts*Src + LaneStart; if (!(LIdx == Index && RIdx == Index + 1) && - !(isCommutative && LIdx == Index + 1 && RIdx == Index)) + !(IsCommutative && LIdx == Index + 1 && RIdx == Index)) return false; } From craig.topper at gmail.com Mon Dec 5 01:27:14 2011 From: craig.topper at gmail.com (Craig Topper) Date: Mon, 05 Dec 2011 07:27:14 -0000 Subject: [llvm-commits] [llvm] r145804 - /llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Message-ID: <20111205072714.AA6741BE003@llvm.org> Author: ctopper Date: Mon Dec 5 01:27:14 2011 New Revision: 145804 URL: http://llvm.org/viewvc/llvm-project?rev=145804&view=rev Log: Remove some leftover remnants that once tried to create 64-bit MMX PALIGNR instructions. Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=145804&r1=145803&r2=145804&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original) +++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Mon Dec 5 01:27:14 2011 @@ -3217,7 +3217,7 @@ static bool isPALIGNRMask(const SmallVectorImpl &Mask, EVT VT, bool hasSSSE3OrAVX) { int i, e = VT.getVectorNumElements(); - if (VT.getSizeInBits() != 128 && VT.getSizeInBits() != 64) + if (VT.getSizeInBits() != 128) return false; // Do not handle v2i64 / v2f64 shuffles with palignr. @@ -11244,7 +11244,7 @@ EVT VT) const { // Very little shuffling can be done for 64-bit vectors right now. if (VT.getSizeInBits() == 64) - return isPALIGNRMask(M, VT, Subtarget->hasSSSE3orAVX()); + return false; // FIXME: pshufb, blends, shifts. return (VT.getVectorNumElements() == 2 || From geek4civic at gmail.com Mon Dec 5 01:54:57 2011 From: geek4civic at gmail.com (NAKAMURA Takumi) Date: Mon, 05 Dec 2011 07:54:57 -0000 Subject: [llvm-commits] [llvm] r145805 - /llvm/trunk/test/CodeGen/X86/pointer-vector.ll Message-ID: <20111205075457.E52F91BE003@llvm.org> Author: chapuni Date: Mon Dec 5 01:54:57 2011 New Revision: 145805 URL: http://llvm.org/viewvc/llvm-project?rev=145805&view=rev Log: test/CodeGen/X86/pointer-vector.ll: Add explicit -mtriple=i686-linux. Modified: llvm/trunk/test/CodeGen/X86/pointer-vector.ll Modified: llvm/trunk/test/CodeGen/X86/pointer-vector.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/pointer-vector.ll?rev=145805&r1=145804&r2=145805&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/X86/pointer-vector.ll (original) +++ llvm/trunk/test/CodeGen/X86/pointer-vector.ll Mon Dec 5 01:54:57 2011 @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=x86 -mcpu=corei7 | FileCheck %s +; RUN: llc < %s -mtriple=i686-linux -mcpu=corei7 | FileCheck %s ; RUN: opt -instsimplify %s -disable-output ;CHECK: SHUFF0 From samsonov at google.com Mon Dec 5 05:11:45 2011 From: samsonov at google.com (samsonov at google.com) Date: Mon, 05 Dec 2011 11:11:45 +0000 Subject: [llvm-commits] Cleanup in ASan interceptors (issue 5437128) Message-ID: <20cf3074d322550fdb04b3566286@google.com> Reviewers: kcc, ramosian.glider, http://codereview.appspot.com/5437128/diff/1/Makefile.old File Makefile.old (right): http://codereview.appspot.com/5437128/diff/1/Makefile.old#newcode162 Makefile.old:162: ASAN_LD_TAIL=$(LIBASAN_A) On 2011/12/04 01:20:31, kcc wrote: > We should not need it. > If we still need it (what's the case?), the fix should go to clang driver. (This > might work as a temporary fix though since the makefile should die anyway) Hm-m, let it be a temporary fix then. Without this change, changes in asan rtl are not reflected when we rebuild the tests (or I'm doing smth completely wrong). http://codereview.appspot.com/5437128/diff/1/asan_interceptors.cc File asan_interceptors.cc (right): http://codereview.appspot.com/5437128/diff/1/asan_interceptors.cc#newcode96 asan_interceptors.cc:96: #define ENSURE_ASAN_INITED do { \ On 2011/12/04 01:20:31, kcc wrote: > make it ENSURE_ASAN_INITED() (here and below) Done. http://codereview.appspot.com/5437128/diff/1/asan_interceptors.cc#newcode101 asan_interceptors.cc:101: } while (0); On 2011/12/04 01:20:31, kcc wrote: > remove ';' Done (for all macro in this file). Please review this at http://codereview.appspot.com/5437128/ Affected files: M Makefile.old M asan_interceptors.cc Index: Makefile.old =================================================================== --- Makefile.old (revision 145805) +++ Makefile.old (working copy) @@ -159,7 +159,7 @@ ifeq ($(ASAN_COMPILER), clang) ASAN_CXX=$(CLANG_ASAN_CXX) ASAN_LD=$(CLANG_ASAN_LD) - ASAN_LD_TAIL= + ASAN_LD_TAIL=$(LIBASAN_A) endif ifeq ($(ASAN_COMPILER), gcc) Index: asan_interceptors.cc =================================================================== --- asan_interceptors.cc (revision 145805) +++ asan_interceptors.cc (working copy) @@ -62,15 +62,15 @@ AccessAddress(ptr, isWrite); \ AccessAddress(ptr + (size) - 1, isWrite); \ } \ -} while (0); +} while (0) #define ASAN_READ_RANGE(offset, size) do { \ ACCESS_MEMORY_RANGE(offset, size, false); \ -} while (0); +} while (0) #define ASAN_WRITE_RANGE(offset, size) do { \ ACCESS_MEMORY_RANGE(offset, size, true); \ -} while (0); +} while (0) // Behavior of functions like "memcpy" or "strcpy" is undefined // if memory intervals overlap. We report error in this case. @@ -90,16 +90,15 @@ PRINT_CURRENT_STACK(); \ ShowStatsAndAbort(); \ } \ -} while (0); +} while (0) -static inline void ensure_asan_inited() { - CHECK(!asan_init_is_running); - if (!asan_inited) { - __asan_init(); - } -} +#define ENSURE_ASAN_INITED() do { \ + CHECK(!asan_init_is_running); \ + if (!asan_inited) { \ + __asan_init(); \ + } \ +} while (0) - size_t internal_strlen(const char *s) { size_t i = 0; while (s[i]) i++; @@ -121,15 +120,9 @@ #else OVERRIDE_FUNCTION(index, WRAP(strchr)); #endif -#ifndef __APPLE__ INTERCEPT_FUNCTION(memcpy); INTERCEPT_FUNCTION(memmove); INTERCEPT_FUNCTION(memset); -#else - real_memcpy = memcpy; - real_memmove = memmove; - real_memset = memset; -#endif INTERCEPT_FUNCTION(strchr); INTERCEPT_FUNCTION(strcmp); INTERCEPT_FUNCTION(strcpy); // NOLINT @@ -156,7 +149,7 @@ if (asan_init_is_running) { return real_memcpy(to, from, size); } - ensure_asan_inited(); + ENSURE_ASAN_INITED(); if (FLAG_replace_intrin) { CHECK_RANGES_OVERLAP(to, from, size); ASAN_WRITE_RANGE(from, size); @@ -166,7 +159,7 @@ } void *WRAP(memmove)(void *to, const void *from, size_t size) { - ensure_asan_inited(); + ENSURE_ASAN_INITED(); if (FLAG_replace_intrin) { ASAN_WRITE_RANGE(from, size); ASAN_READ_RANGE(to, size); @@ -175,7 +168,11 @@ } void *WRAP(memset)(void *block, int c, size_t size) { - ensure_asan_inited(); + // memset is called inside INTERCEPT_FUNCTION on Mac. + if (asan_init_is_running) { + return real_memset(block, c, size); + } + ENSURE_ASAN_INITED(); if (FLAG_replace_intrin) { ASAN_WRITE_RANGE(block, size); } @@ -192,7 +189,7 @@ #endif char *WRAP(strchr)(const char *str, int c) { - ensure_asan_inited(); + ENSURE_ASAN_INITED(); char *result = real_strchr(str, c); if (FLAG_replace_str) { size_t bytes_read = (result ? result - str : real_strlen(str)) + 1; @@ -229,7 +226,7 @@ if (asan_init_is_running) { return real_strcpy(to, from); } - ensure_asan_inited(); + ENSURE_ASAN_INITED(); if (FLAG_replace_str) { size_t from_size = real_strlen(from) + 1; CHECK_RANGES_OVERLAP(to, from, from_size); @@ -240,7 +237,7 @@ } char *WRAP(strdup)(const char *s) { - ensure_asan_inited(); + ENSURE_ASAN_INITED(); if (FLAG_replace_str) { size_t length = real_strlen(s); ASAN_READ_RANGE(s, length + 1); @@ -254,7 +251,7 @@ if (asan_init_is_running) { return real_strlen(s); } - ensure_asan_inited(); + ENSURE_ASAN_INITED(); size_t length = real_strlen(s); if (FLAG_replace_str) { ASAN_READ_RANGE(s, length + 1); @@ -281,7 +278,7 @@ } char *WRAP(strncpy)(char *to, const char *from, size_t size) { - ensure_asan_inited(); + ENSURE_ASAN_INITED(); if (FLAG_replace_str) { size_t from_size = Min(size, internal_strnlen(from, size) + 1); CHECK_RANGES_OVERLAP(to, from, from_size); @@ -293,7 +290,7 @@ #ifndef __APPLE__ size_t WRAP(strnlen)(const char *s, size_t maxlen) { - ensure_asan_inited(); + ENSURE_ASAN_INITED(); size_t length = real_strnlen(s, maxlen); if (FLAG_replace_str) { ASAN_READ_RANGE(s, Min(length + 1, maxlen)); From scanon at apple.com Mon Dec 5 05:37:22 2011 From: scanon at apple.com (Stephen Canon) Date: Mon, 05 Dec 2011 06:37:22 -0500 Subject: [llvm-commits] PATCH: Initial patches for changing the semantics of llvm.cttz and llvm.ctlz In-Reply-To: <2DBA1282-CC2C-430B-9A62-5694D5ABAD4B@apple.com> References: <2DBA1282-CC2C-430B-9A62-5694D5ABAD4B@apple.com> Message-ID: <986B8FE1-E724-446E-B0DB-465FF1595247@apple.com> On Dec 1, 2011, at 2:20 PM, Dan Gohman wrote: > The "old" semantics really are more desirable though, in general. The only > reason I know of for the "new" semantics is to cater to x86's old bsf and > bsr instructions. But x86 admits its own deficiency, and has since introduced > the lzcnt and tzcnt instructions, which behave properly. It seems unfortunate > to require people who want the sane semantics to use a branch (even if > CodeGen is clever and can eliminate it). Agreed. The x86 ISA semantics of BSR/BSF are nuts (and not followed by any other mainstream architecture with which I am familiar). Surely there's some way to give llvm the hint it needs to optimize this particular case on x86 without making the semantics of llvm ir similarly broken. - Steve From stpworld at narod.ru Mon Dec 5 07:03:50 2011 From: stpworld at narod.ru (Stepan Dyatkovskiy) Date: Mon, 05 Dec 2011 17:03:50 +0400 Subject: [llvm-commits] [LLVM, loop-unswitch, bugfix for #11429] Wrong behaviour for switches. In-Reply-To: References: <4ECF4A5A.9030607@narod.ru> <4ED36D99.1080306@narod.ru> <4ED51EEC.6050000@narod.ru> <4ED749D0.8030101@narod.ru> <4ED88CDF.2020104@narod.ru> Message-ID: <4EDCC136.1040903@narod.ru> Hi Dan. This bug is described in details (with examples) here: http://llvm.org/bugs/show_bug.cgi?id=11429 Regarding to your questions.. > It's even possible that this bug is > accidentally helping the code by preventing it from unswitching too > much in the presence of switches. > Do you have an idea on what impact > this patch has on code size, and performance, in general? Happily this bug helps to keep the code size small. But LoopUnswitch::UnswitchIfProfitable method already controls the produced code size. Please, see LoopUnswitch.cpp, string #446 for more details. I think that if we need to improve the "restrictioning" of produced code size we need to implement this improvement instead of keeping some strange code. About impact on code size. For switch with N cases (+ 1 default) we got N new loops. If you wish I can present the .ll code that should be produced after optimization. Impact on performance. The main purpose of this optimization is to move out of loop the switches. Each unswitched case increases the performance. About releaseMemory and CloneUnswitchedVals. This methods the part of unswitch info cloning for new loops. It is also described in bug #11429. > CloneUnswitchedVals doesn't actually need to iterate over the > instructions in the block to find the SwitchInst. If there's a > SwitchInst present, it'll be the Terminator instruction. OK. You're right. Please find the fixed patch. Thanks! -Stepan. > > Thanks, > > Dan > > On Dec 2, 2011, at 12:31 AM, Stepan Dyatkovskiy wrote: > >> >> ping. >> >> -Stepan. >> Stepan Dyatkovskiy wrote: >>> ping. >>> >>> -Stepan. >>> >>> Stepan Dyatkovskiy wrote: >>>> ping. >>>> >>>> -Stepan. >>>> >>>> Stepan Dyatkovskiy wrote: >>>>> ping. >>>>> >>>>> -Stepan >>>>> >>>>> Stepan Dyatkovskiy wrote: >>>>>> Hi all. Please find the patch in attachment for review. Regression tests >>>>>> are attached in separated patch. >>>>>> >>>>>> Short tests description: >>>>>> >>>>>> 2011-11-18-SimpleSwitch.ll >>>>>> Check simple that simple switch will totally unswitched: >>>>>> >>>>>> for (...) >>>>>> switch(c) { >>>>>> case 0: inc(); break; >>>>>> case 1: dec(); break; >>>>>> default: goto loop_exit; >>>>>> } >>>>>> >>>>>> loop_exit: >>>>>> ... >>>>>> >>>>>> Result of processing should be 2 additional loops for c == 0 and for c >>>>>> == 1. >>>>>> >>>>>> >>>>>> 2011-11-18-TwoSwitches.ll >>>>>> Check that second switch will unswitched too. Check that switches will >>>>>> not unswitched again in new loop: >>>>>> >>>>>> Initially we have the next: >>>>>> >>>>>> for (...) { >>>>>> switch(c) { >>>>>> case 0: inc(); break; >>>>>> } >>>>>> switch(d) { >>>>>> case 0: inc(); break; >>>>>> } >>>>>> } >>>>>> >>>>>> After optimization we should got 3 additional loops: when (c == 0&& d >>>>>> == 0), when (c == 0&& d != 0) and when (c != 0&& d == 0). Original >>>>>> loop will activated for (c != 0&& d != 0): >>>>>> >>>>>> if (c == 0&& d == 0) { >>>>>> for (...) ... // All is clear here. Two "switch(0)" instructions. >>>>>> } else if (c == 0&& d != 0) { >>>>>> for (...) { >>>>>> switch (0) { // c == 0 >>>>>> case 0: inc(); break; >>>>>> } >>>>>> switch (d) { >>>>>> case 0: goto unreachable; // CHECK: That it will not unswitched >>>>>> // again, since it looks "trivial", >>>>>> // see LoopUnswitch::IsTrivialUnswitchCondition >>>>>> } >>>>>> } >>>>>> } else if (c != 0&& d == 0) { >>>>>> // the same... >>>>>> ... >>>>>> } else { // if (c != 0&& d != 0) >>>>>> // Original totally unswitched loop: >>>>>> switch (c) { >>>>>> case 0: goto unreachable; >>>>>> } >>>>>> switch (d) { >>>>>> case 0: goto unreachable; >>>>>> } >>>>>> } >>>>>> >>>>>> Stepan. >>>>>> >>>>>> >>>>>> _______________________________________________ >>>>>> llvm-commits mailing list >>>>>> llvm-commits at cs.uiuc.edu >>>>>> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits >>>>> >>>>> _______________________________________________ >>>>> llvm-commits mailing list >>>>> llvm-commits at cs.uiuc.edu >>>>> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits >>>> >>>> _______________________________________________ >>>> llvm-commits mailing list >>>> llvm-commits at cs.uiuc.edu >>>> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits >>> >>> _______________________________________________ >>> llvm-commits mailing list >>> llvm-commits at cs.uiuc.edu >>> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits >> >> _______________________________________________ >> llvm-commits mailing list >> llvm-commits at cs.uiuc.edu >> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits > -------------- next part -------------- A non-text attachment was scrubbed... Name: loop-unswitch-unswitchvals.patch Type: text/x-patch Size: 6362 bytes Desc: not available Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20111205/bfcf2325/attachment.bin From stpworld at narod.ru Mon Dec 5 07:05:38 2011 From: stpworld at narod.ru (Stepan Dyatkovskiy) Date: Mon, 05 Dec 2011 17:05:38 +0400 Subject: [llvm-commits] [LLVM, SelectionDAG] fix for #9905: Failure in code selection for llvm intrinsics sqrt/exp In-Reply-To: <4ED9D140.2070504@narod.ru> References: <4ED74593.2030003@narod.ru> <4ED9D140.2070504@narod.ru> Message-ID: <4EDCC1A2.5010500@narod.ru> ping. -Stepan. Stepan Dyatkovskiy wrote: > ping. > > -Stepan > > Stepan Dyatkovskiy wrote: >> Hi all. Please find the patch and regression tests in attachment for >> review. >> This patch for ARM. It fixes selection for several instructions that >> works with v4f32 arguments: FSQRT, FSIN, FCOS, FPOWI, FPOW, FLOG, FLOG2, >> FLOG10, FEXP, FEXP2. >> I'm still worrying about FCOPYSIGN, FNEG, FABS, FCEIL, FTRUNC, FRINT, >> FNEARBYINT, FFLOOR. I could not found a way to add this instructions >> with v2f32 argument to DAG. It seems that it is impossible in ToT. So >> these instructions was not fixed. >> >> -Stepan. >> >> >> _______________________________________________ >> llvm-commits mailing list >> llvm-commits at cs.uiuc.edu >> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From glider at google.com Mon Dec 5 02:44:28 2011 From: glider at google.com (Alexander Potapenko) Date: Mon, 5 Dec 2011 12:44:28 +0400 Subject: [llvm-commits] AddressSanitizer GCD tests on Mac: prevent optimization, enable. Message-ID: Fix GCD tests for AddressSanitizer on Mac. The following patch declares the char* vars holding the memory allocations as volatile, which prevents the compiler from optimizing them and breaking the tests. I'm also enabling the tests by default, as the GCD support in ASan runtime library is quite stable already. -- Alexander Potapenko Software Engineer Google Moscow -------------- next part -------------- A non-text attachment was scrubbed... Name: asan-mac-test.patch Type: text/x-patch Size: 4035 bytes Desc: not available Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20111205/8ba6136d/attachment.bin From victor.umansky at intel.com Mon Dec 5 06:26:20 2011 From: victor.umansky at intel.com (Umansky, Victor) Date: Mon, 5 Dec 2011 14:26:20 +0200 Subject: [llvm-commits] x86 branch sequence optimization in LLVM code gen: please review Message-ID: <021AD592C708E24FA11FD214489EC9BE0123F25260@hasmsx501.ger.corp.intel.com> Hi, My name is Victor Umansky; I'm an engineer in Intel OpenCL Team. The attached patch contains an optimization of ptest-conditioned branch. I.e., the following LLVM IR code %res = call i32 @llvm.x86.sse41.ptestz(<4 x float> %a, <4 x float> %a) nounwind %tmp = and i32 %res, 1 %one = icmp eq i32 %tmp, 0 br i1 %one, label %label1, label %label2 ends with the following x86 machine code sequence: ptest XMM3, XMM3 sete AL movzx EAX, AL test EAX, EAX jne LBB18_26 which can be optimized to: ptest XMM3, XMM3 je LBB18_26 The current machine code sequence stems from the need to coordinate i32 return type from the ptestz intrinsic with i1 condition type for branch IR instruction. Consequently we can optimize it in x86 codegen backend where the both condition producer (ptest) amd consumer (jcc) use the same x86 EFLAGS register, and thus in-between conversions of the condition can be quietly dropped. The optimization is focused on x86 DAG combining (post-legalization stage) which recognizes the sequence and converts it to the minimized one. The attached patch file includes both the x86 backend instruction combining modification and a LIT regression test for it. I'd like to commit the fix to the LLVM trunk, and your feedback will be mostly appreciated. Best Regards, Victor --------------------------------------------------------------------- Intel Israel (74) Limited This e-mail and any attachments may contain confidential material for the sole use of the intended recipient(s). Any review or distribution by others is strictly prohibited. If you are not the intended recipient, please contact the sender and delete all copies. -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20111205/b8b519d1/attachment.html -------------- next part -------------- A non-text attachment was scrubbed... Name: brcond_combining.patch Type: application/octet-stream Size: 6435 bytes Desc: brcond_combining.patch Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20111205/b8b519d1/attachment.obj From bruno.cardoso at gmail.com Mon Dec 5 11:12:49 2011 From: bruno.cardoso at gmail.com (Bruno Cardoso Lopes) Date: Mon, 5 Dec 2011 15:12:49 -0200 Subject: [llvm-commits] x86 branch sequence optimization in LLVM code gen: please review In-Reply-To: <021AD592C708E24FA11FD214489EC9BE0123F25260@hasmsx501.ger.corp.intel.com> References: <021AD592C708E24FA11FD214489EC9BE0123F25260@hasmsx501.ger.corp.intel.com> Message-ID: Hi Victor, On Mon, Dec 5, 2011 at 10:26 AM, Umansky, Victor wrote: > Hi, > > My name is Victor Umansky; I?m an engineer in Intel OpenCL Team. > > The attached patch contains an optimization of ptest-conditioned branch. > > I.e., the following LLVM IR code > > %res = call i32 @llvm.x86.sse41.ptestz(<4 x float> %a, <4 x float> > %a) nounwind > %tmp = and i32 %res, 1 > %one = icmp eq i32 %tmp, 0 > br i1 %one, label %label1, label %label2 > > ends with the following x86 machine code sequence: > > ptest XMM3, XMM3 > sete AL > movzx EAX, AL > test EAX, EAX > jne LBB18_26 > > which can be optimized to: > > ptest XMM3, XMM3 > je LBB18_26 > > > The current machine code sequence stems from the need to coordinate *i32 > return type* from the ptestz intrinsic with *i1 condition type* for > branch IR instruction. > Consequently we can optimize it in x86 codegen backend where the both > condition producer (ptest) amd consumer (jcc) use the *same x86 **EFLAGS > register*, and thus in-between conversions of the condition can be > quietly dropped. > > The optimization is focused on x86 DAG combining (post-legalization stage) > which recognizes the sequence and converts it to the minimized one. > > The attached patch file includes both the x86 backend instruction > combining modification and a LIT regression test for it. > > > I?d like to commit the fix to the LLVM trunk, and your feedback will be > mostly appreciated. > > +; RUN: llc %s -march=x86-64 -mcpu=corei7 -o %t.asm +; RUN: FileCheck %s --input-file=%t.asm Please do like the other tests, and read the file with "< %s". Also, place it under test/CodeGen/X86/brcond.ll -- Bruno Cardoso Lopes http://www.brunocardoso.cc -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20111205/8e6d2f7f/attachment.html From benny.kra at googlemail.com Mon Dec 5 11:23:27 2011 From: benny.kra at googlemail.com (Benjamin Kramer) Date: Mon, 05 Dec 2011 17:23:27 -0000 Subject: [llvm-commits] [llvm] r145810 - in /llvm/trunk/lib: Transforms/Utils/AddrModeMatcher.cpp VMCore/Value.cpp Message-ID: <20111205172328.0317E2A6C12C@llvm.org> Author: d0k Date: Mon Dec 5 11:23:27 2011 New Revision: 145810 URL: http://llvm.org/viewvc/llvm-project?rev=145810&view=rev Log: Add a little heuristic to Value::isUsedInBasicBlock to speed it up for small basic blocks. - Calling getUser in a loop is much more expensive than iterating over a few instructions. - Use it instead of the open-coded loop in AddrModeMatcher. - 5% speedup on ARMDisassembler.cpp Release builds. Modified: llvm/trunk/lib/Transforms/Utils/AddrModeMatcher.cpp llvm/trunk/lib/VMCore/Value.cpp Modified: llvm/trunk/lib/Transforms/Utils/AddrModeMatcher.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Utils/AddrModeMatcher.cpp?rev=145810&r1=145809&r2=145810&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Utils/AddrModeMatcher.cpp (original) +++ llvm/trunk/lib/Transforms/Utils/AddrModeMatcher.cpp Mon Dec 5 11:23:27 2011 @@ -473,14 +473,7 @@ // Check to see if this value is already used in the memory instruction's // block. If so, it's already live into the block at the very least, so we // can reasonably fold it. - BasicBlock *MemBB = MemoryInst->getParent(); - for (Value::use_iterator UI = Val->use_begin(), E = Val->use_end(); - UI != E; ++UI) - // We know that uses of arguments and instructions have to be instructions. - if (cast(*UI)->getParent() == MemBB) - return true; - - return false; + return Val->isUsedInBasicBlock(MemoryInst->getParent()); } Modified: llvm/trunk/lib/VMCore/Value.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/Value.cpp?rev=145810&r1=145809&r2=145810&view=diff ============================================================================== --- llvm/trunk/lib/VMCore/Value.cpp (original) +++ llvm/trunk/lib/VMCore/Value.cpp Mon Dec 5 11:23:27 2011 @@ -108,6 +108,19 @@ /// isUsedInBasicBlock - Return true if this value is used in the specified /// basic block. bool Value::isUsedInBasicBlock(const BasicBlock *BB) const { + // Start by scanning over the instructions looking for a use before we start + // the expensive use iteration. + unsigned MaxBlockSize = 3; + for (BasicBlock::const_iterator I = BB->begin(), E = BB->end(); I != E; ++I) { + if (std::find(I->op_begin(), I->op_end(), this) != I->op_end()) + return true; + if (MaxBlockSize-- == 0) // If the block is larger fall back to use_iterator + break; + } + + if (MaxBlockSize != 0) // We scanned the entire block and found no use. + return false; + for (const_use_iterator I = use_begin(), E = use_end(); I != E; ++I) { const Instruction *User = dyn_cast(*I); if (User && User->getParent() == BB) From hfinkel at anl.gov Mon Dec 5 11:54:18 2011 From: hfinkel at anl.gov (Hal Finkel) Date: Mon, 05 Dec 2011 17:54:18 -0000 Subject: [llvm-commits] [llvm] r145816 - /llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.cpp Message-ID: <20111205175418.0C62B2A6C12C@llvm.org> Author: hfinkel Date: Mon Dec 5 11:54:17 2011 New Revision: 145816 URL: http://llvm.org/viewvc/llvm-project?rev=145816&view=rev Log: add register pressure for CR regs Modified: llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.cpp Modified: llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.cpp?rev=145816&r1=145815&r2=145816&view=diff ============================================================================== --- llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.cpp (original) +++ llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.cpp Mon Dec 5 11:54:17 2011 @@ -291,6 +291,8 @@ case PPC::F4RCRegClassID: case PPC::VRRCRegClassID: return 32 - DefaultSafety; + case PPC::CRRCRegClassID: + return 8 - DefaultSafety; } } From hfinkel at anl.gov Mon Dec 5 11:55:06 2011 From: hfinkel at anl.gov (Hal Finkel) Date: Mon, 05 Dec 2011 17:55:06 -0000 Subject: [llvm-commits] [llvm] r145817 - /llvm/trunk/test/CodeGen/PowerPC/2010-02-12-saveCR.ll Message-ID: <20111205175506.E17512A6C12C@llvm.org> Author: hfinkel Date: Mon Dec 5 11:55:06 2011 New Revision: 145817 URL: http://llvm.org/viewvc/llvm-project?rev=145817&view=rev Log: remove wasted space for extra bit copies of CR2 subregs Modified: llvm/trunk/test/CodeGen/PowerPC/2010-02-12-saveCR.ll Modified: llvm/trunk/test/CodeGen/PowerPC/2010-02-12-saveCR.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/2010-02-12-saveCR.ll?rev=145817&r1=145816&r2=145817&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/PowerPC/2010-02-12-saveCR.ll (original) +++ llvm/trunk/test/CodeGen/PowerPC/2010-02-12-saveCR.ll Mon Dec 5 11:55:06 2011 @@ -9,7 +9,7 @@ ;CHECK: mfcr r2 ;CHECK: lis r0, 1 ;CHECK: rlwinm r2, r2, 8, 0, 31 -;CHECK: ori r0, r0, 34540 +;CHECK: ori r0, r0, 34524 ;CHECK: stwx r2, r1, r0 %x = alloca [100000 x i8] ; <[100000 x i8]*> [#uses=1] %"alloca point" = bitcast i32 0 to i32 ; [#uses=0] @@ -20,7 +20,7 @@ return: ; preds = %entry ;CHECK: lis r0, 1 -;CHECK: ori r0, r0, 34540 +;CHECK: ori r0, r0, 34524 ;CHECK: lwzx r2, r1, r0 ;CHECK: rlwinm r2, r2, 24, 0, 31 ;CHECK: mtcrf 32, r2 From hfinkel at anl.gov Mon Dec 5 11:55:13 2011 From: hfinkel at anl.gov (Hal Finkel) Date: Mon, 05 Dec 2011 17:55:13 -0000 Subject: [llvm-commits] [llvm] r145818 - /llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.cpp Message-ID: <20111205175513.259212A6C12C@llvm.org> Author: hfinkel Date: Mon Dec 5 11:55:12 2011 New Revision: 145818 URL: http://llvm.org/viewvc/llvm-project?rev=145818&view=rev Log: don't include CR bit subregs in callee-saved list Modified: llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.cpp Modified: llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.cpp?rev=145818&r1=145817&r2=145818&view=diff ============================================================================== --- llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.cpp (original) +++ llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.cpp Mon Dec 5 11:55:12 2011 @@ -120,10 +120,6 @@ PPC::V24, PPC::V25, PPC::V26, PPC::V27, PPC::V28, PPC::V29, PPC::V30, PPC::V31, - PPC::CR2LT, PPC::CR2GT, PPC::CR2EQ, PPC::CR2UN, - PPC::CR3LT, PPC::CR3GT, PPC::CR3EQ, PPC::CR3UN, - PPC::CR4LT, PPC::CR4GT, PPC::CR4EQ, PPC::CR4UN, - PPC::LR, 0 }; @@ -149,10 +145,6 @@ PPC::V24, PPC::V25, PPC::V26, PPC::V27, PPC::V28, PPC::V29, PPC::V30, PPC::V31, - PPC::CR2LT, PPC::CR2GT, PPC::CR2EQ, PPC::CR2UN, - PPC::CR3LT, PPC::CR3GT, PPC::CR3EQ, PPC::CR3UN, - PPC::CR4LT, PPC::CR4GT, PPC::CR4EQ, PPC::CR4UN, - 0 }; // 64-bit Darwin calling convention. @@ -174,10 +166,6 @@ PPC::V24, PPC::V25, PPC::V26, PPC::V27, PPC::V28, PPC::V29, PPC::V30, PPC::V31, - PPC::CR2LT, PPC::CR2GT, PPC::CR2EQ, PPC::CR2UN, - PPC::CR3LT, PPC::CR3GT, PPC::CR3EQ, PPC::CR3UN, - PPC::CR4LT, PPC::CR4GT, PPC::CR4EQ, PPC::CR4UN, - PPC::LR8, 0 }; @@ -203,10 +191,6 @@ PPC::V24, PPC::V25, PPC::V26, PPC::V27, PPC::V28, PPC::V29, PPC::V30, PPC::V31, - PPC::CR2LT, PPC::CR2GT, PPC::CR2EQ, PPC::CR2UN, - PPC::CR3LT, PPC::CR3GT, PPC::CR3EQ, PPC::CR3UN, - PPC::CR4LT, PPC::CR4GT, PPC::CR4EQ, PPC::CR4UN, - 0 }; From hfinkel at anl.gov Mon Dec 5 11:55:18 2011 From: hfinkel at anl.gov (Hal Finkel) Date: Mon, 05 Dec 2011 17:55:18 -0000 Subject: [llvm-commits] [llvm] r145819 - in /llvm/trunk: lib/Target/PowerPC/PPCFrameLowering.cpp lib/Target/PowerPC/PPCInstrInfo.cpp lib/Target/PowerPC/PPCRegisterInfo.cpp test/CodeGen/PowerPC/2008-03-05-RegScavengerAssert.ll test/CodeGen/PowerPC/2008-03-17-RegScavengerCrash.ll test/CodeGen/PowerPC/2008-03-18-RegScavengerAssert.ll test/CodeGen/PowerPC/2010-02-12-saveCR.ll test/CodeGen/PowerPC/Frames-alloca.ll test/CodeGen/PowerPC/ppc32-vaarg.ll Message-ID: <20111205175518.343FF2A6C12C@llvm.org> Author: hfinkel Date: Mon Dec 5 11:55:17 2011 New Revision: 145819 URL: http://llvm.org/viewvc/llvm-project?rev=145819&view=rev Log: enable PPC register scavenging by default (update tests and remove some FIXMEs) Modified: llvm/trunk/lib/Target/PowerPC/PPCFrameLowering.cpp llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.cpp llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.cpp llvm/trunk/test/CodeGen/PowerPC/2008-03-05-RegScavengerAssert.ll llvm/trunk/test/CodeGen/PowerPC/2008-03-17-RegScavengerCrash.ll llvm/trunk/test/CodeGen/PowerPC/2008-03-18-RegScavengerAssert.ll llvm/trunk/test/CodeGen/PowerPC/2010-02-12-saveCR.ll llvm/trunk/test/CodeGen/PowerPC/Frames-alloca.ll llvm/trunk/test/CodeGen/PowerPC/ppc32-vaarg.ll Modified: llvm/trunk/lib/Target/PowerPC/PPCFrameLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCFrameLowering.cpp?rev=145819&r1=145818&r2=145819&view=diff ============================================================================== --- llvm/trunk/lib/Target/PowerPC/PPCFrameLowering.cpp (original) +++ llvm/trunk/lib/Target/PowerPC/PPCFrameLowering.cpp Mon Dec 5 11:55:17 2011 @@ -772,7 +772,7 @@ // FIXME: doesn't detect whether or not we need to spill vXX, which requires // r0 for now. - if (RegInfo->requiresRegisterScavenging(MF)) // FIXME (64-bit): Enable. + if (RegInfo->requiresRegisterScavenging(MF)) if (needsFP(MF) || spillsCR(MF)) { const TargetRegisterClass *GPRC = &PPC::GPRCRegClass; const TargetRegisterClass *G8RC = &PPC::G8RCRegClass; Modified: llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.cpp?rev=145819&r1=145818&r2=145819&view=diff ============================================================================== --- llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.cpp (original) +++ llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.cpp Mon Dec 5 11:55:17 2011 @@ -33,8 +33,8 @@ #include "PPCGenInstrInfo.inc" namespace llvm { -extern cl::opt EnablePPC32RS; // FIXME (64-bit): See PPCRegisterInfo.cpp. -extern cl::opt EnablePPC64RS; // FIXME (64-bit): See PPCRegisterInfo.cpp. +extern cl::opt DisablePPC32RS; +extern cl::opt DisablePPC64RS; } using namespace llvm; @@ -345,6 +345,7 @@ BuildMI(MBB, I, DL, MCID, DestReg).addReg(SrcReg, getKillRegState(KillSrc)); } +// This function returns true if a CR spill is necessary and false otherwise. bool PPCInstrInfo::StoreRegToStackSlot(MachineFunction &MF, unsigned SrcReg, bool isKill, @@ -395,9 +396,8 @@ getKillRegState(isKill)), FrameIdx)); } else if (PPC::CRRCRegisterClass->hasSubClassEq(RC)) { - if ((EnablePPC32RS && !TM.getSubtargetImpl()->isPPC64()) || - (EnablePPC64RS && TM.getSubtargetImpl()->isPPC64())) { - // FIXME (64-bit): Enable + if ((!DisablePPC32RS && !TM.getSubtargetImpl()->isPPC64()) || + (!DisablePPC64RS && TM.getSubtargetImpl()->isPPC64())) { NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::SPILL_CR)) .addReg(SrcReg, getKillRegState(isKill)), Modified: llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.cpp?rev=145819&r1=145818&r2=145819&view=diff ============================================================================== --- llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.cpp (original) +++ llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.cpp Mon Dec 5 11:55:17 2011 @@ -46,15 +46,14 @@ #define GET_REGINFO_TARGET_DESC #include "PPCGenRegisterInfo.inc" -// FIXME (64-bit): Eventually enable by default. namespace llvm { -cl::opt EnablePPC32RS("enable-ppc32-regscavenger", +cl::opt DisablePPC32RS("disable-ppc32-regscavenger", cl::init(false), - cl::desc("Enable PPC32 register scavenger"), + cl::desc("Disable PPC32 register scavenger"), cl::Hidden); -cl::opt EnablePPC64RS("enable-ppc64-regscavenger", +cl::opt DisablePPC64RS("disable-ppc64-regscavenger", cl::init(false), - cl::desc("Enable PPC64 register scavenger"), + cl::desc("Disable PPC64 register scavenger"), cl::Hidden); } @@ -63,8 +62,8 @@ // FIXME (64-bit): Should be inlined. bool PPCRegisterInfo::requiresRegisterScavenging(const MachineFunction &) const { - return ((EnablePPC32RS && !Subtarget.isPPC64()) || - (EnablePPC64RS && Subtarget.isPPC64())); + return ((!DisablePPC32RS && !Subtarget.isPPC64()) || + (!DisablePPC64RS && Subtarget.isPPC64())); } PPCRegisterInfo::PPCRegisterInfo(const PPCSubtarget &ST, @@ -231,9 +230,6 @@ Reserved.set(PPC::R13); Reserved.set(PPC::R31); - if (!requiresRegisterScavenging(MF)) - Reserved.set(PPC::R0); // FIXME (64-bit): Remove - Reserved.set(PPC::X0); Reserved.set(PPC::X1); Reserved.set(PPC::X13); @@ -544,7 +540,7 @@ } // Special case for pseudo-op SPILL_CR. - if (requiresRegisterScavenging(MF)) // FIXME (64-bit): Enable by default. + if (requiresRegisterScavenging(MF)) if (OpC == PPC::SPILL_CR) { lowerCRSpilling(II, FrameIndex, SPAdj, RS); return; Modified: llvm/trunk/test/CodeGen/PowerPC/2008-03-05-RegScavengerAssert.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/2008-03-05-RegScavengerAssert.ll?rev=145819&r1=145818&r2=145819&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/PowerPC/2008-03-05-RegScavengerAssert.ll (original) +++ llvm/trunk/test/CodeGen/PowerPC/2008-03-05-RegScavengerAssert.ll Mon Dec 5 11:55:17 2011 @@ -1,4 +1,4 @@ -; RUN: llc < %s -mtriple=powerpc-apple-darwin -enable-ppc32-regscavenger +; RUN: llc < %s -mtriple=powerpc-apple-darwin declare i8* @bar(i32) Modified: llvm/trunk/test/CodeGen/PowerPC/2008-03-17-RegScavengerCrash.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/2008-03-17-RegScavengerCrash.ll?rev=145819&r1=145818&r2=145819&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/PowerPC/2008-03-17-RegScavengerCrash.ll (original) +++ llvm/trunk/test/CodeGen/PowerPC/2008-03-17-RegScavengerCrash.ll Mon Dec 5 11:55:17 2011 @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=ppc32 -enable-ppc32-regscavenger +; RUN: llc < %s -march=ppc32 %struct._cpp_strbuf = type { i8*, i32, i32 } %struct.cpp_string = type { i32, i8* } Modified: llvm/trunk/test/CodeGen/PowerPC/2008-03-18-RegScavengerAssert.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/2008-03-18-RegScavengerAssert.ll?rev=145819&r1=145818&r2=145819&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/PowerPC/2008-03-18-RegScavengerAssert.ll (original) +++ llvm/trunk/test/CodeGen/PowerPC/2008-03-18-RegScavengerAssert.ll Mon Dec 5 11:55:17 2011 @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=ppc64 -enable-ppc64-regscavenger +; RUN: llc < %s -march=ppc64 define i16 @test(i8* %d1, i16* %d2) { %tmp237 = call i16 asm "lhbrx $0, $2, $1", "=r,r,bO,m"( i8* %d1, i32 0, i16* %d2 ) Modified: llvm/trunk/test/CodeGen/PowerPC/2010-02-12-saveCR.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/2010-02-12-saveCR.ll?rev=145819&r1=145818&r2=145819&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/PowerPC/2010-02-12-saveCR.ll (original) +++ llvm/trunk/test/CodeGen/PowerPC/2010-02-12-saveCR.ll Mon Dec 5 11:55:17 2011 @@ -6,11 +6,11 @@ define void @foo() nounwind { entry: -;CHECK: mfcr r2 -;CHECK: lis r0, 1 -;CHECK: rlwinm r2, r2, 8, 0, 31 -;CHECK: ori r0, r0, 34524 -;CHECK: stwx r2, r1, r0 +;CHECK: lis r4, 1 +;CHECK: ori r4, r4, 34524 +;CHECK: mfcr r3 +;CHECK: rlwinm r3, r3, 8, 0, 31 +;CHECK: stwx r3, r1, r4 %x = alloca [100000 x i8] ; <[100000 x i8]*> [#uses=1] %"alloca point" = bitcast i32 0 to i32 ; [#uses=0] %x1 = bitcast [100000 x i8]* %x to i8* ; [#uses=1] @@ -19,9 +19,9 @@ br label %return return: ; preds = %entry -;CHECK: lis r0, 1 -;CHECK: ori r0, r0, 34524 -;CHECK: lwzx r2, r1, r0 +;CHECK: lis r3, 1 +;CHECK: ori r3, r3, 34524 +;CHECK: lwzx r2, r1, r3 ;CHECK: rlwinm r2, r2, 24, 0, 31 ;CHECK: mtcrf 32, r2 ret void Modified: llvm/trunk/test/CodeGen/PowerPC/Frames-alloca.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/Frames-alloca.ll?rev=145819&r1=145818&r2=145819&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/PowerPC/Frames-alloca.ll (original) +++ llvm/trunk/test/CodeGen/PowerPC/Frames-alloca.ll Mon Dec 5 11:55:17 2011 @@ -2,9 +2,9 @@ ; RUN: llc < %s -march=ppc64 -mtriple=powerpc-apple-darwin8 | FileCheck %s -check-prefix=PPC64 ; RUN: llc < %s -march=ppc32 -mtriple=powerpc-apple-darwin8 -disable-fp-elim | FileCheck %s -check-prefix=PPC32-NOFP ; RUN: llc < %s -march=ppc64 -mtriple=powerpc-apple-darwin8 -disable-fp-elim | FileCheck %s -check-prefix=PPC64-NOFP -; RUN: llc < %s -march=ppc32 -mtriple=powerpc-apple-darwin8 -enable-ppc32-regscavenger | FileCheck %s -check-prefix=PPC32 -; RUN: llc < %s -march=ppc32 -mtriple=powerpc-apple-darwin8 -enable-ppc32-regscavenger | FileCheck %s -check-prefix=PPC32-RS -; RUN: llc < %s -march=ppc32 -mtriple=powerpc-apple-darwin8 -disable-fp-elim -enable-ppc32-regscavenger | FileCheck %s -check-prefix=PPC32-RS-NOFP +; RUN: llc < %s -march=ppc32 -mtriple=powerpc-apple-darwin8 | FileCheck %s -check-prefix=PPC32 +; RUN: llc < %s -march=ppc32 -mtriple=powerpc-apple-darwin8 | FileCheck %s -check-prefix=PPC32-RS +; RUN: llc < %s -march=ppc32 -mtriple=powerpc-apple-darwin8 -disable-fp-elim | FileCheck %s -check-prefix=PPC32-RS-NOFP ; CHECK-PPC32: stw r31, -4(r1) ; CHECK-PPC32: lwz r1, 0(r1) Modified: llvm/trunk/test/CodeGen/PowerPC/ppc32-vaarg.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/ppc32-vaarg.ll?rev=145819&r1=145818&r2=145819&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/PowerPC/ppc32-vaarg.ll (original) +++ llvm/trunk/test/CodeGen/PowerPC/ppc32-vaarg.ll Mon Dec 5 11:55:17 2011 @@ -37,8 +37,8 @@ ; CHECK-NEXT: stw 3, -24(1) ; CHECK-NEXT: stw 8, -28(1) ; CHECK-NEXT: stw 6, -32(1) -; CHECK-NEXT: mfcr 0 # cr0 -; CHECK-NEXT: stw 0, -36(1) +; CHECK-NEXT: mfcr 3 # cr0 +; CHECK-NEXT: stw 3, -36(1) ; CHECK-NEXT: blt 0, .LBB0_4 ; CHECK-NEXT: # BB#3: # %entry ; CHECK-NEXT: lwz 3, -20(1) @@ -82,8 +82,8 @@ ; CHECK-NEXT: stw 4, -52(1) ; CHECK-NEXT: stw 6, -56(1) ; CHECK-NEXT: stw 8, -60(1) -; CHECK-NEXT: mfcr 0 # cr0 -; CHECK-NEXT: stw 0, -64(1) +; CHECK-NEXT: mfcr 3 # cr0 +; CHECK-NEXT: stw 3, -64(1) ; CHECK-NEXT: blt 0, .LBB0_8 ; CHECK-NEXT: # BB#7: # %entry ; CHECK-NEXT: lwz 3, -48(1) @@ -122,8 +122,8 @@ ; CHECK-NEXT: mr 8, 5 ; CHECK-NEXT: stw 4, -72(1) ; CHECK-NEXT: stw 6, -76(1) -; CHECK-NEXT: mfcr 0 # cr0 -; CHECK-NEXT: stw 0, -80(1) +; CHECK-NEXT: mfcr 3 # cr0 +; CHECK-NEXT: stw 3, -80(1) ; CHECK-NEXT: stw 5, -84(1) ; CHECK-NEXT: stw 8, -88(1) ; CHECK-NEXT: stw 7, -92(1) From hfinkel at anl.gov Mon Dec 5 11:55:22 2011 From: hfinkel at anl.gov (Hal Finkel) Date: Mon, 05 Dec 2011 17:55:22 -0000 Subject: [llvm-commits] [llvm] r145820 - /llvm/trunk/test/CodeGen/PowerPC/2011-12-05-NoSpillDupCR.ll Message-ID: <20111205175522.F0EF22A6C12C@llvm.org> Author: hfinkel Date: Mon Dec 5 11:55:22 2011 New Revision: 145820 URL: http://llvm.org/viewvc/llvm-project?rev=145820&view=rev Log: Add test case - this input used to crash because of duplicate generation of SPILL_CRs Added: llvm/trunk/test/CodeGen/PowerPC/2011-12-05-NoSpillDupCR.ll Added: llvm/trunk/test/CodeGen/PowerPC/2011-12-05-NoSpillDupCR.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/2011-12-05-NoSpillDupCR.ll?rev=145820&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/PowerPC/2011-12-05-NoSpillDupCR.ll (added) +++ llvm/trunk/test/CodeGen/PowerPC/2011-12-05-NoSpillDupCR.ll Mon Dec 5 11:55:22 2011 @@ -0,0 +1,191 @@ +; RUN: llc < %s -mtriple=powerpc-apple-darwin -mcpu=g4 | FileCheck %s +; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=g4 | FileCheck %s + +; ModuleID = 'tsc.c' +target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32:64" +target triple = "powerpc64-unknown-linux-gnu" + + at a = common global [32000 x float] zeroinitializer, align 16 + at b = common global [32000 x float] zeroinitializer, align 16 + at c = common global [32000 x float] zeroinitializer, align 16 + at d = common global [32000 x float] zeroinitializer, align 16 + at e = common global [32000 x float] zeroinitializer, align 16 + at aa = common global [256 x [256 x float]] zeroinitializer, align 16 + at bb = common global [256 x [256 x float]] zeroinitializer, align 16 + at cc = common global [256 x [256 x float]] zeroinitializer, align 16 + + at .str11 = private unnamed_addr constant [6 x i8] c"s122 \00", align 1 + at .str152 = private unnamed_addr constant [14 x i8] c"S122\09 %.2f \09\09\00", align 1 + +declare i32 @printf(i8* nocapture, ...) nounwind +declare i32 @init(i8* %name) nounwind +declare i64 @clock() nounwind +declare i32 @dummy(float*, float*, float*, float*, float*, [256 x float]*, [256 x float]*, [256 x float]*, float) +declare void @check(i32 %name) nounwind + +; CHECK: mfcr +; CHECK: mtcr + +define i32 @s122(i32 %n1, i32 %n3) nounwind { +entry: + %call = tail call i32 @init(i8* getelementptr inbounds ([6 x i8]* @.str11, i64 0, i64 0)) + %call1 = tail call i64 @clock() nounwind + %sub = add nsw i32 %n1, -1 + %cmp316 = icmp slt i32 %sub, 32000 + br i1 %cmp316, label %entry.split.us, label %for.end.7 + +entry.split.us: ; preds = %entry + %0 = sext i32 %sub to i64 + %1 = sext i32 %n3 to i64 + br label %for.body4.lr.ph.us + +for.body4.us: ; preds = %for.body4.lr.ph.us, %for.body4.us + %indvars.iv20 = phi i64 [ 0, %for.body4.lr.ph.us ], [ %indvars.iv.next21, %for.body4.us ] + %indvars.iv = phi i64 [ %0, %for.body4.lr.ph.us ], [ %indvars.iv.next, %for.body4.us ] + %indvars.iv.next21 = add i64 %indvars.iv20, 1 + %sub5.us = sub i64 31999, %indvars.iv20 + %sext = shl i64 %sub5.us, 32 + %idxprom.us = ashr exact i64 %sext, 32 + %arrayidx.us = getelementptr inbounds [32000 x float]* @b, i64 0, i64 %idxprom.us + %2 = load float* %arrayidx.us, align 4, !tbaa !5 + %arrayidx7.us = getelementptr inbounds [32000 x float]* @a, i64 0, i64 %indvars.iv + %3 = load float* %arrayidx7.us, align 4, !tbaa !5 + %add8.us = fadd float %3, %2 + store float %add8.us, float* %arrayidx7.us, align 4, !tbaa !5 + %indvars.iv.next = add i64 %indvars.iv, %1 + %4 = trunc i64 %indvars.iv.next to i32 + %cmp3.us = icmp slt i32 %4, 32000 + br i1 %cmp3.us, label %for.body4.us, label %for.body4.lr.ph.us.1 + +for.body4.lr.ph.us: ; preds = %entry.split.us, %for.end.us.4 + %nl.019.us = phi i32 [ 0, %entry.split.us ], [ %inc.us.4, %for.end.us.4 ] + br label %for.body4.us + +for.end12: ; preds = %for.end.7, %for.end.us.4 + %call13 = tail call i64 @clock() nounwind + %sub14 = sub nsw i64 %call13, %call1 + %conv = sitofp i64 %sub14 to double + %div = fdiv double %conv, 1.000000e+06 + %call15 = tail call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([14 x i8]* @.str152, i64 0, i64 0), double %div) nounwind + tail call void @check(i32 1) + ret i32 0 + +for.body4.lr.ph.us.1: ; preds = %for.body4.us + %call10.us = tail call i32 @dummy(float* getelementptr inbounds ([32000 x float]* @a, i64 0, i64 0), float* getelementptr inbounds ([32000 x float]* @b, i64 0, i64 0), float* getelementptr inbounds ([32000 x float]* @c, i64 0, i64 0), float* getelementptr inbounds ([32000 x float]* @d, i64 0, i64 0), float* getelementptr inbounds ([32000 x float]* @e, i64 0, i64 0), [256 x float]* getelementptr inbounds ([256 x [256 x float]]* @aa, i64 0, i64 0), [256 x float]* getelementptr inbounds ([256 x [256 x float]]* @bb, i64 0, i64 0), [256 x float]* getelementptr inbounds ([256 x [256 x float]]* @cc, i64 0, i64 0), float 0.000000e+00) nounwind + br label %for.body4.us.1 + +for.body4.us.1: ; preds = %for.body4.us.1, %for.body4.lr.ph.us.1 + %indvars.iv20.1 = phi i64 [ 0, %for.body4.lr.ph.us.1 ], [ %indvars.iv.next21.1, %for.body4.us.1 ] + %indvars.iv.1 = phi i64 [ %0, %for.body4.lr.ph.us.1 ], [ %indvars.iv.next.1, %for.body4.us.1 ] + %indvars.iv.next21.1 = add i64 %indvars.iv20.1, 1 + %sub5.us.1 = sub i64 31999, %indvars.iv20.1 + %sext23 = shl i64 %sub5.us.1, 32 + %idxprom.us.1 = ashr exact i64 %sext23, 32 + %arrayidx.us.1 = getelementptr inbounds [32000 x float]* @b, i64 0, i64 %idxprom.us.1 + %5 = load float* %arrayidx.us.1, align 4, !tbaa !5 + %arrayidx7.us.1 = getelementptr inbounds [32000 x float]* @a, i64 0, i64 %indvars.iv.1 + %6 = load float* %arrayidx7.us.1, align 4, !tbaa !5 + %add8.us.1 = fadd float %6, %5 + store float %add8.us.1, float* %arrayidx7.us.1, align 4, !tbaa !5 + %indvars.iv.next.1 = add i64 %indvars.iv.1, %1 + %7 = trunc i64 %indvars.iv.next.1 to i32 + %cmp3.us.1 = icmp slt i32 %7, 32000 + br i1 %cmp3.us.1, label %for.body4.us.1, label %for.body4.lr.ph.us.2 + +for.body4.lr.ph.us.2: ; preds = %for.body4.us.1 + %call10.us.1 = tail call i32 @dummy(float* getelementptr inbounds ([32000 x float]* @a, i64 0, i64 0), float* getelementptr inbounds ([32000 x float]* @b, i64 0, i64 0), float* getelementptr inbounds ([32000 x float]* @c, i64 0, i64 0), float* getelementptr inbounds ([32000 x float]* @d, i64 0, i64 0), float* getelementptr inbounds ([32000 x float]* @e, i64 0, i64 0), [256 x float]* getelementptr inbounds ([256 x [256 x float]]* @aa, i64 0, i64 0), [256 x float]* getelementptr inbounds ([256 x [256 x float]]* @bb, i64 0, i64 0), [256 x float]* getelementptr inbounds ([256 x [256 x float]]* @cc, i64 0, i64 0), float 0.000000e+00) nounwind + br label %for.body4.us.2 + +for.body4.us.2: ; preds = %for.body4.us.2, %for.body4.lr.ph.us.2 + %indvars.iv20.2 = phi i64 [ 0, %for.body4.lr.ph.us.2 ], [ %indvars.iv.next21.2, %for.body4.us.2 ] + %indvars.iv.2 = phi i64 [ %0, %for.body4.lr.ph.us.2 ], [ %indvars.iv.next.2, %for.body4.us.2 ] + %indvars.iv.next21.2 = add i64 %indvars.iv20.2, 1 + %sub5.us.2 = sub i64 31999, %indvars.iv20.2 + %sext24 = shl i64 %sub5.us.2, 32 + %idxprom.us.2 = ashr exact i64 %sext24, 32 + %arrayidx.us.2 = getelementptr inbounds [32000 x float]* @b, i64 0, i64 %idxprom.us.2 + %8 = load float* %arrayidx.us.2, align 4, !tbaa !5 + %arrayidx7.us.2 = getelementptr inbounds [32000 x float]* @a, i64 0, i64 %indvars.iv.2 + %9 = load float* %arrayidx7.us.2, align 4, !tbaa !5 + %add8.us.2 = fadd float %9, %8 + store float %add8.us.2, float* %arrayidx7.us.2, align 4, !tbaa !5 + %indvars.iv.next.2 = add i64 %indvars.iv.2, %1 + %10 = trunc i64 %indvars.iv.next.2 to i32 + %cmp3.us.2 = icmp slt i32 %10, 32000 + br i1 %cmp3.us.2, label %for.body4.us.2, label %for.body4.lr.ph.us.3 + +for.body4.lr.ph.us.3: ; preds = %for.body4.us.2 + %call10.us.2 = tail call i32 @dummy(float* getelementptr inbounds ([32000 x float]* @a, i64 0, i64 0), float* getelementptr inbounds ([32000 x float]* @b, i64 0, i64 0), float* getelementptr inbounds ([32000 x float]* @c, i64 0, i64 0), float* getelementptr inbounds ([32000 x float]* @d, i64 0, i64 0), float* getelementptr inbounds ([32000 x float]* @e, i64 0, i64 0), [256 x float]* getelementptr inbounds ([256 x [256 x float]]* @aa, i64 0, i64 0), [256 x float]* getelementptr inbounds ([256 x [256 x float]]* @bb, i64 0, i64 0), [256 x float]* getelementptr inbounds ([256 x [256 x float]]* @cc, i64 0, i64 0), float 0.000000e+00) nounwind + br label %for.body4.us.3 + +for.body4.us.3: ; preds = %for.body4.us.3, %for.body4.lr.ph.us.3 + %indvars.iv20.3 = phi i64 [ 0, %for.body4.lr.ph.us.3 ], [ %indvars.iv.next21.3, %for.body4.us.3 ] + %indvars.iv.3 = phi i64 [ %0, %for.body4.lr.ph.us.3 ], [ %indvars.iv.next.3, %for.body4.us.3 ] + %indvars.iv.next21.3 = add i64 %indvars.iv20.3, 1 + %sub5.us.3 = sub i64 31999, %indvars.iv20.3 + %sext25 = shl i64 %sub5.us.3, 32 + %idxprom.us.3 = ashr exact i64 %sext25, 32 + %arrayidx.us.3 = getelementptr inbounds [32000 x float]* @b, i64 0, i64 %idxprom.us.3 + %11 = load float* %arrayidx.us.3, align 4, !tbaa !5 + %arrayidx7.us.3 = getelementptr inbounds [32000 x float]* @a, i64 0, i64 %indvars.iv.3 + %12 = load float* %arrayidx7.us.3, align 4, !tbaa !5 + %add8.us.3 = fadd float %12, %11 + store float %add8.us.3, float* %arrayidx7.us.3, align 4, !tbaa !5 + %indvars.iv.next.3 = add i64 %indvars.iv.3, %1 + %13 = trunc i64 %indvars.iv.next.3 to i32 + %cmp3.us.3 = icmp slt i32 %13, 32000 + br i1 %cmp3.us.3, label %for.body4.us.3, label %for.body4.lr.ph.us.4 + +for.body4.lr.ph.us.4: ; preds = %for.body4.us.3 + %call10.us.3 = tail call i32 @dummy(float* getelementptr inbounds ([32000 x float]* @a, i64 0, i64 0), float* getelementptr inbounds ([32000 x float]* @b, i64 0, i64 0), float* getelementptr inbounds ([32000 x float]* @c, i64 0, i64 0), float* getelementptr inbounds ([32000 x float]* @d, i64 0, i64 0), float* getelementptr inbounds ([32000 x float]* @e, i64 0, i64 0), [256 x float]* getelementptr inbounds ([256 x [256 x float]]* @aa, i64 0, i64 0), [256 x float]* getelementptr inbounds ([256 x [256 x float]]* @bb, i64 0, i64 0), [256 x float]* getelementptr inbounds ([256 x [256 x float]]* @cc, i64 0, i64 0), float 0.000000e+00) nounwind + br label %for.body4.us.4 + +for.body4.us.4: ; preds = %for.body4.us.4, %for.body4.lr.ph.us.4 + %indvars.iv20.4 = phi i64 [ 0, %for.body4.lr.ph.us.4 ], [ %indvars.iv.next21.4, %for.body4.us.4 ] + %indvars.iv.4 = phi i64 [ %0, %for.body4.lr.ph.us.4 ], [ %indvars.iv.next.4, %for.body4.us.4 ] + %indvars.iv.next21.4 = add i64 %indvars.iv20.4, 1 + %sub5.us.4 = sub i64 31999, %indvars.iv20.4 + %sext26 = shl i64 %sub5.us.4, 32 + %idxprom.us.4 = ashr exact i64 %sext26, 32 + %arrayidx.us.4 = getelementptr inbounds [32000 x float]* @b, i64 0, i64 %idxprom.us.4 + %14 = load float* %arrayidx.us.4, align 4, !tbaa !5 + %arrayidx7.us.4 = getelementptr inbounds [32000 x float]* @a, i64 0, i64 %indvars.iv.4 + %15 = load float* %arrayidx7.us.4, align 4, !tbaa !5 + %add8.us.4 = fadd float %15, %14 + store float %add8.us.4, float* %arrayidx7.us.4, align 4, !tbaa !5 + %indvars.iv.next.4 = add i64 %indvars.iv.4, %1 + %16 = trunc i64 %indvars.iv.next.4 to i32 + %cmp3.us.4 = icmp slt i32 %16, 32000 + br i1 %cmp3.us.4, label %for.body4.us.4, label %for.end.us.4 + +for.end.us.4: ; preds = %for.body4.us.4 + %call10.us.4 = tail call i32 @dummy(float* getelementptr inbounds ([32000 x float]* @a, i64 0, i64 0), float* getelementptr inbounds ([32000 x float]* @b, i64 0, i64 0), float* getelementptr inbounds ([32000 x float]* @c, i64 0, i64 0), float* getelementptr inbounds ([32000 x float]* @d, i64 0, i64 0), float* getelementptr inbounds ([32000 x float]* @e, i64 0, i64 0), [256 x float]* getelementptr inbounds ([256 x [256 x float]]* @aa, i64 0, i64 0), [256 x float]* getelementptr inbounds ([256 x [256 x float]]* @bb, i64 0, i64 0), [256 x float]* getelementptr inbounds ([256 x [256 x float]]* @cc, i64 0, i64 0), float 0.000000e+00) nounwind + %inc.us.4 = add nsw i32 %nl.019.us, 5 + %exitcond.4 = icmp eq i32 %inc.us.4, 200000 + br i1 %exitcond.4, label %for.end12, label %for.body4.lr.ph.us + +for.end.7: ; preds = %entry, %for.end.7 + %nl.019 = phi i32 [ %inc.7, %for.end.7 ], [ 0, %entry ] + %call10 = tail call i32 @dummy(float* getelementptr inbounds ([32000 x float]* @a, i64 0, i64 0), float* getelementptr inbounds ([32000 x float]* @b, i64 0, i64 0), float* getelementptr inbounds ([32000 x float]* @c, i64 0, i64 0), float* getelementptr inbounds ([32000 x float]* @d, i64 0, i64 0), float* getelementptr inbounds ([32000 x float]* @e, i64 0, i64 0), [256 x float]* getelementptr inbounds ([256 x [256 x float]]* @aa, i64 0, i64 0), [256 x float]* getelementptr inbounds ([256 x [256 x float]]* @bb, i64 0, i64 0), [256 x float]* getelementptr inbounds ([256 x [256 x float]]* @cc, i64 0, i64 0), float 0.000000e+00) nounwind + %call10.1 = tail call i32 @dummy(float* getelementptr inbounds ([32000 x float]* @a, i64 0, i64 0), float* getelementptr inbounds ([32000 x float]* @b, i64 0, i64 0), float* getelementptr inbounds ([32000 x float]* @c, i64 0, i64 0), float* getelementptr inbounds ([32000 x float]* @d, i64 0, i64 0), float* getelementptr inbounds ([32000 x float]* @e, i64 0, i64 0), [256 x float]* getelementptr inbounds ([256 x [256 x float]]* @aa, i64 0, i64 0), [256 x float]* getelementptr inbounds ([256 x [256 x float]]* @bb, i64 0, i64 0), [256 x float]* getelementptr inbounds ([256 x [256 x float]]* @cc, i64 0, i64 0), float 0.000000e+00) nounwind + %call10.2 = tail call i32 @dummy(float* getelementptr inbounds ([32000 x float]* @a, i64 0, i64 0), float* getelementptr inbounds ([32000 x float]* @b, i64 0, i64 0), float* getelementptr inbounds ([32000 x float]* @c, i64 0, i64 0), float* getelementptr inbounds ([32000 x float]* @d, i64 0, i64 0), float* getelementptr inbounds ([32000 x float]* @e, i64 0, i64 0), [256 x float]* getelementptr inbounds ([256 x [256 x float]]* @aa, i64 0, i64 0), [256 x float]* getelementptr inbounds ([256 x [256 x float]]* @bb, i64 0, i64 0), [256 x float]* getelementptr inbounds ([256 x [256 x float]]* @cc, i64 0, i64 0), float 0.000000e+00) nounwind + %call10.3 = tail call i32 @dummy(float* getelementptr inbounds ([32000 x float]* @a, i64 0, i64 0), float* getelementptr inbounds ([32000 x float]* @b, i64 0, i64 0), float* getelementptr inbounds ([32000 x float]* @c, i64 0, i64 0), float* getelementptr inbounds ([32000 x float]* @d, i64 0, i64 0), float* getelementptr inbounds ([32000 x float]* @e, i64 0, i64 0), [256 x float]* getelementptr inbounds ([256 x [256 x float]]* @aa, i64 0, i64 0), [256 x float]* getelementptr inbounds ([256 x [256 x float]]* @bb, i64 0, i64 0), [256 x float]* getelementptr inbounds ([256 x [256 x float]]* @cc, i64 0, i64 0), float 0.000000e+00) nounwind + %call10.4 = tail call i32 @dummy(float* getelementptr inbounds ([32000 x float]* @a, i64 0, i64 0), float* getelementptr inbounds ([32000 x float]* @b, i64 0, i64 0), float* getelementptr inbounds ([32000 x float]* @c, i64 0, i64 0), float* getelementptr inbounds ([32000 x float]* @d, i64 0, i64 0), float* getelementptr inbounds ([32000 x float]* @e, i64 0, i64 0), [256 x float]* getelementptr inbounds ([256 x [256 x float]]* @aa, i64 0, i64 0), [256 x float]* getelementptr inbounds ([256 x [256 x float]]* @bb, i64 0, i64 0), [256 x float]* getelementptr inbounds ([256 x [256 x float]]* @cc, i64 0, i64 0), float 0.000000e+00) nounwind + %call10.5 = tail call i32 @dummy(float* getelementptr inbounds ([32000 x float]* @a, i64 0, i64 0), float* getelementptr inbounds ([32000 x float]* @b, i64 0, i64 0), float* getelementptr inbounds ([32000 x float]* @c, i64 0, i64 0), float* getelementptr inbounds ([32000 x float]* @d, i64 0, i64 0), float* getelementptr inbounds ([32000 x float]* @e, i64 0, i64 0), [256 x float]* getelementptr inbounds ([256 x [256 x float]]* @aa, i64 0, i64 0), [256 x float]* getelementptr inbounds ([256 x [256 x float]]* @bb, i64 0, i64 0), [256 x float]* getelementptr inbounds ([256 x [256 x float]]* @cc, i64 0, i64 0), float 0.000000e+00) nounwind + %call10.6 = tail call i32 @dummy(float* getelementptr inbounds ([32000 x float]* @a, i64 0, i64 0), float* getelementptr inbounds ([32000 x float]* @b, i64 0, i64 0), float* getelementptr inbounds ([32000 x float]* @c, i64 0, i64 0), float* getelementptr inbounds ([32000 x float]* @d, i64 0, i64 0), float* getelementptr inbounds ([32000 x float]* @e, i64 0, i64 0), [256 x float]* getelementptr inbounds ([256 x [256 x float]]* @aa, i64 0, i64 0), [256 x float]* getelementptr inbounds ([256 x [256 x float]]* @bb, i64 0, i64 0), [256 x float]* getelementptr inbounds ([256 x [256 x float]]* @cc, i64 0, i64 0), float 0.000000e+00) nounwind + %call10.7 = tail call i32 @dummy(float* getelementptr inbounds ([32000 x float]* @a, i64 0, i64 0), float* getelementptr inbounds ([32000 x float]* @b, i64 0, i64 0), float* getelementptr inbounds ([32000 x float]* @c, i64 0, i64 0), float* getelementptr inbounds ([32000 x float]* @d, i64 0, i64 0), float* getelementptr inbounds ([32000 x float]* @e, i64 0, i64 0), [256 x float]* getelementptr inbounds ([256 x [256 x float]]* @aa, i64 0, i64 0), [256 x float]* getelementptr inbounds ([256 x [256 x float]]* @bb, i64 0, i64 0), [256 x float]* getelementptr inbounds ([256 x [256 x float]]* @cc, i64 0, i64 0), float 0.000000e+00) nounwind + %inc.7 = add nsw i32 %nl.019, 8 + %exitcond.7 = icmp eq i32 %inc.7, 200000 + br i1 %exitcond.7, label %for.end12, label %for.end.7 +} + +declare void @llvm.memcpy.p0i8.p0i8.i64(i8* nocapture, i8* nocapture, i64, i32, i1) nounwind + +declare i32 @puts(i8* nocapture) nounwind + +!0 = metadata !{metadata !"any pointer", metadata !1} +!1 = metadata !{metadata !"omnipotent char", metadata !2} +!2 = metadata !{metadata !"Simple C/C++ TBAA", null} +!3 = metadata !{metadata !"branch_weights", i32 64, i32 4} +!4 = metadata !{metadata !"int", metadata !1} +!5 = metadata !{metadata !"float", metadata !1} From kcc at google.com Mon Dec 5 11:56:33 2011 From: kcc at google.com (Kostya Serebryany) Date: Mon, 05 Dec 2011 17:56:33 -0000 Subject: [llvm-commits] [compiler-rt] r145821 - in /compiler-rt/trunk/lib/asan: asan_interceptors.h asan_rtl.cc Message-ID: <20111205175633.274CB2A6C12C@llvm.org> Author: kcc Date: Mon Dec 5 11:56:32 2011 New Revision: 145821 URL: http://llvm.org/viewvc/llvm-project?rev=145821&view=rev Log: [asan] don't require __cxa_throw to be present in the process. This is the last dependency on libstdc++ Modified: compiler-rt/trunk/lib/asan/asan_interceptors.h compiler-rt/trunk/lib/asan/asan_rtl.cc Modified: compiler-rt/trunk/lib/asan/asan_interceptors.h URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/lib/asan/asan_interceptors.h?rev=145821&r1=145820&r2=145821&view=diff ============================================================================== --- compiler-rt/trunk/lib/asan/asan_interceptors.h (original) +++ compiler-rt/trunk/lib/asan/asan_interceptors.h Mon Dec 5 11:56:32 2011 @@ -37,18 +37,33 @@ #include "mach_override/mach_override.h" #define WRAP(x) wrap_##x #define WRAPPER_NAME(x) "wrap_"#x + #define OVERRIDE_FUNCTION(oldfunc, newfunc) \ CHECK(0 == mach_override_ptr((void*)(oldfunc), \ (void*)(newfunc), \ (void**)&real_##oldfunc)); \ CHECK(real_##oldfunc != NULL); + +#define OVERRIDE_FUNCTION_IF_EXISTS(oldfunc, newfunc) \ + do { mach_override_ptr((void*)(oldfunc), \ + (void*)(newfunc), \ + (void**)&real_##oldfunc); } while (0) + #define INTERCEPT_FUNCTION(func) \ OVERRIDE_FUNCTION(func, WRAP(func)) -#else + +#define INTERCEPT_FUNCTION_IF_EXISTS(func) \ + OVERRIDE_FUNCTION_IF_EXISTS(func, WRAP(func)) + +#else // __linux__ #define WRAP(x) x #define WRAPPER_NAME(x) #x + #define INTERCEPT_FUNCTION(func) \ CHECK((real_##func = (func##_f)dlsym(RTLD_NEXT, #func))); + +#define INTERCEPT_FUNCTION_IF_EXISTS(func) \ + do { real_##func = (func##_f)dlsym(RTLD_NEXT, #func); } while (0) #endif #ifdef __APPLE__ Modified: compiler-rt/trunk/lib/asan/asan_rtl.cc URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/lib/asan/asan_rtl.cc?rev=145821&r1=145820&r2=145821&view=diff ============================================================================== --- compiler-rt/trunk/lib/asan/asan_rtl.cc (original) +++ compiler-rt/trunk/lib/asan/asan_rtl.cc Mon Dec 5 11:56:32 2011 @@ -507,6 +507,7 @@ #if ASAN_HAS_EXCEPTIONS extern "C" void WRAP(__cxa_throw)(void *a, void *b, void *c) { + CHECK(&real___cxa_throw); UnpoisonStackFromHereToTop(); real___cxa_throw(a, b, c); } @@ -690,7 +691,7 @@ INTERCEPT_FUNCTION(signal); INTERCEPT_FUNCTION(longjmp); INTERCEPT_FUNCTION(_longjmp); - INTERCEPT_FUNCTION(__cxa_throw); + INTERCEPT_FUNCTION_IF_EXISTS(__cxa_throw); INTERCEPT_FUNCTION(pthread_create); #ifdef __APPLE__ INTERCEPT_FUNCTION(dispatch_async_f); From stoklund at 2pi.dk Mon Dec 5 12:12:57 2011 From: stoklund at 2pi.dk (Jakob Stoklund Olesen) Date: Mon, 05 Dec 2011 10:12:57 -0800 Subject: [llvm-commits] [llvm] r145819 - in /llvm/trunk: lib/Target/PowerPC/PPCFrameLowering.cpp lib/Target/PowerPC/PPCInstrInfo.cpp lib/Target/PowerPC/PPCRegisterInfo.cpp test/CodeGen/PowerPC/2008-03-05-RegScavengerAssert.ll test/CodeGen/PowerPC/2008-03-17-RegScavengerCrash.ll test/CodeGen/PowerPC/2008-03-18-RegScavengerAssert.ll test/CodeGen/PowerPC/2010-02-12-saveCR.ll test/CodeGen/PowerPC/Frames-alloca.ll test/CodeGen/PowerPC/ppc32-vaarg.ll In-Reply-To: <20111205175518.343FF2A6C12C@llvm.org> References: <20111205175518.343FF2A6C12C@llvm.org> Message-ID: On Dec 5, 2011, at 9:55 AM, Hal Finkel wrote: > Author: hfinkel > Date: Mon Dec 5 11:55:17 2011 > New Revision: 145819 > > URL: http://llvm.org/viewvc/llvm-project?rev=145819&view=rev > Log: > enable PPC register scavenging by default (update tests and remove some FIXMEs) Nice! Did you run extensive tests with this change? Does it work with -O0? The register scavenger is notorious for exposing sloppy liveness info in older targets like PPC. I would expect a number of scavenger assertions. /jakob From kcc at google.com Mon Dec 5 12:56:29 2011 From: kcc at google.com (Kostya Serebryany) Date: Mon, 05 Dec 2011 18:56:29 -0000 Subject: [llvm-commits] [compiler-rt] r145826 - /compiler-rt/trunk/lib/asan/asan_interceptors.cc Message-ID: <20111205185629.3CD7A2A6C12C@llvm.org> Author: kcc Date: Mon Dec 5 12:56:29 2011 New Revision: 145826 URL: http://llvm.org/viewvc/llvm-project?rev=145826&view=rev Log: [asan] cleanup memset/memmove/memcpy interceptors and enable them on Mac. Patch by samsonov at google.com Modified: compiler-rt/trunk/lib/asan/asan_interceptors.cc Modified: compiler-rt/trunk/lib/asan/asan_interceptors.cc URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/lib/asan/asan_interceptors.cc?rev=145826&r1=145825&r2=145826&view=diff ============================================================================== --- compiler-rt/trunk/lib/asan/asan_interceptors.cc (original) +++ compiler-rt/trunk/lib/asan/asan_interceptors.cc Mon Dec 5 12:56:29 2011 @@ -62,15 +62,15 @@ AccessAddress(ptr, isWrite); \ AccessAddress(ptr + (size) - 1, isWrite); \ } \ -} while (0); +} while (0) #define ASAN_READ_RANGE(offset, size) do { \ ACCESS_MEMORY_RANGE(offset, size, false); \ -} while (0); +} while (0) #define ASAN_WRITE_RANGE(offset, size) do { \ ACCESS_MEMORY_RANGE(offset, size, true); \ -} while (0); +} while (0) // Behavior of functions like "memcpy" or "strcpy" is undefined // if memory intervals overlap. We report error in this case. @@ -90,15 +90,14 @@ PRINT_CURRENT_STACK(); \ ShowStatsAndAbort(); \ } \ -} while (0); - -static inline void ensure_asan_inited() { - CHECK(!asan_init_is_running); - if (!asan_inited) { - __asan_init(); - } -} +} while (0) +#define ENSURE_ASAN_INITED() do { \ + CHECK(!asan_init_is_running); \ + if (!asan_inited) { \ + __asan_init(); \ + } \ +} while (0) size_t internal_strlen(const char *s) { size_t i = 0; @@ -121,15 +120,9 @@ #else OVERRIDE_FUNCTION(index, WRAP(strchr)); #endif -#ifndef __APPLE__ INTERCEPT_FUNCTION(memcpy); INTERCEPT_FUNCTION(memmove); INTERCEPT_FUNCTION(memset); -#else - real_memcpy = memcpy; - real_memmove = memmove; - real_memset = memset; -#endif INTERCEPT_FUNCTION(strchr); INTERCEPT_FUNCTION(strcmp); INTERCEPT_FUNCTION(strcpy); // NOLINT @@ -156,7 +149,7 @@ if (asan_init_is_running) { return real_memcpy(to, from, size); } - ensure_asan_inited(); + ENSURE_ASAN_INITED(); if (FLAG_replace_intrin) { CHECK_RANGES_OVERLAP(to, from, size); ASAN_WRITE_RANGE(from, size); @@ -166,7 +159,7 @@ } void *WRAP(memmove)(void *to, const void *from, size_t size) { - ensure_asan_inited(); + ENSURE_ASAN_INITED(); if (FLAG_replace_intrin) { ASAN_WRITE_RANGE(from, size); ASAN_READ_RANGE(to, size); @@ -175,7 +168,11 @@ } void *WRAP(memset)(void *block, int c, size_t size) { - ensure_asan_inited(); + // memset is called inside INTERCEPT_FUNCTION on Mac. + if (asan_init_is_running) { + return real_memset(block, c, size); + } + ENSURE_ASAN_INITED(); if (FLAG_replace_intrin) { ASAN_WRITE_RANGE(block, size); } @@ -192,7 +189,7 @@ #endif char *WRAP(strchr)(const char *str, int c) { - ensure_asan_inited(); + ENSURE_ASAN_INITED(); char *result = real_strchr(str, c); if (FLAG_replace_str) { size_t bytes_read = (result ? result - str : real_strlen(str)) + 1; @@ -229,7 +226,7 @@ if (asan_init_is_running) { return real_strcpy(to, from); } - ensure_asan_inited(); + ENSURE_ASAN_INITED(); if (FLAG_replace_str) { size_t from_size = real_strlen(from) + 1; CHECK_RANGES_OVERLAP(to, from, from_size); @@ -240,7 +237,7 @@ } char *WRAP(strdup)(const char *s) { - ensure_asan_inited(); + ENSURE_ASAN_INITED(); if (FLAG_replace_str) { size_t length = real_strlen(s); ASAN_READ_RANGE(s, length + 1); @@ -254,7 +251,7 @@ if (asan_init_is_running) { return real_strlen(s); } - ensure_asan_inited(); + ENSURE_ASAN_INITED(); size_t length = real_strlen(s); if (FLAG_replace_str) { ASAN_READ_RANGE(s, length + 1); @@ -281,7 +278,7 @@ } char *WRAP(strncpy)(char *to, const char *from, size_t size) { - ensure_asan_inited(); + ENSURE_ASAN_INITED(); if (FLAG_replace_str) { size_t from_size = Min(size, internal_strnlen(from, size) + 1); CHECK_RANGES_OVERLAP(to, from, from_size); @@ -293,7 +290,7 @@ #ifndef __APPLE__ size_t WRAP(strnlen)(const char *s, size_t maxlen) { - ensure_asan_inited(); + ENSURE_ASAN_INITED(); size_t length = real_strnlen(s, maxlen); if (FLAG_replace_str) { ASAN_READ_RANGE(s, Min(length + 1, maxlen)); From kcc at google.com Mon Dec 5 13:00:13 2011 From: kcc at google.com (Kostya Serebryany) Date: Mon, 5 Dec 2011 11:00:13 -0800 Subject: [llvm-commits] Cleanup in ASan interceptors, makefile fix In-Reply-To: References: Message-ID: landed the part with the interceptors as r145826. On Sat, Dec 3, 2011 at 2:35 PM, Alexey Samsonov wrote: > Hello! > > This is a cleanup for projects/compiler-rt/lib/asan: > Rietveld link: http://codereview.appspot.com/5437128/ > > Makefile.old : > 1. Fix in Makefile - changes in asan_*.{cc,h} files were not captured > by "make test" command. > asan_interceptors.cc: > 1. ensure_asan_inited() is now a macro (so that CHECK failure outputs > the line inside a function with troubles). > 2. wiped out stubs, as memset/memmove/memcpy interceptors are now enabled. > > -- > Alexey Samsonov > Software Engineer, Moscow > samsonov at google.com > -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20111205/577d9cf5/attachment.html From konstantin.s.serebryany at gmail.com Mon Dec 5 13:00:55 2011 From: konstantin.s.serebryany at gmail.com (konstantin.s.serebryany at gmail.com) Date: Mon, 05 Dec 2011 19:00:55 +0000 Subject: [llvm-commits] Cleanup in ASan interceptors (issue 5437128) Message-ID: <20cf300fae133a7ea604b35cf0c8@google.com> > Hm-m, let it be a temporary fix then. Without this change, changes in asan rtl > are not reflected when we rebuild the tests (or I'm doing smth completely > wrong). I am not sure this is a good goal, but I am sure this is a wrong solution. http://codereview.appspot.com/5437128/ From kcc at google.com Mon Dec 5 13:04:33 2011 From: kcc at google.com (Kostya Serebryany) Date: Mon, 5 Dec 2011 11:04:33 -0800 Subject: [llvm-commits] AddressSanitizer GCD tests on Mac: prevent optimization, enable. In-Reply-To: References: Message-ID: I wonder if you can reuse Ident() from tests/asan_test_utils.h instead of using volatile. Like this: char *mem = Ident(malloc(10)); // This function returns its parameter but in such a way that compiler // can not prove it. template __attribute__((noinline)) static T Ident(T t) { ... --kcc On Mon, Dec 5, 2011 at 12:44 AM, Alexander Potapenko wrote: > Fix GCD tests for AddressSanitizer on Mac. > The following patch declares the char* vars holding the memory > allocations as volatile, which prevents the compiler from optimizing > them and breaking the tests. > I'm also enabling the tests by default, as the GCD support in ASan > runtime library is quite stable already. > > -- > Alexander Potapenko > Software Engineer > Google Moscow > -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20111205/5af341d9/attachment.html From hfinkel at anl.gov Mon Dec 5 13:14:25 2011 From: hfinkel at anl.gov (Hal Finkel) Date: Mon, 05 Dec 2011 13:14:25 -0600 Subject: [llvm-commits] [llvm] r145819 - in /llvm/trunk: lib/Target/PowerPC/PPCFrameLowering.cpp lib/Target/PowerPC/PPCInstrInfo.cpp lib/Target/PowerPC/PPCRegisterInfo.cpp test/CodeGen/PowerPC/2008-03-05-RegScavengerAssert.ll test/CodeGen/PowerPC/2008-03-17-RegScavengerCrash.ll test/CodeGen/PowerPC/2008-03-18-RegScavengerAssert.ll test/CodeGen/PowerPC/2010-02-12-saveCR.ll test/CodeGen/PowerPC/Frames-alloca.ll test/CodeGen/PowerPC/ppc32-vaarg.ll In-Reply-To: References: <20111205175518.343FF2A6C12C@llvm.org> Message-ID: <1323112465.2507.3170.camel@sapling> On Mon, 2011-12-05 at 10:12 -0800, Jakob Stoklund Olesen wrote: > On Dec 5, 2011, at 9:55 AM, Hal Finkel wrote: > > > Author: hfinkel > > Date: Mon Dec 5 11:55:17 2011 > > New Revision: 145819 > > > > URL: http://llvm.org/viewvc/llvm-project?rev=145819&view=rev > > Log: > > enable PPC register scavenging by default (update tests and remove some FIXMEs) > > Nice! > > Did you run extensive tests with this change? Not extensive; I ran the regression tests and a few other files I've been using recently. I'll be setup soon to run the test suite on ppc64, and so I'll test more-extensively using the test suite. Unfortunately, there are still other problems that I have to fix first (like PR11476, which may be related to register scavenging, but was not fixed by these changes). > Does it work with -O0? Good point, I'll run some more tests (and the test suite) with -O0. Some of the regression tests specify -O0 (like the varargs test, which seemed to be fine). Thanks again, Hal > > The register scavenger is notorious for exposing sloppy liveness info in older targets like PPC. I would expect a number of scavenger assertions. > > /jakob > -- Hal Finkel Postdoctoral Appointee Leadership Computing Facility Argonne National Laboratory From ganna at apple.com Mon Dec 5 13:17:04 2011 From: ganna at apple.com (Anna Zaks) Date: Mon, 05 Dec 2011 19:17:04 -0000 Subject: [llvm-commits] [llvm] r145837 - in /llvm/trunk/include/llvm: ADT/GraphTraits.h Analysis/DominatorInternals.h Analysis/Dominators.h CodeGen/MachineFunction.h Support/CFG.h Message-ID: <20111205191704.D37242A6C12C@llvm.org> Author: zaks Date: Mon Dec 5 13:17:04 2011 New Revision: 145837 URL: http://llvm.org/viewvc/llvm-project?rev=145837&view=rev Log: Change the Dominators recalculate() function to only rely on GraphTraits This is a patch by Guoping Long! As part of utilizing LLVM Dominator computation in Clang, made two changes to LLVM dominators tree implementation: - (1) Change the recalculate() template function to only rely on GraphTraits. - (2) Add a size() method to GraphTraits template class to query the number of nodes in the graph. Modified: llvm/trunk/include/llvm/ADT/GraphTraits.h llvm/trunk/include/llvm/Analysis/DominatorInternals.h llvm/trunk/include/llvm/Analysis/Dominators.h llvm/trunk/include/llvm/CodeGen/MachineFunction.h llvm/trunk/include/llvm/Support/CFG.h Modified: llvm/trunk/include/llvm/ADT/GraphTraits.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/ADT/GraphTraits.h?rev=145837&r1=145836&r2=145837&view=diff ============================================================================== --- llvm/trunk/include/llvm/ADT/GraphTraits.h (original) +++ llvm/trunk/include/llvm/ADT/GraphTraits.h Mon Dec 5 13:17:04 2011 @@ -43,9 +43,12 @@ // typedef ...iterator nodes_iterator; // static nodes_iterator nodes_begin(GraphType *G) // static nodes_iterator nodes_end (GraphType *G) - // // nodes_iterator/begin/end - Allow iteration over all nodes in the graph + // static unsigned size (GraphType *G) + // Return total number of nodes in the graph + // + // If anyone tries to use this class without having an appropriate // specialization, make an error. If you get this error, it's because you Modified: llvm/trunk/include/llvm/Analysis/DominatorInternals.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Analysis/DominatorInternals.h?rev=145837&r1=145836&r2=145837&view=diff ============================================================================== --- llvm/trunk/include/llvm/Analysis/DominatorInternals.h (original) +++ llvm/trunk/include/llvm/Analysis/DominatorInternals.h Mon Dec 5 13:17:04 2011 @@ -171,7 +171,7 @@ // it might be that some blocks did not get a DFS number (e.g., blocks of // infinite loops). In these cases an artificial exit node is required. - MultipleRoots |= (DT.isPostDominator() && N != F.size()); + MultipleRoots |= (DT.isPostDominator() && N != GraphTraits::size(&F)); // When naively implemented, the Lengauer-Tarjan algorithm requires a separate // bucket for each vertex. However, this is unnecessary, because each vertex Modified: llvm/trunk/include/llvm/Analysis/Dominators.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Analysis/Dominators.h?rev=145837&r1=145836&r2=145837&view=diff ============================================================================== --- llvm/trunk/include/llvm/Analysis/Dominators.h (original) +++ llvm/trunk/include/llvm/Analysis/Dominators.h Mon Dec 5 13:17:04 2011 @@ -653,21 +653,24 @@ /// recalculate - compute a dominator tree for the given function template void recalculate(FT& F) { + typedef GraphTraits TraitsTy; reset(); this->Vertex.push_back(0); if (!this->IsPostDominators) { // Initialize root - this->Roots.push_back(&F.front()); - this->IDoms[&F.front()] = 0; - this->DomTreeNodes[&F.front()] = 0; + NodeT *entry = TraitsTy::getEntryNode(&F); + this->Roots.push_back(entry); + this->IDoms[entry] = 0; + this->DomTreeNodes[entry] = 0; Calculate(*this, F); } else { // Initialize the roots list - for (typename FT::iterator I = F.begin(), E = F.end(); I != E; ++I) { - if (std::distance(GraphTraits::child_begin(I), - GraphTraits::child_end(I)) == 0) + for (typename TraitsTy::nodes_iterator I = TraitsTy::nodes_begin(&F), + E = TraitsTy::nodes_end(&F); I != E; ++I) { + if (std::distance(TraitsTy::child_begin(I), + TraitsTy::child_end(I)) == 0) addRoot(I); // Prepopulate maps so that we don't get iterator invalidation issues later. Modified: llvm/trunk/include/llvm/CodeGen/MachineFunction.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/MachineFunction.h?rev=145837&r1=145836&r2=145837&view=diff ============================================================================== --- llvm/trunk/include/llvm/CodeGen/MachineFunction.h (original) +++ llvm/trunk/include/llvm/CodeGen/MachineFunction.h Mon Dec 5 13:17:04 2011 @@ -437,6 +437,7 @@ typedef MachineFunction::iterator nodes_iterator; static nodes_iterator nodes_begin(MachineFunction *F) { return F->begin(); } static nodes_iterator nodes_end (MachineFunction *F) { return F->end(); } + static unsigned size (MachineFunction *F) { return F->size(); } }; template <> struct GraphTraits : public GraphTraits { @@ -452,6 +453,9 @@ static nodes_iterator nodes_end (const MachineFunction *F) { return F->end(); } + static unsigned size (const MachineFunction *F) { + return F->size(); + } }; Modified: llvm/trunk/include/llvm/Support/CFG.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Support/CFG.h?rev=145837&r1=145836&r2=145837&view=diff ============================================================================== --- llvm/trunk/include/llvm/Support/CFG.h (original) +++ llvm/trunk/include/llvm/Support/CFG.h Mon Dec 5 13:17:04 2011 @@ -314,6 +314,7 @@ typedef Function::iterator nodes_iterator; static nodes_iterator nodes_begin(Function *F) { return F->begin(); } static nodes_iterator nodes_end (Function *F) { return F->end(); } + static unsigned size (Function *F) { return F->size(); } }; template <> struct GraphTraits : public GraphTraits { @@ -323,6 +324,7 @@ typedef Function::const_iterator nodes_iterator; static nodes_iterator nodes_begin(const Function *F) { return F->begin(); } static nodes_iterator nodes_end (const Function *F) { return F->end(); } + static unsigned size (const Function *F) { return F->size(); } }; From kcc at google.com Mon Dec 5 13:17:53 2011 From: kcc at google.com (Kostya Serebryany) Date: Mon, 05 Dec 2011 19:17:53 -0000 Subject: [llvm-commits] [compiler-rt] r145838 - in /compiler-rt/trunk/lib/asan: asan_allocator.cc asan_interface.h asan_internal.h asan_rtl.cc asan_stats.cc tests/asan_interface_test.cc tests/asan_noinst_test.cc Message-ID: <20111205191753.5C7522A6C12C@llvm.org> Author: kcc Date: Mon Dec 5 13:17:53 2011 New Revision: 145838 URL: http://llvm.org/viewvc/llvm-project?rev=145838&view=rev Log: [asan] always collect malloc statstics (removed FLAG_stats) Modified: compiler-rt/trunk/lib/asan/asan_allocator.cc compiler-rt/trunk/lib/asan/asan_interface.h compiler-rt/trunk/lib/asan/asan_internal.h compiler-rt/trunk/lib/asan/asan_rtl.cc compiler-rt/trunk/lib/asan/asan_stats.cc compiler-rt/trunk/lib/asan/tests/asan_interface_test.cc compiler-rt/trunk/lib/asan/tests/asan_noinst_test.cc Modified: compiler-rt/trunk/lib/asan/asan_allocator.cc URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/lib/asan/asan_allocator.cc?rev=145838&r1=145837&r2=145838&view=diff ============================================================================== --- compiler-rt/trunk/lib/asan/asan_allocator.cc (original) +++ compiler-rt/trunk/lib/asan/asan_allocator.cc Mon Dec 5 13:17:53 2011 @@ -491,13 +491,12 @@ m->next = free_lists_[size_class]; free_lists_[size_class] = m; - if (FLAG_stats) { - AsanStats &thread_stats = asanThreadRegistry().GetCurrentThreadStats(); - thread_stats.real_frees++; - thread_stats.really_freed += m->used_size; - thread_stats.really_freed_redzones += m->Size() - m->used_size; - thread_stats.really_freed_by_size[m->SizeClass()]++; - } + // Statistics. + AsanStats &thread_stats = asanThreadRegistry().GetCurrentThreadStats(); + thread_stats.real_frees++; + thread_stats.really_freed += m->used_size; + thread_stats.really_freed_redzones += m->Size() - m->used_size; + thread_stats.really_freed_by_size[m->SizeClass()]++; } // Get a list of newly allocated chunks. @@ -517,12 +516,13 @@ } CHECK(n_chunks > 0); uint8_t *mem = MmapNewPagesAndPoisonShadow(mmap_size); - if (FLAG_stats) { - AsanStats &thread_stats = asanThreadRegistry().GetCurrentThreadStats(); - thread_stats.mmaps++; - thread_stats.mmaped += mmap_size; - thread_stats.mmaped_by_size[size_class] += n_chunks; - } + + // Statistics. + AsanStats &thread_stats = asanThreadRegistry().GetCurrentThreadStats(); + thread_stats.mmaps++; + thread_stats.mmaped += mmap_size; + thread_stats.mmaped_by_size[size_class] += n_chunks; + AsanChunk *res = NULL; for (size_t i = 0; i < n_chunks; i++) { AsanChunk *m = (AsanChunk*)(mem + i * size); @@ -623,29 +623,24 @@ AsanThread *t = asanThreadRegistry().GetCurrent(); AsanStats &thread_stats = asanThreadRegistry().GetCurrentThreadStats(); - if (FLAG_stats) { - thread_stats.mallocs++; - thread_stats.malloced += size; - thread_stats.malloced_redzones += size_to_allocate - size; - thread_stats.malloced_by_size[size_class]++; - } + // Statistics + thread_stats.mallocs++; + thread_stats.malloced += size; + thread_stats.malloced_redzones += size_to_allocate - size; + thread_stats.malloced_by_size[size_class]++; AsanChunk *m = NULL; if (!t || size_to_allocate >= kMaxSizeForThreadLocalFreeList) { // get directly from global storage. m = malloc_info.AllocateChunks(size_class, 1); - if (FLAG_stats) { - thread_stats.malloc_large++; - } + thread_stats.malloc_large++; } else { // get from the thread-local storage. AsanChunk **fl = &t->malloc_storage().free_lists_[size_class]; if (!*fl) { size_t n_new_chunks = kMaxSizeForThreadLocalFreeList / size_to_allocate; *fl = malloc_info.AllocateChunks(size_class, n_new_chunks); - if (FLAG_stats) { - thread_stats.malloc_small_slow++; - } + thread_stats.malloc_small_slow++; } m = *fl; *fl = (*fl)->next; @@ -714,12 +709,11 @@ size_t rounded_size = RoundUpTo(m->used_size, REDZONE); PoisonShadow((uintptr_t)ptr, rounded_size, kAsanHeapFreeMagic); - if (FLAG_stats) { - AsanStats &thread_stats = asanThreadRegistry().GetCurrentThreadStats(); - thread_stats.frees++; - thread_stats.freed += m->used_size; - thread_stats.freed_by_size[m->SizeClass()]++; - } + // Statistics. + AsanStats &thread_stats = asanThreadRegistry().GetCurrentThreadStats(); + thread_stats.frees++; + thread_stats.freed += m->used_size; + thread_stats.freed_by_size[m->SizeClass()]++; m->chunk_state = CHUNK_QUARANTINE; if (t) { @@ -739,11 +733,12 @@ static uint8_t *Reallocate(uint8_t *old_ptr, size_t new_size, AsanStackTrace *stack) { CHECK(old_ptr && new_size); - if (FLAG_stats) { - AsanStats &thread_stats = asanThreadRegistry().GetCurrentThreadStats(); - thread_stats.reallocs++; - thread_stats.realloced += new_size; - } + + // Statistics. + AsanStats &thread_stats = asanThreadRegistry().GetCurrentThreadStats(); + thread_stats.reallocs++; + thread_stats.realloced += new_size; + AsanChunk *m = PtrToChunk((uintptr_t)old_ptr); CHECK(m->chunk_state == CHUNK_ALLOCATED); size_t old_size = m->used_size; Modified: compiler-rt/trunk/lib/asan/asan_interface.h URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/lib/asan/asan_interface.h?rev=145838&r1=145837&r2=145838&view=diff ============================================================================== --- compiler-rt/trunk/lib/asan/asan_interface.h (original) +++ compiler-rt/trunk/lib/asan/asan_interface.h Mon Dec 5 13:17:53 2011 @@ -126,8 +126,6 @@ // Number of bytes in unmapped pages, that are released to OS. Currently, // always returns 0. size_t __asan_get_unmapped_bytes(); - // Turns on/off statistics update. Returns the previous value. - bool __asan_enable_statistics(bool enable); // Prints accumulated stats to stderr. Used for debugging. void __asan_print_accumulated_stats(); } // namespace Modified: compiler-rt/trunk/lib/asan/asan_internal.h URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/lib/asan/asan_internal.h?rev=145838&r1=145837&r2=145838&view=diff ============================================================================== --- compiler-rt/trunk/lib/asan/asan_internal.h (original) +++ compiler-rt/trunk/lib/asan/asan_internal.h Mon Dec 5 13:17:53 2011 @@ -97,7 +97,6 @@ extern bool FLAG_poison_shadow; extern int FLAG_report_globals; extern size_t FLAG_malloc_context_size; -extern bool FLAG_stats; extern bool FLAG_replace_str; extern bool FLAG_replace_intrin; extern bool FLAG_replace_cfallocator; Modified: compiler-rt/trunk/lib/asan/asan_rtl.cc URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/lib/asan/asan_rtl.cc?rev=145838&r1=145837&r2=145838&view=diff ============================================================================== --- compiler-rt/trunk/lib/asan/asan_rtl.cc (original) +++ compiler-rt/trunk/lib/asan/asan_rtl.cc Mon Dec 5 13:17:53 2011 @@ -73,7 +73,6 @@ bool FLAG_replace_str; bool FLAG_replace_intrin; bool FLAG_replace_cfallocator; // Used on Mac only. -bool FLAG_stats; size_t FLAG_max_malloc_fill_size = 0; bool FLAG_use_fake_stack; int FLAG_exitcode = EXIT_FAILURE; @@ -661,7 +660,6 @@ FLAG_handle_segv = IntFlagValue(options, "handle_segv=", ASAN_NEEDS_SEGV); FLAG_handle_sigill = IntFlagValue(options, "handle_sigill=", 0); - FLAG_stats = IntFlagValue(options, "stats=", 0); FLAG_symbolize = IntFlagValue(options, "symbolize=", 1); FLAG_demangle = IntFlagValue(options, "demangle=", 1); FLAG_debug = IntFlagValue(options, "debug=", 0); Modified: compiler-rt/trunk/lib/asan/asan_stats.cc URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/lib/asan/asan_stats.cc?rev=145838&r1=145837&r2=145838&view=diff ============================================================================== --- compiler-rt/trunk/lib/asan/asan_stats.cc (original) +++ compiler-rt/trunk/lib/asan/asan_stats.cc Mon Dec 5 13:17:53 2011 @@ -56,7 +56,6 @@ static AsanLock print_lock(LINKER_INITIALIZED); static void PrintAccumulatedStats() { - if (!FLAG_stats) return; AsanStats stats = asanThreadRegistry().GetAccumulatedStats(); // Use lock to keep reports from mixing up. ScopedLock lock(&print_lock); @@ -84,12 +83,6 @@ return 0; } -bool __asan_enable_statistics(bool enable) { - bool old_flag = FLAG_stats; - FLAG_stats = enable; - return old_flag; -} - void __asan_print_accumulated_stats() { PrintAccumulatedStats(); } Modified: compiler-rt/trunk/lib/asan/tests/asan_interface_test.cc URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/lib/asan/tests/asan_interface_test.cc?rev=145838&r1=145837&r2=145838&view=diff ============================================================================== --- compiler-rt/trunk/lib/asan/tests/asan_interface_test.cc (original) +++ compiler-rt/trunk/lib/asan/tests/asan_interface_test.cc Mon Dec 5 13:17:53 2011 @@ -63,17 +63,10 @@ delete int_ptr; } -TEST(AddressSanitizerInterface, EnableStatisticsTest) { - bool old_stats_value = __asan_enable_statistics(true); - EXPECT_EQ(true, __asan_enable_statistics(false)); - EXPECT_EQ(false, __asan_enable_statistics(old_stats_value)); -} - TEST(AddressSanitizerInterface, GetCurrentAllocatedBytesTest) { size_t before_malloc, after_malloc, after_free; char *array; const size_t kMallocSize = 100; - bool old_stats_value = __asan_enable_statistics(true); before_malloc = __asan_get_current_allocated_bytes(); array = Ident((char*)malloc(kMallocSize)); @@ -83,14 +76,6 @@ free(array); after_free = __asan_get_current_allocated_bytes(); EXPECT_EQ(before_malloc, after_free); - - __asan_enable_statistics(false); - array = Ident((char*)malloc(kMallocSize)); - after_malloc = __asan_get_current_allocated_bytes(); - EXPECT_EQ(before_malloc, after_malloc); - - free(array); - __asan_enable_statistics(old_stats_value); } static void DoDoubleFree() { @@ -106,7 +91,6 @@ size_t old_heap_size, new_heap_size, heap_growth; // We unlikely have have chunk of this size in free list. static const size_t kLargeMallocSize = 1 << 29; // 512M - __asan_enable_statistics(true); old_heap_size = __asan_get_heap_size(); fprintf(stderr, "allocating %zu bytes:\n", kLargeMallocSize); free(Ident(malloc(kLargeMallocSize))); @@ -136,7 +120,6 @@ static void DoLargeMallocForGetFreeBytesTestAndDie() { size_t old_free_bytes, new_free_bytes; static const size_t kLargeMallocSize = 1 << 29; // 512M - __asan_enable_statistics(true); // If we malloc and free a large memory chunk, it will not fall // into quarantine and will be available for future requests. old_free_bytes = __asan_get_free_bytes(); @@ -156,7 +139,6 @@ char *chunks[kNumOfChunks]; size_t i; size_t old_free_bytes, new_free_bytes; - bool old_stats_value = __asan_enable_statistics(true); // Allocate a small chunk. Now allocator probably has a lot of these // chunks to fulfill future requests. So, future requests will decrease // the number of free bytes. @@ -175,7 +157,6 @@ EXPECT_EQ(old_free_bytes, __asan_get_free_bytes()); } EXPECT_DEATH(DoLargeMallocForGetFreeBytesTestAndDie(), "double-free"); - __asan_enable_statistics(old_stats_value); } static const size_t kManyThreadsMallocSizes[] = {5, 1UL<<10, 1UL<<20, 357}; @@ -194,7 +175,6 @@ TEST(AddressSanitizerInterface, ManyThreadsWithStatsStressTest) { size_t before_test, after_test, i; pthread_t threads[kManyThreadsNumThreads]; - bool old_stats_value = __asan_enable_statistics(true); before_test = __asan_get_current_allocated_bytes(); for (i = 0; i < kManyThreadsNumThreads; i++) { pthread_create(&threads[i], 0, @@ -207,7 +187,6 @@ // ASan stats also reflect memory usage of internal ASan RTL structs, // so we can't check for equality here. EXPECT_LT(after_test, before_test + (1UL<<20)); - __asan_enable_statistics(old_stats_value); } TEST(AddressSanitizerInterface, ExitCode) { Modified: compiler-rt/trunk/lib/asan/tests/asan_noinst_test.cc URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/lib/asan/tests/asan_noinst_test.cc?rev=145838&r1=145837&r2=145838&view=diff ============================================================================== --- compiler-rt/trunk/lib/asan/tests/asan_noinst_test.cc (original) +++ compiler-rt/trunk/lib/asan/tests/asan_noinst_test.cc Mon Dec 5 13:17:53 2011 @@ -290,7 +290,6 @@ // destroyed. TEST(AddressSanitizer, ThreadedQuarantineTest) { const int n_threads = 3000; - bool old_flag_stats = __asan_enable_statistics(true); size_t mmaped1 = __asan_get_heap_size(); for (int i = 0; i < n_threads; i++) { pthread_t t; @@ -299,7 +298,6 @@ size_t mmaped2 = __asan_get_heap_size(); EXPECT_LT(mmaped2 - mmaped1, 320U * (1 << 20)); } - __asan_enable_statistics(old_flag_stats); } void *ThreadedOneSizeMallocStress(void *unused) { From kcc at google.com Mon Dec 5 13:20:57 2011 From: kcc at google.com (Kostya Serebryany) Date: Mon, 05 Dec 2011 19:20:57 -0000 Subject: [llvm-commits] [compiler-rt] r145839 - /compiler-rt/trunk/lib/asan/tests/asan_exceptions_test.cc Message-ID: <20111205192057.DD7562A6C12C@llvm.org> Author: kcc Date: Mon Dec 5 13:20:57 2011 New Revision: 145839 URL: http://llvm.org/viewvc/llvm-project?rev=145839&view=rev Log: [asan] add the test for bug 11468 Added: compiler-rt/trunk/lib/asan/tests/asan_exceptions_test.cc Added: compiler-rt/trunk/lib/asan/tests/asan_exceptions_test.cc URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/lib/asan/tests/asan_exceptions_test.cc?rev=145839&view=auto ============================================================================== --- compiler-rt/trunk/lib/asan/tests/asan_exceptions_test.cc (added) +++ compiler-rt/trunk/lib/asan/tests/asan_exceptions_test.cc Mon Dec 5 13:20:57 2011 @@ -0,0 +1,27 @@ +// See http://llvm.org/bugs/show_bug.cgi?id=11468 +#include +#include + +class Action { + public: + Action() {} + void PrintString(const std::string& msg) const { + fprintf(stderr, "%s\n", msg.c_str()); + } + void Throw(const char& arg) const { + PrintString("PrintString called!"); // this line is important + throw arg; + } +}; + +int main() { + const Action a; + fprintf(stderr, "&a before = %p\n", &a); + try { + a.Throw('c'); + } catch (const char&) { + fprintf(stderr, "&a in catch = %p\n", &a); + } + fprintf(stderr, "&a final = %p\n", &a); + return 0; +} From grosbach at apple.com Mon Dec 5 13:55:46 2011 From: grosbach at apple.com (Jim Grosbach) Date: Mon, 05 Dec 2011 19:55:46 -0000 Subject: [llvm-commits] [llvm] r145842 - in /llvm/trunk/lib/Target/ARM: ARMInstrFormats.td ARMInstrNEON.td Message-ID: <20111205195546.DFAE62A6C12C@llvm.org> Author: grosbach Date: Mon Dec 5 13:55:46 2011 New Revision: 145842 URL: http://llvm.org/viewvc/llvm-project?rev=145842&view=rev Log: ARM assmebler parsing for two-operand VMUL instructions. Combined destination and first source operand for f32 variant of the VMUL (by scalar) instruction. rdar://10522016 Modified: llvm/trunk/lib/Target/ARM/ARMInstrFormats.td llvm/trunk/lib/Target/ARM/ARMInstrNEON.td Modified: llvm/trunk/lib/Target/ARM/ARMInstrFormats.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrFormats.td?rev=145842&r1=145841&r2=145842&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrFormats.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrFormats.td Mon Dec 5 13:55:46 2011 @@ -231,6 +231,8 @@ : InstAlias, Requires<[HasVFP2]>; class VFP3InstAlias : InstAlias, Requires<[HasVFP3]>; +class NEONInstAlias + : InstAlias, Requires<[HasNEON]>; //===----------------------------------------------------------------------===// // ARM Instruction templates. Modified: llvm/trunk/lib/Target/ARM/ARMInstrNEON.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrNEON.td?rev=145842&r1=145841&r2=145842&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrNEON.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrNEON.td Mon Dec 5 13:55:46 2011 @@ -3672,6 +3672,15 @@ def VMULslfq : N3VQSL<0b10, 0b1001, IIC_VBINQ, "vmul", "f32", v4f32, v2f32, fmul>; +// Two-operand aliases. +def : NEONInstAlias<"vmul${p}.f32 $Ddn $Dm$lane", + (VMULslfd DPR:$Ddn, DPR:$Ddn, DPR_VFP2:$Dm, + VectorIndex32:$lane, pred:$p)>; +def : NEONInstAlias<"vmul${p}.f32 $Qdn $Dm$lane", + (VMULslfq QPR:$Qdn, QPR:$Qdn, DPR_VFP2:$Dm, + VectorIndex32:$lane, pred:$p)>; + + def : Pat<(v8i16 (mul (v8i16 QPR:$src1), (v8i16 (NEONvduplane (v8i16 QPR:$src2), imm:$lane)))), (v8i16 (VMULslv8i16 (v8i16 QPR:$src1), From mcrosier at apple.com Mon Dec 5 14:06:57 2011 From: mcrosier at apple.com (Chad Rosier) Date: Mon, 05 Dec 2011 12:06:57 -0800 Subject: [llvm-commits] [llvm] r145842 - in /llvm/trunk/lib/Target/ARM: ARMInstrFormats.td ARMInstrNEON.td In-Reply-To: <20111205195546.DFAE62A6C12C@llvm.org> References: <20111205195546.DFAE62A6C12C@llvm.org> Message-ID: <17B2F12B-75C4-4F4B-A1F3-6861DEEAE6A3@apple.com> Test case? Chad On Dec 5, 2011, at 11:55 AM, Jim Grosbach wrote: > Author: grosbach > Date: Mon Dec 5 13:55:46 2011 > New Revision: 145842 > > URL: http://llvm.org/viewvc/llvm-project?rev=145842&view=rev > Log: > ARM assmebler parsing for two-operand VMUL instructions. > > Combined destination and first source operand for f32 variant of the VMUL > (by scalar) instruction. > > rdar://10522016 > > Modified: > llvm/trunk/lib/Target/ARM/ARMInstrFormats.td > llvm/trunk/lib/Target/ARM/ARMInstrNEON.td > > Modified: llvm/trunk/lib/Target/ARM/ARMInstrFormats.td > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrFormats.td?rev=145842&r1=145841&r2=145842&view=diff > ============================================================================== > --- llvm/trunk/lib/Target/ARM/ARMInstrFormats.td (original) > +++ llvm/trunk/lib/Target/ARM/ARMInstrFormats.td Mon Dec 5 13:55:46 2011 > @@ -231,6 +231,8 @@ > : InstAlias, Requires<[HasVFP2]>; > class VFP3InstAlias > : InstAlias, Requires<[HasVFP3]>; > +class NEONInstAlias > + : InstAlias, Requires<[HasNEON]>; > > //===----------------------------------------------------------------------===// > // ARM Instruction templates. > > Modified: llvm/trunk/lib/Target/ARM/ARMInstrNEON.td > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrNEON.td?rev=145842&r1=145841&r2=145842&view=diff > ============================================================================== > --- llvm/trunk/lib/Target/ARM/ARMInstrNEON.td (original) > +++ llvm/trunk/lib/Target/ARM/ARMInstrNEON.td Mon Dec 5 13:55:46 2011 > @@ -3672,6 +3672,15 @@ > def VMULslfq : N3VQSL<0b10, 0b1001, IIC_VBINQ, "vmul", "f32", v4f32, > v2f32, fmul>; > > +// Two-operand aliases. > +def : NEONInstAlias<"vmul${p}.f32 $Ddn $Dm$lane", > + (VMULslfd DPR:$Ddn, DPR:$Ddn, DPR_VFP2:$Dm, > + VectorIndex32:$lane, pred:$p)>; > +def : NEONInstAlias<"vmul${p}.f32 $Qdn $Dm$lane", > + (VMULslfq QPR:$Qdn, QPR:$Qdn, DPR_VFP2:$Dm, > + VectorIndex32:$lane, pred:$p)>; > + > + > def : Pat<(v8i16 (mul (v8i16 QPR:$src1), > (v8i16 (NEONvduplane (v8i16 QPR:$src2), imm:$lane)))), > (v8i16 (VMULslv8i16 (v8i16 QPR:$src1), > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From ganna at apple.com Mon Dec 5 14:08:59 2011 From: ganna at apple.com (Anna Zaks) Date: Mon, 05 Dec 2011 12:08:59 -0800 Subject: [llvm-commits] Refactoring of the dominator tree implementation for Clang In-Reply-To: <4B9E5CDC-1444-40F3-8D79-AB84BA475EE4@2pi.dk> References: <5075B012-08E8-49D9-B6AD-419A774FB06E@2pi.dk> <4B9E5CDC-1444-40F3-8D79-AB84BA475EE4@2pi.dk> Message-ID: Guoping, LLVM part of the patch is committed in r145837. Anna. On Nov 30, 2011, at 8:40 PM, Jakob Stoklund Olesen wrote: > > On Nov 30, 2011, at 7:56 PM, Guoping Long wrote: > >> Hi, Jakob >> >> Thanks for your comments. Attached is the revised patch. > > Looks good to me. > > I'll leave the clang stuff to Anna. > > /jakob > From grosbach at apple.com Mon Dec 5 14:09:45 2011 From: grosbach at apple.com (Jim Grosbach) Date: Mon, 05 Dec 2011 20:09:45 -0000 Subject: [llvm-commits] [llvm] r145843 - /llvm/trunk/lib/Target/ARM/ARMInstrNEON.td Message-ID: <20111205200945.2E4062A6C12C@llvm.org> Author: grosbach Date: Mon Dec 5 14:09:44 2011 New Revision: 145843 URL: http://llvm.org/viewvc/llvm-project?rev=145843&view=rev Log: Tidy up. No functional change. Modified: llvm/trunk/lib/Target/ARM/ARMInstrNEON.td Modified: llvm/trunk/lib/Target/ARM/ARMInstrNEON.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrNEON.td?rev=145843&r1=145842&r2=145843&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrNEON.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrNEON.td Mon Dec 5 14:09:44 2011 @@ -2898,14 +2898,11 @@ v4i32, v4i32, OpNode, Commutable>; } -multiclass N3VSL_HS op11_8, string OpcodeStr, string Dt, SDNode ShOp> { - def v4i16 : N3VDSL16<0b01, op11_8, OpcodeStr, !strconcat(Dt, "16"), - v4i16, ShOp>; - def v2i32 : N3VDSL<0b10, op11_8, IIC_VMULi32D, OpcodeStr, !strconcat(Dt,"32"), - v2i32, ShOp>; - def v8i16 : N3VQSL16<0b01, op11_8, OpcodeStr, !strconcat(Dt, "16"), - v8i16, v4i16, ShOp>; - def v4i32 : N3VQSL<0b10, op11_8, IIC_VMULi32Q, OpcodeStr, !strconcat(Dt,"32"), +multiclass N3VSL_HS op11_8, string OpcodeStr, SDNode ShOp> { + def v4i16 : N3VDSL16<0b01, op11_8, OpcodeStr, "16", v4i16, ShOp>; + def v2i32 : N3VDSL<0b10, op11_8, IIC_VMULi32D, OpcodeStr, "32", v2i32, ShOp>; + def v8i16 : N3VQSL16<0b01, op11_8, OpcodeStr, "i16", v8i16, v4i16, ShOp>; + def v4i32 : N3VQSL<0b10, op11_8, IIC_VMULi32Q, OpcodeStr, "32", v4i32, v2i32, ShOp>; } @@ -3667,7 +3664,7 @@ v2f32, v2f32, fmul, 1>; def VMULfq : N3VQ<1, 0, 0b00, 0b1101, 1, IIC_VFMULQ, "vmul", "f32", v4f32, v4f32, fmul, 1>; -defm VMULsl : N3VSL_HS<0b1000, "vmul", "i", mul>; +defm VMULsl : N3VSL_HS<0b1000, "vmul", mul>; def VMULslfd : N3VDSL<0b10, 0b1001, IIC_VBIND, "vmul", "f32", v2f32, fmul>; def VMULslfq : N3VQSL<0b10, 0b1001, IIC_VBINQ, "vmul", "f32", v4f32, v2f32, fmul>; From grosbach at apple.com Mon Dec 5 14:12:26 2011 From: grosbach at apple.com (Jim Grosbach) Date: Mon, 05 Dec 2011 20:12:26 -0000 Subject: [llvm-commits] [llvm] r145844 - /llvm/trunk/lib/Target/ARM/ARMInstrNEON.td Message-ID: <20111205201226.D44E72A6C12D@llvm.org> Author: grosbach Date: Mon Dec 5 14:12:26 2011 New Revision: 145844 URL: http://llvm.org/viewvc/llvm-project?rev=145844&view=rev Log: Fix previous commit. Oops. Modified: llvm/trunk/lib/Target/ARM/ARMInstrNEON.td Modified: llvm/trunk/lib/Target/ARM/ARMInstrNEON.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrNEON.td?rev=145844&r1=145843&r2=145844&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrNEON.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrNEON.td Mon Dec 5 14:12:26 2011 @@ -2899,10 +2899,10 @@ } multiclass N3VSL_HS op11_8, string OpcodeStr, SDNode ShOp> { - def v4i16 : N3VDSL16<0b01, op11_8, OpcodeStr, "16", v4i16, ShOp>; - def v2i32 : N3VDSL<0b10, op11_8, IIC_VMULi32D, OpcodeStr, "32", v2i32, ShOp>; + def v4i16 : N3VDSL16<0b01, op11_8, OpcodeStr, "i16", v4i16, ShOp>; + def v2i32 : N3VDSL<0b10, op11_8, IIC_VMULi32D, OpcodeStr, "i32", v2i32, ShOp>; def v8i16 : N3VQSL16<0b01, op11_8, OpcodeStr, "i16", v8i16, v4i16, ShOp>; - def v4i32 : N3VQSL<0b10, op11_8, IIC_VMULi32Q, OpcodeStr, "32", + def v4i32 : N3VQSL<0b10, op11_8, IIC_VMULi32Q, OpcodeStr, "i32", v4i32, v2i32, ShOp>; } From grosbach at apple.com Mon Dec 5 14:29:59 2011 From: grosbach at apple.com (Jim Grosbach) Date: Mon, 05 Dec 2011 20:29:59 -0000 Subject: [llvm-commits] [llvm] r145846 - in /llvm/trunk: lib/Target/ARM/ARMInstrFormats.td lib/Target/ARM/ARMInstrNEON.td test/MC/ARM/neon-mul-encoding.s Message-ID: <20111205202959.E976F2A6C12C@llvm.org> Author: grosbach Date: Mon Dec 5 14:29:59 2011 New Revision: 145846 URL: http://llvm.org/viewvc/llvm-project?rev=145846&view=rev Log: ARM assembly parsing for the rest of the VMUL data type aliases. Finish up rdar://10522016. Modified: llvm/trunk/lib/Target/ARM/ARMInstrFormats.td llvm/trunk/lib/Target/ARM/ARMInstrNEON.td llvm/trunk/test/MC/ARM/neon-mul-encoding.s Modified: llvm/trunk/lib/Target/ARM/ARMInstrFormats.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrFormats.td?rev=145846&r1=145845&r2=145846&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrFormats.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrFormats.td Mon Dec 5 14:29:59 2011 @@ -1996,7 +1996,7 @@ // VFP/NEON Instruction aliases for type suffices. class VFPDataTypeInstAlias : - InstAlias; + InstAlias, Requires<[HasVFP2]>; multiclass VFPDT8ReqInstAlias { def I8 : VFPDataTypeInstAlias; def S8 : VFPDataTypeInstAlias; Modified: llvm/trunk/lib/Target/ARM/ARMInstrNEON.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrNEON.td?rev=145846&r1=145845&r2=145846&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrNEON.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrNEON.td Mon Dec 5 14:29:59 2011 @@ -3669,15 +3669,6 @@ def VMULslfq : N3VQSL<0b10, 0b1001, IIC_VBINQ, "vmul", "f32", v4f32, v2f32, fmul>; -// Two-operand aliases. -def : NEONInstAlias<"vmul${p}.f32 $Ddn $Dm$lane", - (VMULslfd DPR:$Ddn, DPR:$Ddn, DPR_VFP2:$Dm, - VectorIndex32:$lane, pred:$p)>; -def : NEONInstAlias<"vmul${p}.f32 $Qdn $Dm$lane", - (VMULslfq QPR:$Qdn, QPR:$Qdn, DPR_VFP2:$Dm, - VectorIndex32:$lane, pred:$p)>; - - def : Pat<(v8i16 (mul (v8i16 QPR:$src1), (v8i16 (NEONvduplane (v8i16 QPR:$src2), imm:$lane)))), (v8i16 (VMULslv8i16 (v8i16 QPR:$src1), @@ -5620,6 +5611,79 @@ defm VEXTq : VFPDT64ReqInstAlias<"vext${p}", "$Vd, $Vn, $Vm, $index", (VEXTq64 QPR:$Vd, QPR:$Vn, QPR:$Vm, imm0_1:$index, pred:$p)>; +// VMUL instructions data type suffix aliases for more-specific types. +def : NEONInstAlias<"vmul${p}.s16 $Dd, $Dn $Dm$lane", + (VMULslv4i16 DPR:$Dd, DPR:$Dn, DPR_8:$Dm, + VectorIndex16:$lane, pred:$p)>; +def : NEONInstAlias<"vmul${p}.s16 $Qd, $Qn, $Dm$lane", + (VMULslv8i16 QPR:$Qd, QPR:$Qn, DPR_8:$Dm, + VectorIndex16:$lane, pred:$p)>; +def : NEONInstAlias<"vmul${p}.u16 $Dd, $Dn $Dm$lane", + (VMULslv4i16 DPR:$Dd, DPR:$Dn, DPR_8:$Dm, + VectorIndex16:$lane, pred:$p)>; +def : NEONInstAlias<"vmul${p}.u16 $Qd, $Qn, $Dm$lane", + (VMULslv8i16 QPR:$Qd, QPR:$Qn, DPR_8:$Dm, + VectorIndex16:$lane, pred:$p)>; + +def : NEONInstAlias<"vmul${p}.s32 $Dd, $Dn $Dm$lane", + (VMULslv2i32 DPR:$Dd, DPR:$Dn, DPR_VFP2:$Dm, + VectorIndex32:$lane, pred:$p)>; +def : NEONInstAlias<"vmul${p}.s32 $Qd, $Qn, $Dm$lane", + (VMULslv4i32 QPR:$Qd, QPR:$Qn, DPR_VFP2:$Dm, + VectorIndex32:$lane, pred:$p)>; +def : NEONInstAlias<"vmul${p}.u32 $Dd, $Dn $Dm$lane", + (VMULslv2i32 DPR:$Dd, DPR:$Dn, DPR_VFP2:$Dm, + VectorIndex32:$lane, pred:$p)>; +def : NEONInstAlias<"vmul${p}.u32 $Qd, $Qn, $Dm$lane", + (VMULslv4i32 QPR:$Qd, QPR:$Qn, DPR_VFP2:$Dm, + VectorIndex32:$lane, pred:$p)>; + +// VMUL two-operand aliases. +def : NEONInstAlias<"vmul${p}.i16 $Ddn, $Dm$lane", + (VMULslv4i16 DPR:$Ddn, DPR:$Ddn, DPR_8:$Dm, + VectorIndex16:$lane, pred:$p)>; +def : NEONInstAlias<"vmul${p}.i16 $Qdn, $Dm$lane", + (VMULslv8i16 QPR:$Qdn, QPR:$Qdn, DPR_8:$Dm, + VectorIndex16:$lane, pred:$p)>; +def : NEONInstAlias<"vmul${p}.s16 $Ddn, $Dm$lane", + (VMULslv4i16 DPR:$Ddn, DPR:$Ddn, DPR_8:$Dm, + VectorIndex16:$lane, pred:$p)>; +def : NEONInstAlias<"vmul${p}.s16 $Qdn, $Dm$lane", + (VMULslv8i16 QPR:$Qdn, QPR:$Qdn, DPR_8:$Dm, + VectorIndex16:$lane, pred:$p)>; +def : NEONInstAlias<"vmul${p}.u16 $Ddn, $Dm$lane", + (VMULslv4i16 DPR:$Ddn, DPR:$Ddn, DPR_8:$Dm, + VectorIndex16:$lane, pred:$p)>; +def : NEONInstAlias<"vmul${p}.u16 $Qdn, $Dm$lane", + (VMULslv8i16 QPR:$Qdn, QPR:$Qdn, DPR_8:$Dm, + VectorIndex16:$lane, pred:$p)>; + +def : NEONInstAlias<"vmul${p}.i32 $Ddn, $Dm$lane", + (VMULslv2i32 DPR:$Ddn, DPR:$Ddn, DPR_VFP2:$Dm, + VectorIndex32:$lane, pred:$p)>; +def : NEONInstAlias<"vmul${p}.i32 $Qdn, $Dm$lane", + (VMULslv4i32 QPR:$Qdn, QPR:$Qdn, DPR_VFP2:$Dm, + VectorIndex32:$lane, pred:$p)>; +def : NEONInstAlias<"vmul${p}.s32 $Ddn, $Dm$lane", + (VMULslv2i32 DPR:$Ddn, DPR:$Ddn, DPR_VFP2:$Dm, + VectorIndex32:$lane, pred:$p)>; +def : NEONInstAlias<"vmul${p}.s32 $Qdn, $Dm$lane", + (VMULslv4i32 QPR:$Qdn, QPR:$Qdn, DPR_VFP2:$Dm, + VectorIndex32:$lane, pred:$p)>; +def : NEONInstAlias<"vmul${p}.u32 $Ddn, $Dm$lane", + (VMULslv2i32 DPR:$Ddn, DPR:$Ddn, DPR_VFP2:$Dm, + VectorIndex32:$lane, pred:$p)>; +def : NEONInstAlias<"vmul${p}.u32 $Qdn, $Dm$lane", + (VMULslv4i32 QPR:$Qdn, QPR:$Qdn, DPR_VFP2:$Dm, + VectorIndex32:$lane, pred:$p)>; + +def : NEONInstAlias<"vmul${p}.f32 $Ddn, $Dm$lane", + (VMULslfd DPR:$Ddn, DPR:$Ddn, DPR_VFP2:$Dm, + VectorIndex32:$lane, pred:$p)>; +def : NEONInstAlias<"vmul${p}.f32 $Qdn, $Dm$lane", + (VMULslfq QPR:$Qdn, QPR:$Qdn, DPR_VFP2:$Dm, + VectorIndex32:$lane, pred:$p)>; + // VLD1 single-lane pseudo-instructions. These need special handling for // the lane index that an InstAlias can't handle, so we use these instead. defm VLD1LNdAsm : NEONDT8AsmPseudoInst<"vld1${p}", "$list, $addr", Modified: llvm/trunk/test/MC/ARM/neon-mul-encoding.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/neon-mul-encoding.s?rev=145846&r1=145845&r2=145846&view=diff ============================================================================== --- llvm/trunk/test/MC/ARM/neon-mul-encoding.s (original) +++ llvm/trunk/test/MC/ARM/neon-mul-encoding.s Mon Dec 5 14:29:59 2011 @@ -72,3 +72,68 @@ @ CHECK: vqdmull.s16 q8, d16, d17 @ encoding: [0xa1,0x0d,0xd0,0xf2] @ CHECK: vqdmull.s32 q8, d16, d17 @ encoding: [0xa1,0x0d,0xe0,0xf2] + + + vmul.i16 d0, d4[2] + vmul.s16 d1, d7[3] + vmul.u16 d2, d1[1] + vmul.i32 d3, d2[0] + vmul.s32 d4, d3[1] + vmul.u32 d5, d4[0] + vmul.f32 d6, d5[1] + + vmul.i16 q0, d4[2] + vmul.s16 q1, d7[3] + vmul.u16 q2, d1[1] + vmul.i32 q3, d2[0] + vmul.s32 q4, d3[1] + vmul.u32 q5, d4[0] + vmul.f32 q6, d5[1] + + vmul.i16 d9, d0, d4[2] + vmul.s16 d8, d1, d7[3] + vmul.u16 d7, d2, d1[1] + vmul.i32 d6, d3, d2[0] + vmul.s32 d5, d4, d3[1] + vmul.u32 d4, d5, d4[0] + vmul.f32 d3, d6, d5[1] + + vmul.i16 q9, q0, d4[2] + vmul.s16 q8, q1, d7[3] + vmul.u16 q7, q2, d1[1] + vmul.i32 q6, q3, d2[0] + vmul.s32 q5, q4, d3[1] + vmul.u32 q4, q5, d4[0] + vmul.f32 q3, q6, d5[1] + +@ CHECK: vmul.i16 d0, d0, d4[2] @ encoding: [0x64,0x08,0x90,0xf2] +@ CHECK: vmul.i16 d1, d1, d7[3] @ encoding: [0x6f,0x18,0x91,0xf2] +@ CHECK: vmul.i16 d2, d2, d1[1] @ encoding: [0x49,0x28,0x92,0xf2] +@ CHECK: vmul.i32 d3, d3, d2[0] @ encoding: [0x42,0x38,0xa3,0xf2] +@ CHECK: vmul.i32 d4, d4, d3[1] @ encoding: [0x63,0x48,0xa4,0xf2] +@ CHECK: vmul.i32 d5, d5, d4[0] @ encoding: [0x44,0x58,0xa5,0xf2] +@ CHECK: vmul.f32 d6, d6, d5[1] @ encoding: [0x65,0x69,0xa6,0xf2] + +@ CHECK: vmul.i16 q0, q0, d4[2] @ encoding: [0x64,0x08,0x90,0xf3] +@ CHECK: vmul.i16 q1, q1, d7[3] @ encoding: [0x6f,0x28,0x92,0xf3] +@ CHECK: vmul.i16 q2, q2, d1[1] @ encoding: [0x49,0x48,0x94,0xf3] +@ CHECK: vmul.i32 q3, q3, d2[0] @ encoding: [0x42,0x68,0xa6,0xf3] +@ CHECK: vmul.i32 q4, q4, d3[1] @ encoding: [0x63,0x88,0xa8,0xf3] +@ CHECK: vmul.i32 q5, q5, d4[0] @ encoding: [0x44,0xa8,0xaa,0xf3] +@ CHECK: vmul.f32 q6, q6, d5[1] @ encoding: [0x65,0xc9,0xac,0xf3] + +@ CHECK: vmul.i16 d9, d0, d4[2] @ encoding: [0x64,0x98,0x90,0xf2] +@ CHECK: vmul.i16 d8, d1, d7[3] @ encoding: [0x6f,0x88,0x91,0xf2] +@ CHECK: vmul.i16 d7, d2, d1[1] @ encoding: [0x49,0x78,0x92,0xf2] +@ CHECK: vmul.i32 d6, d3, d2[0] @ encoding: [0x42,0x68,0xa3,0xf2] +@ CHECK: vmul.i32 d5, d4, d3[1] @ encoding: [0x63,0x58,0xa4,0xf2] +@ CHECK: vmul.i32 d4, d5, d4[0] @ encoding: [0x44,0x48,0xa5,0xf2] +@ CHECK: vmul.f32 d3, d6, d5[1] @ encoding: [0x65,0x39,0xa6,0xf2] + +@ CHECK: vmul.i16 q9, q0, d4[2] @ encoding: [0x64,0x28,0xd0,0xf3] +@ CHECK: vmul.i16 q8, q1, d7[3] @ encoding: [0x6f,0x08,0xd2,0xf3] +@ CHECK: vmul.i16 q7, q2, d1[1] @ encoding: [0x49,0xe8,0x94,0xf3] +@ CHECK: vmul.i32 q6, q3, d2[0] @ encoding: [0x42,0xc8,0xa6,0xf3] +@ CHECK: vmul.i32 q5, q4, d3[1] @ encoding: [0x63,0xa8,0xa8,0xf3] +@ CHECK: vmul.i32 q4, q5, d4[0] @ encoding: [0x44,0x88,0xaa,0xf3] +@ CHECK: vmul.f32 q3, q6, d5[1] @ encoding: [0x65,0x69,0xac,0xf3] From grosbach at apple.com Mon Dec 5 14:33:33 2011 From: grosbach at apple.com (Jim Grosbach) Date: Mon, 05 Dec 2011 12:33:33 -0800 Subject: [llvm-commits] [llvm] r145842 - in /llvm/trunk/lib/Target/ARM: ARMInstrFormats.td ARMInstrNEON.td In-Reply-To: <8E1D7282-652A-4DEF-90DF-2E01BF1CDF45@apple.com> References: <20111205195546.DFAE62A6C12C@llvm.org> <17B2F12B-75C4-4F4B-A1F3-6861DEEAE6A3@apple.com> <8E1D7282-652A-4DEF-90DF-2E01BF1CDF45@apple.com> Message-ID: Tests for these along w/ the rest of the aliases in r145846. Thanks for checking! -jim On Dec 5, 2011, at 12:12 PM, Chad Rosier wrote: > 10-4. > > On Dec 5, 2011, at 12:10 PM, Jim Grosbach wrote: > >> Forthcoming, along with a few other variants of this same instruction class. >> >> On Dec 5, 2011, at 12:06 PM, Chad Rosier wrote: >> >>> Test case? >>> >>> Chad >>> >>> On Dec 5, 2011, at 11:55 AM, Jim Grosbach wrote: >>> >>>> Author: grosbach >>>> Date: Mon Dec 5 13:55:46 2011 >>>> New Revision: 145842 >>>> >>>> URL: http://llvm.org/viewvc/llvm-project?rev=145842&view=rev >>>> Log: >>>> ARM assmebler parsing for two-operand VMUL instructions. >>>> >>>> Combined destination and first source operand for f32 variant of the VMUL >>>> (by scalar) instruction. >>>> >>>> rdar://10522016 >>>> >>>> Modified: >>>> llvm/trunk/lib/Target/ARM/ARMInstrFormats.td >>>> llvm/trunk/lib/Target/ARM/ARMInstrNEON.td >>>> >>>> Modified: llvm/trunk/lib/Target/ARM/ARMInstrFormats.td >>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrFormats.td?rev=145842&r1=145841&r2=145842&view=diff >>>> ============================================================================== >>>> --- llvm/trunk/lib/Target/ARM/ARMInstrFormats.td (original) >>>> +++ llvm/trunk/lib/Target/ARM/ARMInstrFormats.td Mon Dec 5 13:55:46 2011 >>>> @@ -231,6 +231,8 @@ >>>> : InstAlias, Requires<[HasVFP2]>; >>>> class VFP3InstAlias >>>> : InstAlias, Requires<[HasVFP3]>; >>>> +class NEONInstAlias >>>> + : InstAlias, Requires<[HasNEON]>; >>>> >>>> //===----------------------------------------------------------------------===// >>>> // ARM Instruction templates. >>>> >>>> Modified: llvm/trunk/lib/Target/ARM/ARMInstrNEON.td >>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrNEON.td?rev=145842&r1=145841&r2=145842&view=diff >>>> ============================================================================== >>>> --- llvm/trunk/lib/Target/ARM/ARMInstrNEON.td (original) >>>> +++ llvm/trunk/lib/Target/ARM/ARMInstrNEON.td Mon Dec 5 13:55:46 2011 >>>> @@ -3672,6 +3672,15 @@ >>>> def VMULslfq : N3VQSL<0b10, 0b1001, IIC_VBINQ, "vmul", "f32", v4f32, >>>> v2f32, fmul>; >>>> >>>> +// Two-operand aliases. >>>> +def : NEONInstAlias<"vmul${p}.f32 $Ddn $Dm$lane", >>>> + (VMULslfd DPR:$Ddn, DPR:$Ddn, DPR_VFP2:$Dm, >>>> + VectorIndex32:$lane, pred:$p)>; >>>> +def : NEONInstAlias<"vmul${p}.f32 $Qdn $Dm$lane", >>>> + (VMULslfq QPR:$Qdn, QPR:$Qdn, DPR_VFP2:$Dm, >>>> + VectorIndex32:$lane, pred:$p)>; >>>> + >>>> + >>>> def : Pat<(v8i16 (mul (v8i16 QPR:$src1), >>>> (v8i16 (NEONvduplane (v8i16 QPR:$src2), imm:$lane)))), >>>> (v8i16 (VMULslv8i16 (v8i16 QPR:$src1), >>>> >>>> >>>> _______________________________________________ >>>> llvm-commits mailing list >>>> llvm-commits at cs.uiuc.edu >>>> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits >>> >> > From benny.kra at googlemail.com Mon Dec 5 14:33:47 2011 From: benny.kra at googlemail.com (Benjamin Kramer) Date: Mon, 05 Dec 2011 20:33:47 -0000 Subject: [llvm-commits] [www-pubs] r145847 - /www-pubs/trunk/2009-01-PEPM-Parfait.html Message-ID: <20111205203347.577C22A6C12C@llvm.org> Author: d0k Date: Mon Dec 5 14:33:47 2011 New Revision: 145847 URL: http://llvm.org/viewvc/llvm-project?rev=145847&view=rev Log: Fix bad markup. Modified: www-pubs/trunk/2009-01-PEPM-Parfait.html Modified: www-pubs/trunk/2009-01-PEPM-Parfait.html URL: http://llvm.org/viewvc/llvm-project/www-pubs/trunk/2009-01-PEPM-Parfait.html?rev=145847&r1=145846&r2=145847&view=diff ============================================================================== --- www-pubs/trunk/2009-01-PEPM-Parfait.html (original) +++ www-pubs/trunk/2009-01-PEPM-Parfait.html Mon Dec 5 14:33:47 2011 @@ -3,7 +3,7 @@ - Program analysis for bug detection using Parfait<title> + <title>Program analysis for bug detection using Parfait From kcc at google.com Mon Dec 5 14:44:30 2011 From: kcc at google.com (Kostya Serebryany) Date: Mon, 05 Dec 2011 20:44:30 -0000 Subject: [llvm-commits] [compiler-rt] r145848 - in /compiler-rt/trunk/lib/asan: Makefile.old tests/asan_exceptions_test.cc tests/test_output.sh Message-ID: <20111205204430.564FD2A6C12C@llvm.org> Author: kcc Date: Mon Dec 5 14:44:30 2011 New Revision: 145848 URL: http://llvm.org/viewvc/llvm-project?rev=145848&view=rev Log: [asan]: test a pure C file with -faddress-sanitizer; lint fixes Modified: compiler-rt/trunk/lib/asan/Makefile.old compiler-rt/trunk/lib/asan/tests/asan_exceptions_test.cc compiler-rt/trunk/lib/asan/tests/test_output.sh Modified: compiler-rt/trunk/lib/asan/Makefile.old URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/lib/asan/Makefile.old?rev=145848&r1=145847&r2=145848&view=diff ============================================================================== --- compiler-rt/trunk/lib/asan/Makefile.old (original) +++ compiler-rt/trunk/lib/asan/Makefile.old Mon Dec 5 14:44:30 2011 @@ -210,7 +210,7 @@ test: t64 t32 output_tests lint output_tests: b32 b64 - cd tests && ./test_output.sh $(CLANG_CXX) + cd tests && ./test_output.sh $(CLANG_CXX) $(CLANG_CC) t64: b64 $(BIN)/asan_test64 Modified: compiler-rt/trunk/lib/asan/tests/asan_exceptions_test.cc URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/lib/asan/tests/asan_exceptions_test.cc?rev=145848&r1=145847&r2=145848&view=diff ============================================================================== --- compiler-rt/trunk/lib/asan/tests/asan_exceptions_test.cc (original) +++ compiler-rt/trunk/lib/asan/tests/asan_exceptions_test.cc Mon Dec 5 14:44:30 2011 @@ -9,7 +9,7 @@ fprintf(stderr, "%s\n", msg.c_str()); } void Throw(const char& arg) const { - PrintString("PrintString called!"); // this line is important + PrintString("PrintString called!"); // this line is important throw arg; } }; @@ -19,7 +19,7 @@ fprintf(stderr, "&a before = %p\n", &a); try { a.Throw('c'); - } catch (const char&) { + } catch(const char&) { fprintf(stderr, "&a in catch = %p\n", &a); } fprintf(stderr, "&a final = %p\n", &a); Modified: compiler-rt/trunk/lib/asan/tests/test_output.sh URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/lib/asan/tests/test_output.sh?rev=145848&r1=145847&r2=145848&view=diff ============================================================================== --- compiler-rt/trunk/lib/asan/tests/test_output.sh (original) +++ compiler-rt/trunk/lib/asan/tests/test_output.sh Mon Dec 5 14:44:30 2011 @@ -2,9 +2,16 @@ OS=`uname` CXX=$1 +CC=$2 CXXFLAGS="-mno-omit-leaf-frame-pointer" SYMBOLIZER=../scripts/asan_symbolize.py +C_TEST=use-after-free +$CC -g -faddress-sanitizer -O2 $C_TEST.c || exit 1 +echo "Sanity checking a test in pure C" +./a.out 2>&1 | grep "heap-use-after-free" > /dev/null || exit 1 +rm ./a.out + for t in *.tmpl; do for b in 32 64; do for O in 0 1 2 3; do @@ -29,4 +36,5 @@ done done done + exit 0 From hfinkel at anl.gov Mon Dec 5 14:56:41 2011 From: hfinkel at anl.gov (Hal Finkel) Date: Mon, 05 Dec 2011 14:56:41 -0600 Subject: [llvm-commits] Dead register (was Re: [llvm] r145819) In-Reply-To: <1323112465.2507.3170.camel@sapling> References: <20111205175518.343FF2A6C12C@llvm.org> <1323112465.2507.3170.camel@sapling> Message-ID: <1323118601.2507.3183.camel@sapling> RegScavenger is complaining about use of an undefined register, CTR8, in the BCTR8 instruction, in the following instance (this is from the PPC backend): BB#38: derived from LLVM BB %for.end50 Predecessors according to CFG: BB#36 %X3 = LD 0, ; mem:LD8[FixedStack27] %X4 = RLDICR %X3, 3, 60 %X5 = LI8 [TF=4] %X5 = ADDIS8 %X5, [TF=8] %X4 = LDX %X4, %X5; mem:LD8[JumpTable] MTCTR8 %X4, %CTR8 BCTR8 %CTR8, %RM Successors according to CFG: BB#23 BB#15 BB#7 BB#8 BB#9 BB#10 BB#11 BB#25 BB#12 BB#16 BB#18 BB#13 BB#17 How could CRT8 be marked implicitly-defined and also dead in the same instruction when it is clearly used in the next instruction? The code that inserts these instructions is in SDNode *PPCDAGToDAGISel::Select(SDNode *N) and reads: case ISD::BRIND: { // FIXME: Should custom lower this. SDValue Chain = N->getOperand(0); SDValue Target = N->getOperand(1); unsigned Opc = Target.getValueType() == MVT::i32 ? PPC::MTCTR : PPC::MTCTR8; unsigned Reg = Target.getValueType() == MVT::i32 ? PPC::BCTR : PPC::BCTR8; Chain = SDValue(CurDAG->getMachineNode(Opc, dl, MVT::Other, Target, Chain), 0); return CurDAG->SelectNodeTo(N, Reg, MVT::Other, Chain); } Thanks in advance, Hal On Mon, 2011-12-05 at 13:14 -0600, Hal Finkel wrote: > On Mon, 2011-12-05 at 10:12 -0800, Jakob Stoklund Olesen wrote: > > On Dec 5, 2011, at 9:55 AM, Hal Finkel wrote: > > > > > Author: hfinkel > > > Date: Mon Dec 5 11:55:17 2011 > > > New Revision: 145819 > > > > > > URL: http://llvm.org/viewvc/llvm-project?rev=145819&view=rev > > > Log: > > > enable PPC register scavenging by default (update tests and remove some FIXMEs) > > > > Nice! > > > > Did you run extensive tests with this change? > > Not extensive; I ran the regression tests and a few other files I've > been using recently. I'll be setup soon to run the test suite on ppc64, > and so I'll test more-extensively using the test suite. Unfortunately, > there are still other problems that I have to fix first (like PR11476, > which may be related to register scavenging, but was not fixed by these > changes). > > > Does it work with -O0? > > Good point, I'll run some more tests (and the test suite) with -O0. Some > of the regression tests specify -O0 (like the varargs test, which seemed > to be fine). > > Thanks again, > Hal > > > > > The register scavenger is notorious for exposing sloppy liveness info in older targets like PPC. I would expect a number of scavenger assertions. > > > > /jakob > > > -- Hal Finkel Postdoctoral Appointee Leadership Computing Facility Argonne National Laboratory From ahatanaka at mips.com Mon Dec 5 15:03:04 2011 From: ahatanaka at mips.com (Akira Hatanaka) Date: Mon, 05 Dec 2011 21:03:04 -0000 Subject: [llvm-commits] [llvm] r145850 - in /llvm/trunk: lib/Target/Mips/MipsISelLowering.cpp test/CodeGen/Mips/2010-07-20-Switch.ll Message-ID: <20111205210304.2E4982A6C12C@llvm.org> Author: ahatanak Date: Mon Dec 5 15:03:03 2011 New Revision: 145850 URL: http://llvm.org/viewvc/llvm-project?rev=145850&view=rev Log: Have LowerJumpTable support Mips64. Modify 2010-07-20-Switch.ll to test N64 and O32 with relocation-model=pic too. Modified: llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp llvm/trunk/test/CodeGen/Mips/2010-07-20-Switch.ll Modified: llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp?rev=145850&r1=145849&r2=145850&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp (original) +++ llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp Mon Dec 5 15:03:03 2011 @@ -130,6 +130,7 @@ setOperationAction(ISD::BlockAddress, MVT::i64, Custom); setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom); setOperationAction(ISD::JumpTable, MVT::i32, Custom); + setOperationAction(ISD::JumpTable, MVT::i64, Custom); setOperationAction(ISD::ConstantPool, MVT::i32, Custom); setOperationAction(ISD::ConstantPool, MVT::i64, Custom); setOperationAction(ISD::SELECT, MVT::f32, Custom); @@ -1594,34 +1595,29 @@ SDValue MipsTargetLowering:: LowerJumpTable(SDValue Op, SelectionDAG &DAG) const { - SDValue ResNode; - SDValue HiPart; + SDValue HiPart, JTI, JTILo; // FIXME there isn't actually debug info here DebugLoc dl = Op.getDebugLoc(); bool IsPIC = getTargetMachine().getRelocationModel() == Reloc::PIC_; - unsigned char OpFlag = IsPIC ? MipsII::MO_GOT : MipsII::MO_ABS_HI; - EVT PtrVT = Op.getValueType(); - JumpTableSDNode *JT = cast(Op); + JumpTableSDNode *JT = cast(Op); - SDValue JTI = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, OpFlag); - - if (!IsPIC) { - SDValue Ops[] = { JTI }; - HiPart = DAG.getNode(MipsISD::Hi, dl, DAG.getVTList(MVT::i32), Ops, 1); + if (!IsPIC && !IsN64) { + JTI = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, MipsII::MO_ABS_HI); + HiPart = DAG.getNode(MipsISD::Hi, dl, PtrVT, JTI); + JTILo = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, MipsII::MO_ABS_LO); } else {// Emit Load from Global Pointer - JTI = DAG.getNode(MipsISD::WrapperPIC, dl, MVT::i32, JTI); - HiPart = DAG.getLoad(MVT::i32, dl, DAG.getEntryNode(), JTI, - MachinePointerInfo(), - false, false, false, 0); + unsigned GOTFlag = IsN64 ? MipsII::MO_GOT_PAGE : MipsII::MO_GOT; + unsigned OfstFlag = IsN64 ? MipsII::MO_GOT_OFST : MipsII::MO_ABS_LO; + JTI = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, GOTFlag); + JTI = DAG.getNode(MipsISD::WrapperPIC, dl, PtrVT, JTI); + HiPart = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), JTI, + MachinePointerInfo(), false, false, false, 0); + JTILo = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, OfstFlag); } - SDValue JTILo = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, - MipsII::MO_ABS_LO); - SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, JTILo); - ResNode = DAG.getNode(ISD::ADD, dl, MVT::i32, HiPart, Lo); - - return ResNode; + SDValue Lo = DAG.getNode(MipsISD::Lo, dl, PtrVT, JTILo); + return DAG.getNode(ISD::ADD, dl, PtrVT, HiPart, Lo); } SDValue MipsTargetLowering:: Modified: llvm/trunk/test/CodeGen/Mips/2010-07-20-Switch.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/2010-07-20-Switch.ll?rev=145850&r1=145849&r2=145850&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/Mips/2010-07-20-Switch.ll (original) +++ llvm/trunk/test/CodeGen/Mips/2010-07-20-Switch.ll Mon Dec 5 15:03:03 2011 @@ -1,13 +1,21 @@ -; RUN: llc < %s -march=mips -relocation-model=static | FileCheck %s +; RUN: llc < %s -march=mips -relocation-model=static | FileCheck %s -check-prefix=STATIC-O32 +; RUN: llc < %s -march=mips -relocation-model=pic | FileCheck %s -check-prefix=PIC-O32 +; RUN: llc < %s -march=mips64 -relocation-model=pic -mcpu=mips64 -mattr=n64 | FileCheck %s -check-prefix=PIC-N64 define i32 @main() nounwind readnone { entry: %x = alloca i32, align 4 ; [#uses=2] store volatile i32 2, i32* %x, align 4 %0 = load volatile i32* %x, align 4 ; [#uses=1] -; CHECK: lui $3, %hi($JTI0_0) -; CHECK: addiu $3, $3, %lo($JTI0_0) -; CHECK: sll $2, $2, 2 +; STATIC-O32: lui $[[R0:[0-9]+]], %hi($JTI0_0) +; STATIC-O32: addiu ${{[0-9]+}}, $[[R0]], %lo($JTI0_0) +; STATIC-O32: sll ${{[0-9]+}}, ${{[0-9]+}}, 2 +; PIC-O32: lw $[[R0:[0-9]+]], %got($JTI0_0) +; PIC-O32: addiu ${{[0-9]+}}, $[[R0]], %lo($JTI0_0) +; PIC-O32: sll ${{[0-9]+}}, ${{[0-9]+}}, 2 +; PIC-N64: ld $[[R0:[0-9]+]], %got_page($JTI0_0) +; PIC-N64: daddiu ${{[0-9]+}}, $[[R0]], %got_ofst($JTI0_0) +; PIC-N64: dsll ${{[0-9]+}}, ${{[0-9]+}}, 2 switch i32 %0, label %bb4 [ i32 0, label %bb5 i32 1, label %bb1 @@ -18,7 +26,7 @@ bb1: ; preds = %entry ret i32 2 -; CHECK: $BB0_2 +; CHECK: STATIC-O32: $BB0_2 bb2: ; preds = %entry ret i32 0 From deeppatel1987 at gmail.com Mon Dec 5 15:06:21 2011 From: deeppatel1987 at gmail.com (Sandeep Patel) Date: Mon, 5 Dec 2011 21:06:21 +0000 Subject: [llvm-commits] PATCH: Initial patches for changing the semantics of llvm.cttz and llvm.ctlz In-Reply-To: <313D9FE2-D633-4744-92EE-9383B6691E62@mac.com> References: <2DBA1282-CC2C-430B-9A62-5694D5ABAD4B@apple.com> <313D9FE2-D633-4744-92EE-9383B6691E62@mac.com> Message-ID: On Sat, Dec 3, 2011 at 6:24 AM, Owen Anderson wrote: > > On Dec 1, 2011, at 3:06 PM, Chris Lattner wrote: > >> >> On Dec 1, 2011, at 11:20 AM, Dan Gohman wrote: >> >>> On Dec 1, 2011, at 2:47 AM, Chandler Carruth wrote: >>>> >>>> 7) remove all support (other than auto-upgrade) for the old intrinsics >>> >>> The "old" semantics really are more desirable though, in general. The only >>> reason I know of for the "new" semantics is to cater to x86's old bsf and >>> bsr instructions. But x86 admits its own deficiency, and has since introduced >>> the lzcnt and tzcnt instructions, which behave properly. It seems unfortunate >>> to require people who want the sane semantics to use a branch (even if >>> CodeGen is clever and can eliminate it). >> >> I would be fine with keeping the existing intrinsics and adding two new ones with gcc-compatible semantics. > > What's the point of having two? ?Would any frontend actually generate the non-GCC compatible ones? It seems likely that intrinsics will be desired to choose a particular instruction on known hardware or in a CPUID-protected code path. deep From grosbach at apple.com Mon Dec 5 15:06:26 2011 From: grosbach at apple.com (Jim Grosbach) Date: Mon, 05 Dec 2011 21:06:26 -0000 Subject: [llvm-commits] [llvm] r145851 - in /llvm/trunk: lib/Target/ARM/AsmParser/ARMAsmParser.cpp test/MC/ARM/basic-thumb2-instructions.s Message-ID: <20111205210626.5A4F42A6C12C@llvm.org> Author: grosbach Date: Mon Dec 5 15:06:26 2011 New Revision: 145851 URL: http://llvm.org/viewvc/llvm-project?rev=145851&view=rev Log: Thumb2 prefer encoding T3 to T4 for ADD/SUB immediate instructions. rdar://10529348 Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp?rev=145851&r1=145850&r2=145851&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp (original) +++ llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Mon Dec 5 15:06:26 2011 @@ -5200,6 +5200,24 @@ Inst = TmpInst; } break; + case ARM::t2ADDri12: + // If the immediate fits for encoding T3 (t2ADDri) and the generic "add" + // mnemonic was used (not "addw"), encoding T3 is preferred. + if (static_cast(Operands[0])->getToken() != "add" || + ARM_AM::getT2SOImmVal(Inst.getOperand(2).getImm()) == -1) + break; + Inst.setOpcode(ARM::t2ADDri); + Inst.addOperand(MCOperand::CreateReg(0)); // cc_out + break; + case ARM::t2SUBri12: + // If the immediate fits for encoding T3 (t2SUBri) and the generic "sub" + // mnemonic was used (not "subw"), encoding T3 is preferred. + if (static_cast(Operands[0])->getToken() != "sub" || + ARM_AM::getT2SOImmVal(Inst.getOperand(2).getImm()) == -1) + break; + Inst.setOpcode(ARM::t2SUBri); + Inst.addOperand(MCOperand::CreateReg(0)); // cc_out + break; case ARM::tADDi8: // If the immediate is in the range 0-7, we want tADDi3 iff Rd was // explicitly specified. From the ARM ARM: "Encoding T1 is preferred Modified: llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s?rev=145851&r1=145850&r2=145851&view=diff ============================================================================== --- llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s (original) +++ llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s Mon Dec 5 15:06:26 2011 @@ -74,6 +74,7 @@ addw r12, r6, #0x100 adds r1, r2, #0x1f0 add r2, #1 + add r0, r0, #32 @ CHECK: itet eq @ encoding: [0x0a,0xbf] @ CHECK: addeq r1, r2, #4 @ encoding: [0x11,0x1d] @@ -87,6 +88,7 @@ @ CHECK: addw r12, r6, #256 @ encoding: [0x06,0xf2,0x00,0x1c] @ CHECK: adds.w r1, r2, #496 @ encoding: [0x12,0xf5,0xf8,0x71] @ CHECK: add.w r2, r2, #1 @ encoding: [0x02,0xf1,0x01,0x02] +@ CHECK: add.w r0, r0, #32 @ encoding: [0x00,0xf1,0x20,0x00] @------------------------------------------------------------------------------ @@ -2566,6 +2568,7 @@ subw r12, r6, #0x100 subs r1, r2, #0x1f0 sub r2, #1 + sub r0, r0, #32 @ CHECK: itet eq @ encoding: [0x0a,0xbf] @ CHECK: subeq r1, r2, #4 @ encoding: [0x11,0x1f] @@ -2579,6 +2582,7 @@ @ CHECK: subw r12, r6, #256 @ encoding: [0xa6,0xf2,0x00,0x1c] @ CHECK: subs.w r1, r2, #496 @ encoding: [0xb2,0xf5,0xf8,0x71] @ CHECK: sub.w r2, r2, #1 @ encoding: [0xa2,0xf1,0x01,0x02] +@ CHECK: sub.w r0, r0, #32 @ encoding: [0xa0,0xf1,0x20,0x00] @------------------------------------------------------------------------------ From grosbach at apple.com Mon Dec 5 14:10:30 2011 From: grosbach at apple.com (Jim Grosbach) Date: Mon, 05 Dec 2011 12:10:30 -0800 Subject: [llvm-commits] [llvm] r145842 - in /llvm/trunk/lib/Target/ARM: ARMInstrFormats.td ARMInstrNEON.td In-Reply-To: <17B2F12B-75C4-4F4B-A1F3-6861DEEAE6A3@apple.com> References: <20111205195546.DFAE62A6C12C@llvm.org> <17B2F12B-75C4-4F4B-A1F3-6861DEEAE6A3@apple.com> Message-ID: Forthcoming, along with a few other variants of this same instruction class. On Dec 5, 2011, at 12:06 PM, Chad Rosier wrote: > Test case? > > Chad > > On Dec 5, 2011, at 11:55 AM, Jim Grosbach wrote: > >> Author: grosbach >> Date: Mon Dec 5 13:55:46 2011 >> New Revision: 145842 >> >> URL: http://llvm.org/viewvc/llvm-project?rev=145842&view=rev >> Log: >> ARM assmebler parsing for two-operand VMUL instructions. >> >> Combined destination and first source operand for f32 variant of the VMUL >> (by scalar) instruction. >> >> rdar://10522016 >> >> Modified: >> llvm/trunk/lib/Target/ARM/ARMInstrFormats.td >> llvm/trunk/lib/Target/ARM/ARMInstrNEON.td >> >> Modified: llvm/trunk/lib/Target/ARM/ARMInstrFormats.td >> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrFormats.td?rev=145842&r1=145841&r2=145842&view=diff >> ============================================================================== >> --- llvm/trunk/lib/Target/ARM/ARMInstrFormats.td (original) >> +++ llvm/trunk/lib/Target/ARM/ARMInstrFormats.td Mon Dec 5 13:55:46 2011 >> @@ -231,6 +231,8 @@ >> : InstAlias, Requires<[HasVFP2]>; >> class VFP3InstAlias >> : InstAlias, Requires<[HasVFP3]>; >> +class NEONInstAlias >> + : InstAlias, Requires<[HasNEON]>; >> >> //===----------------------------------------------------------------------===// >> // ARM Instruction templates. >> >> Modified: llvm/trunk/lib/Target/ARM/ARMInstrNEON.td >> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrNEON.td?rev=145842&r1=145841&r2=145842&view=diff >> ============================================================================== >> --- llvm/trunk/lib/Target/ARM/ARMInstrNEON.td (original) >> +++ llvm/trunk/lib/Target/ARM/ARMInstrNEON.td Mon Dec 5 13:55:46 2011 >> @@ -3672,6 +3672,15 @@ >> def VMULslfq : N3VQSL<0b10, 0b1001, IIC_VBINQ, "vmul", "f32", v4f32, >> v2f32, fmul>; >> >> +// Two-operand aliases. >> +def : NEONInstAlias<"vmul${p}.f32 $Ddn $Dm$lane", >> + (VMULslfd DPR:$Ddn, DPR:$Ddn, DPR_VFP2:$Dm, >> + VectorIndex32:$lane, pred:$p)>; >> +def : NEONInstAlias<"vmul${p}.f32 $Qdn $Dm$lane", >> + (VMULslfq QPR:$Qdn, QPR:$Qdn, DPR_VFP2:$Dm, >> + VectorIndex32:$lane, pred:$p)>; >> + >> + >> def : Pat<(v8i16 (mul (v8i16 QPR:$src1), >> (v8i16 (NEONvduplane (v8i16 QPR:$src2), imm:$lane)))), >> (v8i16 (VMULslv8i16 (v8i16 QPR:$src1), >> >> >> _______________________________________________ >> llvm-commits mailing list >> llvm-commits at cs.uiuc.edu >> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits > From mcrosier at apple.com Mon Dec 5 14:12:03 2011 From: mcrosier at apple.com (Chad Rosier) Date: Mon, 05 Dec 2011 12:12:03 -0800 Subject: [llvm-commits] [llvm] r145842 - in /llvm/trunk/lib/Target/ARM: ARMInstrFormats.td ARMInstrNEON.td In-Reply-To: References: <20111205195546.DFAE62A6C12C@llvm.org> <17B2F12B-75C4-4F4B-A1F3-6861DEEAE6A3@apple.com> Message-ID: <8E1D7282-652A-4DEF-90DF-2E01BF1CDF45@apple.com> 10-4. On Dec 5, 2011, at 12:10 PM, Jim Grosbach wrote: > Forthcoming, along with a few other variants of this same instruction class. > > On Dec 5, 2011, at 12:06 PM, Chad Rosier wrote: > >> Test case? >> >> Chad >> >> On Dec 5, 2011, at 11:55 AM, Jim Grosbach wrote: >> >>> Author: grosbach >>> Date: Mon Dec 5 13:55:46 2011 >>> New Revision: 145842 >>> >>> URL: http://llvm.org/viewvc/llvm-project?rev=145842&view=rev >>> Log: >>> ARM assmebler parsing for two-operand VMUL instructions. >>> >>> Combined destination and first source operand for f32 variant of the VMUL >>> (by scalar) instruction. >>> >>> rdar://10522016 >>> >>> Modified: >>> llvm/trunk/lib/Target/ARM/ARMInstrFormats.td >>> llvm/trunk/lib/Target/ARM/ARMInstrNEON.td >>> >>> Modified: llvm/trunk/lib/Target/ARM/ARMInstrFormats.td >>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrFormats.td?rev=145842&r1=145841&r2=145842&view=diff >>> ============================================================================== >>> --- llvm/trunk/lib/Target/ARM/ARMInstrFormats.td (original) >>> +++ llvm/trunk/lib/Target/ARM/ARMInstrFormats.td Mon Dec 5 13:55:46 2011 >>> @@ -231,6 +231,8 @@ >>> : InstAlias, Requires<[HasVFP2]>; >>> class VFP3InstAlias >>> : InstAlias, Requires<[HasVFP3]>; >>> +class NEONInstAlias >>> + : InstAlias, Requires<[HasNEON]>; >>> >>> //===----------------------------------------------------------------------===// >>> // ARM Instruction templates. >>> >>> Modified: llvm/trunk/lib/Target/ARM/ARMInstrNEON.td >>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrNEON.td?rev=145842&r1=145841&r2=145842&view=diff >>> ============================================================================== >>> --- llvm/trunk/lib/Target/ARM/ARMInstrNEON.td (original) >>> +++ llvm/trunk/lib/Target/ARM/ARMInstrNEON.td Mon Dec 5 13:55:46 2011 >>> @@ -3672,6 +3672,15 @@ >>> def VMULslfq : N3VQSL<0b10, 0b1001, IIC_VBINQ, "vmul", "f32", v4f32, >>> v2f32, fmul>; >>> >>> +// Two-operand aliases. >>> +def : NEONInstAlias<"vmul${p}.f32 $Ddn $Dm$lane", >>> + (VMULslfd DPR:$Ddn, DPR:$Ddn, DPR_VFP2:$Dm, >>> + VectorIndex32:$lane, pred:$p)>; >>> +def : NEONInstAlias<"vmul${p}.f32 $Qdn $Dm$lane", >>> + (VMULslfq QPR:$Qdn, QPR:$Qdn, DPR_VFP2:$Dm, >>> + VectorIndex32:$lane, pred:$p)>; >>> + >>> + >>> def : Pat<(v8i16 (mul (v8i16 QPR:$src1), >>> (v8i16 (NEONvduplane (v8i16 QPR:$src2), imm:$lane)))), >>> (v8i16 (VMULslv8i16 (v8i16 QPR:$src1), >>> >>> >>> _______________________________________________ >>> llvm-commits mailing list >>> llvm-commits at cs.uiuc.edu >>> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits >> > From ahatanaka at mips.com Mon Dec 5 15:14:28 2011 From: ahatanaka at mips.com (Akira Hatanaka) Date: Mon, 05 Dec 2011 21:14:28 -0000 Subject: [llvm-commits] [llvm] r145852 - /llvm/trunk/lib/Target/Mips/MipsInstrInfo.td Message-ID: <20111205211429.0BFEE2A6C12C@llvm.org> Author: ahatanak Date: Mon Dec 5 15:14:28 2011 New Revision: 145852 URL: http://llvm.org/viewvc/llvm-project?rev=145852&view=rev Log: Split ExtIns into two base classes and have instructions EXT and INS derive from them. Modified: llvm/trunk/lib/Target/Mips/MipsInstrInfo.td Modified: llvm/trunk/lib/Target/Mips/MipsInstrInfo.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsInstrInfo.td?rev=145852&r1=145851&r2=145852&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/MipsInstrInfo.td (original) +++ llvm/trunk/lib/Target/Mips/MipsInstrInfo.td Mon Dec 5 15:14:28 2011 @@ -623,14 +623,29 @@ } // Ext and Ins -class ExtIns _funct, string instr_asm, dag outs, dag ins, - list pattern, InstrItinClass itin>: - FR<0x1f, _funct, outs, ins, !strconcat(instr_asm, " $rt, $rs, $pos, $sz"), - pattern, itin>, Requires<[HasMips32r2]> { +class ExtBase _funct, string instr_asm, RegisterClass RC>: + FR<0x1f, _funct, (outs RC:$rt), (ins RC:$rs, uimm16:$pos, size_ext:$sz), + !strconcat(instr_asm, " $rt, $rs, $pos, $sz"), + [(set RC:$rt, (MipsExt RC:$rs, imm:$pos, imm:$sz))], NoItinerary> { bits<5> pos; bits<5> sz; let rd = sz; let shamt = pos; + let Predicates = [HasMips32r2]; +} + +class InsBase _funct, string instr_asm, RegisterClass RC>: + FR<0x1f, _funct, (outs RC:$rt), + (ins RC:$rs, uimm16:$pos, size_ins:$sz, RC:$src), + !strconcat(instr_asm, " $rt, $rs, $pos, $sz"), + [(set RC:$rt, (MipsIns RC:$rs, imm:$pos, imm:$sz, RC:$src))], + NoItinerary> { + bits<5> pos; + bits<5> sz; + let rd = sz; + let shamt = pos; + let Predicates = [HasMips32r2]; + let Constraints = "$src = $rt"; } // Atomic instructions with 2 source operands (ATOMIC_SWAP & ATOMIC_LOAD_*). @@ -890,19 +905,8 @@ def RDHWR : ReadHardware; -def EXT : ExtIns<0, "ext", (outs CPURegs:$rt), - (ins CPURegs:$rs, uimm16:$pos, size_ext:$sz), - [(set CPURegs:$rt, - (MipsExt CPURegs:$rs, immZExt5:$pos, immZExt5:$sz))], - NoItinerary>; - -let Constraints = "$src = $rt" in -def INS : ExtIns<4, "ins", (outs CPURegs:$rt), - (ins CPURegs:$rs, uimm16:$pos, size_ins:$sz, CPURegs:$src), - [(set CPURegs:$rt, - (MipsIns CPURegs:$rs, immZExt5:$pos, immZExt5:$sz, - CPURegs:$src))], - NoItinerary>; +def EXT : ExtBase<0, "ext", CPURegs>; +def INS : InsBase<4, "ins", CPURegs>; //===----------------------------------------------------------------------===// // Arbitrary patterns that map to one or more instructions From stoklund at 2pi.dk Mon Dec 5 15:18:21 2011 From: stoklund at 2pi.dk (Jakob Stoklund Olesen) Date: Mon, 05 Dec 2011 13:18:21 -0800 Subject: [llvm-commits] Dead register (was Re: [llvm] r145819) In-Reply-To: <1323118601.2507.3183.camel@sapling> References: <20111205175518.343FF2A6C12C@llvm.org> <1323112465.2507.3170.camel@sapling> <1323118601.2507.3183.camel@sapling> Message-ID: On Dec 5, 2011, at 12:56 PM, Hal Finkel wrote: > RegScavenger is complaining about use of an undefined register, CTR8, in > the BCTR8 instruction, in the following instance (this is from the PPC > backend): > > BB#38: derived from LLVM BB %for.end50 > Predecessors according to CFG: BB#36 > %X3 = LD 0, ; mem:LD8[FixedStack27] > %X4 = RLDICR %X3, 3, 60 > %X5 = LI8 [TF=4] > %X5 = ADDIS8 %X5, [TF=8] > %X4 = LDX %X4, %X5; mem:LD8[JumpTable] > MTCTR8 %X4, %CTR8 > BCTR8 %CTR8, %RM > Successors according to CFG: BB#23 BB#15 BB#7 BB#8 BB#9 BB#10 BB#11 > BB#25 BB#12 BB#16 BB#18 BB#13 BB#17 > > How could CRT8 be marked implicitly-defined and also dead in the same > instruction when it is clearly used in the next instruction? This is the kind of sloppy liveness, I was talking about ;-) llc -verify-machineinstrs should give you better info. /jakob From ahatanaka at mips.com Mon Dec 5 15:26:35 2011 From: ahatanaka at mips.com (Akira Hatanaka) Date: Mon, 05 Dec 2011 21:26:35 -0000 Subject: [llvm-commits] [llvm] r145853 - in /llvm/trunk: lib/Target/Mips/Mips64InstrInfo.td lib/Target/Mips/MipsISelLowering.cpp test/CodeGen/Mips/mips64extins.ll Message-ID: <20111205212635.3C0D62A6C12C@llvm.org> Author: ahatanak Date: Mon Dec 5 15:26:34 2011 New Revision: 145853 URL: http://llvm.org/viewvc/llvm-project?rev=145853&view=rev Log: Add definitions of 64-bit extract and insert instrucions and make PerformANDCombine and PerformOrCombine aware of them. Test cases are included too. Added: llvm/trunk/test/CodeGen/Mips/mips64extins.ll Modified: llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp Modified: llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td?rev=145853&r1=145852&r2=145853&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td (original) +++ llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td Mon Dec 5 15:26:34 2011 @@ -206,6 +206,9 @@ def DynAlloc64 : EffectiveAddress<"daddiu\t$rt, $addr", CPU64Regs, mem_ea_64>, Requires<[IsN64]>; +def DEXT : ExtBase<3, "dext", CPU64Regs>; +def DINS : InsBase<7, "dins", CPU64Regs>; + //===----------------------------------------------------------------------===// // Arbitrary patterns that map to one or more instructions //===----------------------------------------------------------------------===// Modified: llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp?rev=145853&r1=145852&r2=145853&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp (original) +++ llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp Mon Dec 5 15:26:34 2011 @@ -40,11 +40,11 @@ // mask (Pos), and return true. // For example, if I is 0x003ff800, (Pos, Size) = (11, 11). static bool IsShiftedMask(uint64_t I, uint64_t &Pos, uint64_t &Size) { - if (!isUInt<32>(I) || !isShiftedMask_32(I)) + if (!isShiftedMask_64(I)) return false; - Size = CountPopulation_32(I); - Pos = CountTrailingZeros_32(I); + Size = CountPopulation_64(I); + Pos = CountTrailingZeros_64(I); return true; } @@ -556,20 +556,20 @@ return SDValue(); SDValue ShiftRight = N->getOperand(0), Mask = N->getOperand(1); - + unsigned ShiftRightOpc = ShiftRight.getOpcode(); + // Op's first operand must be a shift right. - if (ShiftRight.getOpcode() != ISD::SRA && ShiftRight.getOpcode() != ISD::SRL) + if (ShiftRightOpc != ISD::SRA && ShiftRightOpc != ISD::SRL) return SDValue(); // The second operand of the shift must be an immediate. - uint64_t Pos; ConstantSDNode *CN; if (!(CN = dyn_cast(ShiftRight.getOperand(1)))) return SDValue(); - Pos = CN->getZExtValue(); - + uint64_t Pos = CN->getZExtValue(); uint64_t SMPos, SMSize; + // Op's second operand must be a shifted mask. if (!(CN = dyn_cast(Mask)) || !IsShiftedMask(CN->getZExtValue(), SMPos, SMSize)) @@ -577,10 +577,11 @@ // Return if the shifted mask does not start at bit 0 or the sum of its size // and Pos exceeds the word's size. - if (SMPos != 0 || Pos + SMSize > 32) + EVT ValTy = N->getValueType(0); + if (SMPos != 0 || Pos + SMSize > ValTy.getSizeInBits()) return SDValue(); - return DAG.getNode(MipsISD::Ext, N->getDebugLoc(), MVT::i32, + return DAG.getNode(MipsISD::Ext, N->getDebugLoc(), ValTy, ShiftRight.getOperand(0), DAG.getConstant(Pos, MVT::i32), DAG.getConstant(SMSize, MVT::i32)); @@ -631,10 +632,11 @@ // Return if the shift amount and the first bit position of mask are not the // same. - if (Shamt != SMPos0) + EVT ValTy = N->getValueType(0); + if ((Shamt != SMPos0) || (SMPos0 + SMSize0 > ValTy.getSizeInBits())) return SDValue(); - return DAG.getNode(MipsISD::Ins, N->getDebugLoc(), MVT::i32, + return DAG.getNode(MipsISD::Ins, N->getDebugLoc(), ValTy, Shl.getOperand(0), DAG.getConstant(SMPos0, MVT::i32), DAG.getConstant(SMSize0, MVT::i32), Added: llvm/trunk/test/CodeGen/Mips/mips64extins.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/mips64extins.ll?rev=145853&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/Mips/mips64extins.ll (added) +++ llvm/trunk/test/CodeGen/Mips/mips64extins.ll Mon Dec 5 15:26:34 2011 @@ -0,0 +1,55 @@ +; RUN: llc < %s -march=mips64el -mcpu=mips64r2 -mattr=n64 | FileCheck %s + +define i64 @dext(i64 %i) nounwind readnone { +entry: +; CHECK: dext ${{[0-9]+}}, ${{[0-9]+}}, 5, 10 + %shr = lshr i64 %i, 5 + %and = and i64 %shr, 1023 + ret i64 %and +} + +define i64 @dextm(i64 %i) nounwind readnone { +entry: +; CHECK: dext ${{[0-9]+}}, ${{[0-9]+}}, 5, 34 + %shr = lshr i64 %i, 5 + %and = and i64 %shr, 17179869183 + ret i64 %and +} + +define i64 @dextu(i64 %i) nounwind readnone { +entry: +; CHECK: dext ${{[0-9]+}}, ${{[0-9]+}}, 34, 6 + %shr = lshr i64 %i, 34 + %and = and i64 %shr, 63 + ret i64 %and +} + +define i64 @dins(i64 %i, i64 %j) nounwind readnone { +entry: +; CHECK: dins ${{[0-9]+}}, ${{[0-9]+}}, 8, 10 + %shl2 = shl i64 %j, 8 + %and = and i64 %shl2, 261888 + %and3 = and i64 %i, -261889 + %or = or i64 %and3, %and + ret i64 %or +} + +define i64 @dinsm(i64 %i, i64 %j) nounwind readnone { +entry: +; CHECK: dins ${{[0-9]+}}, ${{[0-9]+}}, 10, 33 + %shl4 = shl i64 %j, 10 + %and = and i64 %shl4, 8796093021184 + %and5 = and i64 %i, -8796093021185 + %or = or i64 %and5, %and + ret i64 %or +} + +define i64 @dinsu(i64 %i, i64 %j) nounwind readnone { +entry: +; CHECK: dins ${{[0-9]+}}, ${{[0-9]+}}, 40, 13 + %shl4 = shl i64 %j, 40 + %and = and i64 %shl4, 9006099743113216 + %and5 = and i64 %i, -9006099743113217 + %or = or i64 %and5, %and + ret i64 %or +} From isanbard at gmail.com Mon Dec 5 15:27:54 2011 From: isanbard at gmail.com (Bill Wendling) Date: Mon, 05 Dec 2011 21:27:54 -0000 Subject: [llvm-commits] [llvm] r145854 - /llvm/trunk/docs/LangRef.html Message-ID: <20111205212754.D7EAA2A6C12C@llvm.org> Author: void Date: Mon Dec 5 15:27:54 2011 New Revision: 145854 URL: http://llvm.org/viewvc/llvm-project?rev=145854&view=rev Log: Move 'returns_twice' definition into alphabetical place. Modified: llvm/trunk/docs/LangRef.html Modified: llvm/trunk/docs/LangRef.html URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/LangRef.html?rev=145854&r1=145853&r2=145854&view=diff ============================================================================== --- llvm/trunk/docs/LangRef.html (original) +++ llvm/trunk/docs/LangRef.html Mon Dec 5 15:27:54 2011 @@ -1216,6 +1216,12 @@ exception by calling the C++ exception throwing methods, but may use the unwind instruction. +

returns_twice
+
This attribute indicates that this function can return twice. The + C setjmp is an example of such a function. The compiler + disables some optimizations (like tail calls) in the caller of these + functions.
+
ssp
This attribute indicates that the function should emit a stack smashing protector. It is in the form of a "canary"—a random value placed on @@ -1243,12 +1249,6 @@ show that no exceptions passes by it. This is normally the case for the ELF x86-64 abi, but it can be disabled for some compilation units.
- -
returns_twice
-
This attribute indicates that this function can return - twice. The C setjmp is an example of such a function. - The compiler disables some optimizations (like tail calls) in the caller of - these functions.
From hfinkel at anl.gov Mon Dec 5 15:36:50 2011 From: hfinkel at anl.gov (Hal Finkel) Date: Mon, 05 Dec 2011 15:36:50 -0600 Subject: [llvm-commits] Dead register (was Re: [llvm] r145819) In-Reply-To: References: <20111205175518.343FF2A6C12C@llvm.org> <1323112465.2507.3170.camel@sapling> <1323118601.2507.3183.camel@sapling> Message-ID: <1323121010.2507.3186.camel@sapling> On Mon, 2011-12-05 at 13:18 -0800, Jakob Stoklund Olesen wrote: > On Dec 5, 2011, at 12:56 PM, Hal Finkel wrote: > > > RegScavenger is complaining about use of an undefined register, CTR8, in > > the BCTR8 instruction, in the following instance (this is from the PPC > > backend): > > > > BB#38: derived from LLVM BB %for.end50 > > Predecessors according to CFG: BB#36 > > %X3 = LD 0, ; mem:LD8[FixedStack27] > > %X4 = RLDICR %X3, 3, 60 > > %X5 = LI8 [TF=4] > > %X5 = ADDIS8 %X5, [TF=8] > > %X4 = LDX %X4, %X5; mem:LD8[JumpTable] > > MTCTR8 %X4, %CTR8 > > BCTR8 %CTR8, %RM > > Successors according to CFG: BB#23 BB#15 BB#7 BB#8 BB#9 BB#10 BB#11 > > BB#25 BB#12 BB#16 BB#18 BB#13 BB#17 > > > > How could CRT8 be marked implicitly-defined and also dead in the same > > instruction when it is clearly used in the next instruction? > > This is the kind of sloppy liveness, I was talking about ;-) Yea, I went looking ;) > > llc -verify-machineinstrs should give you better info. Thanks! -Hal > > /jakob > -- Hal Finkel Postdoctoral Appointee Leadership Computing Facility Argonne National Laboratory From grosbach at apple.com Mon Dec 5 16:16:39 2011 From: grosbach at apple.com (Jim Grosbach) Date: Mon, 05 Dec 2011 22:16:39 -0000 Subject: [llvm-commits] [llvm] r145860 - /llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Message-ID: <20111205221639.4CC512A6C12C@llvm.org> Author: grosbach Date: Mon Dec 5 16:16:39 2011 New Revision: 145860 URL: http://llvm.org/viewvc/llvm-project?rev=145860&view=rev Log: Thumb2 prefer ADD register encoding T2 to T3 when possible. rdar://10529664 Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp?rev=145860&r1=145859&r2=145860&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp (original) +++ llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Mon Dec 5 16:16:39 2011 @@ -5238,6 +5238,26 @@ return true; } break; + case ARM::t2ADDrr: { + // If the destination and first source operand are the same, and + // there's no setting of the flags, use encoding T2 instead of T3. + // Note that this is only for ADD, not SUB. This mirrors the system + // 'as' behaviour. Make sure the wide encoding wasn't explicit. + if (Inst.getOperand(0).getReg() != Inst.getOperand(1).getReg() || + Inst.getOperand(5).getReg() != 0 || + (static_cast(Operands[2])->isToken() && + static_cast(Operands[2])->getToken() == ".w")) + break; + MCInst TmpInst; + TmpInst.setOpcode(ARM::tADDhirr); + TmpInst.addOperand(Inst.getOperand(0)); + TmpInst.addOperand(Inst.getOperand(0)); + TmpInst.addOperand(Inst.getOperand(2)); + TmpInst.addOperand(Inst.getOperand(3)); + TmpInst.addOperand(Inst.getOperand(4)); + Inst = TmpInst; + return true; + } case ARM::tB: // A Thumb conditional branch outside of an IT block is a tBcc. if (Inst.getOperand(1).getImm() != ARMCC::AL && !inITBlock()) { From grosbach at apple.com Mon Dec 5 16:21:28 2011 From: grosbach at apple.com (Jim Grosbach) Date: Mon, 05 Dec 2011 22:21:28 -0000 Subject: [llvm-commits] [llvm] r145861 - in /llvm/trunk/test/MC/ARM: basic-thumb2-instructions.s mode-switch.s Message-ID: <20111205222128.848972A6C12C@llvm.org> Author: grosbach Date: Mon Dec 5 16:21:28 2011 New Revision: 145861 URL: http://llvm.org/viewvc/llvm-project?rev=145861&view=rev Log: Update tests for r145860. Add a few new ones. Modified: llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s llvm/trunk/test/MC/ARM/mode-switch.s Modified: llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s?rev=145861&r1=145860&r2=145861&view=diff ============================================================================== --- llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s (original) +++ llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s Mon Dec 5 16:21:28 2011 @@ -99,12 +99,16 @@ adds r7, r3, r1, lsl #31 adds.w r0, r3, r6, lsr #25 add.w r4, r8, r1, ror #12 + add r10, r8 + add r10, r10, r8 @ CHECK: add.w r1, r2, r8 @ encoding: [0x02,0xeb,0x08,0x01] @ CHECK: add.w r5, r9, r2, asr #32 @ encoding: [0x09,0xeb,0x22,0x05] @ CHECK: adds.w r7, r3, r1, lsl #31 @ encoding: [0x13,0xeb,0xc1,0x77] @ CHECK: adds.w r0, r3, r6, lsr #25 @ encoding: [0x13,0xeb,0x56,0x60] @ CHECK: add.w r4, r8, r1, ror #12 @ encoding: [0x08,0xeb,0x31,0x34] +@ CHECK: add r10, r8 @ encoding: [0xc2,0x44] +@ CHECK: add r10, r8 @ encoding: [0xc2,0x44] @------------------------------------------------------------------------------ Modified: llvm/trunk/test/MC/ARM/mode-switch.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/mode-switch.s?rev=145861&r1=145860&r2=145861&view=diff ============================================================================== --- llvm/trunk/test/MC/ARM/mode-switch.s (original) +++ llvm/trunk/test/MC/ARM/mode-switch.s Mon Dec 5 16:21:28 2011 @@ -4,7 +4,7 @@ .code 16 add.w r0, r0, r1 -@ CHECK: add.w r0, r0, r1 @ encoding: [0x00,0xeb,0x01,0x00] +@ CHECK: add r0, r1 @ encoding: [0x08,0x44] .code 32 add r0, r0, r1 From grosbach at apple.com Mon Dec 5 16:27:05 2011 From: grosbach at apple.com (Jim Grosbach) Date: Mon, 05 Dec 2011 22:27:05 -0000 Subject: [llvm-commits] [llvm] r145863 - in /llvm/trunk: lib/Target/ARM/AsmParser/ARMAsmParser.cpp test/MC/ARM/mode-switch.s Message-ID: <20111205222705.1E00A2A6C12C@llvm.org> Author: grosbach Date: Mon Dec 5 16:27:04 2011 New Revision: 145863 URL: http://llvm.org/viewvc/llvm-project?rev=145863&view=rev Log: Tweak ADDrr fix. Bad check for explicit .w Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp llvm/trunk/test/MC/ARM/mode-switch.s Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp?rev=145863&r1=145862&r2=145863&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp (original) +++ llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Mon Dec 5 16:27:04 2011 @@ -5245,8 +5245,8 @@ // 'as' behaviour. Make sure the wide encoding wasn't explicit. if (Inst.getOperand(0).getReg() != Inst.getOperand(1).getReg() || Inst.getOperand(5).getReg() != 0 || - (static_cast(Operands[2])->isToken() && - static_cast(Operands[2])->getToken() == ".w")) + (static_cast(Operands[3])->isToken() && + static_cast(Operands[3])->getToken() == ".w")) break; MCInst TmpInst; TmpInst.setOpcode(ARM::tADDhirr); Modified: llvm/trunk/test/MC/ARM/mode-switch.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/mode-switch.s?rev=145863&r1=145862&r2=145863&view=diff ============================================================================== --- llvm/trunk/test/MC/ARM/mode-switch.s (original) +++ llvm/trunk/test/MC/ARM/mode-switch.s Mon Dec 5 16:27:04 2011 @@ -4,7 +4,7 @@ .code 16 add.w r0, r0, r1 -@ CHECK: add r0, r1 @ encoding: [0x08,0x44] +@ CHECK: add.w r0, r0, r1 @ encoding: [0x00,0xeb,0x01,0x00] .code 32 add r0, r0, r1 From mcrosier at apple.com Mon Dec 5 16:37:00 2011 From: mcrosier at apple.com (Chad Rosier) Date: Mon, 05 Dec 2011 22:37:00 -0000 Subject: [llvm-commits] [llvm] r145865 - in /llvm/trunk: lib/Transforms/Scalar/MemCpyOptimizer.cpp test/Transforms/MemCpyOpt/form-memset.ll Message-ID: <20111205223700.8EE422A6C12C@llvm.org> Author: mcrosier Date: Mon Dec 5 16:37:00 2011 New Revision: 145865 URL: http://llvm.org/viewvc/llvm-project?rev=145865&view=rev Log: Make the MemCpyOptimizer a bit more aggressive. I can't think of a scenerio where this would be bad as the backend shouldn't have a problem inlining small memcpys. rdar://10510150 Modified: llvm/trunk/lib/Transforms/Scalar/MemCpyOptimizer.cpp llvm/trunk/test/Transforms/MemCpyOpt/form-memset.ll Modified: llvm/trunk/lib/Transforms/Scalar/MemCpyOptimizer.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/MemCpyOptimizer.cpp?rev=145865&r1=145864&r2=145865&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Scalar/MemCpyOptimizer.cpp (original) +++ llvm/trunk/lib/Transforms/Scalar/MemCpyOptimizer.cpp Mon Dec 5 16:37:00 2011 @@ -148,7 +148,7 @@ bool MemsetRange::isProfitableToUseMemset(const TargetData &TD) const { // If we found more than 8 stores to merge or 64 bytes, use memset. - if (TheStores.size() >= 8 || End-Start >= 64) return true; + if (TheStores.size() >= 4 || End-Start >= 16) return true; // If there is nothing to merge, don't do anything. if (TheStores.size() < 2) return false; Modified: llvm/trunk/test/Transforms/MemCpyOpt/form-memset.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/MemCpyOpt/form-memset.ll?rev=145865&r1=145864&r2=145865&view=diff ============================================================================== --- llvm/trunk/test/Transforms/MemCpyOpt/form-memset.ll (original) +++ llvm/trunk/test/Transforms/MemCpyOpt/form-memset.ll Mon Dec 5 16:37:00 2011 @@ -57,8 +57,8 @@ declare i32 @bar(...) +%struct.MV = type { i16, i16 } - %struct.MV = type { i16, i16 } define void @test2() nounwind { entry: @@ -220,3 +220,19 @@ ; CHECK: call void @llvm.memset.p0i8.i64(i8* %2, i8 0, i64 24, i32 1, i1 false) } +; More aggressive heuristic +; rdar://9892684 +define void @test7(i32* nocapture %c) nounwind optsize { + store i32 -1, i32* %c, align 4 + %1 = getelementptr inbounds i32* %c, i32 1 + store i32 -1, i32* %1, align 4 + %2 = getelementptr inbounds i32* %c, i32 2 + store i32 -1, i32* %2, align 4 + %3 = getelementptr inbounds i32* %c, i32 3 + store i32 -1, i32* %3, align 4 + %4 = getelementptr inbounds i32* %c, i32 4 + store i32 -1, i32* %4, align 4 +; CHECK: @test7 +; CHECK: call void @llvm.memset.p0i8.i64(i8* %5, i8 -1, i64 20, i32 4, i1 false) + ret void +} From bob.wilson at apple.com Mon Dec 5 16:42:45 2011 From: bob.wilson at apple.com (Bob Wilson) Date: Mon, 05 Dec 2011 14:42:45 -0800 Subject: [llvm-commits] [llvm] r145865 - in /llvm/trunk: lib/Transforms/Scalar/MemCpyOptimizer.cpp test/Transforms/MemCpyOpt/form-memset.ll In-Reply-To: <20111205223700.8EE422A6C12C@llvm.org> References: <20111205223700.8EE422A6C12C@llvm.org> Message-ID: I think you meant On Dec 5, 2011, at 2:37 PM, Chad Rosier wrote: > Author: mcrosier > Date: Mon Dec 5 16:37:00 2011 > New Revision: 145865 > > URL: http://llvm.org/viewvc/llvm-project?rev=145865&view=rev > Log: > Make the MemCpyOptimizer a bit more aggressive. I can't think of a scenerio > where this would be bad as the backend shouldn't have a problem inlining small > memcpys. > rdar://10510150 > > Modified: > llvm/trunk/lib/Transforms/Scalar/MemCpyOptimizer.cpp > llvm/trunk/test/Transforms/MemCpyOpt/form-memset.ll > > Modified: llvm/trunk/lib/Transforms/Scalar/MemCpyOptimizer.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/MemCpyOptimizer.cpp?rev=145865&r1=145864&r2=145865&view=diff > ============================================================================== > --- llvm/trunk/lib/Transforms/Scalar/MemCpyOptimizer.cpp (original) > +++ llvm/trunk/lib/Transforms/Scalar/MemCpyOptimizer.cpp Mon Dec 5 16:37:00 2011 > @@ -148,7 +148,7 @@ > > bool MemsetRange::isProfitableToUseMemset(const TargetData &TD) const { > // If we found more than 8 stores to merge or 64 bytes, use memset. > - if (TheStores.size() >= 8 || End-Start >= 64) return true; > + if (TheStores.size() >= 4 || End-Start >= 16) return true; > > // If there is nothing to merge, don't do anything. > if (TheStores.size() < 2) return false; > > Modified: llvm/trunk/test/Transforms/MemCpyOpt/form-memset.ll > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/MemCpyOpt/form-memset.ll?rev=145865&r1=145864&r2=145865&view=diff > ============================================================================== > --- llvm/trunk/test/Transforms/MemCpyOpt/form-memset.ll (original) > +++ llvm/trunk/test/Transforms/MemCpyOpt/form-memset.ll Mon Dec 5 16:37:00 2011 > @@ -57,8 +57,8 @@ > > declare i32 @bar(...) > > +%struct.MV = type { i16, i16 } > > - %struct.MV = type { i16, i16 } > > define void @test2() nounwind { > entry: > @@ -220,3 +220,19 @@ > ; CHECK: call void @llvm.memset.p0i8.i64(i8* %2, i8 0, i64 24, i32 1, i1 false) > } > > +; More aggressive heuristic > +; rdar://9892684 > +define void @test7(i32* nocapture %c) nounwind optsize { > + store i32 -1, i32* %c, align 4 > + %1 = getelementptr inbounds i32* %c, i32 1 > + store i32 -1, i32* %1, align 4 > + %2 = getelementptr inbounds i32* %c, i32 2 > + store i32 -1, i32* %2, align 4 > + %3 = getelementptr inbounds i32* %c, i32 3 > + store i32 -1, i32* %3, align 4 > + %4 = getelementptr inbounds i32* %c, i32 4 > + store i32 -1, i32* %4, align 4 > +; CHECK: @test7 > +; CHECK: call void @llvm.memset.p0i8.i64(i8* %5, i8 -1, i64 20, i32 4, i1 false) > + ret void > +} > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From mcrosier at apple.com Mon Dec 5 16:50:01 2011 From: mcrosier at apple.com (Chad Rosier) Date: Mon, 05 Dec 2011 14:50:01 -0800 Subject: [llvm-commits] [llvm] r145865 - in /llvm/trunk: lib/Transforms/Scalar/MemCpyOptimizer.cpp test/Transforms/MemCpyOpt/form-memset.ll In-Reply-To: <8A7D3AC4-6389-4260-8E5A-61A9C47FB9A4@apple.com> References: <20111205223700.8EE422A6C12C@llvm.org> <8A7D3AC4-6389-4260-8E5A-61A9C47FB9A4@apple.com> Message-ID: Yes, juggling too many things at once. Will do. Chad On Dec 5, 2011, at 2:44 PM, Bob Wilson wrote: > > On Dec 5, 2011, at 2:42 PM, Bob Wilson wrote: > >> I think you meant >> >> On Dec 5, 2011, at 2:37 PM, Chad Rosier wrote: >> >>> Author: mcrosier >>> Date: Mon Dec 5 16:37:00 2011 >>> New Revision: 145865 >>> >>> URL: http://llvm.org/viewvc/llvm-project?rev=145865&view=rev >>> Log: >>> Make the MemCpyOptimizer a bit more aggressive. I can't think of a scenerio >>> where this would be bad as the backend shouldn't have a problem inlining small >>> memcpys. >>> rdar://10510150 >>> >>> Modified: >>> llvm/trunk/lib/Transforms/Scalar/MemCpyOptimizer.cpp >>> llvm/trunk/test/Transforms/MemCpyOpt/form-memset.ll >>> >>> Modified: llvm/trunk/lib/Transforms/Scalar/MemCpyOptimizer.cpp >>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/MemCpyOptimizer.cpp?rev=145865&r1=145864&r2=145865&view=diff >>> ============================================================================== >>> --- llvm/trunk/lib/Transforms/Scalar/MemCpyOptimizer.cpp (original) >>> +++ llvm/trunk/lib/Transforms/Scalar/MemCpyOptimizer.cpp Mon Dec 5 16:37:00 2011 >>> @@ -148,7 +148,7 @@ >>> >>> bool MemsetRange::isProfitableToUseMemset(const TargetData &TD) const { >>> // If we found more than 8 stores to merge or 64 bytes, use memset. >>> - if (TheStores.size() >= 8 || End-Start >= 64) return true; >>> + if (TheStores.size() >= 4 || End-Start >= 16) return true; > > ?and please update the comment to match. From mcrosier at apple.com Mon Dec 5 16:53:09 2011 From: mcrosier at apple.com (Chad Rosier) Date: Mon, 05 Dec 2011 22:53:09 -0000 Subject: [llvm-commits] [llvm] r145866 - /llvm/trunk/lib/Transforms/Scalar/MemCpyOptimizer.cpp Message-ID: <20111205225309.442522A6C12C@llvm.org> Author: mcrosier Date: Mon Dec 5 16:53:09 2011 New Revision: 145866 URL: http://llvm.org/viewvc/llvm-project?rev=145866&view=rev Log: Update comment. Modified: llvm/trunk/lib/Transforms/Scalar/MemCpyOptimizer.cpp Modified: llvm/trunk/lib/Transforms/Scalar/MemCpyOptimizer.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/MemCpyOptimizer.cpp?rev=145866&r1=145865&r2=145866&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Scalar/MemCpyOptimizer.cpp (original) +++ llvm/trunk/lib/Transforms/Scalar/MemCpyOptimizer.cpp Mon Dec 5 16:53:09 2011 @@ -147,7 +147,7 @@ } // end anon namespace bool MemsetRange::isProfitableToUseMemset(const TargetData &TD) const { - // If we found more than 8 stores to merge or 64 bytes, use memset. + // If we found more than 4 stores to merge or 16 bytes, use memset. if (TheStores.size() >= 4 || End-Start >= 16) return true; // If there is nothing to merge, don't do anything. From bob.wilson at apple.com Mon Dec 5 16:44:54 2011 From: bob.wilson at apple.com (Bob Wilson) Date: Mon, 05 Dec 2011 14:44:54 -0800 Subject: [llvm-commits] [llvm] r145865 - in /llvm/trunk: lib/Transforms/Scalar/MemCpyOptimizer.cpp test/Transforms/MemCpyOpt/form-memset.ll In-Reply-To: References: <20111205223700.8EE422A6C12C@llvm.org> Message-ID: <8A7D3AC4-6389-4260-8E5A-61A9C47FB9A4@apple.com> On Dec 5, 2011, at 2:42 PM, Bob Wilson wrote: > I think you meant > > On Dec 5, 2011, at 2:37 PM, Chad Rosier wrote: > >> Author: mcrosier >> Date: Mon Dec 5 16:37:00 2011 >> New Revision: 145865 >> >> URL: http://llvm.org/viewvc/llvm-project?rev=145865&view=rev >> Log: >> Make the MemCpyOptimizer a bit more aggressive. I can't think of a scenerio >> where this would be bad as the backend shouldn't have a problem inlining small >> memcpys. >> rdar://10510150 >> >> Modified: >> llvm/trunk/lib/Transforms/Scalar/MemCpyOptimizer.cpp >> llvm/trunk/test/Transforms/MemCpyOpt/form-memset.ll >> >> Modified: llvm/trunk/lib/Transforms/Scalar/MemCpyOptimizer.cpp >> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/MemCpyOptimizer.cpp?rev=145865&r1=145864&r2=145865&view=diff >> ============================================================================== >> --- llvm/trunk/lib/Transforms/Scalar/MemCpyOptimizer.cpp (original) >> +++ llvm/trunk/lib/Transforms/Scalar/MemCpyOptimizer.cpp Mon Dec 5 16:37:00 2011 >> @@ -148,7 +148,7 @@ >> >> bool MemsetRange::isProfitableToUseMemset(const TargetData &TD) const { >> // If we found more than 8 stores to merge or 64 bytes, use memset. >> - if (TheStores.size() >= 8 || End-Start >= 64) return true; >> + if (TheStores.size() >= 4 || End-Start >= 16) return true; ?and please update the comment to match. From nicholas at mxc.ca Mon Dec 5 17:07:06 2011 From: nicholas at mxc.ca (Nick Lewycky) Date: Mon, 05 Dec 2011 23:07:06 -0000 Subject: [llvm-commits] [llvm] r145869 - in /llvm/trunk: include/llvm/ADT/Statistic.h lib/Support/Statistic.cpp Message-ID: <20111205230706.14E252A6C12C@llvm.org> Author: nicholas Date: Mon Dec 5 17:07:05 2011 New Revision: 145869 URL: http://llvm.org/viewvc/llvm-project?rev=145869&view=rev Log: Silence tsan false-positives (tsan can't track things which are only safe due to memory fences) in statistics registration, which works the same way that ManagedStatic registration does. Modified: llvm/trunk/include/llvm/ADT/Statistic.h llvm/trunk/lib/Support/Statistic.cpp Modified: llvm/trunk/include/llvm/ADT/Statistic.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/ADT/Statistic.h?rev=145869&r1=145868&r2=145869&view=diff ============================================================================== --- llvm/trunk/include/llvm/ADT/Statistic.h (original) +++ llvm/trunk/include/llvm/ADT/Statistic.h Mon Dec 5 17:07:05 2011 @@ -27,6 +27,7 @@ #define LLVM_ADT_STATISTIC_H #include "llvm/Support/Atomic.h" +#include "llvm/Support/Valgrind.h" namespace llvm { class raw_ostream; @@ -110,6 +111,7 @@ bool tmp = Initialized; sys::MemoryFence(); if (!tmp) RegisterStatistic(); + TsanHappensAfter(this); return *this; } void RegisterStatistic(); Modified: llvm/trunk/lib/Support/Statistic.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Support/Statistic.cpp?rev=145869&r1=145868&r2=145869&view=diff ============================================================================== --- llvm/trunk/lib/Support/Statistic.cpp (original) +++ llvm/trunk/lib/Support/Statistic.cpp Mon Dec 5 17:07:05 2011 @@ -73,9 +73,12 @@ if (Enabled) StatInfo->addStatistic(this); + TsanHappensBefore(this); sys::MemoryFence(); // Remember we have been registered. + TsanIgnoreWritesBegin(); Initialized = true; + TsanIgnoreWritesEnd(); } } From grosbach at apple.com Mon Dec 5 17:20:14 2011 From: grosbach at apple.com (Jim Grosbach) Date: Mon, 05 Dec 2011 23:20:14 -0000 Subject: [llvm-commits] [llvm] r145870 - /llvm/trunk/tools/llvm-mc/llvm-mc.cpp Message-ID: <20111205232014.515452A6C12C@llvm.org> Author: grosbach Date: Mon Dec 5 17:20:14 2011 New Revision: 145870 URL: http://llvm.org/viewvc/llvm-project?rev=145870&view=rev Log: Tidy up. Modified: llvm/trunk/tools/llvm-mc/llvm-mc.cpp Modified: llvm/trunk/tools/llvm-mc/llvm-mc.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvm-mc/llvm-mc.cpp?rev=145870&r1=145869&r2=145870&view=diff ============================================================================== --- llvm/trunk/tools/llvm-mc/llvm-mc.cpp (original) +++ llvm/trunk/tools/llvm-mc/llvm-mc.cpp Mon Dec 5 17:20:14 2011 @@ -418,7 +418,7 @@ /*useCFI*/ true, /*useDwarfDirectory*/ true, IP, CE, MAB, ShowInst)); - + } else if (FileType == OFT_Null) { Str.reset(createNullStreamer(Ctx)); } else { From grosbach at apple.com Mon Dec 5 17:45:46 2011 From: grosbach at apple.com (Jim Grosbach) Date: Mon, 05 Dec 2011 23:45:46 -0000 Subject: [llvm-commits] [llvm] r145871 - /llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp Message-ID: <20111205234547.036AA2A6C12C@llvm.org> Author: grosbach Date: Mon Dec 5 17:45:46 2011 New Revision: 145871 URL: http://llvm.org/viewvc/llvm-project?rev=145871&view=rev Log: Simple branch relaxation for Thumb2 Bcc instructions. Not right yet, as the rules for when to relax in the MCAssembler aren't (yet) correct for ARM. This is a step in the proper direction, though. Modified: llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp Modified: llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp?rev=145871&r1=145870&r2=145871&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp (original) +++ llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp Mon Dec 5 17:45:46 2011 @@ -124,14 +124,35 @@ }; } // end anonymous namespace +static unsigned getRelaxedOpcode(unsigned Op) { + switch (Op) { + default: return Op; + case ARM::tBcc: return ARM::t2Bcc; + } +} + bool ARMAsmBackend::MayNeedRelaxation(const MCInst &Inst) const { - // FIXME: Thumb targets, different move constant targets.. + if (getRelaxedOpcode(Inst.getOpcode()) != Inst.getOpcode()) + return true; return false; } void ARMAsmBackend::RelaxInstruction(const MCInst &Inst, MCInst &Res) const { - assert(0 && "ARMAsmBackend::RelaxInstruction() unimplemented"); - return; + unsigned RelaxedOp = getRelaxedOpcode(Inst.getOpcode()); + + // Sanity check w/ diagnostic if we get here w/ a bogus instruction. + if (RelaxedOp == Inst.getOpcode()) { + SmallString<256> Tmp; + raw_svector_ostream OS(Tmp); + Inst.dump_pretty(OS); + OS << "\n"; + report_fatal_error("unexpected instruction to relax: " + OS.str()); + } + + // The instructions we're relaxing have (so far) the same operands. + // We just need to update to the proper opcode. + Res = Inst; + Res.setOpcode(RelaxedOp); } bool ARMAsmBackend::WriteNopData(uint64_t Count, MCObjectWriter *OW) const { From grosbach at apple.com Mon Dec 5 18:03:48 2011 From: grosbach at apple.com (Jim Grosbach) Date: Tue, 06 Dec 2011 00:03:48 -0000 Subject: [llvm-commits] [llvm] r145873 - in /llvm/trunk: include/llvm/MC/MCAssembler.h lib/MC/ELFObjectWriter.cpp lib/MC/MCAssembler.cpp lib/MC/MachObjectWriter.cpp lib/MC/WinCOFFObjectWriter.cpp Message-ID: <20111206000348.6D9012A6C12C@llvm.org> Author: grosbach Date: Mon Dec 5 18:03:48 2011 New Revision: 145873 URL: http://llvm.org/viewvc/llvm-project?rev=145873&view=rev Log: Switch MCAssembler to method names starting w/ lower-case. per http://llvm.org/docs/CodingStandards.html#ll_naming Modified: llvm/trunk/include/llvm/MC/MCAssembler.h llvm/trunk/lib/MC/ELFObjectWriter.cpp llvm/trunk/lib/MC/MCAssembler.cpp llvm/trunk/lib/MC/MachObjectWriter.cpp llvm/trunk/lib/MC/WinCOFFObjectWriter.cpp Modified: llvm/trunk/include/llvm/MC/MCAssembler.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/MC/MCAssembler.h?rev=145873&r1=145872&r2=145873&view=diff ============================================================================== --- llvm/trunk/include/llvm/MC/MCAssembler.h (original) +++ llvm/trunk/include/llvm/MC/MCAssembler.h Mon Dec 5 18:03:48 2011 @@ -711,43 +711,43 @@ /// \return Whether the fixup value was fully resolved. This is true if the /// \arg Value result is fixed, otherwise the value may change due to /// relocation. - bool EvaluateFixup(const MCAsmLayout &Layout, + bool evaluateFixup(const MCAsmLayout &Layout, const MCFixup &Fixup, const MCFragment *DF, MCValue &Target, uint64_t &Value) const; /// Check whether a fixup can be satisfied, or whether it needs to be relaxed /// (increased in size, in order to hold its value correctly). - bool FixupNeedsRelaxation(const MCFixup &Fixup, const MCFragment *DF, + bool fixupNeedsRelaxation(const MCFixup &Fixup, const MCFragment *DF, const MCAsmLayout &Layout) const; /// Check whether the given fragment needs relaxation. - bool FragmentNeedsRelaxation(const MCInstFragment *IF, + bool fragmentNeedsRelaxation(const MCInstFragment *IF, const MCAsmLayout &Layout) const; - /// LayoutOnce - Perform one layout iteration and return true if any offsets + /// layoutOnce - Perform one layout iteration and return true if any offsets /// were adjusted. - bool LayoutOnce(MCAsmLayout &Layout); + bool layoutOnce(MCAsmLayout &Layout); - bool LayoutSectionOnce(MCAsmLayout &Layout, MCSectionData &SD); + bool layoutSectionOnce(MCAsmLayout &Layout, MCSectionData &SD); - bool RelaxInstruction(MCAsmLayout &Layout, MCInstFragment &IF); + bool relaxInstruction(MCAsmLayout &Layout, MCInstFragment &IF); - bool RelaxLEB(MCAsmLayout &Layout, MCLEBFragment &IF); + bool relaxLEB(MCAsmLayout &Layout, MCLEBFragment &IF); - bool RelaxDwarfLineAddr(MCAsmLayout &Layout, MCDwarfLineAddrFragment &DF); - bool RelaxDwarfCallFrameFragment(MCAsmLayout &Layout, + bool relaxDwarfLineAddr(MCAsmLayout &Layout, MCDwarfLineAddrFragment &DF); + bool relaxDwarfCallFrameFragment(MCAsmLayout &Layout, MCDwarfCallFrameFragment &DF); - /// FinishLayout - Finalize a layout, including fragment lowering. - void FinishLayout(MCAsmLayout &Layout); + /// finishLayout - Finalize a layout, including fragment lowering. + void finishLayout(MCAsmLayout &Layout); - uint64_t HandleFixup(const MCAsmLayout &Layout, + uint64_t handleFixup(const MCAsmLayout &Layout, MCFragment &F, const MCFixup &Fixup); public: /// Compute the effective fragment size assuming it is laid out at the given /// \arg SectionAddress and \arg FragmentOffset. - uint64_t ComputeFragmentSize(const MCAsmLayout &Layout, const MCFragment &F) const; + uint64_t computeFragmentSize(const MCAsmLayout &Layout, const MCFragment &F) const; /// Find the symbol which defines the atom containing the given symbol, or /// null if there is no such symbol. @@ -760,7 +760,7 @@ bool isSymbolLinkerVisible(const MCSymbol &SD) const; /// Emit the section contents using the given object writer. - void WriteSectionData(const MCSectionData *Section, + void writeSectionData(const MCSectionData *Section, const MCAsmLayout &Layout) const; /// Check whether a given symbol has been flagged with .thumb_func. Modified: llvm/trunk/lib/MC/ELFObjectWriter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/ELFObjectWriter.cpp?rev=145873&r1=145872&r2=145873&view=diff ============================================================================== --- llvm/trunk/lib/MC/ELFObjectWriter.cpp (original) +++ llvm/trunk/lib/MC/ELFObjectWriter.cpp Mon Dec 5 18:03:48 2011 @@ -1072,7 +1072,7 @@ WriteBytes(cast(F).getContents().str()); } } else { - Asm.WriteSectionData(&SD, Layout); + Asm.writeSectionData(&SD, Layout); } } Modified: llvm/trunk/lib/MC/MCAssembler.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCAssembler.cpp?rev=145873&r1=145872&r2=145873&view=diff ============================================================================== --- llvm/trunk/lib/MC/MCAssembler.cpp (original) +++ llvm/trunk/lib/MC/MCAssembler.cpp Mon Dec 5 18:03:48 2011 @@ -33,7 +33,7 @@ namespace { namespace stats { STATISTIC(EmittedFragments, "Number of emitted assembler fragments"); -STATISTIC(EvaluateFixup, "Number of evaluated fixups"); +STATISTIC(evaluateFixup, "Number of evaluated fixups"); STATISTIC(FragmentLayouts, "Number of fragment layouts"); STATISTIC(ObjectBytes, "Number of emitted object file bytes"); STATISTIC(RelaxationSteps, "Number of assembler layout and relaxation steps"); @@ -136,7 +136,7 @@ uint64_t MCAsmLayout::getSectionAddressSize(const MCSectionData *SD) const { // The size is the last fragment's end offset. const MCFragment &F = SD->getFragmentList().back(); - return getFragmentOffset(&F) + getAssembler().ComputeFragmentSize(*this, F); + return getFragmentOffset(&F) + getAssembler().computeFragmentSize(*this, F); } uint64_t MCAsmLayout::getSectionFileSize(const MCSectionData *SD) const { @@ -237,10 +237,10 @@ return SD->getFragment()->getAtom(); } -bool MCAssembler::EvaluateFixup(const MCAsmLayout &Layout, +bool MCAssembler::evaluateFixup(const MCAsmLayout &Layout, const MCFixup &Fixup, const MCFragment *DF, MCValue &Target, uint64_t &Value) const { - ++stats::EvaluateFixup; + ++stats::evaluateFixup; if (!Fixup.getValue()->EvaluateAsRelocatable(Target, Layout)) report_fatal_error("expected relocatable expression"); @@ -312,7 +312,7 @@ return IsResolved; } -uint64_t MCAssembler::ComputeFragmentSize(const MCAsmLayout &Layout, +uint64_t MCAssembler::computeFragmentSize(const MCAsmLayout &Layout, const MCFragment &F) const { switch (F.getKind()) { case MCFragment::FT_Data: @@ -374,7 +374,7 @@ // Compute fragment offset and size. uint64_t Offset = 0; if (Prev) - Offset += Prev->Offset + getAssembler().ComputeFragmentSize(*this, *Prev); + Offset += Prev->Offset + getAssembler().computeFragmentSize(*this, *Prev); F->Offset = Offset; LastValidFragment[F->getParent()] = F; @@ -390,7 +390,7 @@ ++stats::EmittedFragments; // FIXME: Embed in fragments instead? - uint64_t FragmentSize = Asm.ComputeFragmentSize(Layout, F); + uint64_t FragmentSize = Asm.computeFragmentSize(Layout, F); switch (F.getKind()) { case MCFragment::FT_Align: { MCAlignFragment &AF = cast(F); @@ -493,7 +493,7 @@ assert(OW->getStream().tell() - Start == FragmentSize); } -void MCAssembler::WriteSectionData(const MCSectionData *SD, +void MCAssembler::writeSectionData(const MCSectionData *SD, const MCAsmLayout &Layout) const { // Ignore virtual sections. if (SD->getSection().isVirtualSection()) { @@ -546,13 +546,13 @@ } -uint64_t MCAssembler::HandleFixup(const MCAsmLayout &Layout, +uint64_t MCAssembler::handleFixup(const MCAsmLayout &Layout, MCFragment &F, const MCFixup &Fixup) { // Evaluate the fixup. MCValue Target; uint64_t FixedValue; - if (!EvaluateFixup(Layout, Fixup, &F, Target, FixedValue)) { + if (!evaluateFixup(Layout, Fixup, &F, Target, FixedValue)) { // The fixup was unresolved, we need a relocation. Inform the object // writer of the relocation, and give it an opportunity to adjust the // fixup value if need be. @@ -592,7 +592,7 @@ } // Layout until everything fits. - while (LayoutOnce(Layout)) + while (layoutOnce(Layout)) continue; DEBUG_WITH_TYPE("mc-dump", { @@ -600,7 +600,7 @@ dump(); }); // Finalize the layout, including fragment lowering. - FinishLayout(Layout); + finishLayout(Layout); DEBUG_WITH_TYPE("mc-dump", { llvm::errs() << "assembler backend - final-layout\n--\n"; @@ -621,7 +621,7 @@ for (MCDataFragment::fixup_iterator it3 = DF->fixup_begin(), ie3 = DF->fixup_end(); it3 != ie3; ++it3) { MCFixup &Fixup = *it3; - uint64_t FixedValue = HandleFixup(Layout, *DF, Fixup); + uint64_t FixedValue = handleFixup(Layout, *DF, Fixup); getBackend().ApplyFixup(Fixup, DF->getContents().data(), DF->getContents().size(), FixedValue); } @@ -631,7 +631,7 @@ for (MCInstFragment::fixup_iterator it3 = IF->fixup_begin(), ie3 = IF->fixup_end(); it3 != ie3; ++it3) { MCFixup &Fixup = *it3; - uint64_t FixedValue = HandleFixup(Layout, *IF, Fixup); + uint64_t FixedValue = handleFixup(Layout, *IF, Fixup); getBackend().ApplyFixup(Fixup, IF->getCode().data(), IF->getCode().size(), FixedValue); } @@ -645,7 +645,7 @@ stats::ObjectBytes += OS.tell() - StartOffset; } -bool MCAssembler::FixupNeedsRelaxation(const MCFixup &Fixup, +bool MCAssembler::fixupNeedsRelaxation(const MCFixup &Fixup, const MCFragment *DF, const MCAsmLayout &Layout) const { if (getRelaxAll()) @@ -654,7 +654,7 @@ // If we cannot resolve the fixup value, it requires relaxation. MCValue Target; uint64_t Value; - if (!EvaluateFixup(Layout, Fixup, DF, Target, Value)) + if (!evaluateFixup(Layout, Fixup, DF, Target, Value)) return true; // Otherwise, relax if the value is too big for a (signed) i8. @@ -663,7 +663,7 @@ return int64_t(Value) != int64_t(int8_t(Value)); } -bool MCAssembler::FragmentNeedsRelaxation(const MCInstFragment *IF, +bool MCAssembler::fragmentNeedsRelaxation(const MCInstFragment *IF, const MCAsmLayout &Layout) const { // If this inst doesn't ever need relaxation, ignore it. This occurs when we // are intentionally pushing out inst fragments, or because we relaxed a @@ -673,15 +673,15 @@ for (MCInstFragment::const_fixup_iterator it = IF->fixup_begin(), ie = IF->fixup_end(); it != ie; ++it) - if (FixupNeedsRelaxation(*it, IF, Layout)) + if (fixupNeedsRelaxation(*it, IF, Layout)) return true; return false; } -bool MCAssembler::RelaxInstruction(MCAsmLayout &Layout, +bool MCAssembler::relaxInstruction(MCAsmLayout &Layout, MCInstFragment &IF) { - if (!FragmentNeedsRelaxation(&IF, Layout)) + if (!fragmentNeedsRelaxation(&IF, Layout)) return false; ++stats::RelaxedInstructions; @@ -715,7 +715,7 @@ return true; } -bool MCAssembler::RelaxLEB(MCAsmLayout &Layout, MCLEBFragment &LF) { +bool MCAssembler::relaxLEB(MCAsmLayout &Layout, MCLEBFragment &LF) { int64_t Value = 0; uint64_t OldSize = LF.getContents().size(); bool IsAbs = LF.getValue().EvaluateAsAbsolute(Value, Layout); @@ -732,7 +732,7 @@ return OldSize != LF.getContents().size(); } -bool MCAssembler::RelaxDwarfLineAddr(MCAsmLayout &Layout, +bool MCAssembler::relaxDwarfLineAddr(MCAsmLayout &Layout, MCDwarfLineAddrFragment &DF) { int64_t AddrDelta = 0; uint64_t OldSize = DF.getContents().size(); @@ -749,7 +749,7 @@ return OldSize != Data.size(); } -bool MCAssembler::RelaxDwarfCallFrameFragment(MCAsmLayout &Layout, +bool MCAssembler::relaxDwarfCallFrameFragment(MCAsmLayout &Layout, MCDwarfCallFrameFragment &DF) { int64_t AddrDelta = 0; uint64_t OldSize = DF.getContents().size(); @@ -764,7 +764,7 @@ return OldSize != Data.size(); } -bool MCAssembler::LayoutSectionOnce(MCAsmLayout &Layout, +bool MCAssembler::layoutSectionOnce(MCAsmLayout &Layout, MCSectionData &SD) { MCFragment *FirstInvalidFragment = NULL; // Scan for fragments that need relaxation. @@ -776,19 +776,19 @@ default: break; case MCFragment::FT_Inst: - relaxedFrag = RelaxInstruction(Layout, *cast(it2)); + relaxedFrag = relaxInstruction(Layout, *cast(it2)); break; case MCFragment::FT_Dwarf: - relaxedFrag = RelaxDwarfLineAddr(Layout, + relaxedFrag = relaxDwarfLineAddr(Layout, *cast(it2)); break; case MCFragment::FT_DwarfFrame: relaxedFrag = - RelaxDwarfCallFrameFragment(Layout, + relaxDwarfCallFrameFragment(Layout, *cast(it2)); break; case MCFragment::FT_LEB: - relaxedFrag = RelaxLEB(Layout, *cast(it2)); + relaxedFrag = relaxLEB(Layout, *cast(it2)); break; } // Update the layout, and remember that we relaxed. @@ -802,20 +802,20 @@ return false; } -bool MCAssembler::LayoutOnce(MCAsmLayout &Layout) { +bool MCAssembler::layoutOnce(MCAsmLayout &Layout) { ++stats::RelaxationSteps; bool WasRelaxed = false; for (iterator it = begin(), ie = end(); it != ie; ++it) { MCSectionData &SD = *it; - while(LayoutSectionOnce(Layout, SD)) + while(layoutSectionOnce(Layout, SD)) WasRelaxed = true; } return WasRelaxed; } -void MCAssembler::FinishLayout(MCAsmLayout &Layout) { +void MCAssembler::finishLayout(MCAsmLayout &Layout) { // The layout is done. Mark every fragment as valid. for (unsigned int i = 0, n = Layout.getSectionOrder().size(); i != n; ++i) { Layout.getFragmentOffset(&*Layout.getSectionOrder()[i]->rbegin()); Modified: llvm/trunk/lib/MC/MachObjectWriter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MachObjectWriter.cpp?rev=145873&r1=145872&r2=145873&view=diff ============================================================================== --- llvm/trunk/lib/MC/MachObjectWriter.cpp (original) +++ llvm/trunk/lib/MC/MachObjectWriter.cpp Mon Dec 5 18:03:48 2011 @@ -731,7 +731,7 @@ // Write the actual section data. for (MCAssembler::const_iterator it = Asm.begin(), ie = Asm.end(); it != ie; ++it) { - Asm.WriteSectionData(it, Layout); + Asm.writeSectionData(it, Layout); uint64_t Pad = getPaddingSize(it, Layout); for (unsigned int i = 0; i < Pad; ++i) Modified: llvm/trunk/lib/MC/WinCOFFObjectWriter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/WinCOFFObjectWriter.cpp?rev=145873&r1=145872&r2=145873&view=diff ============================================================================== --- llvm/trunk/lib/MC/WinCOFFObjectWriter.cpp (original) +++ llvm/trunk/lib/MC/WinCOFFObjectWriter.cpp Mon Dec 5 18:03:48 2011 @@ -850,7 +850,7 @@ assert(OS.tell() == (*i)->Header.PointerToRawData && "Section::PointerToRawData is insane!"); - Asm.WriteSectionData(j, Layout); + Asm.writeSectionData(j, Layout); } if ((*i)->Relocations.size() > 0) { From grosbach at apple.com Mon Dec 5 18:11:13 2011 From: grosbach at apple.com (Jim Grosbach) Date: Tue, 06 Dec 2011 00:11:13 -0000 Subject: [llvm-commits] [llvm] r145875 - /llvm/trunk/include/llvm/MC/MCAssembler.h Message-ID: <20111206001113.F0E612A6C12C@llvm.org> Author: grosbach Date: Mon Dec 5 18:11:13 2011 New Revision: 145875 URL: http://llvm.org/viewvc/llvm-project?rev=145875&view=rev Log: Tidy up. 80 columns. Modified: llvm/trunk/include/llvm/MC/MCAssembler.h Modified: llvm/trunk/include/llvm/MC/MCAssembler.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/MC/MCAssembler.h?rev=145875&r1=145874&r2=145875&view=diff ============================================================================== --- llvm/trunk/include/llvm/MC/MCAssembler.h (original) +++ llvm/trunk/include/llvm/MC/MCAssembler.h Mon Dec 5 18:11:13 2011 @@ -747,7 +747,8 @@ public: /// Compute the effective fragment size assuming it is laid out at the given /// \arg SectionAddress and \arg FragmentOffset. - uint64_t computeFragmentSize(const MCAsmLayout &Layout, const MCFragment &F) const; + uint64_t computeFragmentSize(const MCAsmLayout &Layout, + const MCFragment &F) const; /// Find the symbol which defines the atom containing the given symbol, or /// null if there is no such symbol. From nicholas at mxc.ca Mon Dec 5 18:11:58 2011 From: nicholas at mxc.ca (Nick Lewycky) Date: Tue, 06 Dec 2011 00:11:58 -0000 Subject: [llvm-commits] [llvm] r145876 - /llvm/trunk/include/llvm/LinkAllPasses.h Message-ID: <20111206001158.8B47F2A6C12C@llvm.org> Author: nicholas Date: Mon Dec 5 18:11:58 2011 New Revision: 145876 URL: http://llvm.org/viewvc/llvm-project?rev=145876&view=rev Log: All these arguments are default anyways. Modified: llvm/trunk/include/llvm/LinkAllPasses.h Modified: llvm/trunk/include/llvm/LinkAllPasses.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/LinkAllPasses.h?rev=145876&r1=145875&r2=145876&view=diff ============================================================================== --- llvm/trunk/include/llvm/LinkAllPasses.h (original) +++ llvm/trunk/include/llvm/LinkAllPasses.h Mon Dec 5 18:11:58 2011 @@ -69,7 +69,7 @@ (void) llvm::createEdgeProfilerPass(); (void) llvm::createOptimalEdgeProfilerPass(); (void) llvm::createPathProfilerPass(); - (void) llvm::createGCOVProfilerPass(true, true, false); + (void) llvm::createGCOVProfilerPass(); (void) llvm::createFunctionInliningPass(); (void) llvm::createAlwaysInlinerPass(); (void) llvm::createGlobalDCEPass(); From grosbach at apple.com Mon Dec 5 18:12:13 2011 From: grosbach at apple.com (Jim Grosbach) Date: Tue, 06 Dec 2011 00:12:13 -0000 Subject: [llvm-commits] [llvm] r145877 - /llvm/trunk/include/llvm/MC/MCStreamer.h Message-ID: <20111206001213.376F62A6C12C@llvm.org> Author: grosbach Date: Mon Dec 5 18:12:12 2011 New Revision: 145877 URL: http://llvm.org/viewvc/llvm-project?rev=145877&view=rev Log: Tidy up. Hard tabs. Modified: llvm/trunk/include/llvm/MC/MCStreamer.h Modified: llvm/trunk/include/llvm/MC/MCStreamer.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/MC/MCStreamer.h?rev=145877&r1=145876&r2=145877&view=diff ============================================================================== --- llvm/trunk/include/llvm/MC/MCStreamer.h (original) +++ llvm/trunk/include/llvm/MC/MCStreamer.h Mon Dec 5 18:12:12 2011 @@ -641,8 +641,8 @@ /// createELFStreamer - Create a machine code streamer which will generate /// ELF format object files. MCStreamer *createELFStreamer(MCContext &Ctx, MCAsmBackend &TAB, - raw_ostream &OS, MCCodeEmitter *CE, - bool RelaxAll, bool NoExecStack); + raw_ostream &OS, MCCodeEmitter *CE, + bool RelaxAll, bool NoExecStack); /// createLoggingStreamer - Create a machine code streamer which just logs the /// API calls and then dispatches to another streamer. From grosbach at apple.com Mon Dec 5 18:13:10 2011 From: grosbach at apple.com (Jim Grosbach) Date: Tue, 06 Dec 2011 00:13:10 -0000 Subject: [llvm-commits] [llvm] r145878 - in /llvm/trunk/lib/MC: ELFObjectWriter.cpp MCAssembler.cpp MachObjectWriter.cpp Message-ID: <20111206001310.2D9292A6C12C@llvm.org> Author: grosbach Date: Mon Dec 5 18:13:09 2011 New Revision: 145878 URL: http://llvm.org/viewvc/llvm-project?rev=145878&view=rev Log: Tidy up. Hard tabs. Modified: llvm/trunk/lib/MC/ELFObjectWriter.cpp llvm/trunk/lib/MC/MCAssembler.cpp llvm/trunk/lib/MC/MachObjectWriter.cpp Modified: llvm/trunk/lib/MC/ELFObjectWriter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/ELFObjectWriter.cpp?rev=145878&r1=145877&r2=145878&view=diff ============================================================================== --- llvm/trunk/lib/MC/ELFObjectWriter.cpp (original) +++ llvm/trunk/lib/MC/ELFObjectWriter.cpp Mon Dec 5 18:13:09 2011 @@ -182,7 +182,7 @@ if (const MCExpr *Value = Symbol.getVariableValue()) { int64_t IntValue; if (Value->EvaluateAsAbsolute(IntValue, Layout)) - return (uint64_t)IntValue; + return (uint64_t)IntValue; } } Modified: llvm/trunk/lib/MC/MCAssembler.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCAssembler.cpp?rev=145878&r1=145877&r2=145878&view=diff ============================================================================== --- llvm/trunk/lib/MC/MCAssembler.cpp (original) +++ llvm/trunk/lib/MC/MCAssembler.cpp Mon Dec 5 18:13:09 2011 @@ -733,7 +733,7 @@ } bool MCAssembler::relaxDwarfLineAddr(MCAsmLayout &Layout, - MCDwarfLineAddrFragment &DF) { + MCDwarfLineAddrFragment &DF) { int64_t AddrDelta = 0; uint64_t OldSize = DF.getContents().size(); bool IsAbs = DF.getAddrDelta().EvaluateAsAbsolute(AddrDelta, Layout); Modified: llvm/trunk/lib/MC/MachObjectWriter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MachObjectWriter.cpp?rev=145878&r1=145877&r2=145878&view=diff ============================================================================== --- llvm/trunk/lib/MC/MachObjectWriter.cpp (original) +++ llvm/trunk/lib/MC/MachObjectWriter.cpp Mon Dec 5 18:13:09 2011 @@ -628,7 +628,7 @@ } void MachObjectWriter::WriteObject(MCAssembler &Asm, - const MCAsmLayout &Layout) { + const MCAsmLayout &Layout) { unsigned NumSections = Asm.size(); // The section data starts after the header, the segment load command (and From eli.friedman at gmail.com Mon Dec 5 18:20:30 2011 From: eli.friedman at gmail.com (Eli Friedman) Date: Mon, 5 Dec 2011 16:20:30 -0800 Subject: [llvm-commits] [LLVM, SelectionDAG] fix for #9905: Failure in code selection for llvm intrinsics sqrt/exp In-Reply-To: <4EDCC1A2.5010500@narod.ru> References: <4ED74593.2030003@narod.ru> <4ED9D140.2070504@narod.ru> <4EDCC1A2.5010500@narod.ru> Message-ID: The code changes look fine. Please put all the FileCheck tests into one file, and only use CHECK lines for the most important pieces (specifically, that we call sinf etc.). -Eli On Mon, Dec 5, 2011 at 5:05 AM, Stepan Dyatkovskiy wrote: > ping. > > -Stepan. > > Stepan Dyatkovskiy wrote: >> ping. >> >> -Stepan >> >> Stepan Dyatkovskiy wrote: >>> Hi all. Please find the patch and regression tests in attachment for >>> review. >>> This patch for ARM. It fixes selection for several instructions that >>> works with v4f32 arguments: FSQRT, FSIN, FCOS, FPOWI, FPOW, FLOG, FLOG2, >>> FLOG10, FEXP, FEXP2. >>> I'm still worrying about FCOPYSIGN, FNEG, FABS, FCEIL, FTRUNC, FRINT, >>> FNEARBYINT, FFLOOR. I could not found a way to add this instructions >>> with v2f32 argument to DAG. It seems that it is impossible in ToT. So >>> these instructions was not fixed. >>> >>> -Stepan. >>> >>> >>> _______________________________________________ >>> llvm-commits mailing list >>> llvm-commits at cs.uiuc.edu >>> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits >> >> _______________________________________________ >> llvm-commits mailing list >> llvm-commits at cs.uiuc.edu >> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From mcrosier at apple.com Mon Dec 5 18:19:08 2011 From: mcrosier at apple.com (Chad Rosier) Date: Tue, 06 Dec 2011 00:19:08 -0000 Subject: [llvm-commits] [llvm] r145879 - in /llvm/trunk: lib/Analysis/ValueTracking.cpp test/Transforms/MemCpyOpt/form-memset.ll Message-ID: <20111206001908.9814F2A6C12C@llvm.org> Author: mcrosier Date: Mon Dec 5 18:19:08 2011 New Revision: 145879 URL: http://llvm.org/viewvc/llvm-project?rev=145879&view=rev Log: Probably not a good idea to convert a single vector load into a memcpy. We don't do this now, but add a test case to prevent this from happening in the future. Additional test for rdar://9892684 Modified: llvm/trunk/lib/Analysis/ValueTracking.cpp llvm/trunk/test/Transforms/MemCpyOpt/form-memset.ll Modified: llvm/trunk/lib/Analysis/ValueTracking.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/ValueTracking.cpp?rev=145879&r1=145878&r2=145879&view=diff ============================================================================== --- llvm/trunk/lib/Analysis/ValueTracking.cpp (original) +++ llvm/trunk/lib/Analysis/ValueTracking.cpp Mon Dec 5 18:19:08 2011 @@ -1370,6 +1370,8 @@ return Val; } + + // FIXME: Vector types (e.g., <4 x i32> ). // Conceptually, we could handle things like: // %a = zext i8 %X to i16 Modified: llvm/trunk/test/Transforms/MemCpyOpt/form-memset.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/MemCpyOpt/form-memset.ll?rev=145879&r1=145878&r2=145879&view=diff ============================================================================== --- llvm/trunk/test/Transforms/MemCpyOpt/form-memset.ll (original) +++ llvm/trunk/test/Transforms/MemCpyOpt/form-memset.ll Mon Dec 5 18:19:08 2011 @@ -236,3 +236,15 @@ ; CHECK: call void @llvm.memset.p0i8.i64(i8* %5, i8 -1, i64 20, i32 4, i1 false) ret void } + +%struct.test8 = type { [4 x i32] } + +define void @test8() { +entry: + %memtmp = alloca %struct.test8, align 16 + %0 = bitcast %struct.test8* %memtmp to <4 x i32>* + store <4 x i32> , <4 x i32>* %0, align 16 + ret void +; CHECK: @test8 +; CHECK: store <4 x i32> , <4 x i32>* %0, align 16 +} From nicholas at mxc.ca Mon Dec 5 18:29:14 2011 From: nicholas at mxc.ca (Nick Lewycky) Date: Tue, 06 Dec 2011 00:29:14 -0000 Subject: [llvm-commits] [llvm] r145880 - in /llvm/trunk: include/llvm/Transforms/Instrumentation.h lib/Transforms/Instrumentation/GCOVProfiling.cpp Message-ID: <20111206002914.19BBC2A6C12C@llvm.org> Author: nicholas Date: Mon Dec 5 18:29:13 2011 New Revision: 145880 URL: http://llvm.org/viewvc/llvm-project?rev=145880&view=rev Log: Expose a switch for the new gcov format. Modified: llvm/trunk/include/llvm/Transforms/Instrumentation.h llvm/trunk/lib/Transforms/Instrumentation/GCOVProfiling.cpp Modified: llvm/trunk/include/llvm/Transforms/Instrumentation.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Transforms/Instrumentation.h?rev=145880&r1=145879&r2=145880&view=diff ============================================================================== --- llvm/trunk/include/llvm/Transforms/Instrumentation.h (original) +++ llvm/trunk/include/llvm/Transforms/Instrumentation.h Mon Dec 5 18:29:13 2011 @@ -29,7 +29,8 @@ // Insert GCOV profiling instrumentation ModulePass *createGCOVProfilerPass(bool EmitNotes = true, bool EmitData = true, - bool Use402Format = false); + bool Use402Format = false, + bool UseExtraChecksum = false); // Insert AddressSanitizer (address sanity checking) instrumentation ModulePass *createAddressSanitizerPass(); Modified: llvm/trunk/lib/Transforms/Instrumentation/GCOVProfiling.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Instrumentation/GCOVProfiling.cpp?rev=145880&r1=145879&r2=145880&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Instrumentation/GCOVProfiling.cpp (original) +++ llvm/trunk/lib/Transforms/Instrumentation/GCOVProfiling.cpp Mon Dec 5 18:29:13 2011 @@ -108,8 +108,9 @@ "Insert instrumentation for GCOV profiling", false, false) ModulePass *llvm::createGCOVProfilerPass(bool EmitNotes, bool EmitData, - bool Use402Format) { - return new GCOVProfiler(EmitNotes, EmitData, Use402Format); + bool Use402Format, + bool UseExtraChecksum) { + return new GCOVProfiler(EmitNotes, EmitData, Use402Format, UseExtraChecksum); } namespace { From grosbach at apple.com Mon Dec 5 18:47:04 2011 From: grosbach at apple.com (Jim Grosbach) Date: Tue, 06 Dec 2011 00:47:04 -0000 Subject: [llvm-commits] [llvm] r145881 - in /llvm/trunk: include/llvm/MC/MCAsmBackend.h include/llvm/MC/MCAssembler.h lib/MC/MCAssembler.cpp lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp lib/Target/MBlaze/MCTargetDesc/MBlazeAsmBackend.cpp lib/Target/Mips/MCTargetDesc/MipsAsmBackend.cpp lib/Target/PowerPC/MCTargetDesc/PPCAsmBackend.cpp lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp Message-ID: <20111206004704.347C72A6C12C@llvm.org> Author: grosbach Date: Mon Dec 5 18:47:03 2011 New Revision: 145881 URL: http://llvm.org/viewvc/llvm-project?rev=145881&view=rev Log: Move target-specific logic out of generic MCAssembler. Whether a fixup needs relaxation for the associated instruction is a target-specific function, as the FIXME indicated. Create a hook for that and use it. Modified: llvm/trunk/include/llvm/MC/MCAsmBackend.h llvm/trunk/include/llvm/MC/MCAssembler.h llvm/trunk/lib/MC/MCAssembler.cpp llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp llvm/trunk/lib/Target/MBlaze/MCTargetDesc/MBlazeAsmBackend.cpp llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsAsmBackend.cpp llvm/trunk/lib/Target/PowerPC/MCTargetDesc/PPCAsmBackend.cpp llvm/trunk/lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp Modified: llvm/trunk/include/llvm/MC/MCAsmBackend.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/MC/MCAsmBackend.h?rev=145881&r1=145880&r2=145881&view=diff ============================================================================== --- llvm/trunk/include/llvm/MC/MCAsmBackend.h (original) +++ llvm/trunk/include/llvm/MC/MCAsmBackend.h Mon Dec 5 18:47:03 2011 @@ -16,9 +16,11 @@ #include "llvm/Support/DataTypes.h" namespace llvm { +class MCAsmLayout; class MCELFObjectTargetWriter; class MCFixup; class MCInst; +class MCInstFragment; class MCObjectWriter; class MCSection; template @@ -104,6 +106,13 @@ /// \param Inst - The instruction to test. virtual bool MayNeedRelaxation(const MCInst &Inst) const = 0; + /// fixupNeedsRelaxation - Target specific predicate for whether a given + /// fixup requires the associated instruction to be relaxed. + virtual bool fixupNeedsRelaxation(const MCFixup &Fixup, + uint64_t Value, + const MCInstFragment *DF, + const MCAsmLayout &Layout) const = 0; + /// RelaxInstruction - Relax the instruction in the given fragment to the next /// wider instruction. /// Modified: llvm/trunk/include/llvm/MC/MCAssembler.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/MC/MCAssembler.h?rev=145881&r1=145880&r2=145881&view=diff ============================================================================== --- llvm/trunk/include/llvm/MC/MCAssembler.h (original) +++ llvm/trunk/include/llvm/MC/MCAssembler.h Mon Dec 5 18:47:03 2011 @@ -717,7 +717,7 @@ /// Check whether a fixup can be satisfied, or whether it needs to be relaxed /// (increased in size, in order to hold its value correctly). - bool fixupNeedsRelaxation(const MCFixup &Fixup, const MCFragment *DF, + bool fixupNeedsRelaxation(const MCFixup &Fixup, const MCInstFragment *DF, const MCAsmLayout &Layout) const; /// Check whether the given fragment needs relaxation. Modified: llvm/trunk/lib/MC/MCAssembler.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCAssembler.cpp?rev=145881&r1=145880&r2=145881&view=diff ============================================================================== --- llvm/trunk/lib/MC/MCAssembler.cpp (original) +++ llvm/trunk/lib/MC/MCAssembler.cpp Mon Dec 5 18:47:03 2011 @@ -646,7 +646,7 @@ } bool MCAssembler::fixupNeedsRelaxation(const MCFixup &Fixup, - const MCFragment *DF, + const MCInstFragment *DF, const MCAsmLayout &Layout) const { if (getRelaxAll()) return true; @@ -657,10 +657,7 @@ if (!evaluateFixup(Layout, Fixup, DF, Target, Value)) return true; - // Otherwise, relax if the value is too big for a (signed) i8. - // - // FIXME: This is target dependent! - return int64_t(Value) != int64_t(int8_t(Value)); + return getBackend().fixupNeedsRelaxation(Fixup, Value, DF, Layout); } bool MCAssembler::fragmentNeedsRelaxation(const MCInstFragment *IF, Modified: llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp?rev=145881&r1=145880&r2=145881&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp (original) +++ llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp Mon Dec 5 18:47:03 2011 @@ -102,6 +102,11 @@ bool MayNeedRelaxation(const MCInst &Inst) const; + bool fixupNeedsRelaxation(const MCFixup &Fixup, + uint64_t Value, + const MCInstFragment *DF, + const MCAsmLayout &Layout) const; + void RelaxInstruction(const MCInst &Inst, MCInst &Res) const; bool WriteNopData(uint64_t Count, MCObjectWriter *OW) const; @@ -137,6 +142,17 @@ return false; } +bool ARMAsmBackend::fixupNeedsRelaxation(const MCFixup &Fixup, + uint64_t Value, + const MCInstFragment *DF, + const MCAsmLayout &Layout) const { + // FIXME: This isn't correct for ARM. Just moving the "generic" logic + // into the targets for now. + // + // Relax if the value is too big for a (signed) i8. + return int64_t(Value) != int64_t(int8_t(Value)); +} + void ARMAsmBackend::RelaxInstruction(const MCInst &Inst, MCInst &Res) const { unsigned RelaxedOp = getRelaxedOpcode(Inst.getOpcode()); Modified: llvm/trunk/lib/Target/MBlaze/MCTargetDesc/MBlazeAsmBackend.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MBlaze/MCTargetDesc/MBlazeAsmBackend.cpp?rev=145881&r1=145880&r2=145881&view=diff ============================================================================== --- llvm/trunk/lib/Target/MBlaze/MCTargetDesc/MBlazeAsmBackend.cpp (original) +++ llvm/trunk/lib/Target/MBlaze/MCTargetDesc/MBlazeAsmBackend.cpp Mon Dec 5 18:47:03 2011 @@ -58,6 +58,11 @@ bool MayNeedRelaxation(const MCInst &Inst) const; + bool fixupNeedsRelaxation(const MCFixup &Fixup, + uint64_t Value, + const MCInstFragment *DF, + const MCAsmLayout &Layout) const; + void RelaxInstruction(const MCInst &Inst, MCInst &Res) const; bool WriteNopData(uint64_t Count, MCObjectWriter *OW) const; @@ -87,6 +92,18 @@ return hasExprOrImm; } +bool MBlazeAsmBackend::fixupNeedsRelaxation(const MCFixup &Fixup, + uint64_t Value, + const MCInstFragment *DF, + const MCAsmLayout &Layout) const { + // FIXME: Is this right? It's what the "generic" code was doing before, + // but is X86 specific. Is it actually true for MBlaze also, or was it + // just close enough to not be a big deal? + // + // Relax if the value is too big for a (signed) i8. + return int64_t(Value) != int64_t(int8_t(Value)); +} + void MBlazeAsmBackend::RelaxInstruction(const MCInst &Inst, MCInst &Res) const { Res = Inst; Res.setOpcode(getRelaxedOpcode(Inst.getOpcode())); Modified: llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsAsmBackend.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsAsmBackend.cpp?rev=145881&r1=145880&r2=145881&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsAsmBackend.cpp (original) +++ llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsAsmBackend.cpp Mon Dec 5 18:47:03 2011 @@ -173,6 +173,16 @@ return false; } + /// fixupNeedsRelaxation - Target specific predicate for whether a given + /// fixup requires the associated instruction to be relaxed. + bool fixupNeedsRelaxation(const MCFixup &Fixup, + uint64_t Value, + const MCInstFragment *DF, + const MCAsmLayout &Layout) const { + // FIXME. + assert(0 && "RelaxInstruction() unimplemented"); + } + /// RelaxInstruction - Relax the instruction in the given fragment /// to the next wider instruction. /// Modified: llvm/trunk/lib/Target/PowerPC/MCTargetDesc/PPCAsmBackend.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/MCTargetDesc/PPCAsmBackend.cpp?rev=145881&r1=145880&r2=145881&view=diff ============================================================================== --- llvm/trunk/lib/Target/PowerPC/MCTargetDesc/PPCAsmBackend.cpp (original) +++ llvm/trunk/lib/Target/PowerPC/MCTargetDesc/PPCAsmBackend.cpp Mon Dec 5 18:47:03 2011 @@ -93,6 +93,15 @@ // FIXME. return false; } + + bool fixupNeedsRelaxation(const MCFixup &Fixup, + uint64_t Value, + const MCInstFragment *DF, + const MCAsmLayout &Layout) const { + // FIXME. + assert(0 && "RelaxInstruction() unimplemented"); + } + void RelaxInstruction(const MCInst &Inst, MCInst &Res) const { // FIXME. Modified: llvm/trunk/lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp?rev=145881&r1=145880&r2=145881&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp (original) +++ llvm/trunk/lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp Mon Dec 5 18:47:03 2011 @@ -107,6 +107,11 @@ bool MayNeedRelaxation(const MCInst &Inst) const; + bool fixupNeedsRelaxation(const MCFixup &Fixup, + uint64_t Value, + const MCInstFragment *DF, + const MCAsmLayout &Layout) const; + void RelaxInstruction(const MCInst &Inst, MCInst &Res) const; bool WriteNopData(uint64_t Count, MCObjectWriter *OW) const; @@ -244,6 +249,14 @@ return hasExp && !hasRIP; } +bool X86AsmBackend::fixupNeedsRelaxation(const MCFixup &Fixup, + uint64_t Value, + const MCInstFragment *DF, + const MCAsmLayout &Layout) const { + // Relax if the value is too big for a (signed) i8. + return int64_t(Value) != int64_t(int8_t(Value)); +} + // FIXME: Can tblgen help at all here to verify there aren't other instructions // we can relax? void X86AsmBackend::RelaxInstruction(const MCInst &Inst, MCInst &Res) const { From stoklund at 2pi.dk Mon Dec 5 18:51:09 2011 From: stoklund at 2pi.dk (Jakob Stoklund Olesen) Date: Tue, 06 Dec 2011 00:51:09 -0000 Subject: [llvm-commits] [llvm] r145882 - /llvm/trunk/include/llvm/CodeGen/MachineFunction.h Message-ID: <20111206005109.D1E0B2A6C12C@llvm.org> Author: stoklund Date: Mon Dec 5 18:51:09 2011 New Revision: 145882 URL: http://llvm.org/viewvc/llvm-project?rev=145882&view=rev Log: Fix unclear wording. Modified: llvm/trunk/include/llvm/CodeGen/MachineFunction.h Modified: llvm/trunk/include/llvm/CodeGen/MachineFunction.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/MachineFunction.h?rev=145882&r1=145881&r2=145882&view=diff ============================================================================== --- llvm/trunk/include/llvm/CodeGen/MachineFunction.h (original) +++ llvm/trunk/include/llvm/CodeGen/MachineFunction.h Mon Dec 5 18:51:09 2011 @@ -187,7 +187,7 @@ /// void setAlignment(unsigned A) { Alignment = A; } - /// EnsureAlignment - Make sure the function is at least 'A' bits aligned. + /// EnsureAlignment - Make sure the function is at least 1 << A bytes aligned. void EnsureAlignment(unsigned A) { if (Alignment < A) Alignment = A; } From stoklund at 2pi.dk Mon Dec 5 18:51:12 2011 From: stoklund at 2pi.dk (Jakob Stoklund Olesen) Date: Tue, 06 Dec 2011 00:51:12 -0000 Subject: [llvm-commits] [llvm] r145883 - /llvm/trunk/lib/Target/ARM/ARMConstantIslandPass.cpp Message-ID: <20111206005112.D90522A6C12C@llvm.org> Author: stoklund Date: Mon Dec 5 18:51:12 2011 New Revision: 145883 URL: http://llvm.org/viewvc/llvm-project?rev=145883&view=rev Log: Use an existing function. Modified: llvm/trunk/lib/Target/ARM/ARMConstantIslandPass.cpp Modified: llvm/trunk/lib/Target/ARM/ARMConstantIslandPass.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMConstantIslandPass.cpp?rev=145883&r1=145882&r2=145883&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMConstantIslandPass.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMConstantIslandPass.cpp Mon Dec 5 18:51:12 2011 @@ -747,16 +747,7 @@ ++NumSplit; // Update the CFG. All succs of OrigBB are now succs of NewBB. - while (!OrigBB->succ_empty()) { - MachineBasicBlock *Succ = *OrigBB->succ_begin(); - OrigBB->removeSuccessor(Succ); - NewBB->addSuccessor(Succ); - - // This pass should be run after register allocation, so there should be no - // PHI nodes to update. - assert((Succ->empty() || !Succ->begin()->isPHI()) - && "PHI nodes should be eliminated by now!"); - } + NewBB->transferSuccessors(OrigBB); // OrigBB branches to NewBB. OrigBB->addSuccessor(NewBB); From grosbach at apple.com Mon Dec 5 19:08:19 2011 From: grosbach at apple.com (Jim Grosbach) Date: Tue, 06 Dec 2011 01:08:19 -0000 Subject: [llvm-commits] [llvm] r145885 - in /llvm/trunk: lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp test/MC/MachO/relax-thumb2-branches.s Message-ID: <20111206010819.7DB8F2A6C12C@llvm.org> Author: grosbach Date: Mon Dec 5 19:08:19 2011 New Revision: 145885 URL: http://llvm.org/viewvc/llvm-project?rev=145885&view=rev Log: Fix ARM handling of tBcc branch relaxation. rdar://10069056 Added: llvm/trunk/test/MC/MachO/relax-thumb2-branches.s Modified: llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp Modified: llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp?rev=145885&r1=145884&r2=145885&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp (original) +++ llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp Mon Dec 5 19:08:19 2011 @@ -146,11 +146,13 @@ uint64_t Value, const MCInstFragment *DF, const MCAsmLayout &Layout) const { - // FIXME: This isn't correct for ARM. Just moving the "generic" logic - // into the targets for now. + // Relaxing tBcc to t2Bcc. tBcc has a signed 9-bit displacement with the + // low bit being an implied zero. There's an implied +4 offset for the + // branch, so we adjust the other way here to determine what's + // encodable. // // Relax if the value is too big for a (signed) i8. - return int64_t(Value) != int64_t(int8_t(Value)); + return int64_t((Value - 4)>>1) != int64_t(int8_t((Value - 4)>>1)); } void ARMAsmBackend::RelaxInstruction(const MCInst &Inst, MCInst &Res) const { Added: llvm/trunk/test/MC/MachO/relax-thumb2-branches.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/MachO/relax-thumb2-branches.s?rev=145885&view=auto ============================================================================== --- llvm/trunk/test/MC/MachO/relax-thumb2-branches.s (added) +++ llvm/trunk/test/MC/MachO/relax-thumb2-branches.s Mon Dec 5 19:08:19 2011 @@ -0,0 +1,14 @@ +@ RUN: llvm-mc -triple=thumbv7-apple-darwin -show-encoding %s -filetype=obj -o - | macho-dump --dump-section-data | FileCheck %s + + ble Lfoo @ wide encoding + + .space 258 +Lfoo: + nop + + ble Lbaz @ narrow encoding + .space 256 +Lbaz: + +@ CHECK: '_section_data', '40f38180 +@ CHECK: 000000bf 7fdd From kcc at google.com Mon Dec 5 19:08:32 2011 From: kcc at google.com (Kostya Serebryany) Date: Tue, 06 Dec 2011 01:08:32 -0000 Subject: [llvm-commits] [compiler-rt] r145886 - /compiler-rt/trunk/lib/asan/sysinfo/sysinfo.cc Message-ID: <20111206010832.258532A6C12C@llvm.org> Author: kcc Date: Mon Dec 5 19:08:31 2011 New Revision: 145886 URL: http://llvm.org/viewvc/llvm-project?rev=145886&view=rev Log: [asan] remove format warnings in sysinfo/sysinfo.cc Modified: compiler-rt/trunk/lib/asan/sysinfo/sysinfo.cc Modified: compiler-rt/trunk/lib/asan/sysinfo/sysinfo.cc URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/lib/asan/sysinfo/sysinfo.cc?rev=145886&r1=145885&r2=145886&view=diff ============================================================================== --- compiler-rt/trunk/lib/asan/sysinfo/sysinfo.cc (original) +++ compiler-rt/trunk/lib/asan/sysinfo/sysinfo.cc Mon Dec 5 19:08:31 2011 @@ -536,9 +536,10 @@ const int rc = snprintf(buffer, bufsize, "%08"PRIx64"-%08"PRIx64" %c%c%c%c %08"PRIx64" %02x:%02x %-11"PRId64" %s\n", - start, end, r,w,x,p, offset, + (unsigned long long)start, (unsigned long long)end, r,w,x,p, + (unsigned long long)offset, static_cast(dev/256), static_cast(dev%256), - inode, filename); + (unsigned long long)inode, filename); return (rc < 0 || rc >= bufsize) ? 0 : rc; } @@ -609,4 +610,3 @@ void RawClose(RawFD fd) { NO_INTR(close(fd)); } - From isanbard at gmail.com Mon Dec 5 19:26:14 2011 From: isanbard at gmail.com (Bill Wendling) Date: Tue, 06 Dec 2011 01:26:14 -0000 Subject: [llvm-commits] [llvm] r145888 - /llvm/trunk/lib/Target/X86/X86FrameLowering.cpp Message-ID: <20111206012614.D028D2A6C12C@llvm.org> Author: void Date: Mon Dec 5 19:26:14 2011 New Revision: 145888 URL: http://llvm.org/viewvc/llvm-project?rev=145888&view=rev Log: The compact encoding of the registers are 3-bits each. Make sure we shift the value over that much. Modified: llvm/trunk/lib/Target/X86/X86FrameLowering.cpp Modified: llvm/trunk/lib/Target/X86/X86FrameLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86FrameLowering.cpp?rev=145888&r1=145887&r2=145888&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86FrameLowering.cpp (original) +++ llvm/trunk/lib/Target/X86/X86FrameLowering.cpp Mon Dec 5 19:26:14 2011 @@ -385,12 +385,14 @@ }; const unsigned *CURegs = (Is64Bit ? CU64BitRegs : CU32BitRegs); - uint32_t RenumRegs[6]; for (unsigned i = 6 - RegCount; i < 6; ++i) { int CUReg = getCompactUnwindRegNum(CURegs, SavedRegs[i]); if (CUReg == -1) return ~0U; SavedRegs[i] = CUReg; + } + uint32_t RenumRegs[6]; + for (unsigned i = 6 - RegCount; i < 6; ++i) { unsigned Countless = 0; for (unsigned j = 6 - RegCount; j < i; ++j) if (SavedRegs[j] < SavedRegs[i]) @@ -454,7 +456,7 @@ int CURegNum = getCompactUnwindRegNum(CURegs, Reg); if (CURegNum == -1) return ~0U; - RegEnc |= (CURegNum & 0x7) << (5 - I); + RegEnc |= (CURegNum & 0x7) << ((5 - I) * 3); } assert((RegEnc & 0x7FFF) == RegEnc && "Invalid compact register encoding!"); From stoklund at 2pi.dk Mon Dec 5 19:26:19 2011 From: stoklund at 2pi.dk (Jakob Stoklund Olesen) Date: Tue, 06 Dec 2011 01:26:19 -0000 Subject: [llvm-commits] [llvm] r145889 - in /llvm/trunk: include/llvm/CodeGen/MachineBasicBlock.h lib/CodeGen/AsmPrinter/AsmPrinter.cpp lib/Target/X86/X86ISelLowering.cpp Message-ID: <20111206012620.15BC22A6C12C@llvm.org> Author: stoklund Date: Mon Dec 5 19:26:19 2011 New Revision: 145889 URL: http://llvm.org/viewvc/llvm-project?rev=145889&view=rev Log: Use logarithmic units for basic block alignment. This was actually a bit of a mess. TLI.setPrefLoopAlignment was clearly documented as taking log2(bytes) units, but the x86 target would still set a preferred loop alignment of '16'. CodePlacementOpt passed this number on to the basic block, and AsmPrinter interpreted it as bytes. Now both MachineFunction and MachineBasicBlock use logarithmic alignments. Obviously, MachineConstantPool still measures alignments in bytes, so we can emulate the thrill of using as. Modified: llvm/trunk/include/llvm/CodeGen/MachineBasicBlock.h llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Modified: llvm/trunk/include/llvm/CodeGen/MachineBasicBlock.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/MachineBasicBlock.h?rev=145889&r1=145888&r2=145889&view=diff ============================================================================== --- llvm/trunk/include/llvm/CodeGen/MachineBasicBlock.h (original) +++ llvm/trunk/include/llvm/CodeGen/MachineBasicBlock.h Mon Dec 5 19:26:19 2011 @@ -84,8 +84,9 @@ /// Alignment - Alignment of the basic block. Zero if the basic block does /// not need to be aligned. + /// The alignment is specified as log2(bytes). unsigned Alignment; - + /// IsLandingPad - Indicate that this basic block is entered via an /// exception handler. bool IsLandingPad; @@ -219,10 +220,12 @@ bool livein_empty() const { return LiveIns.empty(); } /// getAlignment - Return alignment of the basic block. + /// The alignment is specified as log2(bytes). /// unsigned getAlignment() const { return Alignment; } /// setAlignment - Set alignment of the basic block. + /// The alignment is specified as log2(bytes). /// void setAlignment(unsigned Align) { Alignment = Align; } Modified: llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp?rev=145889&r1=145888&r2=145889&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp (original) +++ llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp Mon Dec 5 19:26:19 2011 @@ -1970,7 +1970,7 @@ void AsmPrinter::EmitBasicBlockStart(const MachineBasicBlock *MBB) const { // Emit an alignment directive for this block, if needed. if (unsigned Align = MBB->getAlignment()) - EmitAlignment(Log2_32(Align)); + EmitAlignment(Align); // If the block has its address taken, emit any labels that were used to // reference the block. It is possible that there is more than one label Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=145889&r1=145888&r2=145889&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original) +++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Mon Dec 5 19:26:19 2011 @@ -1211,10 +1211,10 @@ maxStoresPerMemcpyOptSize = Subtarget->isTargetDarwin() ? 8 : 4; maxStoresPerMemmove = 8; // For @llvm.memmove -> sequence of stores maxStoresPerMemmoveOptSize = Subtarget->isTargetDarwin() ? 8 : 4; - setPrefLoopAlignment(16); + setPrefLoopAlignment(4); // 2^4 bytes. benefitFromCodePlacementOpt = true; - setPrefFunctionAlignment(4); + setPrefFunctionAlignment(4); // 2^4 bytes. } From echristo at apple.com Mon Dec 5 19:33:37 2011 From: echristo at apple.com (Eric Christopher) Date: Mon, 05 Dec 2011 17:33:37 -0800 Subject: [llvm-commits] [llvm] r145888 - /llvm/trunk/lib/Target/X86/X86FrameLowering.cpp In-Reply-To: <20111206012614.D028D2A6C12C@llvm.org> References: <20111206012614.D028D2A6C12C@llvm.org> Message-ID: <4B04AD2F-0259-467C-A520-0E91051E7CE9@apple.com> On Dec 5, 2011, at 5:26 PM, Bill Wendling wrote: > - RegEnc |= (CURegNum & 0x7) << (5 - I); > + RegEnc |= (CURegNum & 0x7) << ((5 - I) * 3); Boo! Confusing numbers! Boo! How about at least a comment saying where the numbers come from? :) -eric -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20111205/8eee0997/attachment.html From stoklund at 2pi.dk Mon Dec 5 19:43:03 2011 From: stoklund at 2pi.dk (Jakob Stoklund Olesen) Date: Tue, 06 Dec 2011 01:43:03 -0000 Subject: [llvm-commits] [llvm] r145890 - in /llvm/trunk: lib/Target/ARM/ARMAsmPrinter.cpp lib/Target/ARM/ARMConstantIslandPass.cpp test/CodeGen/ARM/globals.ll Message-ID: <20111206014304.B53C92A6C12C@llvm.org> Author: stoklund Date: Mon Dec 5 19:43:02 2011 New Revision: 145890 URL: http://llvm.org/viewvc/llvm-project?rev=145890&view=rev Log: Align ARM constant pool islands via their basic block. Previously, all ARM::CONSTPOOL_ENTRY instructions had a hardwired alignment of 4 bytes emitted by ARMAsmPrinter. Now the same alignment is set on the basic block. This is in preparation of supporting ARM constant pool islands with different alignments. Modified: llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp llvm/trunk/lib/Target/ARM/ARMConstantIslandPass.cpp llvm/trunk/test/CodeGen/ARM/globals.ll Modified: llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp?rev=145890&r1=145889&r2=145890&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp Mon Dec 5 19:43:02 2011 @@ -1481,11 +1481,10 @@ /// in the function. The first operand is the ID# for this instruction, the /// second is the index into the MachineConstantPool that this is, the third /// is the size in bytes of this constant pool entry. + /// The required alignment is specified on the basic block holding this MI. unsigned LabelId = (unsigned)MI->getOperand(0).getImm(); unsigned CPIdx = (unsigned)MI->getOperand(1).getIndex(); - EmitAlignment(2); - // Mark the constant pool entry as data if we're not already in a data // region. OutStreamer.EmitDataRegion(); Modified: llvm/trunk/lib/Target/ARM/ARMConstantIslandPass.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMConstantIslandPass.cpp?rev=145890&r1=145889&r2=145890&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMConstantIslandPass.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMConstantIslandPass.cpp Mon Dec 5 19:43:02 2011 @@ -398,6 +398,9 @@ MachineBasicBlock *BB = MF.CreateMachineBasicBlock(); MF.push_back(BB); + // Mark the basic block as 4-byte aligned as required by the const-pool. + BB->setAlignment(2); + // Add all of the constants from the constant pool to the end block, use an // identity mapping of CPI's to CPE's. const std::vector &CPs = @@ -1311,6 +1314,9 @@ CPEntries[CPI].push_back(CPEntry(U.CPEMI, ID, 1)); ++NumCPEs; + // Mark the basic block as 4-byte aligned as required by the const-pool entry. + NewIsland->setAlignment(2); + BBOffsets[NewIsland->getNumber()] = BBOffsets[NewMBB->getNumber()]; // Compensate for .align 2 in thumb mode. if (isThumb && (BBOffsets[NewIsland->getNumber()]%4 != 0 || HasInlineAsm)) Modified: llvm/trunk/test/CodeGen/ARM/globals.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/globals.ll?rev=145890&r1=145889&r2=145890&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/ARM/globals.ll (original) +++ llvm/trunk/test/CodeGen/ARM/globals.ll Mon Dec 5 19:43:02 2011 @@ -70,6 +70,5 @@ ; LinuxPIC: .align 2 ; LinuxPIC: .LCPI0_0: ; LinuxPIC: .long _GLOBAL_OFFSET_TABLE_-(.LPC0_0+8) -; LinuxPIC: .align 2 ; LinuxPIC: .LCPI0_1: ; LinuxPIC: .long G(GOT) From mcrosier at apple.com Mon Dec 5 19:44:17 2011 From: mcrosier at apple.com (Chad Rosier) Date: Tue, 06 Dec 2011 01:44:17 -0000 Subject: [llvm-commits] [llvm] r145891 - in /llvm/trunk: lib/Target/ARM/ARMFastISel.cpp test/CodeGen/ARM/fast-isel.ll Message-ID: <20111206014418.08CA32A6C12C@llvm.org> Author: mcrosier Date: Mon Dec 5 19:44:17 2011 New Revision: 145891 URL: http://llvm.org/viewvc/llvm-project?rev=145891&view=rev Log: [arm-fast-isel] Doublewords only require word-alignment. rdar://10528060 Modified: llvm/trunk/lib/Target/ARM/ARMFastISel.cpp llvm/trunk/test/CodeGen/ARM/fast-isel.ll Modified: llvm/trunk/lib/Target/ARM/ARMFastISel.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMFastISel.cpp?rev=145891&r1=145890&r2=145891&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMFastISel.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMFastISel.cpp Mon Dec 5 19:44:17 2011 @@ -1106,7 +1106,7 @@ case MVT::f32: if (!Subtarget->hasVFP2()) return false; StrOpc = ARM::VSTRS; - // Unaligned stores need special handling. + // Unaligned stores need special handling. Floats require word-alignment. if (Alignment && Alignment < 4) { unsigned MoveReg = createResultReg(TLI.getRegClassFor(MVT::i32)); AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, @@ -1119,8 +1119,9 @@ break; case MVT::f64: if (!Subtarget->hasVFP2()) return false; - // FIXME: Unaligned stores need special handling. - if (Alignment && Alignment < 8) { + // FIXME: Unaligned stores need special handling. Doublewords require + // word-alignment. + if (Alignment && Alignment < 4) { return false; } StrOpc = ARM::VSTRD; Modified: llvm/trunk/test/CodeGen/ARM/fast-isel.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/fast-isel.ll?rev=145891&r1=145890&r2=145891&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/ARM/fast-isel.ll (original) +++ llvm/trunk/test/CodeGen/ARM/fast-isel.ll Mon Dec 5 19:44:17 2011 @@ -180,3 +180,21 @@ store float %add, float* %x1, align 1 ret void } + +; Doublewords require only word-alignment. +; rdar://10528060 +%struct.anon.0 = type { double } + + at foo_unpacked = common global %struct.anon.0 zeroinitializer, align 4 + +define void @test5(double %a, double %b) nounwind { +entry: +; ARM: @test5 +; THUMB: @test5 + %add = fadd double %a, %b + store double %add, double* getelementptr inbounds (%struct.anon.0* @foo_unpacked, i32 0, i32 0), align 4 +; ARM: vstr d16, [r0] +; THUMB: vstr d16, [r0] + ret void +} + From lhames at gmail.com Mon Dec 5 19:45:57 2011 From: lhames at gmail.com (Lang Hames) Date: Tue, 06 Dec 2011 01:45:57 -0000 Subject: [llvm-commits] [llvm] r145893 - /llvm/trunk/lib/CodeGen/RegAllocPBQP.cpp Message-ID: <20111206014559.74FB12A6C12C@llvm.org> Author: lhames Date: Mon Dec 5 19:45:57 2011 New Revision: 145893 URL: http://llvm.org/viewvc/llvm-project?rev=145893&view=rev Log: Update PBQP's analysis usage to reflect the requirements of the inline spiller. Modified: llvm/trunk/lib/CodeGen/RegAllocPBQP.cpp Modified: llvm/trunk/lib/CodeGen/RegAllocPBQP.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/RegAllocPBQP.cpp?rev=145893&r1=145892&r2=145893&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/RegAllocPBQP.cpp (original) +++ llvm/trunk/lib/CodeGen/RegAllocPBQP.cpp Mon Dec 5 19:45:57 2011 @@ -37,10 +37,12 @@ #include "Splitter.h" #include "VirtRegMap.h" #include "RegisterCoalescer.h" +#include "llvm/Analysis/AliasAnalysis.h" #include "llvm/CodeGen/CalcSpillWeights.h" #include "llvm/CodeGen/LiveIntervalAnalysis.h" #include "llvm/CodeGen/LiveStackAnalysis.h" #include "llvm/CodeGen/RegAllocPBQP.h" +#include "llvm/CodeGen/MachineDominators.h" #include "llvm/CodeGen/MachineFunctionPass.h" #include "llvm/CodeGen/MachineLoopInfo.h" #include "llvm/CodeGen/MachineRegisterInfo.h" @@ -444,6 +446,9 @@ void RegAllocPBQP::getAnalysisUsage(AnalysisUsage &au) const { + au.setPreservesCFG(); + au.addRequired(); + au.addPreserved(); au.addRequired(); au.addPreserved(); au.addRequired(); @@ -454,6 +459,8 @@ au.addRequired(); au.addRequired(); au.addPreserved(); + au.addRequired(); + au.addPreserved(); au.addRequired(); au.addPreserved(); if (pbqpPreSplitting) From geek4civic at gmail.com Mon Dec 5 19:48:32 2011 From: geek4civic at gmail.com (NAKAMURA Takumi) Date: Tue, 06 Dec 2011 01:48:32 -0000 Subject: [llvm-commits] [llvm] r145894 - in /llvm/trunk/lib/Target: Mips/MCTargetDesc/MipsAsmBackend.cpp PowerPC/MCTargetDesc/PPCAsmBackend.cpp Message-ID: <20111206014832.F01782A6C12C@llvm.org> Author: chapuni Date: Mon Dec 5 19:48:32 2011 New Revision: 145894 URL: http://llvm.org/viewvc/llvm-project?rev=145894&view=rev Log: MipsAsmBackend.cpp, PPCAsmBackend.cpp: Fix -Asserts build to appease msvc. Modified: llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsAsmBackend.cpp llvm/trunk/lib/Target/PowerPC/MCTargetDesc/PPCAsmBackend.cpp Modified: llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsAsmBackend.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsAsmBackend.cpp?rev=145894&r1=145893&r2=145894&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsAsmBackend.cpp (original) +++ llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsAsmBackend.cpp Mon Dec 5 19:48:32 2011 @@ -181,6 +181,7 @@ const MCAsmLayout &Layout) const { // FIXME. assert(0 && "RelaxInstruction() unimplemented"); + return false; } /// RelaxInstruction - Relax the instruction in the given fragment Modified: llvm/trunk/lib/Target/PowerPC/MCTargetDesc/PPCAsmBackend.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/MCTargetDesc/PPCAsmBackend.cpp?rev=145894&r1=145893&r2=145894&view=diff ============================================================================== --- llvm/trunk/lib/Target/PowerPC/MCTargetDesc/PPCAsmBackend.cpp (original) +++ llvm/trunk/lib/Target/PowerPC/MCTargetDesc/PPCAsmBackend.cpp Mon Dec 5 19:48:32 2011 @@ -100,6 +100,7 @@ const MCAsmLayout &Layout) const { // FIXME. assert(0 && "RelaxInstruction() unimplemented"); + return false; } From grosbach at apple.com Mon Dec 5 19:53:17 2011 From: grosbach at apple.com (Jim Grosbach) Date: Tue, 06 Dec 2011 01:53:17 -0000 Subject: [llvm-commits] [llvm] r145895 - /llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp Message-ID: <20111206015317.3EF8E2A6C12C@llvm.org> Author: grosbach Date: Mon Dec 5 19:53:17 2011 New Revision: 145895 URL: http://llvm.org/viewvc/llvm-project?rev=145895&view=rev Log: Tidy up value checking. Modified: llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp Modified: llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp?rev=145895&r1=145894&r2=145895&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp (original) +++ llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp Mon Dec 5 19:53:17 2011 @@ -152,7 +152,8 @@ // encodable. // // Relax if the value is too big for a (signed) i8. - return int64_t((Value - 4)>>1) != int64_t(int8_t((Value - 4)>>1)); + int64_t Offset = int64_t(Value) - 4; + return Offset > 254 || Offset < -256; } void ARMAsmBackend::RelaxInstruction(const MCInst &Inst, MCInst &Res) const { From isanbard at gmail.com Mon Dec 5 19:57:48 2011 From: isanbard at gmail.com (Bill Wendling) Date: Tue, 06 Dec 2011 01:57:48 -0000 Subject: [llvm-commits] [llvm] r145896 - /llvm/trunk/lib/Target/X86/X86FrameLowering.cpp Message-ID: <20111206015748.8C1002A6C12C@llvm.org> Author: void Date: Mon Dec 5 19:57:48 2011 New Revision: 145896 URL: http://llvm.org/viewvc/llvm-project?rev=145896&view=rev Log: Add a comment. Modified: llvm/trunk/lib/Target/X86/X86FrameLowering.cpp Modified: llvm/trunk/lib/Target/X86/X86FrameLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86FrameLowering.cpp?rev=145896&r1=145895&r2=145896&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86FrameLowering.cpp (original) +++ llvm/trunk/lib/Target/X86/X86FrameLowering.cpp Mon Dec 5 19:57:48 2011 @@ -456,6 +456,9 @@ int CURegNum = getCompactUnwindRegNum(CURegs, Reg); if (CURegNum == -1) return ~0U; + + // Encode the 3-bit register number in order, skipping over 3-bits for each + // register. RegEnc |= (CURegNum & 0x7) << ((5 - I) * 3); } From lhames at gmail.com Mon Dec 5 19:58:00 2011 From: lhames at gmail.com (Lang Hames) Date: Tue, 06 Dec 2011 01:58:00 -0000 Subject: [llvm-commits] [llvm] r145897 - in /llvm/trunk: include/llvm/InitializePasses.h lib/CodeGen/CMakeLists.txt lib/CodeGen/CodeGen.cpp lib/CodeGen/RegAllocPBQP.cpp lib/CodeGen/Splitter.cpp lib/CodeGen/Splitter.h Message-ID: <20111206015800.24B052A6C12C@llvm.org> Author: lhames Date: Mon Dec 5 19:57:59 2011 New Revision: 145897 URL: http://llvm.org/viewvc/llvm-project?rev=145897&view=rev Log: Kill off the LoopSplitter. It's not being used or maintained. Removed: llvm/trunk/lib/CodeGen/Splitter.cpp llvm/trunk/lib/CodeGen/Splitter.h Modified: llvm/trunk/include/llvm/InitializePasses.h llvm/trunk/lib/CodeGen/CMakeLists.txt llvm/trunk/lib/CodeGen/CodeGen.cpp llvm/trunk/lib/CodeGen/RegAllocPBQP.cpp Modified: llvm/trunk/include/llvm/InitializePasses.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/InitializePasses.h?rev=145897&r1=145896&r2=145897&view=diff ============================================================================== --- llvm/trunk/include/llvm/InitializePasses.h (original) +++ llvm/trunk/include/llvm/InitializePasses.h Mon Dec 5 19:57:59 2011 @@ -135,7 +135,6 @@ void initializeLoopInstSimplifyPass(PassRegistry&); void initializeLoopRotatePass(PassRegistry&); void initializeLoopSimplifyPass(PassRegistry&); -void initializeLoopSplitterPass(PassRegistry&); void initializeLoopStrengthReducePass(PassRegistry&); void initializeGlobalMergePass(PassRegistry&); void initializeLoopUnrollPass(PassRegistry&); Modified: llvm/trunk/lib/CodeGen/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/CMakeLists.txt?rev=145897&r1=145896&r2=145897&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/CMakeLists.txt (original) +++ llvm/trunk/lib/CodeGen/CMakeLists.txt Mon Dec 5 19:57:59 2011 @@ -88,7 +88,6 @@ Spiller.cpp SpillPlacement.cpp SplitKit.cpp - Splitter.cpp StackProtector.cpp StackSlotColoring.cpp StrongPHIElimination.cpp Modified: llvm/trunk/lib/CodeGen/CodeGen.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/CodeGen.cpp?rev=145897&r1=145896&r2=145897&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/CodeGen.cpp (original) +++ llvm/trunk/lib/CodeGen/CodeGen.cpp Mon Dec 5 19:57:59 2011 @@ -45,7 +45,6 @@ initializeRegisterCoalescerPass(Registry); initializeRenderMachineFunctionPass(Registry); initializeSlotIndexesPass(Registry); - initializeLoopSplitterPass(Registry); initializeStackProtectorPass(Registry); initializeStackSlotColoringPass(Registry); initializeStrongPHIEliminationPass(Registry); Modified: llvm/trunk/lib/CodeGen/RegAllocPBQP.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/RegAllocPBQP.cpp?rev=145897&r1=145896&r2=145897&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/RegAllocPBQP.cpp (original) +++ llvm/trunk/lib/CodeGen/RegAllocPBQP.cpp Mon Dec 5 19:57:59 2011 @@ -34,7 +34,6 @@ #include "LiveRangeEdit.h" #include "RenderMachineFunction.h" #include "Spiller.h" -#include "Splitter.h" #include "VirtRegMap.h" #include "RegisterCoalescer.h" #include "llvm/Analysis/AliasAnalysis.h" @@ -70,11 +69,6 @@ cl::desc("Attempt coalescing during PBQP register allocation."), cl::init(false), cl::Hidden); -static cl::opt -pbqpPreSplitting("pbqp-pre-splitting", - cl::desc("Pre-split before PBQP register allocation."), - cl::init(false), cl::Hidden); - namespace { /// @@ -95,7 +89,6 @@ initializeCalculateSpillWeightsPass(*PassRegistry::getPassRegistry()); initializeLiveStacksPass(*PassRegistry::getPassRegistry()); initializeMachineLoopInfoPass(*PassRegistry::getPassRegistry()); - initializeLoopSplitterPass(*PassRegistry::getPassRegistry()); initializeVirtRegMapPass(*PassRegistry::getPassRegistry()); initializeRenderMachineFunctionPass(*PassRegistry::getPassRegistry()); } @@ -463,8 +456,6 @@ au.addPreserved(); au.addRequired(); au.addPreserved(); - if (pbqpPreSplitting) - au.addRequired(); au.addRequired(); au.addRequired(); MachineFunctionPass::getAnalysisUsage(au); Removed: llvm/trunk/lib/CodeGen/Splitter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/Splitter.cpp?rev=145896&view=auto ============================================================================== --- llvm/trunk/lib/CodeGen/Splitter.cpp (original) +++ llvm/trunk/lib/CodeGen/Splitter.cpp (removed) @@ -1,829 +0,0 @@ -//===-- llvm/CodeGen/Splitter.cpp - Splitter -----------------------------===// -// -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. -// -//===----------------------------------------------------------------------===// - -#define DEBUG_TYPE "loopsplitter" - -#include "Splitter.h" - -#include "llvm/Module.h" -#include "llvm/CodeGen/CalcSpillWeights.h" -#include "llvm/CodeGen/LiveIntervalAnalysis.h" -#include "llvm/CodeGen/LiveStackAnalysis.h" -#include "llvm/CodeGen/MachineDominators.h" -#include "llvm/CodeGen/MachineInstrBuilder.h" -#include "llvm/CodeGen/MachineFunction.h" -#include "llvm/CodeGen/MachineRegisterInfo.h" -#include "llvm/CodeGen/Passes.h" -#include "llvm/CodeGen/SlotIndexes.h" -#include "llvm/Support/Debug.h" -#include "llvm/Support/raw_ostream.h" -#include "llvm/Target/TargetMachine.h" -#include "llvm/Target/TargetInstrInfo.h" - -using namespace llvm; - -char LoopSplitter::ID = 0; -INITIALIZE_PASS_BEGIN(LoopSplitter, "loop-splitting", - "Split virtual regists across loop boundaries.", false, false) -INITIALIZE_PASS_DEPENDENCY(MachineDominatorTree) -INITIALIZE_PASS_DEPENDENCY(MachineLoopInfo) -INITIALIZE_PASS_DEPENDENCY(SlotIndexes) -INITIALIZE_PASS_DEPENDENCY(LiveIntervals) -INITIALIZE_PASS_END(LoopSplitter, "loop-splitting", - "Split virtual regists across loop boundaries.", false, false) - -namespace { - class StartSlotComparator { - public: - StartSlotComparator(LiveIntervals &lis) : lis(lis) {} - bool operator()(const MachineBasicBlock *mbb1, - const MachineBasicBlock *mbb2) const { - return lis.getMBBStartIdx(mbb1) < lis.getMBBStartIdx(mbb2); - } - private: - LiveIntervals &lis; - }; -} - -namespace llvm { - - class LoopSplit { - public: - LoopSplit(LoopSplitter &ls, LiveInterval &li, MachineLoop &loop) - : ls(ls), li(li), loop(loop), valid(true), inSplit(false), newLI(0) { - assert(TargetRegisterInfo::isVirtualRegister(li.reg) && - "Cannot split physical registers."); - } - - LiveInterval& getLI() const { return li; } - - MachineLoop& getLoop() const { return loop; } - - bool isValid() const { return valid; } - - bool isWorthwhile() const { return valid && (inSplit || !outSplits.empty()); } - - void invalidate() { valid = false; } - - void splitIncoming() { inSplit = true; } - - void splitOutgoing(MachineLoop::Edge &edge) { outSplits.insert(edge); } - - void addLoopInstr(MachineInstr *i) { loopInstrs.push_back(i); } - - void apply() { - assert(valid && "Attempt to apply invalid split."); - applyIncoming(); - applyOutgoing(); - copyRanges(); - renameInside(); - } - - private: - LoopSplitter &ls; - LiveInterval &li; - MachineLoop &loop; - bool valid, inSplit; - std::set outSplits; - std::vector loopInstrs; - - LiveInterval *newLI; - std::map vniMap; - - LiveInterval* getNewLI() { - if (newLI == 0) { - const TargetRegisterClass *trc = ls.mri->getRegClass(li.reg); - unsigned vreg = ls.mri->createVirtualRegister(trc); - newLI = &ls.lis->getOrCreateInterval(vreg); - } - return newLI; - } - - VNInfo* getNewVNI(VNInfo *oldVNI) { - VNInfo *newVNI = vniMap[oldVNI]; - - if (newVNI == 0) { - newVNI = getNewLI()->createValueCopy(oldVNI, - ls.lis->getVNInfoAllocator()); - vniMap[oldVNI] = newVNI; - } - - return newVNI; - } - - void applyIncoming() { - if (!inSplit) { - return; - } - - MachineBasicBlock *preHeader = loop.getLoopPreheader(); - if (preHeader == 0) { - assert(ls.canInsertPreHeader(loop) && - "Can't insert required preheader."); - preHeader = &ls.insertPreHeader(loop); - } - - LiveRange *preHeaderRange = - ls.lis->findExitingRange(li, preHeader); - assert(preHeaderRange != 0 && "Range not live into preheader."); - - // Insert the new copy. - MachineInstr *copy = BuildMI(*preHeader, - preHeader->getFirstTerminator(), - DebugLoc(), - ls.tii->get(TargetOpcode::COPY)) - .addReg(getNewLI()->reg, RegState::Define) - .addReg(li.reg, RegState::Kill); - - ls.lis->InsertMachineInstrInMaps(copy); - - SlotIndex copyDefIdx = ls.lis->getInstructionIndex(copy).getRegSlot(); - - VNInfo *newVal = getNewVNI(preHeaderRange->valno); - newVal->def = copyDefIdx; - newVal->setCopy(copy); - li.removeRange(copyDefIdx, ls.lis->getMBBEndIdx(preHeader), true); - - getNewLI()->addRange(LiveRange(copyDefIdx, - ls.lis->getMBBEndIdx(preHeader), - newVal)); - } - - void applyOutgoing() { - - for (std::set::iterator osItr = outSplits.begin(), - osEnd = outSplits.end(); - osItr != osEnd; ++osItr) { - MachineLoop::Edge edge = *osItr; - MachineBasicBlock *outBlock = edge.second; - if (ls.isCriticalEdge(edge)) { - assert(ls.canSplitEdge(edge) && "Unsplitable critical edge."); - outBlock = &ls.splitEdge(edge, loop); - } - LiveRange *outRange = ls.lis->findEnteringRange(li, outBlock); - assert(outRange != 0 && "No exiting range?"); - - MachineInstr *copy = BuildMI(*outBlock, outBlock->begin(), - DebugLoc(), - ls.tii->get(TargetOpcode::COPY)) - .addReg(li.reg, RegState::Define) - .addReg(getNewLI()->reg, RegState::Kill); - - ls.lis->InsertMachineInstrInMaps(copy); - - SlotIndex copyDefIdx = ls.lis->getInstructionIndex(copy).getRegSlot(); - - // Blow away output range definition. - outRange->valno->def = ls.lis->getInvalidIndex(); - li.removeRange(ls.lis->getMBBStartIdx(outBlock), copyDefIdx); - - SlotIndex newDefIdx = ls.lis->getMBBStartIdx(outBlock); - assert(ls.lis->getInstructionFromIndex(newDefIdx) == 0 && - "PHI def index points at actual instruction."); - VNInfo *newVal = - getNewLI()->getNextValue(newDefIdx, 0, ls.lis->getVNInfoAllocator()); - - getNewLI()->addRange(LiveRange(ls.lis->getMBBStartIdx(outBlock), - copyDefIdx, newVal)); - - } - } - - void copyRange(LiveRange &lr) { - std::pair lsr = - ls.getLoopSubRange(lr, loop); - - if (!lsr.first) - return; - - LiveRange loopRange(lsr.second.first, lsr.second.second, - getNewVNI(lr.valno)); - - li.removeRange(loopRange.start, loopRange.end, true); - - getNewLI()->addRange(loopRange); - } - - void copyRanges() { - for (std::vector::iterator iItr = loopInstrs.begin(), - iEnd = loopInstrs.end(); - iItr != iEnd; ++iItr) { - MachineInstr &instr = **iItr; - SlotIndex instrIdx = ls.lis->getInstructionIndex(&instr); - if (instr.modifiesRegister(li.reg, 0)) { - LiveRange *defRange = - li.getLiveRangeContaining(instrIdx.getRegSlot()); - if (defRange != 0) // May have caught this already. - copyRange(*defRange); - } - if (instr.readsRegister(li.reg, 0)) { - LiveRange *useRange = - li.getLiveRangeContaining(instrIdx.getRegSlot(true)); - if (useRange != 0) { // May have caught this already. - copyRange(*useRange); - } - } - } - - for (MachineLoop::block_iterator bbItr = loop.block_begin(), - bbEnd = loop.block_end(); - bbItr != bbEnd; ++bbItr) { - MachineBasicBlock &loopBlock = **bbItr; - LiveRange *enteringRange = - ls.lis->findEnteringRange(li, &loopBlock); - if (enteringRange != 0) { - copyRange(*enteringRange); - } - } - } - - void renameInside() { - for (std::vector::iterator iItr = loopInstrs.begin(), - iEnd = loopInstrs.end(); - iItr != iEnd; ++iItr) { - MachineInstr &instr = **iItr; - for (unsigned i = 0; i < instr.getNumOperands(); ++i) { - MachineOperand &mop = instr.getOperand(i); - if (mop.isReg() && mop.getReg() == li.reg) { - mop.setReg(getNewLI()->reg); - } - } - } - } - - }; - - void LoopSplitter::getAnalysisUsage(AnalysisUsage &au) const { - au.addRequired(); - au.addPreserved(); - au.addRequired(); - au.addPreserved(); - au.addPreservedID(RegisterCoalescerPassID); - au.addPreserved(); - au.addPreserved(); - au.addRequired(); - au.addPreserved(); - au.addRequired(); - au.addPreserved(); - MachineFunctionPass::getAnalysisUsage(au); - } - - bool LoopSplitter::runOnMachineFunction(MachineFunction &fn) { - - mf = &fn; - mri = &mf->getRegInfo(); - tii = mf->getTarget().getInstrInfo(); - tri = mf->getTarget().getRegisterInfo(); - sis = &getAnalysis(); - lis = &getAnalysis(); - mli = &getAnalysis(); - mdt = &getAnalysis(); - - fqn = mf->getFunction()->getParent()->getModuleIdentifier() + "." + - mf->getFunction()->getName().str(); - - dbgs() << "Splitting " << mf->getFunction()->getName() << "."; - - dumpOddTerminators(); - -// dbgs() << "----------------------------------------\n"; -// lis->dump(); -// dbgs() << "----------------------------------------\n"; - -// std::deque loops; -// std::copy(mli->begin(), mli->end(), std::back_inserter(loops)); -// dbgs() << "Loops:\n"; -// while (!loops.empty()) { -// MachineLoop &loop = *loops.front(); -// loops.pop_front(); -// std::copy(loop.begin(), loop.end(), std::back_inserter(loops)); - -// dumpLoopInfo(loop); -// } - - //lis->dump(); - //exit(0); - - // Setup initial intervals. - for (LiveIntervals::iterator liItr = lis->begin(), liEnd = lis->end(); - liItr != liEnd; ++liItr) { - LiveInterval *li = liItr->second; - - if (TargetRegisterInfo::isVirtualRegister(li->reg) && - !lis->intervalIsInOneMBB(*li)) { - intervals.push_back(li); - } - } - - processIntervals(); - - intervals.clear(); - -// dbgs() << "----------------------------------------\n"; -// lis->dump(); -// dbgs() << "----------------------------------------\n"; - - dumpOddTerminators(); - - //exit(1); - - return false; - } - - void LoopSplitter::releaseMemory() { - fqn.clear(); - intervals.clear(); - loopRangeMap.clear(); - } - - void LoopSplitter::dumpOddTerminators() { - for (MachineFunction::iterator bbItr = mf->begin(), bbEnd = mf->end(); - bbItr != bbEnd; ++bbItr) { - MachineBasicBlock *mbb = &*bbItr; - MachineBasicBlock *a = 0, *b = 0; - SmallVector c; - if (tii->AnalyzeBranch(*mbb, a, b, c)) { - dbgs() << "MBB#" << mbb->getNumber() << " has multiway terminator.\n"; - dbgs() << " Terminators:\n"; - for (MachineBasicBlock::iterator iItr = mbb->begin(), iEnd = mbb->end(); - iItr != iEnd; ++iItr) { - MachineInstr *instr= &*iItr; - dbgs() << " " << *instr << ""; - } - dbgs() << "\n Listed successors: [ "; - for (MachineBasicBlock::succ_iterator sItr = mbb->succ_begin(), sEnd = mbb->succ_end(); - sItr != sEnd; ++sItr) { - MachineBasicBlock *succMBB = *sItr; - dbgs() << succMBB->getNumber() << " "; - } - dbgs() << "]\n\n"; - } - } - } - - void LoopSplitter::dumpLoopInfo(MachineLoop &loop) { - MachineBasicBlock &headerBlock = *loop.getHeader(); - typedef SmallVector ExitEdgesList; - ExitEdgesList exitEdges; - loop.getExitEdges(exitEdges); - - dbgs() << " Header: BB#" << headerBlock.getNumber() << ", Contains: [ "; - for (std::vector::const_iterator - subBlockItr = loop.getBlocks().begin(), - subBlockEnd = loop.getBlocks().end(); - subBlockItr != subBlockEnd; ++subBlockItr) { - MachineBasicBlock &subBlock = **subBlockItr; - dbgs() << "BB#" << subBlock.getNumber() << " "; - } - dbgs() << "], Exit edges: [ "; - for (ExitEdgesList::iterator exitEdgeItr = exitEdges.begin(), - exitEdgeEnd = exitEdges.end(); - exitEdgeItr != exitEdgeEnd; ++exitEdgeItr) { - MachineLoop::Edge &exitEdge = *exitEdgeItr; - dbgs() << "(MBB#" << exitEdge.first->getNumber() - << ", MBB#" << exitEdge.second->getNumber() << ") "; - } - dbgs() << "], Sub-Loop Headers: [ "; - for (MachineLoop::iterator subLoopItr = loop.begin(), - subLoopEnd = loop.end(); - subLoopItr != subLoopEnd; ++subLoopItr) { - MachineLoop &subLoop = **subLoopItr; - MachineBasicBlock &subLoopBlock = *subLoop.getHeader(); - dbgs() << "BB#" << subLoopBlock.getNumber() << " "; - } - dbgs() << "]\n"; - } - - void LoopSplitter::updateTerminators(MachineBasicBlock &mbb) { - mbb.updateTerminator(); - - for (MachineBasicBlock::iterator miItr = mbb.begin(), miEnd = mbb.end(); - miItr != miEnd; ++miItr) { - if (lis->isNotInMIMap(miItr)) { - lis->InsertMachineInstrInMaps(miItr); - } - } - } - - bool LoopSplitter::canInsertPreHeader(MachineLoop &loop) { - MachineBasicBlock *header = loop.getHeader(); - MachineBasicBlock *a = 0, *b = 0; - SmallVector c; - - for (MachineBasicBlock::pred_iterator pbItr = header->pred_begin(), - pbEnd = header->pred_end(); - pbItr != pbEnd; ++pbItr) { - MachineBasicBlock *predBlock = *pbItr; - if (!!tii->AnalyzeBranch(*predBlock, a, b, c)) { - return false; - } - } - - MachineFunction::iterator headerItr(header); - if (headerItr == mf->begin()) - return true; - MachineBasicBlock *headerLayoutPred = llvm::prior(headerItr); - assert(headerLayoutPred != 0 && "Header should have layout pred."); - - return (!tii->AnalyzeBranch(*headerLayoutPred, a, b, c)); - } - - MachineBasicBlock& LoopSplitter::insertPreHeader(MachineLoop &loop) { - assert(loop.getLoopPreheader() == 0 && "Loop already has preheader."); - - MachineBasicBlock &header = *loop.getHeader(); - - // Save the preds - we'll need to update them once we insert the preheader. - typedef std::set HeaderPreds; - HeaderPreds headerPreds; - - for (MachineBasicBlock::pred_iterator predItr = header.pred_begin(), - predEnd = header.pred_end(); - predItr != predEnd; ++predItr) { - if (!loop.contains(*predItr)) - headerPreds.insert(*predItr); - } - - assert(!headerPreds.empty() && "No predecessors for header?"); - - //dbgs() << fqn << " MBB#" << header.getNumber() << " inserting preheader..."; - - MachineBasicBlock *preHeader = - mf->CreateMachineBasicBlock(header.getBasicBlock()); - - assert(preHeader != 0 && "Failed to create pre-header."); - - mf->insert(header, preHeader); - - for (HeaderPreds::iterator hpItr = headerPreds.begin(), - hpEnd = headerPreds.end(); - hpItr != hpEnd; ++hpItr) { - assert(*hpItr != 0 && "How'd a null predecessor get into this set?"); - MachineBasicBlock &hp = **hpItr; - hp.ReplaceUsesOfBlockWith(&header, preHeader); - } - preHeader->addSuccessor(&header); - - MachineBasicBlock *oldLayoutPred = - llvm::prior(MachineFunction::iterator(preHeader)); - if (oldLayoutPred != 0) { - updateTerminators(*oldLayoutPred); - } - - lis->InsertMBBInMaps(preHeader); - - if (MachineLoop *parentLoop = loop.getParentLoop()) { - assert(parentLoop->getHeader() != loop.getHeader() && - "Parent loop has same header?"); - parentLoop->addBasicBlockToLoop(preHeader, mli->getBase()); - - // Invalidate all parent loop ranges. - while (parentLoop != 0) { - loopRangeMap.erase(parentLoop); - parentLoop = parentLoop->getParentLoop(); - } - } - - for (LiveIntervals::iterator liItr = lis->begin(), - liEnd = lis->end(); - liItr != liEnd; ++liItr) { - LiveInterval &li = *liItr->second; - - // Is this safe for physregs? - // TargetRegisterInfo::isPhysicalRegister(li.reg) || - if (!lis->isLiveInToMBB(li, &header)) - continue; - - if (lis->isLiveInToMBB(li, preHeader)) { - assert(lis->isLiveOutOfMBB(li, preHeader) && - "Range terminates in newly added preheader?"); - continue; - } - - bool insertRange = false; - - for (MachineBasicBlock::pred_iterator predItr = preHeader->pred_begin(), - predEnd = preHeader->pred_end(); - predItr != predEnd; ++predItr) { - MachineBasicBlock *predMBB = *predItr; - if (lis->isLiveOutOfMBB(li, predMBB)) { - insertRange = true; - break; - } - } - - if (!insertRange) - continue; - - SlotIndex newDefIdx = lis->getMBBStartIdx(preHeader); - assert(lis->getInstructionFromIndex(newDefIdx) == 0 && - "PHI def index points at actual instruction."); - VNInfo *newVal = li.getNextValue(newDefIdx, 0, lis->getVNInfoAllocator()); - li.addRange(LiveRange(lis->getMBBStartIdx(preHeader), - lis->getMBBEndIdx(preHeader), - newVal)); - } - - - //dbgs() << "Dumping SlotIndexes:\n"; - //sis->dump(); - - //dbgs() << "done. (Added MBB#" << preHeader->getNumber() << ")\n"; - - return *preHeader; - } - - bool LoopSplitter::isCriticalEdge(MachineLoop::Edge &edge) { - assert(edge.first->succ_size() > 1 && "Non-sensical edge."); - if (edge.second->pred_size() > 1) - return true; - return false; - } - - bool LoopSplitter::canSplitEdge(MachineLoop::Edge &edge) { - MachineFunction::iterator outBlockItr(edge.second); - if (outBlockItr == mf->begin()) - return true; - MachineBasicBlock *outBlockLayoutPred = llvm::prior(outBlockItr); - assert(outBlockLayoutPred != 0 && "Should have a layout pred if out!=begin."); - MachineBasicBlock *a = 0, *b = 0; - SmallVector c; - return (!tii->AnalyzeBranch(*outBlockLayoutPred, a, b, c) && - !tii->AnalyzeBranch(*edge.first, a, b, c)); - } - - MachineBasicBlock& LoopSplitter::splitEdge(MachineLoop::Edge &edge, - MachineLoop &loop) { - - MachineBasicBlock &inBlock = *edge.first; - MachineBasicBlock &outBlock = *edge.second; - - assert((inBlock.succ_size() > 1) && (outBlock.pred_size() > 1) && - "Splitting non-critical edge?"); - - //dbgs() << fqn << " Splitting edge (MBB#" << inBlock.getNumber() - // << " -> MBB#" << outBlock.getNumber() << ")..."; - - MachineBasicBlock *splitBlock = - mf->CreateMachineBasicBlock(); - - assert(splitBlock != 0 && "Failed to create split block."); - - mf->insert(&outBlock, splitBlock); - - inBlock.ReplaceUsesOfBlockWith(&outBlock, splitBlock); - splitBlock->addSuccessor(&outBlock); - - MachineBasicBlock *oldLayoutPred = - llvm::prior(MachineFunction::iterator(splitBlock)); - if (oldLayoutPred != 0) { - updateTerminators(*oldLayoutPred); - } - - lis->InsertMBBInMaps(splitBlock); - - loopRangeMap.erase(&loop); - - MachineLoop *splitParentLoop = loop.getParentLoop(); - while (splitParentLoop != 0 && - !splitParentLoop->contains(&outBlock)) { - splitParentLoop = splitParentLoop->getParentLoop(); - } - - if (splitParentLoop != 0) { - assert(splitParentLoop->contains(&loop) && - "Split-block parent doesn't contain original loop?"); - splitParentLoop->addBasicBlockToLoop(splitBlock, mli->getBase()); - - // Invalidate all parent loop ranges. - while (splitParentLoop != 0) { - loopRangeMap.erase(splitParentLoop); - splitParentLoop = splitParentLoop->getParentLoop(); - } - } - - - for (LiveIntervals::iterator liItr = lis->begin(), - liEnd = lis->end(); - liItr != liEnd; ++liItr) { - LiveInterval &li = *liItr->second; - bool intersects = lis->isLiveOutOfMBB(li, &inBlock) && - lis->isLiveInToMBB(li, &outBlock); - if (lis->isLiveInToMBB(li, splitBlock)) { - if (!intersects) { - li.removeRange(lis->getMBBStartIdx(splitBlock), - lis->getMBBEndIdx(splitBlock), true); - } - } else if (intersects) { - SlotIndex newDefIdx = lis->getMBBStartIdx(splitBlock); - assert(lis->getInstructionFromIndex(newDefIdx) == 0 && - "PHI def index points at actual instruction."); - VNInfo *newVal = li.getNextValue(newDefIdx, 0, - lis->getVNInfoAllocator()); - li.addRange(LiveRange(lis->getMBBStartIdx(splitBlock), - lis->getMBBEndIdx(splitBlock), - newVal)); - } - } - - //dbgs() << "done. (Added MBB#" << splitBlock->getNumber() << ")\n"; - - return *splitBlock; - } - - LoopSplitter::LoopRanges& LoopSplitter::getLoopRanges(MachineLoop &loop) { - typedef std::set LoopMBBSet; - LoopRangeMap::iterator lrItr = loopRangeMap.find(&loop); - if (lrItr == loopRangeMap.end()) { - LoopMBBSet loopMBBs((StartSlotComparator(*lis))); - std::copy(loop.block_begin(), loop.block_end(), - std::inserter(loopMBBs, loopMBBs.begin())); - - assert(!loopMBBs.empty() && "No blocks in loop?"); - - LoopRanges &loopRanges = loopRangeMap[&loop]; - assert(loopRanges.empty() && "Loop encountered but not processed?"); - SlotIndex oldEnd = lis->getMBBEndIdx(*loopMBBs.begin()); - loopRanges.push_back( - std::make_pair(lis->getMBBStartIdx(*loopMBBs.begin()), - lis->getInvalidIndex())); - for (LoopMBBSet::iterator curBlockItr = llvm::next(loopMBBs.begin()), - curBlockEnd = loopMBBs.end(); - curBlockItr != curBlockEnd; ++curBlockItr) { - SlotIndex newStart = lis->getMBBStartIdx(*curBlockItr); - if (newStart != oldEnd) { - loopRanges.back().second = oldEnd; - loopRanges.push_back(std::make_pair(newStart, - lis->getInvalidIndex())); - } - oldEnd = lis->getMBBEndIdx(*curBlockItr); - } - - loopRanges.back().second = - lis->getMBBEndIdx(*llvm::prior(loopMBBs.end())); - - return loopRanges; - } - return lrItr->second; - } - - std::pair LoopSplitter::getLoopSubRange( - const LiveRange &lr, - MachineLoop &loop) { - LoopRanges &loopRanges = getLoopRanges(loop); - LoopRanges::iterator lrItr = loopRanges.begin(), - lrEnd = loopRanges.end(); - while (lrItr != lrEnd && lr.start >= lrItr->second) { - ++lrItr; - } - - if (lrItr == lrEnd) { - SlotIndex invalid = lis->getInvalidIndex(); - return std::make_pair(false, SlotPair(invalid, invalid)); - } - - SlotIndex srStart(lr.start < lrItr->first ? lrItr->first : lr.start); - SlotIndex srEnd(lr.end > lrItr->second ? lrItr->second : lr.end); - - return std::make_pair(true, SlotPair(srStart, srEnd)); - } - - void LoopSplitter::dumpLoopRanges(MachineLoop &loop) { - LoopRanges &loopRanges = getLoopRanges(loop); - dbgs() << "For loop MBB#" << loop.getHeader()->getNumber() << ", subranges are: [ "; - for (LoopRanges::iterator lrItr = loopRanges.begin(), lrEnd = loopRanges.end(); - lrItr != lrEnd; ++lrItr) { - dbgs() << "[" << lrItr->first << ", " << lrItr->second << ") "; - } - dbgs() << "]\n"; - } - - void LoopSplitter::processHeader(LoopSplit &split) { - MachineBasicBlock &header = *split.getLoop().getHeader(); - //dbgs() << " Processing loop header BB#" << header.getNumber() << "\n"; - - if (!lis->isLiveInToMBB(split.getLI(), &header)) - return; // Not live in, but nothing wrong so far. - - MachineBasicBlock *preHeader = split.getLoop().getLoopPreheader(); - if (!preHeader) { - - if (!canInsertPreHeader(split.getLoop())) { - split.invalidate(); - return; // Couldn't insert a pre-header. Bail on this interval. - } - - for (MachineBasicBlock::pred_iterator predItr = header.pred_begin(), - predEnd = header.pred_end(); - predItr != predEnd; ++predItr) { - if (lis->isLiveOutOfMBB(split.getLI(), *predItr)) { - split.splitIncoming(); - break; - } - } - } else if (lis->isLiveOutOfMBB(split.getLI(), preHeader)) { - split.splitIncoming(); - } - } - - void LoopSplitter::processLoopExits(LoopSplit &split) { - typedef SmallVector ExitEdgesList; - ExitEdgesList exitEdges; - split.getLoop().getExitEdges(exitEdges); - - //dbgs() << " Processing loop exits:\n"; - - for (ExitEdgesList::iterator exitEdgeItr = exitEdges.begin(), - exitEdgeEnd = exitEdges.end(); - exitEdgeItr != exitEdgeEnd; ++exitEdgeItr) { - MachineLoop::Edge exitEdge = *exitEdgeItr; - - LiveRange *outRange = - split.getLI().getLiveRangeContaining(lis->getMBBStartIdx(exitEdge.second)); - - if (outRange != 0) { - if (isCriticalEdge(exitEdge) && !canSplitEdge(exitEdge)) { - split.invalidate(); - return; - } - - split.splitOutgoing(exitEdge); - } - } - } - - void LoopSplitter::processLoopUses(LoopSplit &split) { - std::set processed; - - for (MachineRegisterInfo::reg_iterator - rItr = mri->reg_begin(split.getLI().reg), - rEnd = mri->reg_end(); - rItr != rEnd; ++rItr) { - MachineInstr &instr = *rItr; - if (split.getLoop().contains(&instr) && processed.count(&instr) == 0) { - split.addLoopInstr(&instr); - processed.insert(&instr); - } - } - - //dbgs() << " Rewriting reg" << li.reg << " to reg" << newLI->reg - // << " in blocks [ "; - //dbgs() << "]\n"; - } - - bool LoopSplitter::splitOverLoop(LiveInterval &li, MachineLoop &loop) { - assert(TargetRegisterInfo::isVirtualRegister(li.reg) && - "Attempt to split physical register."); - - LoopSplit split(*this, li, loop); - processHeader(split); - if (split.isValid()) - processLoopExits(split); - if (split.isValid()) - processLoopUses(split); - if (split.isValid() /* && split.isWorthwhile() */) { - split.apply(); - DEBUG(dbgs() << "Success.\n"); - return true; - } - DEBUG(dbgs() << "Failed.\n"); - return false; - } - - void LoopSplitter::processInterval(LiveInterval &li) { - std::deque loops; - std::copy(mli->begin(), mli->end(), std::back_inserter(loops)); - - while (!loops.empty()) { - MachineLoop &loop = *loops.front(); - loops.pop_front(); - DEBUG( - dbgs() << fqn << " reg" << li.reg << " " << li.weight << " BB#" - << loop.getHeader()->getNumber() << " "; - ); - if (!splitOverLoop(li, loop)) { - // Couldn't split over outer loop, schedule sub-loops to be checked. - std::copy(loop.begin(), loop.end(), std::back_inserter(loops)); - } - } - } - - void LoopSplitter::processIntervals() { - while (!intervals.empty()) { - LiveInterval &li = *intervals.front(); - intervals.pop_front(); - - assert(!lis->intervalIsInOneMBB(li) && - "Single interval in process worklist."); - - processInterval(li); - } - } - -} Removed: llvm/trunk/lib/CodeGen/Splitter.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/Splitter.h?rev=145896&view=auto ============================================================================== --- llvm/trunk/lib/CodeGen/Splitter.h (original) +++ llvm/trunk/lib/CodeGen/Splitter.h (removed) @@ -1,101 +0,0 @@ -//===-- llvm/CodeGen/Splitter.h - Splitter -*- C++ -*----------------------===// -// -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. -// -//===----------------------------------------------------------------------===// - -#ifndef LLVM_CODEGEN_SPLITTER_H -#define LLVM_CODEGEN_SPLITTER_H - -#include "llvm/CodeGen/MachineFunctionPass.h" -#include "llvm/CodeGen/MachineLoopInfo.h" -#include "llvm/CodeGen/SlotIndexes.h" - -#include -#include -#include -#include - -namespace llvm { - - class LiveInterval; - class LiveIntervals; - struct LiveRange; - class LoopSplit; - class MachineDominatorTree; - class MachineRegisterInfo; - class SlotIndexes; - class TargetInstrInfo; - class VNInfo; - - class LoopSplitter : public MachineFunctionPass { - friend class LoopSplit; - public: - static char ID; - - LoopSplitter() : MachineFunctionPass(ID) { - initializeLoopSplitterPass(*PassRegistry::getPassRegistry()); - } - - virtual void getAnalysisUsage(AnalysisUsage &au) const; - - virtual bool runOnMachineFunction(MachineFunction &fn); - - virtual void releaseMemory(); - - - private: - - MachineFunction *mf; - LiveIntervals *lis; - MachineLoopInfo *mli; - MachineRegisterInfo *mri; - MachineDominatorTree *mdt; - SlotIndexes *sis; - const TargetInstrInfo *tii; - const TargetRegisterInfo *tri; - - std::string fqn; - std::deque intervals; - - typedef std::pair SlotPair; - typedef std::vector LoopRanges; - typedef std::map LoopRangeMap; - LoopRangeMap loopRangeMap; - - void dumpLoopInfo(MachineLoop &loop); - - void dumpOddTerminators(); - - void updateTerminators(MachineBasicBlock &mbb); - - bool canInsertPreHeader(MachineLoop &loop); - MachineBasicBlock& insertPreHeader(MachineLoop &loop); - - bool isCriticalEdge(MachineLoop::Edge &edge); - bool canSplitEdge(MachineLoop::Edge &edge); - MachineBasicBlock& splitEdge(MachineLoop::Edge &edge, MachineLoop &loop); - - LoopRanges& getLoopRanges(MachineLoop &loop); - std::pair getLoopSubRange(const LiveRange &lr, - MachineLoop &loop); - - void dumpLoopRanges(MachineLoop &loop); - - void processHeader(LoopSplit &split); - void processLoopExits(LoopSplit &split); - void processLoopUses(LoopSplit &split); - - bool splitOverLoop(LiveInterval &li, MachineLoop &loop); - - void processInterval(LiveInterval &li); - - void processIntervals(); - }; - -} - -#endif From sabre at nondot.org Mon Dec 5 20:00:33 2011 From: sabre at nondot.org (Chris Lattner) Date: Tue, 06 Dec 2011 02:00:33 -0000 Subject: [llvm-commits] [llvm] r145898 - /llvm/trunk/include/llvm/ADT/TinyPtrVector.h Message-ID: <20111206020033.CB4DA2A6C12C@llvm.org> Author: lattner Date: Mon Dec 5 20:00:33 2011 New Revision: 145898 URL: http://llvm.org/viewvc/llvm-project?rev=145898&view=rev Log: allow TinyPtrVector to implicitly convert to ArrayRef. Modified: llvm/trunk/include/llvm/ADT/TinyPtrVector.h Modified: llvm/trunk/include/llvm/ADT/TinyPtrVector.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/ADT/TinyPtrVector.h?rev=145898&r1=145897&r2=145898&view=diff ============================================================================== --- llvm/trunk/include/llvm/ADT/TinyPtrVector.h (original) +++ llvm/trunk/include/llvm/ADT/TinyPtrVector.h Mon Dec 5 20:00:33 2011 @@ -37,6 +37,15 @@ delete V; } + // implicit conversion operator to ArrayRef. + operator ArrayRef() const { + if (Val.isNull()) + return ArrayRef(); + if (Val.template is()) + return *Val.template getAddrOf(); + return *Val.template get(); + } + bool empty() const { // This vector can be empty if it contains no element, or if it // contains a pointer to an empty vector. From dblaikie at gmail.com Mon Dec 5 20:06:44 2011 From: dblaikie at gmail.com (David Blaikie) Date: Tue, 6 Dec 2011 02:06:44 +0000 Subject: [llvm-commits] [llvm] r145894 - in /llvm/trunk/lib/Target: Mips/MCTargetDesc/MipsAsmBackend.cpp PowerPC/MCTargetDesc/PPCAsmBackend.cpp In-Reply-To: <20111206014832.F01782A6C12C@llvm.org> References: <20111206014832.F01782A6C12C@llvm.org> Message-ID: On Tue, Dec 6, 2011 at 1:48 AM, NAKAMURA Takumi wrote: > Author: chapuni > Date: Mon Dec ?5 19:48:32 2011 > New Revision: 145894 > > URL: http://llvm.org/viewvc/llvm-project?rev=145894&view=rev > Log: > MipsAsmBackend.cpp, PPCAsmBackend.cpp: Fix -Asserts build to appease msvc. > > Modified: > ? ?llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsAsmBackend.cpp > ? ?llvm/trunk/lib/Target/PowerPC/MCTargetDesc/PPCAsmBackend.cpp > > Modified: llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsAsmBackend.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsAsmBackend.cpp?rev=145894&r1=145893&r2=145894&view=diff > ============================================================================== > --- llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsAsmBackend.cpp (original) > +++ llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsAsmBackend.cpp Mon Dec ?5 19:48:32 2011 > @@ -181,6 +181,7 @@ > ? ? ? ? ? ? ? ? ? ? ? ? ? ? const MCAsmLayout &Layout) const { > ? ? // FIXME. > ? ? assert(0 && "RelaxInstruction() unimplemented"); > + ? ?return false; Does llvm_unreachable also (as an alternative, not in addition to) silence MSVC? > ? } > > ? /// RelaxInstruction - Relax the instruction in the given fragment > > Modified: llvm/trunk/lib/Target/PowerPC/MCTargetDesc/PPCAsmBackend.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/MCTargetDesc/PPCAsmBackend.cpp?rev=145894&r1=145893&r2=145894&view=diff > ============================================================================== > --- llvm/trunk/lib/Target/PowerPC/MCTargetDesc/PPCAsmBackend.cpp (original) > +++ llvm/trunk/lib/Target/PowerPC/MCTargetDesc/PPCAsmBackend.cpp Mon Dec ?5 19:48:32 2011 > @@ -100,6 +100,7 @@ > ? ? ? ? ? ? ? ? ? ? ? ? ? ? const MCAsmLayout &Layout) const { > ? ? // FIXME. > ? ? assert(0 && "RelaxInstruction() unimplemented"); > + ? ?return false; > ? } > > > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From peter_cooper at apple.com Mon Dec 5 20:06:50 2011 From: peter_cooper at apple.com (Pete Cooper) Date: Tue, 06 Dec 2011 02:06:50 -0000 Subject: [llvm-commits] [llvm] r145899 - /llvm/trunk/lib/CodeGen/RegisterCoalescer.cpp Message-ID: <20111206020650.E730C2A6C12C@llvm.org> Author: pete Date: Mon Dec 5 20:06:50 2011 New Revision: 145899 URL: http://llvm.org/viewvc/llvm-project?rev=145899&view=rev Log: Removed isWinToJoinCrossClass from the register coalescer. The new register allocator is much more able to split back up ranges too constrained by register classes. Fixes Modified: llvm/trunk/lib/CodeGen/RegisterCoalescer.cpp Modified: llvm/trunk/lib/CodeGen/RegisterCoalescer.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/RegisterCoalescer.cpp?rev=145899&r1=145898&r2=145899&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/RegisterCoalescer.cpp (original) +++ llvm/trunk/lib/CodeGen/RegisterCoalescer.cpp Mon Dec 5 20:06:50 2011 @@ -149,14 +149,6 @@ /// shouldJoinPhys - Return true if a physreg copy should be joined. bool shouldJoinPhys(CoalescerPair &CP); - /// isWinToJoinCrossClass - Return true if it's profitable to coalesce - /// two virtual registers from different register classes. - bool isWinToJoinCrossClass(unsigned SrcReg, - unsigned DstReg, - const TargetRegisterClass *SrcRC, - const TargetRegisterClass *DstRC, - const TargetRegisterClass *NewRC); - /// UpdateRegDefsUses - Replace all defs and uses of SrcReg to DstReg and /// update the subregister number if it is not zero. If DstReg is a /// physical register and the existing subregister number of the def / use @@ -1095,56 +1087,6 @@ return true; } -/// isWinToJoinCrossClass - Return true if it's profitable to coalesce -/// two virtual registers from different register classes. -bool -RegisterCoalescer::isWinToJoinCrossClass(unsigned SrcReg, - unsigned DstReg, - const TargetRegisterClass *SrcRC, - const TargetRegisterClass *DstRC, - const TargetRegisterClass *NewRC) { - unsigned NewRCCount = RegClassInfo.getNumAllocatableRegs(NewRC); - // This heuristics is good enough in practice, but it's obviously not *right*. - // 4 is a magic number that works well enough for x86, ARM, etc. It filter - // out all but the most restrictive register classes. - if (NewRCCount > 4 || - // Early exit if the function is fairly small, coalesce aggressively if - // that's the case. For really special register classes with 3 or - // fewer registers, be a bit more careful. - (LIS->getFuncInstructionCount() / NewRCCount) < 8) - return true; - LiveInterval &SrcInt = LIS->getInterval(SrcReg); - LiveInterval &DstInt = LIS->getInterval(DstReg); - unsigned SrcSize = LIS->getApproximateInstructionCount(SrcInt); - unsigned DstSize = LIS->getApproximateInstructionCount(DstInt); - - // Coalesce aggressively if the intervals are small compared to the number of - // registers in the new class. The number 4 is fairly arbitrary, chosen to be - // less aggressive than the 8 used for the whole function size. - const unsigned ThresSize = 4 * NewRCCount; - if (SrcSize <= ThresSize && DstSize <= ThresSize) - return true; - - // Estimate *register use density*. If it doubles or more, abort. - unsigned SrcUses = std::distance(MRI->use_nodbg_begin(SrcReg), - MRI->use_nodbg_end()); - unsigned DstUses = std::distance(MRI->use_nodbg_begin(DstReg), - MRI->use_nodbg_end()); - unsigned NewUses = SrcUses + DstUses; - unsigned NewSize = SrcSize + DstSize; - if (SrcRC != NewRC && SrcSize > ThresSize) { - unsigned SrcRCCount = RegClassInfo.getNumAllocatableRegs(SrcRC); - if (NewUses*SrcSize*SrcRCCount > 2*SrcUses*NewSize*NewRCCount) - return false; - } - if (DstRC != NewRC && DstSize > ThresSize) { - unsigned DstRCCount = RegClassInfo.getNumAllocatableRegs(DstRC); - if (NewUses*DstSize*DstRCCount > 2*DstUses*NewSize*NewRCCount) - return false; - } - return true; -} - /// JoinCopy - Attempt to join intervals corresponding to SrcReg/DstReg, /// which are the src/dst of the copy instruction CopyMI. This returns true @@ -1202,14 +1144,6 @@ DEBUG(dbgs() << "\tCross-class joins disabled.\n"); return false; } - if (!isWinToJoinCrossClass(CP.getSrcReg(), CP.getDstReg(), - MRI->getRegClass(CP.getSrcReg()), - MRI->getRegClass(CP.getDstReg()), - CP.getNewRC())) { - DEBUG(dbgs() << "\tAvoid coalescing to constrained register class.\n"); - Again = true; // May be possible to coalesce later. - return false; - } } // When possible, let DstReg be the larger interval. From geek4civic at gmail.com Mon Dec 5 20:27:06 2011 From: geek4civic at gmail.com (NAKAMURA Takumi) Date: Tue, 6 Dec 2011 11:27:06 +0900 Subject: [llvm-commits] [llvm] r145894 - in /llvm/trunk/lib/Target: Mips/MCTargetDesc/MipsAsmBackend.cpp PowerPC/MCTargetDesc/PPCAsmBackend.cpp In-Reply-To: References: <20111206014832.F01782A6C12C@llvm.org> Message-ID: > Does llvm_unreachable also (as an alternative, not in addition to) silence MSVC? David, I think it could be as-is if they would be fixed in near future. Jim, how is your plan? If they were "should not be implemented", please replace them with llvm_unreachable(). ...Takumi From evan.cheng at apple.com Mon Dec 5 20:49:07 2011 From: evan.cheng at apple.com (Evan Cheng) Date: Tue, 06 Dec 2011 02:49:07 -0000 Subject: [llvm-commits] [llvm] r145903 - /llvm/trunk/lib/CodeGen/MachineSSAUpdater.cpp Message-ID: <20111206024907.2D8112A6C12C@llvm.org> Author: evancheng Date: Mon Dec 5 20:49:06 2011 New Revision: 145903 URL: http://llvm.org/viewvc/llvm-project?rev=145903&view=rev Log: Mix some minor misuse of MachineBasicBlock iterator. Modified: llvm/trunk/lib/CodeGen/MachineSSAUpdater.cpp Modified: llvm/trunk/lib/CodeGen/MachineSSAUpdater.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineSSAUpdater.cpp?rev=145903&r1=145902&r2=145903&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/MachineSSAUpdater.cpp (original) +++ llvm/trunk/lib/CodeGen/MachineSSAUpdater.cpp Mon Dec 5 20:49:06 2011 @@ -81,7 +81,7 @@ if (BB->empty()) return 0; - MachineBasicBlock::iterator I = BB->front(); + MachineBasicBlock::iterator I = BB->begin(); if (!I->isPHI()) return 0; @@ -182,7 +182,7 @@ return DupPHI; // Otherwise, we do need a PHI: insert one now. - MachineBasicBlock::iterator Loc = BB->empty() ? BB->end() : BB->front(); + MachineBasicBlock::iterator Loc = BB->empty() ? BB->end() : BB->begin(); MachineInstr *InsertedPHI = InsertNewDef(TargetOpcode::PHI, BB, Loc, VRC, MRI, TII); @@ -311,7 +311,7 @@ /// Add it into the specified block and return the register. static unsigned CreateEmptyPHI(MachineBasicBlock *BB, unsigned NumPreds, MachineSSAUpdater *Updater) { - MachineBasicBlock::iterator Loc = BB->empty() ? BB->end() : BB->front(); + MachineBasicBlock::iterator Loc = BB->empty() ? BB->end() : BB->begin(); MachineInstr *PHI = InsertNewDef(TargetOpcode::PHI, BB, Loc, Updater->VRC, Updater->MRI, Updater->TII); From atrick at apple.com Mon Dec 5 21:13:32 2011 From: atrick at apple.com (Andrew Trick) Date: Tue, 06 Dec 2011 03:13:32 -0000 Subject: [llvm-commits] [llvm] r145906 - in /llvm/trunk: lib/Transforms/Scalar/LoopStrengthReduce.cpp test/Transforms/LoopStrengthReduce/2011-12-04-loserreg.ll Message-ID: <20111206031332.4BC0E2A6C12C@llvm.org> Author: atrick Date: Mon Dec 5 21:13:31 2011 New Revision: 145906 URL: http://llvm.org/viewvc/llvm-project?rev=145906&view=rev Log: LSR: prune undesirable formulae early. It's always good to prune early, but formulae that are unsatisfactory in their own right need to be removed before running any other pruning heuristics. We easily avoid generating such formulae, but we need them as an intermediate basis for forming other good formulae. Added: llvm/trunk/test/Transforms/LoopStrengthReduce/2011-12-04-loserreg.ll Modified: llvm/trunk/lib/Transforms/Scalar/LoopStrengthReduce.cpp Modified: llvm/trunk/lib/Transforms/Scalar/LoopStrengthReduce.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/LoopStrengthReduce.cpp?rev=145906&r1=145905&r2=145906&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Scalar/LoopStrengthReduce.cpp (original) +++ llvm/trunk/lib/Transforms/Scalar/LoopStrengthReduce.cpp Mon Dec 5 21:13:31 2011 @@ -634,6 +634,19 @@ return AccessTy; } +/// isExistingPhi - Return true if this AddRec is already a phi in its loop. +static bool isExistingPhi(const SCEVAddRecExpr *AR, ScalarEvolution &SE) { + for (BasicBlock::iterator I = AR->getLoop()->getHeader()->begin(); + PHINode *PN = dyn_cast(I); ++I) { + if (SE.isSCEVable(PN->getType()) && + (SE.getEffectiveSCEVType(PN->getType()) == + SE.getEffectiveSCEVType(AR->getType())) && + SE.getSCEV(PN) == AR) + return true; + } + return false; +} + /// DeleteTriviallyDeadInstructions - If any of the instructions is the /// specified set are trivially dead, delete them and see if this makes any of /// their operands subsequently dead. @@ -703,7 +716,8 @@ const DenseSet &VisitedRegs, const Loop *L, const SmallVectorImpl &Offsets, - ScalarEvolution &SE, DominatorTree &DT); + ScalarEvolution &SE, DominatorTree &DT, + SmallPtrSet *LoserRegs = 0); void print(raw_ostream &OS) const; void dump() const; @@ -716,7 +730,8 @@ void RatePrimaryRegister(const SCEV *Reg, SmallPtrSet &Regs, const Loop *L, - ScalarEvolution &SE, DominatorTree &DT); + ScalarEvolution &SE, DominatorTree &DT, + SmallPtrSet *LoserRegs); }; } @@ -736,18 +751,13 @@ // on other loops, and cannot be expected to change sibling loops. If the // AddRec exists, consider it's register free and leave it alone. Otherwise, // do not consider this formula at all. - // FIXME: why do we need to generate such fomulae? else if (!EnableNested || L->contains(AR->getLoop()) || (!AR->getLoop()->contains(L) && DT.dominates(L->getHeader(), AR->getLoop()->getHeader()))) { - for (BasicBlock::iterator I = AR->getLoop()->getHeader()->begin(); - PHINode *PN = dyn_cast(I); ++I) { - if (SE.isSCEVable(PN->getType()) && - (SE.getEffectiveSCEVType(PN->getType()) == - SE.getEffectiveSCEVType(AR->getType())) && - SE.getSCEV(PN) == AR) - return; - } + if (isExistingPhi(AR, SE)) + return; + + // For !EnableNested, never rewrite IVs in other loops. if (!EnableNested) { Loose(); return; @@ -789,13 +799,22 @@ } /// RatePrimaryRegister - Record this register in the set. If we haven't seen it -/// before, rate it. +/// before, rate it. Optional LoserRegs provides a way to declare any formula +/// that refers to one of those regs an instant loser. void Cost::RatePrimaryRegister(const SCEV *Reg, SmallPtrSet &Regs, const Loop *L, - ScalarEvolution &SE, DominatorTree &DT) { - if (Regs.insert(Reg)) + ScalarEvolution &SE, DominatorTree &DT, + SmallPtrSet *LoserRegs) { + if (LoserRegs && LoserRegs->count(Reg)) { + Loose(); + return; + } + if (Regs.insert(Reg)) { RateRegister(Reg, Regs, L, SE, DT); + if (isLoser()) + LoserRegs->insert(Reg); + } } void Cost::RateFormula(const Formula &F, @@ -803,14 +822,15 @@ const DenseSet &VisitedRegs, const Loop *L, const SmallVectorImpl &Offsets, - ScalarEvolution &SE, DominatorTree &DT) { + ScalarEvolution &SE, DominatorTree &DT, + SmallPtrSet *LoserRegs) { // Tally up the registers. if (const SCEV *ScaledReg = F.ScaledReg) { if (VisitedRegs.count(ScaledReg)) { Loose(); return; } - RatePrimaryRegister(ScaledReg, Regs, L, SE, DT); + RatePrimaryRegister(ScaledReg, Regs, L, SE, DT, LoserRegs); if (isLoser()) return; } @@ -821,7 +841,7 @@ Loose(); return; } - RatePrimaryRegister(BaseReg, Regs, L, SE, DT); + RatePrimaryRegister(BaseReg, Regs, L, SE, DT, LoserRegs); if (isLoser()) return; } @@ -1103,7 +1123,6 @@ Formulae.push_back(F); // Record registers now being used by this use. - if (F.ScaledReg) Regs.insert(F.ScaledReg); Regs.insert(F.BaseRegs.begin(), F.BaseRegs.end()); return true; @@ -1114,7 +1133,6 @@ if (&F != &Formulae.back()) std::swap(F, Formulae.back()); Formulae.pop_back(); - assert(!Formulae.empty() && "LSRUse has no formulae left!"); } /// RecomputeRegs - Recompute the Regs field, and update RegUses. @@ -2912,6 +2930,7 @@ void LSRInstance::FilterOutUndesirableDedicatedRegisters() { DenseSet VisitedRegs; SmallPtrSet Regs; + SmallPtrSet LoserRegs; #ifndef NDEBUG bool ChangedFormulae = false; #endif @@ -2931,46 +2950,66 @@ FIdx != NumForms; ++FIdx) { Formula &F = LU.Formulae[FIdx]; - SmallVector Key; - for (SmallVectorImpl::const_iterator J = F.BaseRegs.begin(), - JE = F.BaseRegs.end(); J != JE; ++J) { - const SCEV *Reg = *J; - if (RegUses.isRegUsedByUsesOtherThan(Reg, LUIdx)) - Key.push_back(Reg); - } - if (F.ScaledReg && - RegUses.isRegUsedByUsesOtherThan(F.ScaledReg, LUIdx)) - Key.push_back(F.ScaledReg); - // Unstable sort by host order ok, because this is only used for - // uniquifying. - std::sort(Key.begin(), Key.end()); - - std::pair P = - BestFormulae.insert(std::make_pair(Key, FIdx)); - if (!P.second) { + // Some formulas are instant losers. For example, they may depend on + // nonexistent AddRecs from other loops. These need to be filtered + // immediately, otherwise heuristics could choose them over others leading + // to an unsatisfactory solution. Passing LoserRegs into RateFormula here + // avoids the need to recompute this information across formulae using the + // same bad AddRec. Passing LoserRegs is also essential unless we remove + // the corresponding bad register from the Regs set. + Cost CostF; + Regs.clear(); + CostF.RateFormula(F, Regs, VisitedRegs, L, LU.Offsets, SE, DT, + &LoserRegs); + if (CostF.isLoser()) { + // During initial formula generation, undesirable formulae are generated + // by uses within other loops that have some non-trivial address mode or + // use the postinc form of the IV. LSR needs to provide these formulae + // as the basis of rediscovering the desired formula that uses an AddRec + // corresponding to the existing phi. Once all formulae have been + // generated, these initial losers may be pruned. + DEBUG(dbgs() << " Filtering loser "; F.print(dbgs()); + dbgs() << "\n"); + } + else { + SmallVector Key; + for (SmallVectorImpl::const_iterator J = F.BaseRegs.begin(), + JE = F.BaseRegs.end(); J != JE; ++J) { + const SCEV *Reg = *J; + if (RegUses.isRegUsedByUsesOtherThan(Reg, LUIdx)) + Key.push_back(Reg); + } + if (F.ScaledReg && + RegUses.isRegUsedByUsesOtherThan(F.ScaledReg, LUIdx)) + Key.push_back(F.ScaledReg); + // Unstable sort by host order ok, because this is only used for + // uniquifying. + std::sort(Key.begin(), Key.end()); + + std::pair P = + BestFormulae.insert(std::make_pair(Key, FIdx)); + if (P.second) + continue; + Formula &Best = LU.Formulae[P.first->second]; - Cost CostF; - CostF.RateFormula(F, Regs, VisitedRegs, L, LU.Offsets, SE, DT); - Regs.clear(); Cost CostBest; - CostBest.RateFormula(Best, Regs, VisitedRegs, L, LU.Offsets, SE, DT); Regs.clear(); + CostBest.RateFormula(Best, Regs, VisitedRegs, L, LU.Offsets, SE, DT); if (CostF < CostBest) std::swap(F, Best); DEBUG(dbgs() << " Filtering out formula "; F.print(dbgs()); dbgs() << "\n" " in favor of formula "; Best.print(dbgs()); dbgs() << '\n'); + } #ifndef NDEBUG - ChangedFormulae = true; + ChangedFormulae = true; #endif - LU.DeleteFormula(F); - --FIdx; - --NumForms; - Any = true; - continue; - } + LU.DeleteFormula(F); + --FIdx; + --NumForms; + Any = true; } // Now that we've filtered out some formulae, recompute the Regs set. Added: llvm/trunk/test/Transforms/LoopStrengthReduce/2011-12-04-loserreg.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/LoopStrengthReduce/2011-12-04-loserreg.ll?rev=145906&view=auto ============================================================================== --- llvm/trunk/test/Transforms/LoopStrengthReduce/2011-12-04-loserreg.ll (added) +++ llvm/trunk/test/Transforms/LoopStrengthReduce/2011-12-04-loserreg.ll Mon Dec 5 21:13:31 2011 @@ -0,0 +1,96 @@ +; RUN: llc < %s | FileCheck %s +; +; Test LSR's ability to prune formulae that refer to nonexistant +; AddRecs in other loops. +; +; Unable to reduce this case further because it requires LSR to exceed +; ComplexityLimit. +; +; We really just want to ensure that LSR can process this loop without +; finding an unsatisfactory solution and bailing out. I've added +; dummyout, an obvious candidate for postinc replacement so we can +; verify that LSR removes it. + +target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128" +target triple = "x86_64-apple-darwin" + +; CHECK: @test +; CHECK: # %for.body{{$}} +; dummyiv copy should be removed +; CHECK-NOT: movq +; CHECK: # %for.cond19.preheader +; dummycnt should be removed +; CHECK-NOT: incq +; CHECK: # %for.body23{{$}} +define i64 @test(i64 %count, float* nocapture %srcrow, i32* nocapture %destrow) nounwind uwtable ssp { +entry: + %cmp34 = icmp eq i64 %count, 0 + br i1 %cmp34, label %for.end29, label %for.body + +for.body: ; preds = %entry, %for.body + %dummyiv = phi i64 [ %dummycnt, %for.body ], [ 0, %entry ] + %indvars.iv39 = phi i64 [ %indvars.iv.next40, %for.body ], [ 0, %entry ] + %dp.036 = phi i32* [ %add.ptr, %for.body ], [ %destrow, %entry ] + %p.035 = phi float* [ %incdec.ptr4, %for.body ], [ %srcrow, %entry ] + %incdec.ptr = getelementptr inbounds float* %p.035, i64 1 + %0 = load float* %incdec.ptr, align 4 + %incdec.ptr2 = getelementptr inbounds float* %p.035, i64 2 + %1 = load float* %incdec.ptr2, align 4 + %incdec.ptr3 = getelementptr inbounds float* %p.035, i64 3 + %2 = load float* %incdec.ptr3, align 4 + %incdec.ptr4 = getelementptr inbounds float* %p.035, i64 4 + %3 = load float* %incdec.ptr4, align 4 + %4 = load i32* %dp.036, align 4 + %conv5 = fptoui float %0 to i32 + %or = or i32 %4, %conv5 + %arrayidx6 = getelementptr inbounds i32* %dp.036, i64 1 + %5 = load i32* %arrayidx6, align 4 + %conv7 = fptoui float %1 to i32 + %or8 = or i32 %5, %conv7 + %arrayidx9 = getelementptr inbounds i32* %dp.036, i64 2 + %6 = load i32* %arrayidx9, align 4 + %conv10 = fptoui float %2 to i32 + %or11 = or i32 %6, %conv10 + %arrayidx12 = getelementptr inbounds i32* %dp.036, i64 3 + %7 = load i32* %arrayidx12, align 4 + %conv13 = fptoui float %3 to i32 + %or14 = or i32 %7, %conv13 + store i32 %or, i32* %dp.036, align 4 + store i32 %or8, i32* %arrayidx6, align 4 + store i32 %or11, i32* %arrayidx9, align 4 + store i32 %or14, i32* %arrayidx12, align 4 + %add.ptr = getelementptr inbounds i32* %dp.036, i64 4 + %indvars.iv.next40 = add i64 %indvars.iv39, 4 + %dummycnt = add i64 %dummyiv, 1 + %cmp = icmp ult i64 %indvars.iv.next40, %count + br i1 %cmp, label %for.body, label %for.cond19.preheader + +for.cond19.preheader: ; preds = %for.body + %dummyout = add i64 %dummyiv, 1 + %rem = and i64 %count, 3 + %cmp2130 = icmp eq i64 %rem, 0 + br i1 %cmp2130, label %for.end29, label %for.body23.lr.ph + +for.body23.lr.ph: ; preds = %for.cond19.preheader + %8 = and i64 %count, 3 + br label %for.body23 + +for.body23: ; preds = %for.body23, %for.body23.lr.ph + %indvars.iv = phi i64 [ 0, %for.body23.lr.ph ], [ %indvars.iv.next, %for.body23 ] + %dp.132 = phi i32* [ %add.ptr, %for.body23.lr.ph ], [ %incdec.ptr28, %for.body23 ] + %p.131 = phi float* [ %incdec.ptr4, %for.body23.lr.ph ], [ %incdec.ptr24, %for.body23 ] + %incdec.ptr24 = getelementptr inbounds float* %p.131, i64 1 + %9 = load float* %incdec.ptr24, align 4 + %10 = load i32* %dp.132, align 4 + %conv25 = fptoui float %9 to i32 + %or26 = or i32 %10, %conv25 + store i32 %or26, i32* %dp.132, align 4 + %indvars.iv.next = add i64 %indvars.iv, 1 + %incdec.ptr28 = getelementptr inbounds i32* %dp.132, i64 1 + %exitcond = icmp eq i64 %indvars.iv.next, %8 + br i1 %exitcond, label %for.end29, label %for.body23 + +for.end29: ; preds = %entry, %for.body23, %for.cond19.preheader + %result = phi i64 [ 0, %entry ], [ %dummyout, %for.body23 ], [ %dummyout, %for.cond19.preheader ] + ret i64 %result +} From stoklund at 2pi.dk Mon Dec 5 21:19:58 2011 From: stoklund at 2pi.dk (Jakob Stoklund Olesen) Date: Mon, 5 Dec 2011 19:19:58 -0800 Subject: [llvm-commits] [llvm] r145895 - /llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp In-Reply-To: <20111206015317.3EF8E2A6C12C@llvm.org> References: <20111206015317.3EF8E2A6C12C@llvm.org> Message-ID: On Dec 5, 2011, at 5:53 PM, Jim Grosbach wrote: > // Relax if the value is too big for a (signed) i8. > - return int64_t((Value - 4)>>1) != int64_t(int8_t((Value - 4)>>1)); > + int64_t Offset = int64_t(Value) - 4; > + return Offset > 254 || Offset < -256; Tony was going to add some isShiftedInt templates to compute this stuff. Tony, did you ever write those functions? /jakob From gohman at apple.com Mon Dec 5 21:18:47 2011 From: gohman at apple.com (Dan Gohman) Date: Tue, 06 Dec 2011 03:18:47 -0000 Subject: [llvm-commits] [llvm] r145907 - /llvm/trunk/docs/LangRef.html Message-ID: <20111206031848.04B142A6C12C@llvm.org> Author: djg Date: Mon Dec 5 21:18:47 2011 New Revision: 145907 URL: http://llvm.org/viewvc/llvm-project?rev=145907&view=rev Log: Rename "Trap Values" to "Poison Values", to better reflect their purpose, and to avoid ambiguity with other uses of the word "trap" in LangRef. Modified: llvm/trunk/docs/LangRef.html Modified: llvm/trunk/docs/LangRef.html URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/LangRef.html?rev=145907&r1=145906&r2=145907&view=diff ============================================================================== --- llvm/trunk/docs/LangRef.html (original) +++ llvm/trunk/docs/LangRef.html Mon Dec 5 21:18:47 2011 @@ -92,7 +92,7 @@
  • Complex Constants
  • Global Variable and Function Addresses
  • Undefined Values
    • -
  • Trap Values
    • +
  • Poison Values
  • Addresses of Basic Blocks
  • Constant Expressions
    • @@ -2506,22 +2506,22 @@

    - Trap Values + Poison Values

    -

    Trap values are similar to undef values, however +

    Poison values are similar to undef values, however instead of representing an unspecified bit pattern, they represent the fact that an instruction or constant expression which cannot evoke side effects has nevertheless detected a condition which results in undefined behavior.

    -

    There is currently no way of representing a trap value in the IR; they +

    There is currently no way of representing a poison value in the IR; they only exist when produced by operations such as add with the nsw flag.

    -

    Trap value behavior is defined in terms of value dependence:

    +

    Poison value behavior is defined in terms of value dependence:

    • Values other than phi nodes depend on @@ -2572,31 +2572,31 @@
    -

    Whenever a trap value is generated, all values which depend on it evaluate - to trap. If they have side effects, they evoke their side effects as if each - operand with a trap value were undef. If they have externally-visible side +

    Whenever a poison value is generated, all values which depend on it evaluate + to poison. If they have side effects, they evoke their side effects as if each + operand with a poison value were undef. If they have externally-visible side effects, the behavior is undefined.

    Here are some examples:

     entry:
-  %trap = sub nuw i32 0, 1           ; Results in a trap value.
-  %still_trap = and i32 %trap, 0     ; Whereas (and i32 undef, 0) would return 0.
-  %trap_yet_again = getelementptr i32* @h, i32 %still_trap
-  store i32 0, i32* %trap_yet_again  ; undefined behavior
+  %poison = sub nuw i32 0, 1           ; Results in a poison value.
+  %still_poison = and i32 %poison, 0     ; Whereas (and i32 undef, 0) would return 0.
+  %poison_yet_again = getelementptr i32* @h, i32 %still_poison
+  store i32 0, i32* %poison_yet_again  ; undefined behavior
 
-  store i32 %trap, i32* @g           ; Trap value conceptually stored to memory.
-  %trap2 = load i32* @g              ; Returns a trap value, not just undef.
+  store i32 %poison, i32* @g         ; Poison value conceptually stored to memory.
+  %poison2 = load i32* @g              ; Returns a poison value, not just undef.
 
-  store volatile i32 %trap, i32* @g  ; External observation; undefined behavior.
+  store volatile i32 %poison, i32* @g  ; External observation; undefined behavior.
 
   %narrowaddr = bitcast i32* @g to i16*
   %wideaddr = bitcast i32* @g to i64*
-  %trap3 = load i16* %narrowaddr     ; Returns a trap value.
-  %trap4 = load i64* %wideaddr       ; Returns a trap value.
+  %poison3 = load i16* %narrowaddr     ; Returns a poison value.
+  %poison4 = load i64* %wideaddr       ; Returns a poison value.
 
-  %cmp = icmp slt i32 %trap, 0       ; Returns a trap value.
+  %cmp = icmp slt i32 %poison, 0      ; Returns a poison value.
   br i1 %cmp, label %true, label %end ; Branch to either destination.
 
 true:
@@ -2608,7 +2608,7 @@
   %p = phi i32 [ 0, %entry ], [ 1, %true ]
                                      ; Both edges into this PHI are
                                      ; control-dependent on %cmp, so this
-                                     ; always results in a trap value.
+                                     ; always results in a poison value.
 
   store volatile i32 0, i32* @g      ; This would depend on the store in %true
                                      ; if %cmp is true, or the store in %entry
@@ -3619,7 +3619,7 @@
 
    nuw and nsw stand for "No Unsigned Wrap"
    and "No Signed Wrap", respectively. If the nuw and/or
    nsw keywords are present, the result value of the add
-   is a trap value if unsigned and/or signed overflow,
+   is a poison value if unsigned and/or signed overflow,
    respectively, occurs.
    
 
 
    Example:
    
@@ -3700,7 +3700,7 @@
 
    nuw and nsw stand for "No Unsigned Wrap"
    and "No Signed Wrap", respectively. If the nuw and/or
    nsw keywords are present, the result value of the sub
-   is a trap value if unsigned and/or signed overflow,
+   is a poison value if unsigned and/or signed overflow,
    respectively, occurs.
    
 
 
    Example:
    
@@ -3787,7 +3787,7 @@
 
    nuw and nsw stand for "No Unsigned Wrap"
    and "No Signed Wrap", respectively. If the nuw and/or
    nsw keywords are present, the result value of the mul
-   is a trap value if unsigned and/or signed overflow,
+   is a poison value if unsigned and/or signed overflow,
    respectively, occurs.
    
 
 
    Example:
    
@@ -3857,7 +3857,7 @@
 
    Division by zero leads to undefined behavior.
    
 
 
    If the exact keyword is present, the result value of the
-   udiv is a trap value if %op1 is not a
+   udiv is a poison value if %op1 is not a
   multiple of %op2 (as such, "((a udiv exact b) mul b) == a").
    
 
 
@@ -3901,7 +3901,7 @@
    a 32-bit division of -2147483648 by -1.
    
 
 
    If the exact keyword is present, the result value of the
-   sdiv is a trap value if the result would
+   sdiv is a poison value if the result would
    be rounded.
    
 
 
    Example:
    
@@ -4110,9 +4110,9 @@
    shift amount in op2.
    
 
 
    If the nuw keyword is present, then the shift produces a 
-   trap value if it shifts out any non-zero bits.  If
+   poison value if it shifts out any non-zero bits.  If
    the nsw keyword is present, then the shift produces a
-   trap value if it shifts out any bits that disagree
+   poison value if it shifts out any bits that disagree
    with the resultant sign bit.  As such, NUW/NSW have the same semantics as
    they would if the shift were expressed as a mul instruction with the same
    nsw/nuw bits in (mul %op1, (shl 1, %op2)).
    
@@ -4159,7 +4159,7 @@
    shift amount in op2.
    
 
 
    If the exact keyword is present, the result value of the
-   lshr is a trap value if any of the bits
+   lshr is a poison value if any of the bits
    shifted out are non-zero.
    
 
 
@@ -4207,7 +4207,7 @@
    the corresponding shift amount in op2.
    
 
 
    If the exact keyword is present, the result value of the
-   ashr is a trap value if any of the bits
+   ashr is a poison value if any of the bits
    shifted out are non-zero.
    
 
 
    Example:
    
@@ -5161,7 +5161,7 @@

    If the inbounds keyword is present, the result value of the - getelementptr is a trap value if the + getelementptr is a poison value if the base pointer is not an in bounds address of an allocated object, or if any of the addresses that would be formed by successive addition of the offsets implied by the indices to the base address with infinitely From gohman at apple.com Mon Dec 5 21:31:14 2011 From: gohman at apple.com (Dan Gohman) Date: Tue, 06 Dec 2011 03:31:14 -0000 Subject: [llvm-commits] [llvm] r145908 - /llvm/trunk/docs/LangRef.html Message-ID: <20111206033114.4EE782A6C12C@llvm.org> Author: djg Date: Mon Dec 5 21:31:14 2011 New Revision: 145908 URL: http://llvm.org/viewvc/llvm-project?rev=145908&view=rev Log: Line up the comments in a code example. Modified: llvm/trunk/docs/LangRef.html Modified: llvm/trunk/docs/LangRef.html URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/LangRef.html?rev=145908&r1=145907&r2=145908&view=diff ============================================================================== --- llvm/trunk/docs/LangRef.html (original) +++ llvm/trunk/docs/LangRef.html Mon Dec 5 21:31:14 2011 @@ -2582,11 +2582,11 @@ 

     entry:
   %poison = sub nuw i32 0, 1           ; Results in a poison value.
-  %still_poison = and i32 %poison, 0     ; Whereas (and i32 undef, 0) would return 0.
+  %still_poison = and i32 %poison, 0   ; Whereas (and i32 undef, 0) would return 0.
   %poison_yet_again = getelementptr i32* @h, i32 %still_poison
   store i32 0, i32* %poison_yet_again  ; undefined behavior
 
-  store i32 %poison, i32* @g         ; Poison value conceptually stored to memory.
+  store i32 %poison, i32* @g           ; Poison value conceptually stored to memory.
   %poison2 = load i32* @g              ; Returns a poison value, not just undef.
 
   store volatile i32 %poison, i32* @g  ; External observation; undefined behavior.
@@ -2596,38 +2596,38 @@
   %poison3 = load i16* %narrowaddr     ; Returns a poison value.
   %poison4 = load i64* %wideaddr       ; Returns a poison value.
 
-  %cmp = icmp slt i32 %poison, 0      ; Returns a poison value.
-  br i1 %cmp, label %true, label %end ; Branch to either destination.
+  %cmp = icmp slt i32 %poison, 0       ; Returns a poison value.
+  br i1 %cmp, label %true, label %end  ; Branch to either destination.
 
 true:
-  store volatile i32 0, i32* @g      ; This is control-dependent on %cmp, so
-                                     ; it has undefined behavior.
+  store volatile i32 0, i32* @g        ; This is control-dependent on %cmp, so
+                                       ; it has undefined behavior.
   br label %end
 
 end:
   %p = phi i32 [ 0, %entry ], [ 1, %true ]
-                                     ; Both edges into this PHI are
-                                     ; control-dependent on %cmp, so this
-                                     ; always results in a poison value.
-
-  store volatile i32 0, i32* @g      ; This would depend on the store in %true
-                                     ; if %cmp is true, or the store in %entry
-                                     ; otherwise, so this is undefined behavior.
+                                       ; Both edges into this PHI are
+                                       ; control-dependent on %cmp, so this
+                                       ; always results in a poison value.
+
+  store volatile i32 0, i32* @g        ; This would depend on the store in %true
+                                       ; if %cmp is true, or the store in %entry
+                                       ; otherwise, so this is undefined behavior.
 
   br i1 %cmp, label %second_true, label %second_end
-                                     ; The same branch again, but this time the
-                                     ; true block doesn't have side effects.
+                                       ; The same branch again, but this time the
+                                       ; true block doesn't have side effects.
 
 second_true:
   ; No side effects!
   ret void
 
 second_end:
-  store volatile i32 0, i32* @g      ; This time, the instruction always depends
-                                     ; on the store in %end. Also, it is
-                                     ; control-equivalent to %end, so this is
-                                     ; well-defined (again, ignoring earlier
-                                     ; undefined behavior in this example).
+  store volatile i32 0, i32* @g        ; This time, the instruction always depends
+                                       ; on the store in %end. Also, it is
+                                       ; control-equivalent to %end, so this is
+                                       ; well-defined (again, ignoring earlier
+                                       ; undefined behavior in this example).
    From bruno.cardoso at gmail.com Mon Dec 5 21:34:36 2011 From: bruno.cardoso at gmail.com (Bruno Cardoso Lopes) Date: Tue, 06 Dec 2011 03:34:36 -0000 Subject: [llvm-commits] [llvm] r145910 - in /llvm/trunk/lib/Target/Mips: MCTargetDesc/MipsBaseInfo.h MipsRegisterInfo.cpp Message-ID: <20111206033436.6143A2A6C12C@llvm.org> Author: bruno Date: Mon Dec 5 21:34:36 2011 New Revision: 145910 URL: http://llvm.org/viewvc/llvm-project?rev=145910&view=rev Log: Add register HWR29 numbering. Patch by Jack Carter Modified: llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsBaseInfo.h llvm/trunk/lib/Target/Mips/MipsRegisterInfo.cpp Modified: llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsBaseInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsBaseInfo.h?rev=145910&r1=145909&r2=145910&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsBaseInfo.h (original) +++ llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsBaseInfo.h Mon Dec 5 21:34:36 2011 @@ -180,6 +180,7 @@ case Mips::D14: return 28; case Mips::SP: case Mips::SP_64: case Mips::F29: case Mips::D29_64: + case Mips::HWR29: return 29; case Mips::FP: case Mips::FP_64: case Mips::F30: case Mips::D30_64: case Mips::D15: Modified: llvm/trunk/lib/Target/Mips/MipsRegisterInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsRegisterInfo.cpp?rev=145910&r1=145909&r2=145910&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/MipsRegisterInfo.cpp (original) +++ llvm/trunk/lib/Target/Mips/MipsRegisterInfo.cpp Mon Dec 5 21:34:36 2011 @@ -125,6 +125,7 @@ case Mips::D14: return 28; case Mips::SP: case Mips::SP_64: case Mips::F29: case Mips::D29_64: + case Mips::HWR29: return 29; case Mips::FP: case Mips::FP_64: case Mips::F30: case Mips::D30_64: case Mips::D15: From bruno.cardoso at gmail.com Mon Dec 5 21:34:42 2011 From: bruno.cardoso at gmail.com (Bruno Cardoso Lopes) Date: Tue, 06 Dec 2011 03:34:42 -0000 Subject: [llvm-commits] [llvm] r145911 - in /llvm/trunk/lib/MC: ELFObjectWriter.cpp ELFObjectWriter.h Message-ID: <20111206033442.E04352A6C12C@llvm.org> Author: bruno Date: Mon Dec 5 21:34:42 2011 New Revision: 145911 URL: http://llvm.org/viewvc/llvm-project?rev=145911&view=rev Log: Explicit symbols for gnu mimicing relocations. Patch by Jack Carter Modified: llvm/trunk/lib/MC/ELFObjectWriter.cpp llvm/trunk/lib/MC/ELFObjectWriter.h Modified: llvm/trunk/lib/MC/ELFObjectWriter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/ELFObjectWriter.cpp?rev=145911&r1=145910&r2=145911&view=diff ============================================================================== --- llvm/trunk/lib/MC/ELFObjectWriter.cpp (original) +++ llvm/trunk/lib/MC/ELFObjectWriter.cpp Mon Dec 5 21:34:42 2011 @@ -1831,6 +1831,20 @@ ELF::EF_MIPS_ARCH_32R2); } +const MCSymbol *MipsELFObjectWriter::ExplicitRelSym(const MCAssembler &Asm, + const MCValue &Target, + const MCFragment &F, + const MCFixup &Fixup, + bool IsPCRel) const { + assert(Target.getSymA() && "SymA cannot be 0."); + const MCSymbol &Sym = Target.getSymA()->getSymbol(); + + if (Sym.getSection().getKind().isMergeable1ByteCString()) + return &Sym; + + return NULL; +} + unsigned MipsELFObjectWriter::GetRelocType(const MCValue &Target, const MCFixup &Fixup, bool IsPCRel, Modified: llvm/trunk/lib/MC/ELFObjectWriter.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/ELFObjectWriter.h?rev=145911&r1=145910&r2=145911&view=diff ============================================================================== --- llvm/trunk/lib/MC/ELFObjectWriter.h (original) +++ llvm/trunk/lib/MC/ELFObjectWriter.h Mon Dec 5 21:34:42 2011 @@ -445,6 +445,12 @@ virtual void WriteEFlags(); protected: + virtual const MCSymbol *ExplicitRelSym(const MCAssembler &Asm, + const MCValue &Target, + const MCFragment &F, + const MCFixup &Fixup, + bool IsPCRel) const; + virtual unsigned GetRelocType(const MCValue &Target, const MCFixup &Fixup, bool IsPCRel, bool IsRelocWithSymbol, int64_t Addend); From bruno.cardoso at gmail.com Mon Dec 5 21:34:49 2011 From: bruno.cardoso at gmail.com (Bruno Cardoso Lopes) Date: Tue, 06 Dec 2011 03:34:49 -0000 Subject: [llvm-commits] [llvm] r145912 - in /llvm/trunk/lib/Target/Mips: MipsInstrFormats.td MipsInstrInfo.cpp MipsInstrInfo.td Message-ID: <20111206033449.22EBB2A6C12C@llvm.org> Author: bruno Date: Mon Dec 5 21:34:48 2011 New Revision: 145912 URL: http://llvm.org/viewvc/llvm-project?rev=145912&view=rev Log: Use branches instead of jumps + variable cleanup. Testcase coming next. Patch by Jack Carter Modified: llvm/trunk/lib/Target/Mips/MipsInstrFormats.td llvm/trunk/lib/Target/Mips/MipsInstrInfo.cpp llvm/trunk/lib/Target/Mips/MipsInstrInfo.td Modified: llvm/trunk/lib/Target/Mips/MipsInstrFormats.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsInstrFormats.td?rev=145912&r1=145911&r2=145912&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/MipsInstrFormats.td (original) +++ llvm/trunk/lib/Target/Mips/MipsInstrFormats.td Mon Dec 5 21:34:48 2011 @@ -115,7 +115,7 @@ let Inst{15-0} = imm16; } -class CBranchBase op, dag outs, dag ins, string asmstr, +class BranchBase op, dag outs, dag ins, string asmstr, list pattern, InstrItinClass itin>: MipsInst { Modified: llvm/trunk/lib/Target/Mips/MipsInstrInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsInstrInfo.cpp?rev=145912&r1=145911&r2=145912&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/MipsInstrInfo.cpp (original) +++ llvm/trunk/lib/Target/Mips/MipsInstrInfo.cpp Mon Dec 5 21:34:48 2011 @@ -236,7 +236,7 @@ Opc == Mips::BGEZ || Opc == Mips::BLTZ || Opc == Mips::BLEZ || Opc == Mips::BEQ64 || Opc == Mips::BNE64 || Opc == Mips::BGTZ64 || Opc == Mips::BGEZ64 || Opc == Mips::BLTZ64 || Opc == Mips::BLEZ64 || - Opc == Mips::BC1T || Opc == Mips::BC1F || Opc == Mips::J) ? + Opc == Mips::BC1T || Opc == Mips::BC1F || Opc == Mips::B) ? Opc : 0; } @@ -320,7 +320,7 @@ // If there is only one terminator instruction, process it. if (!SecondLastOpc) { // Unconditional branch - if (LastOpc == Mips::J) { + if (LastOpc == Mips::B) { TBB = LastInst->getOperand(0).getMBB(); return false; } @@ -337,7 +337,7 @@ // If second to last instruction is an unconditional branch, // analyze it and remove the last instruction. - if (SecondLastOpc == Mips::J) { + if (SecondLastOpc == Mips::B) { // Return if the last instruction cannot be removed. if (!AllowModify) return true; @@ -349,7 +349,7 @@ // Conditional branch followed by an unconditional branch. // The last one must be unconditional. - if (LastOpc != Mips::J) + if (LastOpc != Mips::B) return true; AnalyzeCondBr(SecondLastInst, SecondLastOpc, TBB, Cond); @@ -391,14 +391,14 @@ // Two-way Conditional branch. if (FBB) { BuildCondBr(MBB, TBB, DL, Cond); - BuildMI(&MBB, DL, get(Mips::J)).addMBB(FBB); + BuildMI(&MBB, DL, get(Mips::B)).addMBB(FBB); return 2; } // One way branch. // Unconditional branch. if (Cond.empty()) - BuildMI(&MBB, DL, get(Mips::J)).addMBB(TBB); + BuildMI(&MBB, DL, get(Mips::B)).addMBB(TBB); else // Conditional branch. BuildCondBr(MBB, TBB, DL, Cond); return 1; Modified: llvm/trunk/lib/Target/Mips/MipsInstrInfo.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsInstrInfo.td?rev=145912&r1=145911&r2=145912&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/MipsInstrInfo.td (original) +++ llvm/trunk/lib/Target/Mips/MipsInstrInfo.td Mon Dec 5 21:34:48 2011 @@ -380,21 +380,13 @@ let isPseudo = Pseudo; } -// Memory Load/Store +// Unaligned Memory Load/Store let canFoldAsLoad = 1 in -class LoadX op, RegisterClass RC, - Operand MemOpnd>: - FMem { -} +class LoadUnAlign op, RegisterClass RC, Operand MemOpnd>: + FMem {} -class StoreX op, RegisterClass RC, - Operand MemOpnd>: - FMem { -} +class StoreUnAlign op, RegisterClass RC, Operand MemOpnd>: + FMem {} // 32-bit load. multiclass LoadM32 op, string instr_asm, PatFrag OpNode, @@ -415,10 +407,10 @@ } // 32-bit load. -multiclass LoadX32 op> { - def #NAME# : LoadX, +multiclass LoadUnAlign32 op> { + def #NAME# : LoadUnAlign, Requires<[NotN64]>; - def _P8 : LoadX, + def _P8 : LoadUnAlign, Requires<[IsN64]>; } // 32-bit store. @@ -440,18 +432,18 @@ } // 32-bit store. -multiclass StoreX32 op> { - def #NAME# : StoreX, +multiclass StoreUnAlign32 op> { + def #NAME# : StoreUnAlign, Requires<[NotN64]>; - def _P8 : StoreX, + def _P8 : StoreUnAlign, Requires<[IsN64]>; } // Conditional Branch class CBranch op, string instr_asm, PatFrag cond_op, RegisterClass RC>: - CBranchBase { + BranchBase { let isBranch = 1; let isTerminator = 1; let hasDelaySlot = 1; @@ -459,9 +451,9 @@ class CBranchZero op, bits<5> _rt, string instr_asm, PatFrag cond_op, RegisterClass RC>: - CBranchBase { + BranchBase { let rt = _rt; let isBranch = 1; let isTerminator = 1; @@ -486,10 +478,16 @@ IIAlu>; // Unconditional branch -let isBranch=1, isTerminator=1, isBarrier=1, hasDelaySlot = 1 in -class JumpFJ op, string instr_asm>: - FJ; +class UncondBranch op, string instr_asm>: + BranchBase { + let rs = 0; + let rt = 0; + let isBranch = 1; + let isTerminator = 1; + let isBarrier = 1; + let hasDelaySlot = 1; +} let isBranch=1, isTerminator=1, isBarrier=1, rd=0, hasDelaySlot = 1, isIndirectBranch = 1 in @@ -810,10 +808,10 @@ defm USW : StoreM32<0x2b, "usw", store_u, 1>; /// Primitives for unaligned -defm LWL : LoadX32<0x22>; -defm LWR : LoadX32<0x26>; -defm SWL : StoreX32<0x2A>; -defm SWR : StoreX32<0x2E>; +defm LWL : LoadUnAlign32<0x22>; +defm LWR : LoadUnAlign32<0x26>; +defm SWL : StoreUnAlign32<0x2A>; +defm SWR : StoreUnAlign32<0x2E>; let hasSideEffects = 1 in def SYNC : MipsInst<(outs), (ins i32imm:$stype), "sync $stype", @@ -833,10 +831,10 @@ def SC_P8 : SCBase<0x38, "sc", CPURegs, mem64>, Requires<[IsN64]>; /// Jump and Branch Instructions -def J : JumpFJ<0x02, "j">; def JR : JumpFR<0x00, 0x08, "jr", CPURegs>; def JAL : JumpLink<0x03, "jal">; def JALR : JumpLinkReg<0x00, 0x09, "jalr">; +def B : UncondBranch<0x04, "b">; def BEQ : CBranch<0x04, "beq", seteq, CPURegs>; def BNE : CBranch<0x05, "bne", setne, CPURegs>; def BGEZ : CBranchZero<0x01, 1, "bgez", setge, CPURegs>; From gohman at apple.com Mon Dec 5 21:35:58 2011 From: gohman at apple.com (Dan Gohman) Date: Tue, 06 Dec 2011 03:35:58 -0000 Subject: [llvm-commits] [llvm] r145913 - /llvm/trunk/docs/LangRef.html Message-ID: <20111206033558.C5B0A2A6C12C@llvm.org> Author: djg Date: Mon Dec 5 21:35:58 2011 New Revision: 145913 URL: http://llvm.org/viewvc/llvm-project?rev=145913&view=rev Log: Fix a subtle semantic issue with poison values that came up in recent discussions. Poison can't make every value that depends on it act in maximally undefined ways, because the optimizer may still hoist code following the usual rules for undef. Make Poison invoke its full undefined behavior only when it reaches an instruction with externally visible side effects. Modified: llvm/trunk/docs/LangRef.html Modified: llvm/trunk/docs/LangRef.html URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/LangRef.html?rev=145913&r1=145912&r2=145913&view=diff ============================================================================== --- llvm/trunk/docs/LangRef.html (original) +++ llvm/trunk/docs/LangRef.html Mon Dec 5 21:35:58 2011 @@ -2512,10 +2512,9 @@

    Poison values are similar to undef values, however - instead of representing an unspecified bit pattern, they represent the - fact that an instruction or constant expression which cannot evoke side - effects has nevertheless detected a condition which results in undefined - behavior.

    + they also represent the fact that an instruction or constant expression which + cannot evoke side effects has nevertheless detected a condition which results + in undefined behavior.

    There is currently no way of representing a poison value in the IR; they only exist when produced by operations such as @@ -2572,22 +2571,21 @@ -

    Whenever a poison value is generated, all values which depend on it evaluate - to poison. If they have side effects, they evoke their side effects as if each - operand with a poison value were undef. If they have externally-visible side - effects, the behavior is undefined.

    +

    Poison Values have the same behavior as undef values, + with the additional affect that any instruction which has a dependence + on a poison value has undefined behavior.

    Here are some examples:

     entry:
   %poison = sub nuw i32 0, 1           ; Results in a poison value.
-  %still_poison = and i32 %poison, 0   ; Whereas (and i32 undef, 0) would return 0.
+  %still_poison = and i32 %poison, 0   ; 0, but also poison.
   %poison_yet_again = getelementptr i32* @h, i32 %still_poison
-  store i32 0, i32* %poison_yet_again  ; undefined behavior
+  store i32 0, i32* %poison_yet_again  ; memory at @h[0] is poisoned
 
-  store i32 %poison, i32* @g           ; Poison value conceptually stored to memory.
-  %poison2 = load i32* @g              ; Returns a poison value, not just undef.
+  store i32 %poison, i32* @g           ; Poison value stored to memory.
+  %poison2 = load i32* @g              ; Poison value loaded back from memory.
 
   store volatile i32 %poison, i32* @g  ; External observation; undefined behavior.
 
@@ -2626,8 +2624,8 @@
   store volatile i32 0, i32* @g        ; This time, the instruction always depends
                                        ; on the store in %end. Also, it is
                                        ; control-equivalent to %end, so this is
-                                       ; well-defined (again, ignoring earlier
-                                       ; undefined behavior in this example).
+                                       ; well-defined (ignoring earlier undefined
+                                       ; behavior in this example).
    From geek4civic at gmail.com Mon Dec 5 21:56:05 2011 From: geek4civic at gmail.com (NAKAMURA Takumi) Date: Tue, 06 Dec 2011 03:56:05 -0000 Subject: [llvm-commits] [llvm] r145916 - in /llvm/trunk/test/MC: ARM/relax-thumb2-branches.s MachO/relax-thumb2-branches.s Message-ID: <20111206035605.AEADF2A6C12C@llvm.org> Author: chapuni Date: Mon Dec 5 21:56:05 2011 New Revision: 145916 URL: http://llvm.org/viewvc/llvm-project?rev=145916&view=rev Log: test/MC: Move relax-thumb2-branches.s from MC/MachO/ to MC/ARM. MC/MachO assumes x86. Added: llvm/trunk/test/MC/ARM/relax-thumb2-branches.s - copied, changed from r145913, llvm/trunk/test/MC/MachO/relax-thumb2-branches.s Removed: llvm/trunk/test/MC/MachO/relax-thumb2-branches.s Copied: llvm/trunk/test/MC/ARM/relax-thumb2-branches.s (from r145913, llvm/trunk/test/MC/MachO/relax-thumb2-branches.s) URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/relax-thumb2-branches.s?p2=llvm/trunk/test/MC/ARM/relax-thumb2-branches.s&p1=llvm/trunk/test/MC/MachO/relax-thumb2-branches.s&r1=145913&r2=145916&rev=145916&view=diff ============================================================================== (empty) Removed: llvm/trunk/test/MC/MachO/relax-thumb2-branches.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/MachO/relax-thumb2-branches.s?rev=145915&view=auto ============================================================================== --- llvm/trunk/test/MC/MachO/relax-thumb2-branches.s (original) +++ llvm/trunk/test/MC/MachO/relax-thumb2-branches.s (removed) @@ -1,14 +0,0 @@ -@ RUN: llvm-mc -triple=thumbv7-apple-darwin -show-encoding %s -filetype=obj -o - | macho-dump --dump-section-data | FileCheck %s - - ble Lfoo @ wide encoding - - .space 258 -Lfoo: - nop - - ble Lbaz @ narrow encoding - .space 256 -Lbaz: - -@ CHECK: '_section_data', '40f38180 -@ CHECK: 000000bf 7fdd From eli.friedman at gmail.com Mon Dec 5 22:21:16 2011 From: eli.friedman at gmail.com (Eli Friedman) Date: Mon, 5 Dec 2011 20:21:16 -0800 Subject: [llvm-commits] [llvm] r145913 - /llvm/trunk/docs/LangRef.html In-Reply-To: <20111206033558.C5B0A2A6C12C@llvm.org> References: <20111206033558.C5B0A2A6C12C@llvm.org> Message-ID: On Mon, Dec 5, 2011 at 7:35 PM, Dan Gohman wrote: > Author: djg > Date: Mon Dec ?5 21:35:58 2011 > New Revision: 145913 > > URL: http://llvm.org/viewvc/llvm-project?rev=145913&view=rev > Log: > Fix a subtle semantic issue with poison values that came up in > recent discussions. Poison can't make every value that depends on > it act in maximally undefined ways, because the optimizer may still > hoist code following the usual rules for undef. Make Poison invoke > its full undefined behavior only when it reaches an instruction with > externally visible side effects. > > Modified: > ? ?llvm/trunk/docs/LangRef.html > > Modified: llvm/trunk/docs/LangRef.html > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/LangRef.html?rev=145913&r1=145912&r2=145913&view=diff > ============================================================================== > --- llvm/trunk/docs/LangRef.html (original) > +++ llvm/trunk/docs/LangRef.html Mon Dec ?5 21:35:58 2011 > @@ -2512,10 +2512,9 @@ > ?
    > > ?

    Poison values are similar to undef values, however > - ? instead of representing an unspecified bit pattern, they represent the > - ? fact that an instruction or constant expression which cannot evoke side > - ? effects has nevertheless detected a condition which results in undefined > - ? behavior.

    > + ? they also represent the fact that an instruction or constant expression which > + ? cannot evoke side effects has nevertheless detected a condition which results > + ? in undefined behavior.

    > > ?

    There is currently no way of representing a poison value in the IR; they > ? ?only exist when produced by operations such as > @@ -2572,22 +2571,21 @@ > > ? > > -

    Whenever a poison value is generated, all values which depend on it evaluate > - ? to poison. If they have side effects, they evoke their side effects as if each > - ? operand with a poison value were undef. If they have externally-visible side > - ? effects, the behavior is undefined.

    > +

    Poison Values have the same behavior as undef values, > + ? with the additional affect that any instruction which has a dependence > + ? on a poison value has undefined behavior.

    > > ?

    Here are some examples:

    > > ?
    > ?entry:
> ? %poison = sub nuw i32 0, 1 ? ? ? ? ? ; Results in a poison value.
> - ?%still_poison = and i32 %poison, 0 ? ; Whereas (and i32 undef, 0) would return 0.
> + ?%still_poison = and i32 %poison, 0 ? ; 0, but also poison.
> ? %poison_yet_again = getelementptr i32* @h, i32 %still_poison
> - ?store i32 0, i32* %poison_yet_again ?; undefined behavior
> + ?store i32 0, i32* %poison_yet_again ?; memory at @h[0] is poisoned

This change can't be right... storing to a poisoned address has to be
undefined behavior in any sane model.

-Eli

> - ?store i32 %poison, i32* @g ? ? ? ? ? ; Poison value conceptually stored to memory.
> - ?%poison2 = load i32* @g ? ? ? ? ? ? ?; Returns a poison value, not just undef.
> + ?store i32 %poison, i32* @g ? ? ? ? ? ; Poison value stored to memory.
> + ?%poison2 = load i32* @g ? ? ? ? ? ? ?; Poison value loaded back from memory.
>
> ? store volatile i32 %poison, i32* @g ?; External observation; undefined behavior.
>
> @@ -2626,8 +2624,8 @@
> ? store volatile i32 0, i32* @g ? ? ? ?; This time, the instruction always depends
> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?; on the store in %end. Also, it is
> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?; control-equivalent to %end, so this is
> - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ; well-defined (again, ignoring earlier
> - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ; undefined behavior in this example).
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ; well-defined (ignoring earlier undefined
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ; behavior in this example).
> ?
    > > ?
    > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From grosbach at apple.com Mon Dec 5 22:49:29 2011 From: grosbach at apple.com (Jim Grosbach) Date: Tue, 06 Dec 2011 04:49:29 -0000 Subject: [llvm-commits] [llvm] r145919 - in /llvm/trunk: lib/Target/ARM/AsmParser/ARMAsmParser.cpp test/MC/ARM/basic-thumb2-instructions.s Message-ID: <20111206044929.A7B2B2A6C12C@llvm.org> Author: grosbach Date: Mon Dec 5 22:49:29 2011 New Revision: 145919 URL: http://llvm.org/viewvc/llvm-project?rev=145919&view=rev Log: Thumb2 encoding choice correction for PLD. Using encoding T1 for offset of #0 and encoding T2 for #-0. rdar://10532413 Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp?rev=145919&r1=145918&r2=145919&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp (original) +++ llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Mon Dec 5 22:49:29 2011 @@ -916,9 +916,9 @@ if (!isMemory() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0) return false; // Immediate offset in range [-255, -1]. - if (!Memory.OffsetImm) return true; + if (!Memory.OffsetImm) return false; int64_t Val = Memory.OffsetImm->getValue(); - return Val > -256 && Val < 0; + return (Val == INT32_MIN) || (Val > -256 && Val < 0); } bool isMemUImm12Offset() const { if (!isMemory() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0) Modified: llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s?rev=145919&r1=145918&r2=145919&view=diff ============================================================================== --- llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s (original) +++ llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s Mon Dec 5 22:49:29 2011 @@ -1371,12 +1371,16 @@ pld [r6, #33] pld [r6, #257] pld [r7, #257] + pld [r1, #0] + pld [r1, #-0] @ CHECK: pld [r5, #-4] @ encoding: [0x15,0xf8,0x04,0xfc] @ CHECK: pld [r6, #32] @ encoding: [0x96,0xf8,0x20,0xf0] @ CHECK: pld [r6, #33] @ encoding: [0x96,0xf8,0x21,0xf0] @ CHECK: pld [r6, #257] @ encoding: [0x96,0xf8,0x01,0xf1] @ CHECK: pld [r7, #257] @ encoding: [0x97,0xf8,0x01,0xf1] +@ CHECK: pld [r1] @ encoding: [0x91,0xf8,0x00,0xf0] +@ CHECK: pld [r1, #-0] @ encoding: [0x11,0xf8,0x00,0xfc] @------------------------------------------------------------------------------ From craig.topper at gmail.com Mon Dec 5 22:59:07 2011 From: craig.topper at gmail.com (Craig Topper) Date: Tue, 06 Dec 2011 04:59:07 -0000 Subject: [llvm-commits] [llvm] r145921 - in /llvm/trunk: lib/Target/X86/X86ISelLowering.cpp test/CodeGen/X86/avx-vperm2f128.ll test/CodeGen/X86/avx2-vperm2i128.ll Message-ID: <20111206045907.9AC7D2A6C12C@llvm.org> Author: ctopper Date: Mon Dec 5 22:59:07 2011 New Revision: 145921 URL: http://llvm.org/viewvc/llvm-project?rev=145921&view=rev Log: Merge isSHUFPMask and isCommutedSHUFPMask into single function that can do both. Do the same for the 256-bit version. Use loops to reduce size of isVSHUFPYMask. Fix test cases that were incorrectly passing due to isCommutedSHUFPMask not checking for the vector being 128-bit. This caused some 256-bit shuffles to be incorrectly commuted. Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp llvm/trunk/test/CodeGen/X86/avx-vperm2f128.ll llvm/trunk/test/CodeGen/X86/avx2-vperm2i128.ll Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=145921&r1=145920&r2=145921&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original) +++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Mon Dec 5 22:59:07 2011 @@ -3251,7 +3251,7 @@ /// specifies a shuffle of elements that is suitable for input to 256-bit /// VSHUFPSY. static bool isVSHUFPYMask(const SmallVectorImpl &Mask, EVT VT, - bool HasAVX) { + bool HasAVX, bool Commuted = false) { int NumElems = VT.getVectorNumElements(); if (!HasAVX || VT.getSizeInBits() != 256) @@ -3279,114 +3279,27 @@ // // DST => Y3..Y2, X3..X2, Y1..Y0, X1..X0 // - int QuarterSize = NumElems/4; - int HalfSize = QuarterSize*2; - for (int i = 0; i < QuarterSize; ++i) - if (!isUndefOrInRange(Mask[i], 0, HalfSize)) - return false; - for (int i = QuarterSize; i < QuarterSize*2; ++i) - if (!isUndefOrInRange(Mask[i], NumElems, NumElems+HalfSize)) - return false; - - // For VSHUFPSY, the mask of the second half must be the same as the first - // but with the appropriate offsets. This works in the same way as - // VPERMILPS works with masks. - for (int i = QuarterSize*2; i < QuarterSize*3; ++i) { - if (!isUndefOrInRange(Mask[i], HalfSize, NumElems)) - return false; - if (NumElems == 4) - continue; - // VSHUFPSY handling - int FstHalfIdx = i-HalfSize; - if (Mask[FstHalfIdx] < 0) - continue; - if (!isUndefOrEqual(Mask[i], Mask[FstHalfIdx]+HalfSize)) - return false; - } - for (int i = QuarterSize*3; i < NumElems; ++i) { - if (!isUndefOrInRange(Mask[i], NumElems+HalfSize, NumElems*2)) - return false; - int FstHalfIdx = i-HalfSize; - if (NumElems == 4) - continue; - // VSHUFPSY handling - if (Mask[FstHalfIdx] < 0) - continue; - if (!isUndefOrEqual(Mask[i], Mask[FstHalfIdx]+HalfSize)) - return false; - } - - return true; -} - -/// isCommutedVSHUFP() - Returns true if the shuffle mask is exactly -/// the reverse of what x86 shuffles want. x86 shuffles requires the lower -/// half elements to come from vector 1 (which would equal the dest.) and -/// the upper half to come from vector 2. -static bool isCommutedVSHUFPYMask(const SmallVectorImpl &Mask, EVT VT, - bool HasAVX) { - int NumElems = VT.getVectorNumElements(); - - if (!HasAVX || VT.getSizeInBits() != 256) - return false; - - if (NumElems != 4 && NumElems != 8) - return false; - - // VSHUFPSY divides the resulting vector into 4 chunks. - // The sources are also splitted into 4 chunks, and each destination - // chunk must come from a different source chunk. - // - // SRC1 => X7 X6 X5 X4 X3 X2 X1 X0 - // SRC2 => Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y9 - // - // DST => Y7..Y4, Y7..Y4, X7..X4, X7..X4, - // Y3..Y0, Y3..Y0, X3..X0, X3..X0 - // - // VSHUFPDY divides the resulting vector into 4 chunks. - // The sources are also splitted into 4 chunks, and each destination - // chunk must come from a different source chunk. - // - // SRC1 => X3 X2 X1 X0 - // SRC2 => Y3 Y2 Y1 Y0 - // - // DST => Y3..Y2, X3..X2, Y1..Y0, X1..X0 - // - int QuarterSize = NumElems/4; - int HalfSize = QuarterSize*2; - for (int i = 0; i < QuarterSize; ++i) - if (!isUndefOrInRange(Mask[i], NumElems, NumElems+HalfSize)) - return false; - for (int i = QuarterSize; i < QuarterSize*2; ++i) - if (!isUndefOrInRange(Mask[i], 0, HalfSize)) - return false; - - // For VSHUFPSY, the mask of the second half must be the same as the first - // but with the appropriate offsets. This works in the same way as - // VPERMILPS works with masks. - for (int i = QuarterSize*2; i < QuarterSize*3; ++i) { - if (!isUndefOrInRange(Mask[i], NumElems+HalfSize, NumElems*2)) - return false; - if (NumElems == 4) - continue; - // VSHUFPSY handling - int FstHalfIdx = i-HalfSize; - if (Mask[FstHalfIdx] < 0) - continue; - if (!isUndefOrEqual(Mask[i], Mask[FstHalfIdx]+HalfSize)) - return false; - } - for (int i = QuarterSize*3; i < NumElems; ++i) { - if (!isUndefOrInRange(Mask[i], HalfSize, NumElems)) - return false; - if (NumElems == 4) - continue; - // VSHUFPSY handling - int FstHalfIdx = i-HalfSize; - if (Mask[FstHalfIdx] < 0) - continue; - if (!isUndefOrEqual(Mask[i], Mask[FstHalfIdx]+HalfSize)) - return false; + unsigned QuarterSize = NumElems/4; + unsigned HalfSize = QuarterSize*2; + for (unsigned l = 0; l != 2; ++l) { + unsigned LaneStart = l*HalfSize; + for (unsigned s = 0; s != 2; ++s) { + unsigned QuarterStart = s*QuarterSize; + unsigned Src = (Commuted) ? (1-s) : s; + unsigned SrcStart = Src*NumElems + LaneStart; + for (unsigned i = 0; i != QuarterSize; ++i) { + int Idx = Mask[i+QuarterStart+LaneStart]; + if (!isUndefOrInRange(Idx, SrcStart, SrcStart+HalfSize)) + return false; + // For VSHUFPSY, the mask of the second half must be the same as the first + // but with the appropriate offsets. This works in the same way as + // VPERMILPS works with masks. + if (NumElems == 4 || l == 0 || Mask[i+QuarterStart] < 0) + continue; + if (!isUndefOrEqual(Idx, Mask[i+QuarterStart]+HalfSize)) + return false; + } + } } return true; @@ -3436,9 +3349,11 @@ /// isSHUFPMask - Return true if the specified VECTOR_SHUFFLE operand /// specifies a shuffle of elements that is suitable for input to 128-bit -/// SHUFPS and SHUFPD. -static bool isSHUFPMask(const SmallVectorImpl &Mask, EVT VT) { - int NumElems = VT.getVectorNumElements(); +/// SHUFPS and SHUFPD. If Commuted is true, then it checks for sources to be +/// reverse of what x86 shuffles want. +static bool isSHUFPMask(const SmallVectorImpl &Mask, EVT VT, + bool Commuted = false) { + unsigned NumElems = VT.getVectorNumElements(); if (VT.getSizeInBits() != 128) return false; @@ -3446,12 +3361,14 @@ if (NumElems != 2 && NumElems != 4) return false; - int Half = NumElems / 2; - for (int i = 0; i < Half; ++i) - if (!isUndefOrInRange(Mask[i], 0, NumElems)) - return false; - for (int i = Half; i < NumElems; ++i) - if (!isUndefOrInRange(Mask[i], NumElems, NumElems*2)) + unsigned Half = NumElems / 2; + unsigned SrcStart = Commuted ? NumElems : 0; + for (unsigned i = 0; i != Half; ++i) + if (!isUndefOrInRange(Mask[i], SrcStart, SrcStart+NumElems)) + return false; + SrcStart = Commuted ? 0 : NumElems; + for (unsigned i = Half; i != NumElems; ++i) + if (!isUndefOrInRange(Mask[i], SrcStart, SrcStart+NumElems)) return false; return true; @@ -3463,26 +3380,6 @@ return ::isSHUFPMask(M, N->getValueType(0)); } -/// isCommutedSHUFPMask - Returns true if the shuffle mask is exactly -/// the reverse of what x86 shuffles want. x86 shuffles requires the lower -/// half elements to come from vector 1 (which would equal the dest.) and -/// the upper half to come from vector 2. -static bool isCommutedSHUFPMask(const SmallVectorImpl &Mask, EVT VT) { - int NumElems = VT.getVectorNumElements(); - - if (NumElems != 2 && NumElems != 4) - return false; - - int Half = NumElems / 2; - for (int i = 0; i < Half; ++i) - if (!isUndefOrInRange(Mask[i], NumElems, NumElems*2)) - return false; - for (int i = Half; i < NumElems; ++i) - if (!isUndefOrInRange(Mask[i], 0, NumElems)) - return false; - return true; -} - /// isMOVHLPSMask - Return true if the specified VECTOR_SHUFFLE operand /// specifies a shuffle of elements that is suitable for input to MOVHLPS. bool X86::isMOVHLPSMask(ShuffleVectorSDNode *N) { @@ -6780,8 +6677,8 @@ } // Normalize the node to match x86 shuffle ops if needed - if (!V2IsUndef && (isCommutedSHUFPMask(M, VT) || - isCommutedVSHUFPYMask(M, VT, HasAVX))) + if (!V2IsUndef && (isSHUFPMask(M, VT, /* Commuted */ true) || + isVSHUFPYMask(M, VT, HasAVX, /* Commuted */ true))) return CommuteVectorShuffle(SVOp, DAG); // The checks below are all present in isShuffleMaskLegal, but they are @@ -11272,7 +11169,7 @@ return (isMOVLMask(Mask, VT) || isCommutedMOVLMask(Mask, VT, true) || isSHUFPMask(Mask, VT) || - isCommutedSHUFPMask(Mask, VT)); + isSHUFPMask(Mask, VT, /* Commuted */ true)); } return false; } Modified: llvm/trunk/test/CodeGen/X86/avx-vperm2f128.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx-vperm2f128.ll?rev=145921&r1=145920&r2=145921&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/X86/avx-vperm2f128.ll (original) +++ llvm/trunk/test/CodeGen/X86/avx-vperm2f128.ll Mon Dec 5 22:59:07 2011 @@ -1,5 +1,6 @@ ; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=corei7-avx -mattr=+avx | FileCheck %s +; CHECK: _A ; CHECK: vperm2f128 $1 define <8 x float> @A(<8 x float> %a, <8 x float> %b) nounwind uwtable readnone ssp { entry: @@ -7,6 +8,7 @@ ret <8 x float> %shuffle } +; CHECK: _B ; CHECK: vperm2f128 $48 define <8 x float> @B(<8 x float> %a, <8 x float> %b) nounwind uwtable readnone ssp { entry: @@ -14,6 +16,7 @@ ret <8 x float> %shuffle } +; CHECK: _C ; CHECK: vperm2f128 $0 define <8 x float> @C(<8 x float> %a, <8 x float> %b) nounwind uwtable readnone ssp { entry: @@ -21,6 +24,7 @@ ret <8 x float> %shuffle } +; CHECK: _D ; CHECK: vperm2f128 $17 define <8 x float> @D(<8 x float> %a, <8 x float> %b) nounwind uwtable readnone ssp { entry: @@ -28,6 +32,7 @@ ret <8 x float> %shuffle } +; CHECK: _E ; CHECK: vperm2f128 $17 define <32 x i8> @E(<32 x i8> %a, <32 x i8> %b) nounwind uwtable readnone ssp { entry: @@ -35,7 +40,8 @@ ret <32 x i8> %shuffle } -; CHECK: vperm2f128 $33 +; CHECK: _E2 +; CHECK: vperm2f128 $3 define <4 x i64> @E2(<4 x i64> %a, <4 x i64> %b) nounwind uwtable readnone ssp { entry: %shuffle = shufflevector <4 x i64> %a, <4 x i64> %b, <4 x i32> @@ -44,6 +50,7 @@ ;;;; Cases with undef indicies mixed in the mask +; CHECK: _F ; CHECK: vperm2f128 $33 define <8 x float> @F(<8 x float> %a, <8 x float> %b) nounwind uwtable readnone ssp { entry: Modified: llvm/trunk/test/CodeGen/X86/avx2-vperm2i128.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx2-vperm2i128.ll?rev=145921&r1=145920&r2=145921&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/X86/avx2-vperm2i128.ll (original) +++ llvm/trunk/test/CodeGen/X86/avx2-vperm2i128.ll Mon Dec 5 22:59:07 2011 @@ -9,7 +9,7 @@ ret <32 x i8> %shuffle } -; CHECK: vperm2i128 $33 +; CHECK: vperm2i128 $3 define <4 x i64> @E2(<4 x i64> %a, <4 x i64> %b) nounwind uwtable readnone ssp { entry: ; add forces execution domain From grosbach at apple.com Mon Dec 5 23:03:45 2011 From: grosbach at apple.com (Jim Grosbach) Date: Tue, 06 Dec 2011 05:03:45 -0000 Subject: [llvm-commits] [llvm] r145922 - in /llvm/trunk: lib/Target/ARM/ARMInstrThumb2.td test/MC/ARM/basic-thumb2-instructions.s Message-ID: <20111206050345.EF3542A6C12C@llvm.org> Author: grosbach Date: Mon Dec 5 23:03:45 2011 New Revision: 145922 URL: http://llvm.org/viewvc/llvm-project?rev=145922&view=rev Log: Thumb2: MUL two-operand form encoding operand order fix. Fix the alias to encode 'mul r5, r6' as if it were 'mul r5, r6, r5' so we match gas. rdar://10532439 Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td?rev=145922&r1=145921&r2=145922&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td Mon Dec 5 23:03:45 2011 @@ -4088,4 +4088,4 @@ // Wide 'mul' encoding can be specified with only two operands. def : t2InstAlias<"mul${p} $Rn, $Rm", - (t2MUL rGPR:$Rn, rGPR:$Rn, rGPR:$Rm, pred:$p)>; + (t2MUL rGPR:$Rn, rGPR:$Rm, rGPR:$Rn, pred:$p)>; Modified: llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s?rev=145922&r1=145921&r2=145922&view=diff ============================================================================== --- llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s (original) +++ llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s Mon Dec 5 23:03:45 2011 @@ -1236,7 +1236,7 @@ muleq r3, r4, r5 it le mulle r4, r4, r8 - mul r6, r5 + mul r5, r6 @ CHECK: muls r3, r4, r3 @ encoding: [0x63,0x43] @ CHECK: mul r3, r4, r3 @ encoding: [0x04,0xfb,0x03,0xf3] @@ -1245,7 +1245,7 @@ @ CHECK: muleq r3, r4, r5 @ encoding: [0x04,0xfb,0x05,0xf3] @ CHECK: it le @ encoding: [0xd8,0xbf] @ CHECK: mulle r4, r4, r8 @ encoding: [0x04,0xfb,0x08,0xf4] -@ CHECK: mul r6, r6, r5 @ encoding: [0x06,0xfb,0x05,0xf6] +@ CHECK: mul r5, r6, r5 @ encoding: [0x06,0xfb,0x05,0xf5] @------------------------------------------------------------------------------ From grosbach at apple.com Mon Dec 5 23:14:57 2011 From: grosbach at apple.com (Jim Grosbach) Date: Mon, 05 Dec 2011 21:14:57 -0800 Subject: [llvm-commits] [llvm] r145916 - in /llvm/trunk/test/MC: ARM/relax-thumb2-branches.s MachO/relax-thumb2-branches.s In-Reply-To: <20111206035605.AEADF2A6C12C@llvm.org> References: <20111206035605.AEADF2A6C12C@llvm.org> Message-ID: MC/MachO does not assume X86. There are other tests for ARM there as well. Tests which produce an object file, which this one does, belong in the MachO directory, not the MC/ARM directory. That said, I agree there's some oddness in the directory structure. Having target sub-dirs in the MachO directory isn't a bad idea, for example. For the time being, please revert this change. The test was in the correct place. -Jim On Dec 5, 2011, at 7:56 PM, NAKAMURA Takumi wrote: > Author: chapuni > Date: Mon Dec 5 21:56:05 2011 > New Revision: 145916 > > URL: http://llvm.org/viewvc/llvm-project?rev=145916&view=rev > Log: > test/MC: Move relax-thumb2-branches.s from MC/MachO/ to MC/ARM. > > MC/MachO assumes x86. > > Added: > llvm/trunk/test/MC/ARM/relax-thumb2-branches.s > - copied, changed from r145913, llvm/trunk/test/MC/MachO/relax-thumb2-branches.s > Removed: > llvm/trunk/test/MC/MachO/relax-thumb2-branches.s > > Copied: llvm/trunk/test/MC/ARM/relax-thumb2-branches.s (from r145913, llvm/trunk/test/MC/MachO/relax-thumb2-branches.s) > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/relax-thumb2-branches.s?p2=llvm/trunk/test/MC/ARM/relax-thumb2-branches.s&p1=llvm/trunk/test/MC/MachO/relax-thumb2-branches.s&r1=145913&r2=145916&rev=145916&view=diff > ============================================================================== > (empty) > > Removed: llvm/trunk/test/MC/MachO/relax-thumb2-branches.s > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/MachO/relax-thumb2-branches.s?rev=145915&view=auto > ============================================================================== > --- llvm/trunk/test/MC/MachO/relax-thumb2-branches.s (original) > +++ llvm/trunk/test/MC/MachO/relax-thumb2-branches.s (removed) > @@ -1,14 +0,0 @@ > -@ RUN: llvm-mc -triple=thumbv7-apple-darwin -show-encoding %s -filetype=obj -o - | macho-dump --dump-section-data | FileCheck %s > - > - ble Lfoo @ wide encoding > - > - .space 258 > -Lfoo: > - nop > - > - ble Lbaz @ narrow encoding > - .space 256 > -Lbaz: > - > -@ CHECK: '_section_data', '40f38180 > -@ CHECK: 000000bf 7fdd > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From grosbach at apple.com Mon Dec 5 23:18:44 2011 From: grosbach at apple.com (Jim Grosbach) Date: Mon, 05 Dec 2011 21:18:44 -0800 Subject: [llvm-commits] [llvm] r145894 - in /llvm/trunk/lib/Target: Mips/MCTargetDesc/MipsAsmBackend.cpp PowerPC/MCTargetDesc/PPCAsmBackend.cpp In-Reply-To: References: <20111206014832.F01782A6C12C@llvm.org> Message-ID: <827FA739-169B-4E6B-BC2A-0AAF48D8D3CF@apple.com> On Dec 5, 2011, at 6:06 PM, David Blaikie wrote: > On Tue, Dec 6, 2011 at 1:48 AM, NAKAMURA Takumi wrote: >> Author: chapuni >> Date: Mon Dec 5 19:48:32 2011 >> New Revision: 145894 >> >> URL: http://llvm.org/viewvc/llvm-project?rev=145894&view=rev >> Log: >> MipsAsmBackend.cpp, PPCAsmBackend.cpp: Fix -Asserts build to appease msvc. >> >> Modified: >> llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsAsmBackend.cpp >> llvm/trunk/lib/Target/PowerPC/MCTargetDesc/PPCAsmBackend.cpp >> >> Modified: llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsAsmBackend.cpp >> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsAsmBackend.cpp?rev=145894&r1=145893&r2=145894&view=diff >> ============================================================================== >> --- llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsAsmBackend.cpp (original) >> +++ llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsAsmBackend.cpp Mon Dec 5 19:48:32 2011 >> @@ -181,6 +181,7 @@ >> const MCAsmLayout &Layout) const { >> // FIXME. >> assert(0 && "RelaxInstruction() unimplemented"); >> + return false; > > Does llvm_unreachable also (as an alternative, not in addition to) silence MSVC? It probably would, but I believe the change to add a 'return false' is the better one in this instance. These functions are reachable in the sense that they are target hooks for an MC feature (branch relaxation). That feature is not used by these targets, however, so there's an assert in the hooks so if the code somehow gets there, a contract is being violated. In a release build, they just return "nothing to do here, please move along," instead, which is reasonable non-crashing behavior. Sorry for the MSVC breakage, btw. Thank you for the fix! -Jim > >> } >> >> /// RelaxInstruction - Relax the instruction in the given fragment >> >> Modified: llvm/trunk/lib/Target/PowerPC/MCTargetDesc/PPCAsmBackend.cpp >> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/MCTargetDesc/PPCAsmBackend.cpp?rev=145894&r1=145893&r2=145894&view=diff >> ============================================================================== >> --- llvm/trunk/lib/Target/PowerPC/MCTargetDesc/PPCAsmBackend.cpp (original) >> +++ llvm/trunk/lib/Target/PowerPC/MCTargetDesc/PPCAsmBackend.cpp Mon Dec 5 19:48:32 2011 >> @@ -100,6 +100,7 @@ >> const MCAsmLayout &Layout) const { >> // FIXME. >> assert(0 && "RelaxInstruction() unimplemented"); >> + return false; >> } >> >> >> >> >> _______________________________________________ >> llvm-commits mailing list >> llvm-commits at cs.uiuc.edu >> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From grosbach at apple.com Mon Dec 5 23:28:01 2011 From: grosbach at apple.com (Jim Grosbach) Date: Tue, 06 Dec 2011 05:28:01 -0000 Subject: [llvm-commits] [llvm] r145923 - in /llvm/trunk: lib/Target/ARM/ARMInstrInfo.td test/MC/ARM/basic-arm-instructions.s Message-ID: <20111206052801.197B82A6C12C@llvm.org> Author: grosbach Date: Mon Dec 5 23:28:00 2011 New Revision: 145923 URL: http://llvm.org/viewvc/llvm-project?rev=145923&view=rev Log: ARM mode 'mul' operand ordering tweak. Same as r145922, just for ARM mode. Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td llvm/trunk/test/MC/ARM/basic-arm-instructions.s Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.td?rev=145923&r1=145922&r2=145923&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrInfo.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Mon Dec 5 23:28:00 2011 @@ -5067,4 +5067,4 @@ // 'mul' instruction can be specified with only two operands. def : ARMInstAlias<"mul${s}${p} $Rn, $Rm", - (MUL rGPR:$Rn, rGPR:$Rn, rGPR:$Rm, pred:$p, cc_out:$s)>; + (MUL rGPR:$Rn, rGPR:$Rm, rGPR:$Rn, pred:$p, cc_out:$s)>; Modified: llvm/trunk/test/MC/ARM/basic-arm-instructions.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/basic-arm-instructions.s?rev=145923&r1=145922&r2=145923&view=diff ============================================================================== --- llvm/trunk/test/MC/ARM/basic-arm-instructions.s (original) +++ llvm/trunk/test/MC/ARM/basic-arm-instructions.s Mon Dec 5 23:28:00 2011 @@ -1013,7 +1013,6 @@ @ CHECK: muls r5, r6, r7 @ encoding: [0x96,0x07,0x15,0xe0] @ CHECK: mulgt r5, r6, r7 @ encoding: [0x96,0x07,0x05,0xc0] @ CHECK: mulsle r5, r6, r7 @ encoding: [0x96,0x07,0x15,0xd0] -@ CHECK: mul r11, r11, r5 @ encoding: [0x9b,0x05,0x0b,0xe0] @------------------------------------------------------------------------------ From craig.topper at gmail.com Mon Dec 5 23:31:16 2011 From: craig.topper at gmail.com (Craig Topper) Date: Tue, 06 Dec 2011 05:31:16 -0000 Subject: [llvm-commits] [llvm] r145924 - in /llvm/trunk/lib/Target/X86: InstPrinter/X86InstComments.cpp Utils/X86ShuffleDecode.cpp Utils/X86ShuffleDecode.h X86ISelLowering.cpp Message-ID: <20111206053116.713472A6C12C@llvm.org> Author: ctopper Date: Mon Dec 5 23:31:16 2011 New Revision: 145924 URL: http://llvm.org/viewvc/llvm-project?rev=145924&view=rev Log: Clean up some of the shuffle decoding code for UNPCK instructions. Add instruction commenting for AVX/AVX2 forms for integer UNPCKs. Modified: llvm/trunk/lib/Target/X86/InstPrinter/X86InstComments.cpp llvm/trunk/lib/Target/X86/Utils/X86ShuffleDecode.cpp llvm/trunk/lib/Target/X86/Utils/X86ShuffleDecode.h llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Modified: llvm/trunk/lib/Target/X86/InstPrinter/X86InstComments.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/InstPrinter/X86InstComments.cpp?rev=145924&r1=145923&r2=145924&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/InstPrinter/X86InstComments.cpp (original) +++ llvm/trunk/lib/Target/X86/InstPrinter/X86InstComments.cpp Mon Dec 5 23:31:16 2011 @@ -106,28 +106,92 @@ // FALL THROUGH. case X86::PUNPCKHBWrm: Src1Name = getRegName(MI->getOperand(0).getReg()); - DecodePUNPCKHMask(16, ShuffleMask); + DecodeUNPCKHMask(MVT::v16i8, ShuffleMask); + break; + case X86::VPUNPCKHBWrr: + Src2Name = getRegName(MI->getOperand(2).getReg()); + // FALL THROUGH. + case X86::VPUNPCKHBWrm: + Src1Name = getRegName(MI->getOperand(1).getReg()); + DestName = getRegName(MI->getOperand(0).getReg()); + DecodeUNPCKHMask(MVT::v16i8, ShuffleMask); + break; + case X86::VPUNPCKHBWYrr: + Src2Name = getRegName(MI->getOperand(2).getReg()); + // FALL THROUGH. + case X86::VPUNPCKHBWYrm: + Src1Name = getRegName(MI->getOperand(1).getReg()); + DestName = getRegName(MI->getOperand(0).getReg()); + DecodeUNPCKHMask(MVT::v32i8, ShuffleMask); break; case X86::PUNPCKHWDrr: Src2Name = getRegName(MI->getOperand(2).getReg()); // FALL THROUGH. case X86::PUNPCKHWDrm: Src1Name = getRegName(MI->getOperand(0).getReg()); - DecodePUNPCKHMask(8, ShuffleMask); + DecodeUNPCKHMask(MVT::v8i16, ShuffleMask); + break; + case X86::VPUNPCKHWDrr: + Src2Name = getRegName(MI->getOperand(2).getReg()); + // FALL THROUGH. + case X86::VPUNPCKHWDrm: + Src1Name = getRegName(MI->getOperand(1).getReg()); + DestName = getRegName(MI->getOperand(0).getReg()); + DecodeUNPCKHMask(MVT::v8i16, ShuffleMask); + break; + case X86::VPUNPCKHWDYrr: + Src2Name = getRegName(MI->getOperand(2).getReg()); + // FALL THROUGH. + case X86::VPUNPCKHWDYrm: + Src1Name = getRegName(MI->getOperand(1).getReg()); + DestName = getRegName(MI->getOperand(0).getReg()); + DecodeUNPCKHMask(MVT::v16i16, ShuffleMask); break; case X86::PUNPCKHDQrr: Src2Name = getRegName(MI->getOperand(2).getReg()); // FALL THROUGH. case X86::PUNPCKHDQrm: Src1Name = getRegName(MI->getOperand(0).getReg()); - DecodePUNPCKHMask(4, ShuffleMask); + DecodeUNPCKHMask(MVT::v4i32, ShuffleMask); + break; + case X86::VPUNPCKHDQrr: + Src2Name = getRegName(MI->getOperand(2).getReg()); + // FALL THROUGH. + case X86::VPUNPCKHDQrm: + Src1Name = getRegName(MI->getOperand(1).getReg()); + DestName = getRegName(MI->getOperand(0).getReg()); + DecodeUNPCKHMask(MVT::v4i32, ShuffleMask); + break; + case X86::VPUNPCKHDQYrr: + Src2Name = getRegName(MI->getOperand(2).getReg()); + // FALL THROUGH. + case X86::VPUNPCKHDQYrm: + Src1Name = getRegName(MI->getOperand(1).getReg()); + DestName = getRegName(MI->getOperand(0).getReg()); + DecodeUNPCKHMask(MVT::v8i32, ShuffleMask); break; case X86::PUNPCKHQDQrr: Src2Name = getRegName(MI->getOperand(2).getReg()); // FALL THROUGH. case X86::PUNPCKHQDQrm: Src1Name = getRegName(MI->getOperand(0).getReg()); - DecodePUNPCKHMask(2, ShuffleMask); + DecodeUNPCKHMask(MVT::v2i64, ShuffleMask); + break; + case X86::VPUNPCKHQDQrr: + Src2Name = getRegName(MI->getOperand(2).getReg()); + // FALL THROUGH. + case X86::VPUNPCKHQDQrm: + Src1Name = getRegName(MI->getOperand(1).getReg()); + DestName = getRegName(MI->getOperand(0).getReg()); + DecodeUNPCKHMask(MVT::v2i64, ShuffleMask); + break; + case X86::VPUNPCKHQDQYrr: + Src2Name = getRegName(MI->getOperand(2).getReg()); + // FALL THROUGH. + case X86::VPUNPCKHQDQYrm: + Src1Name = getRegName(MI->getOperand(1).getReg()); + DestName = getRegName(MI->getOperand(0).getReg()); + DecodeUNPCKHMask(MVT::v4i64, ShuffleMask); break; case X86::PUNPCKLBWrr: @@ -135,28 +199,92 @@ // FALL THROUGH. case X86::PUNPCKLBWrm: Src1Name = getRegName(MI->getOperand(0).getReg()); - DecodePUNPCKLBWMask(16, ShuffleMask); + DecodeUNPCKLMask(MVT::v16i8, ShuffleMask); + break; + case X86::VPUNPCKLBWrr: + Src2Name = getRegName(MI->getOperand(2).getReg()); + // FALL THROUGH. + case X86::VPUNPCKLBWrm: + Src1Name = getRegName(MI->getOperand(1).getReg()); + DestName = getRegName(MI->getOperand(0).getReg()); + DecodeUNPCKLMask(MVT::v16i8, ShuffleMask); + break; + case X86::VPUNPCKLBWYrr: + Src2Name = getRegName(MI->getOperand(2).getReg()); + // FALL THROUGH. + case X86::VPUNPCKLBWYrm: + Src1Name = getRegName(MI->getOperand(1).getReg()); + DestName = getRegName(MI->getOperand(0).getReg()); + DecodeUNPCKLMask(MVT::v32i8, ShuffleMask); break; case X86::PUNPCKLWDrr: Src2Name = getRegName(MI->getOperand(2).getReg()); // FALL THROUGH. case X86::PUNPCKLWDrm: Src1Name = getRegName(MI->getOperand(0).getReg()); - DecodePUNPCKLWDMask(8, ShuffleMask); + DecodeUNPCKLMask(MVT::v8i16, ShuffleMask); + break; + case X86::VPUNPCKLWDrr: + Src2Name = getRegName(MI->getOperand(2).getReg()); + // FALL THROUGH. + case X86::VPUNPCKLWDrm: + Src1Name = getRegName(MI->getOperand(1).getReg()); + DestName = getRegName(MI->getOperand(0).getReg()); + DecodeUNPCKLMask(MVT::v8i16, ShuffleMask); + break; + case X86::VPUNPCKLWDYrr: + Src2Name = getRegName(MI->getOperand(2).getReg()); + // FALL THROUGH. + case X86::VPUNPCKLWDYrm: + Src1Name = getRegName(MI->getOperand(1).getReg()); + DestName = getRegName(MI->getOperand(0).getReg()); + DecodeUNPCKLMask(MVT::v16i16, ShuffleMask); break; case X86::PUNPCKLDQrr: Src2Name = getRegName(MI->getOperand(2).getReg()); // FALL THROUGH. case X86::PUNPCKLDQrm: Src1Name = getRegName(MI->getOperand(0).getReg()); - DecodePUNPCKLDQMask(4, ShuffleMask); + DecodeUNPCKLMask(MVT::v4i32, ShuffleMask); + break; + case X86::VPUNPCKLDQrr: + Src2Name = getRegName(MI->getOperand(2).getReg()); + // FALL THROUGH. + case X86::VPUNPCKLDQrm: + Src1Name = getRegName(MI->getOperand(1).getReg()); + DestName = getRegName(MI->getOperand(0).getReg()); + DecodeUNPCKLMask(MVT::v4i32, ShuffleMask); + break; + case X86::VPUNPCKLDQYrr: + Src2Name = getRegName(MI->getOperand(2).getReg()); + // FALL THROUGH. + case X86::VPUNPCKLDQYrm: + Src1Name = getRegName(MI->getOperand(1).getReg()); + DestName = getRegName(MI->getOperand(0).getReg()); + DecodeUNPCKLMask(MVT::v8i32, ShuffleMask); break; case X86::PUNPCKLQDQrr: Src2Name = getRegName(MI->getOperand(2).getReg()); // FALL THROUGH. case X86::PUNPCKLQDQrm: Src1Name = getRegName(MI->getOperand(0).getReg()); - DecodePUNPCKLQDQMask(2, ShuffleMask); + DecodeUNPCKLMask(MVT::v2i64, ShuffleMask); + break; + case X86::VPUNPCKLQDQrr: + Src2Name = getRegName(MI->getOperand(2).getReg()); + // FALL THROUGH. + case X86::VPUNPCKLQDQrm: + Src1Name = getRegName(MI->getOperand(1).getReg()); + DestName = getRegName(MI->getOperand(0).getReg()); + DecodeUNPCKLMask(MVT::v2i64, ShuffleMask); + break; + case X86::VPUNPCKLQDQYrr: + Src2Name = getRegName(MI->getOperand(2).getReg()); + // FALL THROUGH. + case X86::VPUNPCKLQDQYrm: + Src1Name = getRegName(MI->getOperand(1).getReg()); + DestName = getRegName(MI->getOperand(0).getReg()); + DecodeUNPCKLMask(MVT::v4i64, ShuffleMask); break; case X86::SHUFPDrri: @@ -217,14 +345,14 @@ Src2Name = getRegName(MI->getOperand(2).getReg()); // FALL THROUGH. case X86::UNPCKLPDrm: - DecodeUNPCKLPMask(MVT::v2f64, ShuffleMask); + DecodeUNPCKLMask(MVT::v2f64, ShuffleMask); Src1Name = getRegName(MI->getOperand(0).getReg()); break; case X86::VUNPCKLPDrr: Src2Name = getRegName(MI->getOperand(2).getReg()); // FALL THROUGH. case X86::VUNPCKLPDrm: - DecodeUNPCKLPMask(MVT::v2f64, ShuffleMask); + DecodeUNPCKLMask(MVT::v2f64, ShuffleMask); Src1Name = getRegName(MI->getOperand(1).getReg()); DestName = getRegName(MI->getOperand(0).getReg()); break; @@ -232,7 +360,7 @@ Src2Name = getRegName(MI->getOperand(2).getReg()); // FALL THROUGH. case X86::VUNPCKLPDYrm: - DecodeUNPCKLPMask(MVT::v4f64, ShuffleMask); + DecodeUNPCKLMask(MVT::v4f64, ShuffleMask); Src1Name = getRegName(MI->getOperand(1).getReg()); DestName = getRegName(MI->getOperand(0).getReg()); break; @@ -240,14 +368,14 @@ Src2Name = getRegName(MI->getOperand(2).getReg()); // FALL THROUGH. case X86::UNPCKLPSrm: - DecodeUNPCKLPMask(MVT::v4f32, ShuffleMask); + DecodeUNPCKLMask(MVT::v4f32, ShuffleMask); Src1Name = getRegName(MI->getOperand(0).getReg()); break; case X86::VUNPCKLPSrr: Src2Name = getRegName(MI->getOperand(2).getReg()); // FALL THROUGH. case X86::VUNPCKLPSrm: - DecodeUNPCKLPMask(MVT::v4f32, ShuffleMask); + DecodeUNPCKLMask(MVT::v4f32, ShuffleMask); Src1Name = getRegName(MI->getOperand(1).getReg()); DestName = getRegName(MI->getOperand(0).getReg()); break; @@ -255,7 +383,7 @@ Src2Name = getRegName(MI->getOperand(2).getReg()); // FALL THROUGH. case X86::VUNPCKLPSYrm: - DecodeUNPCKLPMask(MVT::v8f32, ShuffleMask); + DecodeUNPCKLMask(MVT::v8f32, ShuffleMask); Src1Name = getRegName(MI->getOperand(1).getReg()); DestName = getRegName(MI->getOperand(0).getReg()); break; @@ -263,14 +391,14 @@ Src2Name = getRegName(MI->getOperand(2).getReg()); // FALL THROUGH. case X86::UNPCKHPDrm: - DecodeUNPCKHPMask(MVT::v2f64, ShuffleMask); + DecodeUNPCKHMask(MVT::v2f64, ShuffleMask); Src1Name = getRegName(MI->getOperand(0).getReg()); break; case X86::VUNPCKHPDrr: Src2Name = getRegName(MI->getOperand(2).getReg()); // FALL THROUGH. case X86::VUNPCKHPDrm: - DecodeUNPCKHPMask(MVT::v2f64, ShuffleMask); + DecodeUNPCKHMask(MVT::v2f64, ShuffleMask); Src1Name = getRegName(MI->getOperand(1).getReg()); DestName = getRegName(MI->getOperand(0).getReg()); break; @@ -278,7 +406,7 @@ Src2Name = getRegName(MI->getOperand(2).getReg()); // FALL THROUGH. case X86::VUNPCKHPDYrm: - DecodeUNPCKLPMask(MVT::v4f64, ShuffleMask); + DecodeUNPCKHMask(MVT::v4f64, ShuffleMask); Src1Name = getRegName(MI->getOperand(1).getReg()); DestName = getRegName(MI->getOperand(0).getReg()); break; @@ -286,14 +414,14 @@ Src2Name = getRegName(MI->getOperand(2).getReg()); // FALL THROUGH. case X86::UNPCKHPSrm: - DecodeUNPCKHPMask(MVT::v4f32, ShuffleMask); + DecodeUNPCKHMask(MVT::v4f32, ShuffleMask); Src1Name = getRegName(MI->getOperand(0).getReg()); break; case X86::VUNPCKHPSrr: Src2Name = getRegName(MI->getOperand(2).getReg()); // FALL THROUGH. case X86::VUNPCKHPSrm: - DecodeUNPCKHPMask(MVT::v4f32, ShuffleMask); + DecodeUNPCKHMask(MVT::v4f32, ShuffleMask); Src1Name = getRegName(MI->getOperand(1).getReg()); DestName = getRegName(MI->getOperand(0).getReg()); break; @@ -301,7 +429,7 @@ Src2Name = getRegName(MI->getOperand(2).getReg()); // FALL THROUGH. case X86::VUNPCKHPSYrm: - DecodeUNPCKHPMask(MVT::v8f32, ShuffleMask); + DecodeUNPCKHMask(MVT::v8f32, ShuffleMask); Src1Name = getRegName(MI->getOperand(1).getReg()); DestName = getRegName(MI->getOperand(0).getReg()); break; Modified: llvm/trunk/lib/Target/X86/Utils/X86ShuffleDecode.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/Utils/X86ShuffleDecode.cpp?rev=145924&r1=145923&r2=145924&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/Utils/X86ShuffleDecode.cpp (original) +++ llvm/trunk/lib/Target/X86/Utils/X86ShuffleDecode.cpp Mon Dec 5 23:31:16 2011 @@ -95,39 +95,6 @@ ShuffleMask.push_back(7); } -void DecodePUNPCKLBWMask(unsigned NElts, - SmallVectorImpl &ShuffleMask) { - DecodeUNPCKLPMask(MVT::getVectorVT(MVT::i8, NElts), ShuffleMask); -} - -void DecodePUNPCKLWDMask(unsigned NElts, - SmallVectorImpl &ShuffleMask) { - DecodeUNPCKLPMask(MVT::getVectorVT(MVT::i16, NElts), ShuffleMask); -} - -void DecodePUNPCKLDQMask(unsigned NElts, - SmallVectorImpl &ShuffleMask) { - DecodeUNPCKLPMask(MVT::getVectorVT(MVT::i32, NElts), ShuffleMask); -} - -void DecodePUNPCKLQDQMask(unsigned NElts, - SmallVectorImpl &ShuffleMask) { - DecodeUNPCKLPMask(MVT::getVectorVT(MVT::i64, NElts), ShuffleMask); -} - -void DecodePUNPCKLMask(EVT VT, - SmallVectorImpl &ShuffleMask) { - DecodeUNPCKLPMask(VT, ShuffleMask); -} - -void DecodePUNPCKHMask(unsigned NElts, - SmallVectorImpl &ShuffleMask) { - for (unsigned i = 0; i != NElts/2; ++i) { - ShuffleMask.push_back(i+NElts/2); - ShuffleMask.push_back(i+NElts+NElts/2); - } -} - void DecodeSHUFPMask(EVT VT, unsigned Imm, SmallVectorImpl &ShuffleMask) { unsigned NumElts = VT.getVectorNumElements(); @@ -152,7 +119,7 @@ } } -void DecodeUNPCKHPMask(EVT VT, SmallVectorImpl &ShuffleMask) { +void DecodeUNPCKHMask(EVT VT, SmallVectorImpl &ShuffleMask) { unsigned NumElts = VT.getVectorNumElements(); // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate @@ -171,10 +138,10 @@ } } -/// DecodeUNPCKLPMask - This decodes the shuffle masks for unpcklps/unpcklpd +/// DecodeUNPCKLMask - This decodes the shuffle masks for unpcklps/unpcklpd /// etc. VT indicates the type of the vector allowing it to handle different /// datatypes and vector widths. -void DecodeUNPCKLPMask(EVT VT, SmallVectorImpl &ShuffleMask) { +void DecodeUNPCKLMask(EVT VT, SmallVectorImpl &ShuffleMask) { unsigned NumElts = VT.getVectorNumElements(); // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate Modified: llvm/trunk/lib/Target/X86/Utils/X86ShuffleDecode.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/Utils/X86ShuffleDecode.h?rev=145924&r1=145923&r2=145924&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/Utils/X86ShuffleDecode.h (original) +++ llvm/trunk/lib/Target/X86/Utils/X86ShuffleDecode.h Mon Dec 5 23:31:16 2011 @@ -46,36 +46,18 @@ void DecodePSHUFLWMask(unsigned Imm, SmallVectorImpl &ShuffleMask); -void DecodePUNPCKLBWMask(unsigned NElts, - SmallVectorImpl &ShuffleMask); - -void DecodePUNPCKLWDMask(unsigned NElts, - SmallVectorImpl &ShuffleMask); - -void DecodePUNPCKLDQMask(unsigned NElts, - SmallVectorImpl &ShuffleMask); - -void DecodePUNPCKLQDQMask(unsigned NElts, - SmallVectorImpl &ShuffleMask); - -void DecodePUNPCKLMask(EVT VT, - SmallVectorImpl &ShuffleMask); - -void DecodePUNPCKHMask(unsigned NElts, - SmallVectorImpl &ShuffleMask); - void DecodeSHUFPMask(EVT VT, unsigned Imm, SmallVectorImpl &ShuffleMask); -/// DecodeUNPCKHPMask - This decodes the shuffle masks for unpckhps/unpckhpd +/// DecodeUNPCKHMask - This decodes the shuffle masks for unpckhps/unpckhpd /// etc. VT indicates the type of the vector allowing it to handle different /// datatypes and vector widths. -void DecodeUNPCKHPMask(EVT VT, SmallVectorImpl &ShuffleMask); +void DecodeUNPCKHMask(EVT VT, SmallVectorImpl &ShuffleMask); -/// DecodeUNPCKLPMask - This decodes the shuffle masks for unpcklps/unpcklpd +/// DecodeUNPCKLMask - This decodes the shuffle masks for unpcklps/unpcklpd /// etc. VT indicates the type of the vector allowing it to handle different /// datatypes and vector widths. -void DecodeUNPCKLPMask(EVT VT, SmallVectorImpl &ShuffleMask); +void DecodeUNPCKLMask(EVT VT, SmallVectorImpl &ShuffleMask); // DecodeVPERMILPMask - Decodes VPERMILPS/ VPERMILPD permutes for any 128-bit Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=145924&r1=145923&r2=145924&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original) +++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Mon Dec 5 23:31:16 2011 @@ -4461,16 +4461,12 @@ ShuffleMask); break; case X86ISD::PUNPCKH: - DecodePUNPCKHMask(NumElems, ShuffleMask); - break; case X86ISD::UNPCKHP: - DecodeUNPCKHPMask(VT, ShuffleMask); + DecodeUNPCKHMask(VT, ShuffleMask); break; case X86ISD::PUNPCKL: - DecodePUNPCKLMask(VT, ShuffleMask); - break; case X86ISD::UNPCKLP: - DecodeUNPCKLPMask(VT, ShuffleMask); + DecodeUNPCKLMask(VT, ShuffleMask); break; case X86ISD::MOVHLPS: DecodeMOVHLPSMask(NumElems, ShuffleMask); From geek4civic at gmail.com Tue Dec 6 00:06:44 2011 From: geek4civic at gmail.com (NAKAMURA Takumi) Date: Tue, 6 Dec 2011 15:06:44 +0900 Subject: [llvm-commits] [llvm] r145916 - in /llvm/trunk/test/MC: ARM/relax-thumb2-branches.s MachO/relax-thumb2-branches.s In-Reply-To: References: <20111206035605.AEADF2A6C12C@llvm.org> Message-ID: Jim, (excuse me to resend) 2011/12/6 Jim Grosbach : > MC/MachO does not assume X86. There are other tests for ARM there as well. I didn't find {arm|thumb} in MC/MachO. Did I miss anything? Please see also test/MC/MachO/dg.exp > For the time being, please revert this change. The test was in the correct place. I won't agree to revert. It would fail if enable_targets did not contain ARM. Would it be better if MC/MachO/ARM were there? ...Takumi From grosbach at apple.com Tue Dec 6 00:22:26 2011 From: grosbach at apple.com (Jim Grosbach) Date: Mon, 05 Dec 2011 22:22:26 -0800 Subject: [llvm-commits] [llvm] r145916 - in /llvm/trunk/test/MC: ARM/relax-thumb2-branches.s MachO/relax-thumb2-branches.s In-Reply-To: References: <20111206035605.AEADF2A6C12C@llvm.org> Message-ID: On Dec 5, 2011, at 10:05 PM, NAKAMURA Takumi wrote: > Jim, > > 2011/12/6 Jim Grosbach : >> MC/MachO does not assume X86. There are other tests for ARM there as well. > > I didn't find {arm|thumb} in MC/MachO. Did I miss anything? Hmmm. They must have been moved. There used to be, I'm almost certain of it. In any case, see below. > Please see also test/MC/MachO/dg.exp That is wrong. There is nothing target specific about that directory. >> For the time being, please revert this change. The test was in the correct place. > > I won't agree to revert. It would fail if enable_targets did not contain ARM. Then the predicate on the directory is wrong. Moving the test to MC/ARM is not the correct solution. > Would it be better if MC/MachO/ARM were there? That's what I was suggesting, yes. Please do this. Tests which generate MachO object files belong in the MachO directory, not the ARM directory. The MC/ARM tests aren't supposed to be testing object file format specific features, but rather target-independent parsing and encoding bits. -Jim From evan.cheng at apple.com Tue Dec 6 00:42:30 2011 From: evan.cheng at apple.com (Evan Cheng) Date: Mon, 05 Dec 2011 22:42:30 -0800 Subject: [llvm-commits] [llvm-gcc-4.2] r145784 - in /llvm-gcc-4.2/trunk/gcc: config/arm/arm.h config/i386/i386.h config/rs6000/rs6000.h llvm-backend.cpp In-Reply-To: <20111204014635.9B4232A6C12C@llvm.org> References: <20111204014635.9B4232A6C12C@llvm.org> Message-ID: Are there buildbots that use llvm-gcc? Can they switch to clang? llvm-gcc is supposedly dead now llvm 3.0 is done. Evan On Dec 3, 2011, at 5:46 PM, Nick Lewycky wrote: > Author: nicholas > Date: Sat Dec 3 19:46:35 2011 > New Revision: 145784 > > URL: http://llvm.org/viewvc/llvm-project?rev=145784&view=rev > Log: > Try to fix llvm-gcc build again. Rename my new macro to something that doesn't > exist with a macro that ... once existed but is still called when defined? > > Modified: > llvm-gcc-4.2/trunk/gcc/config/arm/arm.h > llvm-gcc-4.2/trunk/gcc/config/i386/i386.h > llvm-gcc-4.2/trunk/gcc/config/rs6000/rs6000.h > llvm-gcc-4.2/trunk/gcc/llvm-backend.cpp > > Modified: llvm-gcc-4.2/trunk/gcc/config/arm/arm.h > URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/config/arm/arm.h?rev=145784&r1=145783&r2=145784&view=diff > ============================================================================== > --- llvm-gcc-4.2/trunk/gcc/config/arm/arm.h (original) > +++ llvm-gcc-4.2/trunk/gcc/config/arm/arm.h Sat Dec 3 19:46:35 2011 > @@ -3574,7 +3574,7 @@ > argvec.push_back("-arm-strict-align"); \ > } > > -#define LLVM_SET_TARGET_OPTIONS(options) \ > +#define LLVM_SET_TARGET_MACHINE_OPTIONS(options) \ > options.GenerateSoftFloatCalls = TARGET_SOFT_FLOAT; \ > if (TARGET_HARD_FLOAT_ABI) \ > options.FloatABIForCalls = llvm::FloatABI::Hard; > > Modified: llvm-gcc-4.2/trunk/gcc/config/i386/i386.h > URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/config/i386/i386.h?rev=145784&r1=145783&r2=145784&view=diff > ============================================================================== > --- llvm-gcc-4.2/trunk/gcc/config/i386/i386.h (original) > +++ llvm-gcc-4.2/trunk/gcc/config/i386/i386.h Sat Dec 3 19:46:35 2011 > @@ -3966,7 +3966,7 @@ > argvec.push_back("-force-align-stack"); \ > } while (0) > > -#define LLVM_SET_TARGET_OPTIONS(options) \ > +#define LLVM_SET_TARGET_MACHINE_OPTIONS(options) \ > do { \ > /* A value of 3 in flag_omit_frame_pointer implies \ > omitting leaf frame pointers only. */ \ > > Modified: llvm-gcc-4.2/trunk/gcc/config/rs6000/rs6000.h > URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/config/rs6000/rs6000.h?rev=145784&r1=145783&r2=145784&view=diff > ============================================================================== > --- llvm-gcc-4.2/trunk/gcc/config/rs6000/rs6000.h (original) > +++ llvm-gcc-4.2/trunk/gcc/config/rs6000/rs6000.h Sat Dec 3 19:46:35 2011 > @@ -3470,7 +3470,7 @@ > > #define LLVM_SET_MACHINE_OPTIONS(argvec) > > -#define LLVM_SET_TARGET_OPTIONS(options) \ > +#define LLVM_SET_TARGET_MACHINE_OPTIONS(options) \ > options.GenerateSoftFloatCalls = TARGET_SOFT_FLOAT; > > /* When -m64 is specified, set the architecture to powerpc64-os-blah even if the > > Modified: llvm-gcc-4.2/trunk/gcc/llvm-backend.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/llvm-backend.cpp?rev=145784&r1=145783&r2=145784&view=diff > ============================================================================== > --- llvm-gcc-4.2/trunk/gcc/llvm-backend.cpp (original) > +++ llvm-gcc-4.2/trunk/gcc/llvm-backend.cpp Sat Dec 3 19:46:35 2011 > @@ -561,7 +561,7 @@ > FeatureStr = Features.getString(); > > TargetOptions Options; > - LLVM_SET_TARGET_OPTIONS(Options); > + LLVM_SET_TARGET_MACHINE_OPTIONS(Options); > Options.UnsafeFPMath = fast_math_flags_set_p(); > Options.NoInfsFPMath = !flag_honor_infinites; > Options.NoNaNsFPMath = !flag_honor_nans; > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From geek4civic at gmail.com Tue Dec 6 00:48:26 2011 From: geek4civic at gmail.com (NAKAMURA Takumi) Date: Tue, 06 Dec 2011 06:48:26 -0000 Subject: [llvm-commits] [llvm] r145925 - in /llvm/trunk/test/MC: ARM/relax-thumb2-branches.s MachO/ARM/ MachO/ARM/dg.exp MachO/ARM/relax-thumb2-branches.s Message-ID: <20111206064826.BD4812A6C12C@llvm.org> Author: chapuni Date: Tue Dec 6 00:48:26 2011 New Revision: 145925 URL: http://llvm.org/viewvc/llvm-project?rev=145925&view=rev Log: test/MC: Introduce MC/MachO/ARM, and relocate relax-thumb2-branches.s into it. FIXME: Restore more other arch-dependent MachO tests. (eg. r126401 and r133856) Added: llvm/trunk/test/MC/MachO/ARM/ llvm/trunk/test/MC/MachO/ARM/dg.exp llvm/trunk/test/MC/MachO/ARM/relax-thumb2-branches.s - copied, changed from r145924, llvm/trunk/test/MC/ARM/relax-thumb2-branches.s Removed: llvm/trunk/test/MC/ARM/relax-thumb2-branches.s Removed: llvm/trunk/test/MC/ARM/relax-thumb2-branches.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/relax-thumb2-branches.s?rev=145924&view=auto ============================================================================== --- llvm/trunk/test/MC/ARM/relax-thumb2-branches.s (original) +++ llvm/trunk/test/MC/ARM/relax-thumb2-branches.s (removed) @@ -1,14 +0,0 @@ -@ RUN: llvm-mc -triple=thumbv7-apple-darwin -show-encoding %s -filetype=obj -o - | macho-dump --dump-section-data | FileCheck %s - - ble Lfoo @ wide encoding - - .space 258 -Lfoo: - nop - - ble Lbaz @ narrow encoding - .space 256 -Lbaz: - -@ CHECK: '_section_data', '40f38180 -@ CHECK: 000000bf 7fdd Added: llvm/trunk/test/MC/MachO/ARM/dg.exp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/MachO/ARM/dg.exp?rev=145925&view=auto ============================================================================== --- llvm/trunk/test/MC/MachO/ARM/dg.exp (added) +++ llvm/trunk/test/MC/MachO/ARM/dg.exp Tue Dec 6 00:48:26 2011 @@ -0,0 +1,5 @@ +load_lib llvm.exp + +if { [llvm_supports_target ARM] } { + RunLLVMTests [lsort [glob -nocomplain $srcdir/$subdir/*.{ll,c,cpp,s}]] +} Copied: llvm/trunk/test/MC/MachO/ARM/relax-thumb2-branches.s (from r145924, llvm/trunk/test/MC/ARM/relax-thumb2-branches.s) URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/MachO/ARM/relax-thumb2-branches.s?p2=llvm/trunk/test/MC/MachO/ARM/relax-thumb2-branches.s&p1=llvm/trunk/test/MC/ARM/relax-thumb2-branches.s&r1=145924&r2=145925&rev=145925&view=diff ============================================================================== (empty) From geek4civic at gmail.com Tue Dec 6 00:53:20 2011 From: geek4civic at gmail.com (NAKAMURA Takumi) Date: Tue, 6 Dec 2011 15:53:20 +0900 Subject: [llvm-commits] [llvm] r145916 - in /llvm/trunk/test/MC: ARM/relax-thumb2-branches.s MachO/relax-thumb2-branches.s In-Reply-To: References: <20111206035605.AEADF2A6C12C@llvm.org> Message-ID: 2011/12/6 Jim Grosbach : >> Would it be better if MC/MachO/ARM were there? > > That's what I was suggesting, yes. Please do this. Fixed in r145925, thanks! > Tests which generate MachO object files belong in the MachO directory, not the ARM directory. The MC/ARM tests aren't supposed to be testing object file format specific features, but rather target-independent parsing and encoding bits. Shall we restore changes in r126401 and r133856? ...Takumi From clattner at apple.com Tue Dec 6 02:20:14 2011 From: clattner at apple.com (Chris Lattner) Date: Tue, 06 Dec 2011 00:20:14 -0800 Subject: [llvm-commits] PATCH: Initial patches for changing the semantics of llvm.cttz and llvm.ctlz In-Reply-To: <986B8FE1-E724-446E-B0DB-465FF1595247@apple.com> References: <2DBA1282-CC2C-430B-9A62-5694D5ABAD4B@apple.com> <986B8FE1-E724-446E-B0DB-465FF1595247@apple.com> Message-ID: On Dec 5, 2011, at 3:37 AM, Stephen Canon wrote: > On Dec 1, 2011, at 2:20 PM, Dan Gohman wrote: > >> The "old" semantics really are more desirable though, in general. The only >> reason I know of for the "new" semantics is to cater to x86's old bsf and >> bsr instructions. But x86 admits its own deficiency, and has since introduced >> the lzcnt and tzcnt instructions, which behave properly. It seems unfortunate >> to require people who want the sane semantics to use a branch (even if >> CodeGen is clever and can eliminate it). > > Agreed. The x86 ISA semantics of BSR/BSF are nuts (and not followed by any other mainstream architecture with which I am familiar). Surely there's some way to give llvm the hint it needs to optimize this particular case on x86 without making the semantics of llvm ir similarly broken. We have a winner here :). How about you change the intrinsics to "llvm.cttz(i32 X, i1 UndefOnZero)". That allows clean autoupgrade as well as capturing the extra information. Also, if there is a intrinsics for the lzcnt instruction, please replace it with the newly enhanced llvm.ctlz intrinsic. -Chris From craig.topper at gmail.com Tue Dec 6 02:21:25 2011 From: craig.topper at gmail.com (Craig Topper) Date: Tue, 06 Dec 2011 08:21:25 -0000 Subject: [llvm-commits] [llvm] r145926 - in /llvm/trunk/lib/Target/X86: X86ISelLowering.cpp X86ISelLowering.h X86InstrFragmentsSIMD.td X86InstrSSE.td Message-ID: <20111206082126.14E072A6C12C@llvm.org> Author: ctopper Date: Tue Dec 6 02:21:25 2011 New Revision: 145926 URL: http://llvm.org/viewvc/llvm-project?rev=145926&view=rev Log: Merge floating point and integer UNPCK X86ISD node types. Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp llvm/trunk/lib/Target/X86/X86ISelLowering.h llvm/trunk/lib/Target/X86/X86InstrFragmentsSIMD.td llvm/trunk/lib/Target/X86/X86InstrSSE.td Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=145926&r1=145925&r2=145926&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original) +++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Tue Dec 6 02:21:25 2011 @@ -2851,10 +2851,8 @@ case X86ISD::MOVDDUP: case X86ISD::MOVSS: case X86ISD::MOVSD: - case X86ISD::UNPCKLP: - case X86ISD::PUNPCKL: - case X86ISD::UNPCKHP: - case X86ISD::PUNPCKH: + case X86ISD::UNPCKL: + case X86ISD::UNPCKH: case X86ISD::VPERMILP: case X86ISD::VPERM2X128: return true; @@ -2914,10 +2912,8 @@ case X86ISD::MOVLPD: case X86ISD::MOVSS: case X86ISD::MOVSD: - case X86ISD::UNPCKLP: - case X86ISD::PUNPCKL: - case X86ISD::UNPCKHP: - case X86ISD::PUNPCKH: + case X86ISD::UNPCKL: + case X86ISD::UNPCKH: return DAG.getNode(Opc, dl, VT, V1, V2); } return SDValue(); @@ -4460,12 +4456,10 @@ DecodeSHUFPMask(VT, cast(ImmN)->getZExtValue(), ShuffleMask); break; - case X86ISD::PUNPCKH: - case X86ISD::UNPCKHP: + case X86ISD::UNPCKH: DecodeUNPCKHMask(VT, ShuffleMask); break; - case X86ISD::PUNPCKL: - case X86ISD::UNPCKLP: + case X86ISD::UNPCKL: DecodeUNPCKLMask(VT, ShuffleMask); break; case X86ISD::MOVHLPS: @@ -6364,50 +6358,6 @@ X86::getShuffleSHUFImmediate(SVOp), DAG); } -static inline unsigned getUNPCKLOpcode(EVT VT, bool HasAVX2) { - switch(VT.getSimpleVT().SimpleTy) { - case MVT::v32i8: - case MVT::v16i8: - case MVT::v16i16: - case MVT::v8i16: - case MVT::v4i32: - case MVT::v2i64: return X86ISD::PUNPCKL; - case MVT::v8i32: - case MVT::v4i64: - if (HasAVX2) return X86ISD::PUNPCKL; - // else use fp unit for int unpack. - case MVT::v8f32: - case MVT::v4f32: - case MVT::v4f64: - case MVT::v2f64: return X86ISD::UNPCKLP; - default: - llvm_unreachable("Unknown type for unpckl"); - } - return 0; -} - -static inline unsigned getUNPCKHOpcode(EVT VT, bool HasAVX2) { - switch(VT.getSimpleVT().SimpleTy) { - case MVT::v32i8: - case MVT::v16i8: - case MVT::v16i16: - case MVT::v8i16: - case MVT::v4i32: - case MVT::v2i64: return X86ISD::PUNPCKH; - case MVT::v4i64: - case MVT::v8i32: - if (HasAVX2) return X86ISD::PUNPCKH; - // else use fp unit for int unpack. - case MVT::v8f32: - case MVT::v4f32: - case MVT::v4f64: - case MVT::v2f64: return X86ISD::UNPCKHP; - default: - llvm_unreachable("Unknown type for unpckh"); - } - return 0; -} - static SDValue NormalizeVectorShuffle(SDValue Op, SelectionDAG &DAG, const TargetLowering &TLI, @@ -6518,11 +6468,9 @@ // NOTE: isPSHUFDMask can also match both masks below (unpckl_undef and // unpckh_undef). Only use pshufd if speed is more important than size. if (OptForSize && X86::isUNPCKL_v_undef_Mask(SVOp)) - return getTargetShuffleNode(getUNPCKLOpcode(VT, HasAVX2), dl, VT, V1, V1, - DAG); + return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG); if (OptForSize && X86::isUNPCKH_v_undef_Mask(SVOp)) - return getTargetShuffleNode(getUNPCKHOpcode(VT, HasAVX2), dl, VT, V1, V1, - DAG); + return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG); if (X86::isMOVDDUPMask(SVOp) && Subtarget->hasSSE3orAVX() && V2IsUndef && RelaxedMayFoldVectorLoad(V1)) @@ -6534,8 +6482,7 @@ // Use to match splats if (HasXMMInt && X86::isUNPCKHMask(SVOp, HasAVX2) && V2IsUndef && (VT == MVT::v2f64 || VT == MVT::v2i64)) - return getTargetShuffleNode(getUNPCKHOpcode(VT, HasAVX2), dl, VT, V1, V1, - DAG); + return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG); if (X86::isPSHUFDMask(SVOp)) { // The actual implementation will match the mask in the if above and then @@ -6635,12 +6582,10 @@ } if (isUNPCKLMask(M, VT, HasAVX2)) - return getTargetShuffleNode(getUNPCKLOpcode(VT, HasAVX2), dl, VT, V1, V2, - DAG); + return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG); if (isUNPCKHMask(M, VT, HasAVX2)) - return getTargetShuffleNode(getUNPCKHOpcode(VT, HasAVX2), dl, VT, V1, V2, - DAG); + return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG); if (V2IsSplat) { // Normalize mask so all entries that point to V2 points to its first @@ -6664,12 +6609,10 @@ ShuffleVectorSDNode *NewSVOp = cast(NewOp); if (X86::isUNPCKLMask(NewSVOp, HasAVX2)) - return getTargetShuffleNode(getUNPCKLOpcode(VT, HasAVX2), dl, VT, V2, V1, - DAG); + return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V2, V1, DAG); if (X86::isUNPCKHMask(NewSVOp, HasAVX2)) - return getTargetShuffleNode(getUNPCKHOpcode(VT, HasAVX2), dl, VT, V2, V1, - DAG); + return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V2, V1, DAG); } // Normalize the node to match x86 shuffle ops if needed @@ -6689,8 +6632,7 @@ if (ShuffleVectorSDNode::isSplatMask(&M[0], VT) && SVOp->getSplatIndex() == 0 && V2IsUndef) { if (VT == MVT::v2f64 || VT == MVT::v2i64) - return getTargetShuffleNode(getUNPCKLOpcode(VT, HasAVX2), dl, VT, V1, V1, - DAG); + return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG); } if (isPSHUFHWMask(M, VT)) @@ -6708,11 +6650,9 @@ X86::getShuffleSHUFImmediate(SVOp), DAG); if (isUNPCKL_v_undef_Mask(M, VT)) - return getTargetShuffleNode(getUNPCKLOpcode(VT, HasAVX2), dl, VT, V1, V1, - DAG); + return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG); if (isUNPCKH_v_undef_Mask(M, VT)) - return getTargetShuffleNode(getUNPCKHOpcode(VT, HasAVX2), dl, VT, V1, V1, - DAG); + return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG); //===--------------------------------------------------------------------===// // Generate target specific nodes for 128 or 256-bit shuffles only @@ -11023,10 +10963,8 @@ case X86ISD::MOVSLDUP_LD: return "X86ISD::MOVSLDUP_LD"; case X86ISD::MOVSD: return "X86ISD::MOVSD"; case X86ISD::MOVSS: return "X86ISD::MOVSS"; - case X86ISD::UNPCKLP: return "X86ISD::UNPCKLP"; - case X86ISD::UNPCKHP: return "X86ISD::UNPCKHP"; - case X86ISD::PUNPCKL: return "X86ISD::PUNPCKL"; - case X86ISD::PUNPCKH: return "X86ISD::PUNPCKH"; + case X86ISD::UNPCKL: return "X86ISD::UNPCKL"; + case X86ISD::UNPCKH: return "X86ISD::UNPCKH"; case X86ISD::VBROADCAST: return "X86ISD::VBROADCAST"; case X86ISD::VPERMILP: return "X86ISD::VPERMILP"; case X86ISD::VPERM2X128: return "X86ISD::VPERM2X128"; @@ -14616,10 +14554,8 @@ case X86ISD::SHUFPS: // Handle all target specific shuffles case X86ISD::SHUFPD: case X86ISD::PALIGN: - case X86ISD::PUNPCKH: - case X86ISD::UNPCKHP: - case X86ISD::PUNPCKL: - case X86ISD::UNPCKLP: + case X86ISD::UNPCKH: + case X86ISD::UNPCKL: case X86ISD::MOVHLPS: case X86ISD::MOVLHPS: case X86ISD::PSHUFD: Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.h?rev=145926&r1=145925&r2=145926&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86ISelLowering.h (original) +++ llvm/trunk/lib/Target/X86/X86ISelLowering.h Tue Dec 6 02:21:25 2011 @@ -273,10 +273,8 @@ MOVLPD, MOVSD, MOVSS, - UNPCKLP, - UNPCKHP, - PUNPCKL, - PUNPCKH, + UNPCKL, + UNPCKH, VPERMILP, VPERM2X128, VBROADCAST, Modified: llvm/trunk/lib/Target/X86/X86InstrFragmentsSIMD.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrFragmentsSIMD.td?rev=145926&r1=145925&r2=145926&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86InstrFragmentsSIMD.td (original) +++ llvm/trunk/lib/Target/X86/X86InstrFragmentsSIMD.td Tue Dec 6 02:21:25 2011 @@ -130,11 +130,8 @@ def X86Movlps : SDNode<"X86ISD::MOVLPS", SDTShuff2Op>; def X86Movlpd : SDNode<"X86ISD::MOVLPD", SDTShuff2Op>; -def X86Unpcklp : SDNode<"X86ISD::UNPCKLP", SDTShuff2Op>; -def X86Unpckhp : SDNode<"X86ISD::UNPCKHP", SDTShuff2Op>; - -def X86Punpckl : SDNode<"X86ISD::PUNPCKL", SDTShuff2Op>; -def X86Punpckh : SDNode<"X86ISD::PUNPCKH", SDTShuff2Op>; +def X86Unpckl : SDNode<"X86ISD::UNPCKL", SDTShuff2Op>; +def X86Unpckh : SDNode<"X86ISD::UNPCKH", SDTShuff2Op>; def X86VPermilp : SDNode<"X86ISD::VPERMILP", SDTShuff2OpI>; Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrSSE.td?rev=145926&r1=145925&r2=145926&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86InstrSSE.td (original) +++ llvm/trunk/lib/Target/X86/X86InstrSSE.td Tue Dec 6 02:21:25 2011 @@ -1157,11 +1157,11 @@ (bc_v4i32 (v2i64 (X86vzload addr:$src2)))), (VMOVHPSrm VR128:$src1, addr:$src2)>; - // FIXME: Instead of X86Unpcklp, there should be a X86Movlhpd here, the problem + // FIXME: Instead of X86Unpckl, there should be a X86Movlhpd here, the problem // is during lowering, where it's not possible to recognize the load fold cause // it has two uses through a bitcast. One use disappears at isel time and the // fold opportunity reappears. - def : Pat<(v2f64 (X86Unpcklp VR128:$src1, + def : Pat<(v2f64 (X86Unpckl VR128:$src1, (scalar_to_vector (loadf64 addr:$src2)))), (VMOVHPDrm VR128:$src1, addr:$src2)>; @@ -1172,10 +1172,10 @@ // Store patterns def : Pat<(store (f64 (vector_extract - (v2f64 (X86Unpckhp VR128:$src, (undef))), (iPTR 0))), addr:$dst), + (v2f64 (X86Unpckh VR128:$src, (undef))), (iPTR 0))), addr:$dst), (VMOVHPSmr addr:$dst, VR128:$src)>; def : Pat<(store (f64 (vector_extract - (v2f64 (X86Unpckhp VR128:$src, (undef))), (iPTR 0))), addr:$dst), + (v2f64 (X86Unpckh VR128:$src, (undef))), (iPTR 0))), addr:$dst), (VMOVHPDmr addr:$dst, VR128:$src)>; } @@ -1195,16 +1195,16 @@ // Store patterns def : Pat<(store (f64 (vector_extract - (v2f64 (X86Unpckhp VR128:$src, (undef))), (iPTR 0))), addr:$dst), + (v2f64 (X86Unpckh VR128:$src, (undef))), (iPTR 0))), addr:$dst), (MOVHPSmr addr:$dst, VR128:$src)>; } let Predicates = [HasSSE2] in { - // FIXME: Instead of X86Unpcklp, there should be a X86Movlhpd here, the problem + // FIXME: Instead of X86Unpckl, there should be a X86Movlhpd here, the problem // is during lowering, where it's not possible to recognize the load fold cause // it has two uses through a bitcast. One use disappears at isel time and the // fold opportunity reappears. - def : Pat<(v2f64 (X86Unpcklp VR128:$src1, + def : Pat<(v2f64 (X86Unpckl VR128:$src1, (scalar_to_vector (loadf64 addr:$src2)))), (MOVHPDrm VR128:$src1, addr:$src2)>; @@ -1215,7 +1215,7 @@ // Store patterns def : Pat<(store (f64 (vector_extract - (v2f64 (X86Unpckhp VR128:$src, (undef))), (iPTR 0))),addr:$dst), + (v2f64 (X86Unpckh VR128:$src, (undef))), (iPTR 0))),addr:$dst), (MOVHPDmr addr:$dst, VR128:$src)>; } @@ -2431,27 +2431,27 @@ } // AddedComplexity let Predicates = [HasSSE1] in { - def : Pat<(v4f32 (X86Unpcklp VR128:$src1, (memopv4f32 addr:$src2))), + def : Pat<(v4f32 (X86Unpckl VR128:$src1, (memopv4f32 addr:$src2))), (UNPCKLPSrm VR128:$src1, addr:$src2)>; - def : Pat<(v4f32 (X86Unpcklp VR128:$src1, VR128:$src2)), + def : Pat<(v4f32 (X86Unpckl VR128:$src1, VR128:$src2)), (UNPCKLPSrr VR128:$src1, VR128:$src2)>; - def : Pat<(v4f32 (X86Unpckhp VR128:$src1, (memopv4f32 addr:$src2))), + def : Pat<(v4f32 (X86Unpckh VR128:$src1, (memopv4f32 addr:$src2))), (UNPCKHPSrm VR128:$src1, addr:$src2)>; - def : Pat<(v4f32 (X86Unpckhp VR128:$src1, VR128:$src2)), + def : Pat<(v4f32 (X86Unpckh VR128:$src1, VR128:$src2)), (UNPCKHPSrr VR128:$src1, VR128:$src2)>; } let Predicates = [HasSSE2] in { - def : Pat<(v2f64 (X86Unpcklp VR128:$src1, (memopv2f64 addr:$src2))), + def : Pat<(v2f64 (X86Unpckl VR128:$src1, (memopv2f64 addr:$src2))), (UNPCKLPDrm VR128:$src1, addr:$src2)>; - def : Pat<(v2f64 (X86Unpcklp VR128:$src1, VR128:$src2)), + def : Pat<(v2f64 (X86Unpckl VR128:$src1, VR128:$src2)), (UNPCKLPDrr VR128:$src1, VR128:$src2)>; - def : Pat<(v2f64 (X86Unpckhp VR128:$src1, (memopv2f64 addr:$src2))), + def : Pat<(v2f64 (X86Unpckh VR128:$src1, (memopv2f64 addr:$src2))), (UNPCKHPDrm VR128:$src1, addr:$src2)>; - def : Pat<(v2f64 (X86Unpckhp VR128:$src1, VR128:$src2)), + def : Pat<(v2f64 (X86Unpckh VR128:$src1, VR128:$src2)), (UNPCKHPDrr VR128:$src1, VR128:$src2)>; - // FIXME: Instead of X86Movddup, there should be a X86Unpcklp here, the + // FIXME: Instead of X86Movddup, there should be a X86Unpckl here, the // problem is during lowering, where it's not possible to recognize the load // fold cause it has two uses through a bitcast. One use disappears at isel // time and the fold opportunity reappears. @@ -2464,59 +2464,43 @@ } let Predicates = [HasAVX] in { - def : Pat<(v4f32 (X86Unpcklp VR128:$src1, (memopv4f32 addr:$src2))), + def : Pat<(v4f32 (X86Unpckl VR128:$src1, (memopv4f32 addr:$src2))), (VUNPCKLPSrm VR128:$src1, addr:$src2)>; - def : Pat<(v4f32 (X86Unpcklp VR128:$src1, VR128:$src2)), + def : Pat<(v4f32 (X86Unpckl VR128:$src1, VR128:$src2)), (VUNPCKLPSrr VR128:$src1, VR128:$src2)>; - def : Pat<(v4f32 (X86Unpckhp VR128:$src1, (memopv4f32 addr:$src2))), + def : Pat<(v4f32 (X86Unpckh VR128:$src1, (memopv4f32 addr:$src2))), (VUNPCKHPSrm VR128:$src1, addr:$src2)>; - def : Pat<(v4f32 (X86Unpckhp VR128:$src1, VR128:$src2)), + def : Pat<(v4f32 (X86Unpckh VR128:$src1, VR128:$src2)), (VUNPCKHPSrr VR128:$src1, VR128:$src2)>; - def : Pat<(v8f32 (X86Unpcklp VR256:$src1, (memopv8f32 addr:$src2))), + def : Pat<(v8f32 (X86Unpckl VR256:$src1, (memopv8f32 addr:$src2))), (VUNPCKLPSYrm VR256:$src1, addr:$src2)>; - def : Pat<(v8f32 (X86Unpcklp VR256:$src1, VR256:$src2)), + def : Pat<(v8f32 (X86Unpckl VR256:$src1, VR256:$src2)), (VUNPCKLPSYrr VR256:$src1, VR256:$src2)>; - def : Pat<(v8i32 (X86Unpcklp VR256:$src1, VR256:$src2)), - (VUNPCKLPSYrr VR256:$src1, VR256:$src2)>; - def : Pat<(v8i32 (X86Unpcklp VR256:$src1, (bc_v8i32 (memopv4i64 addr:$src2)))), - (VUNPCKLPSYrm VR256:$src1, addr:$src2)>; - def : Pat<(v8f32 (X86Unpckhp VR256:$src1, (memopv8f32 addr:$src2))), + def : Pat<(v8f32 (X86Unpckh VR256:$src1, (memopv8f32 addr:$src2))), (VUNPCKHPSYrm VR256:$src1, addr:$src2)>; - def : Pat<(v8f32 (X86Unpckhp VR256:$src1, VR256:$src2)), - (VUNPCKHPSYrr VR256:$src1, VR256:$src2)>; - def : Pat<(v8i32 (X86Unpckhp VR256:$src1, (bc_v8i32 (memopv4i64 addr:$src2)))), - (VUNPCKHPSYrm VR256:$src1, addr:$src2)>; - def : Pat<(v8i32 (X86Unpckhp VR256:$src1, VR256:$src2)), + def : Pat<(v8f32 (X86Unpckh VR256:$src1, VR256:$src2)), (VUNPCKHPSYrr VR256:$src1, VR256:$src2)>; - def : Pat<(v2f64 (X86Unpcklp VR128:$src1, (memopv2f64 addr:$src2))), + def : Pat<(v2f64 (X86Unpckl VR128:$src1, (memopv2f64 addr:$src2))), (VUNPCKLPDrm VR128:$src1, addr:$src2)>; - def : Pat<(v2f64 (X86Unpcklp VR128:$src1, VR128:$src2)), + def : Pat<(v2f64 (X86Unpckl VR128:$src1, VR128:$src2)), (VUNPCKLPDrr VR128:$src1, VR128:$src2)>; - def : Pat<(v2f64 (X86Unpckhp VR128:$src1, (memopv2f64 addr:$src2))), + def : Pat<(v2f64 (X86Unpckh VR128:$src1, (memopv2f64 addr:$src2))), (VUNPCKHPDrm VR128:$src1, addr:$src2)>; - def : Pat<(v2f64 (X86Unpckhp VR128:$src1, VR128:$src2)), + def : Pat<(v2f64 (X86Unpckh VR128:$src1, VR128:$src2)), (VUNPCKHPDrr VR128:$src1, VR128:$src2)>; - def : Pat<(v4f64 (X86Unpcklp VR256:$src1, (memopv4f64 addr:$src2))), - (VUNPCKLPDYrm VR256:$src1, addr:$src2)>; - def : Pat<(v4f64 (X86Unpcklp VR256:$src1, VR256:$src2)), - (VUNPCKLPDYrr VR256:$src1, VR256:$src2)>; - def : Pat<(v4i64 (X86Unpcklp VR256:$src1, (memopv4i64 addr:$src2))), + def : Pat<(v4f64 (X86Unpckl VR256:$src1, (memopv4f64 addr:$src2))), (VUNPCKLPDYrm VR256:$src1, addr:$src2)>; - def : Pat<(v4i64 (X86Unpcklp VR256:$src1, VR256:$src2)), + def : Pat<(v4f64 (X86Unpckl VR256:$src1, VR256:$src2)), (VUNPCKLPDYrr VR256:$src1, VR256:$src2)>; - def : Pat<(v4f64 (X86Unpckhp VR256:$src1, (memopv4f64 addr:$src2))), - (VUNPCKHPDYrm VR256:$src1, addr:$src2)>; - def : Pat<(v4f64 (X86Unpckhp VR256:$src1, VR256:$src2)), - (VUNPCKHPDYrr VR256:$src1, VR256:$src2)>; - def : Pat<(v4i64 (X86Unpckhp VR256:$src1, (memopv4i64 addr:$src2))), + def : Pat<(v4f64 (X86Unpckh VR256:$src1, (memopv4f64 addr:$src2))), (VUNPCKHPDYrm VR256:$src1, addr:$src2)>; - def : Pat<(v4i64 (X86Unpckhp VR256:$src1, VR256:$src2)), + def : Pat<(v4f64 (X86Unpckh VR256:$src1, VR256:$src2)), (VUNPCKHPDYrr VR256:$src1, VR256:$src2)>; - // FIXME: Instead of X86Movddup, there should be a X86Unpcklp here, the + // FIXME: Instead of X86Movddup, there should be a X86Unpckl here, the // problem is during lowering, where it's not possible to recognize the load // fold cause it has two uses through a bitcast. One use disappears at isel // time and the fold opportunity reappears. @@ -4199,66 +4183,88 @@ } let Predicates = [HasAVX] in { - defm VPUNPCKLBW : sse2_unpack<0x60, "vpunpcklbw", v16i8, X86Punpckl, + defm VPUNPCKLBW : sse2_unpack<0x60, "vpunpcklbw", v16i8, X86Unpckl, bc_v16i8, 0>, VEX_4V; - defm VPUNPCKLWD : sse2_unpack<0x61, "vpunpcklwd", v8i16, X86Punpckl, + defm VPUNPCKLWD : sse2_unpack<0x61, "vpunpcklwd", v8i16, X86Unpckl, bc_v8i16, 0>, VEX_4V; - defm VPUNPCKLDQ : sse2_unpack<0x62, "vpunpckldq", v4i32, X86Punpckl, + defm VPUNPCKLDQ : sse2_unpack<0x62, "vpunpckldq", v4i32, X86Unpckl, bc_v4i32, 0>, VEX_4V; - defm VPUNPCKLQDQ : sse2_unpack<0x6C, "vpunpcklqdq", v2i64, X86Punpckl, + defm VPUNPCKLQDQ : sse2_unpack<0x6C, "vpunpcklqdq", v2i64, X86Unpckl, bc_v2i64, 0>, VEX_4V; - defm VPUNPCKHBW : sse2_unpack<0x68, "vpunpckhbw", v16i8, X86Punpckh, + defm VPUNPCKHBW : sse2_unpack<0x68, "vpunpckhbw", v16i8, X86Unpckh, bc_v16i8, 0>, VEX_4V; - defm VPUNPCKHWD : sse2_unpack<0x69, "vpunpckhwd", v8i16, X86Punpckh, + defm VPUNPCKHWD : sse2_unpack<0x69, "vpunpckhwd", v8i16, X86Unpckh, bc_v8i16, 0>, VEX_4V; - defm VPUNPCKHDQ : sse2_unpack<0x6A, "vpunpckhdq", v4i32, X86Punpckh, + defm VPUNPCKHDQ : sse2_unpack<0x6A, "vpunpckhdq", v4i32, X86Unpckh, bc_v4i32, 0>, VEX_4V; - defm VPUNPCKHQDQ : sse2_unpack<0x6D, "vpunpckhqdq", v2i64, X86Punpckh, + defm VPUNPCKHQDQ : sse2_unpack<0x6D, "vpunpckhqdq", v2i64, X86Unpckh, bc_v2i64, 0>, VEX_4V; } let Predicates = [HasAVX2] in { - defm VPUNPCKLBW : sse2_unpack_y<0x60, "vpunpcklbw", v32i8, X86Punpckl, + defm VPUNPCKLBW : sse2_unpack_y<0x60, "vpunpcklbw", v32i8, X86Unpckl, bc_v32i8>, VEX_4V; - defm VPUNPCKLWD : sse2_unpack_y<0x61, "vpunpcklwd", v16i16, X86Punpckl, + defm VPUNPCKLWD : sse2_unpack_y<0x61, "vpunpcklwd", v16i16, X86Unpckl, bc_v16i16>, VEX_4V; - defm VPUNPCKLDQ : sse2_unpack_y<0x62, "vpunpckldq", v8i32, X86Punpckl, + defm VPUNPCKLDQ : sse2_unpack_y<0x62, "vpunpckldq", v8i32, X86Unpckl, bc_v8i32>, VEX_4V; - defm VPUNPCKLQDQ : sse2_unpack_y<0x6C, "vpunpcklqdq", v4i64, X86Punpckl, + defm VPUNPCKLQDQ : sse2_unpack_y<0x6C, "vpunpcklqdq", v4i64, X86Unpckl, bc_v4i64>, VEX_4V; - defm VPUNPCKHBW : sse2_unpack_y<0x68, "vpunpckhbw", v32i8, X86Punpckh, + defm VPUNPCKHBW : sse2_unpack_y<0x68, "vpunpckhbw", v32i8, X86Unpckh, bc_v32i8>, VEX_4V; - defm VPUNPCKHWD : sse2_unpack_y<0x69, "vpunpckhwd", v16i16, X86Punpckh, + defm VPUNPCKHWD : sse2_unpack_y<0x69, "vpunpckhwd", v16i16, X86Unpckh, bc_v16i16>, VEX_4V; - defm VPUNPCKHDQ : sse2_unpack_y<0x6A, "vpunpckhdq", v8i32, X86Punpckh, + defm VPUNPCKHDQ : sse2_unpack_y<0x6A, "vpunpckhdq", v8i32, X86Unpckh, bc_v8i32>, VEX_4V; - defm VPUNPCKHQDQ : sse2_unpack_y<0x6D, "vpunpckhqdq", v4i64, X86Punpckh, + defm VPUNPCKHQDQ : sse2_unpack_y<0x6D, "vpunpckhqdq", v4i64, X86Unpckh, bc_v4i64>, VEX_4V; } let Constraints = "$src1 = $dst" in { - defm PUNPCKLBW : sse2_unpack<0x60, "punpcklbw", v16i8, X86Punpckl, + defm PUNPCKLBW : sse2_unpack<0x60, "punpcklbw", v16i8, X86Unpckl, bc_v16i8>; - defm PUNPCKLWD : sse2_unpack<0x61, "punpcklwd", v8i16, X86Punpckl, + defm PUNPCKLWD : sse2_unpack<0x61, "punpcklwd", v8i16, X86Unpckl, bc_v8i16>; - defm PUNPCKLDQ : sse2_unpack<0x62, "punpckldq", v4i32, X86Punpckl, + defm PUNPCKLDQ : sse2_unpack<0x62, "punpckldq", v4i32, X86Unpckl, bc_v4i32>; - defm PUNPCKLQDQ : sse2_unpack<0x6C, "punpcklqdq", v2i64, X86Punpckl, + defm PUNPCKLQDQ : sse2_unpack<0x6C, "punpcklqdq", v2i64, X86Unpckl, bc_v2i64>; - defm PUNPCKHBW : sse2_unpack<0x68, "punpckhbw", v16i8, X86Punpckh, + defm PUNPCKHBW : sse2_unpack<0x68, "punpckhbw", v16i8, X86Unpckh, bc_v16i8>; - defm PUNPCKHWD : sse2_unpack<0x69, "punpckhwd", v8i16, X86Punpckh, + defm PUNPCKHWD : sse2_unpack<0x69, "punpckhwd", v8i16, X86Unpckh, bc_v8i16>; - defm PUNPCKHDQ : sse2_unpack<0x6A, "punpckhdq", v4i32, X86Punpckh, + defm PUNPCKHDQ : sse2_unpack<0x6A, "punpckhdq", v4i32, X86Unpckh, bc_v4i32>; - defm PUNPCKHQDQ : sse2_unpack<0x6D, "punpckhqdq", v2i64, X86Punpckh, + defm PUNPCKHQDQ : sse2_unpack<0x6D, "punpckhqdq", v2i64, X86Unpckh, bc_v2i64>; } } // ExeDomain = SSEPackedInt +// Patterns for using AVX1 instructions with integer vectors +// Here to give AVX2 priority +let Predicates = [HasAVX] in { + def : Pat<(v8i32 (X86Unpckl VR256:$src1, (bc_v8i32 (memopv4i64 addr:$src2)))), + (VUNPCKLPSYrm VR256:$src1, addr:$src2)>; + def : Pat<(v8i32 (X86Unpckl VR256:$src1, VR256:$src2)), + (VUNPCKLPSYrr VR256:$src1, VR256:$src2)>; + def : Pat<(v8i32 (X86Unpckh VR256:$src1, (bc_v8i32 (memopv4i64 addr:$src2)))), + (VUNPCKHPSYrm VR256:$src1, addr:$src2)>; + def : Pat<(v8i32 (X86Unpckh VR256:$src1, VR256:$src2)), + (VUNPCKHPSYrr VR256:$src1, VR256:$src2)>; + + def : Pat<(v4i64 (X86Unpckl VR256:$src1, (memopv4i64 addr:$src2))), + (VUNPCKLPDYrm VR256:$src1, addr:$src2)>; + def : Pat<(v4i64 (X86Unpckl VR256:$src1, VR256:$src2)), + (VUNPCKLPDYrr VR256:$src1, VR256:$src2)>; + def : Pat<(v4i64 (X86Unpckh VR256:$src1, (memopv4i64 addr:$src2))), + (VUNPCKHPDYrm VR256:$src1, addr:$src2)>; + def : Pat<(v4i64 (X86Unpckh VR256:$src1, VR256:$src2)), + (VUNPCKHPDYrr VR256:$src1, VR256:$src2)>; +} + // Splat v2f64 / v2i64 let AddedComplexity = 10 in { def : Pat<(splat_lo (v2i64 VR128:$src), (undef)), From grosbach at apple.com Tue Dec 6 01:51:03 2011 From: grosbach at apple.com (Jim Grosbach) Date: Mon, 05 Dec 2011 23:51:03 -0800 Subject: [llvm-commits] [llvm] r145916 - in /llvm/trunk/test/MC: ARM/relax-thumb2-branches.s MachO/relax-thumb2-branches.s In-Reply-To: References: <20111206035605.AEADF2A6C12C@llvm.org> Message-ID: <24FF7829-946F-49C6-9080-9E9C615F1991@apple.com> On Dec 5, 2011, at 10:53 PM, NAKAMURA Takumi wrote: > 2011/12/6 Jim Grosbach : >>> Would it be better if MC/MachO/ARM were there? >> >> That's what I was suggesting, yes. Please do this. > > Fixed in r145925, thanks! Perfect! Thanks for doing that. > >> Tests which generate MachO object files belong in the MachO directory, not the ARM directory. The MC/ARM tests aren't supposed to be testing object file format specific features, but rather target-independent parsing and encoding bits. > > Shall we restore changes in r126401 and r133856? Yes, that makes excellent sense now that we have a better place to put them. I'd forgotten about those patches, which I suppose explains why I was confused earlier! Thanks again, -Jim From ramosian.glider at gmail.com Tue Dec 6 02:43:58 2011 From: ramosian.glider at gmail.com (ramosian.glider at gmail.com) Date: Tue, 06 Dec 2011 08:43:58 +0000 Subject: [llvm-commits] Cleanup in ASan interceptors (issue 5437128) Message-ID: <20cf3074d322a88f0804b3686f04@google.com> Just do `make clean; make tests` There are many implicit deps for the tests, including a dependency on Clang itself. It's not a good idea to hard-code them all. http://codereview.appspot.com/5437128/ From samsonov at google.com Tue Dec 6 03:01:09 2011 From: samsonov at google.com (samsonov at google.com) Date: Tue, 06 Dec 2011 09:01:09 +0000 Subject: [llvm-commits] Cleanup in ASan interceptors (issue 5437128) Message-ID: <20cf300fafbf20763c04b368ad34@google.com> On 2011/12/06 08:43:58, ramosian.glider wrote: > Just do `make clean; make tests` Sure I did, this doesn't work. > There are many implicit deps for the tests, including a dependency on Clang > itself. It's not a good idea to hard-code them all. OK, disregard the change to Makefile then. http://codereview.appspot.com/5437128/ From craig.topper at gmail.com Tue Dec 6 03:04:59 2011 From: craig.topper at gmail.com (Craig Topper) Date: Tue, 06 Dec 2011 09:04:59 -0000 Subject: [llvm-commits] [llvm] r145927 - in /llvm/trunk: lib/Target/X86/X86InstrSSE.td test/CodeGen/X86/avx-intrinsics-x86.ll Message-ID: <20111206090459.9D3E82A6C12C@llvm.org> Author: ctopper Date: Tue Dec 6 03:04:59 2011 New Revision: 145927 URL: http://llvm.org/viewvc/llvm-project?rev=145927&view=rev Log: Fix a bunch of SSE/AVX patterns to use v2i64/v4i64 loads since all other integer vector loads are promoted to those. Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td llvm/trunk/test/CodeGen/X86/avx-intrinsics-x86.ll Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrSSE.td?rev=145927&r1=145926&r2=145927&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86InstrSSE.td (original) +++ llvm/trunk/lib/Target/X86/X86InstrSSE.td Tue Dec 6 03:04:59 2011 @@ -5092,7 +5092,7 @@ /// SS3I_unop_rm_int - Simple SSSE3 unary op whose type can be v*{i8,i16,i32}. multiclass SS3I_unop_rm_int opc, string OpcodeStr, - PatFrag mem_frag128, Intrinsic IntId128> { + Intrinsic IntId128> { def rr128 : SS38I, OpSize; + (bitconvert (memopv2i64 addr:$src))))]>, OpSize; } /// SS3I_unop_rm_int_y - Simple SSSE3 unary op whose type can be v*{i8,i16,i32}. multiclass SS3I_unop_rm_int_y opc, string OpcodeStr, - PatFrag mem_frag256, Intrinsic IntId256> { + Intrinsic IntId256> { def rr256 : SS38I, OpSize; + (bitconvert (memopv4i64 addr:$src))))]>, OpSize; } let Predicates = [HasAVX] in { - defm VPABSB : SS3I_unop_rm_int<0x1C, "vpabsb", memopv16i8, + defm VPABSB : SS3I_unop_rm_int<0x1C, "vpabsb", int_x86_ssse3_pabs_b_128>, VEX; - defm VPABSW : SS3I_unop_rm_int<0x1D, "vpabsw", memopv8i16, + defm VPABSW : SS3I_unop_rm_int<0x1D, "vpabsw", int_x86_ssse3_pabs_w_128>, VEX; - defm VPABSD : SS3I_unop_rm_int<0x1E, "vpabsd", memopv4i32, + defm VPABSD : SS3I_unop_rm_int<0x1E, "vpabsd", int_x86_ssse3_pabs_d_128>, VEX; } let Predicates = [HasAVX2] in { - defm VPABSB : SS3I_unop_rm_int_y<0x1C, "vpabsb", memopv32i8, + defm VPABSB : SS3I_unop_rm_int_y<0x1C, "vpabsb", int_x86_avx2_pabs_b>, VEX; - defm VPABSW : SS3I_unop_rm_int_y<0x1D, "vpabsw", memopv16i16, + defm VPABSW : SS3I_unop_rm_int_y<0x1D, "vpabsw", int_x86_avx2_pabs_w>, VEX; - defm VPABSD : SS3I_unop_rm_int_y<0x1E, "vpabsd", memopv8i32, + defm VPABSD : SS3I_unop_rm_int_y<0x1E, "vpabsd", int_x86_avx2_pabs_d>, VEX; } -defm PABSB : SS3I_unop_rm_int<0x1C, "pabsb", memopv16i8, +defm PABSB : SS3I_unop_rm_int<0x1C, "pabsb", int_x86_ssse3_pabs_b_128>; -defm PABSW : SS3I_unop_rm_int<0x1D, "pabsw", memopv8i16, +defm PABSW : SS3I_unop_rm_int<0x1D, "pabsw", int_x86_ssse3_pabs_w_128>; -defm PABSD : SS3I_unop_rm_int<0x1E, "pabsd", memopv4i32, +defm PABSD : SS3I_unop_rm_int<0x1E, "pabsd", int_x86_ssse3_pabs_d_128>; //===---------------------------------------------------------------------===// @@ -5155,8 +5155,7 @@ /// SS3I_binop_rm_int - Simple SSSE3 bin op whose type can be v*{i8,i16,i32}. multiclass SS3I_binop_rm_int opc, string OpcodeStr, - PatFrag mem_frag128, Intrinsic IntId128, - bit Is2Addr = 1> { + Intrinsic IntId128, bit Is2Addr = 1> { let isCommutable = 1 in def rr128 : SS38I, OpSize; + (bitconvert (memopv2i64 addr:$src2))))]>, OpSize; } multiclass SS3I_binop_rm_int_y opc, string OpcodeStr, - PatFrag mem_frag256, Intrinsic IntId256> { + Intrinsic IntId256> { let isCommutable = 1 in def rr256 : SS38I, OpSize; + (bitconvert (memopv4i64 addr:$src2))))]>, OpSize; } let ImmT = NoImm, Predicates = [HasAVX] in { let isCommutable = 0 in { - defm VPHADDW : SS3I_binop_rm_int<0x01, "vphaddw", memopv8i16, + defm VPHADDW : SS3I_binop_rm_int<0x01, "vphaddw", int_x86_ssse3_phadd_w_128, 0>, VEX_4V; - defm VPHADDD : SS3I_binop_rm_int<0x02, "vphaddd", memopv4i32, + defm VPHADDD : SS3I_binop_rm_int<0x02, "vphaddd", int_x86_ssse3_phadd_d_128, 0>, VEX_4V; - defm VPHADDSW : SS3I_binop_rm_int<0x03, "vphaddsw", memopv8i16, + defm VPHADDSW : SS3I_binop_rm_int<0x03, "vphaddsw", int_x86_ssse3_phadd_sw_128, 0>, VEX_4V; - defm VPHSUBW : SS3I_binop_rm_int<0x05, "vphsubw", memopv8i16, + defm VPHSUBW : SS3I_binop_rm_int<0x05, "vphsubw", int_x86_ssse3_phsub_w_128, 0>, VEX_4V; - defm VPHSUBD : SS3I_binop_rm_int<0x06, "vphsubd", memopv4i32, + defm VPHSUBD : SS3I_binop_rm_int<0x06, "vphsubd", int_x86_ssse3_phsub_d_128, 0>, VEX_4V; - defm VPHSUBSW : SS3I_binop_rm_int<0x07, "vphsubsw", memopv8i16, + defm VPHSUBSW : SS3I_binop_rm_int<0x07, "vphsubsw", int_x86_ssse3_phsub_sw_128, 0>, VEX_4V; - defm VPMADDUBSW : SS3I_binop_rm_int<0x04, "vpmaddubsw", memopv16i8, + defm VPMADDUBSW : SS3I_binop_rm_int<0x04, "vpmaddubsw", int_x86_ssse3_pmadd_ub_sw_128, 0>, VEX_4V; - defm VPSHUFB : SS3I_binop_rm_int<0x00, "vpshufb", memopv16i8, + defm VPSHUFB : SS3I_binop_rm_int<0x00, "vpshufb", int_x86_ssse3_pshuf_b_128, 0>, VEX_4V; - defm VPSIGNB : SS3I_binop_rm_int<0x08, "vpsignb", memopv16i8, + defm VPSIGNB : SS3I_binop_rm_int<0x08, "vpsignb", int_x86_ssse3_psign_b_128, 0>, VEX_4V; - defm VPSIGNW : SS3I_binop_rm_int<0x09, "vpsignw", memopv8i16, + defm VPSIGNW : SS3I_binop_rm_int<0x09, "vpsignw", int_x86_ssse3_psign_w_128, 0>, VEX_4V; - defm VPSIGND : SS3I_binop_rm_int<0x0A, "vpsignd", memopv4i32, + defm VPSIGND : SS3I_binop_rm_int<0x0A, "vpsignd", int_x86_ssse3_psign_d_128, 0>, VEX_4V; } -defm VPMULHRSW : SS3I_binop_rm_int<0x0B, "vpmulhrsw", memopv8i16, +defm VPMULHRSW : SS3I_binop_rm_int<0x0B, "vpmulhrsw", int_x86_ssse3_pmul_hr_sw_128, 0>, VEX_4V; } let ImmT = NoImm, Predicates = [HasAVX2] in { let isCommutable = 0 in { - defm VPHADDW : SS3I_binop_rm_int_y<0x01, "vphaddw", memopv16i16, + defm VPHADDW : SS3I_binop_rm_int_y<0x01, "vphaddw", int_x86_avx2_phadd_w>, VEX_4V; - defm VPHADDD : SS3I_binop_rm_int_y<0x02, "vphaddd", memopv8i32, + defm VPHADDD : SS3I_binop_rm_int_y<0x02, "vphaddd", int_x86_avx2_phadd_d>, VEX_4V; - defm VPHADDSW : SS3I_binop_rm_int_y<0x03, "vphaddsw", memopv16i16, + defm VPHADDSW : SS3I_binop_rm_int_y<0x03, "vphaddsw", int_x86_avx2_phadd_sw>, VEX_4V; - defm VPHSUBW : SS3I_binop_rm_int_y<0x05, "vphsubw", memopv16i16, + defm VPHSUBW : SS3I_binop_rm_int_y<0x05, "vphsubw", int_x86_avx2_phsub_w>, VEX_4V; - defm VPHSUBD : SS3I_binop_rm_int_y<0x06, "vphsubd", memopv8i32, + defm VPHSUBD : SS3I_binop_rm_int_y<0x06, "vphsubd", int_x86_avx2_phsub_d>, VEX_4V; - defm VPHSUBSW : SS3I_binop_rm_int_y<0x07, "vphsubsw", memopv16i16, + defm VPHSUBSW : SS3I_binop_rm_int_y<0x07, "vphsubsw", int_x86_avx2_phsub_sw>, VEX_4V; - defm VPMADDUBSW : SS3I_binop_rm_int_y<0x04, "vpmaddubsw", memopv32i8, + defm VPMADDUBSW : SS3I_binop_rm_int_y<0x04, "vpmaddubsw", int_x86_avx2_pmadd_ub_sw>, VEX_4V; - defm VPSHUFB : SS3I_binop_rm_int_y<0x00, "vpshufb", memopv32i8, + defm VPSHUFB : SS3I_binop_rm_int_y<0x00, "vpshufb", int_x86_avx2_pshuf_b>, VEX_4V; - defm VPSIGNB : SS3I_binop_rm_int_y<0x08, "vpsignb", memopv32i8, + defm VPSIGNB : SS3I_binop_rm_int_y<0x08, "vpsignb", int_x86_avx2_psign_b>, VEX_4V; - defm VPSIGNW : SS3I_binop_rm_int_y<0x09, "vpsignw", memopv16i16, + defm VPSIGNW : SS3I_binop_rm_int_y<0x09, "vpsignw", int_x86_avx2_psign_w>, VEX_4V; - defm VPSIGND : SS3I_binop_rm_int_y<0x0A, "vpsignd", memopv8i32, + defm VPSIGND : SS3I_binop_rm_int_y<0x0A, "vpsignd", int_x86_avx2_psign_d>, VEX_4V; } -defm VPMULHRSW : SS3I_binop_rm_int_y<0x0B, "vpmulhrsw", memopv16i16, +defm VPMULHRSW : SS3I_binop_rm_int_y<0x0B, "vpmulhrsw", int_x86_avx2_pmul_hr_sw>, VEX_4V; } // None of these have i8 immediate fields. let ImmT = NoImm, Constraints = "$src1 = $dst" in { let isCommutable = 0 in { - defm PHADDW : SS3I_binop_rm_int<0x01, "phaddw", memopv8i16, + defm PHADDW : SS3I_binop_rm_int<0x01, "phaddw", int_x86_ssse3_phadd_w_128>; - defm PHADDD : SS3I_binop_rm_int<0x02, "phaddd", memopv4i32, + defm PHADDD : SS3I_binop_rm_int<0x02, "phaddd", int_x86_ssse3_phadd_d_128>; - defm PHADDSW : SS3I_binop_rm_int<0x03, "phaddsw", memopv8i16, + defm PHADDSW : SS3I_binop_rm_int<0x03, "phaddsw", int_x86_ssse3_phadd_sw_128>; - defm PHSUBW : SS3I_binop_rm_int<0x05, "phsubw", memopv8i16, + defm PHSUBW : SS3I_binop_rm_int<0x05, "phsubw", int_x86_ssse3_phsub_w_128>; - defm PHSUBD : SS3I_binop_rm_int<0x06, "phsubd", memopv4i32, + defm PHSUBD : SS3I_binop_rm_int<0x06, "phsubd", int_x86_ssse3_phsub_d_128>; - defm PHSUBSW : SS3I_binop_rm_int<0x07, "phsubsw", memopv8i16, + defm PHSUBSW : SS3I_binop_rm_int<0x07, "phsubsw", int_x86_ssse3_phsub_sw_128>; - defm PMADDUBSW : SS3I_binop_rm_int<0x04, "pmaddubsw", memopv16i8, + defm PMADDUBSW : SS3I_binop_rm_int<0x04, "pmaddubsw", int_x86_ssse3_pmadd_ub_sw_128>; - defm PSHUFB : SS3I_binop_rm_int<0x00, "pshufb", memopv16i8, + defm PSHUFB : SS3I_binop_rm_int<0x00, "pshufb", int_x86_ssse3_pshuf_b_128>; - defm PSIGNB : SS3I_binop_rm_int<0x08, "psignb", memopv16i8, + defm PSIGNB : SS3I_binop_rm_int<0x08, "psignb", int_x86_ssse3_psign_b_128>; - defm PSIGNW : SS3I_binop_rm_int<0x09, "psignw", memopv8i16, + defm PSIGNW : SS3I_binop_rm_int<0x09, "psignw", int_x86_ssse3_psign_w_128>; - defm PSIGND : SS3I_binop_rm_int<0x0A, "psignd", memopv4i32, + defm PSIGND : SS3I_binop_rm_int<0x0A, "psignd", int_x86_ssse3_psign_d_128>; } -defm PMULHRSW : SS3I_binop_rm_int<0x0B, "pmulhrsw", memopv8i16, +defm PMULHRSW : SS3I_binop_rm_int<0x0B, "pmulhrsw", int_x86_ssse3_pmul_hr_sw_128>; } @@ -6202,7 +6201,7 @@ !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), [(set VR128:$dst, (IntId128 - (bitconvert (memopv8i16 addr:$src))))]>, OpSize; + (bitconvert (memopv2i64 addr:$src))))]>, OpSize; } let Predicates = [HasAVX] in @@ -6228,7 +6227,7 @@ !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")), [(set VR128:$dst, (IntId128 VR128:$src1, - (bitconvert (memopv16i8 addr:$src2))))]>, OpSize; + (bitconvert (memopv2i64 addr:$src2))))]>, OpSize; } /// SS41I_binop_rm_int - Simple SSE 4.1 binary operator @@ -6244,7 +6243,7 @@ !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), [(set VR256:$dst, (IntId256 VR256:$src1, - (bitconvert (memopv32i8 addr:$src2))))]>, OpSize; + (bitconvert (memopv4i64 addr:$src2))))]>, OpSize; } let Predicates = [HasAVX] in { @@ -7245,7 +7244,8 @@ def rm : AVX8I, VEX_4V; + [(set RC:$dst, (IntVar RC:$src1, + (bitconvert (i_frag addr:$src2))))]>, VEX_4V; def ri : AVXAIi8; defm VPERMILPSY : avx_permil<0x0C, 0x04, "vpermilps", VR256, f256mem, i256mem, - memopv8f32, memopv8i32, + memopv8f32, memopv4i64, int_x86_avx_vpermilvar_ps_256, int_x86_avx_vpermil_ps_256>; } @@ -7494,11 +7494,12 @@ (ins VR256:$src1, i256mem:$src2), !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), - [(set VR256:$dst, (Int VR256:$src1, (mem_frag addr:$src2)))]>, + [(set VR256:$dst, (Int VR256:$src1, + (bitconvert (mem_frag addr:$src2))))]>, VEX_4V; } -defm VPERMD : avx2_perm<0x36, "vpermd", memopv8i32, int_x86_avx2_permd>; +defm VPERMD : avx2_perm<0x36, "vpermd", memopv4i64, int_x86_avx2_permd>; let ExeDomain = SSEPackedSingle in defm VPERMPS : avx2_perm<0x16, "vpermps", memopv8f32, int_x86_avx2_permps>; Modified: llvm/trunk/test/CodeGen/X86/avx-intrinsics-x86.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx-intrinsics-x86.ll?rev=145927&r1=145926&r2=145927&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/X86/avx-intrinsics-x86.ll (original) +++ llvm/trunk/test/CodeGen/X86/avx-intrinsics-x86.ll Tue Dec 6 03:04:59 2011 @@ -2333,6 +2333,12 @@ %res = call <4 x float> @llvm.x86.avx.vpermilvar.ps(<4 x float> %a0, <4 x i32> %a1) ; <<4 x float>> [#uses=1] ret <4 x float> %res } +define <4 x float> @test_x86_avx_vpermilvar_ps_load(<4 x float> %a0, <4 x i32>* %a1) { + ; CHECK: vpermilps + %a2 = load <4 x i32>* %a1 + %res = call <4 x float> @llvm.x86.avx.vpermilvar.ps(<4 x float> %a0, <4 x i32> %a2) ; <<4 x float>> [#uses=1] + ret <4 x float> %res +} declare <4 x float> @llvm.x86.avx.vpermilvar.ps(<4 x float>, <4 x i32>) nounwind readnone From stpworld at narod.ru Tue Dec 6 03:31:13 2011 From: stpworld at narod.ru (Stepan Dyatkovskiy) Date: Tue, 06 Dec 2011 13:31:13 +0400 Subject: [llvm-commits] [LLVM, SelectionDAG] fix for #9905: Failure in code selection for llvm intrinsics sqrt/exp In-Reply-To: References: <4ED74593.2030003@narod.ru> <4ED9D140.2070504@narod.ru> <4EDCC1A2.5010500@narod.ru> Message-ID: <4EDDE0E1.5060200@narod.ru> OK. Please look at reworked regression test patch in attachment. -Stepan. Eli Friedman wrote: > The code changes look fine. Please put all the FileCheck tests into > one file, and only use CHECK lines for the most important pieces > (specifically, that we call sinf etc.). > > -Eli > > On Mon, Dec 5, 2011 at 5:05 AM, Stepan Dyatkovskiy wrote: >> ping. >> >> -Stepan. >> >> Stepan Dyatkovskiy wrote: >>> ping. >>> >>> -Stepan >>> >>> Stepan Dyatkovskiy wrote: >>>> Hi all. Please find the patch and regression tests in attachment for >>>> review. >>>> This patch for ARM. It fixes selection for several instructions that >>>> works with v4f32 arguments: FSQRT, FSIN, FCOS, FPOWI, FPOW, FLOG, FLOG2, >>>> FLOG10, FEXP, FEXP2. >>>> I'm still worrying about FCOPYSIGN, FNEG, FABS, FCEIL, FTRUNC, FRINT, >>>> FNEARBYINT, FFLOOR. I could not found a way to add this instructions >>>> with v2f32 argument to DAG. It seems that it is impossible in ToT. So >>>> these instructions was not fixed. >>>> >>>> -Stepan. >>>> >>>> >>>> _______________________________________________ >>>> llvm-commits mailing list >>>> llvm-commits at cs.uiuc.edu >>>> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits >>> >>> _______________________________________________ >>> llvm-commits mailing list >>> llvm-commits at cs.uiuc.edu >>> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits >> >> _______________________________________________ >> llvm-commits mailing list >> llvm-commits at cs.uiuc.edu >> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits -------------- next part -------------- A non-text attachment was scrubbed... Name: 9905-regtests.patch Type: text/x-patch Size: 8994 bytes Desc: not available Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20111206/4ecb5e59/attachment.bin From craig.topper at gmail.com Tue Dec 6 03:31:36 2011 From: craig.topper at gmail.com (Craig Topper) Date: Tue, 06 Dec 2011 09:31:36 -0000 Subject: [llvm-commits] [llvm] r145929 - /llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Message-ID: <20111206093136.8D5D12A6C12C@llvm.org> Author: ctopper Date: Tue Dec 6 03:31:36 2011 New Revision: 145929 URL: http://llvm.org/viewvc/llvm-project?rev=145929&view=rev Log: Add X86ISD::HADD/HSUB to getTargetNodeName Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=145929&r1=145928&r2=145929&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original) +++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Tue Dec 6 03:31:36 2011 @@ -10891,6 +10891,8 @@ case X86ISD::ANDNP: return "X86ISD::ANDNP"; case X86ISD::PSIGN: return "X86ISD::PSIGN"; case X86ISD::BLENDV: return "X86ISD::BLENDV"; + case X86ISD::HADD: return "X86ISD::HADD"; + case X86ISD::HSUB: return "X86ISD::HSUB"; case X86ISD::FHADD: return "X86ISD::FHADD"; case X86ISD::FHSUB: return "X86ISD::FHSUB"; case X86ISD::FMAX: return "X86ISD::FMAX"; From stpworld at narod.ru Tue Dec 6 03:46:36 2011 From: stpworld at narod.ru (Stepan Dyatkovskiy) Date: Tue, 06 Dec 2011 13:46:36 +0400 Subject: [llvm-commits] [LLVM, SelectionDAG] fix for #9905: Failure in code selection for llvm intrinsics sqrt/exp In-Reply-To: <4EDDE0E1.5060200@narod.ru> References: <4ED74593.2030003@narod.ru> <4ED9D140.2070504@narod.ru> <4EDCC1A2.5010500@narod.ru> <4EDDE0E1.5060200@narod.ru> Message-ID: <4EDDE47C.4000905@narod.ru> Sorry for previous post. Forgot to remove extra newlines at the end of file. Fixed file is attached here. Thanks. -Stepan. Stepan Dyatkovskiy wrote: > OK. Please look at reworked regression test patch in attachment. > > -Stepan. > > Eli Friedman wrote: >> The code changes look fine. Please put all the FileCheck tests into >> one file, and only use CHECK lines for the most important pieces >> (specifically, that we call sinf etc.). >> >> -Eli >> >> On Mon, Dec 5, 2011 at 5:05 AM, Stepan Dyatkovskiy >> wrote: >>> ping. >>> >>> -Stepan. >>> >>> Stepan Dyatkovskiy wrote: >>>> ping. >>>> >>>> -Stepan >>>> >>>> Stepan Dyatkovskiy wrote: >>>>> Hi all. Please find the patch and regression tests in attachment for >>>>> review. >>>>> This patch for ARM. It fixes selection for several instructions that >>>>> works with v4f32 arguments: FSQRT, FSIN, FCOS, FPOWI, FPOW, FLOG, >>>>> FLOG2, >>>>> FLOG10, FEXP, FEXP2. >>>>> I'm still worrying about FCOPYSIGN, FNEG, FABS, FCEIL, FTRUNC, FRINT, >>>>> FNEARBYINT, FFLOOR. I could not found a way to add this instructions >>>>> with v2f32 argument to DAG. It seems that it is impossible in ToT. So >>>>> these instructions was not fixed. >>>>> >>>>> -Stepan. >>>>> >>>>> >>>>> _______________________________________________ >>>>> llvm-commits mailing list >>>>> llvm-commits at cs.uiuc.edu >>>>> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits >>>> >>>> _______________________________________________ >>>> llvm-commits mailing list >>>> llvm-commits at cs.uiuc.edu >>>> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits >>> >>> _______________________________________________ >>> llvm-commits mailing list >>> llvm-commits at cs.uiuc.edu >>> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits > > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits -------------- next part -------------- A non-text attachment was scrubbed... Name: 9905-regtests.patch Type: text/x-patch Size: 8988 bytes Desc: not available Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20111206/f2612608/attachment.bin From isanbard at gmail.com Tue Dec 6 04:22:55 2011 From: isanbard at gmail.com (Bill Wendling) Date: Tue, 06 Dec 2011 10:22:55 -0000 Subject: [llvm-commits] [www-releases] r145931 - in /www-releases/trunk/3.0: clang+llvm-3.0-i386-linux-debian.tar.gz clang+llvm-3.0-i386-linux-debian.tar.gz.sig clang+llvm-3.0-x86_64-linux-debian.tar.gz clang+llvm-3.0-x86_64-linux-debian.tar.gz.sig Message-ID: <20111206102255.BF2242A6C12C@llvm.org> Author: void Date: Tue Dec 6 04:22:55 2011 New Revision: 145931 URL: http://llvm.org/viewvc/llvm-project?rev=145931&view=rev Log: Remove extaneous '._foo' files. Modified: www-releases/trunk/3.0/clang+llvm-3.0-i386-linux-debian.tar.gz www-releases/trunk/3.0/clang+llvm-3.0-i386-linux-debian.tar.gz.sig www-releases/trunk/3.0/clang+llvm-3.0-x86_64-linux-debian.tar.gz www-releases/trunk/3.0/clang+llvm-3.0-x86_64-linux-debian.tar.gz.sig Modified: www-releases/trunk/3.0/clang+llvm-3.0-i386-linux-debian.tar.gz URL: http://llvm.org/viewvc/llvm-project/www-releases/trunk/3.0/clang%2Bllvm-3.0-i386-linux-debian.tar.gz?rev=145931&r1=145930&r2=145931&view=diff ============================================================================== Binary files - no diff available. Modified: www-releases/trunk/3.0/clang+llvm-3.0-i386-linux-debian.tar.gz.sig URL: http://llvm.org/viewvc/llvm-project/www-releases/trunk/3.0/clang%2Bllvm-3.0-i386-linux-debian.tar.gz.sig?rev=145931&r1=145930&r2=145931&view=diff ============================================================================== Binary files - no diff available. Modified: www-releases/trunk/3.0/clang+llvm-3.0-x86_64-linux-debian.tar.gz URL: http://llvm.org/viewvc/llvm-project/www-releases/trunk/3.0/clang%2Bllvm-3.0-x86_64-linux-debian.tar.gz?rev=145931&r1=145930&r2=145931&view=diff ============================================================================== Binary files - no diff available. Modified: www-releases/trunk/3.0/clang+llvm-3.0-x86_64-linux-debian.tar.gz.sig URL: http://llvm.org/viewvc/llvm-project/www-releases/trunk/3.0/clang%2Bllvm-3.0-x86_64-linux-debian.tar.gz.sig?rev=145931&r1=145930&r2=145931&view=diff ============================================================================== Binary files - no diff available. From grosser at fim.uni-passau.de Tue Dec 6 04:48:27 2011 From: grosser at fim.uni-passau.de (Tobias Grosser) Date: Tue, 06 Dec 2011 10:48:27 -0000 Subject: [llvm-commits] [polly] r145932 - /polly/trunk/lib/CodeGeneration.cpp Message-ID: <20111206104827.8413D2A6C12C@llvm.org> Author: grosser Date: Tue Dec 6 04:48:27 2011 New Revision: 145932 URL: http://llvm.org/viewvc/llvm-project?rev=145932&view=rev Log: CodeGen: Style improvements. Modified: polly/trunk/lib/CodeGeneration.cpp Modified: polly/trunk/lib/CodeGeneration.cpp URL: http://llvm.org/viewvc/llvm-project/polly/trunk/lib/CodeGeneration.cpp?rev=145932&r1=145931&r2=145932&view=diff ============================================================================== --- polly/trunk/lib/CodeGeneration.cpp (original) +++ polly/trunk/lib/CodeGeneration.cpp Tue Dec 6 04:48:27 2011 @@ -873,24 +873,28 @@ } /// @brief Create a classical sequential loop. - void codegenForSequential(const clast_for *f, Value *lowerBound = 0, - Value *upperBound = 0) { - APInt Stride = APInt_from_MPZ(f->stride); + void codegenForSequential(const clast_for *f, Value *LowerBound = 0, + Value *UpperBound = 0) { + APInt Stride; PHINode *IV; Value *IncrementedIV; - BasicBlock *AfterBB; + BasicBlock *AfterBB, *HeaderBB, *LastBodyBB; + Type *IntPtrTy; + + Stride = APInt_from_MPZ(f->stride); + IntPtrTy = TD->getIntPtrType(Builder.getContext()); + // The value of lowerbound and upperbound will be supplied, if this // function is called while generating OpenMP code. Otherwise get // the values. - assert(((lowerBound && upperBound) || (!lowerBound && !upperBound)) - && "Either give both bounds or none"); - if (lowerBound == 0 || upperBound == 0) { - lowerBound = ExpGen.codegen(f->LB, - TD->getIntPtrType(Builder.getContext())); - upperBound = ExpGen.codegen(f->UB, - TD->getIntPtrType(Builder.getContext())); + assert(!!LowerBound == !!UpperBound && "Either give both bounds or none"); + + if (LowerBound == 0) { + LowerBound = ExpGen.codegen(f->LB, IntPtrTy); + UpperBound = ExpGen.codegen(f->UB, IntPtrTy); } - createLoop(&Builder, lowerBound, upperBound, Stride, IV, AfterBB, + + createLoop(&Builder, LowerBound, UpperBound, Stride, IV, AfterBB, IncrementedIV, DT); // Add loop iv to symbols. @@ -902,8 +906,8 @@ // Loop is finished, so remove its iv from the live symbols. clastVars->erase(f->iterator); - BasicBlock *HeaderBB = *pred_begin(AfterBB); - BasicBlock *LastBodyBB = Builder.GetInsertBlock(); + HeaderBB = *pred_begin(AfterBB); + LastBodyBB = Builder.GetInsertBlock(); Builder.CreateBr(HeaderBB); IV->addIncoming(IncrementedIV, LastBodyBB); Builder.SetInsertPoint(AfterBB); From grosser at fim.uni-passau.de Tue Dec 6 04:48:32 2011 From: grosser at fim.uni-passau.de (Tobias Grosser) Date: Tue, 06 Dec 2011 10:48:32 -0000 Subject: [llvm-commits] [polly] r145933 - /polly/trunk/utils/checkout_cloog.sh Message-ID: <20111206104832.8C6A52A6C12C@llvm.org> Author: grosser Date: Tue Dec 6 04:48:32 2011 New Revision: 145933 URL: http://llvm.org/viewvc/llvm-project?rev=145933&view=rev Log: Update isl. Modified: polly/trunk/utils/checkout_cloog.sh Modified: polly/trunk/utils/checkout_cloog.sh URL: http://llvm.org/viewvc/llvm-project/polly/trunk/utils/checkout_cloog.sh?rev=145933&r1=145932&r2=145933&view=diff ============================================================================== --- polly/trunk/utils/checkout_cloog.sh (original) +++ polly/trunk/utils/checkout_cloog.sh Tue Dec 6 04:48:32 2011 @@ -1,7 +1,7 @@ #!/bin/sh CLOOG_HASH="63add93017c20f63455d67cf5127661dbb016d33" -ISL_HASH="addd6871b4f5049cc0cd8654d921717d1949633c" +ISL_HASH="0a2810732967eee50d8c55a371a28704d8a1ec17" PWD=`pwd` From benny.kra at googlemail.com Tue Dec 6 05:50:26 2011 From: benny.kra at googlemail.com (Benjamin Kramer) Date: Tue, 06 Dec 2011 11:50:26 -0000 Subject: [llvm-commits] [llvm] r145934 - in /llvm/trunk: include/llvm/Instruction.h lib/AsmParser/LLParser.cpp lib/Transforms/Scalar/LICM.cpp lib/VMCore/Metadata.cpp Message-ID: <20111206115026.C3CB22A6C12C@llvm.org> Author: d0k Date: Tue Dec 6 05:50:26 2011 New Revision: 145934 URL: http://llvm.org/viewvc/llvm-project?rev=145934&view=rev Log: Push StringRefs through the metadata interface. Modified: llvm/trunk/include/llvm/Instruction.h llvm/trunk/lib/AsmParser/LLParser.cpp llvm/trunk/lib/Transforms/Scalar/LICM.cpp llvm/trunk/lib/VMCore/Metadata.cpp Modified: llvm/trunk/include/llvm/Instruction.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Instruction.h?rev=145934&r1=145933&r2=145934&view=diff ============================================================================== --- llvm/trunk/include/llvm/Instruction.h (original) +++ llvm/trunk/include/llvm/Instruction.h Tue Dec 6 05:50:26 2011 @@ -143,7 +143,7 @@ /// getMetadata - Get the metadata of given kind attached to this Instruction. /// If the metadata is not found then return null. - MDNode *getMetadata(const char *Kind) const { + MDNode *getMetadata(StringRef Kind) const { if (!hasMetadata()) return 0; return getMetadataImpl(Kind); } @@ -168,7 +168,7 @@ /// node. This updates/replaces metadata if already present, or removes it if /// Node is null. void setMetadata(unsigned KindID, MDNode *Node); - void setMetadata(const char *Kind, MDNode *Node); + void setMetadata(StringRef Kind, MDNode *Node); /// setDebugLoc - Set the debug location information for this instruction. void setDebugLoc(const DebugLoc &Loc) { DbgLoc = Loc; } @@ -185,7 +185,7 @@ // These are all implemented in Metadata.cpp. MDNode *getMetadataImpl(unsigned KindID) const; - MDNode *getMetadataImpl(const char *Kind) const; + MDNode *getMetadataImpl(StringRef Kind) const; void getAllMetadataImpl(SmallVectorImpl > &)const; void getAllMetadataOtherThanDebugLocImpl(SmallVectorImpl > &) const; Modified: llvm/trunk/lib/AsmParser/LLParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/AsmParser/LLParser.cpp?rev=145934&r1=145933&r2=145934&view=diff ============================================================================== --- llvm/trunk/lib/AsmParser/LLParser.cpp (original) +++ llvm/trunk/lib/AsmParser/LLParser.cpp Tue Dec 6 05:50:26 2011 @@ -1064,7 +1064,7 @@ return TokError("expected metadata after comma"); std::string Name = Lex.getStrVal(); - unsigned MDK = M->getMDKindID(Name.c_str()); + unsigned MDK = M->getMDKindID(Name); Lex.Lex(); MDNode *Node; Modified: llvm/trunk/lib/Transforms/Scalar/LICM.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/LICM.cpp?rev=145934&r1=145933&r2=145934&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Scalar/LICM.cpp (original) +++ llvm/trunk/lib/Transforms/Scalar/LICM.cpp Tue Dec 6 05:50:26 2011 @@ -379,7 +379,7 @@ // in the same alias set as something that ends up being modified. if (AA->pointsToConstantMemory(LI->getOperand(0))) return true; - if (LI->getMetadata(LI->getContext().getMDKindID("invariant.load"))) + if (LI->getMetadata("invariant.load")) return true; // Don't hoist loads which have may-aliased stores in loop. Modified: llvm/trunk/lib/VMCore/Metadata.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/Metadata.cpp?rev=145934&r1=145933&r2=145934&view=diff ============================================================================== --- llvm/trunk/lib/VMCore/Metadata.cpp (original) +++ llvm/trunk/lib/VMCore/Metadata.cpp Tue Dec 6 05:50:26 2011 @@ -425,12 +425,12 @@ // Instruction Metadata method implementations. // -void Instruction::setMetadata(const char *Kind, MDNode *Node) { +void Instruction::setMetadata(StringRef Kind, MDNode *Node) { if (Node == 0 && !hasMetadata()) return; setMetadata(getContext().getMDKindID(Kind), Node); } -MDNode *Instruction::getMetadataImpl(const char *Kind) const { +MDNode *Instruction::getMetadataImpl(StringRef Kind) const { return getMetadataImpl(getContext().getMDKindID(Kind)); } From eugeni.stepanov at gmail.com Tue Dec 6 06:16:34 2011 From: eugeni.stepanov at gmail.com (Evgeniy Stepanov) Date: Tue, 6 Dec 2011 16:16:34 +0400 Subject: [llvm-commits] Fix constructor order on ARM/ELF In-Reply-To: References: <4ED53E4E.8060205@free.fr> Message-ID: Yes, at the moment we only preserve constructor order inside a translation unit. AFAIK, gcc emits multiple init_array. sections, and therefore preserves correct global constructor order. On Sun, Dec 4, 2011 at 4:49 PM, Anton Korobeynikov wrote: >> Side note: instead of emitting all the stuff into the same section, we >> can emit the symbol into e.g. init_array. section and rely >> on linker to emit all the stuff in the proper order. > Ok, it seems we have to *always* emit stuff this way. Consider e.g. > the following situation: > > File foo.o contains stuff with priorities of 100 & 200. We emit > everything into single init_array section. > File bar.o contains stuff with priorities of 150 & 250. We emit > everything into single init_array section. > > Surely after linking the order of ctors will be wrong. > > -- > With best regards, Anton Korobeynikov > Faculty of Mathematics and Mechanics, Saint Petersburg State University From baldrick at free.fr Tue Dec 6 10:05:12 2011 From: baldrick at free.fr (Duncan Sands) Date: Tue, 06 Dec 2011 16:05:12 -0000 Subject: [llvm-commits] [dragonegg] r145936 - /dragonegg/trunk/www/index.html Message-ID: <20111206160512.29E1C1BE003@llvm.org> Author: baldrick Date: Tue Dec 6 10:05:11 2011 New Revision: 145936 URL: http://llvm.org/viewvc/llvm-project?rev=145936&view=rev Log: Update for the new release (3.0). Modified: dragonegg/trunk/www/index.html Modified: dragonegg/trunk/www/index.html URL: http://llvm.org/viewvc/llvm-project/dragonegg/trunk/www/index.html?rev=145936&r1=145935&r2=145936&view=diff ============================================================================== --- dragonegg/trunk/www/index.html (original) +++ dragonegg/trunk/www/index.html Tue Dec 6 10:05:11 2011 @@ -14,12 +14,15 @@

    DragonEgg is a - gcc plugin dragonegg.so - that replaces gcc's optimizers and code generators with those from the - LLVM project.

    -

    It is a reimplementation of - llvm-gcc - that works with gcc-4.5 or later.

    + gcc plugin that replaces GCC's + optimizers and code generators with those from the + LLVM project. It works with + gcc-4.5 or + gcc-4.6, + targets the x86-32 and x86-64 processor families, and has been successfully + used on the Darwin, FreeBSD, KFreeBSD, Linux and OpenBSD platforms. It fully + supports Ada, C, C++ and Fortran. It has partial support for Go, Java, Obj-C + and Obj-C++.


    @@ -28,8 +31,7 @@
      -
    • Work with unmodified gcc
      • -
    • Support all gcc languages
      • +
    • Fully support all GCC languages
    @@ -37,35 +39,42 @@
      -
    • C works well, for example you can build a working gcc using it.
      • -
    • C++ works fairly well, for example you can build LLVM, clang and boost - with it (the resulting LLVM and clang work correctly; boost mostly works but - there are some mysterious failures).
      • -
    • Fortran works fairly well, for example SPEC CPU mostly compiles and works, - but there are some failures. These have all been fixed in the development - version.
      • -
    • It can compile quite a lot of Ada, and the compiled code mostly seems to - work.
      • -
    • It can compile a small amount of Obj-C and Obj-C++.
      • +
    • Fortran works very well. Ada, C and C++ also work well.
      • +
    • It can compile a reasonable amount of Obj-C, Obj-C++ and Go.
    • It can compile simple Java programs, but they don't execute properly (this is a consequence of the java front-end not supporting GCC's LTO).
      • -
    • Limited debug info.
      • -
    • Versions 2.9 and earlier require patching gcc (the development version - does not).
      • -
    • Only supports x86-32 and x86-64.
      • -
    • Only supports linux, darwin and freebsd (additional gcc patches may be - needed on darwin, see the README file). +
    • Debug info is poor.
    -

    DragonEgg is not mature - while it works quite well, it should not be - considered production quality.

    -

    Releases

      -

    • DragonEgg-2.9 is the most recent +

    • DragonEgg-3.0 is the most recent + DragonEgg release. It requires + LLVM-3.0 and + gcc-4.5 or + gcc-4.6. +

      The 3.0 release has the following notable changes:

      +
        +
      • GCC version 4.6 is now fully supported.
        • + +
      • Patching and building GCC is no longer required: the plugin should work + with your system GCC (version 4.5 or 4.6; on Debian/Ubuntu systems the + gcc-4.5-plugin-dev or gcc-4.6-plugin-dev package is also needed).
        • + +
      • The -fplugin-arg-dragonegg-enable-gcc-optzns option, which runs + GCC's optimizers as well as LLVM's, now works much better. This is the + option to use if you want ultimate performance! It is still experimental + though: it may cause the plugin to crash. Setting the optimization level + to -O4 when using this option will optimize even harder, though + this usually doesn't result in any improvement over -O3.
        • + +
      • The type and constant conversion logic has been almost entirely rewritten, + fixing a multitude of obscure bugs.
        • +
      +

    • DragonEgg-2.9 was the third DragonEgg release. It requires LLVM-2.9 and gcc-4.5.

      @@ -237,39 +246,33 @@

      Get the - DragonEgg-2.9 source code: - 

      	wget http://llvm.org/releases/2.9/dragonegg-2.9.tgz
      + DragonEgg-3.0 source code: + 
      	wget http://llvm.org/releases/3.0/dragonegg-3.0.tgz

      Unpack it:

      - 
      	tar xzf dragonegg-2.9.tgz
      -

      Download the - LLVM-2.9 binaries - (mysteriously referred to as clang binaries) for your platform and install - them.

      -

      Get the gcc-4.5 source code:

      - 
      	wget http://mirrors.kernel.org/gnu/gcc/gcc-4.5.2/gcc-4.5.2.tar.gz
      -

      Unpack it:

      - 
      	tar xzf gcc-4.5.2.tar.gz
      -

      Apply the patch in dragonegg-2.9/gcc-patches/ to the gcc-4.5 - source:

      - 
      	patch -d gcc-4.5.2 -p1 < dragonegg-2.9/gcc-patches/i386_static.diff
      -

      Build and install gcc-4.5 in the - usual way, except that you should add the configure options --enable-plugin - and --enable-lto.

      + 
      	tar xzf dragonegg-3.0.tgz
      +

      Install version 3.0 of LLVM, for example by downloading and installing the + LLVM-3.0 binaries + (mysteriously referred to as clang binaries) for your platform.

      +

      Make sure you have gcc-4.5 or + gcc-4.6 installed (you do not need + to build your own copy). On Debian and Ubuntu linux systems you also need to + install the gcc-4.5-plugin-dev or gcc-4.6-plugin-dev + package, as appropriate.

      Doing

      - 
      	GCC=directory_where_gcc_installed/bin/gcc make
      -

      in the dragonegg-2.9 directory should then build dragonegg.so. - If you have arranged for the gcc executable to occur in your path with the - name gcc-4.5 (using a symbolic link for example) then there is no - need to set the GCC variable: you can just do "make". - If the LLVM binaries are not in your path then you can use

      - 
      	GCC=directory_where_gcc_installed/bin/gcc LLVM_CONFIG=directory_where_llvm_installed/bin/llvm-config make
      + 
      	GCC=gcc-4.6 make
      +

      (if using gcc-4.6), or

      + 
      	GCC=gcc-4.5 make
      +

      (if using gcc-4.5) in the dragonegg-3.0 directory should then + build dragonegg.so. If the LLVM binaries are not in your path then + you can use

      + 
      	GCC=gcc-4.6 LLVM_CONFIG=directory_where_llvm_installed/bin/llvm-config make

      If you only built LLVM and did not install it then you can still build dragonegg by setting LLVM_CONFIG to point to the copy of llvm-config in the build tree.

      -

      To use dragonegg.so, compile something with your just-installed - version of gcc, adding -fplugin=path_to_dragonegg/dragonegg.so - to the command line. See the README file for more details and useful - command line options.

      +

      To use dragonegg.so, compile something with gcc-4.5/gcc-4.6, + adding -fplugin=path_to_dragonegg/dragonegg.so to the command line. + See the README file for more details and useful command line + options.

      Getting the development version

      From benny.kra at googlemail.com Tue Dec 6 10:14:29 2011 From: benny.kra at googlemail.com (Benjamin Kramer) Date: Tue, 06 Dec 2011 16:14:29 -0000 Subject: [llvm-commits] [llvm] r145937 - /llvm/trunk/lib/Transforms/Utils/Local.cpp Message-ID: <20111206161430.3F7E61BE003@llvm.org> Author: d0k Date: Tue Dec 6 10:14:29 2011 New Revision: 145937 URL: http://llvm.org/viewvc/llvm-project?rev=145937&view=rev Log: Simplify common predecessor finding. - Walking over pred_begin/pred_end is an expensive operation. - PHINodes contain a value for each predecessor anyway. - While it may look like we used to save a few iterations with the set, be aware that getIncomingValueForBlock does a linear search on the values of the phi node. - Another -5% on ARMDisassembler.cpp (Release build). This was the last entry in the profile that was obviously wasting time. Modified: llvm/trunk/lib/Transforms/Utils/Local.cpp Modified: llvm/trunk/lib/Transforms/Utils/Local.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Utils/Local.cpp?rev=145937&r1=145936&r2=145937&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Utils/Local.cpp (original) +++ llvm/trunk/lib/Transforms/Utils/Local.cpp Tue Dec 6 10:14:29 2011 @@ -494,22 +494,8 @@ if (Succ->getSinglePredecessor()) return true; // Make a list of the predecessors of BB - typedef SmallPtrSet BlockSet; - BlockSet BBPreds(pred_begin(BB), pred_end(BB)); + SmallPtrSet BBPreds(pred_begin(BB), pred_end(BB)); - // Use that list to make another list of common predecessors of BB and Succ - BlockSet CommonPreds; - for (pred_iterator PI = pred_begin(Succ), PE = pred_end(Succ); - PI != PE; ++PI) { - BasicBlock *P = *PI; - if (BBPreds.count(P)) - CommonPreds.insert(P); - } - - // Shortcut, if there are no common predecessors, merging is always safe - if (CommonPreds.empty()) - return true; - // Look at all the phi nodes in Succ, to see if they present a conflict when // merging these blocks for (BasicBlock::iterator I = Succ->begin(); isa(I); ++I) { @@ -520,28 +506,28 @@ // merge the phi nodes and then the blocks can still be merged PHINode *BBPN = dyn_cast(PN->getIncomingValueForBlock(BB)); if (BBPN && BBPN->getParent() == BB) { - for (BlockSet::iterator PI = CommonPreds.begin(), PE = CommonPreds.end(); - PI != PE; PI++) { - if (BBPN->getIncomingValueForBlock(*PI) - != PN->getIncomingValueForBlock(*PI)) { + for (unsigned PI = 0, PE = PN->getNumIncomingValues(); PI != PE; ++PI) { + BasicBlock *IBB = PN->getIncomingBlock(PI); + if (BBPreds.count(IBB) && + BBPN->getIncomingValueForBlock(IBB) != PN->getIncomingValue(PI)) { DEBUG(dbgs() << "Can't fold, phi node " << PN->getName() << " in " << Succ->getName() << " is conflicting with " << BBPN->getName() << " with regard to common predecessor " - << (*PI)->getName() << "\n"); + << IBB->getName() << "\n"); return false; } } } else { Value* Val = PN->getIncomingValueForBlock(BB); - for (BlockSet::iterator PI = CommonPreds.begin(), PE = CommonPreds.end(); - PI != PE; PI++) { + for (unsigned PI = 0, PE = PN->getNumIncomingValues(); PI != PE; ++PI) { // See if the incoming value for the common predecessor is equal to the // one for BB, in which case this phi node will not prevent the merging // of the block. - if (Val != PN->getIncomingValueForBlock(*PI)) { + BasicBlock *IBB = PN->getIncomingBlock(PI); + if (BBPreds.count(IBB) && Val != PN->getIncomingValue(PI)) { DEBUG(dbgs() << "Can't fold, phi node " << PN->getName() << " in " << Succ->getName() << " is conflicting with regard to common " - << "predecessor " << (*PI)->getName() << "\n"); + << "predecessor " << IBB->getName() << "\n"); return false; } } From glider at google.com Tue Dec 6 05:04:08 2011 From: glider at google.com (Alexander Potapenko) Date: Tue, 6 Dec 2011 15:04:08 +0400 Subject: [llvm-commits] AddressSanitizer GCD tests on Mac: prevent optimization, enable. In-Reply-To: References: Message-ID: Including asan_test_utils.h is not possible, because 'extern "C"' and 'template' is not valid ObjC code. Let it be volatile, otherwise we'll need to write a separate asan_test_utils for ObjC, which'll be an overkill. On Mon, Dec 5, 2011 at 11:04 PM, Kostya Serebryany wrote: > I wonder if you can reuse?Ident() from?tests/asan_test_utils.h instead of > using volatile. > Like this: > ? char *mem = Ident(malloc(10)); > > // This function returns its parameter but in such a way that compiler > > > // can not prove it. > > > template > > > __attribute__((noinline)) > > > static T Ident(T t) { > ... > > > --kcc > > > On Mon, Dec 5, 2011 at 12:44 AM, Alexander Potapenko > wrote: >> >> Fix GCD tests for AddressSanitizer on Mac. >> The following patch declares the char* vars holding the memory >> allocations as volatile, which prevents the compiler from optimizing >> them and breaking the tests. >> I'm also enabling the tests by default, as the GCD support in ASan >> runtime library is quite stable already. >> >> -- >> Alexander Potapenko >> Software Engineer >> Google Moscow > > -- Alexander Potapenko Software Engineer Google Moscow From victor.umansky at intel.com Tue Dec 6 02:52:21 2011 From: victor.umansky at intel.com (Umansky, Victor) Date: Tue, 6 Dec 2011 10:52:21 +0200 Subject: [llvm-commits] x86 branch sequence optimization in LLVM code gen: please review In-Reply-To: References: <021AD592C708E24FA11FD214489EC9BE0123F25260@hasmsx501.ger.corp.intel.com> Message-ID: <021AD592C708E24FA11FD214489EC9BE0123F95DDF@hasmsx501.ger.corp.intel.com> Hi Bruno, Thank you for the response. I've changed the LIT test towards common look (attached). Unfortunately, I cannot put it inside brcond.ll because the "ptest" instruction was introduced only with SSE4.1 (i.e. requires "-mcpu=penryn"), while the current version of brcond.ll is processed with "-mcpu=core2". Will the replacement of-mcpu in brcond.ll with "penryn" be backward-compat with regard to LIT results? Best Regards, Victor From: Bruno Cardoso Lopes [mailto:bruno.cardoso at gmail.com] Sent: Monday, December 05, 2011 19:13 To: Umansky, Victor Cc: llvm-commits at cs.uiuc.edu Subject: Re: [llvm-commits] x86 branch sequence optimization in LLVM code gen: please review Hi Victor, On Mon, Dec 5, 2011 at 10:26 AM, Umansky, Victor > wrote: Hi, My name is Victor Umansky; I'm an engineer in Intel OpenCL Team. The attached patch contains an optimization of ptest-conditioned branch. I.e., the following LLVM IR code %res = call i32 @llvm.x86.sse41.ptestz(<4 x float> %a, <4 x float> %a) nounwind %tmp = and i32 %res, 1 %one = icmp eq i32 %tmp, 0 br i1 %one, label %label1, label %label2 ends with the following x86 machine code sequence: ptest XMM3, XMM3 sete AL movzx EAX, AL test EAX, EAX jne LBB18_26 which can be optimized to: ptest XMM3, XMM3 je LBB18_26 The current machine code sequence stems from the need to coordinate i32 return type from the ptestz intrinsic with i1 condition type for branch IR instruction. Consequently we can optimize it in x86 codegen backend where the both condition producer (ptest) amd consumer (jcc) use the same x86 EFLAGS register, and thus in-between conversions of the condition can be quietly dropped. The optimization is focused on x86 DAG combining (post-legalization stage) which recognizes the sequence and converts it to the minimized one. The attached patch file includes both the x86 backend instruction combining modification and a LIT regression test for it. I'd like to commit the fix to the LLVM trunk, and your feedback will be mostly appreciated. +; RUN: llc %s -march=x86-64 -mcpu=corei7 -o %t.asm +; RUN: FileCheck %s --input-file=%t.asm Please do like the other tests, and read the file with "< %s". Also, place it under test/CodeGen/X86/brcond.ll -- Bruno Cardoso Lopes http://www.brunocardoso.cc --------------------------------------------------------------------- Intel Israel (74) Limited This e-mail and any attachments may contain confidential material for the sole use of the intended recipient(s). Any review or distribution by others is strictly prohibited. If you are not the intended recipient, please contact the sender and delete all copies. -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20111206/4dcda820/attachment.html -------------- next part -------------- A non-text attachment was scrubbed... Name: ptest_sequence.ll Type: application/octet-stream Size: 837 bytes Desc: ptest_sequence.ll Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20111206/4dcda820/attachment.obj From stpworld at narod.ru Tue Dec 6 14:39:17 2011 From: stpworld at narod.ru (Stepan Dyatkovskiy) Date: Wed, 07 Dec 2011 00:39:17 +0400 Subject: [llvm-commits] [LLVM, SwitchInst, case ranges] Auxiliary patch #1 In-Reply-To: <4EB7C319.1000709@narod.ru> References: <4EAA9B5D.802@narod.ru> <4EAA9DE8.80000@free.fr> <485181319805488@web67.yandex.ru> <4EAB079D.6000606@free.fr> <4EB18F12.6060409@narod.ru> <4EB7C319.1000709@narod.ru> Message-ID: <4EDE7D75.704@narod.ru> ping. -Stepan. Stepan Dyatkovskiy wrote: > ping. > -Stepan. > > Stepan Dyatkovskiy wrote: >> Hello, Duncan. >> >> Duncan Sands wrote: >> > I guess Anton can comment on codegen, but the fact that it doesn't make >> > codegen >> > harder has nothing to do with increasing the complexity of the >> > optimizers, since >> > they work at the IR level. It may be that case ranges allow the >> > optimizers to >> > do a better job. It may be that they simplify the optimizers. But it >> > also may >> > be the opposite: they might make switches harder to work with and reason >> > about >> > for no advantage. Which is it? Do you have an example where case ranges >> > would >> > result in better code, or make it easier to produce better code? >> >> I made impact analysis for new case ranges feature. >> 24 out of more than 100 optimizations are affected. 20 of 24 just >> require an integration of a new "case-range" type, i.e. small change of >> code without. The remaining 4 requires some bigger changes. All affected >> optimizers are listed in attached spreadsheet. >> >> Patches that are submitted in this branch are just functionality >> extension for current classes. These patches doesn't brake any of >> existing optimizations and keeps its speed without changes. >> >> Well. Let's enumerate 4 optimizations that should be reworked. >> >> 1. LowerSwitch::Clusterify >> >> This method groups neighbouring cases (by value) that goes to the same >> destination. >> >> For example: >> >> switch i32 %cond, label %default [ >> i32 1, label %successorA >> i32 2, label %successorA >> i32 5, label %successorB >> i32 3, label %successorA >> i32 6, label %successorB >> ] >> >> will be grouped to the two clusters: >> >> [[i32 1] .. [i32 3]], label %successorA >> [[i32 5] .. [i32 6]], label %successorB >> >> This method will work faster if clusters will presented explicitly using >> new case ranges feature. >> >> 2. SimplifyCFG.cpp, TurnSwitchRangeIntoICmp (static function) >> >> "Turns a switch that contains only an integer range comparison into a >> sub, an icmp and a branch." (written in method comments). Algorithm that >> determines "solid" case range should be changed. >> >> Now compare two switches (don't look at syntax of second switch, it is >> still a subject of another discussion): >> >> switch i32 %cond, label %default [ >> i32 1, label %successorA >> i32 2, label %successorA >> i32 3, label %successorA >> ] >> >> and hypothetical switch: >> >> switch i32 %cond, label %default [ >> [[i32 1],[i32 3]], label %successorA ; case range [1..3] >> ] >> >> or even this one: >> >> switch i32 %cond, label %default [ >> [[i32 1],[i32 2]], label %successorA ; case range [1..2] >> i32 3, label %successorA ; single case value "3" >> ] >> >> Its obvious that last two switches will be processed faster than the >> first one. We doesn't need to perform analysis for each separated case >> value. We already know - that it is a range. >> >> 3. SimplifyCFG.cpp, EliminateDeadSwitchCases (static function). >> >> Here switch condition is analysed. We try to determine "1" and "0" bits >> that MUST be in condition value. If we found them, then we look at case >> values; if these bits are absent in case value we remove it since it >> will be never equal to condition. >> I need to think more about the ways of case ranges processing here. At >> least we can represent case range as separated values set and apply >> current algorithm to it. It slow down the processing a little bit, but >> the complexity itself will be not increased. I'm sure that there are >> also exists algorithms that allows to eliminate whole case ranges: e.g. >> we can apply current algorithm to high bits that are constant in case >> range. >> >> 4. lib/Transforms/Scalar/LoopUnswitch.cpp (the set of methods). >> >> Just a quote from LoopUnswitch.cpp header >> >> [quote] >> This pass transforms loops that contain branches on loop-invariant >> conditions >> to have multiple loops. For example, it turns the left into the right code. >> >> for (...) if (lic) >> A for (...) >> if (lic) A; B; C >> B else >> C for (...) >> A; C >> [/quote] >> >> I also must think more about case ranges unswithing here. >> By now loops with switch instruction are unswitched value-by-value. >> There is no any case-values clustering before unswitching. For example >> for case range [0..9] we need to run unswitch process 10 times! >> Theoretically, explicitly given case ranges and properly implemented >> unswitching should make this optimization better. >> >> So, as you can see complexity will not changed and even some of >> optimizations will work faster. >> >> Regards, >> Stepan. >> >> >> _______________________________________________ >> llvm-commits mailing list >> llvm-commits at cs.uiuc.edu >> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From mcrosier at apple.com Tue Dec 6 11:39:49 2011 From: mcrosier at apple.com (Chad Rosier) Date: Tue, 06 Dec 2011 09:39:49 -0800 Subject: [llvm-commits] [llvm] r145912 - in /llvm/trunk/lib/Target/Mips: MipsInstrFormats.td MipsInstrInfo.cpp MipsInstrInfo.td In-Reply-To: <20111206033449.22EBB2A6C12C@llvm.org> References: <20111206033449.22EBB2A6C12C@llvm.org> Message-ID: Did the test case ever land? Chad On Dec 5, 2011, at 7:34 PM, Bruno Cardoso Lopes wrote: > Author: bruno > Date: Mon Dec 5 21:34:48 2011 > New Revision: 145912 > > URL: http://llvm.org/viewvc/llvm-project?rev=145912&view=rev > Log: > Use branches instead of jumps + variable cleanup. Testcase coming next. Patch by Jack Carter > > Modified: > llvm/trunk/lib/Target/Mips/MipsInstrFormats.td > llvm/trunk/lib/Target/Mips/MipsInstrInfo.cpp > llvm/trunk/lib/Target/Mips/MipsInstrInfo.td > > Modified: llvm/trunk/lib/Target/Mips/MipsInstrFormats.td > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsInstrFormats.td?rev=145912&r1=145911&r2=145912&view=diff > ============================================================================== > --- llvm/trunk/lib/Target/Mips/MipsInstrFormats.td (original) > +++ llvm/trunk/lib/Target/Mips/MipsInstrFormats.td Mon Dec 5 21:34:48 2011 > @@ -115,7 +115,7 @@ > let Inst{15-0} = imm16; > } > > -class CBranchBase op, dag outs, dag ins, string asmstr, > +class BranchBase op, dag outs, dag ins, string asmstr, > list pattern, InstrItinClass itin>: > MipsInst > { > > Modified: llvm/trunk/lib/Target/Mips/MipsInstrInfo.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsInstrInfo.cpp?rev=145912&r1=145911&r2=145912&view=diff > ============================================================================== > --- llvm/trunk/lib/Target/Mips/MipsInstrInfo.cpp (original) > +++ llvm/trunk/lib/Target/Mips/MipsInstrInfo.cpp Mon Dec 5 21:34:48 2011 > @@ -236,7 +236,7 @@ > Opc == Mips::BGEZ || Opc == Mips::BLTZ || Opc == Mips::BLEZ || > Opc == Mips::BEQ64 || Opc == Mips::BNE64 || Opc == Mips::BGTZ64 || > Opc == Mips::BGEZ64 || Opc == Mips::BLTZ64 || Opc == Mips::BLEZ64 || > - Opc == Mips::BC1T || Opc == Mips::BC1F || Opc == Mips::J) ? > + Opc == Mips::BC1T || Opc == Mips::BC1F || Opc == Mips::B) ? > Opc : 0; > } > > @@ -320,7 +320,7 @@ > // If there is only one terminator instruction, process it. > if (!SecondLastOpc) { > // Unconditional branch > - if (LastOpc == Mips::J) { > + if (LastOpc == Mips::B) { > TBB = LastInst->getOperand(0).getMBB(); > return false; > } > @@ -337,7 +337,7 @@ > > // If second to last instruction is an unconditional branch, > // analyze it and remove the last instruction. > - if (SecondLastOpc == Mips::J) { > + if (SecondLastOpc == Mips::B) { > // Return if the last instruction cannot be removed. > if (!AllowModify) > return true; > @@ -349,7 +349,7 @@ > > // Conditional branch followed by an unconditional branch. > // The last one must be unconditional. > - if (LastOpc != Mips::J) > + if (LastOpc != Mips::B) > return true; > > AnalyzeCondBr(SecondLastInst, SecondLastOpc, TBB, Cond); > @@ -391,14 +391,14 @@ > // Two-way Conditional branch. > if (FBB) { > BuildCondBr(MBB, TBB, DL, Cond); > - BuildMI(&MBB, DL, get(Mips::J)).addMBB(FBB); > + BuildMI(&MBB, DL, get(Mips::B)).addMBB(FBB); > return 2; > } > > // One way branch. > // Unconditional branch. > if (Cond.empty()) > - BuildMI(&MBB, DL, get(Mips::J)).addMBB(TBB); > + BuildMI(&MBB, DL, get(Mips::B)).addMBB(TBB); > else // Conditional branch. > BuildCondBr(MBB, TBB, DL, Cond); > return 1; > > Modified: llvm/trunk/lib/Target/Mips/MipsInstrInfo.td > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsInstrInfo.td?rev=145912&r1=145911&r2=145912&view=diff > ============================================================================== > --- llvm/trunk/lib/Target/Mips/MipsInstrInfo.td (original) > +++ llvm/trunk/lib/Target/Mips/MipsInstrInfo.td Mon Dec 5 21:34:48 2011 > @@ -380,21 +380,13 @@ > let isPseudo = Pseudo; > } > > -// Memory Load/Store > +// Unaligned Memory Load/Store > let canFoldAsLoad = 1 in > -class LoadX op, RegisterClass RC, > - Operand MemOpnd>: > - FMem - "", > - [], IILoad> { > -} > +class LoadUnAlign op, RegisterClass RC, Operand MemOpnd>: > + FMem {} > > -class StoreX op, RegisterClass RC, > - Operand MemOpnd>: > - FMem - "", > - [], IIStore> { > -} > +class StoreUnAlign op, RegisterClass RC, Operand MemOpnd>: > + FMem {} > > // 32-bit load. > multiclass LoadM32 op, string instr_asm, PatFrag OpNode, > @@ -415,10 +407,10 @@ > } > > // 32-bit load. > -multiclass LoadX32 op> { > - def #NAME# : LoadX, > +multiclass LoadUnAlign32 op> { > + def #NAME# : LoadUnAlign, > Requires<[NotN64]>; > - def _P8 : LoadX, > + def _P8 : LoadUnAlign, > Requires<[IsN64]>; > } > // 32-bit store. > @@ -440,18 +432,18 @@ > } > > // 32-bit store. > -multiclass StoreX32 op> { > - def #NAME# : StoreX, > +multiclass StoreUnAlign32 op> { > + def #NAME# : StoreUnAlign, > Requires<[NotN64]>; > - def _P8 : StoreX, > + def _P8 : StoreUnAlign, > Requires<[IsN64]>; > } > > // Conditional Branch > class CBranch op, string instr_asm, PatFrag cond_op, RegisterClass RC>: > - CBranchBase - !strconcat(instr_asm, "\t$rs, $rt, $imm16"), > - [(brcond (i32 (cond_op RC:$rs, RC:$rt)), bb:$imm16)], IIBranch> { > + BranchBase + !strconcat(instr_asm, "\t$rs, $rt, $imm16"), > + [(brcond (i32 (cond_op RC:$rs, RC:$rt)), bb:$imm16)], IIBranch> { > let isBranch = 1; > let isTerminator = 1; > let hasDelaySlot = 1; > @@ -459,9 +451,9 @@ > > class CBranchZero op, bits<5> _rt, string instr_asm, PatFrag cond_op, > RegisterClass RC>: > - CBranchBase - !strconcat(instr_asm, "\t$rs, $imm16"), > - [(brcond (i32 (cond_op RC:$rs, 0)), bb:$imm16)], IIBranch> { > + BranchBase + !strconcat(instr_asm, "\t$rs, $imm16"), > + [(brcond (i32 (cond_op RC:$rs, 0)), bb:$imm16)], IIBranch> { > let rt = _rt; > let isBranch = 1; > let isTerminator = 1; > @@ -486,10 +478,16 @@ > IIAlu>; > > // Unconditional branch > -let isBranch=1, isTerminator=1, isBarrier=1, hasDelaySlot = 1 in > -class JumpFJ op, string instr_asm>: > - FJ - !strconcat(instr_asm, "\t$target"), [(br bb:$target)], IIBranch>; > +class UncondBranch op, string instr_asm>: > + BranchBase + !strconcat(instr_asm, "\t$imm16"), [(br bb:$imm16)], IIBranch> { > + let rs = 0; > + let rt = 0; > + let isBranch = 1; > + let isTerminator = 1; > + let isBarrier = 1; > + let hasDelaySlot = 1; > +} > > let isBranch=1, isTerminator=1, isBarrier=1, rd=0, hasDelaySlot = 1, > isIndirectBranch = 1 in > @@ -810,10 +808,10 @@ > defm USW : StoreM32<0x2b, "usw", store_u, 1>; > > /// Primitives for unaligned > -defm LWL : LoadX32<0x22>; > -defm LWR : LoadX32<0x26>; > -defm SWL : StoreX32<0x2A>; > -defm SWR : StoreX32<0x2E>; > +defm LWL : LoadUnAlign32<0x22>; > +defm LWR : LoadUnAlign32<0x26>; > +defm SWL : StoreUnAlign32<0x2A>; > +defm SWR : StoreUnAlign32<0x2E>; > > let hasSideEffects = 1 in > def SYNC : MipsInst<(outs), (ins i32imm:$stype), "sync $stype", > @@ -833,10 +831,10 @@ > def SC_P8 : SCBase<0x38, "sc", CPURegs, mem64>, Requires<[IsN64]>; > > /// Jump and Branch Instructions > -def J : JumpFJ<0x02, "j">; > def JR : JumpFR<0x00, 0x08, "jr", CPURegs>; > def JAL : JumpLink<0x03, "jal">; > def JALR : JumpLinkReg<0x00, 0x09, "jalr">; > +def B : UncondBranch<0x04, "b">; > def BEQ : CBranch<0x04, "beq", seteq, CPURegs>; > def BNE : CBranch<0x05, "bne", setne, CPURegs>; > def BGEZ : CBranchZero<0x01, 1, "bgez", setge, CPURegs>; > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From isanbard at gmail.com Tue Dec 6 13:09:06 2011 From: isanbard at gmail.com (Bill Wendling) Date: Tue, 06 Dec 2011 19:09:06 -0000 Subject: [llvm-commits] [llvm] r145952 - /llvm/trunk/lib/Target/X86/X86FrameLowering.cpp Message-ID: <20111206190906.85C811BE003@llvm.org> Author: void Date: Tue Dec 6 13:09:06 2011 New Revision: 145952 URL: http://llvm.org/viewvc/llvm-project?rev=145952&view=rev Log: For a small sized stack, we encode that value directly with no "stack adjust" value. Modified: llvm/trunk/lib/Target/X86/X86FrameLowering.cpp Modified: llvm/trunk/lib/Target/X86/X86FrameLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86FrameLowering.cpp?rev=145952&r1=145951&r2=145952&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86FrameLowering.cpp (original) +++ llvm/trunk/lib/Target/X86/X86FrameLowering.cpp Tue Dec 6 13:09:06 2011 @@ -565,7 +565,7 @@ if ((FullOffset & 0xFF) == FullOffset) { // Frameless stack. CompactUnwindEncoding |= 0x02000000; - CompactUnwindEncoding |= (FullOffset & 0xFF) << 16; + CompactUnwindEncoding |= (CFAOffset & 0xFF) << 16; } else { if ((CFAOffset & 0x7) != CFAOffset) // The extra stack adjustments are too big for us to handle. @@ -582,6 +582,8 @@ CompactUnwindEncoding |= (CFAOffset & 0x7) << 13; } + CompactUnwindEncoding |= ((6 - SavedRegIdx) & 0x7) << 10; + // Get the encoding of the saved registers when we don't have a frame // pointer. uint32_t RegEnc = encodeCompactUnwindRegistersWithoutFrame(SavedRegs, From daniel at zuster.org Tue Dec 6 12:25:42 2011 From: daniel at zuster.org (Daniel Dunbar) Date: Tue, 06 Dec 2011 18:25:42 -0000 Subject: [llvm-commits] [compiler-rt] r145950 - /compiler-rt/trunk/make/platform/clang_linux.mk Message-ID: <20111206182542.E77611BE003@llvm.org> Author: ddunbar Date: Tue Dec 6 12:25:42 2011 New Revision: 145950 URL: http://llvm.org/viewvc/llvm-project?rev=145950&view=rev Log: platform/clang_linux: Add profile and asan libs on x86. Modified: compiler-rt/trunk/make/platform/clang_linux.mk Modified: compiler-rt/trunk/make/platform/clang_linux.mk URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/make/platform/clang_linux.mk?rev=145950&r1=145949&r2=145950&view=diff ============================================================================== --- compiler-rt/trunk/make/platform/clang_linux.mk (original) +++ compiler-rt/trunk/make/platform/clang_linux.mk Tue Dec 6 12:25:42 2011 @@ -33,6 +33,26 @@ Arch.full-x86_64 := x86_64 endif +# Configuration for profile runtime. +ifeq ($(CompilerTargetArch),i386) +Configs += profile-i386 +Arch.profile-i386 := i386 +endif +ifeq ($(CompilerTargetArch),x86_64) +Configs += profile-x86_64 +Arch.profile-x86_64 := x86_64 +endif + +# Configuration for ASAN runtime. +ifeq ($(CompilerTargetArch),i386) +Configs += asan-i386 +Arch.asan-i386 := i386 +endif +ifeq ($(CompilerTargetArch),x86_64) +Configs += asan-x86_64 +Arch.asan-x86_64 := x86_64 +endif + endif ### @@ -41,9 +61,17 @@ CFLAGS.full-i386 := $(CFLAGS) -m32 CFLAGS.full-x86_64 := $(CFLAGS) -m64 +CFLAGS.profile-i386 := $(CFLAGS) -m32 +CFLAGS.profile-x86_64 := $(CFLAGS) -m64 +CFLAGS.asan-i386 := $(CFLAGS) -m32 +CFLAGS.asan-x86_64 := $(CFLAGS) -m64 FUNCTIONS.full-i386 := $(CommonFunctions) $(ArchFunctions.i386) FUNCTIONS.full-x86_64 := $(CommonFunctions) $(ArchFunctions.x86_64) +FUNCTIONS.profile-i386 := GCDAProfiling +FUNCTIONS.profile-x86_64 := GCDAProfiling +FUNCTIONS.asan-i386 := $(AsanFunctions) +FUNCTIONS.asan-x86_64 := $(AsanFunctions) # Always use optimized variants. OPTIMIZED := 1 From spop at codeaurora.org Tue Dec 6 11:34:12 2011 From: spop at codeaurora.org (Sebastian Pop) Date: Tue, 06 Dec 2011 17:34:12 -0000 Subject: [llvm-commits] [llvm] r145943 - in /llvm/trunk: include/llvm/CodeGen/DFAPacketizer.h lib/CodeGen/DFAPacketizer.cpp utils/TableGen/DFAPacketizerEmitter.cpp utils/TableGen/DFAPacketizerEmitter.h Message-ID: <20111206173412.372741BE003@llvm.org> Author: spop Date: Tue Dec 6 11:34:11 2011 New Revision: 145943 URL: http://llvm.org/viewvc/llvm-project?rev=145943&view=rev Log: add missing point at the end of sentences Modified: llvm/trunk/include/llvm/CodeGen/DFAPacketizer.h llvm/trunk/lib/CodeGen/DFAPacketizer.cpp llvm/trunk/utils/TableGen/DFAPacketizerEmitter.cpp llvm/trunk/utils/TableGen/DFAPacketizerEmitter.h Modified: llvm/trunk/include/llvm/CodeGen/DFAPacketizer.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/DFAPacketizer.h?rev=145943&r1=145942&r2=145943&view=diff ============================================================================== --- llvm/trunk/include/llvm/CodeGen/DFAPacketizer.h (original) +++ llvm/trunk/include/llvm/CodeGen/DFAPacketizer.h Tue Dec 6 11:34:11 2011 @@ -42,35 +42,35 @@ const int (*DFAStateInputTable)[2]; const unsigned *DFAStateEntryTable; - // CachedTable is a map from to ToState + // CachedTable is a map from to ToState. DenseMap CachedTable; - // ReadTable - Read the DFA transition table and update CachedTable + // ReadTable - Read the DFA transition table and update CachedTable. void ReadTable(unsigned int state); public: DFAPacketizer(const InstrItineraryData* I, const int (*SIT)[2], const unsigned* SET); - // Reset the current state to make all resources available + // Reset the current state to make all resources available. void clearResources() { CurrentState = 0; } // canReserveResources - Check if the resources occupied by a MCInstrDesc - // are available in the current state + // are available in the current state. bool canReserveResources(const llvm::MCInstrDesc* MID); // reserveResources - Reserve the resources occupied by a MCInstrDesc and - // change the current state to reflect that change + // change the current state to reflect that change. void reserveResources(const llvm::MCInstrDesc* MID); // canReserveResources - Check if the resources occupied by a machine - // instruction are available in the current state + // instruction are available in the current state. bool canReserveResources(llvm::MachineInstr* MI); // reserveResources - Reserve the resources occupied by a machine - // instruction and change the current state to reflect that change + // instruction and change the current state to reflect that change. void reserveResources(llvm::MachineInstr* MI); }; } Modified: llvm/trunk/lib/CodeGen/DFAPacketizer.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/DFAPacketizer.cpp?rev=145943&r1=145942&r2=145943&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/DFAPacketizer.cpp (original) +++ llvm/trunk/lib/CodeGen/DFAPacketizer.cpp Tue Dec 6 11:34:11 2011 @@ -35,7 +35,7 @@ // -// ReadTable - Read the DFA transition table and update CachedTable +// ReadTable - Read the DFA transition table and update CachedTable. // // Format of the transition tables: // DFAStateInputTable[][2] = pairs of for all valid @@ -47,7 +47,7 @@ unsigned ThisState = DFAStateEntryTable[state]; unsigned NextStateInTable = DFAStateEntryTable[state+1]; // Early exit in case CachedTable has already contains this - // state's transitions + // state's transitions. if (CachedTable.count(UnsignPair(state, DFAStateInputTable[ThisState][0]))) return; @@ -59,7 +59,7 @@ // canReserveResources - Check if the resources occupied by a MCInstrDesc -// are available in the current state +// are available in the current state. bool DFAPacketizer::canReserveResources(const llvm::MCInstrDesc* MID) { unsigned InsnClass = MID->getSchedClass(); const llvm::InstrStage* IS = InstrItins->beginStage(InsnClass); @@ -71,7 +71,7 @@ // reserveResources - Reserve the resources occupied by a MCInstrDesc and -// change the current state to reflect that change +// change the current state to reflect that change. void DFAPacketizer::reserveResources(const llvm::MCInstrDesc* MID) { unsigned InsnClass = MID->getSchedClass(); const llvm::InstrStage* IS = InstrItins->beginStage(InsnClass); @@ -84,14 +84,14 @@ // canReserveResources - Check if the resources occupied by a machine -// instruction are available in the current state +// instruction are available in the current state. bool DFAPacketizer::canReserveResources(llvm::MachineInstr* MI) { const llvm::MCInstrDesc& MID = MI->getDesc(); return canReserveResources(&MID); } // reserveResources - Reserve the resources occupied by a machine -// instruction and change the current state to reflect that change +// instruction and change the current state to reflect that change. void DFAPacketizer::reserveResources(llvm::MachineInstr* MI) { const llvm::MCInstrDesc& MID = MI->getDesc(); reserveResources(&MID); Modified: llvm/trunk/utils/TableGen/DFAPacketizerEmitter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/DFAPacketizerEmitter.cpp?rev=145943&r1=145942&r2=145943&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/DFAPacketizerEmitter.cpp (original) +++ llvm/trunk/utils/TableGen/DFAPacketizerEmitter.cpp Tue Dec 6 11:34:11 2011 @@ -29,19 +29,19 @@ // State represents the usage of machine resources if the packet contains // a set of instruction classes. // -// Specifically, currentState is a set of bit-masks +// Specifically, currentState is a set of bit-masks. // The nth bit in a bit-mask indicates whether the nth resource is being used // by this state. The set of bit-masks in a state represent the different // possible outcomes of transitioning to this state. -// For example: Consider a two resource architecture: Resource L and Resource M -// with three instruction classes: L, M, and L_or_M +// For example: consider a two resource architecture: resource L and resource M +// with three instruction classes: L, M, and L_or_M. // From the initial state (currentState = 0x00), if we add instruction class // L_or_M we will transition to a state with currentState = [0x01, 0x10]. This // represents the possible resource states that can result from adding a L_or_M // instruction // // Another way of thinking about this transition is we are mapping a NDFA with -// two states [0x01] and [0x10] into a DFA with a single state [0x01, 0x10] +// two states [0x01] and [0x10] into a DFA with a single state [0x01, 0x10]. // // namespace { @@ -57,15 +57,15 @@ // // canAddInsnClass - Returns true if an instruction of type InsnClass is a - // valid transition from this state i.e., can an instruction of type InsnClass - // be added to the packet represented by this state + // valid transition from this state, i.e., can an instruction of type InsnClass + // be added to the packet represented by this state. // // PossibleStates is the set of valid resource states that ensue from valid - // transitions + // transitions. // bool canAddInsnClass(unsigned InsnClass, std::set& PossibleStates); }; -} // End anonymous namespace +} // End anonymous namespace. namespace { @@ -79,39 +79,39 @@ Transition(State* from_, unsigned input_, State* to_); }; -} // End anonymous namespace +} // End anonymous namespace. // -// Comparators to keep set of states sorted +// Comparators to keep set of states sorted. // namespace { struct ltState { bool operator()(const State* s1, const State* s2) const; }; -} // End anonymous namespace +} // End anonymous namespace. // -// class DFA: deterministic finite automaton for processor resource tracking +// class DFA: deterministic finite automaton for processor resource tracking. // namespace { class DFA { public: DFA(); - // Set of states. Need to keep this sorted to emit the transition table + // Set of states. Need to keep this sorted to emit the transition table. std::set states; - // Map from a state to the list of transitions with that state as source + // Map from a state to the list of transitions with that state as source. std::map, ltState> stateTransitions; State* currentState; - // Highest valued Input seen + // Highest valued Input seen. unsigned LargestInput; // - // Modify the DFA + // Modify the DFA. // void initialize(); void addState(State*); @@ -119,22 +119,22 @@ // // getTransition - Return the state when a transition is made from - // State From with Input I. If a transition is not found, return NULL + // State From with Input I. If a transition is not found, return NULL. // State* getTransition(State*, unsigned); // // isValidTransition: Predicate that checks if there is a valid transition - // from state From on input InsnClass + // from state From on input InsnClass. // bool isValidTransition(State* From, unsigned InsnClass); // - // writeTable: Print out a table representing the DFA + // writeTable: Print out a table representing the DFA. // void writeTableAndAPI(raw_ostream &OS, const std::string& ClassName); }; -} // End anonymous namespace +} // End anonymous namespace. // @@ -166,15 +166,15 @@ // // canAddInsnClass - Returns true if an instruction of type InsnClass is a // valid transition from this state i.e., can an instruction of type InsnClass -// be added to the packet represented by this state +// be added to the packet represented by this state. // // PossibleStates is the set of valid resource states that ensue from valid -// transitions +// transitions. // bool State::canAddInsnClass(unsigned InsnClass, std::set& PossibleStates) { // - // Iterate over all resource states in currentState + // Iterate over all resource states in currentState. // bool AddedState = false; @@ -183,8 +183,8 @@ unsigned thisState = *SI; // - // Iterate over all possible resources used in InsnClass - // For ex: for InsnClass = 0x11, all resources = {0x01, 0x10} + // Iterate over all possible resources used in InsnClass. + // For ex: for InsnClass = 0x11, all resources = {0x01, 0x10}. // DenseSet VisitedResourceStates; @@ -192,18 +192,18 @@ if ((0x1 << j) & InsnClass) { // // For each possible resource used in InsnClass, generate the - // resource state if that resource was used + // resource state if that resource was used. // unsigned ResultingResourceState = thisState | (0x1 << j); // // Check if the resulting resource state can be accommodated in this - // packet - // We compute ResultingResourceState OR thisState + // packet. + // We compute ResultingResourceState OR thisState. // If the result of the OR is different than thisState, it implies // that there is at least one resource that can be used to schedule - // InsnClass in the current packet + // InsnClass in the current packet. // Insert ResultingResourceState into PossibleStates only if we haven't - // processed ResultingResourceState before + // processed ResultingResourceState before. // if ((ResultingResourceState != thisState) && (VisitedResourceStates.count(ResultingResourceState) == 0)) { @@ -231,18 +231,18 @@ void DFA::addTransition(Transition* T) { - // Update LargestInput + // Update LargestInput. if (T->input > LargestInput) LargestInput = T->input; - // Add the new transition + // Add the new transition. stateTransitions[T->from].push_back(T); } // // getTransition - Return the state when a transition is made from -// State From with Input I. If a transition is not found, return NULL +// State From with Input I. If a transition is not found, return NULL. // State* DFA::getTransition(State* From, unsigned I) { // Do we have a transition from state From? @@ -275,26 +275,26 @@ // // writeTableAndAPI - Print out a table representing the DFA and the -// associated API to create a DFA packetizer +// associated API to create a DFA packetizer. // // Format: // DFAStateInputTable[][2] = pairs of for all valid -// transitions +// transitions. // DFAStateEntryTable[i] = Index of the first entry in DFAStateInputTable for -// the ith state +// the ith state. // // void DFA::writeTableAndAPI(raw_ostream &OS, const std::string& TargetName) { std::set::iterator SI = states.begin(); // This table provides a map to the beginning of the transitions for State s - // in DFAStateInputTable i.e., + // in DFAStateInputTable. std::vector StateEntry(states.size()); OS << "namespace llvm {\n\n"; OS << "const int " << TargetName << "DFAStateInputTable[][2] = {\n"; // Tracks the total valid transitions encountered so far. It is used - // to construct the StateEntry table + // to construct the StateEntry table. int ValidTransitions = 0; for (unsigned i = 0; i < states.size(); ++i, ++SI) { StateEntry[i] = ValidTransitions; @@ -309,8 +309,8 @@ ++ValidTransitions; } - /* If there are no valid transitions from this stage, we need a sentinel - transition */ + // If there are no valid transitions from this stage, we need a sentinel + // transition. if (ValidTransitions == StateEntry[i]) OS << "{-1, -1},"; @@ -320,7 +320,7 @@ OS << "const unsigned int " << TargetName << "DFAStateEntryTable[] = {\n"; // Multiply i by 2 since each entry in DFAStateInputTable is a set of - // two numbers + // two numbers. for (unsigned i = 0; i < states.size(); ++i) OS << StateEntry[i] << ", "; @@ -329,7 +329,7 @@ // - // Emit DFA Packetizer tables if the target is a VLIW machine + // Emit DFA Packetizer tables if the target is a VLIW machine. // std::string SubTargetClassName = TargetName + "GenSubtargetInfo"; OS << "\n" << "#include \"llvm/CodeGen/DFAPacketizer.h\"\n"; @@ -350,11 +350,11 @@ Record *ItinData, unsigned &NStages, raw_ostream &OS) { - // Collect processor itineraries + // Collect processor itineraries. std::vector ProcItinList = - Records.getAllDerivedDefinitions("ProcessorItineraries"); + Records.getAllDerivedDefinitions("ProcessorItineraries"); - // If just no itinerary then don't bother + // If just no itinerary then don't bother. if (ProcItinList.size() < 2) return; std::map NameToBitsMap; @@ -364,7 +364,7 @@ Record *Proc = ProcItinList[i]; std::vector FUs = Proc->getValueAsListOfDefs("FU"); - // Convert macros to bits for each stage + // Convert macros to bits for each stage. for (unsigned i = 0, N = FUs.size(); i < N; ++i) NameToBitsMap[FUs[i]->getName()] = (unsigned) (1U << i); } @@ -372,22 +372,22 @@ const std::vector &StageList = ItinData->getValueAsListOfDefs("Stages"); - // The number of stages + // The number of stages. NStages = StageList.size(); - // For each unit + // For each unit. unsigned UnitBitValue = 0; - // Compute the bitwise or of each unit used in this stage + // Compute the bitwise or of each unit used in this stage. for (unsigned i = 0; i < NStages; ++i) { const Record *Stage = StageList[i]; - // Get unit list + // Get unit list. const std::vector &UnitList = Stage->getValueAsListOfDefs("Units"); for (unsigned j = 0, M = UnitList.size(); j < M; ++j) { - // Conduct bitwise or + // Conduct bitwise or. std::string UnitName = UnitList[j]->getName(); assert(NameToBitsMap.count(UnitName)); UnitBitValue |= NameToBitsMap[UnitName]; @@ -400,38 +400,38 @@ // -// Run the worklist algorithm to generate the DFA +// Run the worklist algorithm to generate the DFA. // void DFAGen::run(raw_ostream &OS) { EmitSourceFileHeader("Target DFA Packetizer Tables", OS); - // Collect processor iteraries + // Collect processor iteraries. std::vector ProcItinList = Records.getAllDerivedDefinitions("ProcessorItineraries"); // - // Collect the instruction classes + // Collect the instruction classes. // for (unsigned i = 0, N = ProcItinList.size(); i < N; i++) { Record *Proc = ProcItinList[i]; - // Get processor itinerary name + // Get processor itinerary name. const std::string &Name = Proc->getName(); - // Skip default + // Skip default. if (Name == "NoItineraries") continue; - // Sanity check for at least one instruction itinerary class + // Sanity check for at least one instruction itinerary class. unsigned NItinClasses = Records.getAllDerivedDefinitions("InstrItinClass").size(); if (NItinClasses == 0) return; - // Get itinerary data list + // Get itinerary data list. std::vector ItinDataList = Proc->getValueAsListOfDefs("IID"); - // Collect instruction classes for all itinerary data + // Collect instruction classes for all itinerary data. for (unsigned j = 0, M = ItinDataList.size(); j < M; j++) { Record *ItinData = ItinDataList[j]; unsigned NStages; @@ -441,7 +441,7 @@ // - // Run a worklist algorithm to generate the DFA + // Run a worklist algorithm to generate the DFA. // DFA D; State* Initial = new State; @@ -454,7 +454,7 @@ WorkList.push_back(Initial); // - // Worklist algorithm to create a DFA for processor resource tracking + // Worklist algorithm to create a DFA for processor resource tracking. // C = {set of InsnClasses} // Begin with initial node in worklist. Initial node does not have // any consumed resources, @@ -479,14 +479,14 @@ std::set NewStateResources; // // If we haven't already created a transition for this input - // and the state can accommodate this InsnClass, create a transition + // and the state can accommodate this InsnClass, create a transition. // if (!D.getTransition(current, InsnClass) && current->canAddInsnClass(InsnClass, NewStateResources)) { State* NewState = NULL; // - // If we have seen this state before, then do not create a new state + // If we have seen this state before, then do not create a new state. // // std::map, State*>::iterator VI; @@ -507,6 +507,6 @@ } } - // Print out the table + // Print out the table. D.writeTableAndAPI(OS, TargetName); } Modified: llvm/trunk/utils/TableGen/DFAPacketizerEmitter.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/DFAPacketizerEmitter.h?rev=145943&r1=145942&r2=145943&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/DFAPacketizerEmitter.h (original) +++ llvm/trunk/utils/TableGen/DFAPacketizerEmitter.h Tue Dec 6 11:34:11 2011 @@ -25,14 +25,14 @@ namespace llvm { // // class DFAGen: class that generates and prints out the DFA for resource -// tracking +// tracking. // class DFAGen : public TableGenBackend { private: std::string TargetName; // // allInsnClasses is the set of all possible resources consumed by an - // InstrStage + // InstrStage. // DenseSet allInsnClasses; RecordKeeper &Records; From kcc at google.com Tue Dec 6 13:10:48 2011 From: kcc at google.com (Kostya Serebryany) Date: Tue, 06 Dec 2011 19:10:48 -0000 Subject: [llvm-commits] [compiler-rt] r145953 - in /compiler-rt/trunk/lib/asan/tests: asan_mac_test.mm asan_test.cc Message-ID: <20111206191048.78D751BE003@llvm.org> Author: kcc Date: Tue Dec 6 13:10:48 2011 New Revision: 145953 URL: http://llvm.org/viewvc/llvm-project?rev=145953&view=rev Log: [asan] GCD tests on Mac: prevent optimization and enable. Patch by glider at google.com Modified: compiler-rt/trunk/lib/asan/tests/asan_mac_test.mm compiler-rt/trunk/lib/asan/tests/asan_test.cc Modified: compiler-rt/trunk/lib/asan/tests/asan_mac_test.mm URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/lib/asan/tests/asan_mac_test.mm?rev=145953&r1=145952&r2=145953&view=diff ============================================================================== --- compiler-rt/trunk/lib/asan/tests/asan_mac_test.mm (original) +++ compiler-rt/trunk/lib/asan/tests/asan_mac_test.mm Tue Dec 6 13:10:48 2011 @@ -59,13 +59,13 @@ @end void worker_do_alloc(int size) { - char *mem = malloc(size); + char * volatile mem = malloc(size); mem[0] = 0; // Ok free(mem); } void worker_do_crash(int size) { - char *mem = malloc(size); + char * volatile mem = malloc(size); mem[size] = 0; // BOOM free(mem); } @@ -160,7 +160,7 @@ dispatch_time(DISPATCH_TIME_NOW, 1LL * NSEC_PER_SEC); dispatch_source_set_timer(timer, milestone, DISPATCH_TIME_FOREVER, 0); - char *mem = malloc(10); + char * volatile mem = malloc(10); dispatch_source_set_event_handler(timer, ^{ mem[10] = 1; }); @@ -177,7 +177,7 @@ dispatch_time(DISPATCH_TIME_NOW, 1LL * NSEC_PER_SEC); dispatch_source_set_timer(timer, milestone, DISPATCH_TIME_FOREVER, 0); - char *mem = malloc(10); + char * volatile mem = malloc(10); // Both dispatch_source_set_cancel_handler() and // dispatch_source_set_event_handler() use dispatch_barrier_async_f(). // It's tricky to test dispatch_source_set_cancel_handler() separately, @@ -195,7 +195,7 @@ void TestGCDGroupAsync() { dispatch_queue_t queue = dispatch_get_global_queue(0, 0); dispatch_group_t group = dispatch_group_create(); - char *mem = malloc(10); + char * volatile mem = malloc(10); dispatch_group_async(group, queue, ^{ mem[10] = 1; }); Modified: compiler-rt/trunk/lib/asan/tests/asan_test.cc URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/lib/asan/tests/asan_test.cc?rev=145953&r1=145952&r2=145953&view=diff ============================================================================== --- compiler-rt/trunk/lib/asan/tests/asan_test.cc (original) +++ compiler-rt/trunk/lib/asan/tests/asan_test.cc Tue Dec 6 13:10:48 2011 @@ -1771,50 +1771,50 @@ EXPECT_DEATH(CFAllocatorMallocZoneDoubleFree(), "attempting double-free"); } -TEST(AddressSanitizerMac, DISABLED_GCDDispatchAsync) { +TEST(AddressSanitizerMac, GCDDispatchAsync) { // Make sure the whole ASan report is printed, i.e. that we don't die // on a CHECK. EXPECT_DEATH(TestGCDDispatchAsync(), "Shadow byte and word"); } -TEST(AddressSanitizerMac, DISABLED_GCDDispatchSync) { +TEST(AddressSanitizerMac, GCDDispatchSync) { // Make sure the whole ASan report is printed, i.e. that we don't die // on a CHECK. EXPECT_DEATH(TestGCDDispatchSync(), "Shadow byte and word"); } -TEST(AddressSanitizerMac, DISABLED_GCDReuseWqthreadsAsync) { +TEST(AddressSanitizerMac, GCDReuseWqthreadsAsync) { // Make sure the whole ASan report is printed, i.e. that we don't die // on a CHECK. EXPECT_DEATH(TestGCDReuseWqthreadsAsync(), "Shadow byte and word"); } -TEST(AddressSanitizerMac, DISABLED_GCDReuseWqthreadsSync) { +TEST(AddressSanitizerMac, GCDReuseWqthreadsSync) { // Make sure the whole ASan report is printed, i.e. that we don't die // on a CHECK. EXPECT_DEATH(TestGCDReuseWqthreadsSync(), "Shadow byte and word"); } -TEST(AddressSanitizerMac, DISABLED_GCDDispatchAfter) { +TEST(AddressSanitizerMac, GCDDispatchAfter) { // Make sure the whole ASan report is printed, i.e. that we don't die // on a CHECK. EXPECT_DEATH(TestGCDDispatchAfter(), "Shadow byte and word"); } -TEST(AddressSanitizerMac, DISABLED_GCDSourceEvent) { +TEST(AddressSanitizerMac, GCDSourceEvent) { // Make sure the whole ASan report is printed, i.e. that we don't die // on a CHECK. EXPECT_DEATH(TestGCDSourceEvent(), "Shadow byte and word"); } -TEST(AddressSanitizerMac, DISABLED_GCDSourceCancel) { +TEST(AddressSanitizerMac, GCDSourceCancel) { // Make sure the whole ASan report is printed, i.e. that we don't die // on a CHECK. EXPECT_DEATH(TestGCDSourceCancel(), "Shadow byte and word"); } -TEST(AddressSanitizerMac, DISABLED_GCDGroupAsync) { +TEST(AddressSanitizerMac, GCDGroupAsync) { // Make sure the whole ASan report is printed, i.e. that we don't die // on a CHECK. EXPECT_DEATH(TestGCDGroupAsync(), "Shadow byte and word"); From mcrosier at apple.com Tue Dec 6 12:46:41 2011 From: mcrosier at apple.com (Chad Rosier) Date: Tue, 06 Dec 2011 10:46:41 -0800 Subject: [llvm-commits] [llvm] r145912 - in /llvm/trunk/lib/Target/Mips: MipsInstrFormats.td MipsInstrInfo.cpp MipsInstrInfo.td In-Reply-To: <86AC779C188FE74F88F6494478B46332E8B3F0@exchdb03.mips.com> References: <20111206033449.22EBB2A6C12C@llvm.org> <86AC779C188FE74F88F6494478B46332E8B3F0@exchdb03.mips.com> Message-ID: <3DCFBAAD-5552-41AF-BD8A-66E6524B56E8@apple.com> On Dec 6, 2011, at 10:40 AM, Carter, Jack wrote: > The commit was after I left for home and I just got in again. No problem. > I am checking here for the correct form for a test case and will send it in. Sounds good. See http://llvm.org/docs/TestingGuide.html#rtcustom for more info on writing regression tests. You could also grep through lib/test/* for examples. Chad > Jack > ________________________________________ > From: Bruno Cardoso Lopes [bruno.cardoso at gmail.com] > Sent: Tuesday, December 06, 2011 9:59 AM > To: Chad Rosier; Carter, Jack > Cc: llvm-commits at cs.uiuc.edu > Subject: Re: [llvm-commits] [llvm] r145912 - in /llvm/trunk/lib/Target/Mips: MipsInstrFormats.td MipsInstrInfo.cpp MipsInstrInfo.td > > Still waiting from Jack Carter! Since it was commited yesterday, he > may be taking his time to do it. > > On Tue, Dec 6, 2011 at 3:39 PM, Chad Rosier wrote: >> Did the test case ever land? >> >> Chad >> >> On Dec 5, 2011, at 7:34 PM, Bruno Cardoso Lopes wrote: >> >>> Author: bruno >>> Date: Mon Dec 5 21:34:48 2011 >>> New Revision: 145912 >>> >>> URL: http://llvm.org/viewvc/llvm-project?rev=145912&view=rev >>> Log: >>> Use branches instead of jumps + variable cleanup. Testcase coming next. Patch by Jack Carter >>> >>> Modified: >>> llvm/trunk/lib/Target/Mips/MipsInstrFormats.td >>> llvm/trunk/lib/Target/Mips/MipsInstrInfo.cpp >>> llvm/trunk/lib/Target/Mips/MipsInstrInfo.td >>> >>> Modified: llvm/trunk/lib/Target/Mips/MipsInstrFormats.td >>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsInstrFormats.td?rev=145912&r1=145911&r2=145912&view=diff >>> ============================================================================== >>> --- llvm/trunk/lib/Target/Mips/MipsInstrFormats.td (original) >>> +++ llvm/trunk/lib/Target/Mips/MipsInstrFormats.td Mon Dec 5 21:34:48 2011 >>> @@ -115,7 +115,7 @@ >>> let Inst{15-0} = imm16; >>> } >>> >>> -class CBranchBase op, dag outs, dag ins, string asmstr, >>> +class BranchBase op, dag outs, dag ins, string asmstr, >>> list pattern, InstrItinClass itin>: >>> MipsInst >>> { >>> >>> Modified: llvm/trunk/lib/Target/Mips/MipsInstrInfo.cpp >>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsInstrInfo.cpp?rev=145912&r1=145911&r2=145912&view=diff >>> ============================================================================== >>> --- llvm/trunk/lib/Target/Mips/MipsInstrInfo.cpp (original) >>> +++ llvm/trunk/lib/Target/Mips/MipsInstrInfo.cpp Mon Dec 5 21:34:48 2011 >>> @@ -236,7 +236,7 @@ >>> Opc == Mips::BGEZ || Opc == Mips::BLTZ || Opc == Mips::BLEZ || >>> Opc == Mips::BEQ64 || Opc == Mips::BNE64 || Opc == Mips::BGTZ64 || >>> Opc == Mips::BGEZ64 || Opc == Mips::BLTZ64 || Opc == Mips::BLEZ64 || >>> - Opc == Mips::BC1T || Opc == Mips::BC1F || Opc == Mips::J) ? >>> + Opc == Mips::BC1T || Opc == Mips::BC1F || Opc == Mips::B) ? >>> Opc : 0; >>> } >>> >>> @@ -320,7 +320,7 @@ >>> // If there is only one terminator instruction, process it. >>> if (!SecondLastOpc) { >>> // Unconditional branch >>> - if (LastOpc == Mips::J) { >>> + if (LastOpc == Mips::B) { >>> TBB = LastInst->getOperand(0).getMBB(); >>> return false; >>> } >>> @@ -337,7 +337,7 @@ >>> >>> // If second to last instruction is an unconditional branch, >>> // analyze it and remove the last instruction. >>> - if (SecondLastOpc == Mips::J) { >>> + if (SecondLastOpc == Mips::B) { >>> // Return if the last instruction cannot be removed. >>> if (!AllowModify) >>> return true; >>> @@ -349,7 +349,7 @@ >>> >>> // Conditional branch followed by an unconditional branch. >>> // The last one must be unconditional. >>> - if (LastOpc != Mips::J) >>> + if (LastOpc != Mips::B) >>> return true; >>> >>> AnalyzeCondBr(SecondLastInst, SecondLastOpc, TBB, Cond); >>> @@ -391,14 +391,14 @@ >>> // Two-way Conditional branch. >>> if (FBB) { >>> BuildCondBr(MBB, TBB, DL, Cond); >>> - BuildMI(&MBB, DL, get(Mips::J)).addMBB(FBB); >>> + BuildMI(&MBB, DL, get(Mips::B)).addMBB(FBB); >>> return 2; >>> } >>> >>> // One way branch. >>> // Unconditional branch. >>> if (Cond.empty()) >>> - BuildMI(&MBB, DL, get(Mips::J)).addMBB(TBB); >>> + BuildMI(&MBB, DL, get(Mips::B)).addMBB(TBB); >>> else // Conditional branch. >>> BuildCondBr(MBB, TBB, DL, Cond); >>> return 1; >>> >>> Modified: llvm/trunk/lib/Target/Mips/MipsInstrInfo.td >>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsInstrInfo.td?rev=145912&r1=145911&r2=145912&view=diff >>> ============================================================================== >>> --- llvm/trunk/lib/Target/Mips/MipsInstrInfo.td (original) >>> +++ llvm/trunk/lib/Target/Mips/MipsInstrInfo.td Mon Dec 5 21:34:48 2011 >>> @@ -380,21 +380,13 @@ >>> let isPseudo = Pseudo; >>> } >>> >>> -// Memory Load/Store >>> +// Unaligned Memory Load/Store >>> let canFoldAsLoad = 1 in >>> -class LoadX op, RegisterClass RC, >>> - Operand MemOpnd>: >>> - FMem>> - "", >>> - [], IILoad> { >>> -} >>> +class LoadUnAlign op, RegisterClass RC, Operand MemOpnd>: >>> + FMem {} >>> >>> -class StoreX op, RegisterClass RC, >>> - Operand MemOpnd>: >>> - FMem>> - "", >>> - [], IIStore> { >>> -} >>> +class StoreUnAlign op, RegisterClass RC, Operand MemOpnd>: >>> + FMem {} >>> >>> // 32-bit load. >>> multiclass LoadM32 op, string instr_asm, PatFrag OpNode, >>> @@ -415,10 +407,10 @@ >>> } >>> >>> // 32-bit load. >>> -multiclass LoadX32 op> { >>> - def #NAME# : LoadX, >>> +multiclass LoadUnAlign32 op> { >>> + def #NAME# : LoadUnAlign, >>> Requires<[NotN64]>; >>> - def _P8 : LoadX, >>> + def _P8 : LoadUnAlign, >>> Requires<[IsN64]>; >>> } >>> // 32-bit store. >>> @@ -440,18 +432,18 @@ >>> } >>> >>> // 32-bit store. >>> -multiclass StoreX32 op> { >>> - def #NAME# : StoreX, >>> +multiclass StoreUnAlign32 op> { >>> + def #NAME# : StoreUnAlign, >>> Requires<[NotN64]>; >>> - def _P8 : StoreX, >>> + def _P8 : StoreUnAlign, >>> Requires<[IsN64]>; >>> } >>> >>> // Conditional Branch >>> class CBranch op, string instr_asm, PatFrag cond_op, RegisterClass RC>: >>> - CBranchBase>> - !strconcat(instr_asm, "\t$rs, $rt, $imm16"), >>> - [(brcond (i32 (cond_op RC:$rs, RC:$rt)), bb:$imm16)], IIBranch> { >>> + BranchBase>> + !strconcat(instr_asm, "\t$rs, $rt, $imm16"), >>> + [(brcond (i32 (cond_op RC:$rs, RC:$rt)), bb:$imm16)], IIBranch> { >>> let isBranch = 1; >>> let isTerminator = 1; >>> let hasDelaySlot = 1; >>> @@ -459,9 +451,9 @@ >>> >>> class CBranchZero op, bits<5> _rt, string instr_asm, PatFrag cond_op, >>> RegisterClass RC>: >>> - CBranchBase>> - !strconcat(instr_asm, "\t$rs, $imm16"), >>> - [(brcond (i32 (cond_op RC:$rs, 0)), bb:$imm16)], IIBranch> { >>> + BranchBase>> + !strconcat(instr_asm, "\t$rs, $imm16"), >>> + [(brcond (i32 (cond_op RC:$rs, 0)), bb:$imm16)], IIBranch> { >>> let rt = _rt; >>> let isBranch = 1; >>> let isTerminator = 1; >>> @@ -486,10 +478,16 @@ >>> IIAlu>; >>> >>> // Unconditional branch >>> -let isBranch=1, isTerminator=1, isBarrier=1, hasDelaySlot = 1 in >>> -class JumpFJ op, string instr_asm>: >>> - FJ>> - !strconcat(instr_asm, "\t$target"), [(br bb:$target)], IIBranch>; >>> +class UncondBranch op, string instr_asm>: >>> + BranchBase>> + !strconcat(instr_asm, "\t$imm16"), [(br bb:$imm16)], IIBranch> { >>> + let rs = 0; >>> + let rt = 0; >>> + let isBranch = 1; >>> + let isTerminator = 1; >>> + let isBarrier = 1; >>> + let hasDelaySlot = 1; >>> +} >>> >>> let isBranch=1, isTerminator=1, isBarrier=1, rd=0, hasDelaySlot = 1, >>> isIndirectBranch = 1 in >>> @@ -810,10 +808,10 @@ >>> defm USW : StoreM32<0x2b, "usw", store_u, 1>; >>> >>> /// Primitives for unaligned >>> -defm LWL : LoadX32<0x22>; >>> -defm LWR : LoadX32<0x26>; >>> -defm SWL : StoreX32<0x2A>; >>> -defm SWR : StoreX32<0x2E>; >>> +defm LWL : LoadUnAlign32<0x22>; >>> +defm LWR : LoadUnAlign32<0x26>; >>> +defm SWL : StoreUnAlign32<0x2A>; >>> +defm SWR : StoreUnAlign32<0x2E>; >>> >>> let hasSideEffects = 1 in >>> def SYNC : MipsInst<(outs), (ins i32imm:$stype), "sync $stype", >>> @@ -833,10 +831,10 @@ >>> def SC_P8 : SCBase<0x38, "sc", CPURegs, mem64>, Requires<[IsN64]>; >>> >>> /// Jump and Branch Instructions >>> -def J : JumpFJ<0x02, "j">; >>> def JR : JumpFR<0x00, 0x08, "jr", CPURegs>; >>> def JAL : JumpLink<0x03, "jal">; >>> def JALR : JumpLinkReg<0x00, 0x09, "jalr">; >>> +def B : UncondBranch<0x04, "b">; >>> def BEQ : CBranch<0x04, "beq", seteq, CPURegs>; >>> def BNE : CBranch<0x05, "bne", setne, CPURegs>; >>> def BGEZ : CBranchZero<0x01, 1, "bgez", setge, CPURegs>; >>> >>> >>> _______________________________________________ >>> llvm-commits mailing list >>> llvm-commits at cs.uiuc.edu >>> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits >> > > > > -- > Bruno Cardoso Lopes > http://www.brunocardoso.cc From justin.holewinski at gmail.com Tue Dec 6 11:39:48 2011 From: justin.holewinski at gmail.com (Justin Holewinski) Date: Tue, 06 Dec 2011 17:39:48 -0000 Subject: [llvm-commits] [llvm] r145947 - in /llvm/trunk: lib/Target/PTX/InstPrinter/PTXInstPrinter.cpp lib/Target/PTX/MCTargetDesc/PTXBaseInfo.h lib/Target/PTX/PTXAsmPrinter.cpp lib/Target/PTX/PTXISelLowering.cpp lib/Target/PTX/PTXInstrInfo.td lib/Target/PTX/PTXMFInfoExtract.cpp lib/Target/PTX/PTXMachineFunctionInfo.h test/CodeGen/PTX/mov.ll test/CodeGen/PTX/parameter-order.ll Message-ID: <20111206173949.1B8371BE003@llvm.org> Author: jholewinski Date: Tue Dec 6 11:39:48 2011 New Revision: 145947 URL: http://llvm.org/viewvc/llvm-project?rev=145947&view=rev Log: PTX: Continue to fix up the register mess. Modified: llvm/trunk/lib/Target/PTX/InstPrinter/PTXInstPrinter.cpp llvm/trunk/lib/Target/PTX/MCTargetDesc/PTXBaseInfo.h llvm/trunk/lib/Target/PTX/PTXAsmPrinter.cpp llvm/trunk/lib/Target/PTX/PTXISelLowering.cpp llvm/trunk/lib/Target/PTX/PTXInstrInfo.td llvm/trunk/lib/Target/PTX/PTXMFInfoExtract.cpp llvm/trunk/lib/Target/PTX/PTXMachineFunctionInfo.h llvm/trunk/test/CodeGen/PTX/mov.ll llvm/trunk/test/CodeGen/PTX/parameter-order.ll Modified: llvm/trunk/lib/Target/PTX/InstPrinter/PTXInstPrinter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PTX/InstPrinter/PTXInstPrinter.cpp?rev=145947&r1=145946&r2=145947&view=diff ============================================================================== --- llvm/trunk/lib/Target/PTX/InstPrinter/PTXInstPrinter.cpp (original) +++ llvm/trunk/lib/Target/PTX/InstPrinter/PTXInstPrinter.cpp Tue Dec 6 11:39:48 2011 @@ -39,32 +39,45 @@ void PTXInstPrinter::printRegName(raw_ostream &OS, unsigned RegNo) const { // Decode the register number into type and offset - unsigned RegType = RegNo & 0xF; - unsigned RegOffset = RegNo >> 4; + unsigned RegSpace = RegNo & 0x7; + unsigned RegType = (RegNo >> 3) & 0x7; + unsigned RegOffset = RegNo >> 6; // Print the register OS << "%"; - switch (RegType) { + switch (RegSpace) { default: - llvm_unreachable("Unknown register type!"); - case PTXRegisterType::Pred: - OS << "p"; - break; - case PTXRegisterType::B16: - OS << "rh"; - break; - case PTXRegisterType::B32: - OS << "r"; - break; - case PTXRegisterType::B64: - OS << "rd"; + llvm_unreachable("Unknown register space!"); + case PTXRegisterSpace::Reg: + switch (RegType) { + default: + llvm_unreachable("Unknown register type!"); + case PTXRegisterType::Pred: + OS << "p"; + break; + case PTXRegisterType::B16: + OS << "rh"; + break; + case PTXRegisterType::B32: + OS << "r"; + break; + case PTXRegisterType::B64: + OS << "rd"; + break; + case PTXRegisterType::F32: + OS << "f"; + break; + case PTXRegisterType::F64: + OS << "fd"; + break; + } break; - case PTXRegisterType::F32: - OS << "f"; + case PTXRegisterSpace::Return: + OS << "ret"; break; - case PTXRegisterType::F64: - OS << "fd"; + case PTXRegisterSpace::Argument: + OS << "arg"; break; } Modified: llvm/trunk/lib/Target/PTX/MCTargetDesc/PTXBaseInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PTX/MCTargetDesc/PTXBaseInfo.h?rev=145947&r1=145946&r2=145947&view=diff ============================================================================== --- llvm/trunk/lib/Target/PTX/MCTargetDesc/PTXBaseInfo.h (original) +++ llvm/trunk/lib/Target/PTX/MCTargetDesc/PTXBaseInfo.h Tue Dec 6 11:39:48 2011 @@ -17,6 +17,8 @@ #ifndef PTXBASEINFO_H #define PTXBASEINFO_H +#include "llvm/Support/ErrorHandling.h" +#include "llvm/Support/raw_ostream.h" #include "PTXMCTargetDesc.h" namespace llvm { @@ -69,6 +71,63 @@ F64 }; } // namespace PTXRegisterType + + namespace PTXRegisterSpace { + // Register space encoded in MCOperands + enum { + Reg = 0, + Local, + Param, + Argument, + Return + }; + } + + inline static void decodeRegisterName(raw_ostream &OS, + unsigned EncodedReg) { + OS << "%"; + + unsigned RegSpace = EncodedReg & 0x7; + unsigned RegType = (EncodedReg >> 3) & 0x7; + unsigned RegOffset = EncodedReg >> 6; + + switch (RegSpace) { + default: + llvm_unreachable("Unknown register space!"); + case PTXRegisterSpace::Reg: + switch (RegType) { + default: + llvm_unreachable("Unknown register type!"); + case PTXRegisterType::Pred: + OS << "p"; + break; + case PTXRegisterType::B16: + OS << "rh"; + break; + case PTXRegisterType::B32: + OS << "r"; + break; + case PTXRegisterType::B64: + OS << "rd"; + break; + case PTXRegisterType::F32: + OS << "f"; + break; + case PTXRegisterType::F64: + OS << "fd"; + break; + } + break; + case PTXRegisterSpace::Return: + OS << "ret"; + break; + case PTXRegisterSpace::Argument: + OS << "arg"; + break; + } + + OS << RegOffset; + } } // namespace llvm #endif Modified: llvm/trunk/lib/Target/PTX/PTXAsmPrinter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PTX/PTXAsmPrinter.cpp?rev=145947&r1=145946&r2=145947&view=diff ============================================================================== --- llvm/trunk/lib/Target/PTX/PTXAsmPrinter.cpp (original) +++ llvm/trunk/lib/Target/PTX/PTXAsmPrinter.cpp Tue Dec 6 11:39:48 2011 @@ -51,23 +51,23 @@ static const char PARAM_PREFIX[] = "__param_"; static const char RETURN_PREFIX[] = "__ret_"; -static const char *getRegisterTypeName(unsigned RegNo, - const MachineRegisterInfo& MRI) { - const TargetRegisterClass *TRC = MRI.getRegClass(RegNo); - -#define TEST_REGCLS(cls, clsstr) \ - if (PTX::cls ## RegisterClass == TRC) return # clsstr; - - TEST_REGCLS(RegPred, pred); - TEST_REGCLS(RegI16, b16); - TEST_REGCLS(RegI32, b32); - TEST_REGCLS(RegI64, b64); - TEST_REGCLS(RegF32, b32); - TEST_REGCLS(RegF64, b64); -#undef TEST_REGCLS - - llvm_unreachable("Not in any register class!"); - return NULL; +static const char *getRegisterTypeName(unsigned RegType) { + switch (RegType) { + default: + llvm_unreachable("Unknown register type"); + case PTXRegisterType::Pred: + return ".pred"; + case PTXRegisterType::B16: + return ".b16"; + case PTXRegisterType::B32: + return ".b32"; + case PTXRegisterType::B64: + return ".b64"; + case PTXRegisterType::F32: + return ".f32"; + case PTXRegisterType::F64: + return ".f64"; + } } static const char *getStateSpaceName(unsigned addressSpace) { @@ -188,32 +188,32 @@ unsigned numRegs; // pred - numRegs = MFI->getNumRegistersForClass(PTX::RegPredRegisterClass); + numRegs = MFI->countRegisters(PTXRegisterType::Pred, PTXRegisterSpace::Reg); if(numRegs > 0) os << "\t.reg .pred %p<" << numRegs << ">;\n"; // i16 - numRegs = MFI->getNumRegistersForClass(PTX::RegI16RegisterClass); + numRegs = MFI->countRegisters(PTXRegisterType::B16, PTXRegisterSpace::Reg); if(numRegs > 0) os << "\t.reg .b16 %rh<" << numRegs << ">;\n"; // i32 - numRegs = MFI->getNumRegistersForClass(PTX::RegI32RegisterClass); + numRegs = MFI->countRegisters(PTXRegisterType::B32, PTXRegisterSpace::Reg); if(numRegs > 0) os << "\t.reg .b32 %r<" << numRegs << ">;\n"; // i64 - numRegs = MFI->getNumRegistersForClass(PTX::RegI64RegisterClass); + numRegs = MFI->countRegisters(PTXRegisterType::B64, PTXRegisterSpace::Reg); if(numRegs > 0) os << "\t.reg .b64 %rd<" << numRegs << ">;\n"; // f32 - numRegs = MFI->getNumRegistersForClass(PTX::RegF32RegisterClass); + numRegs = MFI->countRegisters(PTXRegisterType::F32, PTXRegisterSpace::Reg); if(numRegs > 0) os << "\t.reg .f32 %f<" << numRegs << ">;\n"; // f64 - numRegs = MFI->getNumRegistersForClass(PTX::RegF64RegisterClass); + numRegs = MFI->countRegisters(PTXRegisterType::F64, PTXRegisterSpace::Reg); if(numRegs > 0) os << "\t.reg .f64 %fd<" << numRegs << ">;\n"; @@ -368,7 +368,6 @@ const PTXParamManager &PM = MFI->getParamManager(); const bool isKernel = MFI->isKernel(); const PTXSubtarget& ST = TM.getSubtarget(); - const MachineRegisterInfo& MRI = MF->getRegInfo(); SmallString<128> decl; raw_svector_ostream os(decl); @@ -391,7 +390,7 @@ if (i != b) os << ", "; - os << ".reg ." << getRegisterTypeName(*i, MRI) << ' ' + os << ".reg " << getRegisterTypeName(MFI->getRegisterType(*i)) << ' ' << MFI->getRegisterName(*i); } } @@ -450,7 +449,7 @@ if (i != b) os << ", "; - os << ".reg ." << getRegisterTypeName(*i, MRI) << ' ' + os << ".reg " << getRegisterTypeName(MFI->getRegisterType(*i)) << ' ' << MFI->getRegisterName(*i); } } @@ -521,34 +520,14 @@ MCOperand PTXAsmPrinter::lowerOperand(const MachineOperand &MO) { MCOperand MCOp; const PTXMachineFunctionInfo *MFI = MF->getInfo(); - const MachineRegisterInfo& MRI = MF->getRegInfo(); - const TargetRegisterClass* TRC; - unsigned RegType; - unsigned RegOffset; unsigned EncodedReg; switch (MO.getType()) { default: llvm_unreachable("Unknown operand type"); case MachineOperand::MO_Register: if (MO.getReg() > 0) { - TRC = MRI.getRegClass(MO.getReg()); - // Determine which PTX register type to use - if (TRC == PTX::RegPredRegisterClass) - RegType = PTXRegisterType::Pred; - else if (TRC == PTX::RegI16RegisterClass) - RegType = PTXRegisterType::B16; - else if (TRC == PTX::RegI32RegisterClass) - RegType = PTXRegisterType::B32; - else if (TRC == PTX::RegI64RegisterClass) - RegType = PTXRegisterType::B64; - else if (TRC == PTX::RegF32RegisterClass) - RegType = PTXRegisterType::F32; - else if (TRC == PTX::RegF64RegisterClass) - RegType = PTXRegisterType::F64; - // Determine our virtual register offset - RegOffset = MFI->getOffsetForRegister(TRC, MO.getReg()); // Encode the register - EncodedReg = (RegOffset << 4) | RegType; + EncodedReg = MFI->getEncodedRegister(MO.getReg()); } else { EncodedReg = 0; } Modified: llvm/trunk/lib/Target/PTX/PTXISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PTX/PTXISelLowering.cpp?rev=145947&r1=145946&r2=145947&view=diff ============================================================================== --- llvm/trunk/lib/Target/PTX/PTXISelLowering.cpp (original) +++ llvm/trunk/lib/Target/PTX/PTXISelLowering.cpp Tue Dec 6 11:39:48 2011 @@ -243,6 +243,30 @@ for (unsigned i = 0, e = Ins.size(); i != e; ++i) { EVT RegVT = Ins[i].VT; TargetRegisterClass* TRC = getRegClassFor(RegVT); + unsigned RegType; + + // Determine which register class we need + if (RegVT == MVT::i1) { + RegType = PTXRegisterType::Pred; + } + else if (RegVT == MVT::i16) { + RegType = PTXRegisterType::B16; + } + else if (RegVT == MVT::i32) { + RegType = PTXRegisterType::B32; + } + else if (RegVT == MVT::i64) { + RegType = PTXRegisterType::B64; + } + else if (RegVT == MVT::f32) { + RegType = PTXRegisterType::F32; + } + else if (RegVT == MVT::f64) { + RegType = PTXRegisterType::F64; + } + else { + llvm_unreachable("Unknown parameter type"); + } // Use a unique index in the instruction to prevent instruction folding. // Yes, this is a hack. @@ -253,7 +277,7 @@ InVals.push_back(ArgValue); - MFI->addArgReg(Reg); + MFI->addRegister(Reg, RegType, PTXRegisterSpace::Argument); } } @@ -304,25 +328,32 @@ for (unsigned i = 0, e = Outs.size(); i != e; ++i) { EVT RegVT = Outs[i].VT; TargetRegisterClass* TRC = 0; + unsigned RegType; // Determine which register class we need if (RegVT == MVT::i1) { TRC = PTX::RegPredRegisterClass; + RegType = PTXRegisterType::Pred; } else if (RegVT == MVT::i16) { TRC = PTX::RegI16RegisterClass; + RegType = PTXRegisterType::B16; } else if (RegVT == MVT::i32) { TRC = PTX::RegI32RegisterClass; + RegType = PTXRegisterType::B32; } else if (RegVT == MVT::i64) { TRC = PTX::RegI64RegisterClass; + RegType = PTXRegisterType::B64; } else if (RegVT == MVT::f32) { TRC = PTX::RegF32RegisterClass; + RegType = PTXRegisterType::F32; } else if (RegVT == MVT::f64) { TRC = PTX::RegF64RegisterClass; + RegType = PTXRegisterType::F64; } else { llvm_unreachable("Unknown parameter type"); @@ -335,7 +366,7 @@ Chain = DAG.getNode(PTXISD::WRITE_PARAM, dl, MVT::Other, Copy, OutReg); - MFI->addRetReg(Reg); + MFI->addRegister(Reg, RegType, PTXRegisterSpace::Return); } } Modified: llvm/trunk/lib/Target/PTX/PTXInstrInfo.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PTX/PTXInstrInfo.td?rev=145947&r1=145946&r2=145947&view=diff ============================================================================== --- llvm/trunk/lib/Target/PTX/PTXInstrInfo.td (original) +++ llvm/trunk/lib/Target/PTX/PTXInstrInfo.td Tue Dec 6 11:39:48 2011 @@ -825,17 +825,17 @@ ///===- Parameter Passing Pseudo-Instructions -----------------------------===// def READPARAMPRED : InstPTX<(outs RegPred:$a), (ins i32imm:$b), - "mov.pred\t$a, %param$b", []>; + "mov.pred\t$a, %arg$b", []>; def READPARAMI16 : InstPTX<(outs RegI16:$a), (ins i32imm:$b), - "mov.b16\t$a, %param$b", []>; + "mov.b16\t$a, %arg$b", []>; def READPARAMI32 : InstPTX<(outs RegI32:$a), (ins i32imm:$b), - "mov.b32\t$a, %param$b", []>; + "mov.b32\t$a, %arg$b", []>; def READPARAMI64 : InstPTX<(outs RegI64:$a), (ins i32imm:$b), - "mov.b64\t$a, %param$b", []>; + "mov.b64\t$a, %arg$b", []>; def READPARAMF32 : InstPTX<(outs RegF32:$a), (ins i32imm:$b), - "mov.f32\t$a, %param$b", []>; + "mov.f32\t$a, %arg$b", []>; def READPARAMF64 : InstPTX<(outs RegF64:$a), (ins i32imm:$b), - "mov.f64\t$a, %param$b", []>; + "mov.f64\t$a, %arg$b", []>; def WRITEPARAMPRED : InstPTX<(outs), (ins RegPred:$a), "//w", []>; def WRITEPARAMI16 : InstPTX<(outs), (ins RegI16:$a), "//w", []>; Modified: llvm/trunk/lib/Target/PTX/PTXMFInfoExtract.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PTX/PTXMFInfoExtract.cpp?rev=145947&r1=145946&r2=145947&view=diff ============================================================================== --- llvm/trunk/lib/Target/PTX/PTXMFInfoExtract.cpp (original) +++ llvm/trunk/lib/Target/PTX/PTXMFInfoExtract.cpp Tue Dec 6 11:39:48 2011 @@ -58,7 +58,20 @@ for (unsigned i = 0; i < MRI.getNumVirtRegs(); ++i) { unsigned Reg = TargetRegisterInfo::index2VirtReg(i); const TargetRegisterClass *TRC = MRI.getRegClass(Reg); - MFI->addVirtualRegister(TRC, Reg); + unsigned RegType; + if (TRC == PTX::RegPredRegisterClass) + RegType = PTXRegisterType::Pred; + else if (TRC == PTX::RegI16RegisterClass) + RegType = PTXRegisterType::B16; + else if (TRC == PTX::RegI32RegisterClass) + RegType = PTXRegisterType::B32; + else if (TRC == PTX::RegI64RegisterClass) + RegType = PTXRegisterType::B64; + else if (TRC == PTX::RegF32RegisterClass) + RegType = PTXRegisterType::F32; + else if (TRC == PTX::RegF64RegisterClass) + RegType = PTXRegisterType::F64; + MFI->addRegister(Reg, RegType, PTXRegisterSpace::Reg); } return false; Modified: llvm/trunk/lib/Target/PTX/PTXMachineFunctionInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PTX/PTXMachineFunctionInfo.h?rev=145947&r1=145946&r2=145947&view=diff ============================================================================== --- llvm/trunk/lib/Target/PTX/PTXMachineFunctionInfo.h (original) +++ llvm/trunk/lib/Target/PTX/PTXMachineFunctionInfo.h Tue Dec 6 11:39:48 2011 @@ -35,15 +35,22 @@ DenseSet RegArgs; DenseSet RegRets; - typedef std::vector RegisterList; - typedef DenseMap RegisterMap; - typedef DenseMap RegisterNameMap; typedef DenseMap FrameMap; - RegisterMap UsedRegs; - RegisterNameMap RegNames; FrameMap FrameSymbols; + struct RegisterInfo { + unsigned Reg; + unsigned Type; + unsigned Space; + unsigned Offset; + unsigned Encoded; + }; + + typedef DenseMap RegisterInfoMap; + + RegisterInfoMap RegInfo; + PTXParamManager ParamManager; public: @@ -51,13 +58,7 @@ PTXMachineFunctionInfo(MachineFunction &MF) : IsKernel(false) { - UsedRegs[PTX::RegPredRegisterClass] = RegisterList(); - UsedRegs[PTX::RegI16RegisterClass] = RegisterList(); - UsedRegs[PTX::RegI32RegisterClass] = RegisterList(); - UsedRegs[PTX::RegI64RegisterClass] = RegisterList(); - UsedRegs[PTX::RegF32RegisterClass] = RegisterList(); - UsedRegs[PTX::RegF64RegisterClass] = RegisterList(); - } + } /// getParamManager - Returns the PTXParamManager instance for this function. PTXParamManager& getParamManager() { return ParamManager; } @@ -78,81 +79,106 @@ reg_iterator retreg_begin() const { return RegRets.begin(); } reg_iterator retreg_end() const { return RegRets.end(); } + /// addRegister - Adds a virtual register to the set of all used registers + void addRegister(unsigned Reg, unsigned RegType, unsigned RegSpace) { + if (!RegInfo.count(Reg)) { + RegisterInfo Info; + Info.Reg = Reg; + Info.Type = RegType; + Info.Space = RegSpace; + + // Determine register offset + Info.Offset = 0; + for(RegisterInfoMap::const_iterator i = RegInfo.begin(), + e = RegInfo.end(); i != e; ++i) { + const RegisterInfo& RI = i->second; + if (RI.Space == RegSpace) + if (RI.Space != PTXRegisterSpace::Reg || RI.Type == Info.Type) + Info.Offset++; + } + + // Encode the register data into a single register number + Info.Encoded = (Info.Offset << 6) | (Info.Type << 3) | Info.Space; + + RegInfo[Reg] = Info; + + if (RegSpace == PTXRegisterSpace::Argument) + RegArgs.insert(Reg); + else if (RegSpace == PTXRegisterSpace::Return) + RegRets.insert(Reg); + } + } + + /// countRegisters - Returns the number of registers of the given type and + /// space. + unsigned countRegisters(unsigned RegType, unsigned RegSpace) const { + unsigned Count = 0; + for(RegisterInfoMap::const_iterator i = RegInfo.begin(), e = RegInfo.end(); + i != e; ++i) { + const RegisterInfo& RI = i->second; + if (RI.Type == RegType && RI.Space == RegSpace) + Count++; + } + return Count; + } + + /// getEncodedRegister - Returns the encoded value of the register. + unsigned getEncodedRegister(unsigned Reg) const { + return RegInfo.lookup(Reg).Encoded; + } + /// addRetReg - Adds a register to the set of return-value registers. void addRetReg(unsigned Reg) { if (!RegRets.count(Reg)) { RegRets.insert(Reg); - std::string name; - name = "%ret"; - name += utostr(RegRets.size() - 1); - RegNames[Reg] = name; } } /// addArgReg - Adds a register to the set of function argument registers. void addArgReg(unsigned Reg) { RegArgs.insert(Reg); - std::string name; - name = "%param"; - name += utostr(RegArgs.size() - 1); - RegNames[Reg] = name; - } - - /// addVirtualRegister - Adds a virtual register to the set of all used - /// registers in the function. - void addVirtualRegister(const TargetRegisterClass *TRC, unsigned Reg) { - std::string name; - - // Do not count registers that are argument/return registers. - if (!RegRets.count(Reg) && !RegArgs.count(Reg)) { - UsedRegs[TRC].push_back(Reg); - if (TRC == PTX::RegPredRegisterClass) - name = "%p"; - else if (TRC == PTX::RegI16RegisterClass) - name = "%rh"; - else if (TRC == PTX::RegI32RegisterClass) - name = "%r"; - else if (TRC == PTX::RegI64RegisterClass) - name = "%rd"; - else if (TRC == PTX::RegF32RegisterClass) - name = "%f"; - else if (TRC == PTX::RegF64RegisterClass) - name = "%fd"; - else - llvm_unreachable("Invalid register class"); - - name += utostr(UsedRegs[TRC].size() - 1); - RegNames[Reg] = name; - } } /// getRegisterName - Returns the name of the specified virtual register. This /// name is used during PTX emission. - const char *getRegisterName(unsigned Reg) const { - if (RegNames.count(Reg)) - return RegNames.find(Reg)->second.c_str(); + std::string getRegisterName(unsigned Reg) const { + if (RegInfo.count(Reg)) { + const RegisterInfo& RI = RegInfo.lookup(Reg); + std::string Name; + raw_string_ostream NameStr(Name); + decodeRegisterName(NameStr, RI.Encoded); + NameStr.flush(); + return Name; + } else if (Reg == PTX::NoRegister) return "%noreg"; else llvm_unreachable("Register not in register name map"); } - /// getNumRegistersForClass - Returns the number of virtual registers that are - /// used for the specified register class. - unsigned getNumRegistersForClass(const TargetRegisterClass *TRC) const { - return UsedRegs.lookup(TRC).size(); + /// getEncodedRegisterName - Returns the name of the encoded register. + std::string getEncodedRegisterName(unsigned EncodedReg) const { + std::string Name; + raw_string_ostream NameStr(Name); + decodeRegisterName(NameStr, EncodedReg); + NameStr.flush(); + return Name; + } + + /// getRegisterType - Returns the type of the specified virtual register. + unsigned getRegisterType(unsigned Reg) const { + if (RegInfo.count(Reg)) + return RegInfo.lookup(Reg).Type; + else + llvm_unreachable("Unknown register"); } /// getOffsetForRegister - Returns the offset of the virtual register - unsigned getOffsetForRegister(const TargetRegisterClass *TRC, - unsigned Reg) const { - const RegisterList &RegList = UsedRegs.lookup(TRC); - for (unsigned i = 0, e = RegList.size(); i != e; ++i) { - if (RegList[i] == Reg) - return i; - } - //llvm_unreachable("Unknown virtual register"); - return 0; + unsigned getOffsetForRegister(unsigned Reg) const { + if (RegInfo.count(Reg)) + return RegInfo.lookup(Reg).Offset; + else + return 0; } /// getFrameSymbol - Returns the symbol name for the given FrameIndex. Modified: llvm/trunk/test/CodeGen/PTX/mov.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PTX/mov.ll?rev=145947&r1=145946&r2=145947&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/PTX/mov.ll (original) +++ llvm/trunk/test/CodeGen/PTX/mov.ll Tue Dec 6 11:39:48 2011 @@ -31,31 +31,31 @@ } define ptx_device i16 @t2_u16(i16 %x) { -; CHECK: mov.b16 %ret{{[0-9]+}}, %param{{[0-9]+}}; +; CHECK: mov.b16 %ret{{[0-9]+}}, %arg{{[0-9]+}}; ; CHECK: ret; ret i16 %x } define ptx_device i32 @t2_u32(i32 %x) { -; CHECK: mov.b32 %ret{{[0-9]+}}, %param{{[0-9]+}}; +; CHECK: mov.b32 %ret{{[0-9]+}}, %arg{{[0-9]+}}; ; CHECK: ret; ret i32 %x } define ptx_device i64 @t2_u64(i64 %x) { -; CHECK: mov.b64 %ret{{[0-9]+}}, %param{{[0-9]+}}; +; CHECK: mov.b64 %ret{{[0-9]+}}, %arg{{[0-9]+}}; ; CHECK: ret; ret i64 %x } define ptx_device float @t3_f32(float %x) { -; CHECK: mov.f32 %ret{{[0-9]+}}, %param{{[0-9]+}}; +; CHECK: mov.f32 %ret{{[0-9]+}}, %arg{{[0-9]+}}; ; CHECK: ret; ret float %x } define ptx_device double @t3_f64(double %x) { -; CHECK: mov.f64 %ret{{[0-9]+}}, %param{{[0-9]+}}; +; CHECK: mov.f64 %ret{{[0-9]+}}, %arg{{[0-9]+}}; ; CHECK: ret; ret double %x } Modified: llvm/trunk/test/CodeGen/PTX/parameter-order.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PTX/parameter-order.ll?rev=145947&r1=145946&r2=145947&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/PTX/parameter-order.ll (original) +++ llvm/trunk/test/CodeGen/PTX/parameter-order.ll Tue Dec 6 11:39:48 2011 @@ -1,6 +1,6 @@ ; RUN: llc < %s -march=ptx32 | FileCheck %s -; CHECK: .func (.reg .b32 %ret{{[0-9]+}}) test_parameter_order (.reg .b32 %param{{[0-9]+}}, .reg .b32 %param{{[0-9]+}}, .reg .b32 %param{{[0-9]+}}, .reg .b32 %param{{[0-9]+}}) +; CHECK: .func (.reg .b32 %ret{{[0-9]+}}) test_parameter_order (.reg .f32 %arg{{[0-9]+}}, .reg .b32 %arg{{[0-9]+}}, .reg .b32 %arg{{[0-9]+}}, .reg .f32 %arg{{[0-9]+}}) define ptx_device i32 @test_parameter_order(float %a, i32 %b, i32 %c, float %d) { ; CHECK: sub.u32 %ret{{[0-9]+}}, %r{{[0-9]+}}, %r{{[0-9]+}} %result = sub i32 %b, %c From hfinkel at anl.gov Tue Dec 6 14:52:56 2011 From: hfinkel at anl.gov (Hal Finkel) Date: Tue, 06 Dec 2011 20:52:56 -0000 Subject: [llvm-commits] [llvm] r145960 - /llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.cpp Message-ID: <20111206205256.87C5C1BE003@llvm.org> Author: hfinkel Date: Tue Dec 6 14:52:56 2011 New Revision: 145960 URL: http://llvm.org/viewvc/llvm-project?rev=145960&view=rev Log: remove old FIXME Modified: llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.cpp Modified: llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.cpp?rev=145960&r1=145959&r2=145960&view=diff ============================================================================== --- llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.cpp (original) +++ llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.cpp Tue Dec 6 14:52:56 2011 @@ -596,7 +596,6 @@ // offset in. // FIXME: figure out what SPAdj is doing here. - // FIXME (64-bit): Use "findScratchRegister". unsigned SReg; if (requiresRegisterScavenging(MF)) SReg = findScratchRegister(II, RS, &PPC::GPRCRegClass, SPAdj); From jstaszak at apple.com Tue Dec 6 14:56:36 2011 From: jstaszak at apple.com (Jakub Staszak) Date: Tue, 06 Dec 2011 20:56:36 -0000 Subject: [llvm-commits] [llvm] r145964 - /llvm/trunk/docs/ReleaseNotes.html Message-ID: <20111206205636.794091BE003@llvm.org> Author: kuba Date: Tue Dec 6 14:56:36 2011 New Revision: 145964 URL: http://llvm.org/viewvc/llvm-project?rev=145964&view=rev Log: Add link to llvm.expect in Release Notes. Modified: llvm/trunk/docs/ReleaseNotes.html Modified: llvm/trunk/docs/ReleaseNotes.html URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/ReleaseNotes.html?rev=145964&r1=145963&r2=145964&view=diff ============================================================================== --- llvm/trunk/docs/ReleaseNotes.html (original) +++ llvm/trunk/docs/ReleaseNotes.html Tue Dec 6 14:56:36 2011 @@ -821,8 +821,9 @@
    • A new llvm.fma intrinsic directly represents floating point multiply accumulate operations without an intermediate rounding stage.
      • -
    • A new llvm.expect intrinsic allows a frontend to express expected control - flow (and the __builtin_expect builtin from GNU C).
      • +
    • A new llvm.expect intrinsic allows a + frontend to express expected control flow (and the __builtin_expect builtin + from GNU C).
    • The llvm.prefetch intrinsic now takes a 4th argument that specifies whether the prefetch happens from the icache or dcache.
      • From justin.holewinski at gmail.com Tue Dec 6 11:39:46 2011 From: justin.holewinski at gmail.com (Justin Holewinski) Date: Tue, 06 Dec 2011 17:39:46 -0000 Subject: [llvm-commits] [llvm] r145946 - in /llvm/trunk/lib/Target/PTX: InstPrinter/PTXInstPrinter.cpp MCTargetDesc/PTXBaseInfo.h PTXAsmPrinter.cpp PTXMachineFunctionInfo.h Message-ID: <20111206173946.557221BE003@llvm.org> Author: jholewinski Date: Tue Dec 6 11:39:46 2011 New Revision: 145946 URL: http://llvm.org/viewvc/llvm-project?rev=145946&view=rev Log: PTX: Encode registers as unsigned values in the MC asm printer instead of using external symbols Modified: llvm/trunk/lib/Target/PTX/InstPrinter/PTXInstPrinter.cpp llvm/trunk/lib/Target/PTX/MCTargetDesc/PTXBaseInfo.h llvm/trunk/lib/Target/PTX/PTXAsmPrinter.cpp llvm/trunk/lib/Target/PTX/PTXMachineFunctionInfo.h Modified: llvm/trunk/lib/Target/PTX/InstPrinter/PTXInstPrinter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PTX/InstPrinter/PTXInstPrinter.cpp?rev=145946&r1=145945&r2=145946&view=diff ============================================================================== --- llvm/trunk/lib/Target/PTX/InstPrinter/PTXInstPrinter.cpp (original) +++ llvm/trunk/lib/Target/PTX/InstPrinter/PTXInstPrinter.cpp Tue Dec 6 11:39:46 2011 @@ -38,7 +38,37 @@ } void PTXInstPrinter::printRegName(raw_ostream &OS, unsigned RegNo) const { - OS << getRegisterName(RegNo); + // Decode the register number into type and offset + unsigned RegType = RegNo & 0xF; + unsigned RegOffset = RegNo >> 4; + + // Print the register + OS << "%"; + + switch (RegType) { + default: + llvm_unreachable("Unknown register type!"); + case PTXRegisterType::Pred: + OS << "p"; + break; + case PTXRegisterType::B16: + OS << "rh"; + break; + case PTXRegisterType::B32: + OS << "r"; + break; + case PTXRegisterType::B64: + OS << "rd"; + break; + case PTXRegisterType::F32: + OS << "f"; + break; + case PTXRegisterType::F64: + OS << "fd"; + break; + } + + OS << RegOffset; } void PTXInstPrinter::printInst(const MCInst *MI, raw_ostream &O, @@ -139,6 +169,8 @@ } else { O << "0000000000000000"; } + } else if (Op.isReg()) { + printRegName(O, Op.getReg()); } else { assert(Op.isExpr() && "unknown operand kind in printOperand"); const MCExpr *Expr = Op.getExpr(); Modified: llvm/trunk/lib/Target/PTX/MCTargetDesc/PTXBaseInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PTX/MCTargetDesc/PTXBaseInfo.h?rev=145946&r1=145945&r2=145946&view=diff ============================================================================== --- llvm/trunk/lib/Target/PTX/MCTargetDesc/PTXBaseInfo.h (original) +++ llvm/trunk/lib/Target/PTX/MCTargetDesc/PTXBaseInfo.h Tue Dec 6 11:39:46 2011 @@ -57,6 +57,18 @@ RndPosInfInt = 10 // .rpi }; } // namespace PTXII + + namespace PTXRegisterType { + // Register type encoded in MCOperands + enum { + Pred = 0, + B16, + B32, + B64, + F32, + F64 + }; + } // namespace PTXRegisterType } // namespace llvm #endif Modified: llvm/trunk/lib/Target/PTX/PTXAsmPrinter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PTX/PTXAsmPrinter.cpp?rev=145946&r1=145945&r2=145946&view=diff ============================================================================== --- llvm/trunk/lib/Target/PTX/PTXAsmPrinter.cpp (original) +++ llvm/trunk/lib/Target/PTX/PTXAsmPrinter.cpp Tue Dec 6 11:39:46 2011 @@ -521,20 +521,38 @@ MCOperand PTXAsmPrinter::lowerOperand(const MachineOperand &MO) { MCOperand MCOp; const PTXMachineFunctionInfo *MFI = MF->getInfo(); - const MCExpr *Expr; - const char *RegSymbolName; + const MachineRegisterInfo& MRI = MF->getRegInfo(); + const TargetRegisterClass* TRC; + unsigned RegType; + unsigned RegOffset; + unsigned EncodedReg; switch (MO.getType()) { default: llvm_unreachable("Unknown operand type"); case MachineOperand::MO_Register: - // We create register operands as symbols, since the PTXInstPrinter class - // has no way to map virtual registers back to a name without some ugly - // hacks. - // FIXME: Figure out a better way to handle virtual register naming. - RegSymbolName = MFI->getRegisterName(MO.getReg()); - Expr = MCSymbolRefExpr::Create(RegSymbolName, MCSymbolRefExpr::VK_None, - OutContext); - MCOp = MCOperand::CreateExpr(Expr); + if (MO.getReg() > 0) { + TRC = MRI.getRegClass(MO.getReg()); + // Determine which PTX register type to use + if (TRC == PTX::RegPredRegisterClass) + RegType = PTXRegisterType::Pred; + else if (TRC == PTX::RegI16RegisterClass) + RegType = PTXRegisterType::B16; + else if (TRC == PTX::RegI32RegisterClass) + RegType = PTXRegisterType::B32; + else if (TRC == PTX::RegI64RegisterClass) + RegType = PTXRegisterType::B64; + else if (TRC == PTX::RegF32RegisterClass) + RegType = PTXRegisterType::F32; + else if (TRC == PTX::RegF64RegisterClass) + RegType = PTXRegisterType::F64; + // Determine our virtual register offset + RegOffset = MFI->getOffsetForRegister(TRC, MO.getReg()); + // Encode the register + EncodedReg = (RegOffset << 4) | RegType; + } else { + EncodedReg = 0; + } + MCOp = MCOperand::CreateReg(EncodedReg); break; case MachineOperand::MO_Immediate: MCOp = MCOperand::CreateImm(MO.getImm()); Modified: llvm/trunk/lib/Target/PTX/PTXMachineFunctionInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PTX/PTXMachineFunctionInfo.h?rev=145946&r1=145945&r2=145946&view=diff ============================================================================== --- llvm/trunk/lib/Target/PTX/PTXMachineFunctionInfo.h (original) +++ llvm/trunk/lib/Target/PTX/PTXMachineFunctionInfo.h Tue Dec 6 11:39:46 2011 @@ -143,18 +143,30 @@ return UsedRegs.lookup(TRC).size(); } + /// getOffsetForRegister - Returns the offset of the virtual register + unsigned getOffsetForRegister(const TargetRegisterClass *TRC, + unsigned Reg) const { + const RegisterList &RegList = UsedRegs.lookup(TRC); + for (unsigned i = 0, e = RegList.size(); i != e; ++i) { + if (RegList[i] == Reg) + return i; + } + //llvm_unreachable("Unknown virtual register"); + return 0; + } + /// getFrameSymbol - Returns the symbol name for the given FrameIndex. const char* getFrameSymbol(int FrameIndex) { if (FrameSymbols.count(FrameIndex)) { return FrameSymbols.lookup(FrameIndex).c_str(); } else { - std::string Name = "__local"; - Name += utostr(FrameIndex); + std::string Name = "__local"; + Name += utostr(FrameIndex); // The whole point of caching this name is to ensure the pointer we pass // to any getExternalSymbol() calls will remain valid for the lifetime of // the back-end instance. This is to work around an issue in SelectionDAG // where symbol names are expected to be life-long strings. - FrameSymbols[FrameIndex] = Name; + FrameSymbols[FrameIndex] = Name; return FrameSymbols[FrameIndex].c_str(); } } From hfinkel at anl.gov Tue Dec 6 14:55:46 2011 From: hfinkel at anl.gov (Hal Finkel) Date: Tue, 06 Dec 2011 20:55:46 -0000 Subject: [llvm-commits] [llvm] r145963 - in /llvm/trunk/test/CodeGen/PowerPC: 2010-02-12-saveCR.ll ppc32-vaarg.ll Message-ID: <20111206205546.6AAC71BE003@llvm.org> Author: hfinkel Date: Tue Dec 6 14:55:46 2011 New Revision: 145963 URL: http://llvm.org/viewvc/llvm-project?rev=145963&view=rev Log: delaying restore-cr changed assigned registers in some tests Modified: llvm/trunk/test/CodeGen/PowerPC/2010-02-12-saveCR.ll llvm/trunk/test/CodeGen/PowerPC/ppc32-vaarg.ll Modified: llvm/trunk/test/CodeGen/PowerPC/2010-02-12-saveCR.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/2010-02-12-saveCR.ll?rev=145963&r1=145962&r2=145963&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/PowerPC/2010-02-12-saveCR.ll (original) +++ llvm/trunk/test/CodeGen/PowerPC/2010-02-12-saveCR.ll Tue Dec 6 14:55:46 2011 @@ -21,9 +21,9 @@ return: ; preds = %entry ;CHECK: lis r3, 1 ;CHECK: ori r3, r3, 34524 -;CHECK: lwzx r2, r1, r3 -;CHECK: rlwinm r2, r2, 24, 0, 31 -;CHECK: mtcrf 32, r2 +;CHECK: lwzx r3, r1, r3 +;CHECK: rlwinm r3, r3, 24, 0, 31 +;CHECK: mtcrf 32, r3 ret void } Modified: llvm/trunk/test/CodeGen/PowerPC/ppc32-vaarg.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/ppc32-vaarg.ll?rev=145963&r1=145962&r2=145963&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/PowerPC/ppc32-vaarg.ll (original) +++ llvm/trunk/test/CodeGen/PowerPC/ppc32-vaarg.ll Tue Dec 6 14:55:46 2011 @@ -52,8 +52,8 @@ ; CHECK-NEXT: slwi 5, 3, 2 ; CHECK-NEXT: lwz 6, -16(1) ; CHECK-NEXT: add 5, 6, 5 -; CHECK-NEXT: lwz 0, -36(1) -; CHECK-NEXT: mtcrf 128, 0 +; CHECK-NEXT: lwz 3, -36(1) +; CHECK-NEXT: mtcrf 128, 3 ; CHECK-NEXT: stw 5, -40(1) ; CHECK-NEXT: blt 0, .LBB0_6 ; CHECK-NEXT: # BB#5: # %entry @@ -97,8 +97,8 @@ ; CHECK-NEXT: lwz 6, -56(1) ; CHECK-NEXT: add 5, 6, 5 ; CHECK-NEXT: addi 5, 5, 32 -; CHECK-NEXT: lwz 0, -64(1) -; CHECK-NEXT: mtcrf 128, 0 +; CHECK-NEXT: lwz 3, -64(1) +; CHECK-NEXT: mtcrf 128, 3 ; CHECK-NEXT: stw 5, -68(1) ; CHECK-NEXT: blt 0, .LBB0_10 ; CHECK-NEXT: # BB#9: # %entry @@ -139,8 +139,8 @@ ; CHECK-NEXT: slwi 5, 3, 2 ; CHECK-NEXT: lwz 6, -76(1) ; CHECK-NEXT: add 5, 6, 5 -; CHECK-NEXT: lwz 0, -80(1) -; CHECK-NEXT: mtcrf 128, 0 +; CHECK-NEXT: lwz 3, -80(1) +; CHECK-NEXT: mtcrf 128, 3 ; CHECK-NEXT: stw 5, -96(1) ; CHECK-NEXT: blt 0, .LBB0_14 ; CHECK-NEXT: # BB#13: # %entry From jcarter at mips.com Tue Dec 6 14:47:56 2011 From: jcarter at mips.com (Carter, Jack) Date: Tue, 6 Dec 2011 20:47:56 +0000 Subject: [llvm-commits] [llvm] r145912 - in /llvm/trunk/lib/Target/Mips: MipsInstrFormats.td MipsInstrInfo.cpp MipsInstrInfo.td In-Reply-To: <3DCFBAAD-5552-41AF-BD8A-66E6524B56E8@apple.com> References: <20111206033449.22EBB2A6C12C@llvm.org> <86AC779C188FE74F88F6494478B46332E8B3F0@exchdb03.mips.com>, <3DCFBAAD-5552-41AF-BD8A-66E6524B56E8@apple.com> Message-ID: <86AC779C188FE74F88F6494478B46332E8B435@exchdb03.mips.com> Attached is a test case for the branch/jump patch. We overdid it and made all unconditional branches branches. The next patch addresses that and I will have a new test case for that which differentiates between static and pic compiles. Hey, it's my first test case submittal. I should be passing out cigars! Cheers, Jack ________________________________________ From: Chad Rosier [mcrosier at apple.com] Sent: Tuesday, December 06, 2011 10:46 AM To: Carter, Jack Cc: Bruno Cardoso Lopes; llvm-commits at cs.uiuc.edu Subject: Re: [llvm-commits] [llvm] r145912 - in /llvm/trunk/lib/Target/Mips: MipsInstrFormats.td MipsInstrInfo.cpp MipsInstrInfo.td On Dec 6, 2011, at 10:40 AM, Carter, Jack wrote: > The commit was after I left for home and I just got in again. No problem. > I am checking here for the correct form for a test case and will send it in. Sounds good. See http://llvm.org/docs/TestingGuide.html#rtcustom for more info on writing regression tests. You could also grep through lib/test/* for examples. Chad > Jack > ________________________________________ > From: Bruno Cardoso Lopes [bruno.cardoso at gmail.com] > Sent: Tuesday, December 06, 2011 9:59 AM > To: Chad Rosier; Carter, Jack > Cc: llvm-commits at cs.uiuc.edu > Subject: Re: [llvm-commits] [llvm] r145912 - in /llvm/trunk/lib/Target/Mips: MipsInstrFormats.td MipsInstrInfo.cpp MipsInstrInfo.td > > Still waiting from Jack Carter! Since it was commited yesterday, he > may be taking his time to do it. > > On Tue, Dec 6, 2011 at 3:39 PM, Chad Rosier wrote: >> Did the test case ever land? >> >> Chad >> >> On Dec 5, 2011, at 7:34 PM, Bruno Cardoso Lopes wrote: >> >>> Author: bruno >>> Date: Mon Dec 5 21:34:48 2011 >>> New Revision: 145912 >>> >>> URL: http://llvm.org/viewvc/llvm-project?rev=145912&view=rev >>> Log: >>> Use branches instead of jumps + variable cleanup. Testcase coming next. Patch by Jack Carter >>> >>> Modified: >>> llvm/trunk/lib/Target/Mips/MipsInstrFormats.td >>> llvm/trunk/lib/Target/Mips/MipsInstrInfo.cpp >>> llvm/trunk/lib/Target/Mips/MipsInstrInfo.td >>> >>> Modified: llvm/trunk/lib/Target/Mips/MipsInstrFormats.td >>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsInstrFormats.td?rev=145912&r1=145911&r2=145912&view=diff >>> ============================================================================== >>> --- llvm/trunk/lib/Target/Mips/MipsInstrFormats.td (original) >>> +++ llvm/trunk/lib/Target/Mips/MipsInstrFormats.td Mon Dec 5 21:34:48 2011 >>> @@ -115,7 +115,7 @@ >>> let Inst{15-0} = imm16; >>> } >>> >>> -class CBranchBase op, dag outs, dag ins, string asmstr, >>> +class BranchBase op, dag outs, dag ins, string asmstr, >>> list pattern, InstrItinClass itin>: >>> MipsInst >>> { >>> >>> Modified: llvm/trunk/lib/Target/Mips/MipsInstrInfo.cpp >>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsInstrInfo.cpp?rev=145912&r1=145911&r2=145912&view=diff >>> ============================================================================== >>> --- llvm/trunk/lib/Target/Mips/MipsInstrInfo.cpp (original) >>> +++ llvm/trunk/lib/Target/Mips/MipsInstrInfo.cpp Mon Dec 5 21:34:48 2011 >>> @@ -236,7 +236,7 @@ >>> Opc == Mips::BGEZ || Opc == Mips::BLTZ || Opc == Mips::BLEZ || >>> Opc == Mips::BEQ64 || Opc == Mips::BNE64 || Opc == Mips::BGTZ64 || >>> Opc == Mips::BGEZ64 || Opc == Mips::BLTZ64 || Opc == Mips::BLEZ64 || >>> - Opc == Mips::BC1T || Opc == Mips::BC1F || Opc == Mips::J) ? >>> + Opc == Mips::BC1T || Opc == Mips::BC1F || Opc == Mips::B) ? >>> Opc : 0; >>> } >>> >>> @@ -320,7 +320,7 @@ >>> // If there is only one terminator instruction, process it. >>> if (!SecondLastOpc) { >>> // Unconditional branch >>> - if (LastOpc == Mips::J) { >>> + if (LastOpc == Mips::B) { >>> TBB = LastInst->getOperand(0).getMBB(); >>> return false; >>> } >>> @@ -337,7 +337,7 @@ >>> >>> // If second to last instruction is an unconditional branch, >>> // analyze it and remove the last instruction. >>> - if (SecondLastOpc == Mips::J) { >>> + if (SecondLastOpc == Mips::B) { >>> // Return if the last instruction cannot be removed. >>> if (!AllowModify) >>> return true; >>> @@ -349,7 +349,7 @@ >>> >>> // Conditional branch followed by an unconditional branch. >>> // The last one must be unconditional. >>> - if (LastOpc != Mips::J) >>> + if (LastOpc != Mips::B) >>> return true; >>> >>> AnalyzeCondBr(SecondLastInst, SecondLastOpc, TBB, Cond); >>> @@ -391,14 +391,14 @@ >>> // Two-way Conditional branch. >>> if (FBB) { >>> BuildCondBr(MBB, TBB, DL, Cond); >>> - BuildMI(&MBB, DL, get(Mips::J)).addMBB(FBB); >>> + BuildMI(&MBB, DL, get(Mips::B)).addMBB(FBB); >>> return 2; >>> } >>> >>> // One way branch. >>> // Unconditional branch. >>> if (Cond.empty()) >>> - BuildMI(&MBB, DL, get(Mips::J)).addMBB(TBB); >>> + BuildMI(&MBB, DL, get(Mips::B)).addMBB(TBB); >>> else // Conditional branch. >>> BuildCondBr(MBB, TBB, DL, Cond); >>> return 1; >>> >>> Modified: llvm/trunk/lib/Target/Mips/MipsInstrInfo.td >>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsInstrInfo.td?rev=145912&r1=145911&r2=145912&view=diff >>> ============================================================================== >>> --- llvm/trunk/lib/Target/Mips/MipsInstrInfo.td (original) >>> +++ llvm/trunk/lib/Target/Mips/MipsInstrInfo.td Mon Dec 5 21:34:48 2011 >>> @@ -380,21 +380,13 @@ >>> let isPseudo = Pseudo; >>> } >>> >>> -// Memory Load/Store >>> +// Unaligned Memory Load/Store >>> let canFoldAsLoad = 1 in >>> -class LoadX op, RegisterClass RC, >>> - Operand MemOpnd>: >>> - FMem>> - "", >>> - [], IILoad> { >>> -} >>> +class LoadUnAlign op, RegisterClass RC, Operand MemOpnd>: >>> + FMem {} >>> >>> -class StoreX op, RegisterClass RC, >>> - Operand MemOpnd>: >>> - FMem>> - "", >>> - [], IIStore> { >>> -} >>> +class StoreUnAlign op, RegisterClass RC, Operand MemOpnd>: >>> + FMem {} >>> >>> // 32-bit load. >>> multiclass LoadM32 op, string instr_asm, PatFrag OpNode, >>> @@ -415,10 +407,10 @@ >>> } >>> >>> // 32-bit load. >>> -multiclass LoadX32 op> { >>> - def #NAME# : LoadX, >>> +multiclass LoadUnAlign32 op> { >>> + def #NAME# : LoadUnAlign, >>> Requires<[NotN64]>; >>> - def _P8 : LoadX, >>> + def _P8 : LoadUnAlign, >>> Requires<[IsN64]>; >>> } >>> // 32-bit store. >>> @@ -440,18 +432,18 @@ >>> } >>> >>> // 32-bit store. >>> -multiclass StoreX32 op> { >>> - def #NAME# : StoreX, >>> +multiclass StoreUnAlign32 op> { >>> + def #NAME# : StoreUnAlign, >>> Requires<[NotN64]>; >>> - def _P8 : StoreX, >>> + def _P8 : StoreUnAlign, >>> Requires<[IsN64]>; >>> } >>> >>> // Conditional Branch >>> class CBranch op, string instr_asm, PatFrag cond_op, RegisterClass RC>: >>> - CBranchBase>> - !strconcat(instr_asm, "\t$rs, $rt, $imm16"), >>> - [(brcond (i32 (cond_op RC:$rs, RC:$rt)), bb:$imm16)], IIBranch> { >>> + BranchBase>> + !strconcat(instr_asm, "\t$rs, $rt, $imm16"), >>> + [(brcond (i32 (cond_op RC:$rs, RC:$rt)), bb:$imm16)], IIBranch> { >>> let isBranch = 1; >>> let isTerminator = 1; >>> let hasDelaySlot = 1; >>> @@ -459,9 +451,9 @@ >>> >>> class CBranchZero op, bits<5> _rt, string instr_asm, PatFrag cond_op, >>> RegisterClass RC>: >>> - CBranchBase>> - !strconcat(instr_asm, "\t$rs, $imm16"), >>> - [(brcond (i32 (cond_op RC:$rs, 0)), bb:$imm16)], IIBranch> { >>> + BranchBase>> + !strconcat(instr_asm, "\t$rs, $imm16"), >>> + [(brcond (i32 (cond_op RC:$rs, 0)), bb:$imm16)], IIBranch> { >>> let rt = _rt; >>> let isBranch = 1; >>> let isTerminator = 1; >>> @@ -486,10 +478,16 @@ >>> IIAlu>; >>> >>> // Unconditional branch >>> -let isBranch=1, isTerminator=1, isBarrier=1, hasDelaySlot = 1 in >>> -class JumpFJ op, string instr_asm>: >>> - FJ>> - !strconcat(instr_asm, "\t$target"), [(br bb:$target)], IIBranch>; >>> +class UncondBranch op, string instr_asm>: >>> + BranchBase>> + !strconcat(instr_asm, "\t$imm16"), [(br bb:$imm16)], IIBranch> { >>> + let rs = 0; >>> + let rt = 0; >>> + let isBranch = 1; >>> + let isTerminator = 1; >>> + let isBarrier = 1; >>> + let hasDelaySlot = 1; >>> +} >>> >>> let isBranch=1, isTerminator=1, isBarrier=1, rd=0, hasDelaySlot = 1, >>> isIndirectBranch = 1 in >>> @@ -810,10 +808,10 @@ >>> defm USW : StoreM32<0x2b, "usw", store_u, 1>; >>> >>> /// Primitives for unaligned >>> -defm LWL : LoadX32<0x22>; >>> -defm LWR : LoadX32<0x26>; >>> -defm SWL : StoreX32<0x2A>; >>> -defm SWR : StoreX32<0x2E>; >>> +defm LWL : LoadUnAlign32<0x22>; >>> +defm LWR : LoadUnAlign32<0x26>; >>> +defm SWL : StoreUnAlign32<0x2A>; >>> +defm SWR : StoreUnAlign32<0x2E>; >>> >>> let hasSideEffects = 1 in >>> def SYNC : MipsInst<(outs), (ins i32imm:$stype), "sync $stype", >>> @@ -833,10 +831,10 @@ >>> def SC_P8 : SCBase<0x38, "sc", CPURegs, mem64>, Requires<[IsN64]>; >>> >>> /// Jump and Branch Instructions >>> -def J : JumpFJ<0x02, "j">; >>> def JR : JumpFR<0x00, 0x08, "jr", CPURegs>; >>> def JAL : JumpLink<0x03, "jal">; >>> def JALR : JumpLinkReg<0x00, 0x09, "jalr">; >>> +def B : UncondBranch<0x04, "b">; >>> def BEQ : CBranch<0x04, "beq", seteq, CPURegs>; >>> def BNE : CBranch<0x05, "bne", setne, CPURegs>; >>> def BGEZ : CBranchZero<0x01, 1, "bgez", setge, CPURegs>; >>> >>> >>> _______________________________________________ >>> llvm-commits mailing list >>> llvm-commits at cs.uiuc.edu >>> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits >> > > > > -- > Bruno Cardoso Lopes > http://www.brunocardoso.cc -------------- next part -------------- A non-text attachment was scrubbed... Name: 2011-12-05-JpBr.ll Type: application/octet-stream Size: 259 bytes Desc: 2011-12-05-JpBr.ll Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20111206/8ac50666/attachment.obj From kcc at google.com Tue Dec 6 15:10:15 2011 From: kcc at google.com (Kostya Serebryany) Date: Tue, 06 Dec 2011 21:10:15 -0000 Subject: [llvm-commits] [compiler-rt] r145966 - in /compiler-rt/trunk/lib/asan: asan_internal.h asan_rtl.cc Message-ID: <20111206211015.8CACC1BE003@llvm.org> Author: kcc Date: Tue Dec 6 15:10:15 2011 New Revision: 145966 URL: http://llvm.org/viewvc/llvm-project?rev=145966&view=rev Log: [asan] minor cleanup Modified: compiler-rt/trunk/lib/asan/asan_internal.h compiler-rt/trunk/lib/asan/asan_rtl.cc Modified: compiler-rt/trunk/lib/asan/asan_internal.h URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/lib/asan/asan_internal.h?rev=145966&r1=145965&r2=145966&view=diff ============================================================================== --- compiler-rt/trunk/lib/asan/asan_internal.h (original) +++ compiler-rt/trunk/lib/asan/asan_internal.h Tue Dec 6 15:10:15 2011 @@ -91,7 +91,6 @@ extern int FLAG_demangle; extern bool FLAG_symbolize; extern int FLAG_v; -extern bool FLAG_mt; extern size_t FLAG_redzone; extern int FLAG_debug; extern bool FLAG_poison_shadow; @@ -177,7 +176,6 @@ // -------------------------- Atomic ---------------- {{{1 static inline int AtomicInc(int *a) { - if (!FLAG_mt) return ++(*a); #ifdef ANDROID return __atomic_inc(a) + 1; #else @@ -186,7 +184,6 @@ } static inline int AtomicDec(int *a) { - if (!FLAG_mt) return --(*a); #ifdef ANDROID return __atomic_dec(a) - 1; #else Modified: compiler-rt/trunk/lib/asan/asan_rtl.cc URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/lib/asan/asan_rtl.cc?rev=145966&r1=145965&r2=145966&view=diff ============================================================================== --- compiler-rt/trunk/lib/asan/asan_rtl.cc (original) +++ compiler-rt/trunk/lib/asan/asan_rtl.cc Tue Dec 6 15:10:15 2011 @@ -57,7 +57,6 @@ bool FLAG_fast_unwind = true; size_t FLAG_redzone; // power of two, >= 32 -bool FLAG_mt; // set to 0 if you have only one thread. size_t FLAG_quarantine_size; int FLAG_demangle; bool FLAG_symbolize; @@ -665,7 +664,6 @@ FLAG_debug = IntFlagValue(options, "debug=", 0); FLAG_replace_cfallocator = IntFlagValue(options, "replace_cfallocator=", 1); FLAG_fast_unwind = IntFlagValue(options, "fast_unwind=", 1); - FLAG_mt = IntFlagValue(options, "mt=", 1); FLAG_replace_str = IntFlagValue(options, "replace_str=", 1); FLAG_replace_intrin = IntFlagValue(options, "replace_intrin=", 0); FLAG_use_fake_stack = IntFlagValue(options, "use_fake_stack=", 1); From dschuff at google.com Tue Dec 6 15:08:54 2011 From: dschuff at google.com (Derek Schuff) Date: Tue, 6 Dec 2011 13:08:54 -0800 Subject: [llvm-commits] Proposal/patch: Enable bitcode streaming In-Reply-To: References: Message-ID: Ping? I believe I've addressed all the comments. Also (assuming approval), someone will have to commit this, since I'm not yet a committer. On Thu, Dec 1, 2011 at 11:23 AM, Derek Schuff wrote: > Thanks for the review, comments have been addressed > (per IRC discussion: virtual destructors left in place because moving them > to BitcodeReader.cpp breaks linking clang, which includes BitstreamReader.h > for AST serialization but does not depend on bitcode lib) > > Patch attached. > > > On Wed, Nov 30, 2011 at 2:39 PM, Nick Lewycky wrote: > >> On 28 November 2011 12:42, Derek Schuff wrote: >> >>> thanks for the feedback, I'm fixing all the suggestions, but I do have >>> one question: >>> >>> On Mon, Nov 21, 2011 at 3:38 PM, Nick Lewycky wrote: >>> >>>> This is in a header file. Please move the implementation of the virtual >>>> destructor to BitcodeReader.cpp, or else copies will end up in every .o >>>> file that includes this header. >>>> >>>> Same with MemoryBitstreamBytes and LazyBitstreamBytes. More general >>>> question, any reason to put MemoryBitstreamBytes and LazyBitstreamBytes >>>> implementations inside the header? You could create >>>> lib/Bitcode/Reader/BitstreamReader.cpp. >>>> >>>> >>> The BitstreamBytes implementations are in the header file because >>> BitstreamReader/BitstreamCursor is implemented entirely in the header >>> file. Presumably BitstreamReader is in the header file so it can be >>> inlined. Presumably this improves performance (especially in llc where >>> there the usage is only in one file), although there seem to be several >>> uses of BitstreamCursor in clang, so it may contribute to more code size >>> bloat there. If you want I can move everything to BitstreamReader.cpp >>> (perhaps LTO could still buy us back any performance loss from inlining?) >>> >> >> That's a great point. Given the other code in the bitcode reader, I think >> it's fine to leave the implementations in the header -- except for the >> virtual destructors. >> >> It would also be possible to move just the BitstreamBytes implementations >>> into a cpp file using the common idiom of having static factory functions >>> with an anonymous namespace rather than just calling "new" directly like we >>> do right now. >>> >> >> I don't have a sense that either way would be particularly better. >> >> >One other thing. The behaviour when LazyBitcode is true could be >>> really different from when it off on the same .bc file on >disk. It'd be >>> good to add comments pointing out why (module-level assembly comes to mind, >>> anything else?). >>> >>> Sure. where would be a good place to put it? >>> >> >> I was thinking of comments above the option in llc. >> >> Nick >> >> > -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20111206/07d8aa5c/attachment.html From bruno.cardoso at gmail.com Tue Dec 6 11:59:55 2011 From: bruno.cardoso at gmail.com (Bruno Cardoso Lopes) Date: Tue, 6 Dec 2011 15:59:55 -0200 Subject: [llvm-commits] [llvm] r145912 - in /llvm/trunk/lib/Target/Mips: MipsInstrFormats.td MipsInstrInfo.cpp MipsInstrInfo.td In-Reply-To: References: <20111206033449.22EBB2A6C12C@llvm.org> Message-ID: Still waiting from Jack Carter! Since it was commited yesterday, he may be taking his time to do it. On Tue, Dec 6, 2011 at 3:39 PM, Chad Rosier wrote: > Did the test case ever land? > > ?Chad > > On Dec 5, 2011, at 7:34 PM, Bruno Cardoso Lopes wrote: > >> Author: bruno >> Date: Mon Dec ?5 21:34:48 2011 >> New Revision: 145912 >> >> URL: http://llvm.org/viewvc/llvm-project?rev=145912&view=rev >> Log: >> Use branches instead of jumps + variable cleanup. Testcase coming next. Patch by Jack Carter >> >> Modified: >> ? ?llvm/trunk/lib/Target/Mips/MipsInstrFormats.td >> ? ?llvm/trunk/lib/Target/Mips/MipsInstrInfo.cpp >> ? ?llvm/trunk/lib/Target/Mips/MipsInstrInfo.td >> >> Modified: llvm/trunk/lib/Target/Mips/MipsInstrFormats.td >> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsInstrFormats.td?rev=145912&r1=145911&r2=145912&view=diff >> ============================================================================== >> --- llvm/trunk/lib/Target/Mips/MipsInstrFormats.td (original) >> +++ llvm/trunk/lib/Target/Mips/MipsInstrFormats.td Mon Dec ?5 21:34:48 2011 >> @@ -115,7 +115,7 @@ >> ? let Inst{15-0} ?= imm16; >> } >> >> -class CBranchBase op, dag outs, dag ins, string asmstr, >> +class BranchBase op, dag outs, dag ins, string asmstr, >> ? ? ? ? ? ? ? ? ? list pattern, InstrItinClass itin>: >> ? MipsInst >> { >> >> Modified: llvm/trunk/lib/Target/Mips/MipsInstrInfo.cpp >> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsInstrInfo.cpp?rev=145912&r1=145911&r2=145912&view=diff >> ============================================================================== >> --- llvm/trunk/lib/Target/Mips/MipsInstrInfo.cpp (original) >> +++ llvm/trunk/lib/Target/Mips/MipsInstrInfo.cpp Mon Dec ?5 21:34:48 2011 >> @@ -236,7 +236,7 @@ >> ? ? ? ? ? Opc == Mips::BGEZ ? || Opc == Mips::BLTZ ? || Opc == Mips::BLEZ ? || >> ? ? ? ? ? Opc == Mips::BEQ64 ?|| Opc == Mips::BNE64 ?|| Opc == Mips::BGTZ64 || >> ? ? ? ? ? Opc == Mips::BGEZ64 || Opc == Mips::BLTZ64 || Opc == Mips::BLEZ64 || >> - ? ? ? ? ?Opc == Mips::BC1T ? || Opc == Mips::BC1F ? || Opc == Mips::J) ? >> + ? ? ? ? ?Opc == Mips::BC1T ? || Opc == Mips::BC1F ? || Opc == Mips::B) ? >> ? ? ? ? ?Opc : 0; >> } >> >> @@ -320,7 +320,7 @@ >> ? // If there is only one terminator instruction, process it. >> ? if (!SecondLastOpc) { >> ? ? // Unconditional branch >> - ? ?if (LastOpc == Mips::J) { >> + ? ?if (LastOpc == Mips::B) { >> ? ? ? TBB = LastInst->getOperand(0).getMBB(); >> ? ? ? return false; >> ? ? } >> @@ -337,7 +337,7 @@ >> >> ? // If second to last instruction is an unconditional branch, >> ? // analyze it and remove the last instruction. >> - ?if (SecondLastOpc == Mips::J) { >> + ?if (SecondLastOpc == Mips::B) { >> ? ? // Return if the last instruction cannot be removed. >> ? ? if (!AllowModify) >> ? ? ? return true; >> @@ -349,7 +349,7 @@ >> >> ? // Conditional branch followed by an unconditional branch. >> ? // The last one must be unconditional. >> - ?if (LastOpc != Mips::J) >> + ?if (LastOpc != Mips::B) >> ? ? return true; >> >> ? AnalyzeCondBr(SecondLastInst, SecondLastOpc, TBB, Cond); >> @@ -391,14 +391,14 @@ >> ? // Two-way Conditional branch. >> ? if (FBB) { >> ? ? BuildCondBr(MBB, TBB, DL, Cond); >> - ? ?BuildMI(&MBB, DL, get(Mips::J)).addMBB(FBB); >> + ? ?BuildMI(&MBB, DL, get(Mips::B)).addMBB(FBB); >> ? ? return 2; >> ? } >> >> ? // One way branch. >> ? // Unconditional branch. >> ? if (Cond.empty()) >> - ? ?BuildMI(&MBB, DL, get(Mips::J)).addMBB(TBB); >> + ? ?BuildMI(&MBB, DL, get(Mips::B)).addMBB(TBB); >> ? else // Conditional branch. >> ? ? BuildCondBr(MBB, TBB, DL, Cond); >> ? return 1; >> >> Modified: llvm/trunk/lib/Target/Mips/MipsInstrInfo.td >> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsInstrInfo.td?rev=145912&r1=145911&r2=145912&view=diff >> ============================================================================== >> --- llvm/trunk/lib/Target/Mips/MipsInstrInfo.td (original) >> +++ llvm/trunk/lib/Target/Mips/MipsInstrInfo.td Mon Dec ?5 21:34:48 2011 >> @@ -380,21 +380,13 @@ >> ? let isPseudo = Pseudo; >> } >> >> -// Memory Load/Store >> +// Unaligned Memory Load/Store >> let canFoldAsLoad = 1 in >> -class LoadX op, RegisterClass RC, >> - ? ? ? ? ? ?Operand MemOpnd>: >> - ?FMem> - ? ? "", >> - ? ? [], IILoad> { >> -} >> +class LoadUnAlign op, RegisterClass RC, Operand MemOpnd>: >> + ?FMem {} >> >> -class StoreX op, RegisterClass RC, >> - ? ? ? ? ? ? Operand MemOpnd>: >> - ?FMem> - ? ? "", >> - ? ? [], IIStore> { >> -} >> +class StoreUnAlign op, RegisterClass RC, Operand MemOpnd>: >> + ?FMem {} >> >> // 32-bit load. >> multiclass LoadM32 op, string instr_asm, PatFrag OpNode, >> @@ -415,10 +407,10 @@ >> } >> >> // 32-bit load. >> -multiclass LoadX32 op> { >> - ?def #NAME# : LoadX, >> +multiclass LoadUnAlign32 op> { >> + ?def #NAME# : LoadUnAlign, >> ? ? ? ? ? ? ? ?Requires<[NotN64]>; >> - ?def _P8 ? ?: LoadX, >> + ?def _P8 ? ?: LoadUnAlign, >> ? ? ? ? ? ? ? ?Requires<[IsN64]>; >> } >> // 32-bit store. >> @@ -440,18 +432,18 @@ >> } >> >> // 32-bit store. >> -multiclass StoreX32 op> { >> - ?def #NAME# : StoreX, >> +multiclass StoreUnAlign32 op> { >> + ?def #NAME# : StoreUnAlign, >> ? ? ? ? ? ? ? ?Requires<[NotN64]>; >> - ?def _P8 ? ?: StoreX, >> + ?def _P8 ? ?: StoreUnAlign, >> ? ? ? ? ? ? ? ?Requires<[IsN64]>; >> } >> >> // Conditional Branch >> class CBranch op, string instr_asm, PatFrag cond_op, RegisterClass RC>: >> - ?CBranchBase> - ? ? ? ? ? ? ?!strconcat(instr_asm, "\t$rs, $rt, $imm16"), >> - ? ? ? ? ? ? ?[(brcond (i32 (cond_op RC:$rs, RC:$rt)), bb:$imm16)], IIBranch> { >> + ?BranchBase> + ? ? ? ? ? ? !strconcat(instr_asm, "\t$rs, $rt, $imm16"), >> + ? ? ? ? ? ? [(brcond (i32 (cond_op RC:$rs, RC:$rt)), bb:$imm16)], IIBranch> { >> ? let isBranch = 1; >> ? let isTerminator = 1; >> ? let hasDelaySlot = 1; >> @@ -459,9 +451,9 @@ >> >> class CBranchZero op, bits<5> _rt, string instr_asm, PatFrag cond_op, >> ? ? ? ? ? ? ? ? ? RegisterClass RC>: >> - ?CBranchBase> - ? ? ? ? ? ? ?!strconcat(instr_asm, "\t$rs, $imm16"), >> - ? ? ? ? ? ? ?[(brcond (i32 (cond_op RC:$rs, 0)), bb:$imm16)], IIBranch> { >> + ?BranchBase> + ? ? ? ? ? ? !strconcat(instr_asm, "\t$rs, $imm16"), >> + ? ? ? ? ? ? [(brcond (i32 (cond_op RC:$rs, 0)), bb:$imm16)], IIBranch> { >> ? let rt = _rt; >> ? let isBranch = 1; >> ? let isTerminator = 1; >> @@ -486,10 +478,16 @@ >> ? ? ?IIAlu>; >> >> // Unconditional branch >> -let isBranch=1, isTerminator=1, isBarrier=1, hasDelaySlot = 1 in >> -class JumpFJ op, string instr_asm>: >> - ?FJ> - ? ? !strconcat(instr_asm, "\t$target"), [(br bb:$target)], IIBranch>; >> +class UncondBranch op, string instr_asm>: >> + ?BranchBase> + ? ? ? ? ? ? !strconcat(instr_asm, "\t$imm16"), [(br bb:$imm16)], IIBranch> { >> + ?let rs = 0; >> + ?let rt = 0; >> + ?let isBranch = 1; >> + ?let isTerminator = 1; >> + ?let isBarrier = 1; >> + ?let hasDelaySlot = 1; >> +} >> >> let isBranch=1, isTerminator=1, isBarrier=1, rd=0, hasDelaySlot = 1, >> ? ? isIndirectBranch = 1 in >> @@ -810,10 +808,10 @@ >> defm USW ? ? : StoreM32<0x2b, "usw", store_u, 1>; >> >> /// Primitives for unaligned >> -defm LWL ? ? : LoadX32<0x22>; >> -defm LWR ? ? : LoadX32<0x26>; >> -defm SWL ? ? : StoreX32<0x2A>; >> -defm SWR ? ? : StoreX32<0x2E>; >> +defm LWL ? ? : LoadUnAlign32<0x22>; >> +defm LWR ? ? : LoadUnAlign32<0x26>; >> +defm SWL ? ? : StoreUnAlign32<0x2A>; >> +defm SWR ? ? : StoreUnAlign32<0x2E>; >> >> let hasSideEffects = 1 in >> def SYNC : MipsInst<(outs), (ins i32imm:$stype), "sync $stype", >> @@ -833,10 +831,10 @@ >> def SC_P8 : SCBase<0x38, "sc", CPURegs, mem64>, Requires<[IsN64]>; >> >> /// Jump and Branch Instructions >> -def J ? ? ? : JumpFJ<0x02, "j">; >> def JR ? ? ?: JumpFR<0x00, 0x08, "jr", CPURegs>; >> def JAL ? ? : JumpLink<0x03, "jal">; >> def JALR ? ?: JumpLinkReg<0x00, 0x09, "jalr">; >> +def B ? ? ? : UncondBranch<0x04, "b">; >> def BEQ ? ? : CBranch<0x04, "beq", seteq, CPURegs>; >> def BNE ? ? : CBranch<0x05, "bne", setne, CPURegs>; >> def BGEZ ? ?: CBranchZero<0x01, 1, "bgez", setge, CPURegs>; >> >> >> _______________________________________________ >> llvm-commits mailing list >> llvm-commits at cs.uiuc.edu >> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits > -- Bruno Cardoso Lopes http://www.brunocardoso.cc From jcarter at mips.com Tue Dec 6 12:40:26 2011 From: jcarter at mips.com (Carter, Jack) Date: Tue, 6 Dec 2011 18:40:26 +0000 Subject: [llvm-commits] [llvm] r145912 - in /llvm/trunk/lib/Target/Mips: MipsInstrFormats.td MipsInstrInfo.cpp MipsInstrInfo.td In-Reply-To: References: <20111206033449.22EBB2A6C12C@llvm.org> , Message-ID: <86AC779C188FE74F88F6494478B46332E8B3F0@exchdb03.mips.com> The commit was after I left for home and I just got in again. I am checking here for the correct form for a test case and will send it in. Jack ________________________________________ From: Bruno Cardoso Lopes [bruno.cardoso at gmail.com] Sent: Tuesday, December 06, 2011 9:59 AM To: Chad Rosier; Carter, Jack Cc: llvm-commits at cs.uiuc.edu Subject: Re: [llvm-commits] [llvm] r145912 - in /llvm/trunk/lib/Target/Mips: MipsInstrFormats.td MipsInstrInfo.cpp MipsInstrInfo.td Still waiting from Jack Carter! Since it was commited yesterday, he may be taking his time to do it. On Tue, Dec 6, 2011 at 3:39 PM, Chad Rosier wrote: > Did the test case ever land? > > Chad > > On Dec 5, 2011, at 7:34 PM, Bruno Cardoso Lopes wrote: > >> Author: bruno >> Date: Mon Dec 5 21:34:48 2011 >> New Revision: 145912 >> >> URL: http://llvm.org/viewvc/llvm-project?rev=145912&view=rev >> Log: >> Use branches instead of jumps + variable cleanup. Testcase coming next. Patch by Jack Carter >> >> Modified: >> llvm/trunk/lib/Target/Mips/MipsInstrFormats.td >> llvm/trunk/lib/Target/Mips/MipsInstrInfo.cpp >> llvm/trunk/lib/Target/Mips/MipsInstrInfo.td >> >> Modified: llvm/trunk/lib/Target/Mips/MipsInstrFormats.td >> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsInstrFormats.td?rev=145912&r1=145911&r2=145912&view=diff >> ============================================================================== >> --- llvm/trunk/lib/Target/Mips/MipsInstrFormats.td (original) >> +++ llvm/trunk/lib/Target/Mips/MipsInstrFormats.td Mon Dec 5 21:34:48 2011 >> @@ -115,7 +115,7 @@ >> let Inst{15-0} = imm16; >> } >> >> -class CBranchBase op, dag outs, dag ins, string asmstr, >> +class BranchBase op, dag outs, dag ins, string asmstr, >> list pattern, InstrItinClass itin>: >> MipsInst >> { >> >> Modified: llvm/trunk/lib/Target/Mips/MipsInstrInfo.cpp >> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsInstrInfo.cpp?rev=145912&r1=145911&r2=145912&view=diff >> ============================================================================== >> --- llvm/trunk/lib/Target/Mips/MipsInstrInfo.cpp (original) >> +++ llvm/trunk/lib/Target/Mips/MipsInstrInfo.cpp Mon Dec 5 21:34:48 2011 >> @@ -236,7 +236,7 @@ >> Opc == Mips::BGEZ || Opc == Mips::BLTZ || Opc == Mips::BLEZ || >> Opc == Mips::BEQ64 || Opc == Mips::BNE64 || Opc == Mips::BGTZ64 || >> Opc == Mips::BGEZ64 || Opc == Mips::BLTZ64 || Opc == Mips::BLEZ64 || >> - Opc == Mips::BC1T || Opc == Mips::BC1F || Opc == Mips::J) ? >> + Opc == Mips::BC1T || Opc == Mips::BC1F || Opc == Mips::B) ? >> Opc : 0; >> } >> >> @@ -320,7 +320,7 @@ >> // If there is only one terminator instruction, process it. >> if (!SecondLastOpc) { >> // Unconditional branch >> - if (LastOpc == Mips::J) { >> + if (LastOpc == Mips::B) { >> TBB = LastInst->getOperand(0).getMBB(); >> return false; >> } >> @@ -337,7 +337,7 @@ >> >> // If second to last instruction is an unconditional branch, >> // analyze it and remove the last instruction. >> - if (SecondLastOpc == Mips::J) { >> + if (SecondLastOpc == Mips::B) { >> // Return if the last instruction cannot be removed. >> if (!AllowModify) >> return true; >> @@ -349,7 +349,7 @@ >> >> // Conditional branch followed by an unconditional branch. >> // The last one must be unconditional. >> - if (LastOpc != Mips::J) >> + if (LastOpc != Mips::B) >> return true; >> >> AnalyzeCondBr(SecondLastInst, SecondLastOpc, TBB, Cond); >> @@ -391,14 +391,14 @@ >> // Two-way Conditional branch. >> if (FBB) { >> BuildCondBr(MBB, TBB, DL, Cond); >> - BuildMI(&MBB, DL, get(Mips::J)).addMBB(FBB); >> + BuildMI(&MBB, DL, get(Mips::B)).addMBB(FBB); >> return 2; >> } >> >> // One way branch. >> // Unconditional branch. >> if (Cond.empty()) >> - BuildMI(&MBB, DL, get(Mips::J)).addMBB(TBB); >> + BuildMI(&MBB, DL, get(Mips::B)).addMBB(TBB); >> else // Conditional branch. >> BuildCondBr(MBB, TBB, DL, Cond); >> return 1; >> >> Modified: llvm/trunk/lib/Target/Mips/MipsInstrInfo.td >> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsInstrInfo.td?rev=145912&r1=145911&r2=145912&view=diff >> ============================================================================== >> --- llvm/trunk/lib/Target/Mips/MipsInstrInfo.td (original) >> +++ llvm/trunk/lib/Target/Mips/MipsInstrInfo.td Mon Dec 5 21:34:48 2011 >> @@ -380,21 +380,13 @@ >> let isPseudo = Pseudo; >> } >> >> -// Memory Load/Store >> +// Unaligned Memory Load/Store >> let canFoldAsLoad = 1 in >> -class LoadX op, RegisterClass RC, >> - Operand MemOpnd>: >> - FMem> - "", >> - [], IILoad> { >> -} >> +class LoadUnAlign op, RegisterClass RC, Operand MemOpnd>: >> + FMem {} >> >> -class StoreX op, RegisterClass RC, >> - Operand MemOpnd>: >> - FMem> - "", >> - [], IIStore> { >> -} >> +class StoreUnAlign op, RegisterClass RC, Operand MemOpnd>: >> + FMem {} >> >> // 32-bit load. >> multiclass LoadM32 op, string instr_asm, PatFrag OpNode, >> @@ -415,10 +407,10 @@ >> } >> >> // 32-bit load. >> -multiclass LoadX32 op> { >> - def #NAME# : LoadX, >> +multiclass LoadUnAlign32 op> { >> + def #NAME# : LoadUnAlign, >> Requires<[NotN64]>; >> - def _P8 : LoadX, >> + def _P8 : LoadUnAlign, >> Requires<[IsN64]>; >> } >> // 32-bit store. >> @@ -440,18 +432,18 @@ >> } >> >> // 32-bit store. >> -multiclass StoreX32 op> { >> - def #NAME# : StoreX, >> +multiclass StoreUnAlign32 op> { >> + def #NAME# : StoreUnAlign, >> Requires<[NotN64]>; >> - def _P8 : StoreX, >> + def _P8 : StoreUnAlign, >> Requires<[IsN64]>; >> } >> >> // Conditional Branch >> class CBranch op, string instr_asm, PatFrag cond_op, RegisterClass RC>: >> - CBranchBase> - !strconcat(instr_asm, "\t$rs, $rt, $imm16"), >> - [(brcond (i32 (cond_op RC:$rs, RC:$rt)), bb:$imm16)], IIBranch> { >> + BranchBase> + !strconcat(instr_asm, "\t$rs, $rt, $imm16"), >> + [(brcond (i32 (cond_op RC:$rs, RC:$rt)), bb:$imm16)], IIBranch> { >> let isBranch = 1; >> let isTerminator = 1; >> let hasDelaySlot = 1; >> @@ -459,9 +451,9 @@ >> >> class CBranchZero op, bits<5> _rt, string instr_asm, PatFrag cond_op, >> RegisterClass RC>: >> - CBranchBase> - !strconcat(instr_asm, "\t$rs, $imm16"), >> - [(brcond (i32 (cond_op RC:$rs, 0)), bb:$imm16)], IIBranch> { >> + BranchBase> + !strconcat(instr_asm, "\t$rs, $imm16"), >> + [(brcond (i32 (cond_op RC:$rs, 0)), bb:$imm16)], IIBranch> { >> let rt = _rt; >> let isBranch = 1; >> let isTerminator = 1; >> @@ -486,10 +478,16 @@ >> IIAlu>; >> >> // Unconditional branch >> -let isBranch=1, isTerminator=1, isBarrier=1, hasDelaySlot = 1 in >> -class JumpFJ op, string instr_asm>: >> - FJ> - !strconcat(instr_asm, "\t$target"), [(br bb:$target)], IIBranch>; >> +class UncondBranch op, string instr_asm>: >> + BranchBase> + !strconcat(instr_asm, "\t$imm16"), [(br bb:$imm16)], IIBranch> { >> + let rs = 0; >> + let rt = 0; >> + let isBranch = 1; >> + let isTerminator = 1; >> + let isBarrier = 1; >> + let hasDelaySlot = 1; >> +} >> >> let isBranch=1, isTerminator=1, isBarrier=1, rd=0, hasDelaySlot = 1, >> isIndirectBranch = 1 in >> @@ -810,10 +808,10 @@ >> defm USW : StoreM32<0x2b, "usw", store_u, 1>; >> >> /// Primitives for unaligned >> -defm LWL : LoadX32<0x22>; >> -defm LWR : LoadX32<0x26>; >> -defm SWL : StoreX32<0x2A>; >> -defm SWR : StoreX32<0x2E>; >> +defm LWL : LoadUnAlign32<0x22>; >> +defm LWR : LoadUnAlign32<0x26>; >> +defm SWL : StoreUnAlign32<0x2A>; >> +defm SWR : StoreUnAlign32<0x2E>; >> >> let hasSideEffects = 1 in >> def SYNC : MipsInst<(outs), (ins i32imm:$stype), "sync $stype", >> @@ -833,10 +831,10 @@ >> def SC_P8 : SCBase<0x38, "sc", CPURegs, mem64>, Requires<[IsN64]>; >> >> /// Jump and Branch Instructions >> -def J : JumpFJ<0x02, "j">; >> def JR : JumpFR<0x00, 0x08, "jr", CPURegs>; >> def JAL : JumpLink<0x03, "jal">; >> def JALR : JumpLinkReg<0x00, 0x09, "jalr">; >> +def B : UncondBranch<0x04, "b">; >> def BEQ : CBranch<0x04, "beq", seteq, CPURegs>; >> def BNE : CBranch<0x05, "bne", setne, CPURegs>; >> def BGEZ : CBranchZero<0x01, 1, "bgez", setge, CPURegs>; >> >> >> _______________________________________________ >> llvm-commits mailing list >> llvm-commits at cs.uiuc.edu >> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits > -- Bruno Cardoso Lopes http://www.brunocardoso.cc From hfinkel at anl.gov Tue Dec 6 14:55:42 2011 From: hfinkel at anl.gov (Hal Finkel) Date: Tue, 06 Dec 2011 20:55:42 -0000 Subject: [llvm-commits] [llvm] r145962 - /llvm/trunk/test/CodeGen/PowerPC/2011-12-06-SpillAndRestoreCR.ll Message-ID: <20111206205542.199691BE003@llvm.org> Author: hfinkel Date: Tue Dec 6 14:55:41 2011 New Revision: 145962 URL: http://llvm.org/viewvc/llvm-project?rev=145962&view=rev Log: add a test case that uses RESTORE_CR Added: llvm/trunk/test/CodeGen/PowerPC/2011-12-06-SpillAndRestoreCR.ll Added: llvm/trunk/test/CodeGen/PowerPC/2011-12-06-SpillAndRestoreCR.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/2011-12-06-SpillAndRestoreCR.ll?rev=145962&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/PowerPC/2011-12-06-SpillAndRestoreCR.ll (added) +++ llvm/trunk/test/CodeGen/PowerPC/2011-12-06-SpillAndRestoreCR.ll Tue Dec 6 14:55:41 2011 @@ -0,0 +1,225 @@ +; RUN: llc < %s -mtriple=powerpc-apple-darwin -mcpu=g4 | FileCheck %s +; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=g4 | FileCheck %s + +; ModuleID = 'tsc.c' +target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32:64" +target triple = "powerpc64-unknown-linux-gnu" + + at a = common global [32000 x float] zeroinitializer, align 16 + at b = common global [32000 x float] zeroinitializer, align 16 + at c = common global [32000 x float] zeroinitializer, align 16 + at d = common global [32000 x float] zeroinitializer, align 16 + at e = common global [32000 x float] zeroinitializer, align 16 + at aa = common global [256 x [256 x float]] zeroinitializer, align 16 + at bb = common global [256 x [256 x float]] zeroinitializer, align 16 + at cc = common global [256 x [256 x float]] zeroinitializer, align 16 + at temp = common global float 0.000000e+00, align 4 + + at .str81 = private unnamed_addr constant [6 x i8] c"s3110\00", align 1 + at .str235 = private unnamed_addr constant [15 x i8] c"S3110\09 %.2f \09\09\00", align 1 + +declare i32 @printf(i8* nocapture, ...) nounwind +declare i32 @init(i8* %name) nounwind +declare i64 @clock() nounwind +declare i32 @dummy(float*, float*, float*, float*, float*, [256 x float]*, [256 x float]*, [256 x float]*, float) +declare void @check(i32 %name) nounwind + +; CHECK: mfcr +; CHECK: mtcr + +define i32 @s3110() nounwind { +entry: + %call = tail call i32 @init(i8* getelementptr inbounds ([6 x i8]* @.str81, i64 0, i64 0)) + %call1 = tail call i64 @clock() nounwind + br label %for.body + +for.body: ; preds = %for.end17, %entry + %nl.041 = phi i32 [ 0, %entry ], [ %inc22, %for.end17 ] + %0 = load float* getelementptr inbounds ([256 x [256 x float]]* @aa, i64 0, i64 0, i64 0), align 16, !tbaa !5 + br label %for.cond5.preheader + +for.cond5.preheader: ; preds = %for.inc15, %for.body + %indvars.iv42 = phi i64 [ 0, %for.body ], [ %indvars.iv.next43, %for.inc15 ] + %max.139 = phi float [ %0, %for.body ], [ %max.3.15, %for.inc15 ] + %xindex.138 = phi i32 [ 0, %for.body ], [ %xindex.3.15, %for.inc15 ] + %yindex.137 = phi i32 [ 0, %for.body ], [ %yindex.3.15, %for.inc15 ] + br label %for.body7 + +for.body7: ; preds = %for.body7, %for.cond5.preheader + %indvars.iv = phi i64 [ 0, %for.cond5.preheader ], [ %indvars.iv.next.15, %for.body7 ] + %max.235 = phi float [ %max.139, %for.cond5.preheader ], [ %max.3.15, %for.body7 ] + %xindex.234 = phi i32 [ %xindex.138, %for.cond5.preheader ], [ %xindex.3.15, %for.body7 ] + %yindex.233 = phi i32 [ %yindex.137, %for.cond5.preheader ], [ %yindex.3.15, %for.body7 ] + %arrayidx9 = getelementptr inbounds [256 x [256 x float]]* @aa, i64 0, i64 %indvars.iv42, i64 %indvars.iv + %1 = load float* %arrayidx9, align 16, !tbaa !5 + %cmp10 = fcmp ogt float %1, %max.235 + %2 = trunc i64 %indvars.iv to i32 + %yindex.3 = select i1 %cmp10, i32 %2, i32 %yindex.233 + %3 = trunc i64 %indvars.iv42 to i32 + %xindex.3 = select i1 %cmp10, i32 %3, i32 %xindex.234 + %max.3 = select i1 %cmp10, float %1, float %max.235 + %indvars.iv.next45 = or i64 %indvars.iv, 1 + %arrayidx9.1 = getelementptr inbounds [256 x [256 x float]]* @aa, i64 0, i64 %indvars.iv42, i64 %indvars.iv.next45 + %4 = load float* %arrayidx9.1, align 4, !tbaa !5 + %cmp10.1 = fcmp ogt float %4, %max.3 + %5 = trunc i64 %indvars.iv.next45 to i32 + %yindex.3.1 = select i1 %cmp10.1, i32 %5, i32 %yindex.3 + %xindex.3.1 = select i1 %cmp10.1, i32 %3, i32 %xindex.3 + %max.3.1 = select i1 %cmp10.1, float %4, float %max.3 + %indvars.iv.next.146 = or i64 %indvars.iv, 2 + %arrayidx9.2 = getelementptr inbounds [256 x [256 x float]]* @aa, i64 0, i64 %indvars.iv42, i64 %indvars.iv.next.146 + %6 = load float* %arrayidx9.2, align 8, !tbaa !5 + %cmp10.2 = fcmp ogt float %6, %max.3.1 + %7 = trunc i64 %indvars.iv.next.146 to i32 + %yindex.3.2 = select i1 %cmp10.2, i32 %7, i32 %yindex.3.1 + %xindex.3.2 = select i1 %cmp10.2, i32 %3, i32 %xindex.3.1 + %max.3.2 = select i1 %cmp10.2, float %6, float %max.3.1 + %indvars.iv.next.247 = or i64 %indvars.iv, 3 + %arrayidx9.3 = getelementptr inbounds [256 x [256 x float]]* @aa, i64 0, i64 %indvars.iv42, i64 %indvars.iv.next.247 + %8 = load float* %arrayidx9.3, align 4, !tbaa !5 + %cmp10.3 = fcmp ogt float %8, %max.3.2 + %9 = trunc i64 %indvars.iv.next.247 to i32 + %yindex.3.3 = select i1 %cmp10.3, i32 %9, i32 %yindex.3.2 + %xindex.3.3 = select i1 %cmp10.3, i32 %3, i32 %xindex.3.2 + %max.3.3 = select i1 %cmp10.3, float %8, float %max.3.2 + %indvars.iv.next.348 = or i64 %indvars.iv, 4 + %arrayidx9.4 = getelementptr inbounds [256 x [256 x float]]* @aa, i64 0, i64 %indvars.iv42, i64 %indvars.iv.next.348 + %10 = load float* %arrayidx9.4, align 16, !tbaa !5 + %cmp10.4 = fcmp ogt float %10, %max.3.3 + %11 = trunc i64 %indvars.iv.next.348 to i32 + %yindex.3.4 = select i1 %cmp10.4, i32 %11, i32 %yindex.3.3 + %xindex.3.4 = select i1 %cmp10.4, i32 %3, i32 %xindex.3.3 + %max.3.4 = select i1 %cmp10.4, float %10, float %max.3.3 + %indvars.iv.next.449 = or i64 %indvars.iv, 5 + %arrayidx9.5 = getelementptr inbounds [256 x [256 x float]]* @aa, i64 0, i64 %indvars.iv42, i64 %indvars.iv.next.449 + %12 = load float* %arrayidx9.5, align 4, !tbaa !5 + %cmp10.5 = fcmp ogt float %12, %max.3.4 + %13 = trunc i64 %indvars.iv.next.449 to i32 + %yindex.3.5 = select i1 %cmp10.5, i32 %13, i32 %yindex.3.4 + %xindex.3.5 = select i1 %cmp10.5, i32 %3, i32 %xindex.3.4 + %max.3.5 = select i1 %cmp10.5, float %12, float %max.3.4 + %indvars.iv.next.550 = or i64 %indvars.iv, 6 + %arrayidx9.6 = getelementptr inbounds [256 x [256 x float]]* @aa, i64 0, i64 %indvars.iv42, i64 %indvars.iv.next.550 + %14 = load float* %arrayidx9.6, align 8, !tbaa !5 + %cmp10.6 = fcmp ogt float %14, %max.3.5 + %15 = trunc i64 %indvars.iv.next.550 to i32 + %yindex.3.6 = select i1 %cmp10.6, i32 %15, i32 %yindex.3.5 + %xindex.3.6 = select i1 %cmp10.6, i32 %3, i32 %xindex.3.5 + %max.3.6 = select i1 %cmp10.6, float %14, float %max.3.5 + %indvars.iv.next.651 = or i64 %indvars.iv, 7 + %arrayidx9.7 = getelementptr inbounds [256 x [256 x float]]* @aa, i64 0, i64 %indvars.iv42, i64 %indvars.iv.next.651 + %16 = load float* %arrayidx9.7, align 4, !tbaa !5 + %cmp10.7 = fcmp ogt float %16, %max.3.6 + %17 = trunc i64 %indvars.iv.next.651 to i32 + %yindex.3.7 = select i1 %cmp10.7, i32 %17, i32 %yindex.3.6 + %xindex.3.7 = select i1 %cmp10.7, i32 %3, i32 %xindex.3.6 + %max.3.7 = select i1 %cmp10.7, float %16, float %max.3.6 + %indvars.iv.next.752 = or i64 %indvars.iv, 8 + %arrayidx9.8 = getelementptr inbounds [256 x [256 x float]]* @aa, i64 0, i64 %indvars.iv42, i64 %indvars.iv.next.752 + %18 = load float* %arrayidx9.8, align 16, !tbaa !5 + %cmp10.8 = fcmp ogt float %18, %max.3.7 + %19 = trunc i64 %indvars.iv.next.752 to i32 + %yindex.3.8 = select i1 %cmp10.8, i32 %19, i32 %yindex.3.7 + %xindex.3.8 = select i1 %cmp10.8, i32 %3, i32 %xindex.3.7 + %max.3.8 = select i1 %cmp10.8, float %18, float %max.3.7 + %indvars.iv.next.853 = or i64 %indvars.iv, 9 + %arrayidx9.9 = getelementptr inbounds [256 x [256 x float]]* @aa, i64 0, i64 %indvars.iv42, i64 %indvars.iv.next.853 + %20 = load float* %arrayidx9.9, align 4, !tbaa !5 + %cmp10.9 = fcmp ogt float %20, %max.3.8 + %21 = trunc i64 %indvars.iv.next.853 to i32 + %yindex.3.9 = select i1 %cmp10.9, i32 %21, i32 %yindex.3.8 + %xindex.3.9 = select i1 %cmp10.9, i32 %3, i32 %xindex.3.8 + %max.3.9 = select i1 %cmp10.9, float %20, float %max.3.8 + %indvars.iv.next.954 = or i64 %indvars.iv, 10 + %arrayidx9.10 = getelementptr inbounds [256 x [256 x float]]* @aa, i64 0, i64 %indvars.iv42, i64 %indvars.iv.next.954 + %22 = load float* %arrayidx9.10, align 8, !tbaa !5 + %cmp10.10 = fcmp ogt float %22, %max.3.9 + %23 = trunc i64 %indvars.iv.next.954 to i32 + %yindex.3.10 = select i1 %cmp10.10, i32 %23, i32 %yindex.3.9 + %xindex.3.10 = select i1 %cmp10.10, i32 %3, i32 %xindex.3.9 + %max.3.10 = select i1 %cmp10.10, float %22, float %max.3.9 + %indvars.iv.next.1055 = or i64 %indvars.iv, 11 + %arrayidx9.11 = getelementptr inbounds [256 x [256 x float]]* @aa, i64 0, i64 %indvars.iv42, i64 %indvars.iv.next.1055 + %24 = load float* %arrayidx9.11, align 4, !tbaa !5 + %cmp10.11 = fcmp ogt float %24, %max.3.10 + %25 = trunc i64 %indvars.iv.next.1055 to i32 + %yindex.3.11 = select i1 %cmp10.11, i32 %25, i32 %yindex.3.10 + %xindex.3.11 = select i1 %cmp10.11, i32 %3, i32 %xindex.3.10 + %max.3.11 = select i1 %cmp10.11, float %24, float %max.3.10 + %indvars.iv.next.1156 = or i64 %indvars.iv, 12 + %arrayidx9.12 = getelementptr inbounds [256 x [256 x float]]* @aa, i64 0, i64 %indvars.iv42, i64 %indvars.iv.next.1156 + %26 = load float* %arrayidx9.12, align 16, !tbaa !5 + %cmp10.12 = fcmp ogt float %26, %max.3.11 + %27 = trunc i64 %indvars.iv.next.1156 to i32 + %yindex.3.12 = select i1 %cmp10.12, i32 %27, i32 %yindex.3.11 + %xindex.3.12 = select i1 %cmp10.12, i32 %3, i32 %xindex.3.11 + %max.3.12 = select i1 %cmp10.12, float %26, float %max.3.11 + %indvars.iv.next.1257 = or i64 %indvars.iv, 13 + %arrayidx9.13 = getelementptr inbounds [256 x [256 x float]]* @aa, i64 0, i64 %indvars.iv42, i64 %indvars.iv.next.1257 + %28 = load float* %arrayidx9.13, align 4, !tbaa !5 + %cmp10.13 = fcmp ogt float %28, %max.3.12 + %29 = trunc i64 %indvars.iv.next.1257 to i32 + %yindex.3.13 = select i1 %cmp10.13, i32 %29, i32 %yindex.3.12 + %xindex.3.13 = select i1 %cmp10.13, i32 %3, i32 %xindex.3.12 + %max.3.13 = select i1 %cmp10.13, float %28, float %max.3.12 + %indvars.iv.next.1358 = or i64 %indvars.iv, 14 + %arrayidx9.14 = getelementptr inbounds [256 x [256 x float]]* @aa, i64 0, i64 %indvars.iv42, i64 %indvars.iv.next.1358 + %30 = load float* %arrayidx9.14, align 8, !tbaa !5 + %cmp10.14 = fcmp ogt float %30, %max.3.13 + %31 = trunc i64 %indvars.iv.next.1358 to i32 + %yindex.3.14 = select i1 %cmp10.14, i32 %31, i32 %yindex.3.13 + %xindex.3.14 = select i1 %cmp10.14, i32 %3, i32 %xindex.3.13 + %max.3.14 = select i1 %cmp10.14, float %30, float %max.3.13 + %indvars.iv.next.1459 = or i64 %indvars.iv, 15 + %arrayidx9.15 = getelementptr inbounds [256 x [256 x float]]* @aa, i64 0, i64 %indvars.iv42, i64 %indvars.iv.next.1459 + %32 = load float* %arrayidx9.15, align 4, !tbaa !5 + %cmp10.15 = fcmp ogt float %32, %max.3.14 + %33 = trunc i64 %indvars.iv.next.1459 to i32 + %yindex.3.15 = select i1 %cmp10.15, i32 %33, i32 %yindex.3.14 + %xindex.3.15 = select i1 %cmp10.15, i32 %3, i32 %xindex.3.14 + %max.3.15 = select i1 %cmp10.15, float %32, float %max.3.14 + %indvars.iv.next.15 = add i64 %indvars.iv, 16 + %lftr.wideiv.15 = trunc i64 %indvars.iv.next.15 to i32 + %exitcond.15 = icmp eq i32 %lftr.wideiv.15, 256 + br i1 %exitcond.15, label %for.inc15, label %for.body7 + +for.inc15: ; preds = %for.body7 + %indvars.iv.next43 = add i64 %indvars.iv42, 1 + %lftr.wideiv = trunc i64 %indvars.iv.next43 to i32 + %exitcond = icmp eq i32 %lftr.wideiv, 256 + br i1 %exitcond, label %for.end17, label %for.cond5.preheader + +for.end17: ; preds = %for.inc15 + %conv = sitofp i32 %xindex.3.15 to float + %add = fadd float %max.3.15, %conv + %conv18 = sitofp i32 %yindex.3.15 to float + %add19 = fadd float %add, %conv18 + %call20 = tail call i32 @dummy(float* getelementptr inbounds ([32000 x float]* @a, i64 0, i64 0), float* getelementptr inbounds ([32000 x float]* @b, i64 0, i64 0), float* getelementptr inbounds ([32000 x float]* @c, i64 0, i64 0), float* getelementptr inbounds ([32000 x float]* @d, i64 0, i64 0), float* getelementptr inbounds ([32000 x float]* @e, i64 0, i64 0), [256 x float]* getelementptr inbounds ([256 x [256 x float]]* @aa, i64 0, i64 0), [256 x float]* getelementptr inbounds ([256 x [256 x float]]* @bb, i64 0, i64 0), [256 x float]* getelementptr inbounds ([256 x [256 x float]]* @cc, i64 0, i64 0), float %add19) nounwind + %inc22 = add nsw i32 %nl.041, 1 + %exitcond44 = icmp eq i32 %inc22, 78100 + br i1 %exitcond44, label %for.end23, label %for.body + +for.end23: ; preds = %for.end17 + %call24 = tail call i64 @clock() nounwind + %sub = sub nsw i64 %call24, %call1 + %conv25 = sitofp i64 %sub to double + %div = fdiv double %conv25, 1.000000e+06 + %call26 = tail call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([15 x i8]* @.str235, i64 0, i64 0), double %div) nounwind + %add29 = fadd float %add, 1.000000e+00 + %add31 = fadd float %add29, %conv18 + %add32 = fadd float %add31, 1.000000e+00 + store float %add32, float* @temp, align 4, !tbaa !5 + tail call void @check(i32 -1) + ret i32 0 +} + +declare void @llvm.memcpy.p0i8.p0i8.i64(i8* nocapture, i8* nocapture, i64, i32, i1) nounwind + +declare i32 @puts(i8* nocapture) nounwind + +!0 = metadata !{metadata !"any pointer", metadata !1} +!1 = metadata !{metadata !"omnipotent char", metadata !2} +!2 = metadata !{metadata !"Simple C/C++ TBAA", null} +!3 = metadata !{metadata !"branch_weights", i32 64, i32 4} +!4 = metadata !{metadata !"int", metadata !1} +!5 = metadata !{metadata !"float", metadata !1} From spop at codeaurora.org Tue Dec 6 11:34:16 2011 From: spop at codeaurora.org (Sebastian Pop) Date: Tue, 06 Dec 2011 17:34:16 -0000 Subject: [llvm-commits] [llvm] r145944 - in /llvm/trunk: include/llvm/CodeGen/DFAPacketizer.h lib/CodeGen/DFAPacketizer.cpp utils/TableGen/DFAPacketizerEmitter.cpp utils/TableGen/DFAPacketizerEmitter.h utils/TableGen/SubtargetEmitter.cpp Message-ID: <20111206173416.848771BE003@llvm.org> Author: spop Date: Tue Dec 6 11:34:16 2011 New Revision: 145944 URL: http://llvm.org/viewvc/llvm-project?rev=145944&view=rev Log: use space star instead of star space Modified: llvm/trunk/include/llvm/CodeGen/DFAPacketizer.h llvm/trunk/lib/CodeGen/DFAPacketizer.cpp llvm/trunk/utils/TableGen/DFAPacketizerEmitter.cpp llvm/trunk/utils/TableGen/DFAPacketizerEmitter.h llvm/trunk/utils/TableGen/SubtargetEmitter.cpp Modified: llvm/trunk/include/llvm/CodeGen/DFAPacketizer.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/DFAPacketizer.h?rev=145944&r1=145943&r2=145944&view=diff ============================================================================== --- llvm/trunk/include/llvm/CodeGen/DFAPacketizer.h (original) +++ llvm/trunk/include/llvm/CodeGen/DFAPacketizer.h Tue Dec 6 11:34:16 2011 @@ -49,8 +49,8 @@ void ReadTable(unsigned int state); public: - DFAPacketizer(const InstrItineraryData* I, const int (*SIT)[2], - const unsigned* SET); + DFAPacketizer(const InstrItineraryData *I, const int (*SIT)[2], + const unsigned *SET); // Reset the current state to make all resources available. void clearResources() { @@ -59,19 +59,19 @@ // canReserveResources - Check if the resources occupied by a MCInstrDesc // are available in the current state. - bool canReserveResources(const llvm::MCInstrDesc* MID); + bool canReserveResources(const llvm::MCInstrDesc *MID); // reserveResources - Reserve the resources occupied by a MCInstrDesc and // change the current state to reflect that change. - void reserveResources(const llvm::MCInstrDesc* MID); + void reserveResources(const llvm::MCInstrDesc *MID); // canReserveResources - Check if the resources occupied by a machine // instruction are available in the current state. - bool canReserveResources(llvm::MachineInstr* MI); + bool canReserveResources(llvm::MachineInstr *MI); // reserveResources - Reserve the resources occupied by a machine // instruction and change the current state to reflect that change. - void reserveResources(llvm::MachineInstr* MI); + void reserveResources(llvm::MachineInstr *MI); }; } Modified: llvm/trunk/lib/CodeGen/DFAPacketizer.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/DFAPacketizer.cpp?rev=145944&r1=145943&r2=145944&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/DFAPacketizer.cpp (original) +++ llvm/trunk/lib/CodeGen/DFAPacketizer.cpp Tue Dec 6 11:34:16 2011 @@ -29,7 +29,7 @@ using namespace llvm; DFAPacketizer::DFAPacketizer(const InstrItineraryData *I, const int (*SIT)[2], - const unsigned* SET): + const unsigned *SET): InstrItins(I), CurrentState(0), DFAStateInputTable(SIT), DFAStateEntryTable(SET) {} @@ -60,9 +60,9 @@ // canReserveResources - Check if the resources occupied by a MCInstrDesc // are available in the current state. -bool DFAPacketizer::canReserveResources(const llvm::MCInstrDesc* MID) { +bool DFAPacketizer::canReserveResources(const llvm::MCInstrDesc *MID) { unsigned InsnClass = MID->getSchedClass(); - const llvm::InstrStage* IS = InstrItins->beginStage(InsnClass); + const llvm::InstrStage *IS = InstrItins->beginStage(InsnClass); unsigned FuncUnits = IS->getUnits(); UnsignPair StateTrans = UnsignPair(CurrentState, FuncUnits); ReadTable(CurrentState); @@ -72,9 +72,9 @@ // reserveResources - Reserve the resources occupied by a MCInstrDesc and // change the current state to reflect that change. -void DFAPacketizer::reserveResources(const llvm::MCInstrDesc* MID) { +void DFAPacketizer::reserveResources(const llvm::MCInstrDesc *MID) { unsigned InsnClass = MID->getSchedClass(); - const llvm::InstrStage* IS = InstrItins->beginStage(InsnClass); + const llvm::InstrStage *IS = InstrItins->beginStage(InsnClass); unsigned FuncUnits = IS->getUnits(); UnsignPair StateTrans = UnsignPair(CurrentState, FuncUnits); ReadTable(CurrentState); @@ -85,14 +85,14 @@ // canReserveResources - Check if the resources occupied by a machine // instruction are available in the current state. -bool DFAPacketizer::canReserveResources(llvm::MachineInstr* MI) { - const llvm::MCInstrDesc& MID = MI->getDesc(); +bool DFAPacketizer::canReserveResources(llvm::MachineInstr *MI) { + const llvm::MCInstrDesc &MID = MI->getDesc(); return canReserveResources(&MID); } // reserveResources - Reserve the resources occupied by a machine // instruction and change the current state to reflect that change. -void DFAPacketizer::reserveResources(llvm::MachineInstr* MI) { - const llvm::MCInstrDesc& MID = MI->getDesc(); +void DFAPacketizer::reserveResources(llvm::MachineInstr *MI) { + const llvm::MCInstrDesc &MID = MI->getDesc(); reserveResources(&MID); } Modified: llvm/trunk/utils/TableGen/DFAPacketizerEmitter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/DFAPacketizerEmitter.cpp?rev=145944&r1=145943&r2=145944&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/DFAPacketizerEmitter.cpp (original) +++ llvm/trunk/utils/TableGen/DFAPacketizerEmitter.cpp Tue Dec 6 11:34:16 2011 @@ -53,7 +53,7 @@ std::set stateInfo; State(); - State(const State& S); + State(const State &S); // // canAddInsnClass - Returns true if an instruction of type InsnClass is a @@ -63,7 +63,7 @@ // PossibleStates is the set of valid resource states that ensue from valid // transitions. // - bool canAddInsnClass(unsigned InsnClass, std::set& PossibleStates); + bool canAddInsnClass(unsigned InsnClass, std::set &PossibleStates); }; } // End anonymous namespace. @@ -73,11 +73,11 @@ public: static int currentTransitionNum; int transitionNum; - State* from; + State *from; unsigned input; - State* to; + State *to; - Transition(State* from_, unsigned input_, State* to_); + Transition(State *from_, unsigned input_, State *to_); }; } // End anonymous namespace. @@ -87,7 +87,7 @@ // namespace { struct ltState { - bool operator()(const State* s1, const State* s2) const; + bool operator()(const State *s1, const State *s2) const; }; } // End anonymous namespace. @@ -105,7 +105,7 @@ // Map from a state to the list of transitions with that state as source. std::map, ltState> stateTransitions; - State* currentState; + State *currentState; // Highest valued Input seen. unsigned LargestInput; @@ -114,25 +114,25 @@ // Modify the DFA. // void initialize(); - void addState(State*); - void addTransition(Transition*); + void addState(State *); + void addTransition(Transition *); // // getTransition - Return the state when a transition is made from // State From with Input I. If a transition is not found, return NULL. // - State* getTransition(State*, unsigned); + State *getTransition(State *, unsigned); // // isValidTransition: Predicate that checks if there is a valid transition // from state From on input InsnClass. // - bool isValidTransition(State* From, unsigned InsnClass); + bool isValidTransition(State *From, unsigned InsnClass); // // writeTable: Print out a table representing the DFA. // - void writeTableAndAPI(raw_ostream &OS, const std::string& ClassName); + void writeTableAndAPI(raw_ostream &OS, const std::string &ClassName); }; } // End anonymous namespace. @@ -144,12 +144,12 @@ stateNum(currentStateNum++), isInitial(false) {} -State::State(const State& S) : +State::State(const State &S) : stateNum(currentStateNum++), isInitial(S.isInitial), stateInfo(S.stateInfo) {} -Transition::Transition(State* from_, unsigned input_, State* to_) : +Transition::Transition(State *from_, unsigned input_, State *to_) : transitionNum(currentTransitionNum++), from(from_), input(input_), to(to_) {} @@ -158,7 +158,7 @@ LargestInput(0) {} -bool ltState::operator()(const State* s1, const State* s2) const { +bool ltState::operator()(const State *s1, const State *s2) const { return (s1->stateNum < s2->stateNum); } @@ -172,7 +172,7 @@ // transitions. // bool State::canAddInsnClass(unsigned InsnClass, - std::set& PossibleStates) { + std::set &PossibleStates) { // // Iterate over all resource states in currentState. // @@ -224,13 +224,13 @@ } -void DFA::addState(State* S) { +void DFA::addState(State *S) { assert(!states.count(S) && "State already exists"); states.insert(S); } -void DFA::addTransition(Transition* T) { +void DFA::addTransition(Transition *T) { // Update LargestInput. if (T->input > LargestInput) LargestInput = T->input; @@ -244,7 +244,7 @@ // getTransition - Return the state when a transition is made from // State From with Input I. If a transition is not found, return NULL. // -State* DFA::getTransition(State* From, unsigned I) { +State *DFA::getTransition(State *From, unsigned I) { // Do we have a transition from state From? if (!stateTransitions.count(From)) return NULL; @@ -260,7 +260,7 @@ } -bool DFA::isValidTransition(State* From, unsigned InsnClass) { +bool DFA::isValidTransition(State *From, unsigned InsnClass) { return (getTransition(From, InsnClass) != NULL); } @@ -268,7 +268,7 @@ int State::currentStateNum = 0; int Transition::currentTransitionNum = 0; -DFAGen::DFAGen(RecordKeeper& R): +DFAGen::DFAGen(RecordKeeper &R): TargetName(CodeGenTarget(R).getName()), allInsnClasses(), Records(R) {} @@ -284,7 +284,7 @@ // the ith state. // // -void DFA::writeTableAndAPI(raw_ostream &OS, const std::string& TargetName) { +void DFA::writeTableAndAPI(raw_ostream &OS, const std::string &TargetName) { std::set::iterator SI = states.begin(); // This table provides a map to the beginning of the transitions for State s // in DFAStateInputTable. @@ -334,7 +334,7 @@ std::string SubTargetClassName = TargetName + "GenSubtargetInfo"; OS << "\n" << "#include \"llvm/CodeGen/DFAPacketizer.h\"\n"; OS << "namespace llvm {\n"; - OS << "DFAPacketizer* " << SubTargetClassName << "::" + OS << "DFAPacketizer *" << SubTargetClassName << "::" << "createDFAPacketizer(const InstrItineraryData *IID) const {\n" << " return new DFAPacketizer(IID, " << TargetName << "DFAStateInputTable, " << TargetName << "DFAStateEntryTable);\n}\n\n"; @@ -444,7 +444,7 @@ // Run a worklist algorithm to generate the DFA. // DFA D; - State* Initial = new State; + State *Initial = new State; Initial->isInitial = true; Initial->stateInfo.insert(0x0); D.addState(Initial); @@ -471,7 +471,7 @@ // Add S' to Visited // while (!WorkList.empty()) { - State* current = WorkList.pop_back_val(); + State *current = WorkList.pop_back_val(); for (DenseSet::iterator CI = allInsnClasses.begin(), CE = allInsnClasses.end(); CI != CE; ++CI) { unsigned InsnClass = *CI; @@ -483,7 +483,7 @@ // if (!D.getTransition(current, InsnClass) && current->canAddInsnClass(InsnClass, NewStateResources)) { - State* NewState = NULL; + State *NewState = NULL; // // If we have seen this state before, then do not create a new state. @@ -500,7 +500,7 @@ WorkList.push_back(NewState); } - Transition* NewTransition = new Transition(current, InsnClass, + Transition *NewTransition = new Transition(current, InsnClass, NewState); D.addTransition(NewTransition); } Modified: llvm/trunk/utils/TableGen/DFAPacketizerEmitter.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/DFAPacketizerEmitter.h?rev=145944&r1=145943&r2=145944&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/DFAPacketizerEmitter.h (original) +++ llvm/trunk/utils/TableGen/DFAPacketizerEmitter.h Tue Dec 6 11:34:16 2011 @@ -38,7 +38,7 @@ RecordKeeper &Records; public: - DFAGen(RecordKeeper& R); + DFAGen(RecordKeeper &R); // // collectAllInsnClasses: Populate allInsnClasses which is a set of units Modified: llvm/trunk/utils/TableGen/SubtargetEmitter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/SubtargetEmitter.cpp?rev=145944&r1=145943&r2=145944&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/SubtargetEmitter.cpp (original) +++ llvm/trunk/utils/TableGen/SubtargetEmitter.cpp Tue Dec 6 11:34:16 2011 @@ -716,7 +716,7 @@ << " explicit " << ClassName << "(StringRef TT, StringRef CPU, " << "StringRef FS);\n" << "public:\n" - << " DFAPacketizer* createDFAPacketizer(const InstrItineraryData* IID)" + << " DFAPacketizer *createDFAPacketizer(const InstrItineraryData *IID)" << " const;\n" << "};\n"; OS << "} // End llvm namespace \n"; From anton at korobeynikov.info Tue Dec 6 12:01:00 2011 From: anton at korobeynikov.info (Anton Korobeynikov) Date: Tue, 6 Dec 2011 22:01:00 +0400 Subject: [llvm-commits] Fix constructor order on ARM/ELF In-Reply-To: References: <4ED53E4E.8060205@free.fr> Message-ID: > Yes, at the moment we only preserve constructor order inside a > translation unit. > AFAIK, gcc emits multiple init_array. sections, and therefore > preserves correct global constructor order. Yes. I already have patch for this :) I just need to make sure I won't break darwin & windows. -- With best regards, Anton Korobeynikov Faculty of Mathematics and Mechanics, Saint Petersburg State University From kcc at google.com Tue Dec 6 15:11:50 2011 From: kcc at google.com (Kostya Serebryany) Date: Tue, 06 Dec 2011 21:11:50 -0000 Subject: [llvm-commits] [compiler-rt] r145967 - in /compiler-rt/trunk: Makefile make/config.mk Message-ID: <20111206211150.9ADB71BE003@llvm.org> Author: kcc Date: Tue Dec 6 15:11:50 2011 New Revision: 145967 URL: http://llvm.org/viewvc/llvm-project?rev=145967&view=rev Log: build all C++ files in compiler-rt with -fno-exceptions Modified: compiler-rt/trunk/Makefile compiler-rt/trunk/make/config.mk Modified: compiler-rt/trunk/Makefile URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/Makefile?rev=145967&r1=145966&r2=145967&view=diff ============================================================================== --- compiler-rt/trunk/Makefile (original) +++ compiler-rt/trunk/Makefile Tue Dec 6 15:11:50 2011 @@ -230,7 +230,7 @@ $(Verb) $(Tmp.CC) $(Tmp.CFLAGS) -c -o $$@ $$< $(Tmp.ObjPath)/%.o: $(Tmp.SrcPath)/%.cc $(Tmp.Dependencies) $(Tmp.ObjPath)/.dir $(Summary) " COMPILE: $(Tmp.Name)/$(Tmp.Config)/$(Tmp.Arch): $$<" - $(Verb) $(Tmp.CC) $(Tmp.CFLAGS) -c -o $$@ $$< + $(Verb) $(Tmp.CC) $(Tmp.CFLAGS) -c $(COMMON_CXXFLAGS) -o $$@ $$< .PRECIOUS: $(Tmp.ObjPath)/.dir endef Modified: compiler-rt/trunk/make/config.mk URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/make/config.mk?rev=145967&r1=145966&r2=145967&view=diff ============================================================================== --- compiler-rt/trunk/make/config.mk (original) +++ compiler-rt/trunk/make/config.mk Tue Dec 6 15:11:50 2011 @@ -39,3 +39,7 @@ ifndef Summary Summary = $(Echo) endif + +### +# Common compiler options +COMMON_CXXFLAGS=-fno-exceptions From stoklund at 2pi.dk Tue Dec 6 15:55:35 2011 From: stoklund at 2pi.dk (Jakob Stoklund Olesen) Date: Tue, 06 Dec 2011 21:55:35 -0000 Subject: [llvm-commits] [llvm] r145970 - /llvm/trunk/lib/Target/ARM/ARMConstantIslandPass.cpp Message-ID: <20111206215535.ECAC91BE003@llvm.org> Author: stoklund Date: Tue Dec 6 15:55:35 2011 New Revision: 145970 URL: http://llvm.org/viewvc/llvm-project?rev=145970&view=rev Log: Remove alignment from deserted constant islands. ARMConstantIslandPass may sometimes leave empty constant islands behind (it really shouldn't). Remove the alignment from the empty islands so the size calculations are still correct. This should fix the many Thumb1 assembler errors in the nightly test suite. The reduced test case for this problem is way too big. That is to be expected for ARMConstantIslandPass bugs. Modified: llvm/trunk/lib/Target/ARM/ARMConstantIslandPass.cpp Modified: llvm/trunk/lib/Target/ARM/ARMConstantIslandPass.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMConstantIslandPass.cpp?rev=145970&r1=145969&r2=145970&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMConstantIslandPass.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMConstantIslandPass.cpp Tue Dec 6 15:55:35 2011 @@ -1355,6 +1355,9 @@ Size += BBSizes[CPEBB->getNumber()]; BBSizes[CPEBB->getNumber()] = 0; } + + // This block no longer needs to be aligned. . + CPEBB->setAlignment(0); } AdjustBBOffsetsAfter(CPEBB, -Size); // An island has only one predecessor BB and one successor BB. Check if From hfinkel at anl.gov Tue Dec 6 14:55:37 2011 From: hfinkel at anl.gov (Hal Finkel) Date: Tue, 06 Dec 2011 20:55:37 -0000 Subject: [llvm-commits] [llvm] r145961 - in /llvm/trunk/lib/Target/PowerPC: PPCInstrInfo.cpp PPCInstrInfo.h PPCInstrInfo.td PPCRegisterInfo.cpp PPCRegisterInfo.h Message-ID: <20111206205537.23C691BE003@llvm.org> Author: hfinkel Date: Tue Dec 6 14:55:36 2011 New Revision: 145961 URL: http://llvm.org/viewvc/llvm-project?rev=145961&view=rev Log: add RESTORE_CR and support CR unspills Modified: llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.cpp llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.h llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.td llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.cpp llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.h Modified: llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.cpp?rev=145961&r1=145960&r2=145961&view=diff ============================================================================== --- llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.cpp (original) +++ llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.cpp Tue Dec 6 14:55:36 2011 @@ -511,7 +511,7 @@ NewMIs.back()->addMemOperand(MF, MMO); } -void +bool PPCInstrInfo::LoadRegFromStackSlot(MachineFunction &MF, DebugLoc DL, unsigned DestReg, int FrameIdx, const TargetRegisterClass *RC, @@ -541,28 +541,36 @@ NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LFS), DestReg), FrameIdx)); } else if (PPC::CRRCRegisterClass->hasSubClassEq(RC)) { - // FIXME: We need a scatch reg here. The trouble with using R0 is that - // it's possible for the stack frame to be so big the save location is - // out of range of immediate offsets, necessitating another register. - // We hack this on Darwin by reserving R2. It's probably broken on Linux - // at the moment. - unsigned ScratchReg = TM.getSubtargetImpl()->isDarwinABI() ? - PPC::R2 : PPC::R0; - NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LWZ), - ScratchReg), FrameIdx)); - - // If the reloaded register isn't CR0, shift the bits right so that they are - // in the right CR's slot. - if (DestReg != PPC::CR0) { - unsigned ShiftBits = getPPCRegisterNumbering(DestReg)*4; - // rlwinm r11, r11, 32-ShiftBits, 0, 31. - NewMIs.push_back(BuildMI(MF, DL, get(PPC::RLWINM), ScratchReg) - .addReg(ScratchReg).addImm(32-ShiftBits).addImm(0) - .addImm(31)); + if ((!DisablePPC32RS && !TM.getSubtargetImpl()->isPPC64()) || + (!DisablePPC64RS && TM.getSubtargetImpl()->isPPC64())) { + NewMIs.push_back(addFrameReference(BuildMI(MF, DL, + get(PPC::RESTORE_CR), DestReg) + , FrameIdx)); + return true; + } else { + // FIXME: We need a scatch reg here. The trouble with using R0 is that + // it's possible for the stack frame to be so big the save location is + // out of range of immediate offsets, necessitating another register. + // We hack this on Darwin by reserving R2. It's probably broken on Linux + // at the moment. + unsigned ScratchReg = TM.getSubtargetImpl()->isDarwinABI() ? + PPC::R2 : PPC::R0; + NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LWZ), + ScratchReg), FrameIdx)); + + // If the reloaded register isn't CR0, shift the bits right so that they are + // in the right CR's slot. + if (DestReg != PPC::CR0) { + unsigned ShiftBits = getPPCRegisterNumbering(DestReg)*4; + // rlwinm r11, r11, 32-ShiftBits, 0, 31. + NewMIs.push_back(BuildMI(MF, DL, get(PPC::RLWINM), ScratchReg) + .addReg(ScratchReg).addImm(32-ShiftBits).addImm(0) + .addImm(31)); + } + + NewMIs.push_back(BuildMI(MF, DL, get(PPC::MTCRF), DestReg) + .addReg(ScratchReg)); } - - NewMIs.push_back(BuildMI(MF, DL, get(PPC::MTCRF), DestReg) - .addReg(ScratchReg)); } else if (PPC::CRBITRCRegisterClass->hasSubClassEq(RC)) { unsigned Reg = 0; @@ -607,6 +615,8 @@ } else { llvm_unreachable("Unknown regclass!"); } + + return false; } void @@ -619,7 +629,10 @@ SmallVector NewMIs; DebugLoc DL; if (MI != MBB.end()) DL = MI->getDebugLoc(); - LoadRegFromStackSlot(MF, DL, DestReg, FrameIdx, RC, NewMIs); + if (LoadRegFromStackSlot(MF, DL, DestReg, FrameIdx, RC, NewMIs)) { + PPCFunctionInfo *FuncInfo = MF.getInfo(); + FuncInfo->setSpillsCR(); + } for (unsigned i = 0, e = NewMIs.size(); i != e; ++i) MBB.insert(MI, NewMIs[i]); Modified: llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.h?rev=145961&r1=145960&r2=145961&view=diff ============================================================================== --- llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.h (original) +++ llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.h Tue Dec 6 14:55:36 2011 @@ -72,7 +72,7 @@ unsigned SrcReg, bool isKill, int FrameIdx, const TargetRegisterClass *RC, SmallVectorImpl &NewMIs) const; - void LoadRegFromStackSlot(MachineFunction &MF, DebugLoc DL, + bool LoadRegFromStackSlot(MachineFunction &MF, DebugLoc DL, unsigned DestReg, int FrameIdx, const TargetRegisterClass *RC, SmallVectorImpl &NewMIs) const; Modified: llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.td?rev=145961&r1=145960&r2=145961&view=diff ============================================================================== --- llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.td (original) +++ llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.td Tue Dec 6 14:55:36 2011 @@ -402,6 +402,11 @@ def SPILL_CR : Pseudo<(outs), (ins GPRC:$cond, memri:$F), "", []>; +// RESTORE_CR - Indicate that we're restoring the CR register (previously +// spilled), so we'll need to scavenge a register for it. +def RESTORE_CR : Pseudo<(outs GPRC:$cond), (ins memri:$F), + "", []>; + let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7 in { let isReturn = 1, Uses = [LR, RM] in def BLR : XLForm_2_br<19, 16, 0, (outs), (ins pred:$p), Modified: llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.cpp?rev=145961&r1=145960&r2=145961&view=diff ============================================================================== --- llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.cpp (original) +++ llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.cpp Tue Dec 6 14:55:36 2011 @@ -459,7 +459,7 @@ unsigned FrameIndex, int SPAdj, RegScavenger *RS) const { // Get the instruction. - MachineInstr &MI = *II; // ; SPILL_CR , , + MachineInstr &MI = *II; // ; SPILL_CR , // Get the instruction's basic block. MachineBasicBlock &MBB = *MI.getParent(); DebugLoc dl = MI.getDebugLoc(); @@ -494,6 +494,44 @@ MBB.erase(II); } +void PPCRegisterInfo::lowerCRRestore(MachineBasicBlock::iterator II, + unsigned FrameIndex, int SPAdj, + RegScavenger *RS) const { + // Get the instruction. + MachineInstr &MI = *II; // ; = RESTORE_CR + // Get the instruction's basic block. + MachineBasicBlock &MBB = *MI.getParent(); + DebugLoc dl = MI.getDebugLoc(); + + const TargetRegisterClass *G8RC = &PPC::G8RCRegClass; + const TargetRegisterClass *GPRC = &PPC::GPRCRegClass; + const TargetRegisterClass *RC = Subtarget.isPPC64() ? G8RC : GPRC; + unsigned Reg = findScratchRegister(II, RS, RC, SPAdj); + unsigned DestReg = MI.getOperand(0).getReg(); + assert(MI.definesRegister(DestReg) && + "RESTORE_CR does not define its destination"); + bool LP64 = Subtarget.isPPC64(); + + addFrameReference(BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::LWZ8 : PPC::LWZ), + Reg), FrameIndex); + + // If the reloaded register isn't CR0, shift the bits right so that they are + // in the right CR's slot. + if (DestReg != PPC::CR0) { + unsigned ShiftBits = getPPCRegisterNumbering(DestReg)*4; + // rlwinm r11, r11, 32-ShiftBits, 0, 31. + BuildMI(MBB, II, dl, TII.get(PPC::RLWINM), Reg) + .addReg(Reg).addImm(32-ShiftBits).addImm(0) + .addImm(31); + } + + BuildMI(MBB, II, dl, TII.get(PPC::MTCRF), DestReg) + .addReg(Reg); + + // Discard the pseudo instruction. + MBB.erase(II); +} + void PPCRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj, RegScavenger *RS) const { @@ -539,12 +577,16 @@ return; } - // Special case for pseudo-op SPILL_CR. - if (requiresRegisterScavenging(MF)) + // Special case for pseudo-ops SPILL_CR and RESTORE_CR. + if (requiresRegisterScavenging(MF)) { if (OpC == PPC::SPILL_CR) { lowerCRSpilling(II, FrameIndex, SPAdj, RS); return; + } else if (OpC == PPC::RESTORE_CR) { + lowerCRRestore(II, FrameIndex, SPAdj, RS); + return; } + } // Replace the FrameIndex with base register with GPR1 (SP) or GPR31 (FP). MI.getOperand(FIOperandNo).ChangeToRegister(TFI->hasFP(MF) ? @@ -594,7 +636,6 @@ // The offset doesn't fit into a single register, scavenge one to build the // offset in. - // FIXME: figure out what SPAdj is doing here. unsigned SReg; if (requiresRegisterScavenging(MF)) Modified: llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.h?rev=145961&r1=145960&r2=145961&view=diff ============================================================================== --- llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.h (original) +++ llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.h Tue Dec 6 14:55:36 2011 @@ -57,6 +57,8 @@ int SPAdj, RegScavenger *RS) const; void lowerCRSpilling(MachineBasicBlock::iterator II, unsigned FrameIndex, int SPAdj, RegScavenger *RS) const; + void lowerCRRestore(MachineBasicBlock::iterator II, unsigned FrameIndex, + int SPAdj, RegScavenger *RS) const; void eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj, RegScavenger *RS = NULL) const; From adasgupt at codeaurora.org Tue Dec 6 17:12:42 2011 From: adasgupt at codeaurora.org (Anshuman Dasgupta) Date: Tue, 06 Dec 2011 23:12:42 -0000 Subject: [llvm-commits] [llvm] r145988 - /llvm/trunk/docs/CodeGenerator.html Message-ID: <20111206231242.E6B5C1BE003@llvm.org> Author: adasgupt Date: Tue Dec 6 17:12:42 2011 New Revision: 145988 URL: http://llvm.org/viewvc/llvm-project?rev=145988&view=rev Log: Add documentation for machine-independent DFA packetizer Modified: llvm/trunk/docs/CodeGenerator.html Modified: llvm/trunk/docs/CodeGenerator.html URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/CodeGenerator.html?rev=145988&r1=145987&r2=145988&view=diff ============================================================================== --- llvm/trunk/docs/CodeGenerator.html (original) +++ llvm/trunk/docs/CodeGenerator.html Tue Dec 6 17:12:42 2011 @@ -97,6 +97,14 @@
    • Built in register allocators
  • Code Emission
    • +
  • VLIW Packetizer + +
  • Implementing a Native Assembler
    • @@ -2001,6 +2009,73 @@ + +

    + VLIW Packetizer +

    + +
    + +

    In a Very Long Instruction Word (VLIW) architecture, the compiler is + responsible for mapping instructions to functional-units available on + the architecture. To that end, the compiler creates groups of instructions + called packets or bundles. The VLIW packetizer in LLVM is + a target-independent mechanism to enable the packetization of machine + instructions.

    + + + +

    + Mapping from instructions to functional units +

    + +
    + +

    Instructions in a VLIW target can typically be mapped to multiple functional +units. During the process of packetizing, the compiler must be able to reason +about whether an instruction can be added to a packet. This decision can be +complex since the compiler has to examine all possible mappings of instructions +to functional units. Therefore to alleviate compilation-time complexity, the +VLIW packetizer parses the instruction classes of a target and generates tables +at compiler build time. These tables can then be queried by the provided +machine-independent API to determine if an instruction can be accommodated in a +packet.

    +
    + + +

    + + How the packetization tables are generated and used + +

    + +
    + +

    The packetizer reads instruction classes from a target's itineraries and +creates a deterministic finite automaton (DFA) to represent the state of a +packet. A DFA consists of three major elements: inputs, states, and +transitions. The set of inputs for the generated DFA represents the instruction +being added to a packet. The states represent the possible consumption +of functional units by instructions in a packet. In the DFA, transitions from +one state to another occur on the addition of an instruction to an existing +packet. If there is a legal mapping of functional units to instructions, then +the DFA contains a corresponding transition. The absence of a transition +indicates that a legal mapping does not exist and that the instruction cannot +be added to the packet.

    + +

    To generate tables for a VLIW target, add TargetGenDFAPacketizer.inc +as a target to the Makefile in the target directory. The exported API provides +three functions: DFAPacketizer::clearResources(), +DFAPacketizer::reserveResources(MachineInstr *MI), and +DFAPacketizer::canReserveResources(MachineInstr *MI). These functions +allow a target packetizer to add an instruction to an existing packet and to +check whether an instruction can be added to a packet. See +llvm/CodeGen/DFAPacketizer.h for more information.

    + +
    + +
    + From stoklund at 2pi.dk Tue Dec 6 15:08:39 2011 From: stoklund at 2pi.dk (Jakob Stoklund Olesen) Date: Tue, 06 Dec 2011 21:08:39 -0000 Subject: [llvm-commits] [llvm] r145965 - /llvm/trunk/lib/CodeGen/MachineBasicBlock.cpp Message-ID: <20111206210839.7E5001BE003@llvm.org> Author: stoklund Date: Tue Dec 6 15:08:39 2011 New Revision: 145965 URL: http://llvm.org/viewvc/llvm-project?rev=145965&view=rev Log: Pretty-print basic block alignment. Modified: llvm/trunk/lib/CodeGen/MachineBasicBlock.cpp Modified: llvm/trunk/lib/CodeGen/MachineBasicBlock.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineBasicBlock.cpp?rev=145965&r1=145964&r2=145965&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/MachineBasicBlock.cpp (original) +++ llvm/trunk/lib/CodeGen/MachineBasicBlock.cpp Tue Dec 6 15:08:39 2011 @@ -203,8 +203,6 @@ return; } - if (Alignment) { OS << "Alignment " << Alignment << "\n"; } - if (Indexes) OS << Indexes->getMBBStartIdx(this) << '\t'; @@ -218,6 +216,12 @@ } if (isLandingPad()) { OS << Comma << "EH LANDING PAD"; Comma = ", "; } if (hasAddressTaken()) { OS << Comma << "ADDRESS TAKEN"; Comma = ", "; } + if (Alignment) { + OS << Comma << "Align " << Alignment << " (" << (1u << Alignment) + << " bytes)"; + Comma = ", "; + } + OS << '\n'; const TargetRegisterInfo *TRI = MF->getTarget().getRegisterInfo(); From daniel at zuster.org Tue Dec 6 17:13:43 2011 From: daniel at zuster.org (Daniel Dunbar) Date: Tue, 06 Dec 2011 23:13:43 -0000 Subject: [llvm-commits] [llvm] r145989 - /llvm/trunk/utils/llvm-build/llvmbuild/main.py Message-ID: <20111206231343.1AA011BE003@llvm.org> Author: ddunbar Date: Tue Dec 6 17:13:42 2011 New Revision: 145989 URL: http://llvm.org/viewvc/llvm-project?rev=145989&view=rev Log: llvm-build: Don't generate duplicate dependencies when LLVMBuild files define multiple components. Modified: llvm/trunk/utils/llvm-build/llvmbuild/main.py Modified: llvm/trunk/utils/llvm-build/llvmbuild/main.py URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/llvm-build/llvmbuild/main.py?rev=145989&r1=145988&r2=145989&view=diff ============================================================================== --- llvm/trunk/utils/llvm-build/llvmbuild/main.py (original) +++ llvm/trunk/utils/llvm-build/llvmbuild/main.py Tue Dec 6 17:13:42 2011 @@ -397,9 +397,15 @@ # Construct a list of all the dependencies of the Makefile fragment # itself. These include all the LLVMBuild files themselves, as well as # all of our own sources. + # + # Many components may come from the same file, so we make sure to unique + # these. + build_paths = set() for ci in self.component_infos: - yield os.path.join(self.source_root, ci.subpath[1:], - 'LLVMBuild.txt') + p = os.path.join(self.source_root, ci.subpath[1:], 'LLVMBuild.txt') + if p not in build_paths: + yield p + build_paths.add(p) # Gather the list of necessary sources by just finding all loaded # modules that are inside the LLVM source tree. From kcc at google.com Tue Dec 6 13:14:05 2011 From: kcc at google.com (Kostya Serebryany) Date: Tue, 6 Dec 2011 11:14:05 -0800 Subject: [llvm-commits] AddressSanitizer GCD tests on Mac: prevent optimization, enable. In-Reply-To: References: Message-ID: r145953 On Tue, Dec 6, 2011 at 3:04 AM, Alexander Potapenko wrote: > Including asan_test_utils.h is not possible, because 'extern "C"' and > 'template' is not valid ObjC code. > Let it be volatile, otherwise we'll need to write a separate > asan_test_utils for ObjC, which'll be an overkill. > > On Mon, Dec 5, 2011 at 11:04 PM, Kostya Serebryany wrote: > > I wonder if you can reuse Ident() from tests/asan_test_utils.h instead of > > using volatile. > > Like this: > > char *mem = Ident(malloc(10)); > > > > // This function returns its parameter but in such a way that compiler > > > > > > // can not prove it. > > > > > > template > > > > > > __attribute__((noinline)) > > > > > > static T Ident(T t) { > > ... > > > > > > --kcc > > > > > > On Mon, Dec 5, 2011 at 12:44 AM, Alexander Potapenko > > wrote: > >> > >> Fix GCD tests for AddressSanitizer on Mac. > >> The following patch declares the char* vars holding the memory > >> allocations as volatile, which prevents the compiler from optimizing > >> them and breaking the tests. > >> I'm also enabling the tests by default, as the GCD support in ASan > >> runtime library is quite stable already. > >> > >> -- > >> Alexander Potapenko > >> Software Engineer > >> Google Moscow > > > > > > > > -- > Alexander Potapenko > Software Engineer > Google Moscow > -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20111206/642240b7/attachment.html From isanbard at gmail.com Tue Dec 6 16:18:12 2011 From: isanbard at gmail.com (Bill Wendling) Date: Tue, 06 Dec 2011 22:18:12 -0000 Subject: [llvm-commits] [llvm] r145977 - /llvm/trunk/lib/MC/MCDwarf.cpp Message-ID: <20111206221812.536791BE003@llvm.org> Author: void Date: Tue Dec 6 16:18:12 2011 New Revision: 145977 URL: http://llvm.org/viewvc/llvm-project?rev=145977&view=rev Log: Re-enable compact unwind. It seems to work now. Modified: llvm/trunk/lib/MC/MCDwarf.cpp Modified: llvm/trunk/lib/MC/MCDwarf.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCDwarf.cpp?rev=145977&r1=145976&r2=145977&view=diff ============================================================================== --- llvm/trunk/lib/MC/MCDwarf.cpp (original) +++ llvm/trunk/lib/MC/MCDwarf.cpp Tue Dec 6 16:18:12 2011 @@ -1009,10 +1009,7 @@ ArrayRef FrameArray = Streamer.getFrameInfos(); // Emit the compact unwind info if available. - // FIXME: This emits both the compact unwind and the old CIE/FDE - // information. Only one of those is needed. - // FIXME: Disable. This seems to still be causing failures. - if (false && IsEH && MOFI->getCompactUnwindSection()) + if (IsEH && MOFI->getCompactUnwindSection()) for (unsigned i = 0, n = Streamer.getNumFrameInfos(); i < n; ++i) { const MCDwarfFrameInfo &Frame = Streamer.getFrameInfo(i); if (Frame.CompactUnwindEncoding) From stpworld at narod.ru Tue Dec 6 14:42:05 2011 From: stpworld at narod.ru (Stepan Dyatkovskiy) Date: Wed, 07 Dec 2011 00:42:05 +0400 Subject: [llvm-commits] [LLVM, loop-unswitch, bugfix for #11429] Wrong behaviour for switches. In-Reply-To: <4EDCC136.1040903@narod.ru> References: <4ECF4A5A.9030607@narod.ru> <4ED36D99.1080306@narod.ru> <4ED51EEC.6050000@narod.ru> <4ED749D0.8030101@narod.ru> <4ED88CDF.2020104@narod.ru> <4EDCC136.1040903@narod.ru> Message-ID: <4EDE7E1D.9010609@narod.ru> ping. -Stepan. Stepan Dyatkovskiy wrote: > Hi Dan. This bug is described in details (with examples) here: > http://llvm.org/bugs/show_bug.cgi?id=11429 > > Regarding to your questions.. > >> It's even possible that this bug is >> accidentally helping the code by preventing it from unswitching too >> much in the presence of switches. >> Do you have an idea on what impact >> this patch has on code size, and performance, in general? > > Happily this bug helps to keep the code size small. But > LoopUnswitch::UnswitchIfProfitable method already controls the produced > code size. Please, see LoopUnswitch.cpp, string #446 for more details. I > think that if we need to improve the "restrictioning" of produced code > size we need to implement this improvement instead of keeping some > strange code. > > About impact on code size. > For switch with N cases (+ 1 default) we got N new loops. If you wish I > can present the .ll code that should be produced after optimization. > > Impact on performance. > The main purpose of this optimization is to move out of loop the > switches. Each unswitched case increases the performance. > > About releaseMemory and CloneUnswitchedVals. > This methods the part of unswitch info cloning for new loops. It is also > described in bug #11429. > > > CloneUnswitchedVals doesn't actually need to iterate over the > > instructions in the block to find the SwitchInst. If there's a > > SwitchInst present, it'll be the Terminator instruction. > OK. You're right. Please find the fixed patch. > > Thanks! > -Stepan. > >> >> Thanks, >> >> Dan >> >> On Dec 2, 2011, at 12:31 AM, Stepan Dyatkovskiy wrote: >> >>> >>> ping. >>> >>> -Stepan. >>> Stepan Dyatkovskiy wrote: >>>> ping. >>>> >>>> -Stepan. >>>> >>>> Stepan Dyatkovskiy wrote: >>>>> ping. >>>>> >>>>> -Stepan. >>>>> >>>>> Stepan Dyatkovskiy wrote: >>>>>> ping. >>>>>> >>>>>> -Stepan >>>>>> >>>>>> Stepan Dyatkovskiy wrote: >>>>>>> Hi all. Please find the patch in attachment for review. >>>>>>> Regression tests >>>>>>> are attached in separated patch. >>>>>>> >>>>>>> Short tests description: >>>>>>> >>>>>>> 2011-11-18-SimpleSwitch.ll >>>>>>> Check simple that simple switch will totally unswitched: >>>>>>> >>>>>>> for (...) >>>>>>> switch(c) { >>>>>>> case 0: inc(); break; >>>>>>> case 1: dec(); break; >>>>>>> default: goto loop_exit; >>>>>>> } >>>>>>> >>>>>>> loop_exit: >>>>>>> ... >>>>>>> >>>>>>> Result of processing should be 2 additional loops for c == 0 and >>>>>>> for c >>>>>>> == 1. >>>>>>> >>>>>>> >>>>>>> 2011-11-18-TwoSwitches.ll >>>>>>> Check that second switch will unswitched too. Check that switches >>>>>>> will >>>>>>> not unswitched again in new loop: >>>>>>> >>>>>>> Initially we have the next: >>>>>>> >>>>>>> for (...) { >>>>>>> switch(c) { >>>>>>> case 0: inc(); break; >>>>>>> } >>>>>>> switch(d) { >>>>>>> case 0: inc(); break; >>>>>>> } >>>>>>> } >>>>>>> >>>>>>> After optimization we should got 3 additional loops: when (c == >>>>>>> 0&& d >>>>>>> == 0), when (c == 0&& d != 0) and when (c != 0&& d == 0). Original >>>>>>> loop will activated for (c != 0&& d != 0): >>>>>>> >>>>>>> if (c == 0&& d == 0) { >>>>>>> for (...) ... // All is clear here. Two "switch(0)" instructions. >>>>>>> } else if (c == 0&& d != 0) { >>>>>>> for (...) { >>>>>>> switch (0) { // c == 0 >>>>>>> case 0: inc(); break; >>>>>>> } >>>>>>> switch (d) { >>>>>>> case 0: goto unreachable; // CHECK: That it will not unswitched >>>>>>> // again, since it looks "trivial", >>>>>>> // see LoopUnswitch::IsTrivialUnswitchCondition >>>>>>> } >>>>>>> } >>>>>>> } else if (c != 0&& d == 0) { >>>>>>> // the same... >>>>>>> ... >>>>>>> } else { // if (c != 0&& d != 0) >>>>>>> // Original totally unswitched loop: >>>>>>> switch (c) { >>>>>>> case 0: goto unreachable; >>>>>>> } >>>>>>> switch (d) { >>>>>>> case 0: goto unreachable; >>>>>>> } >>>>>>> } >>>>>>> >>>>>>> Stepan. >>>>>>> >>>>>>> >>>>>>> _______________________________________________ >>>>>>> llvm-commits mailing list >>>>>>> llvm-commits at cs.uiuc.edu >>>>>>> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits >>>>>> >>>>>> _______________________________________________ >>>>>> llvm-commits mailing list >>>>>> llvm-commits at cs.uiuc.edu >>>>>> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits >>>>> >>>>> _______________________________________________ >>>>> llvm-commits mailing list >>>>> llvm-commits at cs.uiuc.edu >>>>> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits >>>> >>>> _______________________________________________ >>>> llvm-commits mailing list >>>> llvm-commits at cs.uiuc.edu >>>> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits >>> >>> _______________________________________________ >>> llvm-commits mailing list >>> llvm-commits at cs.uiuc.edu >>> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits >> > > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From stoklund at 2pi.dk Tue Dec 6 15:55:39 2011 From: stoklund at 2pi.dk (Jakob Stoklund Olesen) Date: Tue, 06 Dec 2011 21:55:39 -0000 Subject: [llvm-commits] [llvm] r145971 - in /llvm/trunk/lib/Target/ARM: ARMBaseInstrInfo.cpp ARMConstantIslandPass.cpp Message-ID: <20111206215539.85F841BE003@llvm.org> Author: stoklund Date: Tue Dec 6 15:55:39 2011 New Revision: 145971 URL: http://llvm.org/viewvc/llvm-project?rev=145971&view=rev Log: Use conservative size estimate for tBR_JTr. This pseudo-instruction contains a .align directive in its expansion, so the total size may vary by 2 bytes. It is too difficult to accurately keep track of this alignment directive, just use the worst-case size instead. Modified: llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp llvm/trunk/lib/Target/ARM/ARMConstantIslandPass.cpp Modified: llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp?rev=145971&r1=145970&r2=145971&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp Tue Dec 6 15:55:39 2011 @@ -601,12 +601,12 @@ assert(JTI < JT.size()); // Thumb instructions are 2 byte aligned, but JT entries are 4 byte // 4 aligned. The assembler / linker may add 2 byte padding just before - // the JT entries. The size does not include this padding; the - // constant islands pass does separate bookkeeping for it. + // the JT entries. The size includes the worst case size of this padding. // FIXME: If we know the size of the function is less than (1 << 16) *2 // bytes, we can use 16-bit entries instead. Then there won't be an // alignment issue. - unsigned InstSize = (Opc == ARM::tBR_JTr || Opc == ARM::t2BR_JT) ? 2 : 4; + // tBR_JT is 2 bytes + 2 bytes worst case padding for table alignment. + unsigned InstSize = (Opc == ARM::t2BR_JT) ? 2 : 4; unsigned NumEntries = getNumJTEntries(JT, JTI); if (Opc == ARM::t2TBB_JT && (NumEntries & 1)) // Make sure the instruction that follows TBB is 2-byte aligned. Modified: llvm/trunk/lib/Target/ARM/ARMConstantIslandPass.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMConstantIslandPass.cpp?rev=145971&r1=145970&r2=145971&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMConstantIslandPass.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMConstantIslandPass.cpp Tue Dec 6 15:55:39 2011 @@ -525,13 +525,8 @@ // A Thumb1 table jump may involve padding; for the offsets to // be right, functions containing these must be 4-byte aligned. // tBR_JTr expands to a mov pc followed by .align 2 and then the jump - // table entries. So this code checks whether offset of tBR_JTr + 2 - // is aligned. That is held in Offset+MBBSize, which already has - // 2 added in for the size of the mov pc instruction. + // table entries. GetInstSizeInBytes returns the worst case size. MF.EnsureAlignment(2U); - if ((Offset+MBBSize)%4 != 0 || HasInlineAsm) - // FIXME: Add a pseudo ALIGN instruction instead. - MBBSize += 2; // padding continue; // Does not get an entry in ImmBranches case ARM::t2BR_JT: T2JumpTables.push_back(I); @@ -809,23 +804,6 @@ // Set the size of NewBB in BBSizes. It does not include any padding now. BBSizes[NewBBI] = NewBBSize; - MachineInstr* ThumbJTMI = prior(NewBB->end()); - if (ThumbJTMI->getOpcode() == ARM::tBR_JTr) { - // We've added another 2-byte instruction before this tablejump, which - // means we will always need padding if we didn't before, and vice versa. - - // The original offset of the jump instruction was: - unsigned OrigOffset = BBOffsets[OrigBBI] + BBSizes[OrigBBI] - delta; - if (OrigOffset%4 == 0) { - // We had padding before and now we don't. No net change in code size. - delta = 0; - } else { - // We didn't have padding before and now we do. - BBSizes[NewBBI] += 2; - delta = 4; - } - } - // All BBOffsets following these blocks must be modified. if (delta) AdjustBBOffsetsAfter(NewBB, delta); From evan.cheng at apple.com Tue Dec 6 16:12:01 2011 From: evan.cheng at apple.com (Evan Cheng) Date: Tue, 06 Dec 2011 22:12:01 -0000 Subject: [llvm-commits] [llvm] r145975 - in /llvm/trunk: include/llvm/CodeGen/ include/llvm/MC/ include/llvm/Target/ lib/CodeGen/ lib/CodeGen/SelectionDAG/ lib/Target/ARM/ lib/Target/Mips/ lib/Target/PTX/ utils/TableGen/ Message-ID: <20111206221201.B71981BE003@llvm.org> Author: evancheng Date: Tue Dec 6 16:12:01 2011 New Revision: 145975 URL: http://llvm.org/viewvc/llvm-project?rev=145975&view=rev Log: First chunk of MachineInstr bundle support. 1. Added opcode BUNDLE 2. Taught MachineInstr class to deal with bundled MIs 3. Changed MachineBasicBlock iterator to skip over bundled MIs; added an iterator to walk all the MIs 4. Taught MachineBasicBlock methods about bundled MIs Modified: llvm/trunk/include/llvm/CodeGen/MachineBasicBlock.h llvm/trunk/include/llvm/CodeGen/MachineInstr.h llvm/trunk/include/llvm/MC/MCInstrDesc.h llvm/trunk/include/llvm/Target/Target.td llvm/trunk/include/llvm/Target/TargetOpcodes.h llvm/trunk/lib/CodeGen/LiveVariables.cpp llvm/trunk/lib/CodeGen/MachineBasicBlock.cpp llvm/trunk/lib/CodeGen/MachineInstr.cpp llvm/trunk/lib/CodeGen/MachineLICM.cpp llvm/trunk/lib/CodeGen/PHIElimination.cpp llvm/trunk/lib/CodeGen/RegisterCoalescer.cpp llvm/trunk/lib/CodeGen/ScheduleDAGInstrs.cpp llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp llvm/trunk/lib/CodeGen/TailDuplication.cpp llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp llvm/trunk/lib/Target/Mips/MipsCodeEmitter.cpp llvm/trunk/lib/Target/PTX/PTXInstrInfo.cpp llvm/trunk/utils/TableGen/CodeGenTarget.cpp Modified: llvm/trunk/include/llvm/CodeGen/MachineBasicBlock.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/MachineBasicBlock.h?rev=145975&r1=145974&r2=145975&view=diff ============================================================================== --- llvm/trunk/include/llvm/CodeGen/MachineBasicBlock.h (original) +++ llvm/trunk/include/llvm/CodeGen/MachineBasicBlock.h Tue Dec 6 16:12:01 2011 @@ -129,10 +129,89 @@ const MachineFunction *getParent() const { return xParent; } MachineFunction *getParent() { return xParent; } - typedef Instructions::iterator iterator; - typedef Instructions::const_iterator const_iterator; - typedef std::reverse_iterator const_reverse_iterator; - typedef std::reverse_iterator reverse_iterator; + + /// bundle_iterator - MachineBasicBlock iterator that automatically skips over + /// MIs that are inside bundles (i.e. walk top level MIs only). + template + class bundle_iterator + : public std::iterator { + IterTy MII; + + public: + bundle_iterator(IterTy mii) : MII(mii) { + assert(!MII->isInsideBundle() && + "It's not legal to initialize bundle_iterator with a bundled MI"); + } + + bundle_iterator(Ty &mi) : MII(mi) { + assert(!mi.isInsideBundle() && + "It's not legal to initialize bundle_iterator with a bundled MI"); + } + bundle_iterator(Ty *mi) : MII(mi) { + assert((!mi || !mi->isInsideBundle()) && + "It's not legal to initialize bundle_iterator with a bundled MI"); + } + bundle_iterator(const bundle_iterator &I) : MII(I.MII) {} + bundle_iterator() : MII(0) {} + + Ty &operator*() const { return *MII; } + Ty *operator->() const { return &operator*(); } + + operator Ty*() const { return MII; } + + bool operator==(const bundle_iterator &x) const { + return MII == x.MII; + } + bool operator!=(const bundle_iterator &x) const { + return !operator==(x); + } + + // Increment and decrement operators... + bundle_iterator &operator--() { // predecrement - Back up + do { + --MII; + } while (MII->isInsideBundle()); + return *this; + } + bundle_iterator &operator++() { // preincrement - Advance + do { + ++MII; + } while (MII->isInsideBundle()); + return *this; + } + bundle_iterator operator--(int) { // postdecrement operators... + bundle_iterator tmp = *this; + do { + --MII; + } while (MII->isInsideBundle()); + return tmp; + } + bundle_iterator operator++(int) { // postincrement operators... + bundle_iterator tmp = *this; + do { + ++MII; + } while (MII->isInsideBundle()); + return tmp; + } + + IterTy getInsnIterator() const { + return MII; + } + }; + + typedef Instructions::iterator insn_iterator; + typedef Instructions::const_iterator const_insn_iterator; + typedef std::reverse_iterator reverse_insn_iterator; + typedef + std::reverse_iterator const_reverse_insn_iterator; + + typedef + bundle_iterator iterator; + typedef + bundle_iterator const_iterator; + typedef std::reverse_iterator const_reverse_iterator; + typedef std::reverse_iterator reverse_iterator; + unsigned size() const { return (unsigned)Insts.size(); } bool empty() const { return Insts.empty(); } @@ -142,15 +221,53 @@ const MachineInstr& front() const { return Insts.front(); } const MachineInstr& back() const { return Insts.back(); } + insn_iterator insn_begin() { return Insts.begin(); } + const_insn_iterator insn_begin() const { return Insts.begin(); } + insn_iterator insn_end() { return Insts.end(); } + const_insn_iterator insn_end() const { return Insts.end(); } + reverse_insn_iterator insn_rbegin() { return Insts.rbegin(); } + const_reverse_insn_iterator insn_rbegin() const { return Insts.rbegin(); } + reverse_insn_iterator insn_rend () { return Insts.rend(); } + const_reverse_insn_iterator insn_rend () const { return Insts.rend(); } + iterator begin() { return Insts.begin(); } const_iterator begin() const { return Insts.begin(); } - iterator end() { return Insts.end(); } - const_iterator end() const { return Insts.end(); } - reverse_iterator rbegin() { return Insts.rbegin(); } - const_reverse_iterator rbegin() const { return Insts.rbegin(); } + iterator end() { + insn_iterator II = insn_end(); + if (II != insn_begin()) { + while (II->isInsideBundle()) + --II; + } + return II; + } + const_iterator end() const { + const_insn_iterator II = insn_end(); + if (II != insn_begin()) { + while (II->isInsideBundle()) + --II; + } + return II; + } + reverse_iterator rbegin() { + reverse_insn_iterator II = insn_rbegin(); + if (II != insn_rend()) { + while (II->isInsideBundle()) + ++II; + } + return II; + } + const_reverse_iterator rbegin() const { + const_reverse_insn_iterator II = insn_rbegin(); + if (II != insn_rend()) { + while (II->isInsideBundle()) + ++II; + } + return II; + } reverse_iterator rend () { return Insts.rend(); } const_reverse_iterator rend () const { return Insts.rend(); } + // Machine-CFG iterators typedef std::vector::iterator pred_iterator; typedef std::vector::const_iterator const_pred_iterator; @@ -323,18 +440,16 @@ /// instruction of this basic block. If a terminator does not exist, /// it returns end() iterator getFirstTerminator(); + const_iterator getFirstTerminator() const; - const_iterator getFirstTerminator() const { - return const_cast(this)->getFirstTerminator(); - } + /// getFirstInsnTerminator - Same getFirstTerminator but it ignores bundles + /// and return an insn_iterator instead. + insn_iterator getFirstInsnTerminator(); /// getLastNonDebugInstr - returns an iterator to the last non-debug /// instruction in the basic block, or end() iterator getLastNonDebugInstr(); - - const_iterator getLastNonDebugInstr() const { - return const_cast(this)->getLastNonDebugInstr(); - } + const_iterator getLastNonDebugInstr() const; /// SplitCriticalEdge - Split the critical edge from this block to the /// given successor block, and return the newly created block, or null @@ -347,32 +462,70 @@ void pop_front() { Insts.pop_front(); } void pop_back() { Insts.pop_back(); } void push_back(MachineInstr *MI) { Insts.push_back(MI); } + template - void insert(iterator I, IT S, IT E) { Insts.insert(I, S, E); } - iterator insert(iterator I, MachineInstr *M) { return Insts.insert(I, M); } - iterator insertAfter(iterator I, MachineInstr *M) { + void insert(insn_iterator I, IT S, IT E) { + Insts.insert(I, S, E); + } + insn_iterator insert(insn_iterator I, MachineInstr *M) { + return Insts.insert(I, M); + } + insn_iterator insertAfter(insn_iterator I, MachineInstr *M) { return Insts.insertAfter(I, M); } + template + void insert(iterator I, IT S, IT E) { + Insts.insert(I.getInsnIterator(), S, E); + } + iterator insert(iterator I, MachineInstr *M) { + return Insts.insert(I.getInsnIterator(), M); + } + iterator insertAfter(iterator I, MachineInstr *M) { + return Insts.insertAfter(I.getInsnIterator(), M); + } + // erase - Remove the specified element or range from the instruction list. // These functions delete any instructions removed. // - iterator erase(iterator I) { return Insts.erase(I); } - iterator erase(iterator I, iterator E) { return Insts.erase(I, E); } + insn_iterator erase(insn_iterator I) { + return Insts.erase(I); + } + insn_iterator erase(insn_iterator I, insn_iterator E) { + return Insts.erase(I, E); + } + + iterator erase(iterator I) { + return Insts.erase(I.getInsnIterator()); + } + iterator erase(iterator I, iterator E) { + return Insts.erase(I.getInsnIterator(), E.getInsnIterator()); + } + + iterator erase(MachineInstr *I) { iterator MII(I); return erase(MII); } MachineInstr *remove(MachineInstr *I) { return Insts.remove(I); } void clear() { Insts.clear(); } /// splice - Take an instruction from MBB 'Other' at the position From, /// and insert it into this MBB right before 'where'. - void splice(iterator where, MachineBasicBlock *Other, iterator From) { + void splice(insn_iterator where, MachineBasicBlock *Other, + insn_iterator From) { Insts.splice(where, Other->Insts, From); } + void splice(iterator where, MachineBasicBlock *Other, iterator From) { + Insts.splice(where.getInsnIterator(), Other->Insts, From.getInsnIterator()); + } /// splice - Take a block of instructions from MBB 'Other' in the range [From, /// To), and insert them into this MBB right before 'where'. + void splice(insn_iterator where, MachineBasicBlock *Other, insn_iterator From, + insn_iterator To) { + Insts.splice(where, Other->Insts, From, To); + } void splice(iterator where, MachineBasicBlock *Other, iterator From, iterator To) { - Insts.splice(where, Other->Insts, From, To); + Insts.splice(where.getInsnIterator(), Other->Insts, + From.getInsnIterator(), To.getInsnIterator()); } /// removeFromParent - This method unlinks 'this' from the containing @@ -399,7 +552,10 @@ /// findDebugLoc - find the next valid DebugLoc starting at MBBI, skipping /// any DBG_VALUE instructions. Return UnknownLoc if there is none. - DebugLoc findDebugLoc(MachineBasicBlock::iterator &MBBI); + DebugLoc findDebugLoc(insn_iterator MBBI); + DebugLoc findDebugLoc(iterator MBBI) { + return findDebugLoc(MBBI.getInsnIterator()); + } // Debugging methods. void dump() const; Modified: llvm/trunk/include/llvm/CodeGen/MachineInstr.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/MachineInstr.h?rev=145975&r1=145974&r2=145975&view=diff ============================================================================== --- llvm/trunk/include/llvm/CodeGen/MachineInstr.h (original) +++ llvm/trunk/include/llvm/CodeGen/MachineInstr.h Tue Dec 6 16:12:01 2011 @@ -53,9 +53,11 @@ }; enum MIFlag { - NoFlags = 0, - FrameSetup = 1 << 0 // Instruction is used as a part of + NoFlags = 0, + FrameSetup = 1 << 0, // Instruction is used as a part of // function frame setup code. + InsideBundle = 1 << 1 // Instruction is inside a bundle (not + // the first MI in a bundle) }; private: const MCInstrDesc *MCID; // Instruction descriptor. @@ -148,6 +150,12 @@ AsmPrinterFlags |= (uint8_t)Flag; } + /// clearAsmPrinterFlag - clear specific AsmPrinter flags + /// + void clearAsmPrinterFlag(CommentFlag Flag) { + AsmPrinterFlags &= ~Flag; + } + /// getFlags - Return the MI flags bitvector. uint8_t getFlags() const { return Flags; @@ -167,10 +175,44 @@ Flags = flags; } - /// clearAsmPrinterFlag - clear specific AsmPrinter flags + /// isInsideBundle - Return true if MI is in a bundle (but not the first MI + /// in a bundle). /// - void clearAsmPrinterFlag(CommentFlag Flag) { - AsmPrinterFlags &= ~Flag; + /// A bundle looks like this before it's finalized: + /// ---------------- + /// | MI | + /// ---------------- + /// | + /// ---------------- + /// | MI * | + /// ---------------- + /// | + /// ---------------- + /// | MI * | + /// ---------------- + /// In this case, the first MI starts a bundle but is not inside a bundle, the + /// next 2 MIs are considered "inside" the bundle. + /// + /// After a bundle is finalized, it looks like this: + /// ---------------- + /// | Bundle | + /// ---------------- + /// | + /// ---------------- + /// | MI * | + /// ---------------- + /// | + /// ---------------- + /// | MI * | + /// ---------------- + /// | + /// ---------------- + /// | MI * | + /// ---------------- + /// The first instruction has the special opcode "BUNDLE". It's not "inside" + /// a bundle, but the next three MIs are. + bool isInsideBundle() const { + return getFlag(InsideBundle); } /// getDebugLoc - Returns the debug location id of this MachineInstr. @@ -232,6 +274,14 @@ return MemRefsEnd - MemRefs == 1; } + /// API for querying MachineInstr properties. These are bundle aware. + /// + bool hasProperty(unsigned short Flag) const; + + bool isTerminator() const { + return hasProperty(MCID::Terminator); + } + enum MICheckType { CheckDefs, // Check all operands for equality CheckKillDead, // Check all operands including kill / dead markers Modified: llvm/trunk/include/llvm/MC/MCInstrDesc.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/MC/MCInstrDesc.h?rev=145975&r1=145974&r2=145975&view=diff ============================================================================== --- llvm/trunk/include/llvm/MC/MCInstrDesc.h (original) +++ llvm/trunk/include/llvm/MC/MCInstrDesc.h Tue Dec 6 16:12:01 2011 @@ -184,6 +184,10 @@ return NumDefs; } + /// getFlags - Return flags of this instruction. + /// + unsigned short getFlags() const { return Flags; } + /// isVariadic - Return true if this instruction can have a variable number of /// operands. In this case, the variable operands will be after the normal /// operands but before the implicit definitions and uses (if any are Modified: llvm/trunk/include/llvm/Target/Target.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/Target.td?rev=145975&r1=145974&r2=145975&view=diff ============================================================================== --- llvm/trunk/include/llvm/Target/Target.td (original) +++ llvm/trunk/include/llvm/Target/Target.td Tue Dec 6 16:12:01 2011 @@ -688,6 +688,11 @@ let neverHasSideEffects = 1; let isAsCheapAsAMove = 1; } +def BUNDLE : Instruction { + let OutOperandList = (outs); + let InOperandList = (ins variable_ops); + let AsmString = "BUNDLE"; +} } //===----------------------------------------------------------------------===// Modified: llvm/trunk/include/llvm/Target/TargetOpcodes.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetOpcodes.h?rev=145975&r1=145974&r2=145975&view=diff ============================================================================== --- llvm/trunk/include/llvm/Target/TargetOpcodes.h (original) +++ llvm/trunk/include/llvm/Target/TargetOpcodes.h Tue Dec 6 16:12:01 2011 @@ -82,7 +82,12 @@ /// COPY - Target-independent register copy. This instruction can also be /// used to copy between subregisters of virtual registers. - COPY = 13 + COPY = 13, + + /// BUNDLE - This instruction represents an instruction bundle. Instructions + /// which immediately follow a BUNDLE instruction which are marked with + /// 'InsideBundle' flag are inside the bundle. + BUNDLE }; } // end namespace TargetOpcode } // end namespace llvm Modified: llvm/trunk/lib/CodeGen/LiveVariables.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/LiveVariables.cpp?rev=145975&r1=145974&r2=145975&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/LiveVariables.cpp (original) +++ llvm/trunk/lib/CodeGen/LiveVariables.cpp Tue Dec 6 16:12:01 2011 @@ -754,7 +754,7 @@ const unsigned NumNew = BB->getNumber(); // All registers used by PHI nodes in SuccBB must be live through BB. - for (MachineBasicBlock::const_iterator BBI = SuccBB->begin(), + for (MachineBasicBlock::iterator BBI = SuccBB->begin(), BBE = SuccBB->end(); BBI != BBE && BBI->isPHI(); ++BBI) for (unsigned i = 1, e = BBI->getNumOperands(); i != e; i += 2) if (BBI->getOperand(i+1).getMBB() == BB) Modified: llvm/trunk/lib/CodeGen/MachineBasicBlock.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineBasicBlock.cpp?rev=145975&r1=145974&r2=145975&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/MachineBasicBlock.cpp (original) +++ llvm/trunk/lib/CodeGen/MachineBasicBlock.cpp Tue Dec 6 16:12:01 2011 @@ -73,7 +73,8 @@ // Make sure the instructions have their operands in the reginfo lists. MachineRegisterInfo &RegInfo = MF.getRegInfo(); - for (MachineBasicBlock::iterator I = N->begin(), E = N->end(); I != E; ++I) + for (MachineBasicBlock::insn_iterator I = N->insn_begin(), E = N->insn_end(); + I != E; ++I) I->AddRegOperandsToUseLists(RegInfo); LeakDetector::removeGarbageObject(N); @@ -120,8 +121,8 @@ /// lists. void ilist_traits:: transferNodesFromList(ilist_traits &fromList, - MachineBasicBlock::iterator first, - MachineBasicBlock::iterator last) { + ilist_iterator first, + ilist_iterator last) { assert(Parent->getParent() == fromList.Parent->getParent() && "MachineInstr parent mismatch!"); @@ -140,9 +141,10 @@ } MachineBasicBlock::iterator MachineBasicBlock::getFirstNonPHI() { - iterator I = begin(); + insn_iterator I = insn_begin(); while (I != end() && I->isPHI()) ++I; + assert(!I->isInsideBundle() && "First non-phi MI cannot be inside a bundle!"); return I; } @@ -150,23 +152,63 @@ MachineBasicBlock::SkipPHIsAndLabels(MachineBasicBlock::iterator I) { while (I != end() && (I->isPHI() || I->isLabel() || I->isDebugValue())) ++I; + // FIXME: This needs to change if we wish to bundle labels / dbg_values + // inside the bundle. + assert(!I->isInsideBundle() && + "First non-phi / non-label instruction is inside a bundle!"); return I; } MachineBasicBlock::iterator MachineBasicBlock::getFirstTerminator() { iterator I = end(); - while (I != begin() && ((--I)->getDesc().isTerminator() || I->isDebugValue())) + while (I != begin() && ((--I)->isTerminator() || I->isDebugValue())) ; /*noop */ - while (I != end() && !I->getDesc().isTerminator()) + while (I != end() && !I->isTerminator()) + ++I; + return I; +} + +MachineBasicBlock::const_iterator +MachineBasicBlock::getFirstTerminator() const { + const_iterator I = end(); + while (I != begin() && ((--I)->isTerminator() || I->isDebugValue())) + ; /*noop */ + while (I != end() && !I->isTerminator()) + ++I; + return I; +} + +MachineBasicBlock::insn_iterator MachineBasicBlock::getFirstInsnTerminator() { + insn_iterator I = insn_end(); + while (I != insn_begin() && ((--I)->isTerminator() || I->isDebugValue())) + ; /*noop */ + while (I != insn_end() && !I->isTerminator()) ++I; return I; } MachineBasicBlock::iterator MachineBasicBlock::getLastNonDebugInstr() { - iterator B = begin(), I = end(); + // Skip over end-of-block dbg_value instructions. + insn_iterator B = insn_begin(), I = insn_end(); while (I != B) { --I; - if (I->isDebugValue()) + // Return instruction that starts a bundle. + if (I->isDebugValue() || I->isInsideBundle()) + continue; + return I; + } + // The block is all debug values. + return end(); +} + +MachineBasicBlock::const_iterator +MachineBasicBlock::getLastNonDebugInstr() const { + // Skip over end-of-block dbg_value instructions. + const_insn_iterator B = insn_begin(), I = insn_end(); + while (I != B) { + --I; + // Return instruction that starts a bundle. + if (I->isDebugValue() || I->isInsideBundle()) continue; return I; } @@ -453,8 +495,8 @@ fromMBB->removeSuccessor(Succ); // Fix up any PHI nodes in the successor. - for (MachineBasicBlock::iterator MI = Succ->begin(), ME = Succ->end(); - MI != ME && MI->isPHI(); ++MI) + for (MachineBasicBlock::insn_iterator MI = Succ->insn_begin(), + ME = Succ->insn_end(); MI != ME && MI->isPHI(); ++MI) for (unsigned i = 2, e = MI->getNumOperands()+1; i != e; i += 2) { MachineOperand &MO = MI->getOperand(i); if (MO.getMBB() == fromMBB) @@ -556,7 +598,8 @@ // Collect a list of virtual registers killed by the terminators. SmallVector KilledRegs; if (LV) - for (iterator I = getFirstTerminator(), E = end(); I != E; ++I) { + for (insn_iterator I = getFirstInsnTerminator(), E = insn_end(); + I != E; ++I) { MachineInstr *MI = I; for (MachineInstr::mop_iterator OI = MI->operands_begin(), OE = MI->operands_end(); OI != OE; ++OI) { @@ -583,8 +626,8 @@ } // Fix PHI nodes in Succ so they refer to NMBB instead of this - for (MachineBasicBlock::iterator i = Succ->begin(), e = Succ->end(); - i != e && i->isPHI(); ++i) + for (MachineBasicBlock::insn_iterator + i = Succ->insn_begin(),e = Succ->insn_end(); i != e && i->isPHI(); ++i) for (unsigned ni = 1, ne = i->getNumOperands(); ni != ne; ni += 2) if (i->getOperand(ni+1).getMBB() == this) i->getOperand(ni+1).setMBB(NMBB); @@ -599,7 +642,7 @@ // Restore kills of virtual registers that were killed by the terminators. while (!KilledRegs.empty()) { unsigned Reg = KilledRegs.pop_back_val(); - for (iterator I = end(), E = begin(); I != E;) { + for (insn_iterator I = insn_end(), E = insn_begin(); I != E;) { if (!(--I)->addRegisterKilled(Reg, NULL, /* addIfNotFound= */ false)) continue; LV->getVarInfo(Reg).Kills.push_back(I); @@ -691,8 +734,8 @@ MachineBasicBlock *New) { assert(Old != New && "Cannot replace self with self!"); - MachineBasicBlock::iterator I = end(); - while (I != begin()) { + MachineBasicBlock::insn_iterator I = insn_end(); + while (I != insn_begin()) { --I; if (!I->getDesc().isTerminator()) break; @@ -773,17 +816,17 @@ /// findDebugLoc - find the next valid DebugLoc starting at MBBI, skipping /// any DBG_VALUE instructions. Return UnknownLoc if there is none. DebugLoc -MachineBasicBlock::findDebugLoc(MachineBasicBlock::iterator &MBBI) { +MachineBasicBlock::findDebugLoc(insn_iterator MBBI) { DebugLoc DL; - MachineBasicBlock::iterator E = end(); - if (MBBI != E) { - // Skip debug declarations, we don't want a DebugLoc from them. - MachineBasicBlock::iterator MBBI2 = MBBI; - while (MBBI2 != E && MBBI2->isDebugValue()) - MBBI2++; - if (MBBI2 != E) - DL = MBBI2->getDebugLoc(); - } + insn_iterator E = insn_end(); + if (MBBI == E) + return DL; + + // Skip debug declarations, we don't want a DebugLoc from them. + while (MBBI != E && MBBI->isDebugValue()) + MBBI++; + if (MBBI != E) + DL = MBBI->getDebugLoc(); return DL; } Modified: llvm/trunk/lib/CodeGen/MachineInstr.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineInstr.cpp?rev=145975&r1=145974&r2=145975&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/MachineInstr.cpp (original) +++ llvm/trunk/lib/CodeGen/MachineInstr.cpp Tue Dec 6 16:12:01 2011 @@ -735,6 +735,20 @@ MemRefsEnd = NewMemRefsEnd; } +bool MachineInstr::hasProperty(unsigned short MCFlag) const { + if (getOpcode() != TargetOpcode::BUNDLE) + return getDesc().getFlags() & (1 << MCFlag); + + const MachineBasicBlock *MBB = getParent(); + MachineBasicBlock::const_insn_iterator MII = *this; ++MII; + while (MII != MBB->end() && MII->isInsideBundle()) { + if (MII->getDesc().getFlags() & (1 << MCFlag)) + return true; + ++MII; + } + return false; +} + bool MachineInstr::isIdenticalTo(const MachineInstr *Other, MICheckType Check) const { // If opcodes or number of operands are not the same then the two @@ -789,6 +803,17 @@ /// block, and returns it, but does not delete it. MachineInstr *MachineInstr::removeFromParent() { assert(getParent() && "Not embedded in a basic block!"); + + // If it's a bundle then remove the MIs inside the bundle as well. + if (getOpcode() == TargetOpcode::BUNDLE) { + MachineBasicBlock *MBB = getParent(); + MachineBasicBlock::insn_iterator MII = *this; ++MII; + while (MII != MBB->end() && MII->isInsideBundle()) { + MachineInstr *MI = &*MII; + ++MII; + MBB->remove(MI); + } + } getParent()->remove(this); return this; } @@ -798,6 +823,16 @@ /// block, and deletes it. void MachineInstr::eraseFromParent() { assert(getParent() && "Not embedded in a basic block!"); + // If it's a bundle then remove the MIs inside the bundle as well. + if (getOpcode() == TargetOpcode::BUNDLE) { + MachineBasicBlock *MBB = getParent(); + MachineBasicBlock::insn_iterator MII = *this; ++MII; + while (MII != MBB->end() && MII->isInsideBundle()) { + MachineInstr *MI = &*MII; + ++MII; + MBB->erase(MI); + } + } getParent()->erase(this); } Modified: llvm/trunk/lib/CodeGen/MachineLICM.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineLICM.cpp?rev=145975&r1=145974&r2=145975&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/MachineLICM.cpp (original) +++ llvm/trunk/lib/CodeGen/MachineLICM.cpp Tue Dec 6 16:12:01 2011 @@ -1141,8 +1141,9 @@ assert(NewMIs.size() == 2 && "Unfolded a load into multiple instructions!"); MachineBasicBlock *MBB = MI->getParent(); - MBB->insert(MI, NewMIs[0]); - MBB->insert(MI, NewMIs[1]); + MachineBasicBlock::iterator Pos = MI; + MBB->insert(Pos, NewMIs[0]); + MBB->insert(Pos, NewMIs[1]); // If unfolding produced a load that wasn't loop-invariant or profitable to // hoist, discard the new instructions and bail. if (!IsLoopInvariantInst(*NewMIs[0]) || !IsProfitableToHoist(*NewMIs[0])) { Modified: llvm/trunk/lib/CodeGen/PHIElimination.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/PHIElimination.cpp?rev=145975&r1=145974&r2=145975&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/PHIElimination.cpp (original) +++ llvm/trunk/lib/CodeGen/PHIElimination.cpp Tue Dec 6 16:12:01 2011 @@ -410,7 +410,7 @@ return false; // Quick exit for basic blocks without PHIs. bool Changed = false; - for (MachineBasicBlock::const_iterator BBI = MBB.begin(), BBE = MBB.end(); + for (MachineBasicBlock::iterator BBI = MBB.begin(), BBE = MBB.end(); BBI != BBE && BBI->isPHI(); ++BBI) { for (unsigned i = 1, e = BBI->getNumOperands(); i != e; i += 2) { unsigned Reg = BBI->getOperand(i).getReg(); Modified: llvm/trunk/lib/CodeGen/RegisterCoalescer.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/RegisterCoalescer.cpp?rev=145975&r1=145974&r2=145975&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/RegisterCoalescer.cpp (original) +++ llvm/trunk/lib/CodeGen/RegisterCoalescer.cpp Tue Dec 6 16:12:01 2011 @@ -710,7 +710,8 @@ return false; if (NewMI != DefMI) { LIS->ReplaceMachineInstrInMaps(DefMI, NewMI); - MBB->insert(DefMI, NewMI); + MachineBasicBlock::iterator Pos = DefMI; + MBB->insert(Pos, NewMI); MBB->erase(DefMI); } unsigned OpIdx = NewMI->findRegisterUseOperandIdx(IntA.reg, false); Modified: llvm/trunk/lib/CodeGen/ScheduleDAGInstrs.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/ScheduleDAGInstrs.cpp?rev=145975&r1=145974&r2=145975&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/ScheduleDAGInstrs.cpp (original) +++ llvm/trunk/lib/CodeGen/ScheduleDAGInstrs.cpp Tue Dec 6 16:12:01 2011 @@ -689,7 +689,7 @@ DI = DbgValues.end(), DE = DbgValues.begin(); DI != DE; --DI) { std::pair P = *prior(DI); MachineInstr *DbgValue = P.first; - MachineInstr *OrigPrivMI = P.second; + MachineBasicBlock::iterator OrigPrivMI = P.second; BB->insertAfter(OrigPrivMI, DbgValue); } DbgValues.clear(); Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp?rev=145975&r1=145974&r2=145975&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Tue Dec 6 16:12:01 2011 @@ -346,7 +346,8 @@ TII.get(TargetOpcode::DBG_VALUE)) .addReg(CopyUseMI->getOperand(0).getReg(), RegState::Debug) .addImm(Offset).addMetadata(Variable); - EntryMBB->insertAfter(CopyUseMI, NewMI); + MachineBasicBlock::iterator Pos = CopyUseMI; + EntryMBB->insertAfter(Pos, NewMI); } } } Modified: llvm/trunk/lib/CodeGen/TailDuplication.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/TailDuplication.cpp?rev=145975&r1=145974&r2=145975&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/TailDuplication.cpp (original) +++ llvm/trunk/lib/CodeGen/TailDuplication.cpp Tue Dec 6 16:12:01 2011 @@ -561,8 +561,7 @@ // Check the instructions in the block to determine whether tail-duplication // is invalid or unlikely to be profitable. unsigned InstrCount = 0; - for (MachineBasicBlock::const_iterator I = TailBB.begin(); I != TailBB.end(); - ++I) { + for (MachineBasicBlock::iterator I = TailBB.begin(); I != TailBB.end(); ++I) { // Non-duplicable things shouldn't be tail-duplicated. if (I->getDesc().isNotDuplicable()) return false; Modified: llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp?rev=145975&r1=145974&r2=145975&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp Tue Dec 6 16:12:01 2011 @@ -1762,8 +1762,7 @@ // Check that CPSR isn't set between the comparison instruction and the one we // want to change. - MachineBasicBlock::const_iterator I = CmpInstr, E = MI, - B = MI->getParent()->begin(); + MachineBasicBlock::iterator I = CmpInstr,E = MI, B = MI->getParent()->begin(); // Early exit if CmpInstr is at the beginning of the BB. if (I == B) return false; Modified: llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp?rev=145975&r1=145974&r2=145975&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp Tue Dec 6 16:12:01 2011 @@ -386,7 +386,7 @@ for (MachineFunction::iterator MBB = MF.begin(), E = MF.end(); MBB != E; ++MBB) { MCE.StartMachineBasicBlock(MBB); - for (MachineBasicBlock::const_iterator I = MBB->begin(), E = MBB->end(); + for (MachineBasicBlock::iterator I = MBB->begin(), E = MBB->end(); I != E; ++I) emitInstruction(*I); } Modified: llvm/trunk/lib/Target/Mips/MipsCodeEmitter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsCodeEmitter.cpp?rev=145975&r1=145974&r2=145975&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/MipsCodeEmitter.cpp (original) +++ llvm/trunk/lib/Target/Mips/MipsCodeEmitter.cpp Tue Dec 6 16:12:01 2011 @@ -144,7 +144,7 @@ for (MachineFunction::iterator MBB = MF.begin(), E = MF.end(); MBB != E; ++MBB){ MCE.StartMachineBasicBlock(MBB); - for (MachineBasicBlock::const_iterator I = MBB->begin(), E = MBB->end(); + for (MachineBasicBlock::iterator I = MBB->begin(), E = MBB->end(); I != E; ++I) emitInstruction(*I); } Modified: llvm/trunk/lib/Target/PTX/PTXInstrInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PTX/PTXInstrInfo.cpp?rev=145975&r1=145974&r2=145975&view=diff ============================================================================== --- llvm/trunk/lib/Target/PTX/PTXInstrInfo.cpp (original) +++ llvm/trunk/lib/Target/PTX/PTXInstrInfo.cpp Tue Dec 6 16:12:01 2011 @@ -184,7 +184,7 @@ if (MBB.empty()) return true; - MachineBasicBlock::const_iterator iter = MBB.end(); + MachineBasicBlock::iterator iter = MBB.end(); const MachineInstr& instLast1 = *--iter; const MCInstrDesc &desc1 = instLast1.getDesc(); // for special case that MBB has only 1 instruction Modified: llvm/trunk/utils/TableGen/CodeGenTarget.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/CodeGenTarget.cpp?rev=145975&r1=145974&r2=145975&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/CodeGenTarget.cpp (original) +++ llvm/trunk/utils/TableGen/CodeGenTarget.cpp Tue Dec 6 16:12:01 2011 @@ -267,6 +267,7 @@ "DBG_VALUE", "REG_SEQUENCE", "COPY", + "BUNDLE", 0 }; const DenseMap &Insts = getInstructions(); From mcrosier at apple.com Tue Dec 6 12:53:36 2011 From: mcrosier at apple.com (Chad Rosier) Date: Tue, 06 Dec 2011 10:53:36 -0800 Subject: [llvm-commits] [llvm] r145912 - in /llvm/trunk/lib/Target/Mips: MipsInstrFormats.td MipsInstrInfo.cpp MipsInstrInfo.td In-Reply-To: <3DCFBAAD-5552-41AF-BD8A-66E6524B56E8@apple.com> References: <20111206033449.22EBB2A6C12C@llvm.org> <86AC779C188FE74F88F6494478B46332E8B3F0@exchdb03.mips.com> <3DCFBAAD-5552-41AF-BD8A-66E6524B56E8@apple.com> Message-ID: On Dec 6, 2011, at 10:46 AM, Chad Rosier wrote: > > On Dec 6, 2011, at 10:40 AM, Carter, Jack wrote: > >> The commit was after I left for home and I just got in again. > > No problem. > >> I am checking here for the correct form for a test case and will send it in. > > Sounds good. See http://llvm.org/docs/TestingGuide.html#rtcustom for more info on writing regression tests. You could also grep through lib/test/* for examples. And by lib/test/* I really meant llvm/test/* :) > Chad > >> Jack >> ________________________________________ >> From: Bruno Cardoso Lopes [bruno.cardoso at gmail.com] >> Sent: Tuesday, December 06, 2011 9:59 AM >> To: Chad Rosier; Carter, Jack >> Cc: llvm-commits at cs.uiuc.edu >> Subject: Re: [llvm-commits] [llvm] r145912 - in /llvm/trunk/lib/Target/Mips: MipsInstrFormats.td MipsInstrInfo.cpp MipsInstrInfo.td >> >> Still waiting from Jack Carter! Since it was commited yesterday, he >> may be taking his time to do it. >> >> On Tue, Dec 6, 2011 at 3:39 PM, Chad Rosier wrote: >>> Did the test case ever land? >>> >>> Chad >>> >>> On Dec 5, 2011, at 7:34 PM, Bruno Cardoso Lopes wrote: >>> >>>> Author: bruno >>>> Date: Mon Dec 5 21:34:48 2011 >>>> New Revision: 145912 >>>> >>>> URL: http://llvm.org/viewvc/llvm-project?rev=145912&view=rev >>>> Log: >>>> Use branches instead of jumps + variable cleanup. Testcase coming next. Patch by Jack Carter >>>> >>>> Modified: >>>> llvm/trunk/lib/Target/Mips/MipsInstrFormats.td >>>> llvm/trunk/lib/Target/Mips/MipsInstrInfo.cpp >>>> llvm/trunk/lib/Target/Mips/MipsInstrInfo.td >>>> >>>> Modified: llvm/trunk/lib/Target/Mips/MipsInstrFormats.td >>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsInstrFormats.td?rev=145912&r1=145911&r2=145912&view=diff >>>> ============================================================================== >>>> --- llvm/trunk/lib/Target/Mips/MipsInstrFormats.td (original) >>>> +++ llvm/trunk/lib/Target/Mips/MipsInstrFormats.td Mon Dec 5 21:34:48 2011 >>>> @@ -115,7 +115,7 @@ >>>> let Inst{15-0} = imm16; >>>> } >>>> >>>> -class CBranchBase op, dag outs, dag ins, string asmstr, >>>> +class BranchBase op, dag outs, dag ins, string asmstr, >>>> list pattern, InstrItinClass itin>: >>>> MipsInst >>>> { >>>> >>>> Modified: llvm/trunk/lib/Target/Mips/MipsInstrInfo.cpp >>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsInstrInfo.cpp?rev=145912&r1=145911&r2=145912&view=diff >>>> ============================================================================== >>>> --- llvm/trunk/lib/Target/Mips/MipsInstrInfo.cpp (original) >>>> +++ llvm/trunk/lib/Target/Mips/MipsInstrInfo.cpp Mon Dec 5 21:34:48 2011 >>>> @@ -236,7 +236,7 @@ >>>> Opc == Mips::BGEZ || Opc == Mips::BLTZ || Opc == Mips::BLEZ || >>>> Opc == Mips::BEQ64 || Opc == Mips::BNE64 || Opc == Mips::BGTZ64 || >>>> Opc == Mips::BGEZ64 || Opc == Mips::BLTZ64 || Opc == Mips::BLEZ64 || >>>> - Opc == Mips::BC1T || Opc == Mips::BC1F || Opc == Mips::J) ? >>>> + Opc == Mips::BC1T || Opc == Mips::BC1F || Opc == Mips::B) ? >>>> Opc : 0; >>>> } >>>> >>>> @@ -320,7 +320,7 @@ >>>> // If there is only one terminator instruction, process it. >>>> if (!SecondLastOpc) { >>>> // Unconditional branch >>>> - if (LastOpc == Mips::J) { >>>> + if (LastOpc == Mips::B) { >>>> TBB = LastInst->getOperand(0).getMBB(); >>>> return false; >>>> } >>>> @@ -337,7 +337,7 @@ >>>> >>>> // If second to last instruction is an unconditional branch, >>>> // analyze it and remove the last instruction. >>>> - if (SecondLastOpc == Mips::J) { >>>> + if (SecondLastOpc == Mips::B) { >>>> // Return if the last instruction cannot be removed. >>>> if (!AllowModify) >>>> return true; >>>> @@ -349,7 +349,7 @@ >>>> >>>> // Conditional branch followed by an unconditional branch. >>>> // The last one must be unconditional. >>>> - if (LastOpc != Mips::J) >>>> + if (LastOpc != Mips::B) >>>> return true; >>>> >>>> AnalyzeCondBr(SecondLastInst, SecondLastOpc, TBB, Cond); >>>> @@ -391,14 +391,14 @@ >>>> // Two-way Conditional branch. >>>> if (FBB) { >>>> BuildCondBr(MBB, TBB, DL, Cond); >>>> - BuildMI(&MBB, DL, get(Mips::J)).addMBB(FBB); >>>> + BuildMI(&MBB, DL, get(Mips::B)).addMBB(FBB); >>>> return 2; >>>> } >>>> >>>> // One way branch. >>>> // Unconditional branch. >>>> if (Cond.empty()) >>>> - BuildMI(&MBB, DL, get(Mips::J)).addMBB(TBB); >>>> + BuildMI(&MBB, DL, get(Mips::B)).addMBB(TBB); >>>> else // Conditional branch. >>>> BuildCondBr(MBB, TBB, DL, Cond); >>>> return 1; >>>> >>>> Modified: llvm/trunk/lib/Target/Mips/MipsInstrInfo.td >>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsInstrInfo.td?rev=145912&r1=145911&r2=145912&view=diff >>>> ============================================================================== >>>> --- llvm/trunk/lib/Target/Mips/MipsInstrInfo.td (original) >>>> +++ llvm/trunk/lib/Target/Mips/MipsInstrInfo.td Mon Dec 5 21:34:48 2011 >>>> @@ -380,21 +380,13 @@ >>>> let isPseudo = Pseudo; >>>> } >>>> >>>> -// Memory Load/Store >>>> +// Unaligned Memory Load/Store >>>> let canFoldAsLoad = 1 in >>>> -class LoadX op, RegisterClass RC, >>>> - Operand MemOpnd>: >>>> - FMem>>> - "", >>>> - [], IILoad> { >>>> -} >>>> +class LoadUnAlign op, RegisterClass RC, Operand MemOpnd>: >>>> + FMem {} >>>> >>>> -class StoreX op, RegisterClass RC, >>>> - Operand MemOpnd>: >>>> - FMem>>> - "", >>>> - [], IIStore> { >>>> -} >>>> +class StoreUnAlign op, RegisterClass RC, Operand MemOpnd>: >>>> + FMem {} >>>> >>>> // 32-bit load. >>>> multiclass LoadM32 op, string instr_asm, PatFrag OpNode, >>>> @@ -415,10 +407,10 @@ >>>> } >>>> >>>> // 32-bit load. >>>> -multiclass LoadX32 op> { >>>> - def #NAME# : LoadX, >>>> +multiclass LoadUnAlign32 op> { >>>> + def #NAME# : LoadUnAlign, >>>> Requires<[NotN64]>; >>>> - def _P8 : LoadX, >>>> + def _P8 : LoadUnAlign, >>>> Requires<[IsN64]>; >>>> } >>>> // 32-bit store. >>>> @@ -440,18 +432,18 @@ >>>> } >>>> >>>> // 32-bit store. >>>> -multiclass StoreX32 op> { >>>> - def #NAME# : StoreX, >>>> +multiclass StoreUnAlign32 op> { >>>> + def #NAME# : StoreUnAlign, >>>> Requires<[NotN64]>; >>>> - def _P8 : StoreX, >>>> + def _P8 : StoreUnAlign, >>>> Requires<[IsN64]>; >>>> } >>>> >>>> // Conditional Branch >>>> class CBranch op, string instr_asm, PatFrag cond_op, RegisterClass RC>: >>>> - CBranchBase>>> - !strconcat(instr_asm, "\t$rs, $rt, $imm16"), >>>> - [(brcond (i32 (cond_op RC:$rs, RC:$rt)), bb:$imm16)], IIBranch> { >>>> + BranchBase>>> + !strconcat(instr_asm, "\t$rs, $rt, $imm16"), >>>> + [(brcond (i32 (cond_op RC:$rs, RC:$rt)), bb:$imm16)], IIBranch> { >>>> let isBranch = 1; >>>> let isTerminator = 1; >>>> let hasDelaySlot = 1; >>>> @@ -459,9 +451,9 @@ >>>> >>>> class CBranchZero op, bits<5> _rt, string instr_asm, PatFrag cond_op, >>>> RegisterClass RC>: >>>> - CBranchBase>>> - !strconcat(instr_asm, "\t$rs, $imm16"), >>>> - [(brcond (i32 (cond_op RC:$rs, 0)), bb:$imm16)], IIBranch> { >>>> + BranchBase>>> + !strconcat(instr_asm, "\t$rs, $imm16"), >>>> + [(brcond (i32 (cond_op RC:$rs, 0)), bb:$imm16)], IIBranch> { >>>> let rt = _rt; >>>> let isBranch = 1; >>>> let isTerminator = 1; >>>> @@ -486,10 +478,16 @@ >>>> IIAlu>; >>>> >>>> // Unconditional branch >>>> -let isBranch=1, isTerminator=1, isBarrier=1, hasDelaySlot = 1 in >>>> -class JumpFJ op, string instr_asm>: >>>> - FJ>>> - !strconcat(instr_asm, "\t$target"), [(br bb:$target)], IIBranch>; >>>> +class UncondBranch op, string instr_asm>: >>>> + BranchBase>>> + !strconcat(instr_asm, "\t$imm16"), [(br bb:$imm16)], IIBranch> { >>>> + let rs = 0; >>>> + let rt = 0; >>>> + let isBranch = 1; >>>> + let isTerminator = 1; >>>> + let isBarrier = 1; >>>> + let hasDelaySlot = 1; >>>> +} >>>> >>>> let isBranch=1, isTerminator=1, isBarrier=1, rd=0, hasDelaySlot = 1, >>>> isIndirectBranch = 1 in >>>> @@ -810,10 +808,10 @@ >>>> defm USW : StoreM32<0x2b, "usw", store_u, 1>; >>>> >>>> /// Primitives for unaligned >>>> -defm LWL : LoadX32<0x22>; >>>> -defm LWR : LoadX32<0x26>; >>>> -defm SWL : StoreX32<0x2A>; >>>> -defm SWR : StoreX32<0x2E>; >>>> +defm LWL : LoadUnAlign32<0x22>; >>>> +defm LWR : LoadUnAlign32<0x26>; >>>> +defm SWL : StoreUnAlign32<0x2A>; >>>> +defm SWR : StoreUnAlign32<0x2E>; >>>> >>>> let hasSideEffects = 1 in >>>> def SYNC : MipsInst<(outs), (ins i32imm:$stype), "sync $stype", >>>> @@ -833,10 +831,10 @@ >>>> def SC_P8 : SCBase<0x38, "sc", CPURegs, mem64>, Requires<[IsN64]>; >>>> >>>> /// Jump and Branch Instructions >>>> -def J : JumpFJ<0x02, "j">; >>>> def JR : JumpFR<0x00, 0x08, "jr", CPURegs>; >>>> def JAL : JumpLink<0x03, "jal">; >>>> def JALR : JumpLinkReg<0x00, 0x09, "jalr">; >>>> +def B : UncondBranch<0x04, "b">; >>>> def BEQ : CBranch<0x04, "beq", seteq, CPURegs>; >>>> def BNE : CBranch<0x05, "bne", setne, CPURegs>; >>>> def BGEZ : CBranchZero<0x01, 1, "bgez", setge, CPURegs>; >>>> >>>> >>>> _______________________________________________ >>>> llvm-commits mailing list >>>> llvm-commits at cs.uiuc.edu >>>> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits >>> >> >> >> >> -- >> Bruno Cardoso Lopes >> http://www.brunocardoso.cc > From anton at korobeynikov.info Tue Dec 6 12:00:12 2011 From: anton at korobeynikov.info (Anton Korobeynikov) Date: Tue, 6 Dec 2011 22:00:12 +0400 Subject: [llvm-commits] x86 branch sequence optimization in LLVM code gen: please review In-Reply-To: <021AD592C708E24FA11FD214489EC9BE0123F95DDF@hasmsx501.ger.corp.intel.com> References: <021AD592C708E24FA11FD214489EC9BE0123F25260@hasmsx501.ger.corp.intel.com> <021AD592C708E24FA11FD214489EC9BE0123F95DDF@hasmsx501.ger.corp.intel.com> Message-ID: Hello Victor, > Unfortunately, I cannot put it inside brcond.ll because the ?ptest? instruction was introduced only with SSE4.1 (i.e. requires ?-mcpu=penryn?), while the ?current version of brcond.ll is processed with ?-mcpu=core2?. > Will the replacement of?mcpu in brcond.ll with ?penryn? be backward-compat with regard to LIT results? You can have several RUN lines with different FileCheck prefixes. There are bunch of examples in the current tests. -- With best regards, Anton Korobeynikov Faculty of Mathematics and Mechanics, Saint Petersburg State University From jstaszak at apple.com Tue Dec 6 16:31:27 2011 From: jstaszak at apple.com (Jakub Staszak) Date: Tue, 06 Dec 2011 22:31:27 -0000 Subject: [llvm-commits] [llvm] r145979 - /llvm/trunk/docs/ReleaseNotes.html Message-ID: <20111206223127.6FD7C1BE003@llvm.org> Author: kuba Date: Tue Dec 6 16:31:27 2011 New Revision: 145979 URL: http://llvm.org/viewvc/llvm-project?rev=145979&view=rev Log: Add link to builtin_expect in Release Notes. Modified: llvm/trunk/docs/ReleaseNotes.html Modified: llvm/trunk/docs/ReleaseNotes.html URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/ReleaseNotes.html?rev=145979&r1=145978&r2=145979&view=diff ============================================================================== --- llvm/trunk/docs/ReleaseNotes.html (original) +++ llvm/trunk/docs/ReleaseNotes.html Tue Dec 6 16:31:27 2011 @@ -822,8 +822,9 @@ represents floating point multiply accumulate operations without an intermediate rounding stage.
  • A new llvm.expect intrinsic allows a - frontend to express expected control flow (and the __builtin_expect builtin - from GNU C).
    • + frontend to express expected control flow (and the + + __builtin_expect from GNU C).
  • The llvm.prefetch intrinsic now takes a 4th argument that specifies whether the prefetch happens from the icache or dcache.
    • From isanbard at gmail.com Tue Dec 6 16:14:27 2011 From: isanbard at gmail.com (Bill Wendling) Date: Tue, 06 Dec 2011 22:14:27 -0000 Subject: [llvm-commits] [llvm] r145976 - /llvm/trunk/lib/Target/X86/X86FrameLowering.cpp Message-ID: <20111206221427.92BE71BE003@llvm.org> Author: void Date: Tue Dec 6 16:14:27 2011 New Revision: 145976 URL: http://llvm.org/viewvc/llvm-project?rev=145976&view=rev Log: Explicitly check for the different SUB instructions. Modified: llvm/trunk/lib/Target/X86/X86FrameLowering.cpp Modified: llvm/trunk/lib/Target/X86/X86FrameLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86FrameLowering.cpp?rev=145976&r1=145975&r2=145976&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86FrameLowering.cpp (original) +++ llvm/trunk/lib/Target/X86/X86FrameLowering.cpp Tue Dec 6 16:14:27 2011 @@ -475,9 +475,6 @@ unsigned FramePtr = RegInfo->getFrameRegister(MF); unsigned StackPtr = RegInfo->getStackRegister(); - X86MachineFunctionInfo *X86FI = MF.getInfo(); - int TailCallReturnAddrDelta = X86FI->getTCReturnAddrDelta(); - bool Is64Bit = STI.is64Bit(); bool HasFP = hasFP(MF); @@ -490,7 +487,6 @@ unsigned PushInstrSize = 1; unsigned MoveInstr = (Is64Bit ? X86::MOV64rr : X86::MOV32rr); unsigned MoveInstrSize = (Is64Bit ? 3 : 2); - unsigned SubtractInstr = getSUBriOpcode(Is64Bit, -TailCallReturnAddrDelta); unsigned SubtractInstrIdx = (Is64Bit ? 3 : 2); unsigned StackDivide = (Is64Bit ? 8 : 4); @@ -529,7 +525,8 @@ memset(SavedRegs, 0, sizeof(SavedRegs)); SavedRegIdx = CU_NUM_SAVED_REGS; InstrOffset += MoveInstrSize; - } else if (Opc == SubtractInstr) { + } else if (Opc == X86::SUB64ri32 || Opc == X86::SUB64ri8 || + Opc == X86::SUB32ri || Opc == X86::SUB32ri8) { if (StackSize) // We already have a stack size. return 0; From stoklund at 2pi.dk Tue Dec 6 16:41:31 2011 From: stoklund at 2pi.dk (Jakob Stoklund Olesen) Date: Tue, 06 Dec 2011 22:41:31 -0000 Subject: [llvm-commits] [llvm] r145980 - in /llvm/trunk/lib/Target/ARM: ARMBaseInstrInfo.cpp ARMConstantIslandPass.cpp Message-ID: <20111206224131.5A9081BE003@llvm.org> Author: stoklund Date: Tue Dec 6 16:41:31 2011 New Revision: 145980 URL: http://llvm.org/viewvc/llvm-project?rev=145980&view=rev Log: Revert r145971: "Use conservative size estimate for tBR_JTr." This caused more offset errors. Modified: llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp llvm/trunk/lib/Target/ARM/ARMConstantIslandPass.cpp Modified: llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp?rev=145980&r1=145979&r2=145980&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp Tue Dec 6 16:41:31 2011 @@ -601,12 +601,12 @@ assert(JTI < JT.size()); // Thumb instructions are 2 byte aligned, but JT entries are 4 byte // 4 aligned. The assembler / linker may add 2 byte padding just before - // the JT entries. The size includes the worst case size of this padding. + // the JT entries. The size does not include this padding; the + // constant islands pass does separate bookkeeping for it. // FIXME: If we know the size of the function is less than (1 << 16) *2 // bytes, we can use 16-bit entries instead. Then there won't be an // alignment issue. - // tBR_JT is 2 bytes + 2 bytes worst case padding for table alignment. - unsigned InstSize = (Opc == ARM::t2BR_JT) ? 2 : 4; + unsigned InstSize = (Opc == ARM::tBR_JTr || Opc == ARM::t2BR_JT) ? 2 : 4; unsigned NumEntries = getNumJTEntries(JT, JTI); if (Opc == ARM::t2TBB_JT && (NumEntries & 1)) // Make sure the instruction that follows TBB is 2-byte aligned. Modified: llvm/trunk/lib/Target/ARM/ARMConstantIslandPass.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMConstantIslandPass.cpp?rev=145980&r1=145979&r2=145980&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMConstantIslandPass.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMConstantIslandPass.cpp Tue Dec 6 16:41:31 2011 @@ -525,8 +525,13 @@ // A Thumb1 table jump may involve padding; for the offsets to // be right, functions containing these must be 4-byte aligned. // tBR_JTr expands to a mov pc followed by .align 2 and then the jump - // table entries. GetInstSizeInBytes returns the worst case size. + // table entries. So this code checks whether offset of tBR_JTr + 2 + // is aligned. That is held in Offset+MBBSize, which already has + // 2 added in for the size of the mov pc instruction. MF.EnsureAlignment(2U); + if ((Offset+MBBSize)%4 != 0 || HasInlineAsm) + // FIXME: Add a pseudo ALIGN instruction instead. + MBBSize += 2; // padding continue; // Does not get an entry in ImmBranches case ARM::t2BR_JT: T2JumpTables.push_back(I); @@ -804,6 +809,23 @@ // Set the size of NewBB in BBSizes. It does not include any padding now. BBSizes[NewBBI] = NewBBSize; + MachineInstr* ThumbJTMI = prior(NewBB->end()); + if (ThumbJTMI->getOpcode() == ARM::tBR_JTr) { + // We've added another 2-byte instruction before this tablejump, which + // means we will always need padding if we didn't before, and vice versa. + + // The original offset of the jump instruction was: + unsigned OrigOffset = BBOffsets[OrigBBI] + BBSizes[OrigBBI] - delta; + if (OrigOffset%4 == 0) { + // We had padding before and now we don't. No net change in code size. + delta = 0; + } else { + // We didn't have padding before and now we do. + BBSizes[NewBBI] += 2; + delta = 4; + } + } + // All BBOffsets following these blocks must be modified. if (delta) AdjustBBOffsetsAfter(NewBB, delta); From isanbard at gmail.com Tue Dec 6 13:16:17 2011 From: isanbard at gmail.com (Bill Wendling) Date: Tue, 06 Dec 2011 19:16:17 -0000 Subject: [llvm-commits] [llvm] r145954 - /llvm/trunk/lib/Target/X86/X86FrameLowering.cpp Message-ID: <20111206191617.4AEB71BE003@llvm.org> Author: void Date: Tue Dec 6 13:16:17 2011 New Revision: 145954 URL: http://llvm.org/viewvc/llvm-project?rev=145954&view=rev Log: Check the correct value for small stack sizes. Also modify some comments. Modified: llvm/trunk/lib/Target/X86/X86FrameLowering.cpp Modified: llvm/trunk/lib/Target/X86/X86FrameLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86FrameLowering.cpp?rev=145954&r1=145953&r2=145954&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86FrameLowering.cpp (original) +++ llvm/trunk/lib/Target/X86/X86FrameLowering.cpp Tue Dec 6 13:16:17 2011 @@ -554,17 +554,17 @@ // Get the encoding of the saved registers when we have a frame pointer. uint32_t RegEnc = encodeCompactUnwindRegistersWithFrame(SavedRegs, Is64Bit); - if (RegEnc == ~0U) - return 0; + if (RegEnc == ~0U) return 0; CompactUnwindEncoding |= 0x01000000; CompactUnwindEncoding |= (CFAOffset & 0xFF) << 16; CompactUnwindEncoding |= RegEnc & 0x7FFF; } else { - unsigned FullOffset = CFAOffset + StackAdjust; - if ((FullOffset & 0xFF) == FullOffset) { - // Frameless stack. + if ((CFAOffset & 0xFF) == CFAOffset) { + // Frameless stack with a small stack size. CompactUnwindEncoding |= 0x02000000; + + // Encode the stack size. CompactUnwindEncoding |= (CFAOffset & 0xFF) << 16; } else { if ((CFAOffset & 0x7) != CFAOffset) @@ -582,6 +582,7 @@ CompactUnwindEncoding |= (CFAOffset & 0x7) << 13; } + // Encode the number of registers saved. CompactUnwindEncoding |= ((6 - SavedRegIdx) & 0x7) << 10; // Get the encoding of the saved registers when we don't have a frame @@ -590,6 +591,8 @@ 6 - SavedRegIdx, Is64Bit); if (RegEnc == ~0U) return 0; + + // Encode the register encoding. CompactUnwindEncoding |= RegEnc & 0x3FF; } From grosbach at apple.com Tue Dec 6 16:07:02 2011 From: grosbach at apple.com (Jim Grosbach) Date: Tue, 06 Dec 2011 22:07:02 -0000 Subject: [llvm-commits] [llvm] r145974 - /llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp Message-ID: <20111206220703.0ACD81BE003@llvm.org> Author: grosbach Date: Tue Dec 6 16:07:02 2011 New Revision: 145974 URL: http://llvm.org/viewvc/llvm-project?rev=145974&view=rev Log: Tidy up. Fix naming convention stuff for some internal functions. Modified: llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp Modified: llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp?rev=145974&r1=145973&r2=145974&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp (original) +++ llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp Tue Dec 6 16:07:02 2011 @@ -1665,7 +1665,7 @@ /// EmitValidateOperandClass - Emit the function to validate an operand class. static void EmitValidateOperandClass(AsmMatcherInfo &Info, raw_ostream &OS) { - OS << "static bool ValidateOperandClass(MCParsedAsmOperand *GOp, " + OS << "static bool validateOperandClass(MCParsedAsmOperand *GOp, " << "MatchClassKind Kind) {\n"; OS << " " << Info.Target.getName() << "Operand &Operand = *(" << Info.Target.getName() << "Operand*)GOp;\n"; @@ -1676,7 +1676,7 @@ // Check for Token operands first. OS << " if (Operand.isToken())\n"; - OS << " return MatchTokenString(Operand.getToken()) == Kind;\n\n"; + OS << " return matchTokenString(Operand.getToken()) == Kind;\n\n"; // Check for register operands, including sub-classes. OS << " if (Operand.isReg()) {\n"; @@ -1690,7 +1690,7 @@ << it->first->getName() << ": OpKind = " << it->second->Name << "; break;\n"; OS << " }\n"; - OS << " return IsSubclass(OpKind, Kind);\n"; + OS << " return isSubclass(OpKind, Kind);\n"; OS << " }\n\n"; // Check the user classes. We don't care what order since we're only @@ -1717,8 +1717,8 @@ static void EmitIsSubclass(CodeGenTarget &Target, std::vector &Infos, raw_ostream &OS) { - OS << "/// IsSubclass - Compute whether \\arg A is a subclass of \\arg B.\n"; - OS << "static bool IsSubclass(MatchClassKind A, MatchClassKind B) {\n"; + OS << "/// isSubclass - Compute whether \\arg A is a subclass of \\arg B.\n"; + OS << "static bool isSubclass(MatchClassKind A, MatchClassKind B) {\n"; OS << " if (A == B)\n"; OS << " return true;\n\n"; @@ -1776,7 +1776,7 @@ "return " + CI.Name + ";")); } - OS << "static MatchClassKind MatchTokenString(StringRef Name) {\n"; + OS << "static MatchClassKind matchTokenString(StringRef Name) {\n"; StringMatcher("Name", Matches, OS).Emit(); @@ -1914,7 +1914,7 @@ Info.getRecords().getAllDerivedDefinitions("MnemonicAlias"); if (Aliases.empty()) return false; - OS << "static void ApplyMnemonicAliases(StringRef &Mnemonic, " + OS << "static void applyMnemonicAliases(StringRef &Mnemonic, " "unsigned Features) {\n"; // Keep track of all the aliases from a mnemonic. Use an std::map so that the @@ -2063,7 +2063,7 @@ // the found operand class. OS << Target.getName() << ClassName << "::OperandMatchResultTy " << Target.getName() << ClassName << "::\n" - << "TryCustomParseOperand(SmallVectorImpl" + << "tryCustomParseOperand(SmallVectorImpl" << " &Operands,\n unsigned MCK) {\n\n" << " switch(MCK) {\n"; @@ -2129,7 +2129,7 @@ // Emit call to the custom parser method OS << " // call custom parse method to handle the operand\n"; OS << " OperandMatchResultTy Result = "; - OS << "TryCustomParseOperand(Operands, it->Class);\n"; + OS << "tryCustomParseOperand(Operands, it->Class);\n"; OS << " if (Result != MatchOperand_NoMatch)\n"; OS << " return Result;\n"; OS << " }\n\n"; @@ -2216,7 +2216,7 @@ OS << " SmallVectorImpl &Operands,\n"; OS << " StringRef Mnemonic);\n"; - OS << " OperandMatchResultTy TryCustomParseOperand(\n"; + OS << " OperandMatchResultTy tryCustomParseOperand(\n"; OS << " SmallVectorImpl &Operands,\n"; OS << " unsigned MCK);\n\n"; } @@ -2363,7 +2363,7 @@ if (HasMnemonicAliases) { OS << " // Process all MnemonicAliases to remap the mnemonic.\n"; - OS << " ApplyMnemonicAliases(Mnemonic, AvailableFeatures);\n\n"; + OS << " applyMnemonicAliases(Mnemonic, AvailableFeatures);\n\n"; } // Emit code to compute the class list for this operand vector. @@ -2405,7 +2405,7 @@ OS << " OperandsValid = (it->Classes[i] == " <<"InvalidMatchClass);\n"; OS << " break;\n"; OS << " }\n"; - OS << " if (ValidateOperandClass(Operands[i+1], " + OS << " if (validateOperandClass(Operands[i+1], " "(MatchClassKind)it->Classes[i]))\n"; OS << " continue;\n"; OS << " // If this operand is broken for all of the instances of this\n"; From isanbard at gmail.com Tue Dec 6 15:34:01 2011 From: isanbard at gmail.com (Bill Wendling) Date: Tue, 06 Dec 2011 21:34:01 -0000 Subject: [llvm-commits] [llvm] r145969 - /llvm/trunk/lib/Target/X86/X86FrameLowering.cpp Message-ID: <20111206213402.0B84F1BE003@llvm.org> Author: void Date: Tue Dec 6 15:34:01 2011 New Revision: 145969 URL: http://llvm.org/viewvc/llvm-project?rev=145969&view=rev Log: Encode the total stack if there isn't a frame. Modified: llvm/trunk/lib/Target/X86/X86FrameLowering.cpp Modified: llvm/trunk/lib/Target/X86/X86FrameLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86FrameLowering.cpp?rev=145969&r1=145968&r2=145969&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86FrameLowering.cpp (original) +++ llvm/trunk/lib/Target/X86/X86FrameLowering.cpp Tue Dec 6 15:34:01 2011 @@ -564,12 +564,13 @@ CompactUnwindEncoding |= (StackAdjust & 0xFF) << 16; CompactUnwindEncoding |= RegEnc & 0x7FFF; } else { - if ((StackSize & 0xFF) == StackSize) { + uint32_t TotalStackSize = StackAdjust + StackSize; + if ((TotalStackSize & 0xFF) == TotalStackSize) { // Frameless stack with a small stack size. CompactUnwindEncoding |= 0x02000000; // Encode the stack size. - CompactUnwindEncoding |= (StackSize & 0xFF) << 16; + CompactUnwindEncoding |= (TotalStackSize & 0xFF) << 16; } else { if ((StackAdjust & 0x7) != StackAdjust) // The extra stack adjustments are too big for us to handle. From jstaszak at apple.com Tue Dec 6 17:33:07 2011 From: jstaszak at apple.com (Jakub Staszak) Date: Tue, 06 Dec 2011 23:33:07 -0000 Subject: [llvm-commits] [llvm] r145991 - /llvm/trunk/docs/ReleaseNotes.html Message-ID: <20111206233307.DD0D71BE003@llvm.org> Author: kuba Date: Tue Dec 6 17:33:07 2011 New Revision: 145991 URL: http://llvm.org/viewvc/llvm-project?rev=145991&view=rev Log: Make Release Notes HTML 4.01 Strict. Modified: llvm/trunk/docs/ReleaseNotes.html Modified: llvm/trunk/docs/ReleaseNotes.html URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/ReleaseNotes.html?rev=145991&r1=145990&r2=145991&view=diff ============================================================================== --- llvm/trunk/docs/ReleaseNotes.html (original) +++ llvm/trunk/docs/ReleaseNotes.html Tue Dec 6 17:33:07 2011 @@ -10,8 +10,10 @@

    LLVM 3.0 Release Notes

    -LLVM Dragon Logo +
    +LLVM Dragon Logo +
    1. Introduction
      2. @@ -94,7 +96,7 @@ production-quality compiler for C, Objective-C, C++ and Objective-C++ on x86 (32- and 64-bit), and for Darwin/ARM targets.

      -

      In the LLVM 3.0 time-frame, the Clang team has made many improvements: +

      In the LLVM 3.0 time-frame, the Clang team has made many improvements:

      • Greatly improved support for building C++ applications, with greater stability and better diagnostics.
        • @@ -136,7 +138,7 @@ interface, to improve the performance of code completion and the mapping from source locations to abstract syntax tree nodes.
      -For more details about the changes to Clang since the 2.9 release, see the +

      For more details about the changes to Clang since the 2.9 release, see the Clang release notes

      @@ -1289,8 +1291,6 @@ - -

      Additional Information From hfinkel at anl.gov Tue Dec 6 17:39:15 2011 From: hfinkel at anl.gov (Hal Finkel) Date: Tue, 06 Dec 2011 17:39:15 -0600 Subject: [llvm-commits] Dead register (was Re: [llvm] r145819) In-Reply-To: References: <20111205175518.343FF2A6C12C@llvm.org> <1323112465.2507.3170.camel@sapling> <1323118601.2507.3183.camel@sapling> Message-ID: <1323214755.2507.3294.camel@sapling> On Mon, 2011-12-05 at 13:18 -0800, Jakob Stoklund Olesen wrote: > On Dec 5, 2011, at 12:56 PM, Hal Finkel wrote: > > > RegScavenger is complaining about use of an undefined register, CTR8, in > > the BCTR8 instruction, in the following instance (this is from the PPC > > backend): > > > > BB#38: derived from LLVM BB %for.end50 > > Predecessors according to CFG: BB#36 > > %X3 = LD 0, ; mem:LD8[FixedStack27] > > %X4 = RLDICR %X3, 3, 60 > > %X5 = LI8 [TF=4] > > %X5 = ADDIS8 %X5, [TF=8] > > %X4 = LDX %X4, %X5; mem:LD8[JumpTable] > > MTCTR8 %X4, %CTR8 > > BCTR8 %CTR8, %RM > > Successors according to CFG: BB#23 BB#15 BB#7 BB#8 BB#9 BB#10 BB#11 > > BB#25 BB#12 BB#16 BB#18 BB#13 BB#17 > > > > How could CRT8 be marked implicitly-defined and also dead in the same > > instruction when it is clearly used in the next instruction? > > This is the kind of sloppy liveness, I was talking about ;-) > > llc -verify-machineinstrs should give you better info. Unfortunately, this just tells me what I already knew: *** Bad machine code: Using an undefined physical register *** - function: check - basic block: for.end50 0x2bef428 (BB#38) - instruction: BCTR8 %CTR8, %RM - operand 0: %CTR8 LLVM ERROR: Found 1 machine code errors. This comes from the following four statements in PPCDAGToDAGISel::Select; what's wrong here? SDValue Chain = N->getOperand(0); SDValue Target = N->getOperand(1); unsigned Opc = PPC::MTCTR8; unsigned Reg = PPC::BCTR8; Chain = SDValue(CurDAG->getMachineNode(Opc, dl, MVT::Other, Target, Chain), 0); return CurDAG->SelectNodeTo(N, Reg, MVT::Other, Chain); Thanks again, Hal > > /jakob > -- Hal Finkel Postdoctoral Appointee Leadership Computing Facility Argonne National Laboratory From clattner at apple.com Tue Dec 6 17:38:10 2011 From: clattner at apple.com (Chris Lattner) Date: Tue, 06 Dec 2011 15:38:10 -0800 Subject: [llvm-commits] [llvm] r145975 - in /llvm/trunk: include/llvm/CodeGen/ include/llvm/MC/ include/llvm/Target/ lib/CodeGen/ lib/CodeGen/SelectionDAG/ lib/Target/ARM/ lib/Target/Mips/ lib/Target/PTX/ utils/TableGen/ In-Reply-To: <20111206221201.B71981BE003@llvm.org> References: <20111206221201.B71981BE003@llvm.org> Message-ID: <9AEFAD50-41C2-46D8-AF87-84D729568818@apple.com> On Dec 6, 2011, at 2:12 PM, Evan Cheng wrote: > Author: evancheng > Date: Tue Dec 6 16:12:01 2011 > New Revision: 145975 > > URL: http://llvm.org/viewvc/llvm-project?rev=145975&view=rev > Log: > First chunk of MachineInstr bundle support. > 1. Added opcode BUNDLE > 2. Taught MachineInstr class to deal with bundled MIs > 3. Changed MachineBasicBlock iterator to skip over bundled MIs; added an iterator to walk all the MIs > 4. Taught MachineBasicBlock methods about bundled MIs Nice! Please add some high level description of this to llvm/docs/CodeGenerator.html. -Chris From grosbach at apple.com Tue Dec 6 17:43:54 2011 From: grosbach at apple.com (Jim Grosbach) Date: Tue, 06 Dec 2011 23:43:54 -0000 Subject: [llvm-commits] [llvm] r145992 - in /llvm/trunk: include/llvm/Target/Target.td utils/TableGen/AsmMatcherEmitter.cpp Message-ID: <20111206234354.441411BE003@llvm.org> Author: grosbach Date: Tue Dec 6 17:43:54 2011 New Revision: 145992 URL: http://llvm.org/viewvc/llvm-project?rev=145992&view=rev Log: Extend AsmMatcher token literal matching to allow aliasing. For example, ARM allows: vmov.u32 s4, #0 -> vmov.i32, #0 'u32' is a more specific designator for the 32-bit integer type specifier and is legal for any instruction which accepts 'i32' as a datatype suffix. We want to say, def : TokenAlias<".u32", ".i32">; This works by marking the match class of 'From' as a subclass of the match class of 'To'. rdar://10435076 Modified: llvm/trunk/include/llvm/Target/Target.td llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp Modified: llvm/trunk/include/llvm/Target/Target.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/Target.td?rev=145992&r1=145991&r2=145992&view=diff ============================================================================== --- llvm/trunk/include/llvm/Target/Target.td (original) +++ llvm/trunk/include/llvm/Target/Target.td Tue Dec 6 17:43:54 2011 @@ -738,7 +738,20 @@ string AssemblerCondString = cond; } - +/// TokenAlias - This class allows targets to define assembler token +/// operand aliases. That is, a token literal operand which is equivalent +/// to another, canonical, token literal. For example, ARM allows: +/// vmov.u32 s4, #0 -> vmov.i32, #0 +/// 'u32' is a more specific designator for the 32-bit integer type specifier +/// and is legal for any instruction which accepts 'i32' as a datatype suffix. +/// def : TokenAlias<".u32", ".i32">; +/// +/// This works by marking the match class of 'From' as a subclass of the +/// match class of 'To'. +class TokenAlias { + string FromToken = From; + string ToToken = To; +} /// MnemonicAlias - This class allows targets to define assembler mnemonic /// aliases. This should be used when all forms of one mnemonic are accepted Modified: llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp?rev=145992&r1=145991&r2=145992&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp (original) +++ llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp Tue Dec 6 17:43:54 2011 @@ -252,11 +252,6 @@ switch (Kind) { case Invalid: assert(0 && "Invalid kind!"); - case Token: - // Tokens are comparable by value. - // - // FIXME: Compare by enum value. - return ValueName < RHS.ValueName; default: // This class precedes the RHS if it is a proper subset of the RHS. @@ -1304,6 +1299,17 @@ II->BuildAliasResultOperands(); } + // Process token alias definitions and set up the associated superclass + // information. + std::vector AllTokenAliases = + Records.getAllDerivedDefinitions("TokenAlias"); + for (unsigned i = 0, e = AllTokenAliases.size(); i != e; ++i) { + Record *Rec = AllTokenAliases[i]; + ClassInfo *FromClass = getTokenClass(Rec->getValueAsString("FromToken")); + ClassInfo *ToClass = getTokenClass(Rec->getValueAsString("ToToken")); + FromClass->SuperClasses.push_back(ToClass); + } + // Reorder classes so that classes precede super classes. std::sort(Classes.begin(), Classes.end(), less_ptr()); } @@ -1676,7 +1682,8 @@ // Check for Token operands first. OS << " if (Operand.isToken())\n"; - OS << " return matchTokenString(Operand.getToken()) == Kind;\n\n"; + OS << " return isSubclass(matchTokenString(Operand.getToken()), Kind);" + << "\n\n"; // Check for register operands, including sub-classes. OS << " if (Operand.isReg()) {\n"; @@ -1729,32 +1736,30 @@ ie = Infos.end(); it != ie; ++it) { ClassInfo &A = **it; - if (A.Kind != ClassInfo::Token) { - std::vector SuperClasses; - for (std::vector::iterator it = Infos.begin(), - ie = Infos.end(); it != ie; ++it) { - ClassInfo &B = **it; - - if (&A != &B && A.isSubsetOf(B)) - SuperClasses.push_back(B.Name); - } + std::vector SuperClasses; + for (std::vector::iterator it = Infos.begin(), + ie = Infos.end(); it != ie; ++it) { + ClassInfo &B = **it; - if (SuperClasses.empty()) - continue; + if (&A != &B && A.isSubsetOf(B)) + SuperClasses.push_back(B.Name); + } - OS << "\n case " << A.Name << ":\n"; + if (SuperClasses.empty()) + continue; - if (SuperClasses.size() == 1) { - OS << " return B == " << SuperClasses.back() << ";\n"; - continue; - } + OS << "\n case " << A.Name << ":\n"; - OS << " switch (B) {\n"; - OS << " default: return false;\n"; - for (unsigned i = 0, e = SuperClasses.size(); i != e; ++i) - OS << " case " << SuperClasses[i] << ": return true;\n"; - OS << " }\n"; + if (SuperClasses.size() == 1) { + OS << " return B == " << SuperClasses.back() << ";\n"; + continue; } + + OS << " switch (B) {\n"; + OS << " default: return false;\n"; + for (unsigned i = 0, e = SuperClasses.size(); i != e; ++i) + OS << " case " << SuperClasses[i] << ": return true;\n"; + OS << " }\n"; } OS << " }\n"; OS << "}\n\n"; From jstaszak at apple.com Tue Dec 6 17:59:33 2011 From: jstaszak at apple.com (Jakub Staszak) Date: Tue, 06 Dec 2011 23:59:33 -0000 Subject: [llvm-commits] [llvm] r145993 - /llvm/trunk/lib/CodeGen/MachineBlockPlacement.cpp Message-ID: <20111206235933.C7DAF1BE003@llvm.org> Author: kuba Date: Tue Dec 6 17:59:33 2011 New Revision: 145993 URL: http://llvm.org/viewvc/llvm-project?rev=145993&view=rev Log: - Remove unneeded #includes. - Remove unused types/fields. - Add some constantness. Modified: llvm/trunk/lib/CodeGen/MachineBlockPlacement.cpp Modified: llvm/trunk/lib/CodeGen/MachineBlockPlacement.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineBlockPlacement.cpp?rev=145993&r1=145992&r2=145993&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/MachineBlockPlacement.cpp (original) +++ llvm/trunk/lib/CodeGen/MachineBlockPlacement.cpp Tue Dec 6 17:59:33 2011 @@ -36,10 +36,7 @@ #include "llvm/CodeGen/Passes.h" #include "llvm/Support/Allocator.h" #include "llvm/Support/Debug.h" -#include "llvm/Support/ErrorHandling.h" #include "llvm/ADT/DenseMap.h" -#include "llvm/ADT/PostOrderIterator.h" -#include "llvm/ADT/SCCIterator.h" #include "llvm/ADT/SmallPtrSet.h" #include "llvm/ADT/SmallVector.h" #include "llvm/ADT/Statistic.h" @@ -56,22 +53,6 @@ "Potential frequency of taking unconditional branches"); namespace { -/// \brief A structure for storing a weighted edge. -/// -/// This stores an edge and its weight, computed as the product of the -/// frequency that the starting block is entered with the probability of -/// a particular exit block. -struct WeightedEdge { - BlockFrequency EdgeFrequency; - MachineBasicBlock *From, *To; - - bool operator<(const WeightedEdge &RHS) const { - return EdgeFrequency < RHS.EdgeFrequency; - } -}; -} - -namespace { class BlockChain; /// \brief Type for our function-wide basic block -> block chain mapping. typedef DenseMap BlockToChainMapType; @@ -121,17 +102,15 @@ } /// \brief Iterator over blocks within the chain. - typedef SmallVectorImpl::iterator iterator; - typedef SmallVectorImpl::reverse_iterator + typedef SmallVectorImpl::const_iterator iterator; + typedef SmallVectorImpl::const_reverse_iterator reverse_iterator; /// \brief Beginning of blocks within the chain. - iterator begin() { return Blocks.begin(); } - reverse_iterator rbegin() { return Blocks.rbegin(); } + iterator begin() const { return Blocks.begin(); } /// \brief End of blocks within the chain. - iterator end() { return Blocks.end(); } - reverse_iterator rend() { return Blocks.rend(); } + iterator end() const { return Blocks.end(); } /// \brief Merge a block chain into this one. /// From grosbach at apple.com Tue Dec 6 18:02:18 2011 From: grosbach at apple.com (Jim Grosbach) Date: Wed, 07 Dec 2011 00:02:18 -0000 Subject: [llvm-commits] [llvm] r145994 - /llvm/trunk/lib/Target/ARM/ARMInstrNEON.td Message-ID: <20111207000218.584131BE003@llvm.org> Author: grosbach Date: Tue Dec 6 18:02:17 2011 New Revision: 145994 URL: http://llvm.org/viewvc/llvm-project?rev=145994&view=rev Log: ARM: Parameterize the immediate operand type for NEON VSHLL. No functional change yet. Will be implementing range-checked immediates for better diagnostics and disambiguation of instructions. Modified: llvm/trunk/lib/Target/ARM/ARMInstrNEON.td Modified: llvm/trunk/lib/Target/ARM/ARMInstrNEON.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrNEON.td?rev=145994&r1=145993&r2=145994&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrNEON.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrNEON.td Tue Dec 6 18:02:17 2011 @@ -2666,9 +2666,9 @@ // Long shift by immediate. class N2VLSh op11_8, bit op7, bit op6, bit op4, string OpcodeStr, string Dt, - ValueType ResTy, ValueType OpTy, SDNode OpNode> + ValueType ResTy, ValueType OpTy, Operand ImmTy, SDNode OpNode> : N2VImm; @@ -3567,15 +3567,15 @@ multiclass N2VLSh_QHS op11_8, bit op7, bit op6, bit op4, string OpcodeStr, string Dt, SDNode OpNode> { def v8i16 : N2VLSh { + OpcodeStr, !strconcat(Dt, "8"), v8i16, v8i8, i32imm, OpNode> { let Inst{21-19} = 0b001; // imm6 = 001xxx } def v4i32 : N2VLSh { + OpcodeStr, !strconcat(Dt, "16"), v4i32, v4i16, i32imm, OpNode> { let Inst{21-20} = 0b01; // imm6 = 01xxxx } def v2i64 : N2VLSh { + OpcodeStr, !strconcat(Dt, "32"), v2i64, v2i32, i32imm, OpNode> { let Inst{21} = 0b1; // imm6 = 1xxxxx } } @@ -4375,18 +4375,18 @@ // VSHLL : Vector Shift Left Long (with maximum shift count) class N2VLShMax op21_16, bits<4> op11_8, bit op7, bit op6, bit op4, string OpcodeStr, string Dt, ValueType ResTy, - ValueType OpTy, SDNode OpNode> + ValueType OpTy, Operand ImmTy, SDNode OpNode> : N2VLSh { + ResTy, OpTy, ImmTy, OpNode> { let Inst{21-16} = op21_16; let DecoderMethod = "DecodeVSHLMaxInstruction"; } def VSHLLi8 : N2VLShMax<1, 1, 0b110010, 0b0011, 0, 0, 0, "vshll", "i8", - v8i16, v8i8, NEONvshlli>; + v8i16, v8i8, i32imm, NEONvshlli>; def VSHLLi16 : N2VLShMax<1, 1, 0b110110, 0b0011, 0, 0, 0, "vshll", "i16", - v4i32, v4i16, NEONvshlli>; + v4i32, v4i16, i32imm, NEONvshlli>; def VSHLLi32 : N2VLShMax<1, 1, 0b111010, 0b0011, 0, 0, 0, "vshll", "i32", - v2i64, v2i32, NEONvshlli>; + v2i64, v2i32, i32imm, NEONvshlli>; // VSHRN : Vector Shift Right and Narrow defm VSHRN : N2VNSh_HSD<0,1,0b1000,0,0,1, IIC_VSHLiD, "vshrn", "i", From chandlerc at google.com Tue Dec 6 18:06:26 2011 From: chandlerc at google.com (Chandler Carruth) Date: Tue, 6 Dec 2011 16:06:26 -0800 Subject: [llvm-commits] [llvm] r145993 - /llvm/trunk/lib/CodeGen/MachineBlockPlacement.cpp In-Reply-To: <20111206235933.C7DAF1BE003@llvm.org> References: <20111206235933.C7DAF1BE003@llvm.org> Message-ID: On Tue, Dec 6, 2011 at 3:59 PM, Jakub Staszak wrote: > Author: kuba > Date: Tue Dec 6 17:59:33 2011 > New Revision: 145993 > > URL: http://llvm.org/viewvc/llvm-project?rev=145993&view=rev > Log: > - Remove unneeded #includes. > - Remove unused types/fields. > - Add some constantness. > Thanks for the cleanups! Any general comments on the code is also welcome. =D > /// \brief Iterator over blocks within the chain. > - typedef SmallVectorImpl::iterator iterator; > - typedef SmallVectorImpl::reverse_iterator > + typedef SmallVectorImpl::const_iterator iterator; > + typedef SmallVectorImpl::const_reverse_iterator > reverse_iterator; > Is this one still needed? You deleted the rbegin/rend methods... -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20111206/d53fd1ca/attachment.html From jstaszak at apple.com Tue Dec 6 18:08:01 2011 From: jstaszak at apple.com (Jakub Staszak) Date: Wed, 07 Dec 2011 00:08:01 -0000 Subject: [llvm-commits] [llvm] r145995 - /llvm/trunk/lib/CodeGen/MachineBlockPlacement.cpp Message-ID: <20111207000801.650781BE003@llvm.org> Author: kuba Date: Tue Dec 6 18:08:00 2011 New Revision: 145995 URL: http://llvm.org/viewvc/llvm-project?rev=145995&view=rev Log: Remove unneeded type. Modified: llvm/trunk/lib/CodeGen/MachineBlockPlacement.cpp Modified: llvm/trunk/lib/CodeGen/MachineBlockPlacement.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineBlockPlacement.cpp?rev=145995&r1=145994&r2=145995&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/MachineBlockPlacement.cpp (original) +++ llvm/trunk/lib/CodeGen/MachineBlockPlacement.cpp Tue Dec 6 18:08:00 2011 @@ -103,8 +103,6 @@ /// \brief Iterator over blocks within the chain. typedef SmallVectorImpl::const_iterator iterator; - typedef SmallVectorImpl::const_reverse_iterator - reverse_iterator; /// \brief Beginning of blocks within the chain. iterator begin() const { return Blocks.begin(); } From kubastaszak at gmail.com Tue Dec 6 18:12:53 2011 From: kubastaszak at gmail.com (Jakub Staszak) Date: Wed, 7 Dec 2011 01:12:53 +0100 Subject: [llvm-commits] [llvm] r145993 - /llvm/trunk/lib/CodeGen/MachineBlockPlacement.cpp In-Reply-To: References: <20111206235933.C7DAF1BE003@llvm.org> Message-ID: <2F3A6347-EB49-4026-BF68-F1BCB4C6AACB@gmail.com> On Dec 7, 2011, at 1:06 AM, Chandler Carruth wrote: > On Tue, Dec 6, 2011 at 3:59 PM, Jakub Staszak wrote: > Author: kuba > Date: Tue Dec 6 17:59:33 2011 > New Revision: 145993 > > URL: http://llvm.org/viewvc/llvm-project?rev=145993&view=rev > Log: > - Remove unneeded #includes. > - Remove unused types/fields. > - Add some constantness. > > Thanks for the cleanups! Any general comments on the code is also welcome. =D > > /// \brief Iterator over blocks within the chain. > - typedef SmallVectorImpl::iterator iterator; > - typedef SmallVectorImpl::reverse_iterator > + typedef SmallVectorImpl::const_iterator iterator; > + typedef SmallVectorImpl::const_reverse_iterator > reverse_iterator; > > Is this one still needed? You deleted the rbegin/rend methods? I just noticed that, removed in r145995. - Kuba -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20111207/9bce8d46/attachment.html From eli.friedman at gmail.com Tue Dec 6 18:11:56 2011 From: eli.friedman at gmail.com (Eli Friedman) Date: Wed, 07 Dec 2011 00:11:56 -0000 Subject: [llvm-commits] [llvm] r145996 - in /llvm/trunk: lib/CodeGen/SelectionDAG/DAGCombiner.cpp test/CodeGen/X86/2011-12-06-AVXVectorExtractCombine.ll Message-ID: <20111207001156.641BF1BE003@llvm.org> Author: efriedma Date: Tue Dec 6 18:11:56 2011 New Revision: 145996 URL: http://llvm.org/viewvc/llvm-project?rev=145996&view=rev Log: Fix an optimization involving EXTRACT_SUBVECTOR in DAGCombine so it behaves correctly. PR11494. Added: llvm/trunk/test/CodeGen/X86/2011-12-06-AVXVectorExtractCombine.ll Modified: llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Modified: llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp?rev=145996&r1=145995&r2=145996&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Tue Dec 6 18:11:56 2011 @@ -7181,19 +7181,23 @@ if (NVT != SmallVT || NVT.getSizeInBits()*2 != BigVT.getSizeInBits()) return SDValue(); - // Combine: - // (extract_subvec (insert_subvec V1, V2, InsIdx), ExtIdx) - // Into: - // indicies are equal => V1 - // otherwise => (extract_subvec V1, ExtIdx) - // - SDValue InsIdx = N->getOperand(1); - SDValue ExtIdx = V->getOperand(2); - - if (InsIdx == ExtIdx) - return V->getOperand(1); - return DAG.getNode(ISD::EXTRACT_SUBVECTOR, N->getDebugLoc(), NVT, - V->getOperand(0), N->getOperand(1)); + // Only handle cases where both indexes are constants with the same type. + ConstantSDNode *InsIdx = dyn_cast(N->getOperand(1)); + ConstantSDNode *ExtIdx = dyn_cast(V->getOperand(2)); + + if (InsIdx && ExtIdx && + InsIdx->getValueType(0).getSizeInBits() <= 64 && + ExtIdx->getValueType(0).getSizeInBits() <= 64) { + // Combine: + // (extract_subvec (insert_subvec V1, V2, InsIdx), ExtIdx) + // Into: + // indices are equal => V1 + // otherwise => (extract_subvec V1, ExtIdx) + if (InsIdx->getZExtValue() == ExtIdx->getZExtValue()) + return V->getOperand(1); + return DAG.getNode(ISD::EXTRACT_SUBVECTOR, N->getDebugLoc(), NVT, + V->getOperand(0), N->getOperand(1)); + } } return SDValue(); Added: llvm/trunk/test/CodeGen/X86/2011-12-06-AVXVectorExtractCombine.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2011-12-06-AVXVectorExtractCombine.ll?rev=145996&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/X86/2011-12-06-AVXVectorExtractCombine.ll (added) +++ llvm/trunk/test/CodeGen/X86/2011-12-06-AVXVectorExtractCombine.ll Tue Dec 6 18:11:56 2011 @@ -0,0 +1,18 @@ +; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=corei7-avx -mattr=+avx | FileCheck %s +; PR11494 + +define void @test(<4 x i32>* nocapture %p) nounwind { + ; CHECK: test: + ; CHECK: vpxor %xmm0, %xmm0, %xmm0 + ; CHECK-NEXT: vpmaxsd {{.*}}, %xmm0, %xmm0 + ; CHECK-NEXT: vmovdqu %xmm0, (%rdi) + ; CHECK-NEXT: ret + %a = call <4 x i32> @llvm.x86.sse41.pmaxsd(<4 x i32> , <4 x i32> zeroinitializer) nounwind + %b = shufflevector <4 x i32> %a, <4 x i32> undef, <8 x i32> + %c = shufflevector <8 x i32> %b, <8 x i32> undef, <4 x i32> + store <4 x i32> %c, <4 x i32>* %p, align 1 + ret void +} + +declare <4 x i32> @llvm.x86.sse41.pminsd(<4 x i32>, <4 x i32>) nounwind readnone +declare <4 x i32> @llvm.x86.sse41.pmaxsd(<4 x i32>, <4 x i32>) nounwind readnone From stoklund at 2pi.dk Tue Dec 6 18:22:07 2011 From: stoklund at 2pi.dk (Jakob Stoklund Olesen) Date: Wed, 07 Dec 2011 00:22:07 -0000 Subject: [llvm-commits] [llvm] r145997 - in /llvm/trunk: include/llvm/CodeGen/MachineOperand.h lib/CodeGen/MachineInstr.cpp Message-ID: <20111207002207.A566F1BE003@llvm.org> Author: stoklund Date: Tue Dec 6 18:22:07 2011 New Revision: 145997 URL: http://llvm.org/viewvc/llvm-project?rev=145997&view=rev Log: Add MachineOperand IsInternalRead flag. This flag is used when bundling machine instructions. It indicates whether the operand reads a value defined inside or outside its bundle. Modified: llvm/trunk/include/llvm/CodeGen/MachineOperand.h llvm/trunk/lib/CodeGen/MachineInstr.cpp Modified: llvm/trunk/include/llvm/CodeGen/MachineOperand.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/MachineOperand.h?rev=145997&r1=145996&r2=145997&view=diff ============================================================================== --- llvm/trunk/include/llvm/CodeGen/MachineOperand.h (original) +++ llvm/trunk/include/llvm/CodeGen/MachineOperand.h Tue Dec 6 18:22:07 2011 @@ -102,6 +102,17 @@ /// bool IsUndef : 1; + /// IsInternalRead - True if this operand reads a value that was defined + /// inside the same instruction or bundle. This flag can be set on both use + /// and def operands. On a sub-register def operand, it refers to the part + /// of the register that isn't written. On a full-register def operand, it + /// is a noop. + /// + /// When this flag is set, the instruction bundle must contain at least one + /// other def of the register. If multiple instructions in the bundle define + /// the register, the meaning is target-defined. + bool IsInternalRead : 1; + /// IsEarlyClobber - True if this MO_Register 'def' operand is written to /// by the MachineInstr before all input registers are read. This is used to /// model the GCC inline asm '&' constraint modifier. @@ -258,6 +269,11 @@ return IsUndef; } + bool isInternalRead() const { + assert(isReg() && "Wrong MachineOperand accessor"); + return IsInternalRead; + } + bool isEarlyClobber() const { assert(isReg() && "Wrong MachineOperand accessor"); return IsEarlyClobber; @@ -272,9 +288,12 @@ /// register. A use operand with the flag set doesn't read its /// register. A sub-register def implicitly reads the other parts of the /// register being redefined unless the flag is set. + /// + /// This refers to reading the register value from before the current + /// instruction or bundle. Internal bundle reads are not included. bool readsReg() const { assert(isReg() && "Wrong MachineOperand accessor"); - return !isUndef() && (isUse() || getSubReg()); + return !isUndef() && !isInternalRead() && (isUse() || getSubReg()); } /// getNextOperandForReg - Return the next MachineOperand in the function that @@ -343,6 +362,11 @@ IsUndef = Val; } + void setIsInternalRead(bool Val = true) { + assert(isReg() && "Wrong MachineOperand accessor"); + IsInternalRead = Val; + } + void setIsEarlyClobber(bool Val = true) { assert(isReg() && IsDef && "Wrong MachineOperand accessor"); IsEarlyClobber = Val; @@ -498,6 +522,7 @@ Op.IsKill = isKill; Op.IsDead = isDead; Op.IsUndef = isUndef; + Op.IsInternalRead = false; Op.IsEarlyClobber = isEarlyClobber; Op.IsDebug = isDebug; Op.SmallContents.RegNo = Reg; Modified: llvm/trunk/lib/CodeGen/MachineInstr.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineInstr.cpp?rev=145997&r1=145996&r2=145997&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/MachineInstr.cpp (original) +++ llvm/trunk/lib/CodeGen/MachineInstr.cpp Tue Dec 6 18:22:07 2011 @@ -178,6 +178,7 @@ IsKill = isKill; IsDead = isDead; IsUndef = isUndef; + IsInternalRead = false; IsEarlyClobber = false; IsDebug = isDebug; SubReg = 0; @@ -256,14 +257,26 @@ NeedComma = true; } - if (isKill() || isDead() || isUndef()) { + if (isKill() || isDead() || isUndef() || isInternalRead()) { if (NeedComma) OS << ','; - if (isKill()) OS << "kill"; - if (isDead()) OS << "dead"; + NeedComma = false; + if (isKill()) { + OS << "kill"; + NeedComma = true; + } + if (isDead()) { + OS << "dead"; + NeedComma = true; + } if (isUndef()) { - if (isKill() || isDead()) - OS << ','; + if (NeedComma) OS << ','; OS << "undef"; + NeedComma = true; + } + if (isInternalRead()) { + if (NeedComma) OS << ','; + OS << "internal"; + NeedComma = true; } } OS << '>'; From bruno.cardoso at gmail.com Tue Dec 6 18:28:57 2011 From: bruno.cardoso at gmail.com (Bruno Cardoso Lopes) Date: Wed, 07 Dec 2011 00:28:57 -0000 Subject: [llvm-commits] [llvm] r145998 - in /llvm/trunk: include/llvm/MC/MCExpr.h include/llvm/Support/ELF.h lib/MC/ELFObjectWriter.cpp lib/Target/Mips/InstPrinter/MipsInstPrinter.cpp lib/Target/Mips/MCTargetDesc/MipsAsmBackend.cpp lib/Target/Mips/MCTargetDesc/MipsBaseInfo.h lib/Target/Mips/MCTargetDesc/MipsFixupKinds.h lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp lib/Target/Mips/MipsISelLowering.cpp lib/Target/Mips/MipsMCInstLower.cpp Message-ID: <20111207002858.13CCF1BE003@llvm.org> Author: bruno Date: Tue Dec 6 18:28:57 2011 New Revision: 145998 URL: http://llvm.org/viewvc/llvm-project?rev=145998&view=rev Log: Add a few moreLocal/Global R_MIPS_GOT related fixups and make the addend fixup code a bit more generic Patch by Jack Carter. Modified: llvm/trunk/include/llvm/MC/MCExpr.h llvm/trunk/include/llvm/Support/ELF.h llvm/trunk/lib/MC/ELFObjectWriter.cpp llvm/trunk/lib/Target/Mips/InstPrinter/MipsInstPrinter.cpp llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsAsmBackend.cpp llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsBaseInfo.h llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsFixupKinds.h llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp llvm/trunk/lib/Target/Mips/MipsMCInstLower.cpp Modified: llvm/trunk/include/llvm/MC/MCExpr.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/MC/MCExpr.h?rev=145998&r1=145997&r2=145998&view=diff ============================================================================== --- llvm/trunk/include/llvm/MC/MCExpr.h (original) +++ llvm/trunk/include/llvm/MC/MCExpr.h Tue Dec 6 18:28:57 2011 @@ -179,6 +179,7 @@ VK_Mips_None, VK_Mips_GPREL, VK_Mips_GOT_CALL, + VK_Mips_GOT16, VK_Mips_GOT, VK_Mips_ABS_HI, VK_Mips_ABS_LO, Modified: llvm/trunk/include/llvm/Support/ELF.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Support/ELF.h?rev=145998&r1=145997&r2=145998&view=diff ============================================================================== --- llvm/trunk/include/llvm/Support/ELF.h (original) +++ llvm/trunk/include/llvm/Support/ELF.h Tue Dec 6 18:28:57 2011 @@ -627,6 +627,7 @@ R_MIPS_GPREL16 = 7, R_MIPS_LITERAL = 8, R_MIPS_GOT16 = 9, + R_MIPS_GOT = 9, R_MIPS_PC16 = 10, R_MIPS_CALL16 = 11, R_MIPS_GPREL32 = 12, Modified: llvm/trunk/lib/MC/ELFObjectWriter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/ELFObjectWriter.cpp?rev=145998&r1=145997&r2=145998&view=diff ============================================================================== --- llvm/trunk/lib/MC/ELFObjectWriter.cpp (original) +++ llvm/trunk/lib/MC/ELFObjectWriter.cpp Tue Dec 6 18:28:57 2011 @@ -1872,7 +1872,8 @@ case Mips::fixup_Mips_CALL16: Type = ELF::R_MIPS_CALL16; break; - case Mips::fixup_Mips_GOT16: + case Mips::fixup_Mips_GOT_Global: + case Mips::fixup_Mips_GOT_Local: Type = ELF::R_MIPS_GOT16; break; case Mips::fixup_Mips_HI16: Modified: llvm/trunk/lib/Target/Mips/InstPrinter/MipsInstPrinter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/InstPrinter/MipsInstPrinter.cpp?rev=145998&r1=145997&r2=145998&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/InstPrinter/MipsInstPrinter.cpp (original) +++ llvm/trunk/lib/Target/Mips/InstPrinter/MipsInstPrinter.cpp Tue Dec 6 18:28:57 2011 @@ -96,6 +96,7 @@ case MCSymbolRefExpr::VK_None: break; case MCSymbolRefExpr::VK_Mips_GPREL: OS << "%gp_rel("; break; case MCSymbolRefExpr::VK_Mips_GOT_CALL: OS << "%call16("; break; + case MCSymbolRefExpr::VK_Mips_GOT16: OS << "%got("; break; case MCSymbolRefExpr::VK_Mips_GOT: OS << "%got("; break; case MCSymbolRefExpr::VK_Mips_ABS_HI: OS << "%hi("; break; case MCSymbolRefExpr::VK_Mips_ABS_LO: OS << "%lo("; break; Modified: llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsAsmBackend.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsAsmBackend.cpp?rev=145998&r1=145997&r2=145998&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsAsmBackend.cpp (original) +++ llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsAsmBackend.cpp Tue Dec 6 18:28:57 2011 @@ -29,13 +29,19 @@ #include "llvm/Support/ELF.h" #include "llvm/Support/ErrorHandling.h" #include "llvm/Support/raw_ostream.h" + using namespace llvm; +// Prepare value for the target space for it static unsigned adjustFixupValue(unsigned Kind, uint64_t Value) { // Add/subtract and shift switch (Kind) { default: + return 0; + case FK_GPRel_4: + case FK_Data_4: + case Mips::fixup_Mips_LO16: break; case Mips::fixup_Mips_PC16: // So far we are only using this type for branches. @@ -52,25 +58,10 @@ // address range. Value >>= 2; break; - } - - // Mask off value for placement as an operand - switch (Kind) { - default: - break; - case FK_GPRel_4: - case FK_Data_4: - Value &= 0xffffffff; - break; - case Mips::fixup_Mips_26: - Value &= 0x03ffffff; - break; - case Mips::fixup_Mips_LO16: - case Mips::fixup_Mips_PC16: - Value &= 0x0000ffff; - break; case Mips::fixup_Mips_HI16: - Value >>= 16; + case Mips::fixup_Mips_GOT_Local: + // Get the higher 16-bits. Also add 1 if bit 15 is 1. + Value = (Value >> 16) + ((Value & 0x8000) != 0); break; } @@ -96,42 +87,40 @@ /// fixup kind as appropriate. void ApplyFixup(const MCFixup &Fixup, char *Data, unsigned DataSize, uint64_t Value) const { - unsigned Kind = (unsigned)Fixup.getKind(); - Value = adjustFixupValue(Kind, Value); + MCFixupKind Kind = Fixup.getKind(); + Value = adjustFixupValue((unsigned)Kind, Value); if (!Value) - return; // Doesn't change encoding. + return; // Doesn't change encoding. unsigned Offset = Fixup.getOffset(); - switch (Kind) { - default: - llvm_unreachable("Unknown fixup kind!"); - case Mips::fixup_Mips_GOT16: // This will be fixed up at link time - break; - case FK_GPRel_4: - case FK_Data_4: - case Mips::fixup_Mips_26: - case Mips::fixup_Mips_LO16: - case Mips::fixup_Mips_PC16: - case Mips::fixup_Mips_HI16: - // For each byte of the fragment that the fixup touches, mask i - // the fixup value. The Value has been "split up" into the appr - // bitfields above. - for (unsigned i = 0; i != 4; ++i) // FIXME - Need to support 2 and 8 bytes - Data[Offset + i] += uint8_t((Value >> (i * 8)) & 0xff); - break; + // FIXME: The below code will not work across endian models + // How many bytes/bits are we fixing up? + unsigned NumBytes = ((getFixupKindInfo(Kind).TargetSize-1)/8)+1; + uint64_t Mask = ((uint64_t)1 << getFixupKindInfo(Kind).TargetSize) - 1; + + // Grab current value, if any, from bits. + uint64_t CurVal = 0; + for (unsigned i = 0; i != NumBytes; ++i) + CurVal |= ((uint8_t)Data[Offset + i]) << (i * 8); + + CurVal = (CurVal & ~Mask) | ((CurVal + Value) & Mask); + + // Write out the bytes back to the code/data bits. + // First the unaffected bits and then the fixup. + for (unsigned i = 0; i != NumBytes; ++i) { + Data[Offset + i] = uint8_t((CurVal >> (i * 8)) & 0xff); } - } +} unsigned getNumFixupKinds() const { return Mips::NumTargetFixupKinds; } const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const { const static MCFixupKindInfo Infos[Mips::NumTargetFixupKinds] = { - // This table *must* be in the order that the fixup_* kinds a + // This table *must* be in same the order of fixup_* kinds in // MipsFixupKinds.h. // // name offset bits flags - { "fixup_Mips_NONE", 0, 0, 0 }, { "fixup_Mips_16", 0, 16, 0 }, { "fixup_Mips_32", 0, 32, 0 }, { "fixup_Mips_REL32", 0, 32, 0 }, @@ -140,7 +129,8 @@ { "fixup_Mips_LO16", 0, 16, 0 }, { "fixup_Mips_GPREL16", 0, 16, 0 }, { "fixup_Mips_LITERAL", 0, 16, 0 }, - { "fixup_Mips_GOT16", 0, 16, 0 }, + { "fixup_Mips_GOT_Global", 0, 16, 0 }, + { "fixup_Mips_GOT_Local", 0, 16, 0 }, { "fixup_Mips_PC16", 0, 16, MCFixupKindInfo::FKF_IsPCRel }, { "fixup_Mips_CALL16", 0, 16, 0 }, { "fixup_Mips_GPREL32", 0, 32, 0 }, Modified: llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsBaseInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsBaseInfo.h?rev=145998&r1=145997&r2=145998&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsBaseInfo.h (original) +++ llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsBaseInfo.h Tue Dec 6 18:28:57 2011 @@ -31,8 +31,9 @@ MO_NO_FLAG, - /// MO_GOT - Represents the offset into the global offset table at which + /// MO_GOT16 - Represents the offset into the global offset table at which /// the address the relocation entry symbol resides during execution. + MO_GOT16, MO_GOT, /// MO_GOT_CALL - Represents the offset into the global offset table at Modified: llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsFixupKinds.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsFixupKinds.h?rev=145998&r1=145997&r2=145998&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsFixupKinds.h (original) +++ llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsFixupKinds.h Tue Dec 6 18:28:57 2011 @@ -42,8 +42,11 @@ // fixup_Mips_xxx - R_MIPS_LITERAL. fixup_Mips_LITERAL, - // fixup_Mips_xxx - R_MIPS_GOT16. - fixup_Mips_GOT16, + // Global symbol fixup resulting in - R_MIPS_GOT16. + fixup_Mips_GOT_Global, + + // Local symbol fixup resulting in - R_MIPS_GOT16. + fixup_Mips_GOT_Local, // fixup_Mips_xxx - R_MIPS_PC16. fixup_Mips_PC16, Modified: llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp?rev=145998&r1=145997&r2=145998&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp (original) +++ llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp Tue Dec 6 18:28:57 2011 @@ -194,8 +194,11 @@ case MCSymbolRefExpr::VK_Mips_GOT_CALL: FixupKind = Mips::fixup_Mips_CALL16; break; + case MCSymbolRefExpr::VK_Mips_GOT16: + FixupKind = Mips::fixup_Mips_GOT_Global; + break; case MCSymbolRefExpr::VK_Mips_GOT: - FixupKind = Mips::fixup_Mips_GOT16; + FixupKind = Mips::fixup_Mips_GOT_Local; break; case MCSymbolRefExpr::VK_Mips_ABS_HI: FixupKind = Mips::fixup_Mips_HI16; Modified: llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp?rev=145998&r1=145997&r2=145998&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp (original) +++ llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp Tue Dec 6 18:28:57 2011 @@ -1488,7 +1488,7 @@ (GV->hasLocalLinkage() && !isa(GV))); unsigned GotFlag = IsN64 ? (HasGotOfst ? MipsII::MO_GOT_PAGE : MipsII::MO_GOT_DISP) : - MipsII::MO_GOT; + (HasGotOfst ? MipsII::MO_GOT : MipsII::MO_GOT16); SDValue GA = DAG.getTargetGlobalAddress(GV, dl, ValTy, 0, GotFlag); GA = DAG.getNode(MipsISD::WrapperPIC, dl, ValTy, GA); SDValue ResNode = DAG.getLoad(ValTy, dl, Modified: llvm/trunk/lib/Target/Mips/MipsMCInstLower.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsMCInstLower.cpp?rev=145998&r1=145997&r2=145998&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/MipsMCInstLower.cpp (original) +++ llvm/trunk/lib/Target/Mips/MipsMCInstLower.cpp Tue Dec 6 18:28:57 2011 @@ -41,6 +41,7 @@ case MipsII::MO_NO_FLAG: Kind = MCSymbolRefExpr::VK_None; break; case MipsII::MO_GPREL: Kind = MCSymbolRefExpr::VK_Mips_GPREL; break; case MipsII::MO_GOT_CALL: Kind = MCSymbolRefExpr::VK_Mips_GOT_CALL; break; + case MipsII::MO_GOT16: Kind = MCSymbolRefExpr::VK_Mips_GOT16; break; case MipsII::MO_GOT: Kind = MCSymbolRefExpr::VK_Mips_GOT; break; case MipsII::MO_ABS_HI: Kind = MCSymbolRefExpr::VK_Mips_ABS_HI; break; case MipsII::MO_ABS_LO: Kind = MCSymbolRefExpr::VK_Mips_ABS_LO; break; From rafael.espindola at gmail.com Tue Dec 6 18:47:30 2011 From: rafael.espindola at gmail.com (=?ISO-8859-1?Q?Rafael_=C1vila_de_Esp=EDndola?=) Date: Tue, 06 Dec 2011 19:47:30 -0500 Subject: [llvm-commits] [llvm] r145911 - in /llvm/trunk/lib/MC: ELFObjectWriter.cpp ELFObjectWriter.h In-Reply-To: <20111206033442.E04352A6C12C@llvm.org> References: <20111206033442.E04352A6C12C@llvm.org> Message-ID: <4EDEB7A2.5070108@gmail.com> On 05/12/11 10:34 PM, Bruno Cardoso Lopes wrote: > Author: bruno > Date: Mon Dec 5 21:34:42 2011 > New Revision: 145911 > > URL: http://llvm.org/viewvc/llvm-project?rev=145911&view=rev > Log: > Explicit symbols for gnu mimicing relocations. Patch by Jack Carter > testcase? Cheers, Rafael From eli.friedman at gmail.com Tue Dec 6 18:50:54 2011 From: eli.friedman at gmail.com (Eli Friedman) Date: Wed, 07 Dec 2011 00:50:54 -0000 Subject: [llvm-commits] [llvm] r146001 - in /llvm/trunk: lib/CodeGen/AsmPrinter/AsmPrinter.cpp test/CodeGen/X86/2011-12-06-BitcastVectorGlobal.ll Message-ID: <20111207005054.985271BE003@llvm.org> Author: efriedma Date: Tue Dec 6 18:50:54 2011 New Revision: 146001 URL: http://llvm.org/viewvc/llvm-project?rev=146001&view=rev Log: Support vector bitcasts in the AsmPrinter. PR11495. Added: llvm/trunk/test/CodeGen/X86/2011-12-06-BitcastVectorGlobal.ll Modified: llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp Modified: llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp?rev=146001&r1=146000&r2=146001&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp (original) +++ llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp Tue Dec 6 18:50:54 2011 @@ -1642,6 +1642,28 @@ AP.OutStreamer.EmitZeros(Padding, AddrSpace); } +static void LowerVectorConstant(const Constant *CV, unsigned AddrSpace, + AsmPrinter &AP) { + // Look through bitcasts + if (const ConstantExpr *CE = dyn_cast(CV)) + if (CE->getOpcode() == Instruction::BitCast) + CV = CE->getOperand(0); + + if (const ConstantVector *V = dyn_cast(CV)) + return EmitGlobalConstantVector(V, AddrSpace, AP); + + // If we get here, we're stuck; report the problem to the user. + // FIXME: Are there any other useful tricks for vectors? + { + std::string S; + raw_string_ostream OS(S); + OS << "Unsupported vector expression in static initializer: "; + WriteAsOperand(OS, CV, /*PrintType=*/false, + !AP.MF ? 0 : AP.MF->getFunction()->getParent()); + report_fatal_error(OS.str()); + } +} + static void EmitGlobalConstantStruct(const ConstantStruct *CS, unsigned AddrSpace, AsmPrinter &AP) { // Print the fields in successive locations. Pad to align if needed! @@ -1796,8 +1818,8 @@ return; } - if (const ConstantVector *V = dyn_cast(CV)) - return EmitGlobalConstantVector(V, AddrSpace, AP); + if (CV->getType()->isVectorTy()) + return LowerVectorConstant(CV, AddrSpace, AP); // Otherwise, it must be a ConstantExpr. Lower it to an MCExpr, then emit it // thread the streamer with EmitValue. Added: llvm/trunk/test/CodeGen/X86/2011-12-06-BitcastVectorGlobal.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2011-12-06-BitcastVectorGlobal.ll?rev=146001&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/X86/2011-12-06-BitcastVectorGlobal.ll (added) +++ llvm/trunk/test/CodeGen/X86/2011-12-06-BitcastVectorGlobal.ll Tue Dec 6 18:50:54 2011 @@ -0,0 +1,5 @@ +; RUN: llc < %s -march=x86-64 | FileCheck %s +; PR11495 + +; CHECK: 1311768467463790320 + at v = global <2 x float> bitcast (<1 x i64> to <2 x float>), align 8 From grosbach at apple.com Tue Dec 6 19:07:24 2011 From: grosbach at apple.com (Jim Grosbach) Date: Wed, 07 Dec 2011 01:07:24 -0000 Subject: [llvm-commits] [llvm] r146003 - in /llvm/trunk: lib/Target/ARM/ARMInstrInfo.td lib/Target/ARM/ARMInstrNEON.td lib/Target/ARM/AsmParser/ARMAsmParser.cpp utils/TableGen/EDEmitter.cpp Message-ID: <20111207010724.DCD761BE003@llvm.org> Author: grosbach Date: Tue Dec 6 19:07:24 2011 New Revision: 146003 URL: http://llvm.org/viewvc/llvm-project?rev=146003&view=rev Log: ARM: NEON SHLL instruction immediate operand range checking. Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td llvm/trunk/lib/Target/ARM/ARMInstrNEON.td llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp llvm/trunk/utils/TableGen/EDEmitter.cpp Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.td?rev=146003&r1=146002&r2=146003&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrInfo.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Tue Dec 6 19:07:24 2011 @@ -238,11 +238,6 @@ return CurDAG->getTargetConstant(~(int)N->getZExtValue(), MVT::i32); }]>; -/// imm1_15 predicate - True if the 32-bit immediate is in the range [1,15]. -def imm1_15 : ImmLeaf= 1 && (int32_t)Imm < 16; -}]>; - /// imm16_31 predicate - True if the 32-bit immediate is in the range [16,31]. def imm16_31 : ImmLeaf= 16 && (int32_t)Imm < 32; @@ -528,6 +523,42 @@ let ParserMatchClass = Imm0_7AsmOperand; } +/// imm8 predicate - Immediate is exactly 8. +def Imm8AsmOperand: ImmAsmOperand { let Name = "Imm8"; } +def imm8 : Operand, ImmLeaf { + let ParserMatchClass = Imm8AsmOperand; +} + +/// imm16 predicate - Immediate is exactly 16. +def Imm16AsmOperand: ImmAsmOperand { let Name = "Imm16"; } +def imm16 : Operand, ImmLeaf { + let ParserMatchClass = Imm16AsmOperand; +} + +/// imm32 predicate - Immediate is exactly 32. +def Imm32AsmOperand: ImmAsmOperand { let Name = "Imm32"; } +def imm32 : Operand, ImmLeaf { + let ParserMatchClass = Imm32AsmOperand; +} + +/// imm1_7 predicate - Immediate in the range [1,7]. +def Imm1_7AsmOperand: ImmAsmOperand { let Name = "Imm1_7"; } +def imm1_7 : Operand, ImmLeaf 0 && Imm < 8; }]> { + let ParserMatchClass = Imm1_7AsmOperand; +} + +/// imm1_15 predicate - Immediate in the range [1,15]. +def Imm1_15AsmOperand: ImmAsmOperand { let Name = "Imm1_15"; } +def imm1_15 : Operand, ImmLeaf 0 && Imm < 16; }]> { + let ParserMatchClass = Imm1_15AsmOperand; +} + +/// imm1_31 predicate - Immediate in the range [1,31]. +def Imm1_31AsmOperand: ImmAsmOperand { let Name = "Imm1_31"; } +def imm1_31 : Operand, ImmLeaf 0 && Imm < 32; }]> { + let ParserMatchClass = Imm1_31AsmOperand; +} + /// imm0_15 predicate - Immediate in the range [0,15]. def Imm0_15AsmOperand: ImmAsmOperand { let Name = "Imm0_15"; } def imm0_15 : Operand, ImmLeaf op11_8, bit op7, bit op6, bit op4, string OpcodeStr, string Dt, SDNode OpNode> { def v8i16 : N2VLSh { + OpcodeStr, !strconcat(Dt, "8"), v8i16, v8i8, imm1_7, OpNode> { let Inst{21-19} = 0b001; // imm6 = 001xxx } def v4i32 : N2VLSh { + OpcodeStr, !strconcat(Dt, "16"), v4i32, v4i16, imm1_15, OpNode> { let Inst{21-20} = 0b01; // imm6 = 01xxxx } def v2i64 : N2VLSh { + OpcodeStr, !strconcat(Dt, "32"), v2i64, v2i32, imm1_31, OpNode> { let Inst{21} = 0b1; // imm6 = 1xxxxx } } @@ -4382,11 +4382,11 @@ let DecoderMethod = "DecodeVSHLMaxInstruction"; } def VSHLLi8 : N2VLShMax<1, 1, 0b110010, 0b0011, 0, 0, 0, "vshll", "i8", - v8i16, v8i8, i32imm, NEONvshlli>; + v8i16, v8i8, imm8, NEONvshlli>; def VSHLLi16 : N2VLShMax<1, 1, 0b110110, 0b0011, 0, 0, 0, "vshll", "i16", - v4i32, v4i16, i32imm, NEONvshlli>; + v4i32, v4i16, imm16, NEONvshlli>; def VSHLLi32 : N2VLShMax<1, 1, 0b111010, 0b0011, 0, 0, 0, "vshll", "i32", - v2i64, v2i32, i32imm, NEONvshlli>; + v2i64, v2i32, imm32, NEONvshlli>; // VSHRN : Vector Shift Right and Narrow defm VSHRN : N2VNSh_HSD<0,1,0b1000,0,0,1, IIC_VSHLiD, "vshrn", "i", Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp?rev=146003&r1=146002&r2=146003&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp (original) +++ llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Tue Dec 6 19:07:24 2011 @@ -610,6 +610,54 @@ int64_t Value = CE->getValue(); return Value >= 0 && Value < 32; } + bool isImm8() const { + if (Kind != k_Immediate) + return false; + const MCConstantExpr *CE = dyn_cast(getImm()); + if (!CE) return false; + int64_t Value = CE->getValue(); + return Value == 8; + } + bool isImm16() const { + if (Kind != k_Immediate) + return false; + const MCConstantExpr *CE = dyn_cast(getImm()); + if (!CE) return false; + int64_t Value = CE->getValue(); + return Value == 16; + } + bool isImm32() const { + if (Kind != k_Immediate) + return false; + const MCConstantExpr *CE = dyn_cast(getImm()); + if (!CE) return false; + int64_t Value = CE->getValue(); + return Value == 32; + } + bool isImm1_7() const { + if (Kind != k_Immediate) + return false; + const MCConstantExpr *CE = dyn_cast(getImm()); + if (!CE) return false; + int64_t Value = CE->getValue(); + return Value > 0 && Value < 8; + } + bool isImm1_15() const { + if (Kind != k_Immediate) + return false; + const MCConstantExpr *CE = dyn_cast(getImm()); + if (!CE) return false; + int64_t Value = CE->getValue(); + return Value > 0 && Value < 16; + } + bool isImm1_31() const { + if (Kind != k_Immediate) + return false; + const MCConstantExpr *CE = dyn_cast(getImm()); + if (!CE) return false; + int64_t Value = CE->getValue(); + return Value > 0 && Value < 32; + } bool isImm1_16() const { if (Kind != k_Immediate) return false; Modified: llvm/trunk/utils/TableGen/EDEmitter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/EDEmitter.cpp?rev=146003&r1=146002&r2=146003&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/EDEmitter.cpp (original) +++ llvm/trunk/utils/TableGen/EDEmitter.cpp Tue Dec 6 19:07:24 2011 @@ -610,6 +610,12 @@ IMM("nImmSplatI64"); IMM("nImmVMOVI32"); IMM("nImmVMOVF32"); + IMM("imm8"); + IMM("imm16"); + IMM("imm32"); + IMM("imm1_7"); + IMM("imm1_15"); + IMM("imm1_31"); IMM("imm0_1"); IMM("imm0_3"); IMM("imm0_7"); From stoklund at 2pi.dk Tue Dec 6 19:08:22 2011 From: stoklund at 2pi.dk (Jakob Stoklund Olesen) Date: Wed, 07 Dec 2011 01:08:22 -0000 Subject: [llvm-commits] [llvm] r146004 - /llvm/trunk/lib/CodeGen/MachineInstr.cpp Message-ID: <20111207010822.618CC1BE003@llvm.org> Author: stoklund Date: Tue Dec 6 19:08:22 2011 New Revision: 146004 URL: http://llvm.org/viewvc/llvm-project?rev=146004&view=rev Log: Add missing check. Modified: llvm/trunk/lib/CodeGen/MachineInstr.cpp Modified: llvm/trunk/lib/CodeGen/MachineInstr.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineInstr.cpp?rev=146004&r1=146003&r2=146004&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/MachineInstr.cpp (original) +++ llvm/trunk/lib/CodeGen/MachineInstr.cpp Tue Dec 6 19:08:22 2011 @@ -241,7 +241,7 @@ OS << PrintReg(getReg(), TRI, getSubReg()); if (isDef() || isKill() || isDead() || isImplicit() || isUndef() || - isEarlyClobber()) { + isInternalRead() || isEarlyClobber()) { OS << '<'; bool NeedComma = false; if (isDef()) { From stoklund at 2pi.dk Tue Dec 6 19:08:25 2011 From: stoklund at 2pi.dk (Jakob Stoklund Olesen) Date: Wed, 07 Dec 2011 01:08:25 -0000 Subject: [llvm-commits] [llvm] r146005 - /llvm/trunk/lib/Target/ARM/ARMConstantIslandPass.cpp Message-ID: <20111207010825.7B1DD1BE003@llvm.org> Author: stoklund Date: Tue Dec 6 19:08:25 2011 New Revision: 146005 URL: http://llvm.org/viewvc/llvm-project?rev=146005&view=rev Log: Group BBSizes and BBOffsets into a single vector. No functional change is intended. Modified: llvm/trunk/lib/Target/ARM/ARMConstantIslandPass.cpp Modified: llvm/trunk/lib/Target/ARM/ARMConstantIslandPass.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMConstantIslandPass.cpp?rev=146005&r1=146004&r2=146005&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMConstantIslandPass.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMConstantIslandPass.cpp Tue Dec 6 19:08:25 2011 @@ -64,16 +64,29 @@ /// CPE - A constant pool entry that has been placed somewhere, which /// tracks a list of users. class ARMConstantIslands : public MachineFunctionPass { - /// BBSizes - The size of each MachineBasicBlock in bytes of code, indexed - /// by MBB Number. The two-byte pads required for Thumb alignment are - /// counted as part of the following block (i.e., the offset and size for - /// a padded block will both be ==2 mod 4). - std::vector BBSizes; - - /// BBOffsets - the offset of each MBB in bytes, starting from 0. - /// The two-byte pads required for Thumb alignment are counted as part of - /// the following block. - std::vector BBOffsets; + /// BasicBlockInfo - Information about the offset and size of a single + /// basic block. + struct BasicBlockInfo { + /// Offset - Distance from the beginning of the function to the beginning + /// of this basic block. + /// + /// The two-byte pads required for Thumb alignment are counted as part of + /// the following block. + unsigned Offset; + + /// Size - Size of the basic block in bytes. If the block contains + /// inline assembly, this is a worst case estimate. + /// + /// The two-byte pads required for Thumb alignment are counted as part of + /// the following block (i.e., the offset and size for a padded block + /// will both be ==2 mod 4). + unsigned Size; + + BasicBlockInfo() : Offset(0), Size(0) {} + BasicBlockInfo(unsigned o, unsigned s) : Offset(o), Size(s) {} + }; + + std::vector BBInfo; /// WaterList - A sorted list of basic blocks where islands could be placed /// (i.e. blocks that don't fall through to the following block, due @@ -227,9 +240,8 @@ /// verify - check BBOffsets, BBSizes, alignment of islands void ARMConstantIslands::verify(MachineFunction &MF) { - assert(BBOffsets.size() == BBSizes.size()); - for (unsigned i = 1, e = BBOffsets.size(); i != e; ++i) - assert(BBOffsets[i-1]+BBSizes[i-1] == BBOffsets[i]); + for (unsigned i = 1, e = BBInfo.size(); i != e; ++i) + assert(BBInfo[i-1].Offset + BBInfo[i-1].Size == BBInfo[i].Offset); if (!isThumb) return; #ifndef NDEBUG @@ -240,8 +252,8 @@ MBB->begin()->getOpcode() == ARM::CONSTPOOL_ENTRY) { unsigned MBBId = MBB->getNumber(); assert(HasInlineAsm || - (BBOffsets[MBBId]%4 == 0 && BBSizes[MBBId]%4 == 0) || - (BBOffsets[MBBId]%4 != 0 && BBSizes[MBBId]%4 != 0)); + (BBInfo[MBBId].Offset%4 == 0 && BBInfo[MBBId].Size%4 == 0) || + (BBInfo[MBBId].Offset%4 != 0 && BBInfo[MBBId].Size%4 != 0)); } } for (unsigned i = 0, e = CPUsers.size(); i != e; ++i) { @@ -257,9 +269,9 @@ /// print block size and offset information - debugging void ARMConstantIslands::dumpBBs() { - for (unsigned J = 0, E = BBOffsets.size(); J !=E; ++J) { - DEBUG(errs() << "block " << J << " offset " << BBOffsets[J] - << " size " << BBSizes[J] << "\n"); + for (unsigned J = 0, E = BBInfo.size(); J !=E; ++J) { + DEBUG(errs() << "block " << J << " offset " << BBInfo[J].Offset + << " size " << BBInfo[J].Size << "\n"); } } @@ -378,8 +390,7 @@ DEBUG(errs() << '\n'; dumpBBs()); - BBSizes.clear(); - BBOffsets.clear(); + BBInfo.clear(); WaterList.clear(); CPUsers.clear(); CPEntries.clear(); @@ -659,8 +670,7 @@ ((Offset%4) != 0 || HasInlineAsm)) MBBSize += 2; - BBSizes.push_back(MBBSize); - BBOffsets.push_back(Offset); + BBInfo.push_back(BasicBlockInfo(Offset, MBBSize)); Offset += MBBSize; } } @@ -674,7 +684,7 @@ // The offset is composed of two things: the sum of the sizes of all MBB's // before this instruction's block, and the offset from the start of the block // it is in. - unsigned Offset = BBOffsets[MBB->getNumber()]; + unsigned Offset = BBInfo[MBB->getNumber()].Offset; // If we're looking for a CONSTPOOL_ENTRY in Thumb, see if this block has // alignment padding, and compensate if so. @@ -705,12 +715,9 @@ // Renumber the MBB's to keep them consecutive. NewBB->getParent()->RenumberBlocks(NewBB); - // Insert a size into BBSizes to align it properly with the (newly + // Insert an entry into BBInfo to align it properly with the (newly // renumbered) block numbers. - BBSizes.insert(BBSizes.begin()+NewBB->getNumber(), 0); - - // Likewise for BBOffsets. - BBOffsets.insert(BBOffsets.begin()+NewBB->getNumber(), 0); + BBInfo.insert(BBInfo.begin() + NewBB->getNumber(), BasicBlockInfo()); // Next, update WaterList. Specifically, we need to add NewMBB as having // available water after it. @@ -760,12 +767,9 @@ // the Water goes after OrigBB, not NewBB. MF.RenumberBlocks(NewBB); - // Insert a size into BBSizes to align it properly with the (newly + // Insert an entry into BBInfo to align it properly with the (newly // renumbered) block numbers. - BBSizes.insert(BBSizes.begin()+NewBB->getNumber(), 0); - - // Likewise for BBOffsets. - BBOffsets.insert(BBOffsets.begin()+NewBB->getNumber(), 0); + BBInfo.insert(BBInfo.begin() + NewBB->getNumber(), BasicBlockInfo()); // Next, update WaterList. Specifically, we need to add OrigMBB as having // available water after it (but not if it's already there, which happens @@ -795,10 +799,10 @@ for (MachineBasicBlock::iterator I = OrigBB->begin(), E = OrigBB->end(); I != E; ++I) OrigBBSize += TII->GetInstSizeInBytes(I); - BBSizes[OrigBBI] = OrigBBSize; + BBInfo[OrigBBI].Size = OrigBBSize; // ...and adjust BBOffsets for NewBB accordingly. - BBOffsets[NewBBI] = BBOffsets[OrigBBI] + BBSizes[OrigBBI]; + BBInfo[NewBBI].Offset = BBInfo[OrigBBI].Offset + BBInfo[OrigBBI].Size; // Figure out how large the NewMBB is. As the second half of the original // block, it may contain a tablejump. @@ -807,7 +811,7 @@ I != E; ++I) NewBBSize += TII->GetInstSizeInBytes(I); // Set the size of NewBB in BBSizes. It does not include any padding now. - BBSizes[NewBBI] = NewBBSize; + BBInfo[NewBBI].Size = NewBBSize; MachineInstr* ThumbJTMI = prior(NewBB->end()); if (ThumbJTMI->getOpcode() == ARM::tBR_JTr) { @@ -815,13 +819,13 @@ // means we will always need padding if we didn't before, and vice versa. // The original offset of the jump instruction was: - unsigned OrigOffset = BBOffsets[OrigBBI] + BBSizes[OrigBBI] - delta; + unsigned OrigOffset = BBInfo[OrigBBI].Offset + BBInfo[OrigBBI].Size - delta; if (OrigOffset%4 == 0) { // We had padding before and now we don't. No net change in code size. delta = 0; } else { // We didn't have padding before and now we do. - BBSizes[NewBBI] += 2; + BBInfo[NewBBI].Size += 2; delta = 4; } } @@ -880,8 +884,8 @@ bool ARMConstantIslands::WaterIsInRange(unsigned UserOffset, MachineBasicBlock* Water, CPUser &U) { unsigned MaxDisp = U.MaxDisp; - unsigned CPEOffset = BBOffsets[Water->getNumber()] + - BBSizes[Water->getNumber()]; + unsigned CPEOffset = BBInfo[Water->getNumber()].Offset + + BBInfo[Water->getNumber()].Size; // If the CPE is to be inserted before the instruction, that will raise // the offset of the instruction. @@ -932,7 +936,7 @@ MachineFunction::iterator MBBI = BB; MBBI = llvm::next(MBBI); for(unsigned i = BB->getNumber()+1, e = BB->getParent()->getNumBlockIDs(); i < e; ++i) { - BBOffsets[i] += delta; + BBInfo[i].Offset += delta; // If some existing blocks have padding, adjust the padding as needed, a // bit tricky. delta can be negative so don't use % on that. if (!isThumb) @@ -941,14 +945,14 @@ if (!MBB->empty() && !HasInlineAsm) { // Constant pool entries require padding. if (MBB->begin()->getOpcode() == ARM::CONSTPOOL_ENTRY) { - unsigned OldOffset = BBOffsets[i] - delta; - if ((OldOffset%4) == 0 && (BBOffsets[i]%4) != 0) { + unsigned OldOffset = BBInfo[i].Offset - delta; + if ((OldOffset%4) == 0 && (BBInfo[i].Offset%4) != 0) { // add new padding - BBSizes[i] += 2; + BBInfo[i].Size += 2; delta += 2; - } else if ((OldOffset%4) != 0 && (BBOffsets[i]%4) == 0) { + } else if ((OldOffset%4) != 0 && (BBInfo[i].Offset%4) == 0) { // remove existing padding - BBSizes[i] -= 2; + BBInfo[i].Size -= 2; delta -= 2; } } @@ -964,11 +968,11 @@ unsigned OldMIOffset = NewMIOffset - delta; if ((OldMIOffset%4) == 0 && (NewMIOffset%4) != 0) { // remove existing padding - BBSizes[i] -= 2; + BBInfo[i].Size -= 2; delta -= 2; } else if ((OldMIOffset%4) != 0 && (NewMIOffset%4) == 0) { // add new padding - BBSizes[i] += 2; + BBInfo[i].Size += 2; delta += 2; } } @@ -1091,7 +1095,7 @@ NewWaterList.count(WaterBB))) { unsigned WBBId = WaterBB->getNumber(); if (isThumb && - (BBOffsets[WBBId] + BBSizes[WBBId])%4 != 0) { + (BBInfo[WBBId].Offset + BBInfo[WBBId].Size)%4 != 0) { // This is valid Water, but would introduce padding. Remember // it in case we don't find any Water that doesn't do this. if (!FoundWaterThatWouldPad) { @@ -1127,9 +1131,9 @@ MachineInstr *UserMI = U.MI; MachineInstr *CPEMI = U.CPEMI; MachineBasicBlock *UserMBB = UserMI->getParent(); - unsigned OffsetOfNextBlock = BBOffsets[UserMBB->getNumber()] + - BBSizes[UserMBB->getNumber()]; - assert(OffsetOfNextBlock== BBOffsets[UserMBB->getNumber()+1]); + unsigned OffsetOfNextBlock = BBInfo[UserMBB->getNumber()].Offset + + BBInfo[UserMBB->getNumber()].Size; + assert(OffsetOfNextBlock== BBInfo[UserMBB->getNumber()+1].Offset); // If the block does not end in an unconditional branch already, and if the // end of the block is within range, make new water there. (The addition @@ -1158,7 +1162,7 @@ ImmBranches.push_back(ImmBranch(&UserMBB->back(), MaxDisp, false, UncondBr)); int delta = isThumb1 ? 2 : 4; - BBSizes[UserMBB->getNumber()] += delta; + BBInfo[UserMBB->getNumber()].Size += delta; AdjustBBOffsetsAfter(UserMBB, delta); } else { // What a big block. Find a place within the block to split it. @@ -1182,8 +1186,8 @@ // constant pool entries following this block; only the last one is // in the water list. Back past any possible branches (allow for a // conditional and a maximally long unconditional). - if (BaseInsertOffset >= BBOffsets[UserMBB->getNumber()+1]) - BaseInsertOffset = BBOffsets[UserMBB->getNumber()+1] - + if (BaseInsertOffset >= BBInfo[UserMBB->getNumber()+1].Offset) + BaseInsertOffset = BBInfo[UserMBB->getNumber()+1].Offset - (isThumb1 ? 6 : 8); unsigned EndInsertOffset = BaseInsertOffset + CPEMI->getOperand(2).getImm(); @@ -1317,12 +1321,12 @@ // Mark the basic block as 4-byte aligned as required by the const-pool entry. NewIsland->setAlignment(2); - BBOffsets[NewIsland->getNumber()] = BBOffsets[NewMBB->getNumber()]; + BBInfo[NewIsland->getNumber()].Offset = BBInfo[NewMBB->getNumber()].Offset; // Compensate for .align 2 in thumb mode. - if (isThumb && (BBOffsets[NewIsland->getNumber()]%4 != 0 || HasInlineAsm)) + if (isThumb && (BBInfo[NewIsland->getNumber()].Offset%4 != 0 || HasInlineAsm)) Size += 2; // Increase the size of the island block to account for the new entry. - BBSizes[NewIsland->getNumber()] += Size; + BBInfo[NewIsland->getNumber()].Size += Size; AdjustBBOffsetsAfter(NewIsland, Size); // Finally, change the CPI in the instruction operand to be ID. @@ -1344,16 +1348,16 @@ MachineBasicBlock *CPEBB = CPEMI->getParent(); unsigned Size = CPEMI->getOperand(2).getImm(); CPEMI->eraseFromParent(); - BBSizes[CPEBB->getNumber()] -= Size; + BBInfo[CPEBB->getNumber()].Size -= Size; // All succeeding offsets have the current size value added in, fix this. if (CPEBB->empty()) { // In thumb1 mode, the size of island may be padded by two to compensate for // the alignment requirement. Then it will now be 2 when the block is // empty, so fix this. // All succeeding offsets have the current size value added in, fix this. - if (BBSizes[CPEBB->getNumber()] != 0) { - Size += BBSizes[CPEBB->getNumber()]; - BBSizes[CPEBB->getNumber()] = 0; + if (BBInfo[CPEBB->getNumber()].Size != 0) { + Size += BBInfo[CPEBB->getNumber()].Size; + BBInfo[CPEBB->getNumber()].Size = 0; } // This block no longer needs to be aligned. . @@ -1390,7 +1394,7 @@ unsigned MaxDisp) { unsigned PCAdj = isThumb ? 4 : 8; unsigned BrOffset = GetOffsetOf(MI) + PCAdj; - unsigned DestOffset = BBOffsets[DestBB->getNumber()]; + unsigned DestOffset = BBInfo[DestBB->getNumber()].Offset; DEBUG(errs() << "Branch of destination BB#" << DestBB->getNumber() << " from BB#" << MI->getParent()->getNumber() @@ -1438,7 +1442,7 @@ // Use BL to implement far jump. Br.MaxDisp = (1 << 21) * 2; MI->setDesc(TII->get(ARM::tBfar)); - BBSizes[MBB->getNumber()] += 2; + BBInfo[MBB->getNumber()].Size += 2; AdjustBBOffsetsAfter(MBB, 2); HasFarJump = true; ++NumUBrFixed; @@ -1502,11 +1506,11 @@ // No need for the branch to the next block. We're adding an unconditional // branch to the destination. int delta = TII->GetInstSizeInBytes(&MBB->back()); - BBSizes[MBB->getNumber()] -= delta; + BBInfo[MBB->getNumber()].Size -= delta; MachineBasicBlock* SplitBB = llvm::next(MachineFunction::iterator(MBB)); AdjustBBOffsetsAfter(SplitBB, -delta); MBB->back().eraseFromParent(); - // BBOffsets[SplitBB] is wrong temporarily, fixed below + // BBInfo[SplitBB].Offset is wrong temporarily, fixed below } MachineBasicBlock *NextBB = llvm::next(MachineFunction::iterator(MBB)); @@ -1519,18 +1523,18 @@ BuildMI(MBB, DebugLoc(), TII->get(MI->getOpcode())) .addMBB(NextBB).addImm(CC).addReg(CCReg); Br.MI = &MBB->back(); - BBSizes[MBB->getNumber()] += TII->GetInstSizeInBytes(&MBB->back()); + BBInfo[MBB->getNumber()].Size += TII->GetInstSizeInBytes(&MBB->back()); if (isThumb) BuildMI(MBB, DebugLoc(), TII->get(Br.UncondBr)).addMBB(DestBB) .addImm(ARMCC::AL).addReg(0); else BuildMI(MBB, DebugLoc(), TII->get(Br.UncondBr)).addMBB(DestBB); - BBSizes[MBB->getNumber()] += TII->GetInstSizeInBytes(&MBB->back()); + BBInfo[MBB->getNumber()].Size += TII->GetInstSizeInBytes(&MBB->back()); unsigned MaxDisp = getUnconditionalBrDisp(Br.UncondBr); ImmBranches.push_back(ImmBranch(&MBB->back(), MaxDisp, false, Br.UncondBr)); // Remove the old conditional branch. It may or may not still be in MBB. - BBSizes[MI->getParent()->getNumber()] -= TII->GetInstSizeInBytes(MI); + BBInfo[MI->getParent()->getNumber()].Size -= TII->GetInstSizeInBytes(MI); MI->eraseFromParent(); // The net size change is an addition of one unconditional branch. @@ -1598,7 +1602,7 @@ if (CPEIsInRange(U.MI, UserOffset, U.CPEMI, MaxOffs, false, true)) { U.MI->setDesc(TII->get(NewOpc)); MachineBasicBlock *MBB = U.MI->getParent(); - BBSizes[MBB->getNumber()] -= 2; + BBInfo[MBB->getNumber()].Size -= 2; AdjustBBOffsetsAfter(MBB, -2); ++NumT2CPShrunk; MadeChange = true; @@ -1639,7 +1643,7 @@ if (BBIsInRange(Br.MI, DestBB, MaxOffs)) { Br.MI->setDesc(TII->get(NewOpc)); MachineBasicBlock *MBB = Br.MI->getParent(); - BBSizes[MBB->getNumber()] -= 2; + BBInfo[MBB->getNumber()].Size -= 2; AdjustBBOffsetsAfter(MBB, -2); ++NumT2BrShrunk; MadeChange = true; @@ -1663,7 +1667,7 @@ // Check if the distance is within 126. Subtract starting offset by 2 // because the cmp will be eliminated. unsigned BrOffset = GetOffsetOf(Br.MI) + 4 - 2; - unsigned DestOffset = BBOffsets[DestBB->getNumber()]; + unsigned DestOffset = BBInfo[DestBB->getNumber()].Offset; if (BrOffset < DestOffset && (DestOffset - BrOffset) <= 126) { MachineBasicBlock::iterator CmpMI = Br.MI; if (CmpMI != Br.MI->getParent()->begin()) { @@ -1681,7 +1685,7 @@ CmpMI->eraseFromParent(); Br.MI->eraseFromParent(); Br.MI = NewBR; - BBSizes[MBB->getNumber()] -= 2; + BBInfo[MBB->getNumber()].Size -= 2; AdjustBBOffsetsAfter(MBB, -2); ++NumCBZ; MadeChange = true; @@ -1720,7 +1724,7 @@ const std::vector &JTBBs = JT[JTI].MBBs; for (unsigned j = 0, ee = JTBBs.size(); j != ee; ++j) { MachineBasicBlock *MBB = JTBBs[j]; - unsigned DstOffset = BBOffsets[MBB->getNumber()]; + unsigned DstOffset = BBInfo[MBB->getNumber()].Offset; // Negative offset is not ok. FIXME: We should change BB layout to make // sure all the branches are forward. if (ByteOk && (DstOffset - JTOffset) > ((1<<8)-1)*2) @@ -1808,7 +1812,7 @@ MI->eraseFromParent(); int delta = OrigSize - NewSize; - BBSizes[MBB->getNumber()] -= delta; + BBInfo[MBB->getNumber()].Size -= delta; AdjustBBOffsetsAfter(MBB, -delta); ++NumTBs; From grosbach at apple.com Tue Dec 6 19:17:58 2011 From: grosbach at apple.com (Jim Grosbach) Date: Wed, 07 Dec 2011 01:17:58 -0000 Subject: [llvm-commits] [llvm] r146007 - /llvm/trunk/lib/Target/ARM/ARMInstrFormats.td Message-ID: <20111207011758.6C5E81BE003@llvm.org> Author: grosbach Date: Tue Dec 6 19:17:58 2011 New Revision: 146007 URL: http://llvm.org/viewvc/llvm-project?rev=146007&view=rev Log: ARM Implement ARM ARM Table A7-3 via TokenAlias. Data type suffix aliasing. Previously handled via lots of instruction aliases. Cleanup of those forthcoming. rdar://10435076 Modified: llvm/trunk/lib/Target/ARM/ARMInstrFormats.td Modified: llvm/trunk/lib/Target/ARM/ARMInstrFormats.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrFormats.td?rev=146007&r1=146006&r2=146007&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrFormats.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrFormats.td Tue Dec 6 19:17:58 2011 @@ -2143,3 +2143,23 @@ defm _ : NEONDT32AsmPseudoInst; defm _ : NEONDT64NoF64AsmPseudoInst; } + +// Data type suffix token aliases. Implements Table A7-3 in the ARM ARM. +def : TokenAlias<".s8", ".i8">; +def : TokenAlias<".u8", ".i8">; +def : TokenAlias<".s16", ".i16">; +def : TokenAlias<".u16", ".i16">; +def : TokenAlias<".s32", ".i32">; +def : TokenAlias<".u32", ".i32">; + +def : TokenAlias<".i8", ".8">; +def : TokenAlias<".i16", ".16">; +def : TokenAlias<".i32", ".32">; + +def : TokenAlias<".p8", ".8">; +def : TokenAlias<".p16", ".16">; + +def : TokenAlias<".f32", ".32">; +def : TokenAlias<".f64", ".64">; +def : TokenAlias<".f", ".f32">; +def : TokenAlias<".d", ".f64">; From stoklund at 2pi.dk Tue Dec 6 19:22:52 2011 From: stoklund at 2pi.dk (Jakob Stoklund Olesen) Date: Wed, 07 Dec 2011 01:22:52 -0000 Subject: [llvm-commits] [llvm] r146008 - /llvm/trunk/lib/Target/ARM/ARMConstantIslandPass.cpp Message-ID: <20111207012252.EB6C21BE003@llvm.org> Author: stoklund Date: Tue Dec 6 19:22:52 2011 New Revision: 146008 URL: http://llvm.org/viewvc/llvm-project?rev=146008&view=rev Log: Move common expression into a method. Modified: llvm/trunk/lib/Target/ARM/ARMConstantIslandPass.cpp Modified: llvm/trunk/lib/Target/ARM/ARMConstantIslandPass.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMConstantIslandPass.cpp?rev=146008&r1=146007&r2=146008&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMConstantIslandPass.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMConstantIslandPass.cpp Tue Dec 6 19:22:52 2011 @@ -84,6 +84,9 @@ BasicBlockInfo() : Offset(0), Size(0) {} BasicBlockInfo(unsigned o, unsigned s) : Offset(o), Size(s) {} + + /// Compute the offset immediately following this block. + unsigned postOffset() const { return Offset + Size; } }; std::vector BBInfo; @@ -241,7 +244,7 @@ /// verify - check BBOffsets, BBSizes, alignment of islands void ARMConstantIslands::verify(MachineFunction &MF) { for (unsigned i = 1, e = BBInfo.size(); i != e; ++i) - assert(BBInfo[i-1].Offset + BBInfo[i-1].Size == BBInfo[i].Offset); + assert(BBInfo[i-1].postOffset() == BBInfo[i].Offset); if (!isThumb) return; #ifndef NDEBUG @@ -802,7 +805,7 @@ BBInfo[OrigBBI].Size = OrigBBSize; // ...and adjust BBOffsets for NewBB accordingly. - BBInfo[NewBBI].Offset = BBInfo[OrigBBI].Offset + BBInfo[OrigBBI].Size; + BBInfo[NewBBI].Offset = BBInfo[OrigBBI].postOffset(); // Figure out how large the NewMBB is. As the second half of the original // block, it may contain a tablejump. @@ -819,7 +822,7 @@ // means we will always need padding if we didn't before, and vice versa. // The original offset of the jump instruction was: - unsigned OrigOffset = BBInfo[OrigBBI].Offset + BBInfo[OrigBBI].Size - delta; + unsigned OrigOffset = BBInfo[OrigBBI].postOffset() - delta; if (OrigOffset%4 == 0) { // We had padding before and now we don't. No net change in code size. delta = 0; @@ -884,8 +887,7 @@ bool ARMConstantIslands::WaterIsInRange(unsigned UserOffset, MachineBasicBlock* Water, CPUser &U) { unsigned MaxDisp = U.MaxDisp; - unsigned CPEOffset = BBInfo[Water->getNumber()].Offset + - BBInfo[Water->getNumber()].Size; + unsigned CPEOffset = BBInfo[Water->getNumber()].postOffset(); // If the CPE is to be inserted before the instruction, that will raise // the offset of the instruction. @@ -1094,8 +1096,7 @@ (WaterBB->getNumber() < U.HighWaterMark->getNumber() || NewWaterList.count(WaterBB))) { unsigned WBBId = WaterBB->getNumber(); - if (isThumb && - (BBInfo[WBBId].Offset + BBInfo[WBBId].Size)%4 != 0) { + if (isThumb && BBInfo[WBBId].postOffset()%4 != 0) { // This is valid Water, but would introduce padding. Remember // it in case we don't find any Water that doesn't do this. if (!FoundWaterThatWouldPad) { @@ -1131,9 +1132,8 @@ MachineInstr *UserMI = U.MI; MachineInstr *CPEMI = U.CPEMI; MachineBasicBlock *UserMBB = UserMI->getParent(); - unsigned OffsetOfNextBlock = BBInfo[UserMBB->getNumber()].Offset + - BBInfo[UserMBB->getNumber()].Size; - assert(OffsetOfNextBlock== BBInfo[UserMBB->getNumber()+1].Offset); + unsigned OffsetOfNextBlock = BBInfo[UserMBB->getNumber()].postOffset(); + assert(OffsetOfNextBlock == BBInfo[UserMBB->getNumber()+1].Offset); // If the block does not end in an unconditional branch already, and if the // end of the block is within range, make new water there. (The addition From grosbach at apple.com Tue Dec 6 19:50:36 2011 From: grosbach at apple.com (Jim Grosbach) Date: Wed, 07 Dec 2011 01:50:36 -0000 Subject: [llvm-commits] [llvm] r146010 - in /llvm/trunk/lib/Target/ARM: ARMInstrFormats.td ARMInstrNEON.td ARMInstrVFP.td Message-ID: <20111207015036.E484E1BE003@llvm.org> Author: grosbach Date: Tue Dec 6 19:50:36 2011 New Revision: 146010 URL: http://llvm.org/viewvc/llvm-project?rev=146010&view=rev Log: ARM tidy up and remove no longer needed InstAlias definitions. The TokenAlias handling of data type suffices renders these unnecessary. Modified: llvm/trunk/lib/Target/ARM/ARMInstrFormats.td llvm/trunk/lib/Target/ARM/ARMInstrNEON.td llvm/trunk/lib/Target/ARM/ARMInstrVFP.td Modified: llvm/trunk/lib/Target/ARM/ARMInstrFormats.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrFormats.td?rev=146010&r1=146009&r2=146010&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrFormats.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrFormats.td Tue Dec 6 19:50:36 2011 @@ -1997,74 +1997,12 @@ // VFP/NEON Instruction aliases for type suffices. class VFPDataTypeInstAlias : InstAlias, Requires<[HasVFP2]>; -multiclass VFPDT8ReqInstAlias { - def I8 : VFPDataTypeInstAlias; - def S8 : VFPDataTypeInstAlias; - def U8 : VFPDataTypeInstAlias; - def P8 : VFPDataTypeInstAlias; -} -// VFPDT8ReqInstAlias plus plain ".8" -multiclass VFPDT8InstAlias { - def _8 : VFPDataTypeInstAlias; - defm _ : VFPDT8ReqInstAlias; -} -multiclass VFPDT16ReqInstAlias { - def I16 : VFPDataTypeInstAlias; - def S16 : VFPDataTypeInstAlias; - def U16 : VFPDataTypeInstAlias; - def P16 : VFPDataTypeInstAlias; -} -// VFPDT16ReqInstAlias plus plain ".16" -multiclass VFPDT16InstAlias { - def _16 : VFPDataTypeInstAlias; - defm _ : VFPDT16ReqInstAlias; -} -multiclass VFPDT32ReqInstAlias { - def I32 : VFPDataTypeInstAlias; - def S32 : VFPDataTypeInstAlias; - def U32 : VFPDataTypeInstAlias; - def F32 : VFPDataTypeInstAlias; - def F : VFPDataTypeInstAlias; -} -// VFPDT32ReqInstAlias plus plain ".32" -multiclass VFPDT32InstAlias { - def _32 : VFPDataTypeInstAlias; - defm _ : VFPDT32ReqInstAlias; -} -multiclass VFPDT64ReqInstAlias { - def I64 : VFPDataTypeInstAlias; - def S64 : VFPDataTypeInstAlias; - def U64 : VFPDataTypeInstAlias; - def F64 : VFPDataTypeInstAlias; - def D : VFPDataTypeInstAlias; -} -// VFPDT64ReqInstAlias plus plain ".64" -multiclass VFPDT64InstAlias { - def _64 : VFPDataTypeInstAlias; - defm _ : VFPDT64ReqInstAlias; -} -multiclass VFPDT64NoF64ReqInstAlias { - def I64 : VFPDataTypeInstAlias; - def S64 : VFPDataTypeInstAlias; - def U64 : VFPDataTypeInstAlias; - def D : VFPDataTypeInstAlias; -} -// VFPDT64ReqInstAlias plus plain ".64" -multiclass VFPDT64NoF64InstAlias { - def _64 : VFPDataTypeInstAlias; - defm _ : VFPDT64ReqInstAlias; -} + multiclass VFPDTAnyInstAlias { - defm _ : VFPDT8InstAlias; - defm _ : VFPDT16InstAlias; - defm _ : VFPDT32InstAlias; - defm _ : VFPDT64InstAlias; -} -multiclass VFPDTAnyNoF64InstAlias { - defm _ : VFPDT8InstAlias; - defm _ : VFPDT16InstAlias; - defm _ : VFPDT32InstAlias; - defm _ : VFPDT64NoF64InstAlias; + def : VFPDataTypeInstAlias; + def : VFPDataTypeInstAlias; + def : VFPDataTypeInstAlias; + def : VFPDataTypeInstAlias; } // The same alias classes using AsmPseudo instead, for the more complex @@ -2151,10 +2089,13 @@ def : TokenAlias<".u16", ".i16">; def : TokenAlias<".s32", ".i32">; def : TokenAlias<".u32", ".i32">; +def : TokenAlias<".s64", ".i64">; +def : TokenAlias<".u64", ".i64">; def : TokenAlias<".i8", ".8">; def : TokenAlias<".i16", ".16">; def : TokenAlias<".i32", ".32">; +def : TokenAlias<".i64", ".64">; def : TokenAlias<".p8", ".8">; def : TokenAlias<".p16", ".16">; Modified: llvm/trunk/lib/Target/ARM/ARMInstrNEON.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrNEON.td?rev=146010&r1=146009&r2=146010&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrNEON.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrNEON.td Tue Dec 6 19:50:36 2011 @@ -4559,10 +4559,6 @@ (VORRd DPR:$Vd, DPR:$Vm, DPR:$Vm, pred:$p)>; def : InstAlias<"vmov${p} $Vd, $Vm", (VORRq QPR:$Vd, QPR:$Vm, QPR:$Vm, pred:$p)>; -defm : VFPDTAnyNoF64InstAlias<"vmov${p}", "$Vd, $Vm", - (VORRd DPR:$Vd, DPR:$Vm, DPR:$Vm, pred:$p)>; -defm : VFPDTAnyNoF64InstAlias<"vmov${p}", "$Vd, $Vm", - (VORRq QPR:$Vd, QPR:$Vm, QPR:$Vm, pred:$p)>; // VMOV : Vector Move (Immediate) @@ -5315,329 +5311,6 @@ defm : VFPDTAnyInstAlias<"vorr${p}", "$Vd, $Vn, $Vm", (VORRq QPR:$Vd, QPR:$Vn, QPR:$Vm, pred:$p)>; -// VLD1 requires a size suffix, but also accepts type specific variants. -// Load one D register. -defm : VFPDT8ReqInstAlias<"vld1${p}", "$Vd, $Rn", - (VLD1d8 VecListOneD:$Vd, addrmode6:$Rn, pred:$p)>; -defm : VFPDT16ReqInstAlias<"vld1${p}", "$Vd, $Rn", - (VLD1d16 VecListOneD:$Vd, addrmode6:$Rn, pred:$p)>; -defm : VFPDT32ReqInstAlias<"vld1${p}", "$Vd, $Rn", - (VLD1d32 VecListOneD:$Vd, addrmode6:$Rn, pred:$p)>; -defm : VFPDT64ReqInstAlias<"vld1${p}", "$Vd, $Rn", - (VLD1d64 VecListOneD:$Vd, addrmode6:$Rn, pred:$p)>; -// with writeback, fixed stride -defm : VFPDT8ReqInstAlias<"vld1${p}", "$Vd, $Rn!", - (VLD1d8wb_fixed VecListOneD:$Vd, zero_reg, addrmode6:$Rn, pred:$p)>; -defm : VFPDT16ReqInstAlias<"vld1${p}", "$Vd, $Rn!", - (VLD1d16wb_fixed VecListOneD:$Vd, zero_reg, addrmode6:$Rn, pred:$p)>; -defm : VFPDT32ReqInstAlias<"vld1${p}", "$Vd, $Rn!", - (VLD1d32wb_fixed VecListOneD:$Vd, zero_reg, addrmode6:$Rn, pred:$p)>; -defm : VFPDT64ReqInstAlias<"vld1${p}", "$Vd, $Rn!", - (VLD1d64wb_fixed VecListOneD:$Vd, zero_reg, addrmode6:$Rn, pred:$p)>; -// with writeback, register stride -defm : VFPDT8ReqInstAlias<"vld1${p}", "$Vd, $Rn, $Rm", - (VLD1d8wb_register VecListOneD:$Vd, zero_reg, addrmode6:$Rn, - rGPR:$Rm, pred:$p)>; -defm : VFPDT16ReqInstAlias<"vld1${p}", "$Vd, $Rn, $Rm", - (VLD1d16wb_register VecListOneD:$Vd, zero_reg, addrmode6:$Rn, - rGPR:$Rm, pred:$p)>; -defm : VFPDT32ReqInstAlias<"vld1${p}", "$Vd, $Rn, $Rm", - (VLD1d32wb_register VecListOneD:$Vd, zero_reg, addrmode6:$Rn, - rGPR:$Rm, pred:$p)>; -defm : VFPDT64ReqInstAlias<"vld1${p}", "$Vd, $Rn, $Rm", - (VLD1d64wb_register VecListOneD:$Vd, zero_reg, addrmode6:$Rn, - rGPR:$Rm, pred:$p)>; - -// Load two D registers. -defm : VFPDT8ReqInstAlias<"vld1${p}", "$Vd, $Rn", - (VLD1q8 VecListTwoD:$Vd, addrmode6:$Rn, pred:$p)>; -defm : VFPDT16ReqInstAlias<"vld1${p}", "$Vd, $Rn", - (VLD1q16 VecListTwoD:$Vd, addrmode6:$Rn, pred:$p)>; -defm : VFPDT32ReqInstAlias<"vld1${p}", "$Vd, $Rn", - (VLD1q32 VecListTwoD:$Vd, addrmode6:$Rn, pred:$p)>; -defm : VFPDT64ReqInstAlias<"vld1${p}", "$Vd, $Rn", - (VLD1q64 VecListTwoD:$Vd, addrmode6:$Rn, pred:$p)>; -// with writeback, fixed stride -defm : VFPDT8ReqInstAlias<"vld1${p}", "$Vd, $Rn!", - (VLD1q8wb_fixed VecListTwoD:$Vd, zero_reg, addrmode6:$Rn, pred:$p)>; -defm : VFPDT16ReqInstAlias<"vld1${p}", "$Vd, $Rn!", - (VLD1q16wb_fixed VecListTwoD:$Vd, zero_reg, addrmode6:$Rn, pred:$p)>; -defm : VFPDT32ReqInstAlias<"vld1${p}", "$Vd, $Rn!", - (VLD1q32wb_fixed VecListTwoD:$Vd, zero_reg, addrmode6:$Rn, pred:$p)>; -defm : VFPDT64ReqInstAlias<"vld1${p}", "$Vd, $Rn!", - (VLD1q64wb_fixed VecListTwoD:$Vd, zero_reg, addrmode6:$Rn, pred:$p)>; -// with writeback, register stride -defm : VFPDT8ReqInstAlias<"vld1${p}", "$Vd, $Rn, $Rm", - (VLD1q8wb_register VecListTwoD:$Vd, zero_reg, addrmode6:$Rn, - rGPR:$Rm, pred:$p)>; -defm : VFPDT16ReqInstAlias<"vld1${p}", "$Vd, $Rn, $Rm", - (VLD1q16wb_register VecListTwoD:$Vd, zero_reg, addrmode6:$Rn, - rGPR:$Rm, pred:$p)>; -defm : VFPDT32ReqInstAlias<"vld1${p}", "$Vd, $Rn, $Rm", - (VLD1q32wb_register VecListTwoD:$Vd, zero_reg, addrmode6:$Rn, - rGPR:$Rm, pred:$p)>; -defm : VFPDT64ReqInstAlias<"vld1${p}", "$Vd, $Rn, $Rm", - (VLD1q64wb_register VecListTwoD:$Vd, zero_reg, addrmode6:$Rn, - rGPR:$Rm, pred:$p)>; - -// Load three D registers. -defm : VFPDT8ReqInstAlias<"vld1${p}", "$Vd, $Rn", - (VLD1d8T VecListThreeD:$Vd, addrmode6:$Rn, pred:$p)>; -defm : VFPDT16ReqInstAlias<"vld1${p}", "$Vd, $Rn", - (VLD1d16T VecListThreeD:$Vd, addrmode6:$Rn, pred:$p)>; -defm : VFPDT32ReqInstAlias<"vld1${p}", "$Vd, $Rn", - (VLD1d32T VecListThreeD:$Vd, addrmode6:$Rn, pred:$p)>; -defm : VFPDT64ReqInstAlias<"vld1${p}", "$Vd, $Rn", - (VLD1d64T VecListThreeD:$Vd, addrmode6:$Rn, pred:$p)>; -// with writeback, fixed stride -defm : VFPDT8ReqInstAlias<"vld1${p}", "$Vd, $Rn!", - (VLD1d8Twb_fixed VecListThreeD:$Vd, zero_reg, - addrmode6:$Rn, pred:$p)>; -defm : VFPDT16ReqInstAlias<"vld1${p}", "$Vd, $Rn!", - (VLD1d16Twb_fixed VecListThreeD:$Vd, zero_reg, - addrmode6:$Rn, pred:$p)>; -defm : VFPDT32ReqInstAlias<"vld1${p}", "$Vd, $Rn!", - (VLD1d32Twb_fixed VecListThreeD:$Vd, zero_reg, - addrmode6:$Rn, pred:$p)>; -defm : VFPDT64ReqInstAlias<"vld1${p}", "$Vd, $Rn!", - (VLD1d64Twb_fixed VecListThreeD:$Vd, zero_reg, - addrmode6:$Rn, pred:$p)>; -// with writeback, register stride -defm : VFPDT8ReqInstAlias<"vld1${p}", "$Vd, $Rn, $Rm", - (VLD1d8Twb_register VecListThreeD:$Vd, zero_reg, - addrmode6:$Rn, rGPR:$Rm, pred:$p)>; -defm : VFPDT16ReqInstAlias<"vld1${p}", "$Vd, $Rn, $Rm", - (VLD1d16Twb_register VecListThreeD:$Vd, zero_reg, - addrmode6:$Rn, rGPR:$Rm, pred:$p)>; -defm : VFPDT32ReqInstAlias<"vld1${p}", "$Vd, $Rn, $Rm", - (VLD1d32Twb_register VecListThreeD:$Vd, zero_reg, - addrmode6:$Rn, rGPR:$Rm, pred:$p)>; -defm : VFPDT64ReqInstAlias<"vld1${p}", "$Vd, $Rn, $Rm", - (VLD1d64Twb_register VecListThreeD:$Vd, zero_reg, - addrmode6:$Rn, rGPR:$Rm, pred:$p)>; - - -// Load four D registers. -defm : VFPDT8ReqInstAlias<"vld1${p}", "$Vd, $Rn", - (VLD1d8Q VecListFourD:$Vd, addrmode6:$Rn, pred:$p)>; -defm : VFPDT16ReqInstAlias<"vld1${p}", "$Vd, $Rn", - (VLD1d16Q VecListFourD:$Vd, addrmode6:$Rn, pred:$p)>; -defm : VFPDT32ReqInstAlias<"vld1${p}", "$Vd, $Rn", - (VLD1d32Q VecListFourD:$Vd, addrmode6:$Rn, pred:$p)>; -defm : VFPDT64ReqInstAlias<"vld1${p}", "$Vd, $Rn", - (VLD1d64Q VecListFourD:$Vd, addrmode6:$Rn, pred:$p)>; -// with writeback, fixed stride -defm : VFPDT8ReqInstAlias<"vld1${p}", "$Vd, $Rn!", - (VLD1d8Qwb_fixed VecListFourD:$Vd, zero_reg, - addrmode6:$Rn, pred:$p)>; -defm : VFPDT16ReqInstAlias<"vld1${p}", "$Vd, $Rn!", - (VLD1d16Qwb_fixed VecListFourD:$Vd, zero_reg, - addrmode6:$Rn, pred:$p)>; -defm : VFPDT32ReqInstAlias<"vld1${p}", "$Vd, $Rn!", - (VLD1d32Qwb_fixed VecListFourD:$Vd, zero_reg, - addrmode6:$Rn, pred:$p)>; -defm : VFPDT64ReqInstAlias<"vld1${p}", "$Vd, $Rn!", - (VLD1d64Qwb_fixed VecListFourD:$Vd, zero_reg, - addrmode6:$Rn, pred:$p)>; -// with writeback, register stride -defm : VFPDT8ReqInstAlias<"vld1${p}", "$Vd, $Rn, $Rm", - (VLD1d8Qwb_register VecListFourD:$Vd, zero_reg, - addrmode6:$Rn, rGPR:$Rm, pred:$p)>; -defm : VFPDT16ReqInstAlias<"vld1${p}", "$Vd, $Rn, $Rm", - (VLD1d16Qwb_register VecListFourD:$Vd, zero_reg, - addrmode6:$Rn, rGPR:$Rm, pred:$p)>; -defm : VFPDT32ReqInstAlias<"vld1${p}", "$Vd, $Rn, $Rm", - (VLD1d32Qwb_register VecListFourD:$Vd, zero_reg, - addrmode6:$Rn, rGPR:$Rm, pred:$p)>; -defm : VFPDT64ReqInstAlias<"vld1${p}", "$Vd, $Rn, $Rm", - (VLD1d64Qwb_register VecListFourD:$Vd, zero_reg, - addrmode6:$Rn, rGPR:$Rm, pred:$p)>; - -// VST1 requires a size suffix, but also accepts type specific variants. -// Store one D register. -defm : VFPDT8ReqInstAlias<"vst1${p}", "$Vd, $Rn", - (VST1d8 addrmode6:$Rn, VecListOneD:$Vd, pred:$p)>; -defm : VFPDT16ReqInstAlias<"vst1${p}", "$Vd, $Rn", - (VST1d16 addrmode6:$Rn, VecListOneD:$Vd, pred:$p)>; -defm : VFPDT32ReqInstAlias<"vst1${p}", "$Vd, $Rn", - (VST1d32 addrmode6:$Rn, VecListOneD:$Vd, pred:$p)>; -defm : VFPDT64ReqInstAlias<"vst1${p}", "$Vd, $Rn", - (VST1d64 addrmode6:$Rn, VecListOneD:$Vd, pred:$p)>; -// with writeback, fixed stride -defm : VFPDT8ReqInstAlias<"vst1${p}", "$Vd, $Rn!", - (VST1d8wb_fixed zero_reg, addrmode6:$Rn, VecListOneD:$Vd, pred:$p)>; -defm : VFPDT16ReqInstAlias<"vst1${p}", "$Vd, $Rn!", - (VST1d16wb_fixed zero_reg, addrmode6:$Rn, VecListOneD:$Vd, pred:$p)>; -defm : VFPDT32ReqInstAlias<"vst1${p}", "$Vd, $Rn!", - (VST1d32wb_fixed zero_reg, addrmode6:$Rn, VecListOneD:$Vd, pred:$p)>; -defm : VFPDT64ReqInstAlias<"vst1${p}", "$Vd, $Rn!", - (VST1d64wb_fixed zero_reg, addrmode6:$Rn, VecListOneD:$Vd, pred:$p)>; -// with writeback, register stride -defm : VFPDT8ReqInstAlias<"vst1${p}", "$Vd, $Rn, $Rm", - (VST1d8wb_register zero_reg, addrmode6:$Rn, rGPR:$Rm, - VecListOneD:$Vd, pred:$p)>; -defm : VFPDT16ReqInstAlias<"vst1${p}", "$Vd, $Rn, $Rm", - (VST1d16wb_register zero_reg, addrmode6:$Rn, rGPR:$Rm, - VecListOneD:$Vd, pred:$p)>; -defm : VFPDT32ReqInstAlias<"vst1${p}", "$Vd, $Rn, $Rm", - (VST1d32wb_register zero_reg, addrmode6:$Rn, rGPR:$Rm, - VecListOneD:$Vd, pred:$p)>; -defm : VFPDT64ReqInstAlias<"vst1${p}", "$Vd, $Rn, $Rm", - (VST1d64wb_register zero_reg, addrmode6:$Rn, rGPR:$Rm, - VecListOneD:$Vd, pred:$p)>; - -// Store two D registers. -defm : VFPDT8ReqInstAlias<"vst1${p}", "$Vd, $Rn", - (VST1q8 addrmode6:$Rn, VecListTwoD:$Vd, pred:$p)>; -defm : VFPDT16ReqInstAlias<"vst1${p}", "$Vd, $Rn", - (VST1q16 addrmode6:$Rn, VecListTwoD:$Vd, pred:$p)>; -defm : VFPDT32ReqInstAlias<"vst1${p}", "$Vd, $Rn", - (VST1q32 addrmode6:$Rn, VecListTwoD:$Vd, pred:$p)>; -defm : VFPDT64ReqInstAlias<"vst1${p}", "$Vd, $Rn", - (VST1q64 addrmode6:$Rn, VecListTwoD:$Vd, pred:$p)>; -// with writeback, fixed stride -defm : VFPDT8ReqInstAlias<"vst1${p}", "$Vd, $Rn!", - (VST1q8wb_fixed zero_reg, addrmode6:$Rn, VecListTwoD:$Vd, pred:$p)>; -defm : VFPDT16ReqInstAlias<"vst1${p}", "$Vd, $Rn!", - (VST1q16wb_fixed zero_reg, addrmode6:$Rn, VecListTwoD:$Vd, pred:$p)>; -defm : VFPDT32ReqInstAlias<"vst1${p}", "$Vd, $Rn!", - (VST1q32wb_fixed zero_reg, addrmode6:$Rn, VecListTwoD:$Vd, pred:$p)>; -defm : VFPDT64ReqInstAlias<"vst1${p}", "$Vd, $Rn!", - (VST1q64wb_fixed zero_reg, addrmode6:$Rn, VecListTwoD:$Vd, pred:$p)>; -// with writeback, register stride -defm : VFPDT8ReqInstAlias<"vst1${p}", "$Vd, $Rn, $Rm", - (VST1q8wb_register zero_reg, addrmode6:$Rn, - rGPR:$Rm, VecListTwoD:$Vd, pred:$p)>; -defm : VFPDT16ReqInstAlias<"vst1${p}", "$Vd, $Rn, $Rm", - (VST1q16wb_register zero_reg, addrmode6:$Rn, - rGPR:$Rm, VecListTwoD:$Vd, pred:$p)>; -defm : VFPDT32ReqInstAlias<"vst1${p}", "$Vd, $Rn, $Rm", - (VST1q32wb_register zero_reg, addrmode6:$Rn, - rGPR:$Rm, VecListTwoD:$Vd, pred:$p)>; -defm : VFPDT64ReqInstAlias<"vst1${p}", "$Vd, $Rn, $Rm", - (VST1q64wb_register zero_reg, addrmode6:$Rn, - rGPR:$Rm, VecListTwoD:$Vd, pred:$p)>; - -// Load three D registers. -defm : VFPDT8ReqInstAlias<"vst1${p}", "$Vd, $Rn", - (VST1d8T addrmode6:$Rn, VecListThreeD:$Vd, pred:$p)>; -defm : VFPDT16ReqInstAlias<"vst1${p}", "$Vd, $Rn", - (VST1d16T addrmode6:$Rn, VecListThreeD:$Vd, pred:$p)>; -defm : VFPDT32ReqInstAlias<"vst1${p}", "$Vd, $Rn", - (VST1d32T addrmode6:$Rn, VecListThreeD:$Vd, pred:$p)>; -defm : VFPDT64ReqInstAlias<"vst1${p}", "$Vd, $Rn", - (VST1d64T addrmode6:$Rn, VecListThreeD:$Vd, pred:$p)>; -defm : VFPDT8ReqInstAlias<"vst1${p}", "$Vd, $Rn!", - (VST1d8Twb_fixed zero_reg, addrmode6:$Rn, VecListThreeD:$Vd, pred:$p)>; -defm : VFPDT16ReqInstAlias<"vst1${p}", "$Vd, $Rn!", - (VST1d16Twb_fixed zero_reg, addrmode6:$Rn, VecListThreeD:$Vd, pred:$p)>; -defm : VFPDT32ReqInstAlias<"vst1${p}", "$Vd, $Rn!", - (VST1d32Twb_fixed zero_reg, addrmode6:$Rn, VecListThreeD:$Vd, pred:$p)>; -defm : VFPDT64ReqInstAlias<"vst1${p}", "$Vd, $Rn!", - (VST1d64Twb_fixed zero_reg, addrmode6:$Rn, VecListThreeD:$Vd, pred:$p)>; -defm : VFPDT8ReqInstAlias<"vst1${p}", "$Vd, $Rn, $Rm", - (VST1d8Twb_register zero_reg, addrmode6:$Rn, rGPR:$Rm, - VecListThreeD:$Vd, pred:$p)>; -defm : VFPDT16ReqInstAlias<"vst1${p}", "$Vd, $Rn, $Rm", - (VST1d16Twb_register zero_reg, addrmode6:$Rn, rGPR:$Rm, - VecListThreeD:$Vd, pred:$p)>; -defm : VFPDT32ReqInstAlias<"vst1${p}", "$Vd, $Rn, $Rm", - (VST1d32Twb_register zero_reg, addrmode6:$Rn, rGPR:$Rm, - VecListThreeD:$Vd, pred:$p)>; -defm : VFPDT64ReqInstAlias<"vst1${p}", "$Vd, $Rn, $Rm", - (VST1d64Twb_register zero_reg, addrmode6:$Rn, rGPR:$Rm, - VecListThreeD:$Vd, pred:$p)>; - -// Load four D registers. -defm : VFPDT8ReqInstAlias<"vst1${p}", "$Vd, $Rn", - (VST1d8Q addrmode6:$Rn, VecListFourD:$Vd, pred:$p)>; -defm : VFPDT16ReqInstAlias<"vst1${p}", "$Vd, $Rn", - (VST1d16Q addrmode6:$Rn, VecListFourD:$Vd, pred:$p)>; -defm : VFPDT32ReqInstAlias<"vst1${p}", "$Vd, $Rn", - (VST1d32Q addrmode6:$Rn, VecListFourD:$Vd, pred:$p)>; -defm : VFPDT64ReqInstAlias<"vst1${p}", "$Vd, $Rn", - (VST1d64Q addrmode6:$Rn, VecListFourD:$Vd, pred:$p)>; -defm : VFPDT8ReqInstAlias<"vst1${p}", "$Vd, $Rn!", - (VST1d8Qwb_fixed zero_reg, addrmode6:$Rn, VecListFourD:$Vd, pred:$p)>; -defm : VFPDT16ReqInstAlias<"vst1${p}", "$Vd, $Rn!", - (VST1d16Qwb_fixed zero_reg, addrmode6:$Rn, VecListFourD:$Vd, pred:$p)>; -defm : VFPDT32ReqInstAlias<"vst1${p}", "$Vd, $Rn!", - (VST1d32Qwb_fixed zero_reg, addrmode6:$Rn, VecListFourD:$Vd, pred:$p)>; -defm : VFPDT64ReqInstAlias<"vst1${p}", "$Vd, $Rn!", - (VST1d64Qwb_fixed zero_reg, addrmode6:$Rn, VecListFourD:$Vd, pred:$p)>; -defm : VFPDT8ReqInstAlias<"vst1${p}", "$Vd, $Rn, $Rm", - (VST1d8Qwb_register zero_reg, addrmode6:$Rn, rGPR:$Rm, - VecListFourD:$Vd, pred:$p)>; -defm : VFPDT16ReqInstAlias<"vst1${p}", "$Vd, $Rn, $Rm", - (VST1d16Qwb_register zero_reg, addrmode6:$Rn, rGPR:$Rm, - VecListFourD:$Vd, pred:$p)>; -defm : VFPDT32ReqInstAlias<"vst1${p}", "$Vd, $Rn, $Rm", - (VST1d32Qwb_register zero_reg, addrmode6:$Rn, rGPR:$Rm, - VecListFourD:$Vd, pred:$p)>; -defm : VFPDT64ReqInstAlias<"vst1${p}", "$Vd, $Rn, $Rm", - (VST1d64Qwb_register zero_reg, addrmode6:$Rn, rGPR:$Rm, - VecListFourD:$Vd, pred:$p)>; - - -// VTRN instructions data type suffix aliases for more-specific types. -defm : VFPDT8ReqInstAlias <"vtrn${p}", "$Dd, $Dm", - (VTRNd8 DPR:$Dd, DPR:$Dm, pred:$p)>; -defm : VFPDT16ReqInstAlias<"vtrn${p}", "$Dd, $Dm", - (VTRNd16 DPR:$Dd, DPR:$Dm, pred:$p)>; -defm : VFPDT32ReqInstAlias<"vtrn${p}", "$Dd, $Dm", - (VTRNd32 DPR:$Dd, DPR:$Dm, pred:$p)>; - -defm : VFPDT8ReqInstAlias <"vtrn${p}", "$Qd, $Qm", - (VTRNq8 QPR:$Qd, QPR:$Qm, pred:$p)>; -defm : VFPDT16ReqInstAlias<"vtrn${p}", "$Qd, $Qm", - (VTRNq16 QPR:$Qd, QPR:$Qm, pred:$p)>; -defm : VFPDT32ReqInstAlias<"vtrn${p}", "$Qd, $Qm", - (VTRNq32 QPR:$Qd, QPR:$Qm, pred:$p)>; - -// VEXT instructions data type suffix aliases for more-specific types. -defm VEXTd : VFPDT8ReqInstAlias <"vext${p}", "$Vd, $Vn, $Vm, $index", - (VEXTd8 DPR:$Vd, DPR:$Vn, DPR:$Vm, imm0_7:$index, pred:$p)>; -defm VEXTd : VFPDT16ReqInstAlias<"vext${p}", "$Vd, $Vn, $Vm, $index", - (VEXTd16 DPR:$Vd, DPR:$Vn, DPR:$Vm, imm0_3:$index, pred:$p)>; -defm VEXTd : VFPDT32ReqInstAlias<"vext${p}", "$Vd, $Vn, $Vm, $index", - (VEXTd32 DPR:$Vd, DPR:$Vn, DPR:$Vm, imm0_1:$index, pred:$p)>; - -defm VEXTq : VFPDT8ReqInstAlias <"vext${p}", "$Vd, $Vn, $Vm, $index", - (VEXTq8 QPR:$Vd, QPR:$Vn, QPR:$Vm, imm0_15:$index, pred:$p)>; -defm VEXTq : VFPDT16ReqInstAlias<"vext${p}", "$Vd, $Vn, $Vm, $index", - (VEXTq16 QPR:$Vd, QPR:$Vn, QPR:$Vm, imm0_7:$index, pred:$p)>; -defm VEXTq : VFPDT32ReqInstAlias<"vext${p}", "$Vd, $Vn, $Vm, $index", - (VEXTq32 QPR:$Vd, QPR:$Vn, QPR:$Vm, imm0_3:$index, pred:$p)>; -defm VEXTq : VFPDT64ReqInstAlias<"vext${p}", "$Vd, $Vn, $Vm, $index", - (VEXTq64 QPR:$Vd, QPR:$Vn, QPR:$Vm, imm0_1:$index, pred:$p)>; - -// VMUL instructions data type suffix aliases for more-specific types. -def : NEONInstAlias<"vmul${p}.s16 $Dd, $Dn $Dm$lane", - (VMULslv4i16 DPR:$Dd, DPR:$Dn, DPR_8:$Dm, - VectorIndex16:$lane, pred:$p)>; -def : NEONInstAlias<"vmul${p}.s16 $Qd, $Qn, $Dm$lane", - (VMULslv8i16 QPR:$Qd, QPR:$Qn, DPR_8:$Dm, - VectorIndex16:$lane, pred:$p)>; -def : NEONInstAlias<"vmul${p}.u16 $Dd, $Dn $Dm$lane", - (VMULslv4i16 DPR:$Dd, DPR:$Dn, DPR_8:$Dm, - VectorIndex16:$lane, pred:$p)>; -def : NEONInstAlias<"vmul${p}.u16 $Qd, $Qn, $Dm$lane", - (VMULslv8i16 QPR:$Qd, QPR:$Qn, DPR_8:$Dm, - VectorIndex16:$lane, pred:$p)>; - -def : NEONInstAlias<"vmul${p}.s32 $Dd, $Dn $Dm$lane", - (VMULslv2i32 DPR:$Dd, DPR:$Dn, DPR_VFP2:$Dm, - VectorIndex32:$lane, pred:$p)>; -def : NEONInstAlias<"vmul${p}.s32 $Qd, $Qn, $Dm$lane", - (VMULslv4i32 QPR:$Qd, QPR:$Qn, DPR_VFP2:$Dm, - VectorIndex32:$lane, pred:$p)>; -def : NEONInstAlias<"vmul${p}.u32 $Dd, $Dn $Dm$lane", - (VMULslv2i32 DPR:$Dd, DPR:$Dn, DPR_VFP2:$Dm, - VectorIndex32:$lane, pred:$p)>; -def : NEONInstAlias<"vmul${p}.u32 $Qd, $Qn, $Dm$lane", - (VMULslv4i32 QPR:$Qd, QPR:$Qn, DPR_VFP2:$Dm, - VectorIndex32:$lane, pred:$p)>; - // VMUL two-operand aliases. def : NEONInstAlias<"vmul${p}.i16 $Ddn, $Dm$lane", (VMULslv4i16 DPR:$Ddn, DPR:$Ddn, DPR_8:$Dm, @@ -5645,18 +5318,6 @@ def : NEONInstAlias<"vmul${p}.i16 $Qdn, $Dm$lane", (VMULslv8i16 QPR:$Qdn, QPR:$Qdn, DPR_8:$Dm, VectorIndex16:$lane, pred:$p)>; -def : NEONInstAlias<"vmul${p}.s16 $Ddn, $Dm$lane", - (VMULslv4i16 DPR:$Ddn, DPR:$Ddn, DPR_8:$Dm, - VectorIndex16:$lane, pred:$p)>; -def : NEONInstAlias<"vmul${p}.s16 $Qdn, $Dm$lane", - (VMULslv8i16 QPR:$Qdn, QPR:$Qdn, DPR_8:$Dm, - VectorIndex16:$lane, pred:$p)>; -def : NEONInstAlias<"vmul${p}.u16 $Ddn, $Dm$lane", - (VMULslv4i16 DPR:$Ddn, DPR:$Ddn, DPR_8:$Dm, - VectorIndex16:$lane, pred:$p)>; -def : NEONInstAlias<"vmul${p}.u16 $Qdn, $Dm$lane", - (VMULslv8i16 QPR:$Qdn, QPR:$Qdn, DPR_8:$Dm, - VectorIndex16:$lane, pred:$p)>; def : NEONInstAlias<"vmul${p}.i32 $Ddn, $Dm$lane", (VMULslv2i32 DPR:$Ddn, DPR:$Ddn, DPR_VFP2:$Dm, @@ -5664,18 +5325,6 @@ def : NEONInstAlias<"vmul${p}.i32 $Qdn, $Dm$lane", (VMULslv4i32 QPR:$Qdn, QPR:$Qdn, DPR_VFP2:$Dm, VectorIndex32:$lane, pred:$p)>; -def : NEONInstAlias<"vmul${p}.s32 $Ddn, $Dm$lane", - (VMULslv2i32 DPR:$Ddn, DPR:$Ddn, DPR_VFP2:$Dm, - VectorIndex32:$lane, pred:$p)>; -def : NEONInstAlias<"vmul${p}.s32 $Qdn, $Dm$lane", - (VMULslv4i32 QPR:$Qdn, QPR:$Qdn, DPR_VFP2:$Dm, - VectorIndex32:$lane, pred:$p)>; -def : NEONInstAlias<"vmul${p}.u32 $Ddn, $Dm$lane", - (VMULslv2i32 DPR:$Ddn, DPR:$Ddn, DPR_VFP2:$Dm, - VectorIndex32:$lane, pred:$p)>; -def : NEONInstAlias<"vmul${p}.u32 $Qdn, $Dm$lane", - (VMULslv4i32 QPR:$Qdn, QPR:$Qdn, DPR_VFP2:$Dm, - VectorIndex32:$lane, pred:$p)>; def : NEONInstAlias<"vmul${p}.f32 $Ddn, $Dm$lane", (VMULslfd DPR:$Ddn, DPR:$Ddn, DPR_VFP2:$Dm, @@ -5740,3 +5389,10 @@ NEONDT32AsmPseudoInst<"vst1${p}", "$list, $addr, $Rm", (ins VecListOneDByteIndexed:$list, addrmode6:$addr, rGPR:$Rm, pred:$p)>; + +// VMOV takes an optional datatype suffix +defm : VFPDTAnyInstAlias<"vmov${p}", "$Vd, $Vm", + (VORRd DPR:$Vd, DPR:$Vm, DPR:$Vm, pred:$p)>; +defm : VFPDTAnyInstAlias<"vmov${p}", "$Vd, $Vm", + (VORRq QPR:$Vd, QPR:$Vm, QPR:$Vm, pred:$p)>; + Modified: llvm/trunk/lib/Target/ARM/ARMInstrVFP.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrVFP.td?rev=146010&r1=146009&r2=146010&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrVFP.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrVFP.td Tue Dec 6 19:50:36 2011 @@ -1164,14 +1164,14 @@ def : VFP2InstAlias<"fmstat${p}", (FMSTAT pred:$p)>; // VLDR/VSTR accept an optional type suffix. -defm : VFPDT32InstAlias<"vldr${p}", "$Sd, $addr", - (VLDRS SPR:$Sd, addrmode5:$addr, pred:$p)>; -defm : VFPDT32InstAlias<"vstr${p}", "$Sd, $addr", - (VSTRS SPR:$Sd, addrmode5:$addr, pred:$p)>; -defm : VFPDT64InstAlias<"vldr${p}", "$Dd, $addr", - (VLDRD DPR:$Dd, addrmode5:$addr, pred:$p)>; -defm : VFPDT64InstAlias<"vstr${p}", "$Dd, $addr", - (VSTRD DPR:$Dd, addrmode5:$addr, pred:$p)>; +def : VFP2InstAlias<"vldr${p}.32 $Sd, $addr", + (VLDRS SPR:$Sd, addrmode5:$addr, pred:$p)>; +def : VFP2InstAlias<"vstr${p}.32 $Sd, $addr", + (VSTRS SPR:$Sd, addrmode5:$addr, pred:$p)>; +def : VFP2InstAlias<"vldr${p}.64 $Dd, $addr", + (VLDRD DPR:$Dd, addrmode5:$addr, pred:$p)>; +def : VFP2InstAlias<"vstr${p}.64 $Dd, $addr", + (VSTRD DPR:$Dd, addrmode5:$addr, pred:$p)>; // VMUL has a two-operand form (implied destination operand) def : VFP2InstAlias<"vmul${p}.f64 $Dn, $Dm", From gohman at apple.com Tue Dec 6 20:17:06 2011 From: gohman at apple.com (Dan Gohman) Date: Tue, 06 Dec 2011 18:17:06 -0800 Subject: [llvm-commits] [llvm] r145913 - /llvm/trunk/docs/LangRef.html In-Reply-To: References: <20111206033558.C5B0A2A6C12C@llvm.org> Message-ID: <90770681-BDF1-41D9-BAC1-248EB1830777@apple.com> On Dec 5, 2011, at 8:21 PM, Eli Friedman wrote: > On Mon, Dec 5, 2011 at 7:35 PM, Dan Gohman wrote: >> Author: djg >> Date: Mon Dec 5 21:35:58 2011 >> New Revision: 145913 >> >> URL: http://llvm.org/viewvc/llvm-project?rev=145913&view=rev >> Log: >> Fix a subtle semantic issue with poison values that came up in >> recent discussions. Poison can't make every value that depends on >> it act in maximally undefined ways, because the optimizer may still >> hoist code following the usual rules for undef. Make Poison invoke >> its full undefined behavior only when it reaches an instruction with >> externally visible side effects. >> >> Modified: >> llvm/trunk/docs/LangRef.html >> >> Modified: llvm/trunk/docs/LangRef.html >> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/LangRef.html?rev=145913&r1=145912&r2=145913&view=diff >> ============================================================================== >> --- llvm/trunk/docs/LangRef.html (original) >> +++ llvm/trunk/docs/LangRef.html Mon Dec 5 21:35:58 2011 >> @@ -2512,10 +2512,9 @@ >>
      >> >>

      Poison values are similar to undef values, however >> - instead of representing an unspecified bit pattern, they represent the >> - fact that an instruction or constant expression which cannot evoke side >> - effects has nevertheless detected a condition which results in undefined >> - behavior.

      >> + they also represent the fact that an instruction or constant expression which >> + cannot evoke side effects has nevertheless detected a condition which results >> + in undefined behavior.

      >> >>

      There is currently no way of representing a poison value in the IR; they >> only exist when produced by operations such as >> @@ -2572,22 +2571,21 @@ >> >> >> >> -

      Whenever a poison value is generated, all values which depend on it evaluate >> - to poison. If they have side effects, they evoke their side effects as if each >> - operand with a poison value were undef. If they have externally-visible side >> - effects, the behavior is undefined.

      >> +

      Poison Values have the same behavior as undef values, >> + with the additional affect that any instruction which has a dependence >> + on a poison value has undefined behavior.

      >> >>

      Here are some examples:

      >> >> 
      >>  entry:
>>   %poison = sub nuw i32 0, 1           ; Results in a poison value.
>> -  %still_poison = and i32 %poison, 0   ; Whereas (and i32 undef, 0) would return 0.
>> +  %still_poison = and i32 %poison, 0   ; 0, but also poison.
>>   %poison_yet_again = getelementptr i32* @h, i32 %still_poison
>> -  store i32 0, i32* %poison_yet_again  ; undefined behavior
>> +  store i32 0, i32* %poison_yet_again  ; memory at @h[0] is poisoned
> 
> This change can't be right... storing to a poisoned address has to be
> undefined behavior in any sane model.


It's intentional. %still_poison is the result of anding with 0,
so it has to behave as if it were all zeros, for SimplifyDemandedBits
reasons.

Dan


From gohman at apple.com  Tue Dec  6 20:26:10 2011
From: gohman at apple.com (Dan Gohman)
Date: Tue, 06 Dec 2011 18:26:10 -0800
Subject: [llvm-commits] [LLVM, loop-unswitch,
 bugfix for #11429] Wrong behaviour for switches.
In-Reply-To: <4EDCC136.1040903@narod.ru>
References: <4ECF4A5A.9030607@narod.ru> <4ED36D99.1080306@narod.ru>
	<4ED51EEC.6050000@narod.ru> <4ED749D0.8030101@narod.ru>
	<4ED88CDF.2020104@narod.ru>
	
	<4EDCC136.1040903@narod.ru>
Message-ID: <566DBA1B-7099-44E0-B2EB-3413A054F5E3@apple.com>


On Dec 5, 2011, at 5:03 AM, Stepan Dyatkovskiy wrote:

> Hi Dan. This bug is described in details (with examples) here:
> http://llvm.org/bugs/show_bug.cgi?id=11429
> 
> Regarding to your questions..
> 
>> It's even possible that this bug is
>> accidentally helping the code by preventing it from unswitching too
>> much in the presence of switches.
>> Do you have an idea on what impact
>> this patch has on code size, and performance, in general?
> 
> Happily this bug helps to keep the code size small. But LoopUnswitch::UnswitchIfProfitable method already controls the produced code size. Please, see LoopUnswitch.cpp, string #446 for more details. I think that if we need to improve the "restrictioning" of produced code size we need to implement this improvement instead of keeping some strange code.

This sounds good. How sure are you that the existing size heuristics
are actually kicking in for the new unrollings? I don't have a reason
to suspect a bug, other than that you're asking code to work in cases
that it hasn't before.

> 
> About impact on code size.
> For switch with N cases (+ 1 default) we got N new loops. If you wish I can present the .ll code that should be produced after optimization.
> 
> Impact on performance.
> The main purpose of this optimization is to move out of loop the switches. Each unswitched case increases the performance.

Each unswitched case has the potential to increase performance,
if conditions are favorable. But if code size is increased, there's
also the possibility of decreased performance. But I think you're
right, the existing throttle ought to handle that. If you can confirm
that that's working as expected, it should be fine.

> 
> About releaseMemory and CloneUnswitchedVals.
> This methods the part of unswitch info cloning for new loops. It is also described in bug #11429.
> 
> > CloneUnswitchedVals doesn't actually need to iterate over the
> > instructions in the block to find the SwitchInst. If there's a
> > SwitchInst present, it'll be the Terminator instruction.
> OK. You're right. Please find the fixed patch.

Thanks,

Dan


From eli.friedman at gmail.com  Tue Dec  6 20:41:13 2011
From: eli.friedman at gmail.com (Eli Friedman)
Date: Tue, 6 Dec 2011 18:41:13 -0800
Subject: [llvm-commits] [llvm] r145913 - /llvm/trunk/docs/LangRef.html
In-Reply-To: <90770681-BDF1-41D9-BAC1-248EB1830777@apple.com>
References: <20111206033558.C5B0A2A6C12C@llvm.org>
	
	<90770681-BDF1-41D9-BAC1-248EB1830777@apple.com>
Message-ID: 

On Tue, Dec 6, 2011 at 6:17 PM, Dan Gohman  wrote:
> On Dec 5, 2011, at 8:21 PM, Eli Friedman wrote:
>
>> On Mon, Dec 5, 2011 at 7:35 PM, Dan Gohman  wrote:
>>> Author: djg
>>> Date: Mon Dec ?5 21:35:58 2011
>>> New Revision: 145913
>>>
>>> URL: http://llvm.org/viewvc/llvm-project?rev=145913&view=rev
>>> Log:
>>> Fix a subtle semantic issue with poison values that came up in
>>> recent discussions. Poison can't make every value that depends on
>>> it act in maximally undefined ways, because the optimizer may still
>>> hoist code following the usual rules for undef. Make Poison invoke
>>> its full undefined behavior only when it reaches an instruction with
>>> externally visible side effects.
>>>
>>> Modified:
>>> ? ?llvm/trunk/docs/LangRef.html
>>>
>>> Modified: llvm/trunk/docs/LangRef.html
>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/LangRef.html?rev=145913&r1=145912&r2=145913&view=diff
>>> ==============================================================================
>>> --- llvm/trunk/docs/LangRef.html (original)
>>> +++ llvm/trunk/docs/LangRef.html Mon Dec ?5 21:35:58 2011
>>> @@ -2512,10 +2512,9 @@
>>> ?
      
>>>
>>> ?
      Poison values are similar to undef values, however
>>> - ? instead of representing an unspecified bit pattern, they represent the
>>> - ? fact that an instruction or constant expression which cannot evoke side
>>> - ? effects has nevertheless detected a condition which results in undefined
>>> - ? behavior.
      
>>> + ? they also represent the fact that an instruction or constant expression which
>>> + ? cannot evoke side effects has nevertheless detected a condition which results
>>> + ? in undefined behavior.
      
>>>
>>> ?
      There is currently no way of representing a poison value in the IR; they
>>> ? ?only exist when produced by operations such as
>>> @@ -2572,22 +2571,21 @@
>>>
>>> ?
>>>
>>> -
      Whenever a poison value is generated, all values which depend on it evaluate
>>> - ? to poison. If they have side effects, they evoke their side effects as if each
>>> - ? operand with a poison value were undef. If they have externally-visible side
>>> - ? effects, the behavior is undefined.
      
>>> +
      Poison Values have the same behavior as undef values,
>>> + ? with the additional affect that any instruction which has a dependence
>>> + ? on a poison value has undefined behavior.
      
>>>
>>> ?
      Here are some examples:
      
>>>
>>> ?
      >>> ?entry:
>>> ? %poison = sub nuw i32 0, 1 ? ? ? ? ? ; Results in a poison value.
>>> - ?%still_poison = and i32 %poison, 0 ? ; Whereas (and i32 undef, 0) would return 0.
>>> + ?%still_poison = and i32 %poison, 0 ? ; 0, but also poison.
>>> ? %poison_yet_again = getelementptr i32* @h, i32 %still_poison
>>> - ?store i32 0, i32* %poison_yet_again ?; undefined behavior
>>> + ?store i32 0, i32* %poison_yet_again ?; memory at @h[0] is poisoned
>>
>> This change can't be right... storing to a poisoned address has to be
>> undefined behavior in any sane model.
>
>
> It's intentional. %still_poison is the result of anding with 0,
> so it has to behave as if it were all zeros, for SimplifyDemandedBits
> reasons.

Okay... I'm not sure the model is quite right, but that's correct in your model.

-Eli


From eli.friedman at gmail.com  Tue Dec  6 21:55:52 2011
From: eli.friedman at gmail.com (Eli Friedman)
Date: Wed, 07 Dec 2011 03:55:52 -0000
Subject: [llvm-commits] [llvm] r146015 -
	/llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
Message-ID: <20111207035553.10F8F1BE003@llvm.org>

Author: efriedma
Date: Tue Dec  6 21:55:52 2011
New Revision: 146015

URL: http://llvm.org/viewvc/llvm-project?rev=146015&view=rev
Log:
Zap unnecessary isIntDivCheap() check.  PR11485.  No testcase because this doesn't affect any in-tree target.


Modified:
    llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp?rev=146015&r1=146014&r2=146015&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Tue Dec  6 21:55:52 2011
@@ -1777,7 +1777,7 @@
                          N0, N1);
   }
   // fold (sdiv X, pow2) -> simple ops after legalize
-  if (N1C && !N1C->isNullValue() && !TLI.isIntDivCheap() &&
+  if (N1C && !N1C->isNullValue() &&
       (N1C->getAPIntValue().isPowerOf2() ||
        (-N1C->getAPIntValue()).isPowerOf2())) {
     // If dividing by powers of two is cheap, then don't perform the following



From eli.friedman at gmail.com  Tue Dec  6 22:09:20 2011
From: eli.friedman at gmail.com (Eli Friedman)
Date: Tue, 6 Dec 2011 20:09:20 -0800
Subject: [llvm-commits] [LLVM,
 SelectionDAG] fix for #9905: Failure in code selection for llvm
 intrinsics sqrt/exp
In-Reply-To: <4EDDE47C.4000905@narod.ru>
References: <4ED74593.2030003@narod.ru> <4ED9D140.2070504@narod.ru>
	<4EDCC1A2.5010500@narod.ru>
	
	<4EDDE0E1.5060200@narod.ru> <4EDDE47C.4000905@narod.ru>
Message-ID: 

On Tue, Dec 6, 2011 at 1:46 AM, Stepan Dyatkovskiy  wrote:
> Sorry for previous post. Forgot to remove extra newlines at the end of file.
> Fixed file is attached here.

Better... but please try to make it less sensitive to register
allocation and scheduler choices.

-Eli

>
> Thanks.
> -Stepan.
>
>
> Stepan Dyatkovskiy wrote:
>>
>> OK. Please look at reworked regression test patch in attachment.
>>
>> -Stepan.
>>
>> Eli Friedman wrote:
>>>
>>> The code changes look fine. Please put all the FileCheck tests into
>>> one file, and only use CHECK lines for the most important pieces
>>> (specifically, that we call sinf etc.).
>>>
>>> -Eli
>>>
>>> On Mon, Dec 5, 2011 at 5:05 AM, Stepan Dyatkovskiy
>>> wrote:
>>>>
>>>> ping.
>>>>
>>>> -Stepan.
>>>>
>>>> Stepan Dyatkovskiy wrote:
>>>>>
>>>>> ping.
>>>>>
>>>>> -Stepan
>>>>>
>>>>> Stepan Dyatkovskiy wrote:
>>>>>>
>>>>>> Hi all. Please find the patch and regression tests in attachment for
>>>>>> review.
>>>>>> This patch for ARM. It fixes selection for several instructions that
>>>>>> works with v4f32 arguments: FSQRT, FSIN, FCOS, FPOWI, FPOW, FLOG,
>>>>>> FLOG2,
>>>>>> FLOG10, FEXP, FEXP2.
>>>>>> I'm still worrying about FCOPYSIGN, FNEG, FABS, FCEIL, FTRUNC, FRINT,
>>>>>> FNEARBYINT, FFLOOR. I could not found a way to add this instructions
>>>>>> with v2f32 argument to DAG. It seems that it is impossible in ToT. So
>>>>>> these instructions was not fixed.
>>>>>>
>>>>>> -Stepan.
>>>>>>
>>>>>>
>>>>>> _______________________________________________
>>>>>> llvm-commits mailing list
>>>>>> llvm-commits at cs.uiuc.edu
>>>>>> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
>>>>>
>>>>>
>>>>> _______________________________________________
>>>>> llvm-commits mailing list
>>>>> llvm-commits at cs.uiuc.edu
>>>>> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
>>>>
>>>>
>>>> _______________________________________________
>>>> llvm-commits mailing list
>>>> llvm-commits at cs.uiuc.edu
>>>> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
>>
>>
>>
>>
>> _______________________________________________
>> llvm-commits mailing list
>> llvm-commits at cs.uiuc.edu
>> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
>
>

From stoklund at 2pi.dk  Tue Dec  6 22:17:35 2011
From: stoklund at 2pi.dk (Jakob Stoklund Olesen)
Date: Wed, 07 Dec 2011 04:17:35 -0000
Subject: [llvm-commits] [llvm] r146017 -
	/llvm/trunk/lib/Target/ARM/ARMConstantIslandPass.cpp
Message-ID: <20111207041735.F15051BE003@llvm.org>

Author: stoklund
Date: Tue Dec  6 22:17:35 2011
New Revision: 146017

URL: http://llvm.org/viewvc/llvm-project?rev=146017&view=rev
Log:
Compute some alignment information for each basic block.

These fields are not used for anything yet.

Modified:
    llvm/trunk/lib/Target/ARM/ARMConstantIslandPass.cpp

Modified: llvm/trunk/lib/Target/ARM/ARMConstantIslandPass.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMConstantIslandPass.cpp?rev=146017&r1=146016&r2=146017&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMConstantIslandPass.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMConstantIslandPass.cpp Tue Dec  6 22:17:35 2011
@@ -82,8 +82,17 @@
       /// will both be ==2 mod 4).
       unsigned Size;
 
-      BasicBlockInfo() : Offset(0), Size(0) {}
-      BasicBlockInfo(unsigned o, unsigned s) : Offset(o), Size(s) {}
+      /// Unalign - When non-zero, the block contains instructions (inline asm)
+      /// of unknown size.  The real size may be smaller than Size bytes by a
+      /// multiple of 1 << Unalign.
+      uint8_t Unalign;
+
+      /// PostAlign - When non-zero, the block terminator contains a .align
+      /// directive, so the end of the block is aligned to 1 << PostAlign
+      /// bytes.
+      uint8_t PostAlign;
+
+      BasicBlockInfo() : Offset(0), Size(0), Unalign(0), PostAlign(0) {}
 
       /// Compute the offset immediately following this block.
       unsigned postOffset() const { return Offset + Size; }
@@ -234,6 +243,7 @@
     MachineBasicBlock *AdjustJTTargetBlockForward(MachineBasicBlock *BB,
                                                   MachineBasicBlock *JTBB);
 
+    void ComputeBlockSize(const MachineBasicBlock *MBB);
     unsigned GetOffsetOf(MachineInstr *MI) const;
     void dumpBBs();
     void verify(MachineFunction &MF);
@@ -507,11 +517,16 @@
         HasInlineAsm = true;
   }
 
+  BBInfo.clear();
+  BBInfo.resize(MF.getNumBlockIDs());
+
   // Now go back through the instructions and build up our data structures.
   unsigned Offset = 0;
   for (MachineFunction::iterator MBBI = MF.begin(), E = MF.end();
        MBBI != E; ++MBBI) {
     MachineBasicBlock &MBB = *MBBI;
+    BasicBlockInfo &BBI = BBInfo[MBB.getNumber()];
+    BBI.Offset = Offset;
 
     // If this block doesn't fall through into the next MBB, then this is
     // 'water' that a constant pool island could be placed.
@@ -526,6 +541,11 @@
       // Add instruction size to MBBSize.
       MBBSize += TII->GetInstSizeInBytes(I);
 
+      // For inline asm, GetInstSizeInBytes returns a conservative estimate.
+      // The actual size may be smaller, but still a multiple of the instr size.
+      if (I->isInlineAsm())
+        BBI.Unalign = isThumb ? 1 : 2;
+
       int Opc = I->getOpcode();
       if (I->getDesc().isBranch()) {
         bool isCond = false;
@@ -543,6 +563,7 @@
           // is aligned.  That is held in Offset+MBBSize, which already has
           // 2 added in for the size of the mov pc instruction.
           MF.EnsureAlignment(2U);
+          BBI.PostAlign = 2;
           if ((Offset+MBBSize)%4 != 0 || HasInlineAsm)
             // FIXME: Add a pseudo ALIGN instruction instead.
             MBBSize += 2;           // padding
@@ -673,11 +694,33 @@
         ((Offset%4) != 0 || HasInlineAsm))
       MBBSize += 2;
 
-    BBInfo.push_back(BasicBlockInfo(Offset, MBBSize));
+    BBI.Size = MBBSize;
     Offset += MBBSize;
   }
 }
 
+/// ComputeBlockSize - Compute the size and some alignment information for MBB.
+/// This function updates BBInfo directly.
+void ARMConstantIslands::ComputeBlockSize(const MachineBasicBlock *MBB) {
+  BasicBlockInfo &BBI = BBInfo[MBB->getNumber()];
+  BBI.Size = 0;
+  BBI.Unalign = 0;
+  BBI.PostAlign = 0;
+
+  for (MachineBasicBlock::const_iterator I = MBB->begin(), E = MBB->end();
+       I != E; ++I) {
+    BBI.Size += TII->GetInstSizeInBytes(I);
+    // For inline asm, GetInstSizeInBytes returns a conservative estimate.
+    // The actual size may be smaller, but still a multiple of the instr size.
+    if (I->isInlineAsm())
+      BBI.Unalign = isThumb ? 1 : 2;
+  }
+
+  // tBR_JTr contains a .align 2 directive.
+  if (!MBB->empty() && MBB->back().getOpcode() == ARM::tBR_JTr)
+    BBI.PostAlign = 2;
+}
+
 /// GetOffsetOf - Return the current offset of the specified machine instruction
 /// from the start of the function.  This offset changes as stuff is moved
 /// around inside the function.
@@ -798,23 +841,14 @@
   // the new jump we added.  (It should be possible to do this without
   // recounting everything, but it's very confusing, and this is rarely
   // executed.)
-  unsigned OrigBBSize = 0;
-  for (MachineBasicBlock::iterator I = OrigBB->begin(), E = OrigBB->end();
-       I != E; ++I)
-    OrigBBSize += TII->GetInstSizeInBytes(I);
-  BBInfo[OrigBBI].Size = OrigBBSize;
+  ComputeBlockSize(OrigBB);
 
   // ...and adjust BBOffsets for NewBB accordingly.
   BBInfo[NewBBI].Offset = BBInfo[OrigBBI].postOffset();
 
   // Figure out how large the NewMBB is.  As the second half of the original
   // block, it may contain a tablejump.
-  unsigned NewBBSize = 0;
-  for (MachineBasicBlock::iterator I = NewBB->begin(), E = NewBB->end();
-       I != E; ++I)
-    NewBBSize += TII->GetInstSizeInBytes(I);
-  // Set the size of NewBB in BBSizes.  It does not include any padding now.
-  BBInfo[NewBBI].Size = NewBBSize;
+  ComputeBlockSize(NewBB);
 
   MachineInstr* ThumbJTMI = prior(NewBB->end());
   if (ThumbJTMI->getOpcode() == ARM::tBR_JTr) {



From stoklund at 2pi.dk  Tue Dec  6 23:17:30 2011
From: stoklund at 2pi.dk (Jakob Stoklund Olesen)
Date: Wed, 07 Dec 2011 05:17:30 -0000
Subject: [llvm-commits] [llvm] r146018 -
	/llvm/trunk/lib/Target/ARM/ARMConstantIslandPass.cpp
Message-ID: <20111207051730.5C6A11BE003@llvm.org>

Author: stoklund
Date: Tue Dec  6 23:17:30 2011
New Revision: 146018

URL: http://llvm.org/viewvc/llvm-project?rev=146018&view=rev
Log:
Eliminate delta argument from AdjustBBOffsetsAfter.

The block offset can be computed from the previous block. That is more
robust than keeping track of a delta.

Eliminate one redundant AdjustBBOffsetsAfter call.

Modified:
    llvm/trunk/lib/Target/ARM/ARMConstantIslandPass.cpp

Modified: llvm/trunk/lib/Target/ARM/ARMConstantIslandPass.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMConstantIslandPass.cpp?rev=146018&r1=146017&r2=146018&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMConstantIslandPass.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMConstantIslandPass.cpp Tue Dec  6 23:17:30 2011
@@ -215,7 +215,7 @@
                              const std::vector &CPEMIs);
     MachineBasicBlock *SplitBlockBeforeInstr(MachineInstr *MI);
     void UpdateForInsertedWaterBlock(MachineBasicBlock *NewBB);
-    void AdjustBBOffsetsAfter(MachineBasicBlock *BB, int delta);
+    void AdjustBBOffsetsAfter(MachineBasicBlock *BB);
     bool DecrementOldEntry(unsigned CPI, MachineInstr* CPEMI);
     int LookForExistingCPEntry(CPUser& U, unsigned UserOffset);
     bool LookForWater(CPUser&U, unsigned UserOffset, water_iterator &WaterIter);
@@ -869,7 +869,7 @@
 
   // All BBOffsets following these blocks must be modified.
   if (delta)
-    AdjustBBOffsetsAfter(NewBB, delta);
+    AdjustBBOffsetsAfter(NewBB);
 
   return NewBB;
 }
@@ -967,12 +967,13 @@
 }
 #endif // NDEBUG
 
-void ARMConstantIslands::AdjustBBOffsetsAfter(MachineBasicBlock *BB,
-                                              int delta) {
+void ARMConstantIslands::AdjustBBOffsetsAfter(MachineBasicBlock *BB) {
   MachineFunction::iterator MBBI = BB; MBBI = llvm::next(MBBI);
   for(unsigned i = BB->getNumber()+1, e = BB->getParent()->getNumBlockIDs();
       i < e; ++i) {
-    BBInfo[i].Offset += delta;
+    unsigned OldOffset = BBInfo[i].Offset;
+    BBInfo[i].Offset = BBInfo[i-1].postOffset();
+    int delta = BBInfo[i].Offset - OldOffset;
     // If some existing blocks have padding, adjust the padding as needed, a
     // bit tricky.  delta can be negative so don't use % on that.
     if (!isThumb)
@@ -981,7 +982,6 @@
     if (!MBB->empty() && !HasInlineAsm) {
       // Constant pool entries require padding.
       if (MBB->begin()->getOpcode() == ARM::CONSTPOOL_ENTRY) {
-        unsigned OldOffset = BBInfo[i].Offset - delta;
         if ((OldOffset%4) == 0 && (BBInfo[i].Offset%4) != 0) {
           // add new padding
           BBInfo[i].Size += 2;
@@ -1005,15 +1005,11 @@
         if ((OldMIOffset%4) == 0 && (NewMIOffset%4) != 0) {
           // remove existing padding
           BBInfo[i].Size -= 2;
-          delta -= 2;
         } else if ((OldMIOffset%4) != 0 && (NewMIOffset%4) == 0) {
           // add new padding
           BBInfo[i].Size += 2;
-          delta += 2;
         }
       }
-      if (delta==0)
-        return;
     }
     MBBI = llvm::next(MBBI);
   }
@@ -1197,7 +1193,7 @@
                           MaxDisp, false, UncondBr));
     int delta = isThumb1 ? 2 : 4;
     BBInfo[UserMBB->getNumber()].Size += delta;
-    AdjustBBOffsetsAfter(UserMBB, delta);
+    AdjustBBOffsetsAfter(UserMBB);
   } else {
     // What a big block.  Find a place within the block to split it.
     // This is a little tricky on Thumb1 since instructions are 2 bytes
@@ -1361,7 +1357,7 @@
     Size += 2;
   // Increase the size of the island block to account for the new entry.
   BBInfo[NewIsland->getNumber()].Size += Size;
-  AdjustBBOffsetsAfter(NewIsland, Size);
+  AdjustBBOffsetsAfter(NewIsland);
 
   // Finally, change the CPI in the instruction operand to be ID.
   for (unsigned i = 0, e = UserMI->getNumOperands(); i != e; ++i)
@@ -1397,7 +1393,7 @@
     // This block no longer needs to be aligned. .
     CPEBB->setAlignment(0);
   }
-  AdjustBBOffsetsAfter(CPEBB, -Size);
+  AdjustBBOffsetsAfter(CPEBB);
   // An island has only one predecessor BB and one successor BB. Check if
   // this BB's predecessor jumps directly to this BB's successor. This
   // shouldn't happen currently.
@@ -1477,7 +1473,7 @@
   Br.MaxDisp = (1 << 21) * 2;
   MI->setDesc(TII->get(ARM::tBfar));
   BBInfo[MBB->getNumber()].Size += 2;
-  AdjustBBOffsetsAfter(MBB, 2);
+  AdjustBBOffsetsAfter(MBB);
   HasFarJump = true;
   ++NumUBrFixed;
 
@@ -1541,8 +1537,6 @@
     // branch to the destination.
     int delta = TII->GetInstSizeInBytes(&MBB->back());
     BBInfo[MBB->getNumber()].Size -= delta;
-    MachineBasicBlock* SplitBB = llvm::next(MachineFunction::iterator(MBB));
-    AdjustBBOffsetsAfter(SplitBB, -delta);
     MBB->back().eraseFromParent();
     // BBInfo[SplitBB].Offset is wrong temporarily, fixed below
   }
@@ -1570,10 +1564,7 @@
   // Remove the old conditional branch.  It may or may not still be in MBB.
   BBInfo[MI->getParent()->getNumber()].Size -= TII->GetInstSizeInBytes(MI);
   MI->eraseFromParent();
-
-  // The net size change is an addition of one unconditional branch.
-  int delta = TII->GetInstSizeInBytes(&MBB->back());
-  AdjustBBOffsetsAfter(MBB, delta);
+  AdjustBBOffsetsAfter(MBB);
   return true;
 }
 
@@ -1637,7 +1628,7 @@
       U.MI->setDesc(TII->get(NewOpc));
       MachineBasicBlock *MBB = U.MI->getParent();
       BBInfo[MBB->getNumber()].Size -= 2;
-      AdjustBBOffsetsAfter(MBB, -2);
+      AdjustBBOffsetsAfter(MBB);
       ++NumT2CPShrunk;
       MadeChange = true;
     }
@@ -1678,7 +1669,7 @@
         Br.MI->setDesc(TII->get(NewOpc));
         MachineBasicBlock *MBB = Br.MI->getParent();
         BBInfo[MBB->getNumber()].Size -= 2;
-        AdjustBBOffsetsAfter(MBB, -2);
+        AdjustBBOffsetsAfter(MBB);
         ++NumT2BrShrunk;
         MadeChange = true;
       }
@@ -1720,7 +1711,7 @@
             Br.MI->eraseFromParent();
             Br.MI = NewBR;
             BBInfo[MBB->getNumber()].Size -= 2;
-            AdjustBBOffsetsAfter(MBB, -2);
+            AdjustBBOffsetsAfter(MBB);
             ++NumCBZ;
             MadeChange = true;
           }
@@ -1847,7 +1838,7 @@
 
       int delta = OrigSize - NewSize;
       BBInfo[MBB->getNumber()].Size -= delta;
-      AdjustBBOffsetsAfter(MBB, -delta);
+      AdjustBBOffsetsAfter(MBB);
 
       ++NumTBs;
       MadeChange = true;



From hfinkel at anl.gov  Wed Dec  7 00:32:37 2011
From: hfinkel at anl.gov (Hal Finkel)
Date: Wed, 07 Dec 2011 06:32:37 -0000
Subject: [llvm-commits] [llvm] r146021 -
	/llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.cpp
Message-ID: <20111207063238.027071BE003@llvm.org>

Author: hfinkel
Date: Wed Dec  7 00:32:37 2011
New Revision: 146021

URL: http://llvm.org/viewvc/llvm-project?rev=146021&view=rev
Log:
64-bit LR8 load should use X11 not R11

Modified:
    llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.cpp

Modified: llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.cpp?rev=146021&r1=146020&r2=146021&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.cpp Wed Dec  7 00:32:37 2011
@@ -377,7 +377,7 @@
                                          FrameIdx));
     } else {
       // FIXME: this spills LR immediately to memory in one step.  To do this,
-      // we use R11, which we know cannot be used in the prolog/epilog.  This is
+      // we use X11, which we know cannot be used in the prolog/epilog.  This is
       // a hack.
       NewMIs.push_back(BuildMI(MF, DL, get(PPC::MFLR8), PPC::X11));
       NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STD))
@@ -531,8 +531,8 @@
                                          FrameIdx));
     } else {
       NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LD),
-                                                 PPC::R11), FrameIdx));
-      NewMIs.push_back(BuildMI(MF, DL, get(PPC::MTLR8)).addReg(PPC::R11));
+                                                 PPC::X11), FrameIdx));
+      NewMIs.push_back(BuildMI(MF, DL, get(PPC::MTLR8)).addReg(PPC::X11));
     }
   } else if (PPC::F8RCRegisterClass->hasSubClassEq(RC)) {
     NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LFD), DestReg),



From hfinkel at anl.gov  Wed Dec  7 00:33:58 2011
From: hfinkel at anl.gov (Hal Finkel)
Date: Wed, 07 Dec 2011 06:33:58 -0000
Subject: [llvm-commits] [llvm] r146022 -
	/llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.td
Message-ID: <20111207063358.1A6E71BE003@llvm.org>

Author: hfinkel
Date: Wed Dec  7 00:33:57 2011
New Revision: 146022

URL: http://llvm.org/viewvc/llvm-project?rev=146022&view=rev
Log:
set mayStore and mayLoad on CR pseudos

Modified:
    llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.td

Modified: llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.td?rev=146022&r1=146021&r2=146022&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.td (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.td Wed Dec  7 00:33:57 2011
@@ -399,12 +399,14 @@
 
 // SPILL_CR - Indicate that we're dumping the CR register, so we'll need to
 // scavenge a register for it.
-def SPILL_CR : Pseudo<(outs), (ins GPRC:$cond, memri:$F),
+let mayStore = 1 in
+def SPILL_CR : Pseudo<(outs), (ins CRRC:$cond, memri:$F),
                      "", []>;
 
 // RESTORE_CR - Indicate that we're restoring the CR register (previously
 // spilled), so we'll need to scavenge a register for it.
-def RESTORE_CR : Pseudo<(outs GPRC:$cond), (ins memri:$F),
+let mayLoad = 1 in
+def RESTORE_CR : Pseudo<(outs CRRC:$cond), (ins memri:$F),
                      "", []>;
 
 let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7 in {



From hfinkel at anl.gov  Wed Dec  7 00:34:02 2011
From: hfinkel at anl.gov (Hal Finkel)
Date: Wed, 07 Dec 2011 06:34:02 -0000
Subject: [llvm-commits] [llvm] r146023 -
	/llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.cpp
Message-ID: <20111207063402.76ABA1BE003@llvm.org>

Author: hfinkel
Date: Wed Dec  7 00:34:02 2011
New Revision: 146023

URL: http://llvm.org/viewvc/llvm-project?rev=146023&view=rev
Log:
make base register selection used in eliminateFrameIndex 64-bit clean

Modified:
    llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.cpp

Modified: llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.cpp?rev=146023&r1=146022&r2=146023&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.cpp (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.cpp Wed Dec  7 00:34:02 2011
@@ -239,7 +239,7 @@
     if (Subtarget.isSVR4ABI()) {
       Reserved.set(PPC::X2);
     }
-    // Reserve R2 on Darwin to hack around the problem of save/restore of CR
+    // Reserve X2 on Darwin to hack around the problem of save/restore of CR
     // when the stack frame is too big to address directly; we need two regs.
     // This is a hack.
     if (Subtarget.isDarwinABI()) {
@@ -589,8 +589,11 @@
   }
 
   // Replace the FrameIndex with base register with GPR1 (SP) or GPR31 (FP).
+
+  bool is64Bit = Subtarget.isPPC64();
   MI.getOperand(FIOperandNo).ChangeToRegister(TFI->hasFP(MF) ?
-                                              PPC::R31 : PPC::R1,
+                                              (is64Bit ? PPC::X31 : PPC::R31) :
+                                                (is64Bit ? PPC::X1 : PPC::R1),
                                               false);
 
   // Figure out if the offset in the instruction is shifted right two bits. This
@@ -638,15 +641,17 @@
   // offset in.
 
   unsigned SReg;
-  if (requiresRegisterScavenging(MF))
-    SReg = findScratchRegister(II, RS, &PPC::GPRCRegClass, SPAdj);
-  else
-    SReg = PPC::R0;
+  if (requiresRegisterScavenging(MF)) {
+    const TargetRegisterClass *G8RC = &PPC::G8RCRegClass;
+    const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
+    SReg = findScratchRegister(II, RS, is64Bit ? G8RC : GPRC, SPAdj);
+  } else
+    SReg = is64Bit ? PPC::X0 : PPC::R0;
 
   // Insert a set of rA with the full offset value before the ld, st, or add
-  BuildMI(MBB, II, dl, TII.get(PPC::LIS), SReg)
+  BuildMI(MBB, II, dl, TII.get(is64Bit ? PPC::LIS8 : PPC::LIS), SReg)
     .addImm(Offset >> 16);
-  BuildMI(MBB, II, dl, TII.get(PPC::ORI), SReg)
+  BuildMI(MBB, II, dl, TII.get(is64Bit ? PPC::ORI8 : PPC::ORI), SReg)
     .addReg(SReg, RegState::Kill)
     .addImm(Offset);
 



From hfinkel at anl.gov  Wed Dec  7 00:34:07 2011
From: hfinkel at anl.gov (Hal Finkel)
Date: Wed, 07 Dec 2011 06:34:07 -0000
Subject: [llvm-commits] [llvm] r146024 - in /llvm/trunk/lib/Target/PowerPC:
 PPCAsmPrinter.cpp PPCCodeEmitter.cpp PPCInstr64Bit.td PPCInstrInfo.cpp
 PPCInstrInfo.td PPCRegisterInfo.cpp
Message-ID: <20111207063407.5E53C1BE003@llvm.org>

Author: hfinkel
Date: Wed Dec  7 00:34:06 2011
New Revision: 146024

URL: http://llvm.org/viewvc/llvm-project?rev=146024&view=rev
Log:
make CR spill and restore 64-bit clean (no functional change), and fix some other problems found with -verify-machineinstrs

Modified:
    llvm/trunk/lib/Target/PowerPC/PPCAsmPrinter.cpp
    llvm/trunk/lib/Target/PowerPC/PPCCodeEmitter.cpp
    llvm/trunk/lib/Target/PowerPC/PPCInstr64Bit.td
    llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.cpp
    llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.td
    llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.cpp

Modified: llvm/trunk/lib/Target/PowerPC/PPCAsmPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCAsmPrinter.cpp?rev=146024&r1=146023&r2=146024&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCAsmPrinter.cpp (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCAsmPrinter.cpp Wed Dec  7 00:34:06 2011
@@ -365,11 +365,12 @@
   }
       
   case PPC::MFCRpseud:
+  case PPC::MFCR8pseud:
     // Transform: %R3 = MFCRpseud %CR7
     // Into:      %R3 = MFCR      ;; cr7
     OutStreamer.AddComment(PPCInstPrinter::
                            getRegisterName(MI->getOperand(1).getReg()));
-    TmpInst.setOpcode(PPC::MFCR);
+    TmpInst.setOpcode(Subtarget.isPPC64() ? PPC::MFCR8 : PPC::MFCR);
     TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
     OutStreamer.EmitInstruction(TmpInst);
     return;

Modified: llvm/trunk/lib/Target/PowerPC/PPCCodeEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCCodeEmitter.cpp?rev=146024&r1=146023&r2=146024&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCCodeEmitter.cpp (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCCodeEmitter.cpp Wed Dec  7 00:34:06 2011
@@ -138,7 +138,8 @@
 unsigned PPCCodeEmitter::get_crbitm_encoding(const MachineInstr &MI,
                                              unsigned OpNo) const {
   const MachineOperand &MO = MI.getOperand(OpNo);
-  assert((MI.getOpcode() == PPC::MTCRF || MI.getOpcode() == PPC::MFOCRF) &&
+  assert((MI.getOpcode() == PPC::MTCRF || MI.getOpcode() == PPC::MTCRF8 ||
+            MI.getOpcode() == PPC::MFOCRF) &&
          (MO.getReg() >= PPC::CR0 && MO.getReg() <= PPC::CR7));
   return 0x80 >> getPPCRegisterNumbering(MO.getReg());
 }
@@ -248,7 +249,8 @@
   if (MO.isReg()) {
     // MTCRF/MFOCRF should go through get_crbitm_encoding for the CR operand.
     // The GPR operand should come through here though.
-    assert((MI.getOpcode() != PPC::MTCRF && MI.getOpcode() != PPC::MFOCRF) ||
+    assert((MI.getOpcode() != PPC::MTCRF && MI.getOpcode() != PPC::MTCRF8 &&
+             MI.getOpcode() != PPC::MFOCRF) ||
            MO.getReg() < PPC::CR0 || MO.getReg() > PPC::CR7);
     return getPPCRegisterNumbering(MO.getReg());
   }

Modified: llvm/trunk/lib/Target/PowerPC/PPCInstr64Bit.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCInstr64Bit.td?rev=146024&r1=146023&r2=146024&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCInstr64Bit.td (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCInstr64Bit.td Wed Dec  7 00:34:06 2011
@@ -223,6 +223,18 @@
 def : Pat<(PPCtc_return CTRRC8:$dst, imm:$imm),
           (TCRETURNri8 CTRRC8:$dst, imm:$imm)>;
 
+// 64-but CR instructions
+def MTCRF8 : XFXForm_5<31, 144, (outs crbitm:$FXM), (ins G8RC:$rS),
+                      "mtcrf $FXM, $rS", BrMCRX>,
+            PPC970_MicroCode, PPC970_Unit_CRU;
+
+def MFCR8pseud: XFXForm_3<31, 19, (outs G8RC:$rT), (ins crbitm:$FXM),
+                       "", SprMFCR>,
+            PPC970_MicroCode, PPC970_Unit_CRU;
+            
+def MFCR8 : XFXForm_3<31, 19, (outs G8RC:$rT), (ins),
+                     "mfcr $rT", SprMFCR>,
+                     PPC970_MicroCode, PPC970_Unit_CRU;
 
 //===----------------------------------------------------------------------===//
 // 64-bit SPR manipulation instrs.
@@ -469,6 +481,12 @@
                       (outs G8RC:$rA), (ins G8RC:$rS, u6imm:$SH, u6imm:$ME),
                       "rldicr $rA, $rS, $SH, $ME", IntRotateD,
                       []>, isPPC64;
+
+def RLWINM8 : MForm_2<21,
+                     (outs G8RC:$rA), (ins G8RC:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME),
+                     "rlwinm $rA, $rS, $SH, $MB, $ME", IntGeneral,
+                     []>;
+
 }  // End FXU Operations.
 
 

Modified: llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.cpp?rev=146024&r1=146023&r2=146024&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.cpp Wed Dec  7 00:34:06 2011
@@ -410,11 +410,14 @@
       // We hack this on Darwin by reserving R2.  It's probably broken on Linux
       // at the moment.
 
+      bool is64Bit = TM.getSubtargetImpl()->isPPC64();
       // We need to store the CR in the low 4-bits of the saved value.  First,
       // issue a MFCR to save all of the CRBits.
       unsigned ScratchReg = TM.getSubtargetImpl()->isDarwinABI() ?
-                                                           PPC::R2 : PPC::R0;
-      NewMIs.push_back(BuildMI(MF, DL, get(PPC::MFCRpseud), ScratchReg)
+                              (is64Bit ? PPC::X2 : PPC::R2) :
+                              (is64Bit ? PPC::X0 : PPC::R0);
+      NewMIs.push_back(BuildMI(MF, DL, get(is64Bit ? PPC::MFCR8pseud :
+                                             PPC::MFCRpseud), ScratchReg)
                                .addReg(SrcReg, getKillRegState(isKill)));
 
       // If the saved register wasn't CR0, shift the bits left so that they are
@@ -422,12 +425,14 @@
       if (SrcReg != PPC::CR0) {
         unsigned ShiftBits = getPPCRegisterNumbering(SrcReg)*4;
         // rlwinm scratch, scratch, ShiftBits, 0, 31.
-        NewMIs.push_back(BuildMI(MF, DL, get(PPC::RLWINM), ScratchReg)
+        NewMIs.push_back(BuildMI(MF, DL, get(is64Bit ? PPC::RLWINM8 :
+                           PPC::RLWINM), ScratchReg)
                        .addReg(ScratchReg).addImm(ShiftBits)
                        .addImm(0).addImm(31));
       }
 
-      NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STW))
+      NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(is64Bit ?
+                                           PPC::STW8 : PPC::STW))
                                          .addReg(ScratchReg,
                                                  getKillRegState(isKill)),
                                          FrameIdx));
@@ -568,7 +573,8 @@
                       .addImm(31));
       }
   
-      NewMIs.push_back(BuildMI(MF, DL, get(PPC::MTCRF), DestReg)
+      NewMIs.push_back(BuildMI(MF, DL, get(TM.getSubtargetImpl()->isPPC64() ?
+                         PPC::MTCRF8 : PPC::MTCRF), DestReg)
                        .addReg(ScratchReg));
     }
   } else if (PPC::CRBITRCRegisterClass->hasSubClassEq(RC)) {

Modified: llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.td?rev=146024&r1=146023&r2=146024&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.td (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.td Wed Dec  7 00:34:06 2011
@@ -1098,7 +1098,7 @@
                              "mfspr $rT, 256", IntGeneral>,
                PPC970_DGroup_First, PPC970_Unit_FXU;
 
-def MTCRF : XFXForm_5<31, 144, (outs), (ins crbitm:$FXM, GPRC:$rS),
+def MTCRF : XFXForm_5<31, 144, (outs crbitm:$FXM), (ins GPRC:$rS),
                       "mtcrf $FXM, $rS", BrMCRX>,
             PPC970_MicroCode, PPC970_Unit_CRU;
 

Modified: llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.cpp?rev=146024&r1=146023&r2=146024&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.cpp (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.cpp Wed Dec  7 00:34:06 2011
@@ -473,14 +473,14 @@
 
   // We need to store the CR in the low 4-bits of the saved value. First, issue
   // an MFCRpsued to save all of the CRBits and, if needed, kill the SrcReg.
-  BuildMI(MBB, II, dl, TII.get(PPC::MFCRpseud), Reg)
+  BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::MFCR8pseud : PPC::MFCRpseud), Reg)
           .addReg(SrcReg, getKillRegState(MI.getOperand(0).isKill()));
     
   // If the saved register wasn't CR0, shift the bits left so that they are in
   // CR0's slot.
   if (SrcReg != PPC::CR0)
     // rlwinm rA, rA, ShiftBits, 0, 31.
-    BuildMI(MBB, II, dl, TII.get(PPC::RLWINM), Reg)
+    BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::RLWINM8 : PPC::RLWINM), Reg)
       .addReg(Reg, RegState::Kill)
       .addImm(getPPCRegisterNumbering(SrcReg) * 4)
       .addImm(0)
@@ -525,7 +525,7 @@
              .addImm(31);
   }
 
-  BuildMI(MBB, II, dl, TII.get(PPC::MTCRF), DestReg)
+  BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::MTCRF8 : PPC::MTCRF), DestReg)
              .addReg(Reg);
 
   // Discard the pseudo instruction.



From dblaikie at gmail.com  Wed Dec  7 00:44:24 2011
From: dblaikie at gmail.com (David Blaikie)
Date: Wed, 07 Dec 2011 06:44:24 -0000
Subject: [llvm-commits] [llvm] r146025 - in /llvm/trunk:
 include/llvm/ADT/DAGDeltaAlgorithm.h lib/Support/DAGDeltaAlgorithm.cpp
Message-ID: <20111207064424.9A40F1BE003@llvm.org>

Author: dblaikie
Date: Wed Dec  7 00:44:23 2011
New Revision: 146025

URL: http://llvm.org/viewvc/llvm-project?rev=146025&view=rev
Log:
Adding missing anchor to DATDeltaAlgorithm.

Modified:
    llvm/trunk/include/llvm/ADT/DAGDeltaAlgorithm.h
    llvm/trunk/lib/Support/DAGDeltaAlgorithm.cpp

Modified: llvm/trunk/include/llvm/ADT/DAGDeltaAlgorithm.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/ADT/DAGDeltaAlgorithm.h?rev=146025&r1=146024&r2=146025&view=diff
==============================================================================
--- llvm/trunk/include/llvm/ADT/DAGDeltaAlgorithm.h (original)
+++ llvm/trunk/include/llvm/ADT/DAGDeltaAlgorithm.h Wed Dec  7 00:44:23 2011
@@ -36,6 +36,7 @@
 /// for more information on the properties which the predicate function itself
 /// should satisfy.
 class DAGDeltaAlgorithm {
+  virtual void anchor();
 public:
   typedef unsigned change_ty;
   typedef std::pair edge_ty;

Modified: llvm/trunk/lib/Support/DAGDeltaAlgorithm.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Support/DAGDeltaAlgorithm.cpp?rev=146025&r1=146024&r2=146025&view=diff
==============================================================================
--- llvm/trunk/lib/Support/DAGDeltaAlgorithm.cpp (original)
+++ llvm/trunk/lib/Support/DAGDeltaAlgorithm.cpp Wed Dec  7 00:44:23 2011
@@ -350,6 +350,9 @@
   return Required;
 }
 
+void DAGDeltaAlgorithm::anchor() {
+}
+
 DAGDeltaAlgorithm::changeset_ty
 DAGDeltaAlgorithm::Run(const changeset_ty &Changes,
                        const std::vector &Dependencies) {



From evan.cheng at apple.com  Wed Dec  7 01:15:53 2011
From: evan.cheng at apple.com (Evan Cheng)
Date: Wed, 07 Dec 2011 07:15:53 -0000
Subject: [llvm-commits] [llvm] r146026 - in /llvm/trunk:
 include/llvm/CodeGen/ include/llvm/MC/ lib/CodeGen/ lib/CodeGen/AsmPrinter/
 lib/CodeGen/SelectionDAG/ lib/ExecutionEngine/JIT/ lib/Target/
 lib/Target/ARM/ lib/Target/MBlaze/ lib/Target/MSP430/ lib/Target/Mips/
 lib/Target/PTX/ lib/Target/PowerPC/ lib/Target/Sparc/ lib/Target/X86/
Message-ID: <20111207071555.D23421BE003@llvm.org>

Author: evancheng
Date: Wed Dec  7 01:15:52 2011
New Revision: 146026

URL: http://llvm.org/viewvc/llvm-project?rev=146026&view=rev
Log:
Add bundle aware API for querying instruction properties and switch the code
generator to it. For non-bundle instructions, these behave exactly the same
as the MC layer API.

For properties like mayLoad / mayStore, look into the bundle and if any of the
bundled instructions has the property it would return true.
For properties like isPredicable, only return true if *all* of the bundled
instructions have the property.
For properties like canFoldAsLoad, isCompare, conservatively return false for
bundles.

Modified:
    llvm/trunk/include/llvm/CodeGen/MachineInstr.h
    llvm/trunk/include/llvm/MC/MCInstrDesc.h
    llvm/trunk/lib/CodeGen/AggressiveAntiDepBreaker.cpp
    llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
    llvm/trunk/lib/CodeGen/AsmPrinter/DwarfException.cpp
    llvm/trunk/lib/CodeGen/BranchFolding.cpp
    llvm/trunk/lib/CodeGen/CriticalAntiDepBreaker.cpp
    llvm/trunk/lib/CodeGen/DeadMachineInstructionElim.cpp
    llvm/trunk/lib/CodeGen/ExecutionDepsFix.cpp
    llvm/trunk/lib/CodeGen/ExpandISelPseudos.cpp
    llvm/trunk/lib/CodeGen/ExpandPostRAPseudos.cpp
    llvm/trunk/lib/CodeGen/GCStrategy.cpp
    llvm/trunk/lib/CodeGen/IfConversion.cpp
    llvm/trunk/lib/CodeGen/InlineSpiller.cpp
    llvm/trunk/lib/CodeGen/LiveDebugVariables.cpp
    llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp
    llvm/trunk/lib/CodeGen/LiveRangeEdit.cpp
    llvm/trunk/lib/CodeGen/LiveVariables.cpp
    llvm/trunk/lib/CodeGen/MachineBasicBlock.cpp
    llvm/trunk/lib/CodeGen/MachineCSE.cpp
    llvm/trunk/lib/CodeGen/MachineInstr.cpp
    llvm/trunk/lib/CodeGen/MachineLICM.cpp
    llvm/trunk/lib/CodeGen/MachineSink.cpp
    llvm/trunk/lib/CodeGen/MachineVerifier.cpp
    llvm/trunk/lib/CodeGen/PeepholeOptimizer.cpp
    llvm/trunk/lib/CodeGen/PostRASchedulerList.cpp
    llvm/trunk/lib/CodeGen/PrologEpilogInserter.cpp
    llvm/trunk/lib/CodeGen/RegAllocFast.cpp
    llvm/trunk/lib/CodeGen/RegisterCoalescer.cpp
    llvm/trunk/lib/CodeGen/ScheduleDAGInstrs.cpp
    llvm/trunk/lib/CodeGen/SelectionDAG/InstrEmitter.cpp
    llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
    llvm/trunk/lib/CodeGen/ShrinkWrapping.cpp
    llvm/trunk/lib/CodeGen/SplitKit.cpp
    llvm/trunk/lib/CodeGen/TailDuplication.cpp
    llvm/trunk/lib/CodeGen/TargetInstrInfoImpl.cpp
    llvm/trunk/lib/CodeGen/TwoAddressInstructionPass.cpp
    llvm/trunk/lib/ExecutionEngine/JIT/JITDwarfEmitter.cpp
    llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp
    llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp
    llvm/trunk/lib/Target/ARM/ARMConstantIslandPass.cpp
    llvm/trunk/lib/Target/ARM/ARMFastISel.cpp
    llvm/trunk/lib/Target/ARM/ARMFrameLowering.cpp
    llvm/trunk/lib/Target/ARM/ARMHazardRecognizer.cpp
    llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
    llvm/trunk/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
    llvm/trunk/lib/Target/ARM/MLxExpansionPass.cpp
    llvm/trunk/lib/Target/ARM/Thumb1RegisterInfo.cpp
    llvm/trunk/lib/Target/ARM/Thumb2ITBlockPass.cpp
    llvm/trunk/lib/Target/ARM/Thumb2SizeReduction.cpp
    llvm/trunk/lib/Target/MBlaze/MBlazeAsmPrinter.cpp
    llvm/trunk/lib/Target/MBlaze/MBlazeDelaySlotFiller.cpp
    llvm/trunk/lib/Target/MSP430/MSP430FrameLowering.cpp
    llvm/trunk/lib/Target/MSP430/MSP430InstrInfo.cpp
    llvm/trunk/lib/Target/Mips/MipsAsmPrinter.cpp
    llvm/trunk/lib/Target/Mips/MipsCodeEmitter.cpp
    llvm/trunk/lib/Target/Mips/MipsDelaySlotFiller.cpp
    llvm/trunk/lib/Target/PTX/PTXInstrInfo.cpp
    llvm/trunk/lib/Target/PowerPC/PPCFrameLowering.cpp
    llvm/trunk/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
    llvm/trunk/lib/Target/Sparc/DelaySlotFiller.cpp
    llvm/trunk/lib/Target/Sparc/SparcAsmPrinter.cpp
    llvm/trunk/lib/Target/Sparc/SparcInstrInfo.cpp
    llvm/trunk/lib/Target/TargetInstrInfo.cpp
    llvm/trunk/lib/Target/X86/X86CodeEmitter.cpp
    llvm/trunk/lib/Target/X86/X86FrameLowering.cpp
    llvm/trunk/lib/Target/X86/X86InstrInfo.cpp
    llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp
    llvm/trunk/lib/Target/X86/X86VZeroUpper.cpp

Modified: llvm/trunk/include/llvm/CodeGen/MachineInstr.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/MachineInstr.h?rev=146026&r1=146025&r2=146026&view=diff
==============================================================================
--- llvm/trunk/include/llvm/CodeGen/MachineInstr.h (original)
+++ llvm/trunk/include/llvm/CodeGen/MachineInstr.h Wed Dec  7 01:15:52 2011
@@ -274,14 +274,267 @@
     return MemRefsEnd - MemRefs == 1;
   }
 
-  /// API for querying MachineInstr properties. These are bundle aware.
+  /// API for querying MachineInstr properties. They are the same as MCInstrDesc
+  /// queries but they are bundle aware.
+
+  /// hasProperty - Return true if the instruction (or in the case of a bundle,
+  /// the instructions inside the bundle) has the specified property.
+  /// The first argument is the property being queried.
+  /// The second argument indicates whether the query should look inside
+  /// instruction bundles.
+  /// If the third argument is true, than the query can return true when *any*
+  /// of the bundled instructions has the queried property. If it's false, then
+  /// this can return true iff *all* of the instructions have the property.
+  bool hasProperty(unsigned Flag,
+                   bool PeekInBundle = true, bool IsOr = true) const;
+
+  /// isVariadic - Return true if this instruction can have a variable number of
+  /// operands.  In this case, the variable operands will be after the normal
+  /// operands but before the implicit definitions and uses (if any are
+  /// present).
+  bool isVariadic() const {
+    return hasProperty(MCID::Variadic, false);
+  }
+
+  /// hasOptionalDef - Set if this instruction has an optional definition, e.g.
+  /// ARM instructions which can set condition code if 's' bit is set.
+  bool hasOptionalDef() const {
+    return hasProperty(MCID::HasOptionalDef, false);
+  }
+
+  /// isPseudo - Return true if this is a pseudo instruction that doesn't
+  /// correspond to a real machine instruction.
   ///
-  bool hasProperty(unsigned short Flag) const;
+  bool isPseudo() const {
+    return hasProperty(MCID::Pseudo, false);
+  }
+
+  bool isReturn() const {
+    return hasProperty(MCID::Return);
+  }
+
+  bool isCall() const {
+    return hasProperty(MCID::Call);
+  }
+
+  /// isBarrier - Returns true if the specified instruction stops control flow
+  /// from executing the instruction immediately following it.  Examples include
+  /// unconditional branches and return instructions.
+  bool isBarrier() const {
+    return hasProperty(MCID::Barrier);
+  }
 
+  /// isTerminator - Returns true if this instruction part of the terminator for
+  /// a basic block.  Typically this is things like return and branch
+  /// instructions.
+  ///
+  /// Various passes use this to insert code into the bottom of a basic block,
+  /// but before control flow occurs.
   bool isTerminator() const {
     return hasProperty(MCID::Terminator);
   }
 
+  /// isBranch - Returns true if this is a conditional, unconditional, or
+  /// indirect branch.  Predicates below can be used to discriminate between
+  /// these cases, and the TargetInstrInfo::AnalyzeBranch method can be used to
+  /// get more information.
+  bool isBranch() const {
+    return hasProperty(MCID::Branch);
+  }
+
+  /// isIndirectBranch - Return true if this is an indirect branch, such as a
+  /// branch through a register.
+  bool isIndirectBranch() const {
+    return hasProperty(MCID::IndirectBranch);
+  }
+
+  /// isConditionalBranch - Return true if this is a branch which may fall
+  /// through to the next instruction or may transfer control flow to some other
+  /// block.  The TargetInstrInfo::AnalyzeBranch method can be used to get more
+  /// information about this branch.
+  bool isConditionalBranch() const {
+    return isBranch() & !isBarrier() & !isIndirectBranch();
+  }
+
+  /// isUnconditionalBranch - Return true if this is a branch which always
+  /// transfers control flow to some other block.  The
+  /// TargetInstrInfo::AnalyzeBranch method can be used to get more information
+  /// about this branch.
+  bool isUnconditionalBranch() const {
+    return isBranch() & isBarrier() & !isIndirectBranch();
+  }
+
+  // isPredicable - Return true if this instruction has a predicate operand that
+  // controls execution.  It may be set to 'always', or may be set to other
+  /// values.   There are various methods in TargetInstrInfo that can be used to
+  /// control and modify the predicate in this instruction.
+  bool isPredicable() const {
+    // If it's a bundle than all bundled instructions must be predicable for this
+    // to return true.
+    return hasProperty(MCID::Predicable, true, false);
+  }
+
+  /// isCompare - Return true if this instruction is a comparison.
+  bool isCompare() const {
+    return hasProperty(MCID::Compare, false);
+  }
+
+  /// isMoveImmediate - Return true if this instruction is a move immediate
+  /// (including conditional moves) instruction.
+  bool isMoveImmediate() const {
+    return hasProperty(MCID::MoveImm, false);
+  }
+
+  /// isBitcast - Return true if this instruction is a bitcast instruction.
+  ///
+  bool isBitcast() const {
+    return hasProperty(MCID::Bitcast, false);
+  }
+
+  /// isNotDuplicable - Return true if this instruction cannot be safely
+  /// duplicated.  For example, if the instruction has a unique labels attached
+  /// to it, duplicating it would cause multiple definition errors.
+  bool isNotDuplicable() const {
+    return hasProperty(MCID::NotDuplicable);
+  }
+
+  /// hasDelaySlot - Returns true if the specified instruction has a delay slot
+  /// which must be filled by the code generator.
+  bool hasDelaySlot() const {
+    return hasProperty(MCID::DelaySlot);
+  }
+
+  /// canFoldAsLoad - Return true for instructions that can be folded as
+  /// memory operands in other instructions. The most common use for this
+  /// is instructions that are simple loads from memory that don't modify
+  /// the loaded value in any way, but it can also be used for instructions
+  /// that can be expressed as constant-pool loads, such as V_SETALLONES
+  /// on x86, to allow them to be folded when it is beneficial.
+  /// This should only be set on instructions that return a value in their
+  /// only virtual register definition.
+  bool canFoldAsLoad() const {
+    return hasProperty(MCID::FoldableAsLoad, false);
+  }
+
+  //===--------------------------------------------------------------------===//
+  // Side Effect Analysis
+  //===--------------------------------------------------------------------===//
+
+  /// mayLoad - Return true if this instruction could possibly read memory.
+  /// Instructions with this flag set are not necessarily simple load
+  /// instructions, they may load a value and modify it, for example.
+  bool mayLoad() const {
+    return hasProperty(MCID::MayLoad);
+  }
+
+
+  /// mayStore - Return true if this instruction could possibly modify memory.
+  /// Instructions with this flag set are not necessarily simple store
+  /// instructions, they may store a modified value based on their operands, or
+  /// may not actually modify anything, for example.
+  bool mayStore() const {
+    return hasProperty(MCID::MayStore);
+  }
+
+  //===--------------------------------------------------------------------===//
+  // Flags that indicate whether an instruction can be modified by a method.
+  //===--------------------------------------------------------------------===//
+
+  /// isCommutable - Return true if this may be a 2- or 3-address
+  /// instruction (of the form "X = op Y, Z, ..."), which produces the same
+  /// result if Y and Z are exchanged.  If this flag is set, then the
+  /// TargetInstrInfo::commuteInstruction method may be used to hack on the
+  /// instruction.
+  ///
+  /// Note that this flag may be set on instructions that are only commutable
+  /// sometimes.  In these cases, the call to commuteInstruction will fail.
+  /// Also note that some instructions require non-trivial modification to
+  /// commute them.
+  bool isCommutable() const {
+    return hasProperty(MCID::Commutable, false);
+  }
+
+  /// isConvertibleTo3Addr - Return true if this is a 2-address instruction
+  /// which can be changed into a 3-address instruction if needed.  Doing this
+  /// transformation can be profitable in the register allocator, because it
+  /// means that the instruction can use a 2-address form if possible, but
+  /// degrade into a less efficient form if the source and dest register cannot
+  /// be assigned to the same register.  For example, this allows the x86
+  /// backend to turn a "shl reg, 3" instruction into an LEA instruction, which
+  /// is the same speed as the shift but has bigger code size.
+  ///
+  /// If this returns true, then the target must implement the
+  /// TargetInstrInfo::convertToThreeAddress method for this instruction, which
+  /// is allowed to fail if the transformation isn't valid for this specific
+  /// instruction (e.g. shl reg, 4 on x86).
+  ///
+  bool isConvertibleTo3Addr() const {
+    return hasProperty(MCID::ConvertibleTo3Addr, false);
+  }
+
+  /// usesCustomInsertionHook - Return true if this instruction requires
+  /// custom insertion support when the DAG scheduler is inserting it into a
+  /// machine basic block.  If this is true for the instruction, it basically
+  /// means that it is a pseudo instruction used at SelectionDAG time that is
+  /// expanded out into magic code by the target when MachineInstrs are formed.
+  ///
+  /// If this is true, the TargetLoweringInfo::InsertAtEndOfBasicBlock method
+  /// is used to insert this into the MachineBasicBlock.
+  bool usesCustomInsertionHook() const {
+    return hasProperty(MCID::UsesCustomInserter, false);
+  }
+
+  /// hasPostISelHook - Return true if this instruction requires *adjustment*
+  /// after instruction selection by calling a target hook. For example, this
+  /// can be used to fill in ARM 's' optional operand depending on whether
+  /// the conditional flag register is used.
+  bool hasPostISelHook() const {
+    return hasProperty(MCID::HasPostISelHook, false);
+  }
+
+  /// isRematerializable - Returns true if this instruction is a candidate for
+  /// remat.  This flag is deprecated, please don't use it anymore.  If this
+  /// flag is set, the isReallyTriviallyReMaterializable() method is called to
+  /// verify the instruction is really rematable.
+  bool isRematerializable() const {
+    // It's only possible to re-mat a bundle if all bundled instructions are
+    // re-materializable.
+    return hasProperty(MCID::Rematerializable, true, false);
+  }
+
+  /// isAsCheapAsAMove - Returns true if this instruction has the same cost (or
+  /// less) than a move instruction. This is useful during certain types of
+  /// optimizations (e.g., remat during two-address conversion or machine licm)
+  /// where we would like to remat or hoist the instruction, but not if it costs
+  /// more than moving the instruction into the appropriate register. Note, we
+  /// are not marking copies from and to the same register class with this flag.
+  bool isAsCheapAsAMove() const {
+    // Only returns true for a bundle if all bundled instructions are cheap.
+    // FIXME: This probably requires a target hook.
+    return hasProperty(MCID::CheapAsAMove, true, true);
+  }
+
+  /// hasExtraSrcRegAllocReq - Returns true if this instruction source operands
+  /// have special register allocation requirements that are not captured by the
+  /// operand register classes. e.g. ARM::STRD's two source registers must be an
+  /// even / odd pair, ARM::STM registers have to be in ascending order.
+  /// Post-register allocation passes should not attempt to change allocations
+  /// for sources of instructions with this flag.
+  bool hasExtraSrcRegAllocReq() const {
+    return hasProperty(MCID::ExtraSrcRegAllocReq);
+  }
+
+  /// hasExtraDefRegAllocReq - Returns true if this instruction def operands
+  /// have special register allocation requirements that are not captured by the
+  /// operand register classes. e.g. ARM::LDRD's two def registers must be an
+  /// even / odd pair, ARM::LDM registers have to be in ascending order.
+  /// Post-register allocation passes should not attempt to change allocations
+  /// for definitions of instructions with this flag.
+  bool hasExtraDefRegAllocReq() const {
+    return hasProperty(MCID::ExtraDefRegAllocReq);
+  }
+
+
   enum MICheckType {
     CheckDefs,      // Check all operands for equality
     CheckKillDead,  // Check all operands including kill / dead markers

Modified: llvm/trunk/include/llvm/MC/MCInstrDesc.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/MC/MCInstrDesc.h?rev=146026&r1=146025&r2=146026&view=diff
==============================================================================
--- llvm/trunk/include/llvm/MC/MCInstrDesc.h (original)
+++ llvm/trunk/include/llvm/MC/MCInstrDesc.h Wed Dec  7 01:15:52 2011
@@ -186,7 +186,7 @@
 
   /// getFlags - Return flags of this instruction.
   ///
-  unsigned short getFlags() const { return Flags; }
+  unsigned getFlags() const { return Flags; }
 
   /// isVariadic - Return true if this instruction can have a variable number of
   /// operands.  In this case, the variable operands will be after the normal
@@ -202,84 +202,6 @@
     return Flags & (1 << MCID::HasOptionalDef);
   }
 
-  /// getImplicitUses - Return a list of registers that are potentially
-  /// read by any instance of this machine instruction.  For example, on X86,
-  /// the "adc" instruction adds two register operands and adds the carry bit in
-  /// from the flags register.  In this case, the instruction is marked as
-  /// implicitly reading the flags.  Likewise, the variable shift instruction on
-  /// X86 is marked as implicitly reading the 'CL' register, which it always
-  /// does.
-  ///
-  /// This method returns null if the instruction has no implicit uses.
-  const unsigned *getImplicitUses() const {
-    return ImplicitUses;
-  }
-
-  /// getNumImplicitUses - Return the number of implicit uses this instruction
-  /// has.
-  unsigned getNumImplicitUses() const {
-    if (ImplicitUses == 0) return 0;
-    unsigned i = 0;
-    for (; ImplicitUses[i]; ++i) /*empty*/;
-    return i;
-  }
-
-  /// getImplicitDefs - Return a list of registers that are potentially
-  /// written by any instance of this machine instruction.  For example, on X86,
-  /// many instructions implicitly set the flags register.  In this case, they
-  /// are marked as setting the FLAGS.  Likewise, many instructions always
-  /// deposit their result in a physical register.  For example, the X86 divide
-  /// instruction always deposits the quotient and remainder in the EAX/EDX
-  /// registers.  For that instruction, this will return a list containing the
-  /// EAX/EDX/EFLAGS registers.
-  ///
-  /// This method returns null if the instruction has no implicit defs.
-  const unsigned *getImplicitDefs() const {
-    return ImplicitDefs;
-  }
-
-  /// getNumImplicitDefs - Return the number of implicit defs this instruction
-  /// has.
-  unsigned getNumImplicitDefs() const {
-    if (ImplicitDefs == 0) return 0;
-    unsigned i = 0;
-    for (; ImplicitDefs[i]; ++i) /*empty*/;
-    return i;
-  }
-
-  /// hasImplicitUseOfPhysReg - Return true if this instruction implicitly
-  /// uses the specified physical register.
-  bool hasImplicitUseOfPhysReg(unsigned Reg) const {
-    if (const unsigned *ImpUses = ImplicitUses)
-      for (; *ImpUses; ++ImpUses)
-        if (*ImpUses == Reg) return true;
-    return false;
-  }
-
-  /// hasImplicitDefOfPhysReg - Return true if this instruction implicitly
-  /// defines the specified physical register.
-  bool hasImplicitDefOfPhysReg(unsigned Reg) const {
-    if (const unsigned *ImpDefs = ImplicitDefs)
-      for (; *ImpDefs; ++ImpDefs)
-        if (*ImpDefs == Reg) return true;
-    return false;
-  }
-
-  /// getSchedClass - Return the scheduling class for this instruction.  The
-  /// scheduling class is an index into the InstrItineraryData table.  This
-  /// returns zero if there is no known scheduling information for the
-  /// instruction.
-  ///
-  unsigned getSchedClass() const {
-    return SchedClass;
-  }
-
-  /// getSize - Return the number of bytes in the encoding of this instruction,
-  /// or zero if the encoding size cannot be known from the opcode.
-  unsigned getSize() const {
-    return Size;
-  }
-
   /// isPseudo - Return true if this is a pseudo instruction that doesn't
   /// correspond to a real machine instruction.
   ///
@@ -302,18 +224,6 @@
     return Flags & (1 << MCID::Barrier);
   }
 
-  /// findFirstPredOperandIdx() - Find the index of the first operand in the
-  /// operand list that is used to represent the predicate. It returns -1 if
-  /// none is found.
-  int findFirstPredOperandIdx() const {
-    if (isPredicable()) {
-      for (unsigned i = 0, e = getNumOperands(); i != e; ++i)
-        if (OpInfo[i].isPredicate())
-          return i;
-    }
-    return -1;
-  }
-
   /// isTerminator - Returns true if this instruction part of the terminator for
   /// a basic block.  Typically this is things like return and branch
   /// instructions.
@@ -534,6 +444,97 @@
   bool hasExtraDefRegAllocReq() const {
     return Flags & (1 << MCID::ExtraDefRegAllocReq);
   }
+
+
+  /// getImplicitUses - Return a list of registers that are potentially
+  /// read by any instance of this machine instruction.  For example, on X86,
+  /// the "adc" instruction adds two register operands and adds the carry bit in
+  /// from the flags register.  In this case, the instruction is marked as
+  /// implicitly reading the flags.  Likewise, the variable shift instruction on
+  /// X86 is marked as implicitly reading the 'CL' register, which it always
+  /// does.
+  ///
+  /// This method returns null if the instruction has no implicit uses.
+  const unsigned *getImplicitUses() const {
+    return ImplicitUses;
+  }
+
+  /// getNumImplicitUses - Return the number of implicit uses this instruction
+  /// has.
+  unsigned getNumImplicitUses() const {
+    if (ImplicitUses == 0) return 0;
+    unsigned i = 0;
+    for (; ImplicitUses[i]; ++i) /*empty*/;
+    return i;
+  }
+
+  /// getImplicitDefs - Return a list of registers that are potentially
+  /// written by any instance of this machine instruction.  For example, on X86,
+  /// many instructions implicitly set the flags register.  In this case, they
+  /// are marked as setting the FLAGS.  Likewise, many instructions always
+  /// deposit their result in a physical register.  For example, the X86 divide
+  /// instruction always deposits the quotient and remainder in the EAX/EDX
+  /// registers.  For that instruction, this will return a list containing the
+  /// EAX/EDX/EFLAGS registers.
+  ///
+  /// This method returns null if the instruction has no implicit defs.
+  const unsigned *getImplicitDefs() const {
+    return ImplicitDefs;
+  }
+
+  /// getNumImplicitDefs - Return the number of implicit defs this instruction
+  /// has.
+  unsigned getNumImplicitDefs() const {
+    if (ImplicitDefs == 0) return 0;
+    unsigned i = 0;
+    for (; ImplicitDefs[i]; ++i) /*empty*/;
+    return i;
+  }
+
+  /// hasImplicitUseOfPhysReg - Return true if this instruction implicitly
+  /// uses the specified physical register.
+  bool hasImplicitUseOfPhysReg(unsigned Reg) const {
+    if (const unsigned *ImpUses = ImplicitUses)
+      for (; *ImpUses; ++ImpUses)
+        if (*ImpUses == Reg) return true;
+    return false;
+  }
+
+  /// hasImplicitDefOfPhysReg - Return true if this instruction implicitly
+  /// defines the specified physical register.
+  bool hasImplicitDefOfPhysReg(unsigned Reg) const {
+    if (const unsigned *ImpDefs = ImplicitDefs)
+      for (; *ImpDefs; ++ImpDefs)
+        if (*ImpDefs == Reg) return true;
+    return false;
+  }
+
+  /// getSchedClass - Return the scheduling class for this instruction.  The
+  /// scheduling class is an index into the InstrItineraryData table.  This
+  /// returns zero if there is no known scheduling information for the
+  /// instruction.
+  ///
+  unsigned getSchedClass() const {
+    return SchedClass;
+  }
+
+  /// getSize - Return the number of bytes in the encoding of this instruction,
+  /// or zero if the encoding size cannot be known from the opcode.
+  unsigned getSize() const {
+    return Size;
+  }
+
+  /// findFirstPredOperandIdx() - Find the index of the first operand in the
+  /// operand list that is used to represent the predicate. It returns -1 if
+  /// none is found.
+  int findFirstPredOperandIdx() const {
+    if (isPredicable()) {
+      for (unsigned i = 0, e = getNumOperands(); i != e; ++i)
+        if (OpInfo[i].isPredicate())
+          return i;
+    }
+    return -1;
+  }
 };
 
 } // end namespace llvm

Modified: llvm/trunk/lib/CodeGen/AggressiveAntiDepBreaker.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AggressiveAntiDepBreaker.cpp?rev=146026&r1=146025&r2=146026&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/AggressiveAntiDepBreaker.cpp (original)
+++ llvm/trunk/lib/CodeGen/AggressiveAntiDepBreaker.cpp Wed Dec  7 01:15:52 2011
@@ -148,7 +148,7 @@
   assert(State == NULL);
   State = new AggressiveAntiDepState(TRI->getNumRegs(), BB);
 
-  bool IsReturnBlock = (!BB->empty() && BB->back().getDesc().isReturn());
+  bool IsReturnBlock = (!BB->empty() && BB->back().isReturn());
   std::vector &KillIndices = State->GetKillIndices();
   std::vector &DefIndices = State->GetDefIndices();
 
@@ -384,7 +384,7 @@
     // If MI's defs have a special allocation requirement, don't allow
     // any def registers to be changed. Also assume all registers
     // defined in a call must not be changed (ABI).
-    if (MI->getDesc().isCall() || MI->getDesc().hasExtraDefRegAllocReq() ||
+    if (MI->isCall() || MI->hasExtraDefRegAllocReq() ||
         TII->isPredicated(MI)) {
       DEBUG(if (State->GetGroup(Reg) != 0) dbgs() << "->g0(alloc-req)");
       State->UnionGroups(Reg, 0);
@@ -451,8 +451,8 @@
   // instruction which may not be executed. The second R6 def may or may not
   // re-define R6 so it's not safe to change it since the last R6 use cannot be
   // changed.
-  bool Special = MI->getDesc().isCall() ||
-    MI->getDesc().hasExtraSrcRegAllocReq() ||
+  bool Special = MI->isCall() ||
+    MI->hasExtraSrcRegAllocReq() ||
     TII->isPredicated(MI);
 
   // Scan the register uses for this instruction and update

Modified: llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp?rev=146026&r1=146025&r2=146026&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp (original)
+++ llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp Wed Dec  7 01:15:52 2011
@@ -2087,7 +2087,7 @@
     MachineInstr &MI = *II;
 
     // If it is not a simple branch, we are in a table somewhere.
-    if (!MI.getDesc().isBranch() || MI.getDesc().isIndirectBranch())
+    if (!MI.isBranch() || MI.isIndirectBranch())
       return false;
 
     // If we are the operands of one of the branches, this is not

Modified: llvm/trunk/lib/CodeGen/AsmPrinter/DwarfException.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/DwarfException.cpp?rev=146026&r1=146025&r2=146026&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/AsmPrinter/DwarfException.cpp (original)
+++ llvm/trunk/lib/CodeGen/AsmPrinter/DwarfException.cpp Wed Dec  7 01:15:52 2011
@@ -184,7 +184,7 @@
 /// CallToNoUnwindFunction - Return `true' if this is a call to a function
 /// marked `nounwind'. Return `false' otherwise.
 bool DwarfException::CallToNoUnwindFunction(const MachineInstr *MI) {
-  assert(MI->getDesc().isCall() && "This should be a call instruction!");
+  assert(MI->isCall() && "This should be a call instruction!");
 
   bool MarkedNoUnwind = false;
   bool SawFunc = false;
@@ -243,7 +243,7 @@
     for (MachineBasicBlock::const_iterator MI = I->begin(), E = I->end();
          MI != E; ++MI) {
       if (!MI->isLabel()) {
-        if (MI->getDesc().isCall())
+        if (MI->isCall())
           SawPotentiallyThrowing |= !CallToNoUnwindFunction(MI);
         continue;
       }

Modified: llvm/trunk/lib/CodeGen/BranchFolding.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/BranchFolding.cpp?rev=146026&r1=146025&r2=146026&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/BranchFolding.cpp (original)
+++ llvm/trunk/lib/CodeGen/BranchFolding.cpp Wed Dec  7 01:15:52 2011
@@ -432,10 +432,9 @@
   for (; I != E; ++I) {
     if (I->isDebugValue())
       continue;
-    const MCInstrDesc &MCID = I->getDesc();
-    if (MCID.isCall())
+    if (I->isCall())
       Time += 10;
-    else if (MCID.mayLoad() || MCID.mayStore())
+    else if (I->mayLoad() || I->mayStore())
       Time += 2;
     else
       ++Time;
@@ -502,7 +501,7 @@
       break;
     }
     --I;
-    if (!I->getDesc().isTerminator()) break;
+    if (!I->isTerminator()) break;
     ++NumTerms;
   }
   return NumTerms;
@@ -550,8 +549,8 @@
   // heuristics.
   unsigned EffectiveTailLen = CommonTailLen;
   if (SuccBB && MBB1 != PredBB && MBB2 != PredBB &&
-      !MBB1->back().getDesc().isBarrier() &&
-      !MBB2->back().getDesc().isBarrier())
+      !MBB1->back().isBarrier() &&
+      !MBB2->back().isBarrier())
     ++EffectiveTailLen;
 
   // Check if the common tail is long enough to be worthwhile.
@@ -983,7 +982,7 @@
     if (!MBBI->isDebugValue())
       break;
   }
-  return (MBBI->getDesc().isBranch());
+  return (MBBI->isBranch());
 }
 
 /// IsBetterFallthrough - Return true if it would be clearly better to
@@ -1011,7 +1010,7 @@
   MachineBasicBlock::iterator MBB2I = --MBB2->end();
   while (MBB2I->isDebugValue())
     --MBB2I;
-  return MBB2I->getDesc().isCall() && !MBB1I->getDesc().isCall();
+  return MBB2I->isCall() && !MBB1I->isCall();
 }
 
 /// OptimizeBlock - Analyze and optimize control flow related to the specified

Modified: llvm/trunk/lib/CodeGen/CriticalAntiDepBreaker.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/CriticalAntiDepBreaker.cpp?rev=146026&r1=146025&r2=146026&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/CriticalAntiDepBreaker.cpp (original)
+++ llvm/trunk/lib/CodeGen/CriticalAntiDepBreaker.cpp Wed Dec  7 01:15:52 2011
@@ -54,7 +54,7 @@
   // Clear "do not change" set.
   KeepRegs.clear();
 
-  bool IsReturnBlock = (!BB->empty() && BB->back().getDesc().isReturn());
+  bool IsReturnBlock = (!BB->empty() && BB->back().isReturn());
 
   // Determine the live-out physregs for this block.
   if (IsReturnBlock) {
@@ -193,8 +193,8 @@
   // instruction which may not be executed. The second R6 def may or may not
   // re-define R6 so it's not safe to change it since the last R6 use cannot be
   // changed.
-  bool Special = MI->getDesc().isCall() ||
-    MI->getDesc().hasExtraSrcRegAllocReq() ||
+  bool Special = MI->isCall() ||
+    MI->hasExtraSrcRegAllocReq() ||
     TII->isPredicated(MI);
 
   // Scan the register operands for this instruction and update
@@ -572,7 +572,7 @@
     // If MI's defs have a special allocation requirement, don't allow
     // any def registers to be changed. Also assume all registers
     // defined in a call must not be changed (ABI).
-    if (MI->getDesc().isCall() || MI->getDesc().hasExtraDefRegAllocReq() ||
+    if (MI->isCall() || MI->hasExtraDefRegAllocReq() ||
         TII->isPredicated(MI))
       // If this instruction's defs have special allocation requirement, don't
       // break this anti-dependency.

Modified: llvm/trunk/lib/CodeGen/DeadMachineInstructionElim.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/DeadMachineInstructionElim.cpp?rev=146026&r1=146025&r2=146026&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/DeadMachineInstructionElim.cpp (original)
+++ llvm/trunk/lib/CodeGen/DeadMachineInstructionElim.cpp Wed Dec  7 01:15:52 2011
@@ -102,7 +102,7 @@
     LivePhysRegs = ReservedRegs;
 
     // Also add any explicit live-out physregs for this block.
-    if (!MBB->empty() && MBB->back().getDesc().isReturn())
+    if (!MBB->empty() && MBB->back().isReturn())
       for (MachineRegisterInfo::liveout_iterator LOI = MRI->liveout_begin(),
            LOE = MRI->liveout_end(); LOI != LOE; ++LOI) {
         unsigned Reg = *LOI;

Modified: llvm/trunk/lib/CodeGen/ExecutionDepsFix.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/ExecutionDepsFix.cpp?rev=146026&r1=146025&r2=146026&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/ExecutionDepsFix.cpp (original)
+++ llvm/trunk/lib/CodeGen/ExecutionDepsFix.cpp Wed Dec  7 01:15:52 2011
@@ -454,7 +454,7 @@
   assert(!MI->isDebugValue() && "Won't process debug values");
   const MCInstrDesc &MCID = MI->getDesc();
   for (unsigned i = 0,
-         e = MCID.isVariadic() ? MI->getNumOperands() : MCID.getNumDefs();
+         e = MI->isVariadic() ? MI->getNumOperands() : MCID.getNumDefs();
          i != e; ++i) {
     MachineOperand &MO = MI->getOperand(i);
     if (!MO.isReg())

Modified: llvm/trunk/lib/CodeGen/ExpandISelPseudos.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/ExpandISelPseudos.cpp?rev=146026&r1=146025&r2=146026&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/ExpandISelPseudos.cpp (original)
+++ llvm/trunk/lib/CodeGen/ExpandISelPseudos.cpp Wed Dec  7 01:15:52 2011
@@ -62,8 +62,7 @@
       MachineInstr *MI = MBBI++;
 
       // If MI is a pseudo, expand it.
-      const MCInstrDesc &MCID = MI->getDesc();
-      if (MCID.usesCustomInsertionHook()) {
+      if (MI->usesCustomInsertionHook()) {
         Changed = true;
         MachineBasicBlock *NewMBB =
           TLI->EmitInstrWithCustomInserter(MI, MBB);

Modified: llvm/trunk/lib/CodeGen/ExpandPostRAPseudos.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/ExpandPostRAPseudos.cpp?rev=146026&r1=146025&r2=146026&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/ExpandPostRAPseudos.cpp (original)
+++ llvm/trunk/lib/CodeGen/ExpandPostRAPseudos.cpp Wed Dec  7 01:15:52 2011
@@ -207,7 +207,7 @@
       ++mi;
 
       // Only expand pseudos.
-      if (!MI->getDesc().isPseudo())
+      if (!MI->isPseudo())
         continue;
 
       // Give targets a chance to expand even standard pseudos.

Modified: llvm/trunk/lib/CodeGen/GCStrategy.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/GCStrategy.cpp?rev=146026&r1=146025&r2=146026&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/GCStrategy.cpp (original)
+++ llvm/trunk/lib/CodeGen/GCStrategy.cpp Wed Dec  7 01:15:52 2011
@@ -386,7 +386,7 @@
                                  BBE = MF.end(); BBI != BBE; ++BBI)
     for (MachineBasicBlock::iterator MI = BBI->begin(),
                                      ME = BBI->end(); MI != ME; ++MI)
-      if (MI->getDesc().isCall())
+      if (MI->isCall())
         VisitCallPoint(MI);
 }
 

Modified: llvm/trunk/lib/CodeGen/IfConversion.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/IfConversion.cpp?rev=146026&r1=146025&r2=146026&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/IfConversion.cpp (original)
+++ llvm/trunk/lib/CodeGen/IfConversion.cpp Wed Dec  7 01:15:52 2011
@@ -573,12 +573,12 @@
   // blocks, move the end iterators up past any branch instructions.
   while (TIE != TIB) {
     --TIE;
-    if (!TIE->getDesc().isBranch())
+    if (!TIE->isBranch())
       break;
   }
   while (FIE != FIB) {
     --FIE;
-    if (!FIE->getDesc().isBranch())
+    if (!FIE->isBranch())
       break;
   }
 
@@ -651,12 +651,11 @@
     if (I->isDebugValue())
       continue;
 
-    const MCInstrDesc &MCID = I->getDesc();
-    if (MCID.isNotDuplicable())
+    if (I->isNotDuplicable())
       BBI.CannotBeCopied = true;
 
     bool isPredicated = TII->isPredicated(I);
-    bool isCondBr = BBI.IsBrAnalyzable && MCID.isConditionalBranch();
+    bool isCondBr = BBI.IsBrAnalyzable && I->isConditionalBranch();
 
     if (!isCondBr) {
       if (!isPredicated) {
@@ -1395,9 +1394,8 @@
 
   for (MachineBasicBlock::iterator I = FromBBI.BB->begin(),
          E = FromBBI.BB->end(); I != E; ++I) {
-    const MCInstrDesc &MCID = I->getDesc();
     // Do not copy the end of the block branches.
-    if (IgnoreBr && MCID.isBranch())
+    if (IgnoreBr && I->isBranch())
       break;
 
     MachineInstr *MI = MF.CloneMachineInstr(I);

Modified: llvm/trunk/lib/CodeGen/InlineSpiller.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/InlineSpiller.cpp?rev=146026&r1=146025&r2=146026&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/InlineSpiller.cpp (original)
+++ llvm/trunk/lib/CodeGen/InlineSpiller.cpp Wed Dec  7 01:15:52 2011
@@ -759,7 +759,7 @@
     // Find all spills and copies of VNI.
     for (MachineRegisterInfo::use_nodbg_iterator UI = MRI.use_nodbg_begin(Reg);
          MachineInstr *MI = UI.skipInstruction();) {
-      if (!MI->isCopy() && !MI->getDesc().mayStore())
+      if (!MI->isCopy() && !MI->mayStore())
         continue;
       SlotIndex Idx = LIS.getInstructionIndex(MI);
       if (LI->getVNInfoAt(Idx) != VNI)
@@ -878,7 +878,7 @@
 
   // Before rematerializing into a register for a single instruction, try to
   // fold a load into the instruction. That avoids allocating a new register.
-  if (RM.OrigMI->getDesc().canFoldAsLoad() &&
+  if (RM.OrigMI->canFoldAsLoad() &&
       foldMemoryOperand(MI, Ops, RM.OrigMI)) {
     Edit->markRematerialized(RM.ParentVNI);
     ++NumFoldedLoads;

Modified: llvm/trunk/lib/CodeGen/LiveDebugVariables.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/LiveDebugVariables.cpp?rev=146026&r1=146025&r2=146026&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/LiveDebugVariables.cpp (original)
+++ llvm/trunk/lib/CodeGen/LiveDebugVariables.cpp Wed Dec  7 01:15:52 2011
@@ -920,8 +920,8 @@
   }
 
   // Don't insert anything after the first terminator, though.
-  return MI->getDesc().isTerminator() ? MBB->getFirstTerminator() :
-                                    llvm::next(MachineBasicBlock::iterator(MI));
+  return MI->isTerminator() ? MBB->getFirstTerminator() :
+                              llvm::next(MachineBasicBlock::iterator(MI));
 }
 
 DebugLoc UserValue::findDebugLoc() {

Modified: llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp?rev=146026&r1=146025&r2=146026&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp (original)
+++ llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp Wed Dec  7 01:15:52 2011
@@ -794,7 +794,7 @@
   MachineBasicBlock::iterator I = mbb->end(), B = mbb->begin();
   while (I != B) {
     --I;
-    if (I->getDesc().isCall())
+    if (I->isCall())
       return I;
   }
   // The block contains no calls that can throw, so use the first terminator.

Modified: llvm/trunk/lib/CodeGen/LiveRangeEdit.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/LiveRangeEdit.cpp?rev=146026&r1=146025&r2=146026&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/LiveRangeEdit.cpp (original)
+++ llvm/trunk/lib/CodeGen/LiveRangeEdit.cpp Wed Dec  7 01:15:52 2011
@@ -129,7 +129,7 @@
   }
 
   // If only cheap remats were requested, bail out early.
-  if (cheapAsAMove && !RM.OrigMI->getDesc().isAsCheapAsAMove())
+  if (cheapAsAMove && !RM.OrigMI->isAsCheapAsAMove())
     return false;
 
   // Verify that all used registers are available with the same values.
@@ -174,7 +174,7 @@
     if (MO.isDef()) {
       if (DefMI && DefMI != MI)
         return false;
-      if (!MI->getDesc().canFoldAsLoad())
+      if (!MI->canFoldAsLoad())
         return false;
       DefMI = MI;
     } else if (!MO.isUndef()) {

Modified: llvm/trunk/lib/CodeGen/LiveVariables.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/LiveVariables.cpp?rev=146026&r1=146025&r2=146026&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/LiveVariables.cpp (original)
+++ llvm/trunk/lib/CodeGen/LiveVariables.cpp Wed Dec  7 01:15:52 2011
@@ -590,8 +590,8 @@
     // them.  The tail callee need not take the same registers as input
     // that it produces as output, and there are dependencies for its input
     // registers elsewhere.
-    if (!MBB->empty() && MBB->back().getDesc().isReturn()
-        && !MBB->back().getDesc().isCall()) {
+    if (!MBB->empty() && MBB->back().isReturn()
+        && !MBB->back().isCall()) {
       MachineInstr *Ret = &MBB->back();
 
       for (MachineRegisterInfo::liveout_iterator

Modified: llvm/trunk/lib/CodeGen/MachineBasicBlock.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineBasicBlock.cpp?rev=146026&r1=146025&r2=146026&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/MachineBasicBlock.cpp (original)
+++ llvm/trunk/lib/CodeGen/MachineBasicBlock.cpp Wed Dec  7 01:15:52 2011
@@ -538,8 +538,8 @@
     // Barrier is predicated and thus no longer an actual control barrier. This
     // is over-conservative though, because if an instruction isn't actually
     // predicated we could still treat it like a barrier.
-    return empty() || !back().getDesc().isBarrier() ||
-           back().getDesc().isPredicable();
+    return empty() || !back().isBarrier() ||
+           back().isPredicable();
   }
 
   // If there is no branch, control always falls through.
@@ -737,7 +737,7 @@
   MachineBasicBlock::insn_iterator I = insn_end();
   while (I != insn_begin()) {
     --I;
-    if (!I->getDesc().isTerminator()) break;
+    if (!I->isTerminator()) break;
 
     // Scan the operands of this machine instruction, replacing any uses of Old
     // with New.

Modified: llvm/trunk/lib/CodeGen/MachineCSE.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineCSE.cpp?rev=146026&r1=146025&r2=146026&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/MachineCSE.cpp (original)
+++ llvm/trunk/lib/CodeGen/MachineCSE.cpp Wed Dec  7 01:15:52 2011
@@ -260,12 +260,11 @@
     return false;
 
   // Ignore stuff that we obviously can't move.
-  const MCInstrDesc &MCID = MI->getDesc();  
-  if (MCID.mayStore() || MCID.isCall() || MCID.isTerminator() ||
+  if (MI->mayStore() || MI->isCall() || MI->isTerminator() ||
       MI->hasUnmodeledSideEffects())
     return false;
 
-  if (MCID.mayLoad()) {
+  if (MI->mayLoad()) {
     // Okay, this instruction does a load. As a refinement, we allow the target
     // to decide whether the loaded value is actually a constant. If so, we can
     // actually use it as a load.
@@ -287,7 +286,7 @@
   // Heuristics #1: Don't CSE "cheap" computation if the def is not local or in
   // an immediate predecessor. We don't want to increase register pressure and
   // end up causing other computation to be spilled.
-  if (MI->getDesc().isAsCheapAsAMove()) {
+  if (MI->isAsCheapAsAMove()) {
     MachineBasicBlock *CSBB = CSMI->getParent();
     MachineBasicBlock *BB = MI->getParent();
     if (CSBB != BB && !CSBB->isSuccessor(BB))
@@ -376,7 +375,7 @@
 
     // Commute commutable instructions.
     bool Commuted = false;
-    if (!FoundCSE && MI->getDesc().isCommutable()) {
+    if (!FoundCSE && MI->isCommutable()) {
       MachineInstr *NewMI = TII->commuteInstruction(MI);
       if (NewMI) {
         Commuted = true;

Modified: llvm/trunk/lib/CodeGen/MachineInstr.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineInstr.cpp?rev=146026&r1=146025&r2=146026&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/MachineInstr.cpp (original)
+++ llvm/trunk/lib/CodeGen/MachineInstr.cpp Wed Dec  7 01:15:52 2011
@@ -748,18 +748,25 @@
   MemRefsEnd = NewMemRefsEnd;
 }
 
-bool MachineInstr::hasProperty(unsigned short MCFlag) const {
-  if (getOpcode() != TargetOpcode::BUNDLE)
+bool
+MachineInstr::hasProperty(unsigned MCFlag, bool PeekInBundle, bool IsOr) const {
+  if (!PeekInBundle || getOpcode() != TargetOpcode::BUNDLE)
     return getDesc().getFlags() & (1 << MCFlag);
 
   const MachineBasicBlock *MBB = getParent();
   MachineBasicBlock::const_insn_iterator MII = *this; ++MII;
   while (MII != MBB->end() && MII->isInsideBundle()) {
-    if (MII->getDesc().getFlags() & (1 << MCFlag))
-      return true;
+    if (MII->getDesc().getFlags() & (1 << MCFlag)) {
+      if (IsOr)
+        return true;
+    } else {
+      if (!IsOr)
+        return false;
+    }
     ++MII;
   }
-  return false;
+
+  return !IsOr;
 }
 
 bool MachineInstr::isIdenticalTo(const MachineInstr *Other,
@@ -1017,6 +1024,9 @@
 /// operand list that is used to represent the predicate. It returns -1 if
 /// none is found.
 int MachineInstr::findFirstPredOperandIdx() const {
+  assert(getOpcode() != TargetOpcode::BUNDLE &&
+         "MachineInstr::findFirstPredOperandIdx() can't handle bundles");
+
   // Don't call MCID.findFirstPredOperandIdx() because this variant
   // is sometimes called on an instruction that's not yet complete, and
   // so the number of operands is less than the MCID indicates. In
@@ -1166,6 +1176,9 @@
 
 /// copyPredicates - Copies predicate operand(s) from MI.
 void MachineInstr::copyPredicates(const MachineInstr *MI) {
+  assert(getOpcode() != TargetOpcode::BUNDLE &&
+         "MachineInstr::copyPredicates() can't handle bundles");
+
   const MCInstrDesc &MCID = MI->getDesc();
   if (!MCID.isPredicable())
     return;
@@ -1207,13 +1220,13 @@
                                 AliasAnalysis *AA,
                                 bool &SawStore) const {
   // Ignore stuff that we obviously can't move.
-  if (MCID->mayStore() || MCID->isCall()) {
+  if (mayStore() || isCall()) {
     SawStore = true;
     return false;
   }
 
   if (isLabel() || isDebugValue() ||
-      MCID->isTerminator() || hasUnmodeledSideEffects())
+      isTerminator() || hasUnmodeledSideEffects())
     return false;
 
   // See if this instruction does a load.  If so, we have to guarantee that the
@@ -1221,7 +1234,7 @@
   // destination. The check for isInvariantLoad gives the targe the chance to
   // classify the load as always returning a constant, e.g. a constant pool
   // load.
-  if (MCID->mayLoad() && !isInvariantLoad(AA))
+  if (mayLoad() && !isInvariantLoad(AA))
     // Otherwise, this is a real load.  If there is a store between the load and
     // end of block, or if the load is volatile, we can't move it.
     return !SawStore && !hasVolatileMemoryRef();
@@ -1261,9 +1274,9 @@
 /// have no volatile memory references.
 bool MachineInstr::hasVolatileMemoryRef() const {
   // An instruction known never to access memory won't have a volatile access.
-  if (!MCID->mayStore() &&
-      !MCID->mayLoad() &&
-      !MCID->isCall() &&
+  if (!mayStore() &&
+      !mayLoad() &&
+      !isCall() &&
       !hasUnmodeledSideEffects())
     return false;
 
@@ -1287,7 +1300,7 @@
 /// *all* loads the instruction does are invariant (if it does multiple loads).
 bool MachineInstr::isInvariantLoad(AliasAnalysis *AA) const {
   // If the instruction doesn't load at all, it isn't an invariant load.
-  if (!MCID->mayLoad())
+  if (!mayLoad())
     return false;
 
   // If the instruction has lost its memoperands, conservatively assume that
@@ -1340,7 +1353,7 @@
 }
 
 bool MachineInstr::hasUnmodeledSideEffects() const {
-  if (getDesc().hasUnmodeledSideEffects())
+  if (hasProperty(MCID::UnmodeledSideEffects))
     return true;
   if (isInlineAsm()) {
     unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
@@ -1468,7 +1481,7 @@
     // call instructions much less noisy on targets where calls clobber lots
     // of registers. Don't rely on MO.isDead() because we may be called before
     // LiveVariables is run, or we may be looking at a non-allocatable reg.
-    if (MF && getDesc().isCall() &&
+    if (MF && isCall() &&
         MO.isReg() && MO.isImplicit() && MO.isDef()) {
       unsigned Reg = MO.getReg();
       if (TargetRegisterInfo::isPhysicalRegister(Reg)) {

Modified: llvm/trunk/lib/CodeGen/MachineLICM.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineLICM.cpp?rev=146026&r1=146025&r2=146026&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/MachineLICM.cpp (original)
+++ llvm/trunk/lib/CodeGen/MachineLICM.cpp Wed Dec  7 01:15:52 2011
@@ -765,7 +765,7 @@
 /// isLoadFromGOTOrConstantPool - Return true if this machine instruction 
 /// loads from global offset table or constant pool.
 static bool isLoadFromGOTOrConstantPool(MachineInstr &MI) {
-  assert (MI.getDesc().mayLoad() && "Expected MI that loads!");
+  assert (MI.mayLoad() && "Expected MI that loads!");
   for (MachineInstr::mmo_iterator I = MI.memoperands_begin(),
 	 E = MI.memoperands_end(); I != E; ++I) {
     if (const Value *V = (*I)->getValue()) {
@@ -792,7 +792,7 @@
   // from constant memory are not safe to speculate all the time, for example
   // indexed load from a jump table.
   // Stores and side effects are already checked by isSafeToMove.
-  if (I.getDesc().mayLoad() && !isLoadFromGOTOrConstantPool(I) && 
+  if (I.mayLoad() && !isLoadFromGOTOrConstantPool(I) && 
       !IsGuaranteedToExecute(I.getParent()))
     return false;
 
@@ -921,7 +921,7 @@
 /// IsCheapInstruction - Return true if the instruction is marked "cheap" or
 /// the operand latency between its def and a use is one or less.
 bool MachineLICM::IsCheapInstruction(MachineInstr &MI) const {
-  if (MI.getDesc().isAsCheapAsAMove() || MI.isCopyLike())
+  if (MI.isAsCheapAsAMove() || MI.isCopyLike())
     return true;
   if (!InstrItins || InstrItins->isEmpty())
     return false;
@@ -1105,7 +1105,7 @@
 
 MachineInstr *MachineLICM::ExtractHoistableLoad(MachineInstr *MI) {
   // Don't unfold simple loads.
-  if (MI->getDesc().canFoldAsLoad())
+  if (MI->canFoldAsLoad())
     return 0;
 
   // If not, we may be able to unfold a load and hoist that.

Modified: llvm/trunk/lib/CodeGen/MachineSink.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineSink.cpp?rev=146026&r1=146025&r2=146026&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/MachineSink.cpp (original)
+++ llvm/trunk/lib/CodeGen/MachineSink.cpp Wed Dec  7 01:15:52 2011
@@ -291,7 +291,7 @@
   if (!CEBCandidates.insert(std::make_pair(From, To)))
     return true;
 
-  if (!MI->isCopy() && !MI->getDesc().isAsCheapAsAMove())
+  if (!MI->isCopy() && !MI->isAsCheapAsAMove())
     return true;
 
   // MI is cheap, we probably don't want to break the critical edge for it.

Modified: llvm/trunk/lib/CodeGen/MachineVerifier.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineVerifier.cpp?rev=146026&r1=146025&r2=146026&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/MachineVerifier.cpp (original)
+++ llvm/trunk/lib/CodeGen/MachineVerifier.cpp Wed Dec  7 01:15:52 2011
@@ -435,7 +435,7 @@
         report("MBB exits via unconditional fall-through but its successor "
                "differs from its CFG successor!", MBB);
       }
-      if (!MBB->empty() && MBB->back().getDesc().isBarrier() &&
+      if (!MBB->empty() && MBB->back().isBarrier() &&
           !TII->isPredicated(&MBB->back())) {
         report("MBB exits via unconditional fall-through but ends with a "
                "barrier instruction!", MBB);
@@ -456,10 +456,10 @@
       if (MBB->empty()) {
         report("MBB exits via unconditional branch but doesn't contain "
                "any instructions!", MBB);
-      } else if (!MBB->back().getDesc().isBarrier()) {
+      } else if (!MBB->back().isBarrier()) {
         report("MBB exits via unconditional branch but doesn't end with a "
                "barrier instruction!", MBB);
-      } else if (!MBB->back().getDesc().isTerminator()) {
+      } else if (!MBB->back().isTerminator()) {
         report("MBB exits via unconditional branch but the branch isn't a "
                "terminator instruction!", MBB);
       }
@@ -479,10 +479,10 @@
       if (MBB->empty()) {
         report("MBB exits via conditional branch/fall-through but doesn't "
                "contain any instructions!", MBB);
-      } else if (MBB->back().getDesc().isBarrier()) {
+      } else if (MBB->back().isBarrier()) {
         report("MBB exits via conditional branch/fall-through but ends with a "
                "barrier instruction!", MBB);
-      } else if (!MBB->back().getDesc().isTerminator()) {
+      } else if (!MBB->back().isTerminator()) {
         report("MBB exits via conditional branch/fall-through but the branch "
                "isn't a terminator instruction!", MBB);
       }
@@ -499,10 +499,10 @@
       if (MBB->empty()) {
         report("MBB exits via conditional branch/branch but doesn't "
                "contain any instructions!", MBB);
-      } else if (!MBB->back().getDesc().isBarrier()) {
+      } else if (!MBB->back().isBarrier()) {
         report("MBB exits via conditional branch/branch but doesn't end with a "
                "barrier instruction!", MBB);
-      } else if (!MBB->back().getDesc().isTerminator()) {
+      } else if (!MBB->back().isTerminator()) {
         report("MBB exits via conditional branch/branch but the branch "
                "isn't a terminator instruction!", MBB);
       }
@@ -555,9 +555,9 @@
   // Check the MachineMemOperands for basic consistency.
   for (MachineInstr::mmo_iterator I = MI->memoperands_begin(),
        E = MI->memoperands_end(); I != E; ++I) {
-    if ((*I)->isLoad() && !MCID.mayLoad())
+    if ((*I)->isLoad() && !MI->mayLoad())
       report("Missing mayLoad flag", MI);
-    if ((*I)->isStore() && !MCID.mayStore())
+    if ((*I)->isStore() && !MI->mayStore())
       report("Missing mayStore flag", MI);
   }
 
@@ -575,7 +575,7 @@
   }
 
   // Ensure non-terminators don't follow terminators.
-  if (MCID.isTerminator()) {
+  if (MI->isTerminator()) {
     if (!FirstTerminator)
       FirstTerminator = MI;
   } else if (FirstTerminator) {
@@ -606,7 +606,7 @@
     // Don't check if it's the last operand in a variadic instruction. See,
     // e.g., LDM_RET in the arm back end.
     if (MO->isReg() &&
-        !(MCID.isVariadic() && MONum == MCID.getNumOperands()-1)) {
+        !(MI->isVariadic() && MONum == MCID.getNumOperands()-1)) {
       if (MO->isDef() && !MCOI.isOptionalDef())
           report("Explicit operand marked as def", MO, MONum);
       if (MO->isImplicit())
@@ -614,7 +614,7 @@
     }
   } else {
     // ARM adds %reg0 operands to indicate predicates. We'll allow that.
-    if (MO->isReg() && !MO->isImplicit() && !MCID.isVariadic() && MO->getReg())
+    if (MO->isReg() && !MO->isImplicit() && !MI->isVariadic() && MO->getReg())
       report("Extra explicit operand on non-variadic instruction", MO, MONum);
   }
 
@@ -800,11 +800,11 @@
         LiveInts && !LiveInts->isNotInMIMap(MI)) {
       LiveInterval &LI = LiveStks->getInterval(MO->getIndex());
       SlotIndex Idx = LiveInts->getInstructionIndex(MI);
-      if (MCID.mayLoad() && !LI.liveAt(Idx.getRegSlot(true))) {
+      if (MI->mayLoad() && !LI.liveAt(Idx.getRegSlot(true))) {
         report("Instruction loads from dead spill slot", MO, MONum);
         *OS << "Live stack: " << LI << '\n';
       }
-      if (MCID.mayStore() && !LI.liveAt(Idx.getRegSlot())) {
+      if (MI->mayStore() && !LI.liveAt(Idx.getRegSlot())) {
         report("Instruction stores to dead spill slot", MO, MONum);
         *OS << "Live stack: " << LI << '\n';
       }

Modified: llvm/trunk/lib/CodeGen/PeepholeOptimizer.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/PeepholeOptimizer.cpp?rev=146026&r1=146025&r2=146026&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/PeepholeOptimizer.cpp (original)
+++ llvm/trunk/lib/CodeGen/PeepholeOptimizer.cpp Wed Dec  7 01:15:52 2011
@@ -292,7 +292,7 @@
   assert(Def && Src && "Malformed bitcast instruction!");
 
   MachineInstr *DefMI = MRI->getVRegDef(Src);
-  if (!DefMI || !DefMI->getDesc().isBitcast())
+  if (!DefMI || !DefMI->isBitcast())
     return false;
 
   unsigned SrcSrc = 0;
@@ -353,7 +353,7 @@
                                         SmallSet &ImmDefRegs,
                                  DenseMap &ImmDefMIs) {
   const MCInstrDesc &MCID = MI->getDesc();
-  if (!MCID.isMoveImmediate())
+  if (!MI->isMoveImmediate())
     return false;
   if (MCID.getNumDefs() != 1)
     return false;
@@ -428,9 +428,7 @@
         continue;
       }
 
-      const MCInstrDesc &MCID = MI->getDesc();
-
-      if (MCID.isBitcast()) {
+      if (MI->isBitcast()) {
         if (OptimizeBitcastInstr(MI, MBB)) {
           // MI is deleted.
           LocalMIs.erase(MI);
@@ -438,7 +436,7 @@
           MII = First ? I->begin() : llvm::next(PMII);
           continue;
         }        
-      } else if (MCID.isCompare()) {
+      } else if (MI->isCompare()) {
         if (OptimizeCmpInstr(MI, MBB)) {
           // MI is deleted.
           LocalMIs.erase(MI);

Modified: llvm/trunk/lib/CodeGen/PostRASchedulerList.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/PostRASchedulerList.cpp?rev=146026&r1=146025&r2=146026&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/PostRASchedulerList.cpp (original)
+++ llvm/trunk/lib/CodeGen/PostRASchedulerList.cpp Wed Dec  7 01:15:52 2011
@@ -364,7 +364,7 @@
     KillIndices[i] = ~0u;
 
   // Determine the live-out physregs for this block.
-  if (!BB->empty() && BB->back().getDesc().isReturn()) {
+  if (!BB->empty() && BB->back().isReturn()) {
     // In a return block, examine the function live-out regs.
     for (MachineRegisterInfo::liveout_iterator I = MRI.liveout_begin(),
            E = MRI.liveout_end(); I != E; ++I) {

Modified: llvm/trunk/lib/CodeGen/PrologEpilogInserter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/PrologEpilogInserter.cpp?rev=146026&r1=146025&r2=146026&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/PrologEpilogInserter.cpp (original)
+++ llvm/trunk/lib/CodeGen/PrologEpilogInserter.cpp Wed Dec  7 01:15:52 2011
@@ -332,7 +332,7 @@
       // Skip over all terminator instructions, which are part of the return
       // sequence.
       MachineBasicBlock::iterator I2 = I;
-      while (I2 != MBB->begin() && (--I2)->getDesc().isTerminator())
+      while (I2 != MBB->begin() && (--I2)->isTerminator())
         I = I2;
 
       bool AtStart = I == MBB->begin();
@@ -426,11 +426,11 @@
 
       // Skip over all terminator instructions, which are part of the
       // return sequence.
-      if (! I->getDesc().isTerminator()) {
+      if (! I->isTerminator()) {
         ++I;
       } else {
         MachineBasicBlock::iterator I2 = I;
-        while (I2 != MBB->begin() && (--I2)->getDesc().isTerminator())
+        while (I2 != MBB->begin() && (--I2)->isTerminator())
           I = I2;
       }
     }
@@ -698,7 +698,7 @@
   // Add epilogue to restore the callee-save registers in each exiting block
   for (MachineFunction::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I) {
     // If last instruction is a return instruction, add an epilogue
-    if (!I->empty() && I->back().getDesc().isReturn())
+    if (!I->empty() && I->back().isReturn())
       TFI.emitEpilogue(Fn, *I);
   }
 

Modified: llvm/trunk/lib/CodeGen/RegAllocFast.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/RegAllocFast.cpp?rev=146026&r1=146025&r2=146026&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/RegAllocFast.cpp (original)
+++ llvm/trunk/lib/CodeGen/RegAllocFast.cpp Wed Dec  7 01:15:52 2011
@@ -748,8 +748,8 @@
   // and return are tail calls; do not do this for them.  The tail callee need
   // not take the same registers as input that it produces as output, and there
   // are dependencies for its input registers elsewhere.
-  if (!MBB->empty() && MBB->back().getDesc().isReturn() &&
-      !MBB->back().getDesc().isCall()) {
+  if (!MBB->empty() && MBB->back().isReturn() &&
+      !MBB->back().isCall()) {
     MachineInstr *Ret = &MBB->back();
 
     for (MachineRegisterInfo::liveout_iterator
@@ -968,7 +968,7 @@
     }
 
     unsigned DefOpEnd = MI->getNumOperands();
-    if (MCID.isCall()) {
+    if (MI->isCall()) {
       // Spill all virtregs before a call. This serves two purposes: 1. If an
       // exception is thrown, the landing pad is going to expect to find
       // registers in their spill slots, and 2. we don't have to wade through

Modified: llvm/trunk/lib/CodeGen/RegisterCoalescer.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/RegisterCoalescer.cpp?rev=146026&r1=146025&r2=146026&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/RegisterCoalescer.cpp (original)
+++ llvm/trunk/lib/CodeGen/RegisterCoalescer.cpp Wed Dec  7 01:15:52 2011
@@ -643,8 +643,7 @@
   MachineInstr *DefMI = LIS->getInstructionFromIndex(AValNo->def);
   if (!DefMI)
     return false;
-  const MCInstrDesc &MCID = DefMI->getDesc();
-  if (!MCID.isCommutable())
+  if (!DefMI->isCommutable())
     return false;
   // If DefMI is a two-address instruction then commuting it will change the
   // destination register.
@@ -802,14 +801,14 @@
   if (!DefMI)
     return false;
   assert(DefMI && "Defining instruction disappeared");
-  const MCInstrDesc &MCID = DefMI->getDesc();
-  if (!MCID.isAsCheapAsAMove())
+  if (!DefMI->isAsCheapAsAMove())
     return false;
   if (!TII->isTriviallyReMaterializable(DefMI, AA))
     return false;
   bool SawStore = false;
   if (!DefMI->isSafeToMove(TII, AA, SawStore))
     return false;
+  const MCInstrDesc &MCID = DefMI->getDesc();
   if (MCID.getNumDefs() != 1)
     return false;
   if (!DefMI->isImplicitDef()) {

Modified: llvm/trunk/lib/CodeGen/ScheduleDAGInstrs.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/ScheduleDAGInstrs.cpp?rev=146026&r1=146025&r2=146026&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/ScheduleDAGInstrs.cpp (original)
+++ llvm/trunk/lib/CodeGen/ScheduleDAGInstrs.cpp Wed Dec  7 01:15:52 2011
@@ -157,7 +157,7 @@
   MachineInstr *ExitMI = InsertPos != BB->end() ? &*InsertPos : 0;
   ExitSU.setInstr(ExitMI);
   bool AllDepKnown = ExitMI &&
-    (ExitMI->getDesc().isCall() || ExitMI->getDesc().isBarrier());
+    (ExitMI->isCall() || ExitMI->isBarrier());
   if (ExitMI && AllDepKnown) {
     // If it's a call or a barrier, add dependencies on the defs and uses of
     // instruction.
@@ -238,13 +238,12 @@
       continue;
     }
 
-    const MCInstrDesc &MCID = MI->getDesc();
-    assert(!MCID.isTerminator() && !MI->isLabel() &&
+    assert(!MI->isTerminator() && !MI->isLabel() &&
            "Cannot schedule terminators or labels!");
     // Create the SUnit for this MI.
     SUnit *SU = NewSUnit(MI);
-    SU->isCall = MCID.isCall();
-    SU->isCommutable = MCID.isCommutable();
+    SU->isCall = MI->isCall();
+    SU->isCommutable = MI->isCommutable();
 
     // Assign the Latency field of SU using target-provided information.
     if (UnitLatencies)
@@ -315,7 +314,7 @@
             int RegUseIndex = UseMI->findRegisterUseOperandIdx(Reg);
             assert(RegUseIndex >= 0 && "UseMI doesn's use register!");
             if (RegUseIndex >= 0 &&
-                (UseMCID.mayLoad() || UseMCID.mayStore()) &&
+                (UseMI->mayLoad() || UseMI->mayStore()) &&
                 (unsigned)RegUseIndex < UseMCID.getNumOperands() &&
                 UseMCID.OpInfo[RegUseIndex].isLookupPtrRegClass())
               LDataLatency += SpecialAddressLatency;
@@ -419,9 +418,9 @@
     // produce more precise dependence information.
 #define STORE_LOAD_LATENCY 1
     unsigned TrueMemOrderLatency = 0;
-    if (MCID.isCall() || MI->hasUnmodeledSideEffects() ||
+    if (MI->isCall() || MI->hasUnmodeledSideEffects() ||
         (MI->hasVolatileMemoryRef() &&
-         (!MCID.mayLoad() || !MI->isInvariantLoad(AA)))) {
+         (!MI->mayLoad() || !MI->isInvariantLoad(AA)))) {
       // Be conservative with these and add dependencies on all memory
       // references, even those that are known to not alias.
       for (std::map::iterator I =
@@ -460,7 +459,7 @@
       PendingLoads.clear();
       AliasMemDefs.clear();
       AliasMemUses.clear();
-    } else if (MCID.mayStore()) {
+    } else if (MI->mayStore()) {
       bool MayAlias = true;
       TrueMemOrderLatency = STORE_LOAD_LATENCY;
       if (const Value *V = getUnderlyingObjectForInstr(MI, MFI, MayAlias)) {
@@ -516,7 +515,7 @@
                             /*Reg=*/0, /*isNormalMemory=*/false,
                             /*isMustAlias=*/false,
                             /*isArtificial=*/true));
-    } else if (MCID.mayLoad()) {
+    } else if (MI->mayLoad()) {
       bool MayAlias = true;
       TrueMemOrderLatency = 0;
       if (MI->isInvariantLoad(AA)) {
@@ -576,7 +575,7 @@
 
     // Simplistic target-independent heuristic: assume that loads take
     // extra time.
-    if (SU->getInstr()->getDesc().mayLoad())
+    if (SU->getInstr()->mayLoad())
       SU->Latency += 2;
   } else {
     SU->Latency = TII->getInstrLatency(InstrItins, SU->getInstr());

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/InstrEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/InstrEmitter.cpp?rev=146026&r1=146025&r2=146026&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/InstrEmitter.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/InstrEmitter.cpp Wed Dec  7 01:15:52 2011
@@ -294,7 +294,7 @@
     const TargetRegisterClass *DstRC = 0;
     if (IIOpNum < II->getNumOperands())
       DstRC = TII->getRegClass(*II, IIOpNum, TRI);
-    assert((DstRC || (MCID.isVariadic() && IIOpNum >= MCID.getNumOperands())) &&
+    assert((DstRC || (MI->isVariadic() && IIOpNum >= MCID.getNumOperands())) &&
            "Don't have operand info for this instruction!");
     if (DstRC && !MRI->constrainRegClass(VReg, DstRC, MinRCSize)) {
       unsigned NewVReg = MRI->createVirtualRegister(DstRC);

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp?rev=146026&r1=146025&r2=146026&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Wed Dec  7 01:15:52 2011
@@ -177,7 +177,7 @@
 
 void TargetLowering::AdjustInstrPostInstrSelection(MachineInstr *MI,
                                                    SDNode *Node) const {
-  assert(!MI->getDesc().hasPostISelHook() &&
+  assert(!MI->hasPostISelHook() &&
          "If a target marks an instruction with 'hasPostISelHook', "
          "it must implement TargetLowering::AdjustInstrPostInstrSelection!");
 }

Modified: llvm/trunk/lib/CodeGen/ShrinkWrapping.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/ShrinkWrapping.cpp?rev=146026&r1=146025&r2=146026&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/ShrinkWrapping.cpp (original)
+++ llvm/trunk/lib/CodeGen/ShrinkWrapping.cpp Wed Dec  7 01:15:52 2011
@@ -124,7 +124,7 @@
 }
 
 bool PEI::isReturnBlock(MachineBasicBlock* MBB) {
-  return (MBB && !MBB->empty() && MBB->back().getDesc().isReturn());
+  return (MBB && !MBB->empty() && MBB->back().isReturn());
 }
 
 // Initialize shrink wrapping DFA sets, called before iterations.

Modified: llvm/trunk/lib/CodeGen/SplitKit.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SplitKit.cpp?rev=146026&r1=146025&r2=146026&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SplitKit.cpp (original)
+++ llvm/trunk/lib/CodeGen/SplitKit.cpp Wed Dec  7 01:15:52 2011
@@ -80,7 +80,7 @@
     for (MachineBasicBlock::const_iterator I = MBB->end(), E = MBB->begin();
          I != E;) {
       --I;
-      if (I->getDesc().isCall()) {
+      if (I->isCall()) {
         LSP.second = LIS.getInstructionIndex(I);
         break;
       }

Modified: llvm/trunk/lib/CodeGen/TailDuplication.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/TailDuplication.cpp?rev=146026&r1=146025&r2=146026&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/TailDuplication.cpp (original)
+++ llvm/trunk/lib/CodeGen/TailDuplication.cpp Wed Dec  7 01:15:52 2011
@@ -553,7 +553,7 @@
 
   bool HasIndirectbr = false;
   if (!TailBB.empty())
-    HasIndirectbr = TailBB.back().getDesc().isIndirectBranch();
+    HasIndirectbr = TailBB.back().isIndirectBranch();
 
   if (HasIndirectbr && PreRegAlloc)
     MaxDuplicateCount = 20;
@@ -563,19 +563,19 @@
   unsigned InstrCount = 0;
   for (MachineBasicBlock::iterator I = TailBB.begin(); I != TailBB.end(); ++I) {
     // Non-duplicable things shouldn't be tail-duplicated.
-    if (I->getDesc().isNotDuplicable())
+    if (I->isNotDuplicable())
       return false;
 
     // Do not duplicate 'return' instructions if this is a pre-regalloc run.
     // A return may expand into a lot more instructions (e.g. reload of callee
     // saved registers) after PEI.
-    if (PreRegAlloc && I->getDesc().isReturn())
+    if (PreRegAlloc && I->isReturn())
       return false;
 
     // Avoid duplicating calls before register allocation. Calls presents a
     // barrier to register allocation so duplicating them may end up increasing
     // spills.
-    if (PreRegAlloc && I->getDesc().isCall())
+    if (PreRegAlloc && I->isCall())
       return false;
 
     if (!I->isPHI() && !I->isDebugValue())
@@ -610,7 +610,7 @@
     ++I;
   if (I == E)
     return true;
-  return I->getDesc().isUnconditionalBranch();
+  return I->isUnconditionalBranch();
 }
 
 static bool

Modified: llvm/trunk/lib/CodeGen/TargetInstrInfoImpl.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/TargetInstrInfoImpl.cpp?rev=146026&r1=146025&r2=146026&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/TargetInstrInfoImpl.cpp (original)
+++ llvm/trunk/lib/CodeGen/TargetInstrInfoImpl.cpp Wed Dec  7 01:15:52 2011
@@ -121,6 +121,9 @@
 bool TargetInstrInfoImpl::findCommutedOpIndices(MachineInstr *MI,
                                                 unsigned &SrcOpIdx1,
                                                 unsigned &SrcOpIdx2) const {
+  assert(MI->getOpcode() != TargetOpcode::BUNDLE &&
+         "TargetInstrInfoImpl::findCommutedOpIndices() can't handle bundles");
+
   const MCInstrDesc &MCID = MI->getDesc();
   if (!MCID.isCommutable())
     return false;
@@ -139,8 +142,12 @@
 bool TargetInstrInfoImpl::PredicateInstruction(MachineInstr *MI,
                             const SmallVectorImpl &Pred) const {
   bool MadeChange = false;
+
+  assert(MI->getOpcode() != TargetOpcode::BUNDLE &&
+         "TargetInstrInfoImpl::PredicateInstruction() can't handle bundles");
+
   const MCInstrDesc &MCID = MI->getDesc();
-  if (!MCID.isPredicable())
+  if (!MI->isPredicable())
     return false;
 
   for (unsigned j = 0, i = 0, e = MI->getNumOperands(); i != e; ++i) {
@@ -218,7 +225,7 @@
 
 MachineInstr *TargetInstrInfoImpl::duplicate(MachineInstr *Orig,
                                              MachineFunction &MF) const {
-  assert(!Orig->getDesc().isNotDuplicable() &&
+  assert(!Orig->isNotDuplicable() &&
          "Instruction cannot be duplicated");
   return MF.CloneMachineInstr(Orig);
 }
@@ -288,10 +295,10 @@
   if (MachineInstr *NewMI = foldMemoryOperandImpl(MF, MI, Ops, FI)) {
     // Add a memory operand, foldMemoryOperandImpl doesn't do that.
     assert((!(Flags & MachineMemOperand::MOStore) ||
-            NewMI->getDesc().mayStore()) &&
+            NewMI->mayStore()) &&
            "Folded a def to a non-store!");
     assert((!(Flags & MachineMemOperand::MOLoad) ||
-            NewMI->getDesc().mayLoad()) &&
+            NewMI->mayLoad()) &&
            "Folded a use to a non-load!");
     const MachineFrameInfo &MFI = *MF.getFrameInfo();
     assert(MFI.getObjectOffset(FI) != -1);
@@ -331,7 +338,7 @@
 TargetInstrInfo::foldMemoryOperand(MachineBasicBlock::iterator MI,
                                    const SmallVectorImpl &Ops,
                                    MachineInstr* LoadMI) const {
-  assert(LoadMI->getDesc().canFoldAsLoad() && "LoadMI isn't foldable!");
+  assert(LoadMI->canFoldAsLoad() && "LoadMI isn't foldable!");
 #ifndef NDEBUG
   for (unsigned i = 0, e = Ops.size(); i != e; ++i)
     assert(MI->getOperand(Ops[i]).isUse() && "Folding load into def!");
@@ -382,10 +389,8 @@
       MF.getFrameInfo()->isImmutableObjectIndex(FrameIdx))
     return true;
 
-  const MCInstrDesc &MCID = MI->getDesc();
-
   // Avoid instructions obviously unsafe for remat.
-  if (MCID.isNotDuplicable() || MCID.mayStore() ||
+  if (MI->isNotDuplicable() || MI->mayStore() ||
       MI->hasUnmodeledSideEffects())
     return false;
 
@@ -395,7 +400,7 @@
     return false;
 
   // Avoid instructions which load from potentially varying memory.
-  if (MCID.mayLoad() && !MI->isInvariantLoad(AA))
+  if (MI->mayLoad() && !MI->isInvariantLoad(AA))
     return false;
 
   // If any of the registers accessed are non-constant, conservatively assume
@@ -456,7 +461,7 @@
                                                const MachineBasicBlock *MBB,
                                                const MachineFunction &MF) const{
   // Terminators and labels can't be scheduled around.
-  if (MI->getDesc().isTerminator() || MI->isLabel())
+  if (MI->isTerminator() || MI->isLabel())
     return true;
 
   // Don't attempt to schedule around any instruction that defines

Modified: llvm/trunk/lib/CodeGen/TwoAddressInstructionPass.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/TwoAddressInstructionPass.cpp?rev=146026&r1=146025&r2=146026&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/TwoAddressInstructionPass.cpp (original)
+++ llvm/trunk/lib/CodeGen/TwoAddressInstructionPass.cpp Wed Dec  7 01:15:52 2011
@@ -242,7 +242,7 @@
   // appropriate location, we can try to sink the current instruction
   // past it.
   if (!KillMI || KillMI->getParent() != MBB || KillMI == MI ||
-      KillMI->getDesc().isTerminator())
+      KillMI->isTerminator())
     return false;
 
   // If any of the definitions are used by another instruction between the
@@ -816,10 +816,9 @@
 static bool isSafeToDelete(MachineInstr *MI,
                            const TargetInstrInfo *TII,
                            SmallVector &Kills) {
-  const MCInstrDesc &MCID = MI->getDesc();
-  if (MCID.mayStore() || MCID.isCall())
+  if (MI->mayStore() || MI->isCall())
     return false;
-  if (MCID.isTerminator() || MI->hasUnmodeledSideEffects())
+  if (MI->isTerminator() || MI->hasUnmodeledSideEffects())
     return false;
 
   for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
@@ -917,9 +916,8 @@
     // Don't mess with copies, they may be coalesced later.
     return false;
 
-  const MCInstrDesc &MCID = KillMI->getDesc();
-  if (MCID.hasUnmodeledSideEffects() || MCID.isCall() || MCID.isBranch() ||
-      MCID.isTerminator())
+  if (KillMI->hasUnmodeledSideEffects() || KillMI->isCall() ||
+      KillMI->isBranch() || KillMI->isTerminator())
     // Don't move pass calls, etc.
     return false;
 
@@ -974,9 +972,8 @@
     if (NumVisited > 10)  // FIXME: Arbitrary limit to reduce compile time cost.
       return false;
     ++NumVisited;
-    const MCInstrDesc &OMCID = OtherMI->getDesc();
-    if (OMCID.hasUnmodeledSideEffects() || OMCID.isCall() || OMCID.isBranch() ||
-        OMCID.isTerminator())
+    if (OtherMI->hasUnmodeledSideEffects() || OtherMI->isCall() ||
+        OtherMI->isBranch() || OtherMI->isTerminator())
       // Don't move pass calls, etc.
       return false;
     for (unsigned i = 0, e = OtherMI->getNumOperands(); i != e; ++i) {
@@ -1118,9 +1115,8 @@
     if (NumVisited > 10)  // FIXME: Arbitrary limit to reduce compile time cost.
       return false;
     ++NumVisited;
-    const MCInstrDesc &MCID = OtherMI->getDesc();
-    if (MCID.hasUnmodeledSideEffects() || MCID.isCall() || MCID.isBranch() ||
-        MCID.isTerminator())
+    if (OtherMI->hasUnmodeledSideEffects() || OtherMI->isCall() ||
+        OtherMI->isBranch() || OtherMI->isTerminator())
       // Don't move pass calls, etc.
       return false;
     SmallVector OtherDefs;
@@ -1200,7 +1196,6 @@
     return false;
 
   MachineInstr &MI = *mi;
-  const MCInstrDesc &MCID = MI.getDesc();
   unsigned regA = MI.getOperand(DstIdx).getReg();
   unsigned regB = MI.getOperand(SrcIdx).getReg();
 
@@ -1222,7 +1217,7 @@
   unsigned regCIdx = ~0U;
   bool TryCommute = false;
   bool AggressiveCommute = false;
-  if (MCID.isCommutable() && MI.getNumOperands() >= 3 &&
+  if (MI.isCommutable() && MI.getNumOperands() >= 3 &&
       TII->findCommutedOpIndices(&MI, SrcOp1, SrcOp2)) {
     if (SrcIdx == SrcOp1)
       regCIdx = SrcOp2;
@@ -1260,7 +1255,7 @@
   if (TargetRegisterInfo::isVirtualRegister(regA))
     ScanUses(regA, &*mbbi, Processed);
 
-  if (MCID.isConvertibleTo3Addr()) {
+  if (MI.isConvertibleTo3Addr()) {
     // This instruction is potentially convertible to a true
     // three-address instruction.  Check if it is profitable.
     if (!regBKilled || isProfitableToConv3Addr(regA, regB)) {
@@ -1287,7 +1282,7 @@
   //   movq (%rax), %rcx
   //   addq %rdx, %rcx
   // because it's preferable to schedule a load than a register copy.
-  if (MCID.mayLoad() && !regBKilled) {
+  if (MI.mayLoad() && !regBKilled) {
     // Determine if a load can be unfolded.
     unsigned LoadRegIndex;
     unsigned NewOpc =
@@ -1530,7 +1525,7 @@
           // If it's safe and profitable, remat the definition instead of
           // copying it.
           if (DefMI &&
-              DefMI->getDesc().isAsCheapAsAMove() &&
+              DefMI->isAsCheapAsAMove() &&
               DefMI->isSafeToReMat(TII, AA, regB) &&
               isProfitableToReMat(regB, rc, mi, DefMI, mbbi, Dist)){
             DEBUG(dbgs() << "2addr: REMATTING : " << *DefMI << "\n");

Modified: llvm/trunk/lib/ExecutionEngine/JIT/JITDwarfEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/ExecutionEngine/JIT/JITDwarfEmitter.cpp?rev=146026&r1=146025&r2=146026&view=diff
==============================================================================
--- llvm/trunk/lib/ExecutionEngine/JIT/JITDwarfEmitter.cpp (original)
+++ llvm/trunk/lib/ExecutionEngine/JIT/JITDwarfEmitter.cpp Wed Dec  7 01:15:52 2011
@@ -313,7 +313,7 @@
     for (MachineBasicBlock::const_iterator MI = I->begin(), E = I->end();
           MI != E; ++MI) {
       if (!MI->isLabel()) {
-        MayThrow |= MI->getDesc().isCall();
+        MayThrow |= MI->isCall();
         continue;
       }
 

Modified: llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp?rev=146026&r1=146025&r2=146026&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp Wed Dec  7 01:15:52 2011
@@ -1069,7 +1069,7 @@
   }
 
   // Try to figure out the unwinding opcode out of src / dst regs.
-  if (MI->getDesc().mayStore()) {
+  if (MI->mayStore()) {
     // Register saves.
     assert(DstReg == ARM::SP &&
            "Only stack pointer as a destination reg is supported");

Modified: llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp?rev=146026&r1=146025&r2=146026&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp Wed Dec  7 01:15:52 2011
@@ -146,7 +146,7 @@
   unsigned AddrMode = (TSFlags & ARMII::AddrModeMask);
   const MCInstrDesc &MCID = MI->getDesc();
   unsigned NumOps = MCID.getNumOperands();
-  bool isLoad = !MCID.mayStore();
+  bool isLoad = !MI->mayStore();
   const MachineOperand &WB = isLoad ? MI->getOperand(1) : MI->getOperand(0);
   const MachineOperand &Base = MI->getOperand(2);
   const MachineOperand &Offset = MI->getOperand(NumOps-3);
@@ -491,7 +491,7 @@
                                     std::vector &Pred) const {
   // FIXME: This confuses implicit_def with optional CPSR def.
   const MCInstrDesc &MCID = MI->getDesc();
-  if (!MCID.getImplicitDefs() && !MCID.hasOptionalDef())
+  if (!MCID.getImplicitDefs() && !MI->hasOptionalDef())
     return false;
 
   bool Found = false;
@@ -510,11 +510,10 @@
 /// By default, this returns true for every instruction with a
 /// PredicateOperand.
 bool ARMBaseInstrInfo::isPredicable(MachineInstr *MI) const {
-  const MCInstrDesc &MCID = MI->getDesc();
-  if (!MCID.isPredicable())
+  if (!MI->isPredicable())
     return false;
 
-  if ((MCID.TSFlags & ARMII::DomainMask) == ARMII::DomainNEON) {
+  if ((MI->getDesc().TSFlags & ARMII::DomainMask) == ARMII::DomainNEON) {
     ARMFunctionInfo *AFI =
       MI->getParent()->getParent()->getInfo();
     return AFI->isThumb2Function();
@@ -593,7 +592,7 @@
         ? 1 : ((Opc == ARM::t2TBH_JT) ? 2 : 4);
       unsigned NumOps = MCID.getNumOperands();
       MachineOperand JTOP =
-        MI->getOperand(NumOps - (MCID.isPredicable() ? 3 : 2));
+        MI->getOperand(NumOps - (MI->isPredicable() ? 3 : 2));
       unsigned JTI = JTOP.getIndex();
       const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
       assert(MJTI != 0);
@@ -845,7 +844,7 @@
 unsigned ARMBaseInstrInfo::isStoreToStackSlotPostFE(const MachineInstr *MI,
                                                     int &FrameIndex) const {
   const MachineMemOperand *Dummy;
-  return MI->getDesc().mayStore() && hasStoreToStackSlot(MI, Dummy, FrameIndex);
+  return MI->mayStore() && hasStoreToStackSlot(MI, Dummy, FrameIndex);
 }
 
 void ARMBaseInstrInfo::
@@ -991,7 +990,7 @@
 unsigned ARMBaseInstrInfo::isLoadFromStackSlotPostFE(const MachineInstr *MI,
                                              int &FrameIndex) const {
   const MachineMemOperand *Dummy;
-  return MI->getDesc().mayLoad() && hasLoadFromStackSlot(MI, Dummy, FrameIndex);
+  return MI->mayLoad() && hasLoadFromStackSlot(MI, Dummy, FrameIndex);
 }
 
 bool ARMBaseInstrInfo::expandPostRAPseudo(MachineBasicBlock::iterator MI) const{
@@ -1357,7 +1356,7 @@
     return false;
 
   // Terminators and labels can't be scheduled around.
-  if (MI->getDesc().isTerminator() || MI->isLabel())
+  if (MI->isTerminator() || MI->isLabel())
     return true;
 
   // Treat the start of the IT block as a scheduling boundary, but schedule
@@ -2339,10 +2338,10 @@
       DefMI->isRegSequence() || DefMI->isImplicitDef())
     return 1;
 
-  const MCInstrDesc &DefMCID = DefMI->getDesc();
   if (!ItinData || ItinData->isEmpty())
-    return DefMCID.mayLoad() ? 3 : 1;
+    return DefMI->mayLoad() ? 3 : 1;
 
+  const MCInstrDesc &DefMCID = DefMI->getDesc();
   const MCInstrDesc &UseMCID = UseMI->getDesc();
   const MachineOperand &DefMO = DefMI->getOperand(DefIdx);
   if (DefMO.getReg() == ARM::CPSR) {
@@ -2352,7 +2351,7 @@
     }
 
     // CPSR set and branch can be paired in the same cycle.
-    if (UseMCID.isBranch())
+    if (UseMI->isBranch())
       return 0;
   }
 

Modified: llvm/trunk/lib/Target/ARM/ARMConstantIslandPass.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMConstantIslandPass.cpp?rev=146026&r1=146025&r2=146026&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMConstantIslandPass.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMConstantIslandPass.cpp Wed Dec  7 01:15:52 2011
@@ -495,7 +495,7 @@
 
     for (MachineBasicBlock::iterator I = MBB.begin(), E = MBB.end();
          I != E; ++I)
-      if (I->getDesc().isBranch() && I->getOpcode() == ARM::t2BR_JT)
+      if (I->isBranch() && I->getOpcode() == ARM::t2BR_JT)
         T2JumpTables.push_back(I);
   }
 }
@@ -547,7 +547,7 @@
         BBI.Unalign = isThumb ? 1 : 2;
 
       int Opc = I->getOpcode();
-      if (I->getDesc().isBranch()) {
+      if (I->isBranch()) {
         bool isCond = false;
         unsigned Bits = 0;
         unsigned Scale = 1;
@@ -1738,7 +1738,7 @@
     MachineInstr *MI = T2JumpTables[i];
     const MCInstrDesc &MCID = MI->getDesc();
     unsigned NumOps = MCID.getNumOperands();
-    unsigned JTOpIdx = NumOps - (MCID.isPredicable() ? 3 : 2);
+    unsigned JTOpIdx = NumOps - (MI->isPredicable() ? 3 : 2);
     MachineOperand JTOP = MI->getOperand(JTOpIdx);
     unsigned JTI = JTOP.getIndex();
     assert(JTI < JT.size());
@@ -1861,7 +1861,7 @@
     MachineInstr *MI = T2JumpTables[i];
     const MCInstrDesc &MCID = MI->getDesc();
     unsigned NumOps = MCID.getNumOperands();
-    unsigned JTOpIdx = NumOps - (MCID.isPredicable() ? 3 : 2);
+    unsigned JTOpIdx = NumOps - (MI->isPredicable() ? 3 : 2);
     MachineOperand JTOP = MI->getOperand(JTOpIdx);
     unsigned JTI = JTOP.getIndex();
     assert(JTI < JT.size());

Modified: llvm/trunk/lib/Target/ARM/ARMFastISel.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMFastISel.cpp?rev=146026&r1=146025&r2=146026&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMFastISel.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMFastISel.cpp Wed Dec  7 01:15:52 2011
@@ -228,8 +228,7 @@
 // we don't care about implicit defs here, just places we'll need to add a
 // default CCReg argument. Sets CPSR if we're setting CPSR instead of CCR.
 bool ARMFastISel::DefinesOptionalPredicate(MachineInstr *MI, bool *CPSR) {
-  const MCInstrDesc &MCID = MI->getDesc();
-  if (!MCID.hasOptionalDef())
+  if (!MI->hasOptionalDef())
     return false;
 
   // Look to see if our OptionalDef is defining CPSR or CCR.

Modified: llvm/trunk/lib/Target/ARM/ARMFrameLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMFrameLowering.cpp?rev=146026&r1=146025&r2=146026&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMFrameLowering.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMFrameLowering.cpp Wed Dec  7 01:15:52 2011
@@ -310,8 +310,7 @@
 void ARMFrameLowering::emitEpilogue(MachineFunction &MF,
                                     MachineBasicBlock &MBB) const {
   MachineBasicBlock::iterator MBBI = MBB.getLastNonDebugInstr();
-  assert(MBBI->getDesc().isReturn() &&
-         "Can only insert epilog into returning blocks");
+  assert(MBBI->isReturn() && "Can only insert epilog into returning blocks");
   unsigned RetOpcode = MBBI->getOpcode();
   DebugLoc dl = MBBI->getDebugLoc();
   MachineFrameInfo *MFI = MF.getFrameInfo();

Modified: llvm/trunk/lib/Target/ARM/ARMHazardRecognizer.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMHazardRecognizer.cpp?rev=146026&r1=146025&r2=146026&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMHazardRecognizer.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMHazardRecognizer.cpp Wed Dec  7 01:15:52 2011
@@ -21,7 +21,7 @@
   // FIXME: Detect integer instructions properly.
   const MCInstrDesc &MCID = MI->getDesc();
   unsigned Domain = MCID.TSFlags & ARMII::DomainMask;
-  if (MCID.mayStore())
+  if (MI->mayStore())
     return false;
   unsigned Opcode = MCID.getOpcode();
   if (Opcode == ARM::VMOVRS || Opcode == ARM::VMOVRRD)
@@ -48,9 +48,9 @@
       MachineInstr *DefMI = LastMI;
       const MCInstrDesc &LastMCID = LastMI->getDesc();
       // Skip over one non-VFP / NEON instruction.
-      if (!LastMCID.isBarrier() &&
+      if (!LastMI->isBarrier() &&
           // On A9, AGU and NEON/FPU are muxed.
-          !(STI.isCortexA9() && (LastMCID.mayLoad() || LastMCID.mayStore())) &&
+          !(STI.isCortexA9() && (LastMI->mayLoad() || LastMI->mayStore())) &&
           (LastMCID.TSFlags & ARMII::DomainMask) == ARMII::DomainGeneral) {
         MachineBasicBlock::iterator I = LastMI;
         if (I != LastMI->getParent()->begin()) {

Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp?rev=146026&r1=146025&r2=146026&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp Wed Dec  7 01:15:52 2011
@@ -6015,7 +6015,7 @@
     // executed.
     for (MachineBasicBlock::reverse_iterator
            II = BB->rbegin(), IE = BB->rend(); II != IE; ++II) {
-      if (!II->getDesc().isCall()) continue;
+      if (!II->isCall()) continue;
 
       DenseMap DefRegs;
       for (MachineInstr::mop_iterator
@@ -6426,13 +6426,13 @@
 
 void ARMTargetLowering::AdjustInstrPostInstrSelection(MachineInstr *MI,
                                                       SDNode *Node) const {
-  const MCInstrDesc *MCID = &MI->getDesc();
-  if (!MCID->hasPostISelHook()) {
+  if (!MI->hasPostISelHook()) {
     assert(!convertAddSubFlagsOpcode(MI->getOpcode()) &&
            "Pseudo flag-setting opcodes must be marked with 'hasPostISelHook'");
     return;
   }
 
+  const MCInstrDesc *MCID = &MI->getDesc();
   // Adjust potentially 's' setting instructions after isel, i.e. ADC, SBC, RSB,
   // RSC. Coming out of isel, they have an implicit CPSR def, but the optional
   // operand is still set to noreg. If needed, set the optional operand's
@@ -6459,7 +6459,7 @@
 
   // Any ARM instruction that sets the 's' bit should specify an optional
   // "cc_out" operand in the last operand position.
-  if (!MCID->hasOptionalDef() || !MCID->OpInfo[ccOutIdx].isOptionalDef()) {
+  if (!MI->hasOptionalDef() || !MCID->OpInfo[ccOutIdx].isOptionalDef()) {
     assert(!NewOpc && "Optional cc_out operand required");
     return;
   }

Modified: llvm/trunk/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMLoadStoreOptimizer.cpp?rev=146026&r1=146025&r2=146026&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMLoadStoreOptimizer.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMLoadStoreOptimizer.cpp Wed Dec  7 01:15:52 2011
@@ -1472,19 +1472,18 @@
   while (++I != E) {
     if (I->isDebugValue() || MemOps.count(&*I))
       continue;
-    const MCInstrDesc &MCID = I->getDesc();
-    if (MCID.isCall() || MCID.isTerminator() || I->hasUnmodeledSideEffects())
+    if (I->isCall() || I->isTerminator() || I->hasUnmodeledSideEffects())
       return false;
-    if (isLd && MCID.mayStore())
+    if (isLd && I->mayStore())
       return false;
     if (!isLd) {
-      if (MCID.mayLoad())
+      if (I->mayLoad())
         return false;
       // It's not safe to move the first 'str' down.
       // str r1, [r0]
       // strh r5, [r0]
       // str r4, [r0, #+4]
-      if (MCID.mayStore())
+      if (I->mayStore())
         return false;
     }
     for (unsigned j = 0, NumOps = I->getNumOperands(); j != NumOps; ++j) {
@@ -1774,8 +1773,7 @@
   while (MBBI != E) {
     for (; MBBI != E; ++MBBI) {
       MachineInstr *MI = MBBI;
-      const MCInstrDesc &MCID = MI->getDesc();
-      if (MCID.isCall() || MCID.isTerminator()) {
+      if (MI->isCall() || MI->isTerminator()) {
         // Stop at barriers.
         ++MBBI;
         break;

Modified: llvm/trunk/lib/Target/ARM/MLxExpansionPass.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/MLxExpansionPass.cpp?rev=146026&r1=146025&r2=146026&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/MLxExpansionPass.cpp (original)
+++ llvm/trunk/lib/Target/ARM/MLxExpansionPass.cpp Wed Dec  7 01:15:52 2011
@@ -139,7 +139,7 @@
   // FIXME: Detect integer instructions properly.
   const MCInstrDesc &MCID = MI->getDesc();
   unsigned Domain = MCID.TSFlags & ARMII::DomainMask;
-  if (MCID.mayStore())
+  if (MI->mayStore())
     return false;
   unsigned Opcode = MCID.getOpcode();
   if (Opcode == ARM::VMOVRS || Opcode == ARM::VMOVRRD)
@@ -274,7 +274,7 @@
     }
 
     const MCInstrDesc &MCID = MI->getDesc();
-    if (MCID.isBarrier()) {
+    if (MI->isBarrier()) {
       clearStack();
       Skip = 0;
       ++MII;

Modified: llvm/trunk/lib/Target/ARM/Thumb1RegisterInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Thumb1RegisterInfo.cpp?rev=146026&r1=146025&r2=146026&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/Thumb1RegisterInfo.cpp (original)
+++ llvm/trunk/lib/Target/ARM/Thumb1RegisterInfo.cpp Wed Dec  7 01:15:52 2011
@@ -643,14 +643,13 @@
   assert(Offset && "This code isn't needed if offset already handled!");
 
   unsigned Opcode = MI.getOpcode();
-  const MCInstrDesc &Desc = MI.getDesc();
 
   // Remove predicate first.
   int PIdx = MI.findFirstPredOperandIdx();
   if (PIdx != -1)
     removeOperands(MI, PIdx);
 
-  if (Desc.mayLoad()) {
+  if (MI.mayLoad()) {
     // Use the destination register to materialize sp + offset.
     unsigned TmpReg = MI.getOperand(0).getReg();
     bool UseRR = false;
@@ -673,7 +672,7 @@
       // Use [reg, reg] addrmode. Replace the immediate operand w/ the frame
       // register. The offset is already handled in the vreg value.
       MI.getOperand(i+1).ChangeToRegister(FrameReg, false, false, false);
-  } else if (Desc.mayStore()) {
+  } else if (MI.mayStore()) {
       VReg = MF.getRegInfo().createVirtualRegister(ARM::tGPRRegisterClass);
       bool UseRR = false;
 
@@ -699,7 +698,7 @@
   }
 
   // Add predicate back if it's needed.
-  if (MI.getDesc().isPredicable()) {
+  if (MI.isPredicable()) {
     MachineInstrBuilder MIB(&MI);
     AddDefaultPred(MIB);
   }

Modified: llvm/trunk/lib/Target/ARM/Thumb2ITBlockPass.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Thumb2ITBlockPass.cpp?rev=146026&r1=146025&r2=146026&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/Thumb2ITBlockPass.cpp (original)
+++ llvm/trunk/lib/Target/ARM/Thumb2ITBlockPass.cpp Wed Dec  7 01:15:52 2011
@@ -141,7 +141,7 @@
   //   rsb   r2, 0
   //
   const MCInstrDesc &MCID = MI->getDesc();
-  if (MCID.hasOptionalDef() &&
+  if (MI->hasOptionalDef() &&
       MI->getOperand(MCID.getNumOperands() - 1).getReg() == ARM::CPSR)
     return false;
 
@@ -198,7 +198,7 @@
     // Branches, including tricky ones like LDM_RET, need to end an IT
     // block so check the instruction we just put in the block.
     for (; MBBI != E && Pos &&
-           (!MI->getDesc().isBranch() && !MI->getDesc().isReturn()) ; ++MBBI) {
+           (!MI->isBranch() && !MI->isReturn()) ; ++MBBI) {
       if (MBBI->isDebugValue())
         continue;
 

Modified: llvm/trunk/lib/Target/ARM/Thumb2SizeReduction.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Thumb2SizeReduction.cpp?rev=146026&r1=146025&r2=146026&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/Thumb2SizeReduction.cpp (original)
+++ llvm/trunk/lib/Target/ARM/Thumb2SizeReduction.cpp Wed Dec  7 01:15:52 2011
@@ -533,8 +533,7 @@
   if (Entry.LowRegs1 && !VerifyLowRegs(MI))
     return false;
 
-  const MCInstrDesc &MCID = MI->getDesc();
-  if (MCID.mayLoad() || MCID.mayStore())
+  if (MI->mayLoad() || MI->mayStore())
     return ReduceLoadStore(MBB, MI, Entry);
 
   switch (Opc) {
@@ -877,7 +876,7 @@
   ProcessNext:
     bool DefCPSR = false;
     LiveCPSR = UpdateCPSRDef(*MI, LiveCPSR, DefCPSR);
-    if (MI->getDesc().isCall()) {
+    if (MI->isCall()) {
       // Calls don't really set CPSR.
       CPSRDef = 0;
       IsSelfLoop = false;

Modified: llvm/trunk/lib/Target/MBlaze/MBlazeAsmPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MBlaze/MBlazeAsmPrinter.cpp?rev=146026&r1=146025&r2=146026&view=diff
==============================================================================
--- llvm/trunk/lib/Target/MBlaze/MBlazeAsmPrinter.cpp (original)
+++ llvm/trunk/lib/Target/MBlaze/MBlazeAsmPrinter.cpp Wed Dec  7 01:15:52 2011
@@ -310,9 +310,9 @@
 
   // Check if the last terminator is an unconditional branch.
   MachineBasicBlock::const_iterator I = Pred->end();
-  while (I != Pred->begin() && !(--I)->getDesc().isTerminator())
+  while (I != Pred->begin() && !(--I)->isTerminator())
     ; // Noop
-  return I == Pred->end() || !I->getDesc().isBarrier();
+  return I == Pred->end() || !I->isBarrier();
 }
 
 // Force static initialization.

Modified: llvm/trunk/lib/Target/MBlaze/MBlazeDelaySlotFiller.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MBlaze/MBlazeDelaySlotFiller.cpp?rev=146026&r1=146025&r2=146026&view=diff
==============================================================================
--- llvm/trunk/lib/Target/MBlaze/MBlazeDelaySlotFiller.cpp (original)
+++ llvm/trunk/lib/Target/MBlaze/MBlazeDelaySlotFiller.cpp Wed Dec  7 01:15:52 2011
@@ -107,7 +107,6 @@
   // Hazard check
   MachineBasicBlock::iterator a = candidate;
   MachineBasicBlock::iterator b = slot;
-  MCInstrDesc desc = candidate->getDesc();
 
   // MBB layout:-
   //    candidate := a0 = operation(a1, a2)
@@ -121,7 +120,7 @@
   // 4. b0 is one or more of {a1, a2}
   // 5. a accesses memory, and the middle bit
   //    contains a store operation.
-  bool a_is_memory = desc.mayLoad() || desc.mayStore();
+  bool a_is_memory = candidate->mayLoad() || candidate->mayStore();
 
   // Determine the number of operands in the slot instruction and in the
   // candidate instruction.
@@ -154,7 +153,7 @@
     }
 
     // Check hazard type 5
-    if (a_is_memory && m->getDesc().mayStore())
+    if (a_is_memory && m->mayStore())
       return true;
   }
 
@@ -181,8 +180,8 @@
   if (candidate == MBB.begin())
     return false;
 
-  MCInstrDesc brdesc = (--candidate)->getDesc();
-  return (brdesc.hasDelaySlot());
+  --candidate;
+  return (candidate->hasDelaySlot());
 }
 
 static bool hasUnknownSideEffects(MachineBasicBlock::iterator &I) {
@@ -209,9 +208,8 @@
       break;
 
     --I;
-    MCInstrDesc desc = I->getDesc();
-    if (desc.hasDelaySlot() || desc.isBranch() || isDelayFiller(MBB,I) ||
-        desc.isCall() || desc.isReturn() || desc.isBarrier() ||
+    if (I->hasDelaySlot() || I->isBranch() || isDelayFiller(MBB,I) ||
+        I->isCall() || I->isReturn() || I->isBarrier() ||
         hasUnknownSideEffects(I))
       break;
 
@@ -230,7 +228,7 @@
 bool Filler::runOnMachineBasicBlock(MachineBasicBlock &MBB) {
   bool Changed = false;
   for (MachineBasicBlock::iterator I = MBB.begin(); I != MBB.end(); ++I)
-    if (I->getDesc().hasDelaySlot()) {
+    if (I->hasDelaySlot()) {
       MachineBasicBlock::iterator D = MBB.end();
       MachineBasicBlock::iterator J = I;
 

Modified: llvm/trunk/lib/Target/MSP430/MSP430FrameLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MSP430/MSP430FrameLowering.cpp?rev=146026&r1=146025&r2=146026&view=diff
==============================================================================
--- llvm/trunk/lib/Target/MSP430/MSP430FrameLowering.cpp (original)
+++ llvm/trunk/lib/Target/MSP430/MSP430FrameLowering.cpp Wed Dec  7 01:15:52 2011
@@ -140,7 +140,7 @@
   while (MBBI != MBB.begin()) {
     MachineBasicBlock::iterator PI = prior(MBBI);
     unsigned Opc = PI->getOpcode();
-    if (Opc != MSP430::POP16r && !PI->getDesc().isTerminator())
+    if (Opc != MSP430::POP16r && !PI->isTerminator())
       break;
     --MBBI;
   }

Modified: llvm/trunk/lib/Target/MSP430/MSP430InstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MSP430/MSP430InstrInfo.cpp?rev=146026&r1=146025&r2=146026&view=diff
==============================================================================
--- llvm/trunk/lib/Target/MSP430/MSP430InstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/MSP430/MSP430InstrInfo.cpp Wed Dec  7 01:15:52 2011
@@ -158,13 +158,12 @@
 }
 
 bool MSP430InstrInfo::isUnpredicatedTerminator(const MachineInstr *MI) const {
-  const MCInstrDesc &MCID = MI->getDesc();
-  if (!MCID.isTerminator()) return false;
+  if (!MI->isTerminator()) return false;
 
   // Conditional branch is a special case.
-  if (MCID.isBranch() && !MCID.isBarrier())
+  if (MI->isBranch() && !MI->isBarrier())
     return true;
-  if (!MCID.isPredicable())
+  if (!MI->isPredicable())
     return true;
   return !isPredicated(MI);
 }
@@ -189,7 +188,7 @@
 
     // A terminator that isn't a branch can't easily be handled
     // by this analysis.
-    if (!I->getDesc().isBranch())
+    if (!I->isBranch())
       return true;
 
     // Cannot handle indirect branches.

Modified: llvm/trunk/lib/Target/Mips/MipsAsmPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsAsmPrinter.cpp?rev=146026&r1=146025&r2=146026&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsAsmPrinter.cpp (original)
+++ llvm/trunk/lib/Target/Mips/MipsAsmPrinter.cpp Wed Dec  7 01:15:52 2011
@@ -317,9 +317,9 @@
   // Otherwise, check the last instruction.
   // Check if the last terminator is an unconditional branch.
   MachineBasicBlock::const_iterator I = Pred->end();
-  while (I != Pred->begin() && !(--I)->getDesc().isTerminator()) ;
+  while (I != Pred->begin() && !(--I)->isTerminator()) ;
 
-  return !I->getDesc().isBarrier();
+  return !I->isBarrier();
 }
 
 // Print out an operand for an inline asm expression.

Modified: llvm/trunk/lib/Target/Mips/MipsCodeEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsCodeEmitter.cpp?rev=146026&r1=146025&r2=146026&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsCodeEmitter.cpp (original)
+++ llvm/trunk/lib/Target/Mips/MipsCodeEmitter.cpp Wed Dec  7 01:15:52 2011
@@ -161,7 +161,7 @@
   if (Form == MipsII::FrmJ)
     return Mips::reloc_mips_26;
   if ((Form == MipsII::FrmI || Form == MipsII::FrmFI)
-       && MI.getDesc().isBranch())
+       && MI.isBranch())
     return Mips::reloc_mips_branch;
   if (Form == MipsII::FrmI && MI.getOpcode() == Mips::LUi)
     return Mips::reloc_mips_hi;

Modified: llvm/trunk/lib/Target/Mips/MipsDelaySlotFiller.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsDelaySlotFiller.cpp?rev=146026&r1=146025&r2=146026&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsDelaySlotFiller.cpp (original)
+++ llvm/trunk/lib/Target/Mips/MipsDelaySlotFiller.cpp Wed Dec  7 01:15:52 2011
@@ -96,7 +96,7 @@
   LastFiller = MBB.end();
 
   for (MachineBasicBlock::iterator I = MBB.begin(); I != MBB.end(); ++I)
-    if (I->getDesc().hasDelaySlot()) {
+    if (I->hasDelaySlot()) {
       ++FilledSlots;
       Changed = true;
 
@@ -146,7 +146,7 @@
         || I->isInlineAsm()
         || I->isLabel()
         || FI == LastFiller
-        || I->getDesc().isPseudo()
+        || I->isPseudo()
         //
         // Should not allow:
         // ERET, DERET or WAIT, PAUSE. Need to add these to instruction
@@ -174,16 +174,15 @@
   if (candidate->isImplicitDef() || candidate->isKill())
     return true;
 
-  MCInstrDesc MCID = candidate->getDesc();
   // Loads or stores cannot be moved past a store to the delay slot
   // and stores cannot be moved past a load. 
-  if (MCID.mayLoad()) {
+  if (candidate->mayLoad()) {
     if (sawStore)
       return true;
     sawLoad = true;
   }
 
-  if (MCID.mayStore()) {
+  if (candidate->mayStore()) {
     if (sawStore)
       return true;
     sawStore = true;
@@ -191,7 +190,7 @@
       return true;
   }
 
-  assert((!MCID.isCall() && !MCID.isReturn()) &&
+  assert((!candidate->isCall() && !candidate->isReturn()) &&
          "Cannot put calls or returns in delay slot.");
 
   for (unsigned i = 0, e = candidate->getNumOperands(); i!= e; ++i) {
@@ -221,11 +220,11 @@
                             SmallSet& RegUses) {
   // If MI is a call or return, just examine the explicit non-variadic operands.
   MCInstrDesc MCID = MI->getDesc();
-  unsigned e = MCID.isCall() || MCID.isReturn() ? MCID.getNumOperands() :
-                                                  MI->getNumOperands();
+  unsigned e = MI->isCall() || MI->isReturn() ? MCID.getNumOperands() :
+                                                MI->getNumOperands();
   
   // Add RA to RegDefs to prevent users of RA from going into delay slot. 
-  if (MCID.isCall())
+  if (MI->isCall())
     RegDefs.insert(Mips::RA);
 
   for (unsigned i = 0; i != e; ++i) {

Modified: llvm/trunk/lib/Target/PTX/PTXInstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PTX/PTXInstrInfo.cpp?rev=146026&r1=146025&r2=146026&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PTX/PTXInstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/PTX/PTXInstrInfo.cpp Wed Dec  7 01:15:52 2011
@@ -116,7 +116,7 @@
 }
 
 bool PTXInstrInfo::isUnpredicatedTerminator(const MachineInstr *MI) const {
-  return !isPredicated(MI) && get(MI->getOpcode()).isTerminator();
+  return !isPredicated(MI) && MI->isTerminator();
 }
 
 bool PTXInstrInfo::
@@ -186,13 +186,11 @@
 
   MachineBasicBlock::iterator iter = MBB.end();
   const MachineInstr& instLast1 = *--iter;
-  const MCInstrDesc &desc1 = instLast1.getDesc();
   // for special case that MBB has only 1 instruction
   const bool IsSizeOne = MBB.size() == 1;
   // if IsSizeOne is true, *--iter and instLast2 are invalid
   // we put a dummy value in instLast2 and desc2 since they are used
   const MachineInstr& instLast2 = IsSizeOne ? instLast1 : *--iter;
-  const MCInstrDesc &desc2 = IsSizeOne ? desc1 : instLast2.getDesc();
 
   DEBUG(dbgs() << "\n");
   DEBUG(dbgs() << "AnalyzeBranch: opcode: " << instLast1.getOpcode() << "\n");
@@ -207,7 +205,7 @@
   }
 
   // this block ends with only an unconditional branch
-  if (desc1.isUnconditionalBranch() &&
+  if (instLast1.isUnconditionalBranch() &&
       // when IsSizeOne is true, it "absorbs" the evaluation of instLast2
       (IsSizeOne || !IsAnyKindOfBranch(instLast2))) {
     DEBUG(dbgs() << "AnalyzeBranch: ends with only uncond branch\n");
@@ -217,7 +215,7 @@
 
   // this block ends with a conditional branch and
   // it falls through to a successor block
-  if (desc1.isConditionalBranch() &&
+  if (instLast1.isConditionalBranch() &&
       IsAnySuccessorAlsoLayoutSuccessor(MBB)) {
     DEBUG(dbgs() << "AnalyzeBranch: ends with cond branch and fall through\n");
     TBB = GetBranchTarget(instLast1);
@@ -233,8 +231,8 @@
 
   // this block ends with a conditional branch
   // followed by an unconditional branch
-  if (desc2.isConditionalBranch() &&
-      desc1.isUnconditionalBranch()) {
+  if (instLast2.isConditionalBranch() &&
+      instLast1.isUnconditionalBranch()) {
     DEBUG(dbgs() << "AnalyzeBranch: ends with cond and uncond branch\n");
     TBB = GetBranchTarget(instLast2);
     FBB = GetBranchTarget(instLast1);
@@ -341,8 +339,7 @@
 }
 
 bool PTXInstrInfo::IsAnyKindOfBranch(const MachineInstr& inst) {
-  const MCInstrDesc &desc = inst.getDesc();
-  return desc.isTerminator() || desc.isBranch() || desc.isIndirectBranch();
+  return inst.isTerminator() || inst.isBranch() || inst.isIndirectBranch();
 }
 
 bool PTXInstrInfo::

Modified: llvm/trunk/lib/Target/PowerPC/PPCFrameLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCFrameLowering.cpp?rev=146026&r1=146025&r2=146026&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCFrameLowering.cpp (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCFrameLowering.cpp Wed Dec  7 01:15:52 2011
@@ -64,7 +64,7 @@
   // epilog blocks.
   for (MachineFunction::iterator I = MF->begin(), E = MF->end(); I != E; ++I) {
     // If last instruction is a return instruction, add an epilogue
-    if (!I->empty() && I->back().getDesc().isReturn()) {
+    if (!I->empty() && I->back().isReturn()) {
       bool FoundIt = false;
       for (MBBI = I->end(); MBBI != I->begin(); ) {
         --MBBI;

Modified: llvm/trunk/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCISelDAGToDAG.cpp?rev=146026&r1=146025&r2=146026&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCISelDAGToDAG.cpp (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCISelDAGToDAG.cpp Wed Dec  7 01:15:52 2011
@@ -210,13 +210,13 @@
 
   // Find all return blocks, outputting a restore in each epilog.
   for (MachineFunction::iterator BB = Fn.begin(), E = Fn.end(); BB != E; ++BB) {
-    if (!BB->empty() && BB->back().getDesc().isReturn()) {
+    if (!BB->empty() && BB->back().isReturn()) {
       IP = BB->end(); --IP;
 
       // Skip over all terminator instructions, which are part of the return
       // sequence.
       MachineBasicBlock::iterator I2 = IP;
-      while (I2 != BB->begin() && (--I2)->getDesc().isTerminator())
+      while (I2 != BB->begin() && (--I2)->isTerminator())
         IP = I2;
 
       // Emit: MTVRSAVE InVRSave

Modified: llvm/trunk/lib/Target/Sparc/DelaySlotFiller.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/DelaySlotFiller.cpp?rev=146026&r1=146025&r2=146026&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Sparc/DelaySlotFiller.cpp (original)
+++ llvm/trunk/lib/Target/Sparc/DelaySlotFiller.cpp Wed Dec  7 01:15:52 2011
@@ -100,7 +100,7 @@
   bool Changed = false;
 
   for (MachineBasicBlock::iterator I = MBB.begin(); I != MBB.end(); ++I)
-    if (I->getDesc().hasDelaySlot()) {
+    if (I->hasDelaySlot()) {
       MachineBasicBlock::iterator D = MBB.end();
       MachineBasicBlock::iterator J = I;
 
@@ -149,7 +149,7 @@
   }
 
   //Call's delay filler can def some of call's uses.
-  if (slot->getDesc().isCall())
+  if (slot->isCall())
     insertCallUses(slot, RegUses);
   else
     insertDefsUses(slot, RegDefs, RegUses);
@@ -170,7 +170,7 @@
     if (I->hasUnmodeledSideEffects()
         || I->isInlineAsm()
         || I->isLabel()
-        || I->getDesc().hasDelaySlot()
+        || I->hasDelaySlot()
         || isDelayFiller(MBB, I))
       break;
 
@@ -194,13 +194,13 @@
   if (candidate->isImplicitDef() || candidate->isKill())
     return true;
 
-  if (candidate->getDesc().mayLoad()) {
+  if (candidate->mayLoad()) {
     sawLoad = true;
     if (sawStore)
       return true;
   }
 
-  if (candidate->getDesc().mayStore()) {
+  if (candidate->mayStore()) {
     if (sawStore)
       return true;
     sawStore = true;
@@ -298,13 +298,13 @@
     return false;
   if (candidate->getOpcode() == SP::UNIMP)
     return true;
-  const MCInstrDesc &prevdesc = (--candidate)->getDesc();
-  return prevdesc.hasDelaySlot();
+  --candidate;
+  return candidate->hasDelaySlot();
 }
 
 bool Filler::needsUnimp(MachineBasicBlock::iterator I, unsigned &StructSize)
 {
-  if (!I->getDesc().isCall())
+  if (!I->isCall())
     return false;
 
   unsigned structSizeOpNum = 0;

Modified: llvm/trunk/lib/Target/Sparc/SparcAsmPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/SparcAsmPrinter.cpp?rev=146026&r1=146025&r2=146026&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Sparc/SparcAsmPrinter.cpp (original)
+++ llvm/trunk/lib/Target/Sparc/SparcAsmPrinter.cpp Wed Dec  7 01:15:52 2011
@@ -236,9 +236,9 @@
   
   // Check if the last terminator is an unconditional branch.
   MachineBasicBlock::const_iterator I = Pred->end();
-  while (I != Pred->begin() && !(--I)->getDesc().isTerminator())
+  while (I != Pred->begin() && !(--I)->isTerminator())
     ; // Noop
-  return I == Pred->end() || !I->getDesc().isBarrier();
+  return I == Pred->end() || !I->isBarrier();
 }
 
 

Modified: llvm/trunk/lib/Target/Sparc/SparcInstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/SparcInstrInfo.cpp?rev=146026&r1=146025&r2=146026&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Sparc/SparcInstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/Sparc/SparcInstrInfo.cpp Wed Dec  7 01:15:52 2011
@@ -133,7 +133,7 @@
       break;
 
     //Terminator is not a branch
-    if (!I->getDesc().isBranch())
+    if (!I->isBranch())
       return true;
 
     //Handle Unconditional branches

Modified: llvm/trunk/lib/Target/TargetInstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/TargetInstrInfo.cpp?rev=146026&r1=146025&r2=146026&view=diff
==============================================================================
--- llvm/trunk/lib/Target/TargetInstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/TargetInstrInfo.cpp Wed Dec  7 01:15:52 2011
@@ -130,13 +130,12 @@
 
 
 bool TargetInstrInfo::isUnpredicatedTerminator(const MachineInstr *MI) const {
-  const MCInstrDesc &MCID = MI->getDesc();
-  if (!MCID.isTerminator()) return false;
+  if (!MI->isTerminator()) return false;
 
   // Conditional branch is a special case.
-  if (MCID.isBranch() && !MCID.isBarrier())
+  if (MI->isBranch() && !MI->isBarrier())
     return true;
-  if (!MCID.isPredicable())
+  if (!MI->isPredicable())
     return true;
   return !isPredicated(MI);
 }

Modified: llvm/trunk/lib/Target/X86/X86CodeEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86CodeEmitter.cpp?rev=146026&r1=146025&r2=146026&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86CodeEmitter.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86CodeEmitter.cpp Wed Dec  7 01:15:52 2011
@@ -1004,7 +1004,7 @@
     break;
   }
 
-  if (!Desc->isVariadic() && CurOp != NumOps) {
+  if (!MI.isVariadic() && CurOp != NumOps) {
 #ifndef NDEBUG
     dbgs() << "Cannot encode all operands of: " << MI << "\n";
 #endif

Modified: llvm/trunk/lib/Target/X86/X86FrameLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86FrameLowering.cpp?rev=146026&r1=146025&r2=146026&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86FrameLowering.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86FrameLowering.cpp Wed Dec  7 01:15:52 2011
@@ -991,7 +991,7 @@
     unsigned Opc = PI->getOpcode();
 
     if (Opc != X86::POP32r && Opc != X86::POP64r && Opc != X86::DBG_VALUE &&
-        !PI->getDesc().isTerminator())
+        !PI->isTerminator())
       break;
 
     --MBBI;

Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.cpp?rev=146026&r1=146025&r2=146026&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86InstrInfo.cpp Wed Dec  7 01:15:52 2011
@@ -2040,13 +2040,12 @@
 }
 
 bool X86InstrInfo::isUnpredicatedTerminator(const MachineInstr *MI) const {
-  const MCInstrDesc &MCID = MI->getDesc();
-  if (!MCID.isTerminator()) return false;
+  if (!MI->isTerminator()) return false;
 
   // Conditional branch is a special case.
-  if (MCID.isBranch() && !MCID.isBarrier())
+  if (MI->isBranch() && !MI->isBarrier())
     return true;
-  if (!MCID.isPredicable())
+  if (!MI->isPredicable())
     return true;
   return !isPredicated(MI);
 }
@@ -2072,7 +2071,7 @@
 
     // A terminator that isn't a branch can't easily be handled by this
     // analysis.
-    if (!I->getDesc().isBranch())
+    if (!I->isBranch())
       return true;
 
     // Handle unconditional branches.

Modified: llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp?rev=146026&r1=146025&r2=146026&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp Wed Dec  7 01:15:52 2011
@@ -583,7 +583,7 @@
     // sure we restore the stack pointer immediately after the call, there may
     // be spill code inserted between the CALL and ADJCALLSTACKUP instructions.
     MachineBasicBlock::iterator B = MBB.begin();
-    while (I != B && !llvm::prior(I)->getDesc().isCall())
+    while (I != B && !llvm::prior(I)->isCall())
       --I;
     MBB.insert(I, New);
   }

Modified: llvm/trunk/lib/Target/X86/X86VZeroUpper.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86VZeroUpper.cpp?rev=146026&r1=146025&r2=146026&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86VZeroUpper.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86VZeroUpper.cpp Wed Dec  7 01:15:52 2011
@@ -220,7 +220,7 @@
   for (MachineBasicBlock::iterator I = BB.begin(); I != BB.end(); ++I) {
     MachineInstr *MI = I;
     DebugLoc dl = I->getDebugLoc();
-    bool isControlFlow = MI->getDesc().isCall() || MI->getDesc().isReturn();
+    bool isControlFlow = MI->isCall() || MI->isReturn();
 
     // Shortcut: don't need to check regular instructions in dirty state. 
     if (!isControlFlow && CurState == ST_DIRTY)



From grosser at fim.uni-passau.de  Wed Dec  7 01:42:51 2011
From: grosser at fim.uni-passau.de (Tobias Grosser)
Date: Wed, 07 Dec 2011 07:42:51 -0000
Subject: [llvm-commits] [polly] r146027 -
	/polly/trunk/lib/Analysis/ScopInfo.cpp
Message-ID: <20111207074251.AA9D81BE003@llvm.org>

Author: grosser
Date: Wed Dec  7 01:42:51 2011
New Revision: 146027

URL: http://llvm.org/viewvc/llvm-project?rev=146027&view=rev
Log:
Make isl abort when an error is encountered

Modified:
    polly/trunk/lib/Analysis/ScopInfo.cpp

Modified: polly/trunk/lib/Analysis/ScopInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/polly/trunk/lib/Analysis/ScopInfo.cpp?rev=146027&r1=146026&r2=146027&view=diff
==============================================================================
--- polly/trunk/lib/Analysis/ScopInfo.cpp (original)
+++ polly/trunk/lib/Analysis/ScopInfo.cpp Wed Dec  7 01:42:51 2011
@@ -42,6 +42,7 @@
 #include "isl/aff.h"
 #include "isl/printer.h"
 #include "isl/local_space.h"
+#include "isl/options.h"
 #include 
 #include 
 #include 
@@ -1055,6 +1056,7 @@
 //===----------------------------------------------------------------------===//
 ScopInfo::ScopInfo() : RegionPass(ID), scop(0) {
   ctx = isl_ctx_alloc();
+  isl_options_set_on_error(ctx, ISL_ON_ERROR_ABORT);
 }
 
 ScopInfo::~ScopInfo() {



From grosser at fim.uni-passau.de  Wed Dec  7 01:42:57 2011
From: grosser at fim.uni-passau.de (Tobias Grosser)
Date: Wed, 07 Dec 2011 07:42:57 -0000
Subject: [llvm-commits] [polly] r146028 -
	/polly/trunk/lib/ScheduleOptimizer.cpp
Message-ID: <20111207074257.B0D9C1BE003@llvm.org>

Author: grosser
Date: Wed Dec  7 01:42:57 2011
New Revision: 146028

URL: http://llvm.org/viewvc/llvm-project?rev=146028&view=rev
Log:
ScheduleOptimizer: Rewrite getPrevectorMap to use isl_pw_aff

This increases the readablity. This also adds some comments that explain
what this function does.

Modified:
    polly/trunk/lib/ScheduleOptimizer.cpp

Modified: polly/trunk/lib/ScheduleOptimizer.cpp
URL: http://llvm.org/viewvc/llvm-project/polly/trunk/lib/ScheduleOptimizer.cpp?rev=146028&r1=146027&r2=146028&view=diff
==============================================================================
--- polly/trunk/lib/ScheduleOptimizer.cpp (original)
+++ polly/trunk/lib/ScheduleOptimizer.cpp Wed Dec  7 01:42:57 2011
@@ -26,6 +26,7 @@
 #include "polly/Dependences.h"
 #include "polly/ScopInfo.h"
 
+#include "isl/aff.h"
 #include "isl/space.h"
 #include "isl/map.h"
 #include "isl/constraint.h"
@@ -223,68 +224,107 @@
   return isl_union_map_apply_range(PartialSchedule, TileUMap);
 }
 
-static isl_map *getPrevectorMap(isl_ctx *ctx, int vectorDimension,
-				int scheduleDimensions,
-				int parameterDimensions,
-				int vectorWidth = 4) {
-  assert (0 <= vectorDimension && vectorDimension < scheduleDimensions);
-
-  isl_space *Space = isl_space_alloc(ctx, parameterDimensions,
-                                     scheduleDimensions, scheduleDimensions + 2);
-  isl_basic_map *tilingMap = isl_basic_map_universe(isl_space_copy(Space));
-
+// Create a map that pre-vectorizes one scheduling dimension.
+//
+// getPrevectorMap creates a map that maps each input dimension to the same
+// output dimension, except for the dimension DimToVectorize. DimToVectorize is
+// strip mined by 'VectorWidth' and the newly created point loop of
+// DimToVectorize is moved to the innermost level.
+//
+// Example (DimToVectorize=0, ScheduleDimensions=2, VectorWidth=4):
+//
+// | Before transformation
+// |
+// | A[i,j] -> [i,j]
+// |
+// | for (i = 0; i < 128; i++)
+// |    for (j = 0; j < 128; j++)
+// |      A(i,j);
+//
+//   Prevector map:
+//   [i,j] -> [it,j,ip] : it % 4 = 0 and it <= ip <= it + 3 and i = ip
+//
+// | After transformation:
+// |
+// | A[i,j] -> [it,j,ip] : it % 4 = 0 and it <= ip <= it + 3 and i = ip
+// |
+// | for (it = 0; it < 128; it+=4)
+// |    for (j = 0; j < 128; j++)
+// |      for (ip = max(0,it); ip < min(128, it + 3); ip++)
+// |        A(ip,j);
+//
+// The goal of this transformation is to create a trivially vectorizable loop.
+// This means a parallel loop at the innermost level that has a constant number
+// of iterations corresponding to the target vector width.
+//
+// This transformation creates a loop at the innermost level. The loop has a
+// constant number of iterations, if the number of loop iterations at
+// DimToVectorize can be devided by VectorWidth. The default VectorWidth is
+// currently constant and not yet target specific. This function does not reason
+// about parallelism.
+static isl_map *getPrevectorMap(isl_ctx *ctx, int DimToVectorize,
+				int ScheduleDimensions,
+				int VectorWidth = 4) {
+  isl_space *Space;
+  isl_local_space *LocalSpace, *LocalSpaceRange;
+  isl_set *Modulo;
+  isl_map *TilingMap;
   isl_constraint *c;
-
-  isl_local_space *LocalSpace = isl_local_space_from_space(Space);
-
-  for (int i = 0; i < vectorDimension; i++) {
+  isl_aff *Aff;
+  int PointDimension; /* ip */
+  int TileDimension;  /* it */
+  isl_int VectorWidthMP;
+
+  assert (0 <= DimToVectorize && DimToVectorize < ScheduleDimensions);
+
+  Space = isl_space_alloc(ctx, 0, ScheduleDimensions, ScheduleDimensions + 1);
+  TilingMap = isl_map_universe(isl_space_copy(Space));
+  LocalSpace = isl_local_space_from_space(Space);
+  PointDimension = ScheduleDimensions;
+  TileDimension = DimToVectorize;
+
+  // Create an identity map for everything except DimToVectorize and map
+  // DimToVectorize to the point loop at the innermost dimension.
+  for (int i = 0; i < ScheduleDimensions; i++) {
     c = isl_equality_alloc(isl_local_space_copy(LocalSpace));
     isl_constraint_set_coefficient_si(c, isl_dim_in, i, -1);
-    isl_constraint_set_coefficient_si(c, isl_dim_out, i, 1);
-    tilingMap = isl_basic_map_add_constraint(tilingMap, c);
-  }
 
-  for (int i = vectorDimension + 1; i < scheduleDimensions; i++) {
-    c = isl_equality_alloc(isl_local_space_copy(LocalSpace));
-    isl_constraint_set_coefficient_si(c, isl_dim_in, i, -1);
-    isl_constraint_set_coefficient_si(c, isl_dim_out, i, 1);
-    tilingMap = isl_basic_map_add_constraint(tilingMap, c);
-  }
+    if (i == DimToVectorize)
+      isl_constraint_set_coefficient_si(c, isl_dim_out, PointDimension, 1);
+    else
+      isl_constraint_set_coefficient_si(c, isl_dim_out, i, 1);
 
-  int stepDimension = scheduleDimensions;
-  int auxilaryDimension = scheduleDimensions + 1;
+    TilingMap = isl_map_add_constraint(TilingMap, c);
+  }
 
-  c = isl_equality_alloc(isl_local_space_copy(LocalSpace));
-  isl_constraint_set_coefficient_si(c, isl_dim_out, vectorDimension, 1);
-  isl_constraint_set_coefficient_si(c, isl_dim_out, auxilaryDimension,
-				    -vectorWidth);
-  tilingMap = isl_basic_map_add_constraint(tilingMap, c);
-
-  c = isl_equality_alloc(isl_local_space_copy(LocalSpace));
-  isl_constraint_set_coefficient_si(c, isl_dim_in, vectorDimension, -1);
-  isl_constraint_set_coefficient_si(c, isl_dim_out, stepDimension, 1);
-  tilingMap = isl_basic_map_add_constraint(tilingMap, c);
+  // it % 'VectorWidth' = 0
+  LocalSpaceRange = isl_local_space_range(isl_local_space_copy(LocalSpace));
+  Aff = isl_aff_zero_on_domain(LocalSpaceRange);
+  Aff = isl_aff_set_constant_si(Aff, VectorWidth);
+  Aff = isl_aff_set_coefficient_si(Aff, isl_dim_in, TileDimension, 1);
+  isl_int_init(VectorWidthMP);
+  isl_int_set_si(VectorWidthMP, VectorWidth);
+  Aff = isl_aff_mod(Aff, VectorWidthMP);
+  isl_int_clear(VectorWidthMP);
+  Modulo = isl_pw_aff_zero_set(isl_pw_aff_from_aff(Aff));
+  TilingMap = isl_map_intersect_range(TilingMap, Modulo);
 
+  // it <= ip
   c = isl_inequality_alloc(isl_local_space_copy(LocalSpace));
-  isl_constraint_set_coefficient_si(c, isl_dim_out, vectorDimension, -1);
-  isl_constraint_set_coefficient_si(c, isl_dim_out, stepDimension, 1);
-  tilingMap = isl_basic_map_add_constraint(tilingMap, c);
+  isl_constraint_set_coefficient_si(c, isl_dim_out, TileDimension, -1);
+  isl_constraint_set_coefficient_si(c, isl_dim_out, PointDimension, 1);
+  TilingMap = isl_map_add_constraint(TilingMap, c);
 
+  // ip <= it + ('VectorWidth' - 1)
   c = isl_inequality_alloc(LocalSpace);
-  isl_constraint_set_coefficient_si(c, isl_dim_out, vectorDimension, 1);
-  isl_constraint_set_coefficient_si(c, isl_dim_out, stepDimension, -1);
-  isl_constraint_set_constant_si(c, vectorWidth- 1);
-  tilingMap = isl_basic_map_add_constraint(tilingMap, c);
+  isl_constraint_set_coefficient_si(c, isl_dim_out, TileDimension, 1);
+  isl_constraint_set_coefficient_si(c, isl_dim_out, PointDimension, -1);
+  isl_constraint_set_constant_si(c, VectorWidth - 1);
+  TilingMap = isl_map_add_constraint(TilingMap, c);
 
-  // Project out auxilary dimensions (introduced to ensure 'ii % tileSize = 0')
-  //
-  // The real dimensions are transformed into existentially quantified ones.
-  // This reduces the number of visible scattering dimensions.  Also, Cloog
-  // produces better code, if auxilary dimensions are existentially quantified.
-  tilingMap = isl_basic_map_project_out(tilingMap, isl_dim_out,
-					scheduleDimensions + 1, 1);
+  isl_map_dump(TilingMap);
 
-  return isl_map_from_basic_map(tilingMap);
+  return TilingMap;
 }
 
 // getScheduleForBandList - Get the scheduling map for a list of bands.
@@ -328,7 +368,7 @@
           isl_union_map *TileUMap;
 
 	  TileMap = getPrevectorMap(ctx, ScheduleDimensions + i,
-				    ScheduleDimensions * 2, 0);
+				    ScheduleDimensions * 2);
 	  TileUMap = isl_union_map_from_map(TileMap);
           TileUMap = isl_union_map_align_params(TileUMap,
                                                 isl_space_copy(Space));



From isanbard at gmail.com  Wed Dec  7 01:49:49 2011
From: isanbard at gmail.com (Bill Wendling)
Date: Wed, 07 Dec 2011 07:49:49 -0000
Subject: [llvm-commits] [llvm] r146029 -
	/llvm/trunk/lib/Target/X86/X86FrameLowering.cpp
Message-ID: <20111207074949.DFB9E1BE003@llvm.org>

Author: void
Date: Wed Dec  7 01:49:49 2011
New Revision: 146029

URL: http://llvm.org/viewvc/llvm-project?rev=146029&view=rev
Log:
Fix off-by-one error when encoding the stack size for a frameless stack.

Modified:
    llvm/trunk/lib/Target/X86/X86FrameLowering.cpp

Modified: llvm/trunk/lib/Target/X86/X86FrameLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86FrameLowering.cpp?rev=146029&r1=146028&r2=146029&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86FrameLowering.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86FrameLowering.cpp Wed Dec  7 01:49:49 2011
@@ -561,7 +561,7 @@
     CompactUnwindEncoding |= (StackAdjust & 0xFF) << 16;
     CompactUnwindEncoding |= RegEnc & 0x7FFF;
   } else {
-    uint32_t TotalStackSize = StackAdjust + StackSize;
+    uint32_t TotalStackSize = StackAdjust + StackSize + 1;
     if ((TotalStackSize & 0xFF) == TotalStackSize) {
       // Frameless stack with a small stack size.
       CompactUnwindEncoding |= 0x02000000;



From isanbard at gmail.com  Wed Dec  7 01:58:55 2011
From: isanbard at gmail.com (Bill Wendling)
Date: Wed, 07 Dec 2011 07:58:55 -0000
Subject: [llvm-commits] [llvm] r146030 -
	/llvm/trunk/lib/Target/X86/X86FrameLowering.cpp
Message-ID: <20111207075855.553DF1BE003@llvm.org>

Author: void
Date: Wed Dec  7 01:58:55 2011
New Revision: 146030

URL: http://llvm.org/viewvc/llvm-project?rev=146030&view=rev
Log:
Adjust the stack by one pointer size for all frameless stacks.

Modified:
    llvm/trunk/lib/Target/X86/X86FrameLowering.cpp

Modified: llvm/trunk/lib/Target/X86/X86FrameLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86FrameLowering.cpp?rev=146030&r1=146029&r2=146030&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86FrameLowering.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86FrameLowering.cpp Wed Dec  7 01:58:55 2011
@@ -561,7 +561,8 @@
     CompactUnwindEncoding |= (StackAdjust & 0xFF) << 16;
     CompactUnwindEncoding |= RegEnc & 0x7FFF;
   } else {
-    uint32_t TotalStackSize = StackAdjust + StackSize + 1;
+    ++StackAdjust;
+    uint32_t TotalStackSize = StackAdjust + StackSize;
     if ((TotalStackSize & 0xFF) == TotalStackSize) {
       // Frameless stack with a small stack size.
       CompactUnwindEncoding |= 0x02000000;



From craig.topper at gmail.com  Wed Dec  7 02:30:54 2011
From: craig.topper at gmail.com (Craig Topper)
Date: Wed, 07 Dec 2011 08:30:54 -0000
Subject: [llvm-commits] [llvm] r146031 -
	/llvm/trunk/lib/Target/X86/X86InstrSSE.td
Message-ID: <20111207083054.2671F1BE003@llvm.org>

Author: ctopper
Date: Wed Dec  7 02:30:53 2011
New Revision: 146031

URL: http://llvm.org/viewvc/llvm-project?rev=146031&view=rev
Log:
Fix a bunch of SSE/AVX patterns to use proper memop types. In particular, not using integer loads other than v2i64/v4i64 since the others are all promoted.

Modified:
    llvm/trunk/lib/Target/X86/X86InstrSSE.td

Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrSSE.td?rev=146031&r1=146030&r2=146031&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrSSE.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrSSE.td Wed Dec  7 02:30:53 2011
@@ -1944,7 +1944,7 @@
 // whenever possible to avoid declaring two versions of each one.
 def : Pat<(int_x86_avx_cvtdq2_ps_256 VR256:$src),
           (VCVTDQ2PSYrr VR256:$src)>;
-def : Pat<(int_x86_avx_cvtdq2_ps_256 (memopv8i32 addr:$src)),
+def : Pat<(int_x86_avx_cvtdq2_ps_256 (bitconvert (memopv4i64 addr:$src))),
           (VCVTDQ2PSYrm addr:$src)>;
 
 def : Pat<(int_x86_avx_cvt_pd2_ps_256 VR256:$src),
@@ -3637,6 +3637,8 @@
                           i128mem, 1, 0>, VEX_4V;
 defm VPXOR : PDI_binop_rm<0xEF, "vpxor", xor, v2i64, VR128, memopv2i64,
                           i128mem, 1, 0>, VEX_4V;
+defm VPANDN : PDI_binop_rm<0xDF, "vpandn", X86andnp, v2i64, VR128, memopv2i64,
+                          i128mem, 0, 0>, VEX_4V;
 
 let ExeDomain = SSEPackedInt in {
   let neverHasSideEffects = 1 in {
@@ -3651,17 +3653,6 @@
                       VEX_4V;
     // PSRADQri doesn't exist in SSE[1-3].
   }
-  def VPANDNrr : PDI<0xDF, MRMSrcReg,
-                    (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
-                    "vpandn\t{$src2, $src1, $dst|$dst, $src1, $src2}",
-                    [(set VR128:$dst,
-                          (v2i64 (X86andnp VR128:$src1, VR128:$src2)))]>,VEX_4V;
-
-  def VPANDNrm : PDI<0xDF, MRMSrcMem,
-                    (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
-                    "vpandn\t{$src2, $src1, $dst|$dst, $src1, $src2}",
-                    [(set VR128:$dst, (X86andnp VR128:$src1,
-                                            (memopv2i64 addr:$src2)))]>, VEX_4V;
 }
 }
 
@@ -3699,6 +3690,8 @@
                            i256mem, 1, 0>, VEX_4V;
 defm VPXORY : PDI_binop_rm<0xEF, "vpxor", xor, v4i64, VR256, memopv4i64,
                            i256mem, 1, 0>, VEX_4V;
+defm VPANDNY : PDI_binop_rm<0xDF, "vpandn", X86andnp, v4i64, VR256, memopv4i64,
+                            i256mem, 0, 0>, VEX_4V;
 
 let ExeDomain = SSEPackedInt in {
   let neverHasSideEffects = 1 in {
@@ -3713,17 +3706,6 @@
                       VEX_4V;
     // PSRADQYri doesn't exist in SSE[1-3].
   }
-  def VPANDNYrr : PDI<0xDF, MRMSrcReg,
-                     (outs VR256:$dst), (ins VR256:$src1, VR256:$src2),
-                     "vpandn\t{$src2, $src1, $dst|$dst, $src1, $src2}",
-                     [(set VR256:$dst,
-                          (v4i64 (X86andnp VR256:$src1, VR256:$src2)))]>,VEX_4V;
-
-  def VPANDNYrm : PDI<0xDF, MRMSrcMem,
-                     (outs VR256:$dst), (ins VR256:$src1, i256mem:$src2),
-                     "vpandn\t{$src2, $src1, $dst|$dst, $src1, $src2}",
-                     [(set VR256:$dst, (X86andnp VR256:$src1,
-                                            (memopv4i64 addr:$src2)))]>, VEX_4V;
 }
 }
 
@@ -3761,6 +3743,8 @@
                          i128mem, 1>;
 defm PXOR : PDI_binop_rm<0xEF, "pxor", xor, v2i64, VR128, memopv2i64,
                          i128mem, 1>;
+defm PANDN : PDI_binop_rm<0xDF, "pandn", X86andnp, v2i64, VR128, memopv2i64,
+                          i128mem, 0>;
 
 let ExeDomain = SSEPackedInt in {
   let neverHasSideEffects = 1 in {
@@ -3772,14 +3756,6 @@
                          (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
                          "psrldq\t{$src2, $dst|$dst, $src2}", []>;
     // PSRADQri doesn't exist in SSE[1-3].
-    def PANDNrr : PDI<0xDF, MRMSrcReg,
-                      (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
-                      "pandn\t{$src2, $dst|$dst, $src2}", []>;
-
-    let mayLoad = 1 in
-    def PANDNrm : PDI<0xDF, MRMSrcMem,
-                      (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
-                      "pandn\t{$src2, $dst|$dst, $src2}", []>;
   }
 }
 } // Constraints = "$src1 = $dst"
@@ -4791,7 +4767,7 @@
 // AVX 256-bit register conversion intrinsics
 def : Pat<(int_x86_avx_cvtdq2_pd_256 VR128:$src),
            (VCVTDQ2PDYrr VR128:$src)>;
-def : Pat<(int_x86_avx_cvtdq2_pd_256 (memopv4i32 addr:$src)),
+def : Pat<(int_x86_avx_cvtdq2_pd_256 (bitconvert (memopv2i64 addr:$src))),
            (VCVTDQ2PDYrm addr:$src)>;
 
 def : Pat<(int_x86_avx_cvt_pd2dq_256 VR256:$src),
@@ -4801,7 +4777,7 @@
 
 def : Pat<(v4f64 (sint_to_fp (v4i32 VR128:$src))),
           (VCVTDQ2PDYrr VR128:$src)>;
-def : Pat<(v4f64 (sint_to_fp (memopv4i32 addr:$src))),
+def : Pat<(v4f64 (sint_to_fp (bc_v4i32 (memopv2i64 addr:$src)))),
           (VCVTDQ2PDYrm addr:$src)>;
 
 //===---------------------------------------------------------------------===//
@@ -6406,38 +6382,38 @@
   let isCommutable = 0 in {
     let ExeDomain = SSEPackedSingle in {
     defm VBLENDPS : SS41I_binop_rmi_int<0x0C, "vblendps", int_x86_sse41_blendps,
-                                        VR128, memopv16i8, i128mem, 0>, VEX_4V;
+                                        VR128, memopv4f32, i128mem, 0>, VEX_4V;
     defm VBLENDPSY : SS41I_binop_rmi_int<0x0C, "vblendps",
-              int_x86_avx_blend_ps_256, VR256, memopv32i8, i256mem, 0>, VEX_4V;
+              int_x86_avx_blend_ps_256, VR256, memopv8f32, i256mem, 0>, VEX_4V;
     }
     let ExeDomain = SSEPackedDouble in {
     defm VBLENDPD : SS41I_binop_rmi_int<0x0D, "vblendpd", int_x86_sse41_blendpd,
-                                        VR128, memopv16i8, i128mem, 0>, VEX_4V;
+                                        VR128, memopv2f64, i128mem, 0>, VEX_4V;
     defm VBLENDPDY : SS41I_binop_rmi_int<0x0D, "vblendpd",
-              int_x86_avx_blend_pd_256, VR256, memopv32i8, i256mem, 0>, VEX_4V;
+              int_x86_avx_blend_pd_256, VR256, memopv4f64, i256mem, 0>, VEX_4V;
     }
   defm VPBLENDW : SS41I_binop_rmi_int<0x0E, "vpblendw", int_x86_sse41_pblendw,
-                                      VR128, memopv16i8, i128mem, 0>, VEX_4V;
+                                      VR128, memopv2i64, i128mem, 0>, VEX_4V;
   defm VMPSADBW : SS41I_binop_rmi_int<0x42, "vmpsadbw", int_x86_sse41_mpsadbw,
-                                      VR128, memopv16i8, i128mem, 0>, VEX_4V;
+                                      VR128, memopv2i64, i128mem, 0>, VEX_4V;
   }
   let ExeDomain = SSEPackedSingle in
   defm VDPPS : SS41I_binop_rmi_int<0x40, "vdpps", int_x86_sse41_dpps,
-                                   VR128, memopv16i8, i128mem, 0>, VEX_4V;
+                                   VR128, memopv4f32, i128mem, 0>, VEX_4V;
   let ExeDomain = SSEPackedDouble in
   defm VDPPD : SS41I_binop_rmi_int<0x41, "vdppd", int_x86_sse41_dppd,
-                                   VR128, memopv16i8, i128mem, 0>, VEX_4V;
+                                   VR128, memopv2f64, i128mem, 0>, VEX_4V;
   let ExeDomain = SSEPackedSingle in
   defm VDPPSY : SS41I_binop_rmi_int<0x40, "vdpps", int_x86_avx_dp_ps_256,
-                                   VR256, memopv32i8, i256mem, 0>, VEX_4V;
+                                   VR256, memopv8f32, i256mem, 0>, VEX_4V;
 }
 
 let Predicates = [HasAVX2] in {
   let isCommutable = 0 in {
   defm VPBLENDWY : SS41I_binop_rmi_int<0x0E, "vpblendw", int_x86_avx2_pblendw,
-                                       VR256, memopv32i8, i256mem, 0>, VEX_4V;
+                                       VR256, memopv4i64, i256mem, 0>, VEX_4V;
   defm VMPSADBWY : SS41I_binop_rmi_int<0x42, "vmpsadbw", int_x86_avx2_mpsadbw,
-                                       VR256, memopv32i8, i256mem, 0>, VEX_4V;
+                                       VR256, memopv4i64, i256mem, 0>, VEX_4V;
   }
 }
 
@@ -6445,21 +6421,21 @@
   let isCommutable = 0 in {
   let ExeDomain = SSEPackedSingle in
   defm BLENDPS : SS41I_binop_rmi_int<0x0C, "blendps", int_x86_sse41_blendps,
-                                     VR128, memopv16i8, i128mem>;
+                                     VR128, memopv4f32, i128mem>;
   let ExeDomain = SSEPackedDouble in
   defm BLENDPD : SS41I_binop_rmi_int<0x0D, "blendpd", int_x86_sse41_blendpd,
-                                     VR128, memopv16i8, i128mem>;
+                                     VR128, memopv2f64, i128mem>;
   defm PBLENDW : SS41I_binop_rmi_int<0x0E, "pblendw", int_x86_sse41_pblendw,
-                                     VR128, memopv16i8, i128mem>;
+                                     VR128, memopv2i64, i128mem>;
   defm MPSADBW : SS41I_binop_rmi_int<0x42, "mpsadbw", int_x86_sse41_mpsadbw,
-                                     VR128, memopv16i8, i128mem>;
+                                     VR128, memopv2i64, i128mem>;
   }
   let ExeDomain = SSEPackedSingle in
   defm DPPS : SS41I_binop_rmi_int<0x40, "dpps", int_x86_sse41_dpps,
-                                  VR128, memopv16i8, i128mem>;
+                                  VR128, memopv4f32, i128mem>;
   let ExeDomain = SSEPackedDouble in
   defm DPPD : SS41I_binop_rmi_int<0x41, "dppd", int_x86_sse41_dppd,
-                                  VR128, memopv16i8, i128mem>;
+                                  VR128, memopv2f64, i128mem>;
 }
 
 /// SS41I_quaternary_int_avx - AVX SSE 4.1 with 4 operators
@@ -6486,23 +6462,23 @@
 let Predicates = [HasAVX] in {
 let ExeDomain = SSEPackedDouble in {
 defm VBLENDVPD  : SS41I_quaternary_int_avx<0x4B, "vblendvpd", VR128, i128mem,
-                                           memopv16i8, int_x86_sse41_blendvpd>;
+                                           memopv2f64, int_x86_sse41_blendvpd>;
 defm VBLENDVPDY : SS41I_quaternary_int_avx<0x4B, "vblendvpd", VR256, i256mem,
-                                         memopv32i8, int_x86_avx_blendv_pd_256>;
+                                         memopv4f64, int_x86_avx_blendv_pd_256>;
 } // ExeDomain = SSEPackedDouble
 let ExeDomain = SSEPackedSingle in {
 defm VBLENDVPS  : SS41I_quaternary_int_avx<0x4A, "vblendvps", VR128, i128mem,
-                                           memopv16i8, int_x86_sse41_blendvps>;
+                                           memopv4f32, int_x86_sse41_blendvps>;
 defm VBLENDVPSY : SS41I_quaternary_int_avx<0x4A, "vblendvps", VR256, i256mem,
-                                         memopv32i8, int_x86_avx_blendv_ps_256>;
+                                         memopv8f32, int_x86_avx_blendv_ps_256>;
 } // ExeDomain = SSEPackedSingle
 defm VPBLENDVB  : SS41I_quaternary_int_avx<0x4C, "vpblendvb", VR128, i128mem,
-                                           memopv16i8, int_x86_sse41_pblendvb>;
+                                           memopv2i64, int_x86_sse41_pblendvb>;
 }
 
 let Predicates = [HasAVX2] in {
 defm VPBLENDVBY : SS41I_quaternary_int_avx<0x4C, "vpblendvb", VR256, i256mem,
-                                           memopv32i8, int_x86_avx2_pblendvb>;
+                                           memopv4i64, int_x86_avx2_pblendvb>;
 }
 
 let Predicates = [HasAVX] in {
@@ -6543,7 +6519,8 @@
 
 /// SS41I_ternary_int - SSE 4.1 ternary operator
 let Uses = [XMM0], Constraints = "$src1 = $dst" in {
-  multiclass SS41I_ternary_int opc, string OpcodeStr, Intrinsic IntId> {
+  multiclass SS41I_ternary_int opc, string OpcodeStr, PatFrag mem_frag,
+                               Intrinsic IntId> {
     def rr0 : SS48I, OpSize;
+                       (bitconvert (mem_frag addr:$src2)), XMM0))]>, OpSize;
   }
 }
 
 let ExeDomain = SSEPackedDouble in
-defm BLENDVPD : SS41I_ternary_int<0x15, "blendvpd", int_x86_sse41_blendvpd>;
+defm BLENDVPD : SS41I_ternary_int<0x15, "blendvpd", memopv2f64,
+                                  int_x86_sse41_blendvpd>;
 let ExeDomain = SSEPackedSingle in
-defm BLENDVPS : SS41I_ternary_int<0x14, "blendvps", int_x86_sse41_blendvps>;
-defm PBLENDVB : SS41I_ternary_int<0x10, "pblendvb", int_x86_sse41_pblendvb>;
+defm BLENDVPS : SS41I_ternary_int<0x14, "blendvps", memopv4f32,
+                                  int_x86_sse41_blendvps>;
+defm PBLENDVB : SS41I_ternary_int<0x10, "pblendvb", memopv2i64,
+                                  int_x86_sse41_pblendvb>;
 
 let Predicates = [HasSSE41] in {
   def : Pat<(v16i8 (vselect (v16i8 XMM0), (v16i8 VR128:$src1),
@@ -6620,8 +6600,7 @@
            !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
            !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
        [(set VR128:$dst,
-         (IntId128 VR128:$src1,
-          (bitconvert (memopv16i8 addr:$src2))))]>, OpSize;
+         (IntId128 VR128:$src1, (memopv2i64 addr:$src2)))]>, OpSize;
 }
 
 /// SS42I_binop_rm_int - Simple SSE 4.2 binary operator
@@ -6636,8 +6615,7 @@
        (ins VR256:$src1, i256mem:$src2),
        !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
        [(set VR256:$dst,
-         (IntId256 VR256:$src1,
-          (bitconvert (memopv32i8 addr:$src2))))]>, OpSize;
+         (IntId256 VR256:$src1, (memopv4i64 addr:$src2)))]>, OpSize;
 }
 
 let Predicates = [HasAVX] in {
@@ -6919,7 +6897,7 @@
            !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
        [(set VR128:$dst,
          (IntId128 VR128:$src1,
-          (bitconvert (memopv16i8 addr:$src2))))]>, OpSize;
+          (bitconvert (memopv2i64 addr:$src2))))]>, OpSize;
 }
 
 // Perform One Round of an AES Encryption/Decryption Flow
@@ -7404,9 +7382,9 @@
 
 let isCommutable = 0 in {
 defm VPBLENDD : AVX2_binop_rmi_int<0x02, "vpblendd", int_x86_avx2_pblendd_128,
-                                   VR128, memopv16i8, i128mem>;
+                                   VR128, memopv2i64, i128mem>;
 defm VPBLENDDY : AVX2_binop_rmi_int<0x02, "vpblendd", int_x86_avx2_pblendd_256,
-                                    VR256, memopv32i8, i256mem>;
+                                    VR256, memopv4i64, i256mem>;
 }
 
 //===----------------------------------------------------------------------===//



From stpworld at narod.ru  Wed Dec  7 04:42:15 2011
From: stpworld at narod.ru (Stepan Dyatkovskiy)
Date: Wed, 07 Dec 2011 14:42:15 +0400
Subject: [llvm-commits] [LLVM,
 SelectionDAG] fix for #9905: Failure in code selection for llvm
 intrinsics sqrt/exp
In-Reply-To: 
References: <4ED74593.2030003@narod.ru> <4ED9D140.2070504@narod.ru>
	<4EDCC1A2.5010500@narod.ru>
	
	<4EDDE0E1.5060200@narod.ru> <4EDDE47C.4000905@narod.ru>
	
Message-ID: <4EDF4307.4060909@narod.ru>

Please, look at fixed patch in attachment.

Thanks.
-Stepan.

Eli Friedman wrote:
> On Tue, Dec 6, 2011 at 1:46 AM, Stepan Dyatkovskiy  wrote:
>> Sorry for previous post. Forgot to remove extra newlines at the end of file.
>> Fixed file is attached here.
>
> Better... but please try to make it less sensitive to register
> allocation and scheduler choices.
>
> -Eli
>
>>
>> Thanks.
>> -Stepan.
>>
>>
>> Stepan Dyatkovskiy wrote:
>>>
>>> OK. Please look at reworked regression test patch in attachment.
>>>
>>> -Stepan.
>>>
>>> Eli Friedman wrote:
>>>>
>>>> The code changes look fine. Please put all the FileCheck tests into
>>>> one file, and only use CHECK lines for the most important pieces
>>>> (specifically, that we call sinf etc.).
>>>>
>>>> -Eli
>>>>
>>>> On Mon, Dec 5, 2011 at 5:05 AM, Stepan Dyatkovskiy
>>>> wrote:
>>>>>
>>>>> ping.
>>>>>
>>>>> -Stepan.
>>>>>
>>>>> Stepan Dyatkovskiy wrote:
>>>>>>
>>>>>> ping.
>>>>>>
>>>>>> -Stepan
>>>>>>
>>>>>> Stepan Dyatkovskiy wrote:
>>>>>>>
>>>>>>> Hi all. Please find the patch and regression tests in attachment for
>>>>>>> review.
>>>>>>> This patch for ARM. It fixes selection for several instructions that
>>>>>>> works with v4f32 arguments: FSQRT, FSIN, FCOS, FPOWI, FPOW, FLOG,
>>>>>>> FLOG2,
>>>>>>> FLOG10, FEXP, FEXP2.
>>>>>>> I'm still worrying about FCOPYSIGN, FNEG, FABS, FCEIL, FTRUNC, FRINT,
>>>>>>> FNEARBYINT, FFLOOR. I could not found a way to add this instructions
>>>>>>> with v2f32 argument to DAG. It seems that it is impossible in ToT. So
>>>>>>> these instructions was not fixed.
>>>>>>>
>>>>>>> -Stepan.
>>>>>>>
>>>>>>>
>>>>>>> _______________________________________________
>>>>>>> llvm-commits mailing list
>>>>>>> llvm-commits at cs.uiuc.edu
>>>>>>> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
>>>>>>
>>>>>>
>>>>>> _______________________________________________
>>>>>> llvm-commits mailing list
>>>>>> llvm-commits at cs.uiuc.edu
>>>>>> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
>>>>>
>>>>>
>>>>> _______________________________________________
>>>>> llvm-commits mailing list
>>>>> llvm-commits at cs.uiuc.edu
>>>>> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
>>>
>>>
>>>
>>>
>>> _______________________________________________
>>> llvm-commits mailing list
>>> llvm-commits at cs.uiuc.edu
>>> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
>>
>>

-------------- next part --------------
A non-text attachment was scrubbed...
Name: 9905-regtests.patch
Type: text/x-patch
Size: 8053 bytes
Desc: not available
Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20111207/5f11521f/attachment.bin 

From grosser at fim.uni-passau.de  Wed Dec  7 05:03:49 2011
From: grosser at fim.uni-passau.de (Tobias Grosser)
Date: Wed, 07 Dec 2011 11:03:49 -0000
Subject: [llvm-commits] [polly] r146033 - in /polly/trunk: lib/Cloog.cpp
 test/CMakeLists.txt test/Cloog/ test/Cloog/ambigous_schedule.ll
 test/Cloog/ambigous_schedule___%for.cond---%for.end30.jscop
Message-ID: <20111207110349.1B0701BE003@llvm.org>

Author: grosser
Date: Wed Dec  7 05:03:48 2011
New Revision: 146033

URL: http://llvm.org/viewvc/llvm-project?rev=146033&view=rev
Log:
ClooG: Make sure ambigous schedules do not introduce complicated code

Cloog continued to split the domains even after the scattering. This lead to
complicated code.

Added:
    polly/trunk/test/Cloog/
    polly/trunk/test/Cloog/ambigous_schedule.ll
    polly/trunk/test/Cloog/ambigous_schedule___%for.cond---%for.end30.jscop
Modified:
    polly/trunk/lib/Cloog.cpp
    polly/trunk/test/CMakeLists.txt

Modified: polly/trunk/lib/Cloog.cpp
URL: http://llvm.org/viewvc/llvm-project/polly/trunk/lib/Cloog.cpp?rev=146033&r1=146032&r2=146033&view=diff
==============================================================================
--- polly/trunk/lib/Cloog.cpp (original)
+++ polly/trunk/lib/Cloog.cpp Wed Dec  7 05:03:48 2011
@@ -152,6 +152,15 @@
   Options->strides = 1;
   Options->save_domains = 1;
   Options->noscalars = 1;
+
+  // The last loop depth to optimize should be the last scattering dimension.
+  // CLooG by default will continue to split the loops even after the last
+  // scattering dimension. This splitting is problematic for the schedules
+  // calculated by the PoCC/isl/Pluto optimizer. Such schedules contain may
+  // not be fully defined, but statements without dependences may be mapped
+  // to the same exeuction time. For such schedules, continuing to split
+  // may lead to a larger set of if-conditions in the innermost loop.
+  Options->l = 0;
 }
 
 CloogUnionDomain *Cloog::buildCloogUnionDomain() {

Modified: polly/trunk/test/CMakeLists.txt
URL: http://llvm.org/viewvc/llvm-project/polly/trunk/test/CMakeLists.txt?rev=146033&r1=146032&r2=146033&view=diff
==============================================================================
--- polly/trunk/test/CMakeLists.txt (original)
+++ polly/trunk/test/CMakeLists.txt Wed Dec  7 05:03:48 2011
@@ -3,6 +3,7 @@
   "ScopInfo"
   "ScheduleOptimizer"
   "CodeGen"
+  "Cloog"
   "OpenMP"
   "polybench"
   "vect")

Added: polly/trunk/test/Cloog/ambigous_schedule.ll
URL: http://llvm.org/viewvc/llvm-project/polly/trunk/test/Cloog/ambigous_schedule.ll?rev=146033&view=auto
==============================================================================
--- polly/trunk/test/Cloog/ambigous_schedule.ll (added)
+++ polly/trunk/test/Cloog/ambigous_schedule.ll Wed Dec  7 05:03:48 2011
@@ -0,0 +1,118 @@
+; RUN: opt %loadPolly %defaultOpts -polly-import-jscop-dir=`dirname %s` -polly-import-jscop -polly-cloog -analyze %s | FileCheck %s
+target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128"
+target triple = "x86_64-unknown-linux-gnu"
+
+ at A = common global [100 x [100 x double]] zeroinitializer, align 16
+ at B = common global [100 x [100 x double]] zeroinitializer, align 16
+
+define void @ambigous_schedule() nounwind uwtable {
+entry:
+  br label %for.cond
+
+for.cond:                                         ; preds = %for.inc6, %entry
+  %i.0 = phi i32 [ 0, %entry ], [ %inc7, %for.inc6 ]
+  %cmp = icmp slt i32 %i.0, 100
+  br i1 %cmp, label %for.body, label %for.end8
+
+for.body:                                         ; preds = %for.cond
+  br label %for.cond1
+
+for.cond1:                                        ; preds = %for.inc, %for.body
+  %j.0 = phi i32 [ 0, %for.body ], [ %inc, %for.inc ]
+  %cmp2 = icmp slt i32 %j.0, 100
+  br i1 %cmp2, label %for.body3, label %for.end
+
+for.body3:                                        ; preds = %for.cond1
+  %add = add nsw i32 %i.0, %j.0
+  %conv = sitofp i32 %add to double
+  %idxprom = sext i32 %j.0 to i64
+  %idxprom4 = sext i32 %i.0 to i64
+  %arrayidx = getelementptr inbounds [100 x [100 x double]]* @A, i32 0, i64 %idxprom4
+  %arrayidx5 = getelementptr inbounds [100 x double]* %arrayidx, i32 0, i64 %idxprom
+  store double %conv, double* %arrayidx5, align 8
+  br label %for.inc
+
+for.inc:                                          ; preds = %for.body3
+  %inc = add nsw i32 %j.0, 1
+  br label %for.cond1
+
+for.end:                                          ; preds = %for.cond1
+  br label %for.inc6
+
+for.inc6:                                         ; preds = %for.end
+  %inc7 = add nsw i32 %i.0, 1
+  br label %for.cond
+
+for.end8:                                         ; preds = %for.cond
+  br label %for.cond10
+
+for.cond10:                                       ; preds = %for.inc28, %for.end8
+  %i9.0 = phi i32 [ 0, %for.end8 ], [ %inc29, %for.inc28 ]
+  %cmp11 = icmp slt i32 %i9.0, 100
+  br i1 %cmp11, label %for.body13, label %for.end30
+
+for.body13:                                       ; preds = %for.cond10
+  br label %for.cond15
+
+for.cond15:                                       ; preds = %for.inc25, %for.body13
+  %j14.0 = phi i32 [ 0, %for.body13 ], [ %inc26, %for.inc25 ]
+  %cmp16 = icmp slt i32 %j14.0, 100
+  br i1 %cmp16, label %for.body18, label %for.end27
+
+for.body18:                                       ; preds = %for.cond15
+  %add19 = add nsw i32 %i9.0, %j14.0
+  %conv20 = sitofp i32 %add19 to double
+  %idxprom21 = sext i32 %j14.0 to i64
+  %idxprom22 = sext i32 %i9.0 to i64
+  %arrayidx23 = getelementptr inbounds [100 x [100 x double]]* @B, i32 0, i64 %idxprom22
+  %arrayidx24 = getelementptr inbounds [100 x double]* %arrayidx23, i32 0, i64 %idxprom21
+  store double %conv20, double* %arrayidx24, align 8
+  br label %for.inc25
+
+for.inc25:                                        ; preds = %for.body18
+  %inc26 = add nsw i32 %j14.0, 1
+  br label %for.cond15
+
+for.end27:                                        ; preds = %for.cond15
+  br label %for.inc28
+
+for.inc28:                                        ; preds = %for.end27
+  %inc29 = add nsw i32 %i9.0, 1
+  br label %for.cond10
+
+for.end30:                                        ; preds = %for.cond10
+  ret void
+}
+
+; CHECK: for (c2=0;c2<=99;c2++) {
+; CHECK:   for (c3=0;c3<=99;c3++) {
+; CHECK:     Stmt_for_body3(c2,c3);
+; CHECK:     Stmt_for_body18(c3,c2);
+; CHECK:   }
+; CHECK: }
+
+; This check makes sure CLooG stops splitting for ambigious schedules as
+; they may be generated by the isl/PoCC/Pluto schedule optimizers.
+;
+; Previously we created such code:
+;
+; for (c2=0;c2<=99;c2++) {
+;   for (c3=0;c3<=99;c3++) {
+;     if (c2 == c3) {
+;       Stmt_for_body3(c2,c2);
+;       Stmt_for_body18(c2,c2);
+;     }
+;     if (c2 <= c3-1) {
+;       Stmt_for_body3(c2,c3);
+;     }
+;     if (c2 <= c3-1) {
+;       Stmt_for_body18(c3,c2);
+;     }
+;     if (c2 >= c3+1) {
+;       Stmt_for_body18(c3,c2);
+;     }
+;     if (c2 >= c3+1) {
+;       Stmt_for_body3(c2,c3);
+;     }
+;   }
+; }

Added: polly/trunk/test/Cloog/ambigous_schedule___%for.cond---%for.end30.jscop
URL: http://llvm.org/viewvc/llvm-project/polly/trunk/test/Cloog/ambigous_schedule___%25for.cond---%25for.end30.jscop?rev=146033&view=auto
==============================================================================
--- polly/trunk/test/Cloog/ambigous_schedule___%for.cond---%for.end30.jscop (added)
+++ polly/trunk/test/Cloog/ambigous_schedule___%for.cond---%for.end30.jscop Wed Dec  7 05:03:48 2011
@@ -0,0 +1,28 @@
+{
+   "context" : "{  :  }",
+   "name" : "for.cond => for.end30",
+   "statements" : [
+      {
+         "accesses" : [
+            {
+               "kind" : "write",
+               "relation" : "{ Stmt_for_body3[i0, i1] -> MemRef_A[100i0 + i1] }"
+            }
+         ],
+         "domain" : "{ Stmt_for_body3[i0, i1] : i0 >= 0 and i0 <= 99 and i1 >= 0 and i1 <= 99 }",
+         "name" : "Stmt_for_body3",
+         "schedule" : "{ Stmt_for_body3[i0, i1] -> scattering[0, i0, i1, 0] }"
+      },
+      {
+         "accesses" : [
+            {
+               "kind" : "write",
+               "relation" : "{ Stmt_for_body18[i0, i1] -> MemRef_B[100i0 + i1] }"
+            }
+         ],
+         "domain" : "{ Stmt_for_body18[i0, i1] : i0 >= 0 and i0 <= 99 and i1 >= 0 and i1 <= 99 }",
+         "name" : "Stmt_for_body18",
+         "schedule" : "{ Stmt_for_body18[i0, i1] -> scattering[0, i1, i0, 0] }"
+      }
+   ]
+}



From eugeni.stepanov at gmail.com  Wed Dec  7 05:09:41 2011
From: eugeni.stepanov at gmail.com (Evgeniy Stepanov)
Date: Wed, 7 Dec 2011 15:09:41 +0400
Subject: [llvm-commits] Update the comment for StructorOutputOrder
Message-ID: 

This patch removes the mention of "default" value for
StructorOutputOrder, as it depends on the target ABI, and there is no
global default.
-------------- next part --------------
A non-text attachment was scrubbed...
Name: structoroutputorder-comment.patch
Type: text/x-patch
Size: 712 bytes
Desc: not available
Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20111207/3c1351a6/attachment.bin 

From baldrick at free.fr  Wed Dec  7 06:40:49 2011
From: baldrick at free.fr (Duncan Sands)
Date: Wed, 07 Dec 2011 13:40:49 +0100
Subject: [llvm-commits] Update the comment for StructorOutputOrder
In-Reply-To: 
References: 
Message-ID: <4EDF5ED1.6070702@free.fr>

Hi Evgeniy,

> This patch removes the mention of "default" value for
> StructorOutputOrder, as it depends on the target ABI, and there is no
> global default.

the field is initialized to that value.  That is the meaning of default in
this context.  So can you please either remove the initial value for the
field, or revert this patch.

Ciao, Duncan.

From eugeni.stepanov at gmail.com  Wed Dec  7 07:12:55 2011
From: eugeni.stepanov at gmail.com (Evgeniy Stepanov)
Date: Wed, 7 Dec 2011 17:12:55 +0400
Subject: [llvm-commits] Update the comment for StructorOutputOrder
In-Reply-To: <4EDF5ED1.6070702@free.fr>
References: 
	<4EDF5ED1.6070702@free.fr>
Message-ID: 

On Wed, Dec 7, 2011 at 4:40 PM, Duncan Sands  wrote:
> Hi Evgeniy,
>
>> This patch removes the mention of "default" value for
>> StructorOutputOrder, as it depends on the target ABI, and there is no
>> global default.
>
> the field is initialized to that value. ?That is the meaning of default in
> this context. ?So can you please either remove the initial value for the
> field, or revert this patch.

It's not, as far as I can see. Since r145781 is it initialized to
different values depending on the target arch.

>
> Ciao, Duncan.
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits


From baldrick at free.fr  Wed Dec  7 07:22:18 2011
From: baldrick at free.fr (Duncan Sands)
Date: Wed, 07 Dec 2011 14:22:18 +0100
Subject: [llvm-commits] Update the comment for StructorOutputOrder
In-Reply-To: 
References: 	<4EDF5ED1.6070702@free.fr>
	
Message-ID: <4EDF688A.8040703@free.fr>

Hi Evgeniy,

>>> This patch removes the mention of "default" value for
>>> StructorOutputOrder, as it depends on the target ABI, and there is no
>>> global default.
>>
>> the field is initialized to that value.  That is the meaning of default in
>> this context.  So can you please either remove the initial value for the
>> field, or revert this patch.
>
> It's not, as far as I can see. Since r145781 is it initialized to
> different values depending on the target arch.

I see - it seems I'm out of date!  In that case please get rid of the
references to the default.

Ciao, Duncan.

From stpworld at narod.ru  Wed Dec  7 07:54:18 2011
From: stpworld at narod.ru (Stepan Dyatkovskiy)
Date: Wed, 07 Dec 2011 17:54:18 +0400
Subject: [llvm-commits] [LLVM, loop-unswitch,
 bugfix for #11429] Wrong behaviour for switches.
In-Reply-To: <566DBA1B-7099-44E0-B2EB-3413A054F5E3@apple.com>
References: <4ECF4A5A.9030607@narod.ru> <4ED36D99.1080306@narod.ru>
	<4ED51EEC.6050000@narod.ru> <4ED749D0.8030101@narod.ru>
	<4ED88CDF.2020104@narod.ru>
	
	<4EDCC136.1040903@narod.ru>
	<566DBA1B-7099-44E0-B2EB-3413A054F5E3@apple.com>
Message-ID: <4EDF700A.3080605@narod.ru>

Dan Gohman wrote:

> This sounds good. How sure are you that the existing size heuristics
> are actually kicking in for the new unrollings? I don't have a reason
> to suspect a bug, other than that you're asking code to work in cases
> that it hasn't before.

The main reason to suspect a bug is that the pass doesn't work as it was 
planned initially. I made this conclusion after reading the code and its 
comments. Especially this ones (LoopUnswitch.cpp, string #277):
         // FIXME: this should choose the most expensive case!
         // FIXME: scan for a case with a non-critical edge?
Programmer placed the stub by now:
	Constant *UnswitchVal = SI->getCaseValue(1);

Probably he missed one thing. Since we selected 1-st case always, all 
other cases will never unswitched. But there is no comments about it. 
This "feature" looks unplanned. If not - ok, it is not a bug then. I 
proposed to insert additional comments though.

Size heuristics currently analyses the size of loop to be unswitched. If 
number of instructions, or number of BBs exceeds some threshold, then 
the loop will skipped. We can also control the number cases to be 
unswitched.

> Each unswitched case has the potential to increase performance,
> if conditions are favorable. But if code size is increased, there's
> also the possibility of decreased performance.

Before unswitchment, loop executes switch N times. The switch is lowered 
to several "icmp" checks (let it be "n"). Depending on lowering 
algorithm selected the "n" is either linear or logarithmic function on 
cases number ( n=k*num_cases or n=k*log(num_cases) ). Summary we have 
N*n "icmp" checks.

After unswitchment all checks will moved out of loop. And we got 1*n_us 
"icmp" checks in this case. But the "n_us" is always linear after 
unswitchment. So if (1*n_us < N*n) then performance will increased. Else 
- it will decreased.

 > If you can confirm
> that that's working as expected, it should be fine.

Did you mean the regression tests? If yes - they are attached in initial 
post. These tests checks that all working as expected for loop with 
single switch instruction and for loop with two switches.

In my patch I fixed the stub described above. I also can improve the 
size heuristics if you need.

Thanks,
-Stepan.

From glider at google.com  Wed Dec  7 02:18:49 2011
From: glider at google.com (Alexander Potapenko)
Date: Wed, 7 Dec 2011 12:18:49 +0400
Subject: [llvm-commits] [compiler-rt] r145966 - in
 /compiler-rt/trunk/lib/asan: asan_internal.h asan_rtl.cc
In-Reply-To: <20111206211015.8CACC1BE003@llvm.org>
References: <20111206211015.8CACC1BE003@llvm.org>
Message-ID: 

What's this flag for? Can you choose a better name?

On Wed, Dec 7, 2011 at 1:10 AM, Kostya Serebryany  wrote:
> Author: kcc
> Date: Tue Dec ?6 15:10:15 2011
> New Revision: 145966
>
> URL: http://llvm.org/viewvc/llvm-project?rev=145966&view=rev
> Log:
> [asan] minor cleanup
>
> Modified:
> ? ?compiler-rt/trunk/lib/asan/asan_internal.h
> ? ?compiler-rt/trunk/lib/asan/asan_rtl.cc
>
> Modified: compiler-rt/trunk/lib/asan/asan_internal.h
> URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/lib/asan/asan_internal.h?rev=145966&r1=145965&r2=145966&view=diff
> ==============================================================================
> --- compiler-rt/trunk/lib/asan/asan_internal.h (original)
> +++ compiler-rt/trunk/lib/asan/asan_internal.h Tue Dec ?6 15:10:15 2011
> @@ -91,7 +91,6 @@
> ?extern int ? ?FLAG_demangle;
> ?extern bool ? FLAG_symbolize;
> ?extern int ? ?FLAG_v;
> -extern bool ? FLAG_mt;
> ?extern size_t FLAG_redzone;
> ?extern int ? ?FLAG_debug;
> ?extern bool ? FLAG_poison_shadow;
> @@ -177,7 +176,6 @@
>
> ?// -------------------------- Atomic ---------------- {{{1
> ?static inline int AtomicInc(int *a) {
> - ?if (!FLAG_mt) return ++(*a);
> ?#ifdef ANDROID
> ? return __atomic_inc(a) + 1;
> ?#else
> @@ -186,7 +184,6 @@
> ?}
>
> ?static inline int AtomicDec(int *a) {
> - ?if (!FLAG_mt) return --(*a);
> ?#ifdef ANDROID
> ? return __atomic_dec(a) - 1;
> ?#else
>
> Modified: compiler-rt/trunk/lib/asan/asan_rtl.cc
> URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/lib/asan/asan_rtl.cc?rev=145966&r1=145965&r2=145966&view=diff
> ==============================================================================
> --- compiler-rt/trunk/lib/asan/asan_rtl.cc (original)
> +++ compiler-rt/trunk/lib/asan/asan_rtl.cc Tue Dec ?6 15:10:15 2011
> @@ -57,7 +57,6 @@
> ?bool ? FLAG_fast_unwind = true;
>
> ?size_t FLAG_redzone; ?// power of two, >= 32
> -bool ? FLAG_mt; ?// set to 0 if you have only one thread.
> ?size_t FLAG_quarantine_size;
> ?int ? ?FLAG_demangle;
> ?bool ? FLAG_symbolize;
> @@ -665,7 +664,6 @@
> ? FLAG_debug = IntFlagValue(options, "debug=", 0);
> ? FLAG_replace_cfallocator = IntFlagValue(options, "replace_cfallocator=", 1);
> ? FLAG_fast_unwind = IntFlagValue(options, "fast_unwind=", 1);
> - ?FLAG_mt = IntFlagValue(options, "mt=", 1);
> ? FLAG_replace_str = IntFlagValue(options, "replace_str=", 1);
> ? FLAG_replace_intrin = IntFlagValue(options, "replace_intrin=", 0);
> ? FLAG_use_fake_stack = IntFlagValue(options, "use_fake_stack=", 1);
>
>
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits



-- 
Alexander Potapenko
Software Engineer
Google Moscow


From glider at google.com  Wed Dec  7 02:20:52 2011
From: glider at google.com (Alexander Potapenko)
Date: Wed, 7 Dec 2011 12:20:52 +0400
Subject: [llvm-commits] [compiler-rt] r145966 - in
 /compiler-rt/trunk/lib/asan: asan_internal.h asan_rtl.cc
In-Reply-To: 
References: <20111206211015.8CACC1BE003@llvm.org>
	
Message-ID: 

Oh, sorry, I see you've actually removed this flag.

On Wed, Dec 7, 2011 at 12:18 PM, Alexander Potapenko  wrote:
> What's this flag for? Can you choose a better name?
>
> On Wed, Dec 7, 2011 at 1:10 AM, Kostya Serebryany  wrote:
>> Author: kcc
>> Date: Tue Dec ?6 15:10:15 2011
>> New Revision: 145966
>>
>> URL: http://llvm.org/viewvc/llvm-project?rev=145966&view=rev
>> Log:
>> [asan] minor cleanup
>>
>> Modified:
>> ? ?compiler-rt/trunk/lib/asan/asan_internal.h
>> ? ?compiler-rt/trunk/lib/asan/asan_rtl.cc
>>
>> Modified: compiler-rt/trunk/lib/asan/asan_internal.h
>> URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/lib/asan/asan_internal.h?rev=145966&r1=145965&r2=145966&view=diff
>> ==============================================================================
>> --- compiler-rt/trunk/lib/asan/asan_internal.h (original)
>> +++ compiler-rt/trunk/lib/asan/asan_internal.h Tue Dec ?6 15:10:15 2011
>> @@ -91,7 +91,6 @@
>> ?extern int ? ?FLAG_demangle;
>> ?extern bool ? FLAG_symbolize;
>> ?extern int ? ?FLAG_v;
>> -extern bool ? FLAG_mt;
>> ?extern size_t FLAG_redzone;
>> ?extern int ? ?FLAG_debug;
>> ?extern bool ? FLAG_poison_shadow;
>> @@ -177,7 +176,6 @@
>>
>> ?// -------------------------- Atomic ---------------- {{{1
>> ?static inline int AtomicInc(int *a) {
>> - ?if (!FLAG_mt) return ++(*a);
>> ?#ifdef ANDROID
>> ? return __atomic_inc(a) + 1;
>> ?#else
>> @@ -186,7 +184,6 @@
>> ?}
>>
>> ?static inline int AtomicDec(int *a) {
>> - ?if (!FLAG_mt) return --(*a);
>> ?#ifdef ANDROID
>> ? return __atomic_dec(a) - 1;
>> ?#else
>>
>> Modified: compiler-rt/trunk/lib/asan/asan_rtl.cc
>> URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/lib/asan/asan_rtl.cc?rev=145966&r1=145965&r2=145966&view=diff
>> ==============================================================================
>> --- compiler-rt/trunk/lib/asan/asan_rtl.cc (original)
>> +++ compiler-rt/trunk/lib/asan/asan_rtl.cc Tue Dec ?6 15:10:15 2011
>> @@ -57,7 +57,6 @@
>> ?bool ? FLAG_fast_unwind = true;
>>
>> ?size_t FLAG_redzone; ?// power of two, >= 32
>> -bool ? FLAG_mt; ?// set to 0 if you have only one thread.
>> ?size_t FLAG_quarantine_size;
>> ?int ? ?FLAG_demangle;
>> ?bool ? FLAG_symbolize;
>> @@ -665,7 +664,6 @@
>> ? FLAG_debug = IntFlagValue(options, "debug=", 0);
>> ? FLAG_replace_cfallocator = IntFlagValue(options, "replace_cfallocator=", 1);
>> ? FLAG_fast_unwind = IntFlagValue(options, "fast_unwind=", 1);
>> - ?FLAG_mt = IntFlagValue(options, "mt=", 1);
>> ? FLAG_replace_str = IntFlagValue(options, "replace_str=", 1);
>> ? FLAG_replace_intrin = IntFlagValue(options, "replace_intrin=", 0);
>> ? FLAG_use_fake_stack = IntFlagValue(options, "use_fake_stack=", 1);
>>
>>
>> _______________________________________________
>> llvm-commits mailing list
>> llvm-commits at cs.uiuc.edu
>> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
>
>
>
> --
> Alexander Potapenko
> Software Engineer
> Google Moscow



-- 
Alexander Potapenko
Software Engineer
Google Moscow


From victor.umansky at intel.com  Wed Dec  7 09:03:24 2011
From: victor.umansky at intel.com (Umansky, Victor)
Date: Wed, 7 Dec 2011 17:03:24 +0200
Subject: [llvm-commits] x86 branch sequence optimization in LLVM code
 gen: please review
In-Reply-To: <90F01864-DEB5-4DEA-B8E2-625EF4449126@apple.com>
References: <021AD592C708E24FA11FD214489EC9BE0123F25260@hasmsx501.ger.corp.intel.com>
	
	<021AD592C708E24FA11FD214489EC9BE0123F95DDF@hasmsx501.ger.corp.intel.com>
	<90F01864-DEB5-4DEA-B8E2-625EF4449126@apple.com>
Message-ID: <021AD592C708E24FA11FD214489EC9BE0123FE98C8@hasmsx501.ger.corp.intel.com>

Hi Chad, Anton, Bruno,

Thank you for the suggestion.

Unfortunately, it won't work in the case of brcond.ll file.

Indeed I can introduce different "check-prefix" values in order to separate checks for "core2" case from those for "penryn" case.
However, the compilation of all functions in a file will be done unconditionally for both "RUN" cases. And this will inevitably lead to the test failure (in instruction selection) when a function using "ptest" LLVM intrinsic will be processed with "-mcpu=core2" option.
That's why I was not able to include the test cases for "ptest" intrinsic sequence to a file which will be compiled for a pre-Penryn target.

A solution which does work is to have legacy brcond.ll LIT tests running under "-mcpu=penryn".
I'm attaching the file.
Are you OK with such solution?

Best Regards,
    Victor

From: Chad Rosier [mailto:mcrosier at apple.com]
Sent: Tuesday, December 06, 2011 19:48
To: Umansky, Victor
Cc: Bruno Cardoso Lopes; llvm-commits at cs.uiuc.edu
Subject: Re: [llvm-commits] x86 branch sequence optimization in LLVM code gen: please review

Hi Victor,
You should be able to include the test in brcond.ll by specifying a new run line and using the -check-prefix option.

See: http://llvm.org/docs/TestingGuide.html#FileCheck

It would look something like this:

; RUN: llc < %s -mtriple=i386-apple-darwin10 -mcpu=penryn | FileCheck %s -check-prefix=FOO

declare i32 @llvm.x86.sse41.ptestz(<4 x float> %p1, <4 x float> %p2) nounwind

define <4 x float> @test1(<4 x float> %a, <4 x float> %b) nounwind {
entry:
; FOO: test1:
; FOO: ptest
; FOO-NEXT: je

etc..

 Chad

On Dec 6, 2011, at 12:52 AM, Umansky, Victor wrote:


Hi Bruno,

Thank you for the response.
I've changed the LIT test towards common look (attached).

Unfortunately, I cannot put it inside brcond.ll because the "ptest" instruction was introduced only with SSE4.1 (i.e. requires "-mcpu=penryn"), while the  current version of brcond.ll is processed with "-mcpu=core2".
Will the replacement of-mcpu in brcond.ll with "penryn" be backward-compat with regard to LIT results?

Best Regards,
    Victor

From: Bruno Cardoso Lopes [mailto:bruno.cardoso at gmail.com]
Sent: Monday, December 05, 2011 19:13
To: Umansky, Victor
Cc: llvm-commits at cs.uiuc.edu
Subject: Re: [llvm-commits] x86 branch sequence optimization in LLVM code gen: please review

Hi Victor,
On Mon, Dec 5, 2011 at 10:26 AM, Umansky, Victor > wrote:
Hi,

My name is Victor Umansky; I'm an engineer in Intel OpenCL Team.

The attached patch contains an optimization of ptest-conditioned branch.

I.e., the following LLVM IR code

  %res = call i32 @llvm.x86.sse41.ptestz(<4 x float> %a, <4 x float> %a) nounwind
  %tmp = and i32 %res, 1
  %one = icmp eq i32 %tmp, 0
  br i1 %one, label %label1, label %label2


ends with the following x86 machine code sequence:

    ptest     XMM3, XMM3
    sete    AL
    movzx    EAX, AL
    test    EAX, EAX
    jne    LBB18_26


which can be optimized to:

             ptest     XMM3, XMM3
             je    LBB18_26



The current machine code sequence stems from the need to coordinate i32 return type from the ptestz intrinsic with i1 condition type for branch IR instruction.
Consequently we can optimize it in x86 codegen backend where the both condition producer (ptest) amd consumer (jcc) use the same x86 EFLAGS register, and thus in-between conversions of the condition can be quietly dropped.

The optimization is focused on x86 DAG combining (post-legalization stage) which recognizes the sequence and converts it to the minimized one.

The attached patch file includes both the x86 backend instruction combining modification and a LIT regression test for it.


I'd like to commit the fix to the LLVM trunk, and your feedback will be mostly appreciated.



+; RUN: llc %s -march=x86-64 -mcpu=corei7 -o %t.asm
+; RUN: FileCheck %s --input-file=%t.asm

Please do like the other tests, and read the file with "< %s". Also, place it under test/CodeGen/X86/brcond.ll

--
Bruno Cardoso Lopes
http://www.brunocardoso.cc
---------------------------------------------------------------------
Intel Israel (74) Limited

This e-mail and any attachments may contain confidential material for
the sole use of the intended recipient(s). Any review or distribution
by others is strictly prohibited. If you are not the intended
recipient, please contact the sender and delete all copies._______________________________________________
llvm-commits mailing list
llvm-commits at cs.uiuc.edu
http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits

---------------------------------------------------------------------
Intel Israel (74) Limited

This e-mail and any attachments may contain confidential material for
the sole use of the intended recipient(s). Any review or distribution
by others is strictly prohibited. If you are not the intended
recipient, please contact the sender and delete all copies.
-------------- next part --------------
An HTML attachment was scrubbed...
URL: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20111207/69c65299/attachment-0001.html 
-------------- next part --------------
A non-text attachment was scrubbed...
Name: brcond.ll.patch
Type: application/octet-stream
Size: 1939 bytes
Desc: brcond.ll.patch
Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20111207/69c65299/attachment-0001.obj 

From 6yearold at gmail.com  Wed Dec  7 09:49:44 2011
From: 6yearold at gmail.com (arrowdodger)
Date: Wed, 7 Dec 2011 18:49:44 +0300
Subject: [llvm-commits] [PATCH][CMake] Connect llvm-cov tool to the
	build.
Message-ID: 

I've found that llvm-cov tool is not being built by CMake buildsystem, this
patch fixes this.
-------------- next part --------------
An HTML attachment was scrubbed...
URL: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20111207/1c9ab4e8/attachment.html 
-------------- next part --------------
A non-text attachment was scrubbed...
Name: llvm-cov.patch
Type: text/x-patch
Size: 363 bytes
Desc: not available
Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20111207/1c9ab4e8/attachment.bin 

From jan_sjodin at yahoo.com  Wed Dec  7 09:50:15 2011
From: jan_sjodin at yahoo.com (Jan Sjodin)
Date: Wed, 7 Dec 2011 07:50:15 -0800 (PST)
Subject: [llvm-commits] FMA4 cleanup patch
Message-ID: <1323273015.33804.YahooMailNeo@web161505.mail.bf1.yahoo.com>

Patch to clean up the FMA4 encoding. I had accidentally swapped the operands in the asm strings for the FMA4 rr patterns, which caused some confusion. 

Ok to commit?

- Jan
-------------- next part --------------
An HTML attachment was scrubbed...
URL: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20111207/685e26fe/attachment.html 
-------------- next part --------------
A non-text attachment was scrubbed...
Name: 0057_fma4_cleanup.patch
Type: application/octet-stream
Size: 2914 bytes
Desc: not available
Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20111207/685e26fe/attachment.obj 

From baldrick at free.fr  Wed Dec  7 11:14:21 2011
From: baldrick at free.fr (Duncan Sands)
Date: Wed, 07 Dec 2011 17:14:21 -0000
Subject: [llvm-commits] [llvm] r146036 - /llvm/trunk/tools/opt/opt.cpp
Message-ID: <20111207171421.33D622A6C12C@llvm.org>

Author: baldrick
Date: Wed Dec  7 11:14:20 2011
New Revision: 146036

URL: http://llvm.org/viewvc/llvm-project?rev=146036&view=rev
Log:
When doing "opt -O2" verify the bitcode like is done for
"opt -std-compile-opts".

Modified:
    llvm/trunk/tools/opt/opt.cpp

Modified: llvm/trunk/tools/opt/opt.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/opt/opt.cpp?rev=146036&r1=146035&r2=146036&view=diff
==============================================================================
--- llvm/trunk/tools/opt/opt.cpp (original)
+++ llvm/trunk/tools/opt/opt.cpp Wed Dec  7 11:14:20 2011
@@ -407,6 +407,8 @@
 /// OptLevel - Optimization Level
 static void AddOptimizationPasses(PassManagerBase &MPM,FunctionPassManager &FPM,
                                   unsigned OptLevel) {
+  FPM.add(createVerifierPass());                  // Verify that input is correct
+
   PassManagerBuilder Builder;
   Builder.OptLevel = OptLevel;
 



From baldrick at free.fr  Wed Dec  7 11:18:31 2011
From: baldrick at free.fr (Duncan Sands)
Date: Wed, 07 Dec 2011 17:18:31 -0000
Subject: [llvm-commits] [llvm] r146037 -
	/llvm/trunk/lib/Transforms/IPO/PassManagerBuilder.cpp
Message-ID: <20111207171831.6768A2A6C12C@llvm.org>

Author: baldrick
Date: Wed Dec  7 11:18:31 2011
New Revision: 146037

URL: http://llvm.org/viewvc/llvm-project?rev=146037&view=rev
Log:
Remove unused include.

Modified:
    llvm/trunk/lib/Transforms/IPO/PassManagerBuilder.cpp

Modified: llvm/trunk/lib/Transforms/IPO/PassManagerBuilder.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/IPO/PassManagerBuilder.cpp?rev=146037&r1=146036&r2=146037&view=diff
==============================================================================
--- llvm/trunk/lib/Transforms/IPO/PassManagerBuilder.cpp (original)
+++ llvm/trunk/lib/Transforms/IPO/PassManagerBuilder.cpp Wed Dec  7 11:18:31 2011
@@ -21,7 +21,6 @@
 #include "llvm/DefaultPasses.h"
 #include "llvm/PassManager.h"
 #include "llvm/Analysis/Passes.h"
-#include "llvm/Analysis/Verifier.h"
 #include "llvm/Target/TargetLibraryInfo.h"
 #include "llvm/Transforms/Scalar.h"
 #include "llvm/Transforms/IPO.h"



From hfinkel at anl.gov  Wed Dec  7 11:48:13 2011
From: hfinkel at anl.gov (Hal Finkel)
Date: Wed, 07 Dec 2011 11:48:13 -0600
Subject: [llvm-commits] [LLVMdev] Dead register (was Re: [llvm] r145819)
In-Reply-To: <1323214755.2507.3294.camel@sapling>
References: <20111205175518.343FF2A6C12C@llvm.org>
	
	<1323112465.2507.3170.camel@sapling>
	<1323118601.2507.3183.camel@sapling>
	
	<1323214755.2507.3294.camel@sapling>
Message-ID: <1323280093.2507.3305.camel@sapling>

Ping.

And, if I count correctly, I meant six statements, not four. Regardless,
this is the last remaining -verify-machineinstrs error in PPC that I've
found so far, so please help me fix it.

Thanks again,
Hal

On Tue, 2011-12-06 at 17:39 -0600, Hal Finkel wrote:
> On Mon, 2011-12-05 at 13:18 -0800, Jakob Stoklund Olesen wrote:
> > On Dec 5, 2011, at 12:56 PM, Hal Finkel wrote:
> > 
> > > RegScavenger is complaining about use of an undefined register, CTR8, in
> > > the BCTR8 instruction, in the following instance (this is from the PPC
> > > backend):
> > > 
> > > BB#38: derived from LLVM BB %for.end50
> > >    Predecessors according to CFG: BB#36
> > >        %X3 = LD 0, ; mem:LD8[FixedStack27]
> > >        %X4 = RLDICR %X3, 3, 60
> > >        %X5 = LI8 [TF=4]
> > >        %X5 = ADDIS8 %X5, [TF=8]
> > >        %X4 = LDX %X4, %X5; mem:LD8[JumpTable]
> > >        MTCTR8 %X4, %CTR8
> > >        BCTR8 %CTR8, %RM
> > >    Successors according to CFG: BB#23 BB#15 BB#7 BB#8 BB#9 BB#10 BB#11
> > > BB#25 BB#12 BB#16 BB#18 BB#13 BB#17
> > > 
> > > How could CRT8 be marked implicitly-defined and also dead in the same
> > > instruction when it is clearly used in the next instruction?
> > 
> > This is the kind of sloppy liveness, I was talking about ;-)
> > 
> > llc -verify-machineinstrs should give you better info.
> 
> Unfortunately, this just tells me what I already knew:
> 
> *** Bad machine code: Using an undefined physical register ***
> - function:    check
> - basic block: for.end50 0x2bef428 (BB#38)
> - instruction: BCTR8 %CTR8, %RM
> - operand 0:   %CTR8
> LLVM ERROR: Found 1 machine code errors.
> 
> This comes from the following four statements in
> PPCDAGToDAGISel::Select; what's wrong here?
> SDValue Chain = N->getOperand(0);
> SDValue Target = N->getOperand(1);
> unsigned Opc = PPC::MTCTR8;
> unsigned Reg = PPC::BCTR8;
> Chain = SDValue(CurDAG->getMachineNode(Opc, dl, MVT::Other, Target,
>                                            Chain), 0);
> return CurDAG->SelectNodeTo(N, Reg, MVT::Other, Chain);
> 
> Thanks again,
> Hal
> 
> > 
> > /jakob
> > 
> 

-- 
Hal Finkel
Postdoctoral Appointee
Leadership Computing Facility
Argonne National Laboratory


From grosbach at apple.com  Wed Dec  7 11:50:29 2011
From: grosbach at apple.com (Jim Grosbach)
Date: Wed, 07 Dec 2011 17:50:29 -0000
Subject: [llvm-commits] [llvm] r146038 - in /llvm/trunk/test/MC:
 ARM/darwin-ARM-reloc.s ARM/darwin-Thumb-reloc.s ARM/nop-armv4-padding.s
 ARM/nop-armv6t2-padding.s ARM/nop-thumb-padding.s ARM/nop-thumb2-padding.s
 ARM/thumb2-movt-fixup.s MachO/ARM/darwin-ARM-reloc.s
 MachO/ARM/darwin-Thumb-reloc.s MachO/ARM/nop-armv4-padding.s
 MachO/ARM/nop-armv6t2-padding.s MachO/ARM/nop-thumb-padding.s
 MachO/ARM/nop-thumb2-padding.s MachO/ARM/thumb2-movt-fixup.s
Message-ID: <20111207175029.1995F2A6C12C@llvm.org>

Author: grosbach
Date: Wed Dec  7 11:50:28 2011
New Revision: 146038

URL: http://llvm.org/viewvc/llvm-project?rev=146038&view=rev
Log:
Tidy up. Move MachO tests to MachO directory.

Added:
    llvm/trunk/test/MC/MachO/ARM/darwin-ARM-reloc.s
      - copied unchanged from r146037, llvm/trunk/test/MC/ARM/darwin-ARM-reloc.s
    llvm/trunk/test/MC/MachO/ARM/darwin-Thumb-reloc.s
      - copied unchanged from r146037, llvm/trunk/test/MC/ARM/darwin-Thumb-reloc.s
    llvm/trunk/test/MC/MachO/ARM/nop-armv4-padding.s
      - copied unchanged from r146037, llvm/trunk/test/MC/ARM/nop-armv4-padding.s
    llvm/trunk/test/MC/MachO/ARM/nop-armv6t2-padding.s
      - copied unchanged from r146037, llvm/trunk/test/MC/ARM/nop-armv6t2-padding.s
    llvm/trunk/test/MC/MachO/ARM/nop-thumb-padding.s
      - copied unchanged from r146037, llvm/trunk/test/MC/ARM/nop-thumb-padding.s
    llvm/trunk/test/MC/MachO/ARM/nop-thumb2-padding.s
      - copied unchanged from r146037, llvm/trunk/test/MC/ARM/nop-thumb2-padding.s
    llvm/trunk/test/MC/MachO/ARM/thumb2-movt-fixup.s
      - copied unchanged from r146037, llvm/trunk/test/MC/ARM/thumb2-movt-fixup.s
Removed:
    llvm/trunk/test/MC/ARM/darwin-ARM-reloc.s
    llvm/trunk/test/MC/ARM/darwin-Thumb-reloc.s
    llvm/trunk/test/MC/ARM/nop-armv4-padding.s
    llvm/trunk/test/MC/ARM/nop-armv6t2-padding.s
    llvm/trunk/test/MC/ARM/nop-thumb-padding.s
    llvm/trunk/test/MC/ARM/nop-thumb2-padding.s
    llvm/trunk/test/MC/ARM/thumb2-movt-fixup.s

Removed: llvm/trunk/test/MC/ARM/darwin-ARM-reloc.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/darwin-ARM-reloc.s?rev=146037&view=auto
==============================================================================
--- llvm/trunk/test/MC/ARM/darwin-ARM-reloc.s (original)
+++ llvm/trunk/test/MC/ARM/darwin-ARM-reloc.s (removed)
@@ -1,171 +0,0 @@
-@ RUN: llvm-mc -n -triple armv7-apple-darwin10 %s -filetype=obj -o %t.obj
-@ RUN: macho-dump --dump-section-data < %t.obj > %t.dump
-@ RUN: FileCheck < %t.dump %s
-
-	.syntax unified
-        .text
-_f0:
-        bl _printf
-
-_f1:
-        bl _f0
-
-        .data
-_d0:
-Ld0_0:  
-        .long Lsc0_0 - Ld0_0
-        
-	.section	__TEXT,__cstring,cstring_literals
-Lsc0_0:
-        .long 0
-
-@ CHECK: ('cputype', 12)
-@ CHECK: ('cpusubtype', 9)
-@ CHECK: ('filetype', 1)
-@ CHECK: ('num_load_commands', 3)
-@ CHECK: ('load_commands_size', 364)
-@ CHECK: ('flag', 0)
-@ CHECK: ('load_commands', [
-@ CHECK:   # Load Command 0
-@ CHECK:  (('command', 1)
-@ CHECK:   ('size', 260)
-@ CHECK:   ('segment_name', '\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00')
-@ CHECK:   ('vm_addr', 0)
-@ CHECK:   ('vm_size', 16)
-@ CHECK:   ('file_offset', 392)
-@ CHECK:   ('file_size', 16)
-@ CHECK:   ('maxprot', 7)
-@ CHECK:   ('initprot', 7)
-@ CHECK:   ('num_sections', 3)
-@ CHECK:   ('flags', 0)
-@ CHECK:   ('sections', [
-@ CHECK:     # Section 0
-@ CHECK:    (('section_name', '__text\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00')
-@ CHECK:     ('segment_name', '__TEXT\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00')
-@ CHECK:     ('address', 0)
-@ CHECK:     ('size', 8)
-@ CHECK:     ('offset', 392)
-@ CHECK:     ('alignment', 0)
-@ CHECK:     ('reloc_offset', 408)
-@ CHECK:     ('num_reloc', 2)
-@ CHECK:     ('flags', 0x80000400)
-@ CHECK:     ('reserved1', 0)
-@ CHECK:     ('reserved2', 0)
-@ CHECK:    ),
-@ CHECK:   ('_relocations', [
-@ CHECK:     # Relocation 0
-@ CHECK:     (('word-0', 0x4),
-@ CHECK:      ('word-1', 0x55000001)),
-@ CHECK:     # Relocation 1
-@ CHECK:     (('word-0', 0x0),
-@ CHECK:      ('word-1', 0x5d000003)),
-@ CHECK:   ])
-@ CHECK:   ('_section_data', 'feffffeb fdffffeb')
-@ CHECK:     # Section 1
-@ CHECK:    (('section_name', '__data\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00')
-@ CHECK:     ('segment_name', '__DATA\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00')
-@ CHECK:     ('address', 8)
-@ CHECK:     ('size', 4)
-@ CHECK:     ('offset', 400)
-@ CHECK:     ('alignment', 0)
-@ CHECK:     ('reloc_offset', 424)
-@ CHECK:     ('num_reloc', 2)
-@ CHECK:     ('flags', 0x0)
-@ CHECK:     ('reserved1', 0)
-@ CHECK:     ('reserved2', 0)
-@ CHECK:    ),
-@ CHECK:   ('_relocations', [
-@ CHECK:     # Relocation 0
-@ CHECK:     (('word-0', 0xa2000000),
-@ CHECK:      ('word-1', 0xc)),
-@ CHECK:     # Relocation 1
-@ CHECK:     (('word-0', 0xa1000000),
-@ CHECK:      ('word-1', 0x8)),
-@ CHECK:   ])
-@ CHECK:   ('_section_data', '04000000')
-@ CHECK:     # Section 2
-@ CHECK:    (('section_name', '__cstring\x00\x00\x00\x00\x00\x00\x00')
-@ CHECK:     ('segment_name', '__TEXT\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00')
-@ CHECK:     ('address', 12)
-@ CHECK:     ('size', 4)
-@ CHECK:     ('offset', 404)
-@ CHECK:     ('alignment', 0)
-@ CHECK:     ('reloc_offset', 0)
-@ CHECK:     ('num_reloc', 0)
-@ CHECK:     ('flags', 0x2)
-@ CHECK:     ('reserved1', 0)
-@ CHECK:     ('reserved2', 0)
-@ CHECK:    ),
-@ CHECK:   ('_relocations', [
-@ CHECK:   ])
-@ CHECK:   ('_section_data', '00000000')
-@ CHECK:   ])
-@ CHECK:  ),
-@ CHECK:   # Load Command 1
-@ CHECK:  (('command', 2)
-@ CHECK:   ('size', 24)
-@ CHECK:   ('symoff', 440)
-@ CHECK:   ('nsyms', 4)
-@ CHECK:   ('stroff', 488)
-@ CHECK:   ('strsize', 24)
-@ CHECK:   ('_string_data', '\x00_printf\x00_f0\x00_f1\x00_d0\x00\x00\x00\x00')
-@ CHECK:   ('_symbols', [
-@ CHECK:     # Symbol 0
-@ CHECK:    (('n_strx', 9)
-@ CHECK:     ('n_type', 0xe)
-@ CHECK:     ('n_sect', 1)
-@ CHECK:     ('n_desc', 0)
-@ CHECK:     ('n_value', 0)
-@ CHECK:     ('_string', '_f0')
-@ CHECK:    ),
-@ CHECK:     # Symbol 1
-@ CHECK:    (('n_strx', 13)
-@ CHECK:     ('n_type', 0xe)
-@ CHECK:     ('n_sect', 1)
-@ CHECK:     ('n_desc', 0)
-@ CHECK:     ('n_value', 4)
-@ CHECK:     ('_string', '_f1')
-@ CHECK:    ),
-@ CHECK:     # Symbol 2
-@ CHECK:    (('n_strx', 17)
-@ CHECK:     ('n_type', 0xe)
-@ CHECK:     ('n_sect', 2)
-@ CHECK:     ('n_desc', 0)
-@ CHECK:     ('n_value', 8)
-@ CHECK:     ('_string', '_d0')
-@ CHECK:    ),
-@ CHECK:     # Symbol 3
-@ CHECK:    (('n_strx', 1)
-@ CHECK:     ('n_type', 0x1)
-@ CHECK:     ('n_sect', 0)
-@ CHECK:     ('n_desc', 0)
-@ CHECK:     ('n_value', 0)
-@ CHECK:     ('_string', '_printf')
-@ CHECK:    ),
-@ CHECK:   ])
-@ CHECK:  ),
-@ CHECK:   # Load Command 2
-@ CHECK:  (('command', 11)
-@ CHECK:   ('size', 80)
-@ CHECK:   ('ilocalsym', 0)
-@ CHECK:   ('nlocalsym', 3)
-@ CHECK:   ('iextdefsym', 3)
-@ CHECK:   ('nextdefsym', 0)
-@ CHECK:   ('iundefsym', 3)
-@ CHECK:   ('nundefsym', 1)
-@ CHECK:   ('tocoff', 0)
-@ CHECK:   ('ntoc', 0)
-@ CHECK:   ('modtaboff', 0)
-@ CHECK:   ('nmodtab', 0)
-@ CHECK:   ('extrefsymoff', 0)
-@ CHECK:   ('nextrefsyms', 0)
-@ CHECK:   ('indirectsymoff', 0)
-@ CHECK:   ('nindirectsyms', 0)
-@ CHECK:   ('extreloff', 0)
-@ CHECK:   ('nextrel', 0)
-@ CHECK:   ('locreloff', 0)
-@ CHECK:   ('nlocrel', 0)
-@ CHECK:   ('_indirect_symbols', [
-@ CHECK:   ])
-@ CHECK:  ),
-@ CHECK: ])

Removed: llvm/trunk/test/MC/ARM/darwin-Thumb-reloc.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/darwin-Thumb-reloc.s?rev=146037&view=auto
==============================================================================
--- llvm/trunk/test/MC/ARM/darwin-Thumb-reloc.s (original)
+++ llvm/trunk/test/MC/ARM/darwin-Thumb-reloc.s (removed)
@@ -1,139 +0,0 @@
-@ RUN: llvm-mc -n -triple thumbv7-apple-darwin10 %s -filetype=obj -o %t.obj
-@ RUN: macho-dump --dump-section-data < %t.obj > %t.dump
-@ RUN: FileCheck < %t.dump %s
-
-	.syntax unified
-	.section	__TEXT,__text,regular,pure_instructions
-	.globl	_main
-	.align	2
-	.code	16
-	.thumb_func	_main
-_main:
-LPC0_0:
-	blx	_printf
-	.align	2
-LCPI0_0:
-	.long	L_.str-(LPC0_0+4)
-
-	.section	__TEXT,__cstring,cstring_literals
-	.align	2
-L_.str:
-	.asciz	 "s0"
-
-.subsections_via_symbols
-
-@ CHECK: ('cputype', 12)
-@ CHECK: ('cpusubtype', 9)
-@ CHECK: ('filetype', 1)
-@ CHECK: ('num_load_commands', 3)
-@ CHECK: ('load_commands_size', 296)
-@ CHECK: ('flag', 8192)
-@ CHECK: ('load_commands', [
-@ CHECK:   # Load Command 0
-@ CHECK:  (('command', 1)
-@ CHECK:   ('size', 192)
-@ CHECK:   ('segment_name', '\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00')
-@ CHECK:   ('vm_addr', 0)
-@ CHECK:   ('vm_size', 11)
-@ CHECK:   ('file_offset', 324)
-@ CHECK:   ('file_size', 11)
-@ CHECK:   ('maxprot', 7)
-@ CHECK:   ('initprot', 7)
-@ CHECK:   ('num_sections', 2)
-@ CHECK:   ('flags', 0)
-@ CHECK:   ('sections', [
-@ CHECK:     # Section 0
-@ CHECK:    (('section_name', '__text\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00')
-@ CHECK:     ('segment_name', '__TEXT\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00')
-@ CHECK:     ('address', 0)
-@ CHECK:     ('size', 8)
-@ CHECK:     ('offset', 324)
-@ CHECK:     ('alignment', 2)
-@ CHECK:     ('reloc_offset', 336)
-@ CHECK:     ('num_reloc', 3)
-@ CHECK:     ('flags', 0x80000400)
-@ CHECK:     ('reserved1', 0)
-@ CHECK:     ('reserved2', 0)
-@ CHECK:    ),
-@ CHECK:   ('_relocations', [
-@ CHECK:     # Relocation 0
-@ CHECK:     (('word-0', 0xa2000004),
-@ CHECK:      ('word-1', 0x8)),
-@ CHECK:     # Relocation 1
-@ CHECK:     (('word-0', 0xa1000000),
-@ CHECK:      ('word-1', 0x0)),
-@ CHECK:     # Relocation 2
-@ CHECK:     (('word-0', 0x0),
-@ CHECK:      ('word-1', 0x6d000001)),
-@ CHECK:   ])
-@ CHECK-FIXME:   ('_section_data', 'fff7feef 04000000')
-@ CHECK:     # Section 1
-@ CHECK:    (('section_name', '__cstring\x00\x00\x00\x00\x00\x00\x00')
-@ CHECK:     ('segment_name', '__TEXT\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00')
-@ CHECK:     ('address', 8)
-@ CHECK:     ('size', 3)
-@ CHECK:     ('offset', 332)
-@ CHECK:     ('alignment', 2)
-@ CHECK:     ('reloc_offset', 0)
-@ CHECK:     ('num_reloc', 0)
-@ CHECK:     ('flags', 0x2)
-@ CHECK:     ('reserved1', 0)
-@ CHECK:     ('reserved2', 0)
-@ CHECK:    ),
-@ CHECK:   ('_relocations', [
-@ CHECK:   ])
-@ CHECK:   ('_section_data', '733000')
-@ CHECK:   ])
-@ CHECK:  ),
-@ CHECK:   # Load Command 1
-@ CHECK:  (('command', 2)
-@ CHECK:   ('size', 24)
-@ CHECK:   ('symoff', 360)
-@ CHECK:   ('nsyms', 2)
-@ CHECK:   ('stroff', 384)
-@ CHECK:   ('strsize', 16)
-@ CHECK:   ('_string_data', '\x00_main\x00_printf\x00\x00')
-@ CHECK:   ('_symbols', [
-@ CHECK:     # Symbol 0
-@ CHECK:    (('n_strx', 1)
-@ CHECK:     ('n_type', 0xf)
-@ CHECK:     ('n_sect', 1)
-@ CHECK:     ('n_desc', 8)
-@ CHECK:     ('n_value', 0)
-@ CHECK:     ('_string', '_main')
-@ CHECK:    ),
-@ CHECK:     # Symbol 1
-@ CHECK:    (('n_strx', 7)
-@ CHECK:     ('n_type', 0x1)
-@ CHECK:     ('n_sect', 0)
-@ CHECK:     ('n_desc', 0)
-@ CHECK:     ('n_value', 0)
-@ CHECK:     ('_string', '_printf')
-@ CHECK:    ),
-@ CHECK:   ])
-@ CHECK:  ),
-@ CHECK:   # Load Command 2
-@ CHECK:  (('command', 11)
-@ CHECK:   ('size', 80)
-@ CHECK:   ('ilocalsym', 0)
-@ CHECK:   ('nlocalsym', 0)
-@ CHECK:   ('iextdefsym', 0)
-@ CHECK:   ('nextdefsym', 1)
-@ CHECK:   ('iundefsym', 1)
-@ CHECK:   ('nundefsym', 1)
-@ CHECK:   ('tocoff', 0)
-@ CHECK:   ('ntoc', 0)
-@ CHECK:   ('modtaboff', 0)
-@ CHECK:   ('nmodtab', 0)
-@ CHECK:   ('extrefsymoff', 0)
-@ CHECK:   ('nextrefsyms', 0)
-@ CHECK:   ('indirectsymoff', 0)
-@ CHECK:   ('nindirectsyms', 0)
-@ CHECK:   ('extreloff', 0)
-@ CHECK:   ('nextrel', 0)
-@ CHECK:   ('locreloff', 0)
-@ CHECK:   ('nlocrel', 0)
-@ CHECK:   ('_indirect_symbols', [
-@ CHECK:   ])
-@ CHECK:  ),
-@ CHECK: ])

Removed: llvm/trunk/test/MC/ARM/nop-armv4-padding.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/nop-armv4-padding.s?rev=146037&view=auto
==============================================================================
--- llvm/trunk/test/MC/ARM/nop-armv4-padding.s (original)
+++ llvm/trunk/test/MC/ARM/nop-armv4-padding.s (removed)
@@ -1,10 +0,0 @@
-@ RUN: llvm-mc -triple armv4-apple-darwin %s -filetype=obj -o %t.obj
-@ RUN: macho-dump --dump-section-data < %t.obj > %t.dump
-@ RUN: FileCheck %s < %t.dump
-
-x:
-      add r0, r1, r2
-      .align 4
-      add r0, r1, r2
-
-@ CHECK: ('_section_data', '020081e0 00001a0e 00001a0e 00001a0e 020081e0')

Removed: llvm/trunk/test/MC/ARM/nop-armv6t2-padding.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/nop-armv6t2-padding.s?rev=146037&view=auto
==============================================================================
--- llvm/trunk/test/MC/ARM/nop-armv6t2-padding.s (original)
+++ llvm/trunk/test/MC/ARM/nop-armv6t2-padding.s (removed)
@@ -1,10 +0,0 @@
-@ RUN: llvm-mc -triple armv6t2-apple-darwin %s -filetype=obj -o %t.obj
-@ RUN: macho-dump --dump-section-data < %t.obj > %t.dump
-@ RUN: FileCheck %s < %t.dump
-
-x:
-      add r0, r1, r2
-      .align 4
-      add r0, r1, r2
-
-@ CHECK: ('_section_data', '020081e0 00f020e3 00f020e3 00f020e3 020081e0')

Removed: llvm/trunk/test/MC/ARM/nop-thumb-padding.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/nop-thumb-padding.s?rev=146037&view=auto
==============================================================================
--- llvm/trunk/test/MC/ARM/nop-thumb-padding.s (original)
+++ llvm/trunk/test/MC/ARM/nop-thumb-padding.s (removed)
@@ -1,12 +0,0 @@
-@ RUN: llvm-mc -triple armv6-apple-darwin %s -filetype=obj -o %t.obj
-@ RUN: macho-dump --dump-section-data < %t.obj > %t.dump
-@ RUN: FileCheck %s < %t.dump
-
-.thumb_func x
-.code 16
-x:
-      adds r0, r1, r2
-      .align 4
-      adds r0, r1, r2
-
-@ CHECK: ('_section_data', '8818c046 c046c046 c046c046 c046c046 8818')

Removed: llvm/trunk/test/MC/ARM/nop-thumb2-padding.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/nop-thumb2-padding.s?rev=146037&view=auto
==============================================================================
--- llvm/trunk/test/MC/ARM/nop-thumb2-padding.s (original)
+++ llvm/trunk/test/MC/ARM/nop-thumb2-padding.s (removed)
@@ -1,12 +0,0 @@
-@ RUN: llvm-mc -triple armv7-apple-darwin %s -filetype=obj -o %t.obj
-@ RUN: macho-dump --dump-section-data < %t.obj > %t.dump
-@ RUN: FileCheck %s < %t.dump
-
-.thumb_func x
-.code 16
-x:
-      adds r0, r1, r2
-      .align 4
-      adds r0, r1, r2
-
-@ CHECK: ('_section_data', '881800bf 00bf00bf 00bf00bf 00bf00bf 8818')

Removed: llvm/trunk/test/MC/ARM/thumb2-movt-fixup.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/thumb2-movt-fixup.s?rev=146037&view=auto
==============================================================================
--- llvm/trunk/test/MC/ARM/thumb2-movt-fixup.s (original)
+++ llvm/trunk/test/MC/ARM/thumb2-movt-fixup.s (removed)
@@ -1,17 +0,0 @@
-@ RUN: llvm-mc -mcpu=cortex-a8 -triple thumbv7-apple-darwin10 -filetype=obj -o - < %s | macho-dump | FileCheck %s
-
-_fred:
-	movt	r3, :upper16:(_wilma-(LPC0_0+4))
-LPC0_0:
-
-_wilma:
-  .long 0
-
-@ CHECK:  ('_relocations', [
-@ CHECK:    # Relocation 0
-@ CHECK:    (('word-0', 0xb9000000),
-@ CHECK:     ('word-1', 0x4)),
-@ CHECK:    # Relocation 1
-@ CHECK:    (('word-0', 0xb100fffc),
-@ CHECK:     ('word-1', 0x4)),
-



From grosbach at apple.com  Wed Dec  7 11:51:15 2011
From: grosbach at apple.com (Jim Grosbach)
Date: Wed, 07 Dec 2011 17:51:15 -0000
Subject: [llvm-commits] [llvm] r146039 - in /llvm/trunk:
 lib/Target/ARM/ARMInstrNEON.td test/MC/ARM/neon-cmp-encoding.s
Message-ID: <20111207175115.EC1E02A6C12C@llvm.org>

Author: grosbach
Date: Wed Dec  7 11:51:15 2011
New Revision: 146039

URL: http://llvm.org/viewvc/llvm-project?rev=146039&view=rev
Log:
ARM NEON VCLT(register) is a pseudo aliasing VCGT(register).

Modified:
    llvm/trunk/lib/Target/ARM/ARMInstrNEON.td
    llvm/trunk/test/MC/ARM/neon-cmp-encoding.s

Modified: llvm/trunk/lib/Target/ARM/ARMInstrNEON.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrNEON.td?rev=146039&r1=146038&r2=146039&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrNEON.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrNEON.td Wed Dec  7 11:51:15 2011
@@ -5396,3 +5396,34 @@
 defm : VFPDTAnyInstAlias<"vmov${p}", "$Vd, $Vm",
                          (VORRq QPR:$Vd, QPR:$Vm, QPR:$Vm, pred:$p)>;
 
+// VCLT (register) is an assembler alias for VCGT w/ the operands reversed.
+// D-register versions.
+def : NEONInstAlias<"vclt${p}.s8 $Dd, $Dn, $Dm",
+                    (VCGTsv8i8 DPR:$Dd, DPR:$Dm, DPR:$Dn, pred:$p)>;
+def : NEONInstAlias<"vclt${p}.s16 $Dd, $Dn, $Dm",
+                    (VCGTsv4i16 DPR:$Dd, DPR:$Dm, DPR:$Dn, pred:$p)>;
+def : NEONInstAlias<"vclt${p}.s32 $Dd, $Dn, $Dm",
+                    (VCGTsv2i32 DPR:$Dd, DPR:$Dm, DPR:$Dn, pred:$p)>;
+def : NEONInstAlias<"vclt${p}.u8 $Dd, $Dn, $Dm",
+                    (VCGTuv8i8 DPR:$Dd, DPR:$Dm, DPR:$Dn, pred:$p)>;
+def : NEONInstAlias<"vclt${p}.u16 $Dd, $Dn, $Dm",
+                    (VCGTuv4i16 DPR:$Dd, DPR:$Dm, DPR:$Dn, pred:$p)>;
+def : NEONInstAlias<"vclt${p}.u32 $Dd, $Dn, $Dm",
+                    (VCGTuv2i32 DPR:$Dd, DPR:$Dm, DPR:$Dn, pred:$p)>;
+def : NEONInstAlias<"vclt${p}.f32 $Dd, $Dn, $Dm",
+                    (VCGTfd DPR:$Dd, DPR:$Dm, DPR:$Dn, pred:$p)>;
+// Q-register versions.
+def : NEONInstAlias<"vclt${p}.s8 $Qd, $Qn, $Qm",
+                    (VCGTsv16i8 QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p)>;
+def : NEONInstAlias<"vclt${p}.s16 $Qd, $Qn, $Qm",
+                    (VCGTsv8i16 QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p)>;
+def : NEONInstAlias<"vclt${p}.s32 $Qd, $Qn, $Qm",
+                    (VCGTsv4i32 QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p)>;
+def : NEONInstAlias<"vclt${p}.u8 $Qd, $Qn, $Qm",
+                    (VCGTuv16i8 QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p)>;
+def : NEONInstAlias<"vclt${p}.u16 $Qd, $Qn, $Qm",
+                    (VCGTuv8i16 QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p)>;
+def : NEONInstAlias<"vclt${p}.u32 $Qd, $Qn, $Qm",
+                    (VCGTuv4i32 QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p)>;
+def : NEONInstAlias<"vclt${p}.f32 $Qd, $Qn, $Qm",
+                    (VCGTfq QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p)>;

Modified: llvm/trunk/test/MC/ARM/neon-cmp-encoding.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/neon-cmp-encoding.s?rev=146039&r1=146038&r2=146039&view=diff
==============================================================================
--- llvm/trunk/test/MC/ARM/neon-cmp-encoding.s (original)
+++ llvm/trunk/test/MC/ARM/neon-cmp-encoding.s Wed Dec  7 11:51:15 2011
@@ -111,3 +111,36 @@
 @ CHECK: vcle.s8	d16, d16, #0    @ encoding: [0xa0,0x01,0xf1,0xf3]
 @ CHECK: vcgt.s8	d16, d16, #0    @ encoding: [0x20,0x00,0xf1,0xf3]
 @ CHECK: vclt.s8	d16, d16, #0    @ encoding: [0x20,0x02,0xf1,0xf3]
+
+
+        vclt.s8 q12, q13, q3
+        vclt.s16 q12, q13, q3
+        vclt.s32 q12, q13, q3
+        vclt.u8 q12, q13, q3
+        vclt.u16 q12, q13, q3
+        vclt.u32 q12, q13, q3
+        vclt.f32 q12, q13, q3
+
+        vclt.s8 d12, d13, d3
+        vclt.s16 d12, d13, d3
+        vclt.s32 d12, d13, d3
+        vclt.u8 d12, d13, d3
+        vclt.u16 d12, d13, d3
+        vclt.u32 d12, d13, d3
+        vclt.f32 d12, d13, d3
+
+@ CHECK: vcgt.s8	q12, q3, q13    @ encoding: [0x6a,0x83,0x46,0xf2]
+@ CHECK: vcgt.s16	q12, q3, q13    @ encoding: [0x6a,0x83,0x56,0xf2]
+@ CHECK: vcgt.s32	q12, q3, q13    @ encoding: [0x6a,0x83,0x66,0xf2]
+@ CHECK: vcgt.u8	q12, q3, q13    @ encoding: [0x6a,0x83,0x46,0xf3]
+@ CHECK: vcgt.u16	q12, q3, q13    @ encoding: [0x6a,0x83,0x56,0xf3]
+@ CHECK: vcgt.u32	q12, q3, q13    @ encoding: [0x6a,0x83,0x66,0xf3]
+@ CHECK: vcgt.f32	q12, q3, q13    @ encoding: [0x6a,0x8e,0x66,0xf3]
+
+@ CHECK: vcgt.s8	d12, d3, d13    @ encoding: [0x0d,0xc3,0x03,0xf2]
+@ CHECK: vcgt.s16	d12, d3, d13    @ encoding: [0x0d,0xc3,0x13,0xf2]
+@ CHECK: vcgt.s32	d12, d3, d13    @ encoding: [0x0d,0xc3,0x23,0xf2]
+@ CHECK: vcgt.u8	d12, d3, d13    @ encoding: [0x0d,0xc3,0x03,0xf3]
+@ CHECK: vcgt.u16	d12, d3, d13    @ encoding: [0x0d,0xc3,0x13,0xf3]
+@ CHECK: vcgt.u32	d12, d3, d13    @ encoding: [0x0d,0xc3,0x23,0xf3]
+@ CHECK: vcgt.f32	d12, d3, d13    @ encoding: [0x0d,0xce,0x23,0xf3]



From isanbard at gmail.com  Wed Dec  7 11:58:43 2011
From: isanbard at gmail.com (Bill Wendling)
Date: Wed, 07 Dec 2011 17:58:43 -0000
Subject: [llvm-commits] [www-releases] r146040 - in /www-releases/trunk/3.0:
 clang+llvm-3.0-i386-linux-Ubuntu-11_10.tar.gz
 clang+llvm-3.0-i386-linux-Ubuntu-11_10.tar.gz.sig
Message-ID: <20111207175843.D59DD2A6C12C@llvm.org>

Author: void
Date: Wed Dec  7 11:58:43 2011
New Revision: 146040

URL: http://llvm.org/viewvc/llvm-project?rev=146040&view=rev
Log:
Update so that these are truely i386 binaries.

Modified:
    www-releases/trunk/3.0/clang+llvm-3.0-i386-linux-Ubuntu-11_10.tar.gz
    www-releases/trunk/3.0/clang+llvm-3.0-i386-linux-Ubuntu-11_10.tar.gz.sig

Modified: www-releases/trunk/3.0/clang+llvm-3.0-i386-linux-Ubuntu-11_10.tar.gz
URL: http://llvm.org/viewvc/llvm-project/www-releases/trunk/3.0/clang%2Bllvm-3.0-i386-linux-Ubuntu-11_10.tar.gz?rev=146040&r1=146039&r2=146040&view=diff
==============================================================================
Binary files - no diff available.

Modified: www-releases/trunk/3.0/clang+llvm-3.0-i386-linux-Ubuntu-11_10.tar.gz.sig
URL: http://llvm.org/viewvc/llvm-project/www-releases/trunk/3.0/clang%2Bllvm-3.0-i386-linux-Ubuntu-11_10.tar.gz.sig?rev=146040&r1=146039&r2=146040&view=diff
==============================================================================
Binary files - no diff available.



From isanbard at gmail.com  Wed Dec  7 12:02:44 2011
From: isanbard at gmail.com (Bill Wendling)
Date: Wed, 07 Dec 2011 18:02:44 -0000
Subject: [llvm-commits] [llvm] r146041 -
	/llvm/trunk/docs/WritingAnLLVMPass.html
Message-ID: <20111207180244.DD9062A6C12C@llvm.org>

Author: void
Date: Wed Dec  7 12:02:44 2011
New Revision: 146041

URL: http://llvm.org/viewvc/llvm-project?rev=146041&view=rev
Log:
Correct initializer in example.

Modified:
    llvm/trunk/docs/WritingAnLLVMPass.html

Modified: llvm/trunk/docs/WritingAnLLVMPass.html
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/WritingAnLLVMPass.html?rev=146041&r1=146040&r2=146041&view=diff
==============================================================================
--- llvm/trunk/docs/WritingAnLLVMPass.html (original)
+++ llvm/trunk/docs/WritingAnLLVMPass.html Wed Dec  7 12:02:44 2011
@@ -284,7 +284,7 @@
 
      
 
           static char ID;
-    Hello() : FunctionPass(ID) {}
+    Hello() : FunctionPass(&ID) {}
 
      
 
      
 



From grosbach at apple.com  Wed Dec  7 12:04:19 2011
From: grosbach at apple.com (Jim Grosbach)
Date: Wed, 07 Dec 2011 18:04:19 -0000
Subject: [llvm-commits] [llvm] r146042 - in /llvm/trunk:
 lib/Target/ARM/AsmParser/ARMAsmParser.cpp test/MC/ARM/mode-switch.s
Message-ID: <20111207180419.CC1AF2A6C12C@llvm.org>

Author: grosbach
Date: Wed Dec  7 12:04:19 2011
New Revision: 146042

URL: http://llvm.org/viewvc/llvm-project?rev=146042&view=rev
Log:
ARM support the .arm and .thumb directives for assembly mode switching.

Modified:
    llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
    llvm/trunk/test/MC/ARM/mode-switch.s

Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp?rev=146042&r1=146041&r2=146042&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp (original)
+++ llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Wed Dec  7 12:04:19 2011
@@ -92,6 +92,7 @@
                               unsigned &ShiftAmount);
   bool parseDirectiveWord(unsigned Size, SMLoc L);
   bool parseDirectiveThumb(SMLoc L);
+  bool parseDirectiveARM(SMLoc L);
   bool parseDirectiveThumbFunc(SMLoc L);
   bool parseDirectiveCode(SMLoc L);
   bool parseDirectiveSyntax(SMLoc L);
@@ -5622,6 +5623,8 @@
     return parseDirectiveWord(4, DirectiveID.getLoc());
   else if (IDVal == ".thumb")
     return parseDirectiveThumb(DirectiveID.getLoc());
+  else if (IDVal == ".arm")
+    return parseDirectiveARM(DirectiveID.getLoc());
   else if (IDVal == ".thumb_func")
     return parseDirectiveThumbFunc(DirectiveID.getLoc());
   else if (IDVal == ".code")
@@ -5663,9 +5666,22 @@
     return Error(L, "unexpected token in directive");
   Parser.Lex();
 
-  // TODO: set thumb mode
-  // TODO: tell the MC streamer the mode
-  // getParser().getStreamer().Emit???();
+  if (!isThumb())
+    SwitchMode();
+  getParser().getStreamer().EmitAssemblerFlag(MCAF_Code16);
+  return false;
+}
+
+/// parseDirectiveARM
+///  ::= .arm
+bool ARMAsmParser::parseDirectiveARM(SMLoc L) {
+  if (getLexer().isNot(AsmToken::EndOfStatement))
+    return Error(L, "unexpected token in directive");
+  Parser.Lex();
+
+  if (isThumb())
+    SwitchMode();
+  getParser().getStreamer().EmitAssemblerFlag(MCAF_Code32);
   return false;
 }
 

Modified: llvm/trunk/test/MC/ARM/mode-switch.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/mode-switch.s?rev=146042&r1=146041&r2=146042&view=diff
==============================================================================
--- llvm/trunk/test/MC/ARM/mode-switch.s (original)
+++ llvm/trunk/test/MC/ARM/mode-switch.s Wed Dec  7 12:04:19 2011
@@ -13,3 +13,14 @@
 .code 16
         adds    r0, r0, r1
 @ CHECK: adds	r0, r0, r1              @ encoding: [0x40,0x18]
+
+.arm
+	add	r0, r0, r1
+@ CHECK: add	r0, r0, r1              @ encoding: [0x01,0x00,0x80,0xe0]
+
+.thumb
+	add.w	r0, r0, r1
+        adds    r0, r0, r1
+
+@ CHECK: add.w	r0, r0, r1              @ encoding: [0x00,0xeb,0x01,0x00]
+@ CHECK: adds	r0, r0, r1              @ encoding: [0x40,0x18]



From criswell at uiuc.edu  Wed Dec  7 12:13:19 2011
From: criswell at uiuc.edu (John Criswell)
Date: Wed, 07 Dec 2011 18:13:19 -0000
Subject: [llvm-commits] [www-pubs] r146043 - /www-pubs/trunk/index.html
Message-ID: <20111207181319.5B7622A6C12C@llvm.org>

Author: criswell
Date: Wed Dec  7 12:13:19 2011
New Revision: 146043

URL: http://llvm.org/viewvc/llvm-project?rev=146043&view=rev
Log:
Have publications sent to llvmdev.

Modified:
    www-pubs/trunk/index.html

Modified: www-pubs/trunk/index.html
URL: http://llvm.org/viewvc/llvm-project/www-pubs/trunk/index.html?rev=146043&r1=146042&r2=146043&view=diff
==============================================================================
--- www-pubs/trunk/index.html (original)
+++ www-pubs/trunk/index.html Wed Dec  7 12:13:19 2011
@@ -3,7 +3,9 @@
 
 
      Here are some of the publications that use or build on LLVM.  This list 
    generally lags behind publication; if you have a paper for this list,
-   please email Chris or commit it 
+   please email the 
+   LLVM Developer's mailing list with a Subject: line that begins with the
+   word "Publication" or commit it 
    directly to the llvm-pubs SVN module if you have llvm.org commit access.
      
 
 



From isanbard at gmail.com  Wed Dec  7 12:18:11 2011
From: isanbard at gmail.com (Bill Wendling)
Date: Wed, 07 Dec 2011 18:18:11 -0000
Subject: [llvm-commits] [llvm] r146044 -
	/llvm/trunk/docs/WritingAnLLVMPass.html
Message-ID: <20111207181811.E76C52A6C12C@llvm.org>

Author: void
Date: Wed Dec  7 12:18:11 2011
New Revision: 146044

URL: http://llvm.org/viewvc/llvm-project?rev=146044&view=rev
Log:
Also pass in correct initializer here.

Modified:
    llvm/trunk/docs/WritingAnLLVMPass.html

Modified: llvm/trunk/docs/WritingAnLLVMPass.html
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/WritingAnLLVMPass.html?rev=146044&r1=146043&r2=146044&view=diff
==============================================================================
--- llvm/trunk/docs/WritingAnLLVMPass.html (original)
+++ llvm/trunk/docs/WritingAnLLVMPass.html Wed Dec  7 12:18:11 2011
@@ -347,7 +347,7 @@
   struct Hello : public FunctionPass {
     
     static char ID;
-    Hello() : FunctionPass(ID) {}
+    Hello() : FunctionPass(&ID) {}
 
     virtual bool runOnFunction(Function &F) {
       errs() << "Hello: ";



From daniel.malea at intel.com  Wed Dec  7 11:59:22 2011
From: daniel.malea at intel.com (Malea, Daniel)
Date: Wed, 7 Dec 2011 10:59:22 -0700
Subject: [llvm-commits] Add support for JIT profiling tool (Intel Parallel
 Amplifier XE 2011)
Message-ID: <2C2ECF4B05BCF3489866AB805260FEC50630A32BD2@rrsmsx509.amr.corp.intel.com>

Hi all,

Please find the attached patches ready for review which add JIT profiling support for Intel Parallel Amplifier XE 2011 (through the JITEventListener interface) and also fix oprofile support in the CMake build system. The meat (implementation and tests) is in the first patch, and the subsequent patches are the build system changes.

Add Intel JIT Events API compatible JITEventListener, and allow OProfileJITEventListener to load libopagent.so at runtime

-        Removed link-time requirement on libopagent when building with OProfile support

-        Added Intel JIT API and OProfile support to cmake builds (Boolean options LLVM_USE_OPROFILE and LLVM_USE_INTEL_JITEVENTS)

-        Added IntelJITEventListener to connect to Intel JIT API (support for profiling with Parallel Amplifier XE 2011)

-        Added unit tests for both IntelJIT and OProfile JITEventListener implementations which can still be run in the absence the respective 3rd party libraries

Thanks
-------------- next part --------------
An HTML attachment was scrubbed...
URL: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20111207/36d50e78/attachment-0001.html 
-------------- next part --------------
A non-text attachment was scrubbed...
Name: 0001-intel_jitevents_impl_and_tests.patch
Type: application/octet-stream
Size: 48624 bytes
Desc: 0001-intel_jitevents_impl_and_tests.patch
Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20111207/36d50e78/attachment-0004.obj 
-------------- next part --------------
A non-text attachment was scrubbed...
Name: 0002-intel_jitevents_cmake.patch
Type: application/octet-stream
Size: 4612 bytes
Desc: 0002-intel_jitevents_cmake.patch
Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20111207/36d50e78/attachment-0005.obj 
-------------- next part --------------
A non-text attachment was scrubbed...
Name: 0003-intel_jitevents_automake.patch
Type: application/octet-stream
Size: 4187 bytes
Desc: 0003-intel_jitevents_automake.patch
Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20111207/36d50e78/attachment-0006.obj 
-------------- next part --------------
A non-text attachment was scrubbed...
Name: 0004-intel_jitevents_autogenerated.patch
Type: application/octet-stream
Size: 12826 bytes
Desc: 0004-intel_jitevents_autogenerated.patch
Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20111207/36d50e78/attachment-0007.obj 

From grosbach at apple.com  Wed Dec  7 12:32:28 2011
From: grosbach at apple.com (Jim Grosbach)
Date: Wed, 07 Dec 2011 18:32:28 -0000
Subject: [llvm-commits] [llvm] r146046 - in /llvm/trunk:
 lib/Target/ARM/ARMInstrThumb2.td test/MC/ARM/basic-thumb2-instructions.s
Message-ID: <20111207183228.D8BCD2A6C12C@llvm.org>

Author: grosbach
Date: Wed Dec  7 12:32:28 2011
New Revision: 146046

URL: http://llvm.org/viewvc/llvm-project?rev=146046&view=rev
Log:
Thumb2 alias for long-form pop and friends.
rdar://10542474

Modified:
    llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td
    llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s

Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td?rev=146046&r1=146045&r2=146046&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td Wed Dec  7 12:32:28 2011
@@ -3971,6 +3971,18 @@
 def : t2InstAlias<"pop${p}.w $regs", (t2LDMIA_UPD SP, pred:$p, reglist:$regs)>;
 def : t2InstAlias<"pop${p} $regs", (t2LDMIA_UPD SP, pred:$p, reglist:$regs)>;
 
+// STMIA/STMIA_UPD aliases w/o the optional .w suffix
+def : t2InstAlias<"stm${p} $Rn, $regs",
+                  (t2STMIA GPR:$Rn, pred:$p, reglist:$regs)>;
+def : t2InstAlias<"stm${p} $Rn!, $regs",
+                  (t2STMIA_UPD GPR:$Rn, pred:$p, reglist:$regs)>;
+
+// LDMIA/LDMIA_UPD aliases w/o the optional .w suffix
+def : t2InstAlias<"ldm${p} $Rn, $regs",
+                  (t2LDMIA GPR:$Rn, pred:$p, reglist:$regs)>;
+def : t2InstAlias<"ldm${p} $Rn!, $regs",
+                  (t2LDMIA_UPD GPR:$Rn, pred:$p, reglist:$regs)>;
+
 // STMDB/STMDB_UPD aliases w/ the optional .w suffix
 def : t2InstAlias<"stmdb${p}.w $Rn, $regs",
                   (t2STMDB GPR:$Rn, pred:$p, reglist:$regs)>;

Modified: llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s?rev=146046&r1=146045&r2=146046&view=diff
==============================================================================
--- llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s (original)
+++ llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s Wed Dec  7 12:32:28 2011
@@ -581,6 +581,7 @@
         ldm r4, {r5, r6}
         ldm r5!, {r3, r8}
         ldmfd r5!, {r3, r8}
+        ldmia sp!, {r4-r11, pc}
 
 @ CHECK: ldm.w	r4, {r4, r5, r8, r9}    @ encoding: [0x94,0xe8,0x30,0x03]
 @ CHECK: ldm.w	r4, {r5, r6}            @ encoding: [0x94,0xe8,0x60,0x00]
@@ -598,6 +599,7 @@
 @ CHECK: ldm.w	r4, {r5, r6}            @ encoding: [0x94,0xe8,0x60,0x00]
 @ CHECK: ldm.w	r5!, {r3, r8}           @ encoding: [0xb5,0xe8,0x08,0x01]
 @ CHECK: ldm.w	r5!, {r3, r8}           @ encoding: [0xb5,0xe8,0x08,0x01]
+@ CHECK: pop.w	{pc, r4, r5, r6, r7, r8, r9, r10, r11} @ encoding: [0xbd,0xe8,0xf0,0x8f]
 
 
 @------------------------------------------------------------------------------



From daniel at zuster.org  Wed Dec  7 12:43:12 2011
From: daniel at zuster.org (Daniel Dunbar)
Date: Wed, 07 Dec 2011 18:43:12 -0000
Subject: [llvm-commits] [compiler-rt] r146047 -
	/compiler-rt/trunk/www/index.html
Message-ID: <20111207184312.CBFC82A6C12C@llvm.org>

Author: ddunbar
Date: Wed Dec  7 12:43:12 2011
New Revision: 146047

URL: http://llvm.org/viewvc/llvm-project?rev=146047&view=rev
Log:
www: Add some more notes to compiler-rt web page.

Modified:
    compiler-rt/trunk/www/index.html

Modified: compiler-rt/trunk/www/index.html
URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/www/index.html?rev=146047&r1=146046&r2=146047&view=diff
==============================================================================
--- compiler-rt/trunk/www/index.html (original)
+++ compiler-rt/trunk/www/index.html Wed Dec  7 12:43:12 2011
@@ -26,6 +26,22 @@
   
      All of the code in the compiler-rt project is dual licensed
      under the MIT license and the UIUC License (a BSD-like license).
      
+
+  
+  
      Clients
      
+  
+
+  
      Currently compiler-rt is primarily used by
+    the Clang
+    and LLVM projects as the implementation for
+    the runtime compiler support libraries. The library currently provides both
+    the low-level target-specific hooks required by code generation, as well as
+    additional modules for supporting the runtime requirements of features like
+    code coverage, profiling, or address sanitizer (ASAN) instrumentation.
      
+
+  
      For more information on using compiler-rt with Clang, please see the Clang
+    Getting Started
+    page.
      
   
   
   
      Goals
      



From daniel.malea at intel.com  Wed Dec  7 13:12:56 2011
From: daniel.malea at intel.com (Malea, Daniel)
Date: Wed, 7 Dec 2011 12:12:56 -0700
Subject: [llvm-commits] Add basic ELF Dyld loader (on behalf of Andy Kaylor)
Message-ID: <2C2ECF4B05BCF3489866AB805260FEC50630A32C8A@rrsmsx509.amr.corp.intel.com>

Hi all,

Please find the attached patch for review. It is the first step toward enabling lli -use-mcjit to work with ELF objects.

Basic ELF loader in MCJIT (on behalf of Andy Kaylor):

-        Supports loading ELF object files emitted by MC

-        Adds minimal x86 relocation support (function calls)

Thanks,
Dan
-------------- next part --------------
An HTML attachment was scrubbed...
URL: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20111207/f7f2c349/attachment.html 
-------------- next part --------------
A non-text attachment was scrubbed...
Name: 0001-basic-runtimedyld-elf-loader.patch
Type: application/octet-stream
Size: 14906 bytes
Desc: 0001-basic-runtimedyld-elf-loader.patch
Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20111207/f7f2c349/attachment.obj 

From criswell at uiuc.edu  Wed Dec  7 13:37:39 2011
From: criswell at uiuc.edu (John Criswell)
Date: Wed, 07 Dec 2011 19:37:39 -0000
Subject: [llvm-commits] [www-pubs] r146052 - /www-pubs/trunk/pubs.js
Message-ID: <20111207193740.070032A6C12C@llvm.org>

Author: criswell
Date: Wed Dec  7 13:37:39 2011
New Revision: 146052

URL: http://llvm.org/viewvc/llvm-project?rev=146052&view=rev
Log:
Added publications submitted by Mariusz Grad.

Modified:
    www-pubs/trunk/pubs.js

Modified: www-pubs/trunk/pubs.js
URL: http://llvm.org/viewvc/llvm-project/www-pubs/trunk/pubs.js?rev=146052&r1=146051&r2=146052&view=diff
==============================================================================
--- www-pubs/trunk/pubs.js (original)
+++ www-pubs/trunk/pubs.js Wed Dec  7 13:37:39 2011
@@ -1,7 +1,16 @@
 // The array should be sorted reverse-chronologically, and will be displayed on
 // the page in the order listed.
 var PUBS =
-[{ url: "2011-02-FOSDEM-LLVMAndClang.html",
+[ { url: "http://homepages.uni-paderborn.de/mgrad/Mariusz_Grad_Homepage/Publications_files/grad11_raw_paper.pdf",
+    author: "Mariusz Grad and Christian Plessl",
+    title: "Just-in-time Instruction Set Extension - Feasibility and Limitations for an FPGA-based Reconfigurable ASIP Architecture",
+    published: "Reconfigurable Architectures Workshop (RAW 2011), Proceedings of the International Parallel and Distributed Processing Symposium",
+    location: "Anchorage, Alaska, USA.",
+    month:  5,
+    year: 2011
+  },
+
+ { url: "2011-02-FOSDEM-LLVMAndClang.html",
    title: "LLVM and Clang: Advancing Compiler Technology",
    published: "Keynote Talk, FOSDEM 2011: Free and Open Source Developers European Meeting",
    location: "Brussels, Belgium",
@@ -9,7 +18,16 @@
    month: 2,
    year: 2011
  },
- 
+
+  { url: "http://homepages.uni-paderborn.de/mgrad/Mariusz_Grad_Homepage/Publications_files/grad10_reconfig_paper.pdf",
+    author: "Mariusz Grad and Christian Plessl",
+    title: "Pruning the Design Space for Just-in-time Processor Customization",
+    published: "Proceedings of the International Conference on Reconfigurable Computing (ReConFig 2010)",
+    location: "Cancun, Mexico",
+    month: 12,
+    year: 2010.
+  },
+
  { url: "2010-12-Preuss-PathProfiling.html",
  title: "Implementation of Path Profiling in the Low-Level Virtual-Machine (LLVM) Compiler Infrastructure",
 published: "Technical Report #10-05, University of Alberta",
@@ -365,6 +383,15 @@
    month: 8,
    year: 2009},
 
+  { url: "http://homepages.uni-paderborn.de/mgrad/Mariusz_Grad_Homepage/Publications_files/grad09_ersa_paper.pdf",
+    author: "Mariusz Grad and Christian Plessl",
+    title: "Woolcano: An Architecture and Tool Flow for Dynamic Instruction Set Extension on Xilinx Virtex-4 FX",
+    published: "Proceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA 2009)",
+    location: "Las Vegas, Nevada, USA",
+    month: 7,
+    year: 2009
+  },
+
   {url: '2009-07-ISSTA-BegBunch.html',
    title: 'BegBunch: benchmarking for C bug detection tools',
    author: 'Cristina Cifuentes, Christian Hoermann, Nathan Keynes, Lian Li, Simon Long, Erica Mealy, Michael Mounteney, and Bernhard Scholz',
@@ -491,6 +518,15 @@
    month: 5,
    year: 2009},
 
+  { url: "http://homepages.uni-paderborn.de/mgrad/Mariusz_Grad_Homepage/Publications_files/grad09_fccm_poster.pdf",
+    author: "Mariusz Grad and Christian Plessl",
+    title: "Woolcano: An Architecture and Tool Flow for Dynamic Instruction Set Extension on Xilinx Virtex-4 FX",
+    published: "Proceedings of IEEE Symposium on Field-Programmable Custom Machines (FCCM 2009)",
+    location: "Napa, CA, USA",
+    month: 4,
+    year: 2009
+  },
+
   {url: '2009-04-TECS-MEMMU.html',
    title: 'MEMMU: Memory expansion for MMU-less embedded systems',
    author: 'Lan S. Bai, Lei Yang, and Robert P. Dick',



From kubastaszak at gmail.com  Wed Dec  7 13:46:10 2011
From: kubastaszak at gmail.com (Jakub Staszak)
Date: Wed, 07 Dec 2011 19:46:10 -0000
Subject: [llvm-commits] [llvm] r146053 -
	/llvm/trunk/lib/CodeGen/MachineBlockPlacement.cpp
Message-ID: <20111207194610.4DD172A6C12C@llvm.org>

Author: kuba
Date: Wed Dec  7 13:46:10 2011
New Revision: 146053

URL: http://llvm.org/viewvc/llvm-project?rev=146053&view=rev
Log:
Remove unneeded semicolon.
Skip two looking up at BlockChain.

Modified:
    llvm/trunk/lib/CodeGen/MachineBlockPlacement.cpp

Modified: llvm/trunk/lib/CodeGen/MachineBlockPlacement.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineBlockPlacement.cpp?rev=146053&r1=146052&r2=146053&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/MachineBlockPlacement.cpp (original)
+++ llvm/trunk/lib/CodeGen/MachineBlockPlacement.cpp Wed Dec  7 13:46:10 2011
@@ -530,7 +530,7 @@
     markChainSuccessors(SuccChain, LoopHeaderBB, BlockWorkList, BlockFilter);
     Chain.merge(BestSucc, &SuccChain);
     BB = *llvm::prior(Chain.end());
-  };
+  }
 
   DEBUG(dbgs() << "Finished forming chain for header block "
                << getBlockNum(*Chain.begin()) << "\n");
@@ -681,8 +681,8 @@
   // walk the blocks, and use a set to prevent visiting a particular chain
   // twice.
   SmallPtrSet UpdatedPreds;
-  assert(BlockToChain[LayoutTop]->LoopPredecessors == 0);
-  UpdatedPreds.insert(BlockToChain[LayoutTop]);
+  assert(LoopChain.LoopPredecessors == 0);
+  UpdatedPreds.insert(&LoopChain);
   for (MachineLoop::block_iterator BI = L.block_begin(),
                                    BE = L.block_end();
        BI != BE; ++BI) {



From grosbach at apple.com  Wed Dec  7 13:46:59 2011
From: grosbach at apple.com (Jim Grosbach)
Date: Wed, 07 Dec 2011 19:46:59 -0000
Subject: [llvm-commits] [llvm] r146054 - in /llvm/trunk:
 lib/MC/MachObjectWriter.cpp
 lib/Target/ARM/MCTargetDesc/ARMMachObjectWriter.cpp
 test/MC/MachO/ARM/darwin-ARM-reloc.s test/MC/MachO/reloc-pcrel-offset.s
 test/MC/MachO/reloc-pcrel.s
Message-ID: <20111207194659.DEF222A6C12C@llvm.org>

Author: grosbach
Date: Wed Dec  7 13:46:59 2011
New Revision: 146054

URL: http://llvm.org/viewvc/llvm-project?rev=146054&view=rev
Log:
Darwin assembler improved relocs when w/o subsections_via_symbols.

When the file isn't being built with subsections-via-symbols, symbol
differences involving non-local symbols can be resolved more aggressively.
Needed for gas compatibility.


Modified:
    llvm/trunk/lib/MC/MachObjectWriter.cpp
    llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMachObjectWriter.cpp
    llvm/trunk/test/MC/MachO/ARM/darwin-ARM-reloc.s
    llvm/trunk/test/MC/MachO/reloc-pcrel-offset.s
    llvm/trunk/test/MC/MachO/reloc-pcrel.s

Modified: llvm/trunk/lib/MC/MachObjectWriter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MachObjectWriter.cpp?rev=146054&r1=146053&r2=146054&view=diff
==============================================================================
--- llvm/trunk/lib/MC/MachObjectWriter.cpp (original)
+++ llvm/trunk/lib/MC/MachObjectWriter.cpp Wed Dec  7 13:46:59 2011
@@ -584,9 +584,14 @@
     // requires the compiler to use .set to absolutize the differences between
     // symbols which the compiler knows to be assembly time constants, so we
     // don't need to worry about considering symbol differences fully resolved.
+    //
+    // If the file isn't using sub-sections-via-symbols, we can make the
+    // same assumptions about any symbol that we normally make about
+    // assembler locals.
 
     if (!Asm.getBackend().hasReliableSymbolDifference()) {
-      if (!SA.isTemporary() || !SA.isInSection() || &SecA != &SecB)
+      if ((!SA.isTemporary() && Asm.getSubsectionsViaSymbols()) ||
+           !SA.isInSection() || &SecA != &SecB)
         return false;
       return true;
     }

Modified: llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMachObjectWriter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMachObjectWriter.cpp?rev=146054&r1=146053&r2=146054&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMachObjectWriter.cpp (original)
+++ llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMachObjectWriter.cpp Wed Dec  7 13:46:59 2011
@@ -62,6 +62,9 @@
   default:
     return false;
 
+  case ARM::fixup_t2_condbranch:
+    assert(0);
+    return false;
   case FK_Data_1:
     Log2Size = llvm::Log2_32(1);
     return true;

Modified: llvm/trunk/test/MC/MachO/ARM/darwin-ARM-reloc.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/MachO/ARM/darwin-ARM-reloc.s?rev=146054&r1=146053&r2=146054&view=diff
==============================================================================
--- llvm/trunk/test/MC/MachO/ARM/darwin-ARM-reloc.s (original)
+++ llvm/trunk/test/MC/MachO/ARM/darwin-ARM-reloc.s Wed Dec  7 13:46:59 2011
@@ -19,12 +19,14 @@
 Lsc0_0:
         .long 0
 
+        .subsections_via_symbols
+
 @ CHECK: ('cputype', 12)
 @ CHECK: ('cpusubtype', 9)
 @ CHECK: ('filetype', 1)
 @ CHECK: ('num_load_commands', 3)
 @ CHECK: ('load_commands_size', 364)
-@ CHECK: ('flag', 0)
+@ CHECK: ('flag', 8192)
 @ CHECK: ('load_commands', [
 @ CHECK:   # Load Command 0
 @ CHECK:  (('command', 1)

Modified: llvm/trunk/test/MC/MachO/reloc-pcrel-offset.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/MachO/reloc-pcrel-offset.s?rev=146054&r1=146053&r2=146054&view=diff
==============================================================================
--- llvm/trunk/test/MC/MachO/reloc-pcrel-offset.s (original)
+++ llvm/trunk/test/MC/MachO/reloc-pcrel-offset.s Wed Dec  7 13:46:59 2011
@@ -12,3 +12,5 @@
         .text
 _a:
         call _a
+
+        .subsections_via_symbols

Modified: llvm/trunk/test/MC/MachO/reloc-pcrel.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/MachO/reloc-pcrel.s?rev=146054&r1=146053&r2=146054&view=diff
==============================================================================
--- llvm/trunk/test/MC/MachO/reloc-pcrel.s (original)
+++ llvm/trunk/test/MC/MachO/reloc-pcrel.s Wed Dec  7 13:46:59 2011
@@ -60,3 +60,5 @@
         call _c + 1
 //        call _a - L0
         call _b - L0
+
+        .subsections_via_symbols



From eli.friedman at gmail.com  Wed Dec  7 13:54:03 2011
From: eli.friedman at gmail.com (Eli Friedman)
Date: Wed, 7 Dec 2011 11:54:03 -0800
Subject: [llvm-commits] [llvm] r146054 - in /llvm/trunk:
 lib/MC/MachObjectWriter.cpp
 lib/Target/ARM/MCTargetDesc/ARMMachObjectWriter.cpp
 test/MC/MachO/ARM/darwin-ARM-reloc.s test/MC/MachO/reloc-pcrel-offset.s
 test/MC/MachO/reloc-pcrel.s
In-Reply-To: <20111207194659.DEF222A6C12C@llvm.org>
References: <20111207194659.DEF222A6C12C@llvm.org>
Message-ID: 

On Wed, Dec 7, 2011 at 11:46 AM, Jim Grosbach  wrote:
> Author: grosbach
> Date: Wed Dec ?7 13:46:59 2011
> New Revision: 146054
>
> URL: http://llvm.org/viewvc/llvm-project?rev=146054&view=rev
> Log:
> Darwin assembler improved relocs when w/o subsections_via_symbols.
>
> When the file isn't being built with subsections-via-symbols, symbol
> differences involving non-local symbols can be resolved more aggressively.
> Needed for gas compatibility.
>
>
> Modified:
> ? ?llvm/trunk/lib/MC/MachObjectWriter.cpp
> ? ?llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMachObjectWriter.cpp
> ? ?llvm/trunk/test/MC/MachO/ARM/darwin-ARM-reloc.s
> ? ?llvm/trunk/test/MC/MachO/reloc-pcrel-offset.s
> ? ?llvm/trunk/test/MC/MachO/reloc-pcrel.s
>
> Modified: llvm/trunk/lib/MC/MachObjectWriter.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MachObjectWriter.cpp?rev=146054&r1=146053&r2=146054&view=diff
> ==============================================================================
> --- llvm/trunk/lib/MC/MachObjectWriter.cpp (original)
> +++ llvm/trunk/lib/MC/MachObjectWriter.cpp Wed Dec ?7 13:46:59 2011
> @@ -584,9 +584,14 @@
> ? ? // requires the compiler to use .set to absolutize the differences between
> ? ? // symbols which the compiler knows to be assembly time constants, so we
> ? ? // don't need to worry about considering symbol differences fully resolved.
> + ? ?//
> + ? ?// If the file isn't using sub-sections-via-symbols, we can make the
> + ? ?// same assumptions about any symbol that we normally make about
> + ? ?// assembler locals.
>
> ? ? if (!Asm.getBackend().hasReliableSymbolDifference()) {
> - ? ? ?if (!SA.isTemporary() || !SA.isInSection() || &SecA != &SecB)
> + ? ? ?if ((!SA.isTemporary() && Asm.getSubsectionsViaSymbols()) ||
> + ? ? ? ? ? !SA.isInSection() || &SecA != &SecB)
> ? ? ? ? return false;
> ? ? ? return true;
> ? ? }
>
> Modified: llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMachObjectWriter.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMachObjectWriter.cpp?rev=146054&r1=146053&r2=146054&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMachObjectWriter.cpp (original)
> +++ llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMachObjectWriter.cpp Wed Dec ?7 13:46:59 2011
> @@ -62,6 +62,9 @@
> ? default:
> ? ? return false;
>
> + ?case ARM::fixup_t2_condbranch:
> + ? ?assert(0);
> + ? ?return false;

Did you intend to commit this bit?

-Eli


From criswell at uiuc.edu  Wed Dec  7 13:52:17 2011
From: criswell at uiuc.edu (John Criswell)
Date: Wed, 07 Dec 2011 19:52:17 -0000
Subject: [llvm-commits] [www-pubs] r146055 - /www-pubs/trunk/pubs.js
Message-ID: <20111207195217.7284C2A6C12C@llvm.org>

Author: criswell
Date: Wed Dec  7 13:52:17 2011
New Revision: 146055

URL: http://llvm.org/viewvc/llvm-project?rev=146055&view=rev
Log:
Added code to add a space between entries.  This makes the list easier to read.

Modified:
    www-pubs/trunk/pubs.js

Modified: www-pubs/trunk/pubs.js
URL: http://llvm.org/viewvc/llvm-project/www-pubs/trunk/pubs.js?rev=146055&r1=146054&r2=146055&view=diff
==============================================================================
--- www-pubs/trunk/pubs.js (original)
+++ www-pubs/trunk/pubs.js Wed Dec  7 13:52:17 2011
@@ -1396,6 +1396,7 @@
     if (isDef(pub.award)) {
       item.innerHTML += '
      ' + pub.award + '.';
     }
+    item.innerHTML += '

      ';
     list.appendChild(item);
   }
 }



From grosbach at apple.com  Wed Dec  7 13:58:34 2011
From: grosbach at apple.com (Jim Grosbach)
Date: Wed, 07 Dec 2011 11:58:34 -0800
Subject: [llvm-commits] [llvm] r146054 - in /llvm/trunk:
 lib/MC/MachObjectWriter.cpp
 lib/Target/ARM/MCTargetDesc/ARMMachObjectWriter.cpp
 test/MC/MachO/ARM/darwin-ARM-reloc.s test/MC/MachO/reloc-pcrel-offset.s
 test/MC/MachO/reloc-pcrel.s
In-Reply-To: 
References: <20111207194659.DEF222A6C12C@llvm.org>
	
Message-ID: <5CD1F297-628A-4065-8951-A6AD8CFA961F@apple.com>


On Dec 7, 2011, at 11:54 AM, Eli Friedman wrote:

> On Wed, Dec 7, 2011 at 11:46 AM, Jim Grosbach  wrote:
>> Author: grosbach
>> Date: Wed Dec  7 13:46:59 2011
>> New Revision: 146054
>> 
>> URL: http://llvm.org/viewvc/llvm-project?rev=146054&view=rev
>> Log:
>> Darwin assembler improved relocs when w/o subsections_via_symbols.
>> 
>> When the file isn't being built with subsections-via-symbols, symbol
>> differences involving non-local symbols can be resolved more aggressively.
>> Needed for gas compatibility.
>> 
>> 
>> Modified:
>>    llvm/trunk/lib/MC/MachObjectWriter.cpp
>>    llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMachObjectWriter.cpp
>>    llvm/trunk/test/MC/MachO/ARM/darwin-ARM-reloc.s
>>    llvm/trunk/test/MC/MachO/reloc-pcrel-offset.s
>>    llvm/trunk/test/MC/MachO/reloc-pcrel.s
>> 
>> Modified: llvm/trunk/lib/MC/MachObjectWriter.cpp
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MachObjectWriter.cpp?rev=146054&r1=146053&r2=146054&view=diff
>> ==============================================================================
>> --- llvm/trunk/lib/MC/MachObjectWriter.cpp (original)
>> +++ llvm/trunk/lib/MC/MachObjectWriter.cpp Wed Dec  7 13:46:59 2011
>> @@ -584,9 +584,14 @@
>>     // requires the compiler to use .set to absolutize the differences between
>>     // symbols which the compiler knows to be assembly time constants, so we
>>     // don't need to worry about considering symbol differences fully resolved.
>> +    //
>> +    // If the file isn't using sub-sections-via-symbols, we can make the
>> +    // same assumptions about any symbol that we normally make about
>> +    // assembler locals.
>> 
>>     if (!Asm.getBackend().hasReliableSymbolDifference()) {
>> -      if (!SA.isTemporary() || !SA.isInSection() || &SecA != &SecB)
>> +      if ((!SA.isTemporary() && Asm.getSubsectionsViaSymbols()) ||
>> +           !SA.isInSection() || &SecA != &SecB)
>>         return false;
>>       return true;
>>     }
>> 
>> Modified: llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMachObjectWriter.cpp
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMachObjectWriter.cpp?rev=146054&r1=146053&r2=146054&view=diff
>> ==============================================================================
>> --- llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMachObjectWriter.cpp (original)
>> +++ llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMachObjectWriter.cpp Wed Dec  7 13:46:59 2011
>> @@ -62,6 +62,9 @@
>>   default:
>>     return false;
>> 
>> +  case ARM::fixup_t2_condbranch:
>> +    assert(0);
>> +    return false;
> 
> Did you intend to commit this bit?
> 

Doh. Nope.

Thank you!

> -Eli


From grosbach at apple.com  Wed Dec  7 13:56:17 2011
From: grosbach at apple.com (Jim Grosbach)
Date: Wed, 07 Dec 2011 19:56:17 -0000
Subject: [llvm-commits] [llvm] r146057 -
 /llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMachObjectWriter.cpp
Message-ID: <20111207195617.31A622A6C12C@llvm.org>

Author: grosbach
Date: Wed Dec  7 13:56:16 2011
New Revision: 146057

URL: http://llvm.org/viewvc/llvm-project?rev=146057&view=rev
Log:
Nuke inadvertant debugging commit.

Modified:
    llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMachObjectWriter.cpp

Modified: llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMachObjectWriter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMachObjectWriter.cpp?rev=146057&r1=146056&r2=146057&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMachObjectWriter.cpp (original)
+++ llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMachObjectWriter.cpp Wed Dec  7 13:56:16 2011
@@ -62,9 +62,6 @@
   default:
     return false;
 
-  case ARM::fixup_t2_condbranch:
-    assert(0);
-    return false;
   case FK_Data_1:
     Log2Size = llvm::Log2_32(1);
     return true;



From tonic at nondot.org  Wed Dec  7 14:07:51 2011
From: tonic at nondot.org (Tanya Lattner)
Date: Wed, 07 Dec 2011 20:07:51 -0000
Subject: [llvm-commits] [www] r146058 - /www/trunk/devmtg/2011-11/index.html
Message-ID: <20111207200751.4300E2A6C12C@llvm.org>

Author: tbrethou
Date: Wed Dec  7 14:07:50 2011
New Revision: 146058

URL: http://llvm.org/viewvc/llvm-project?rev=146058&view=rev
Log:
Remove outdated information.

Modified:
    www/trunk/devmtg/2011-11/index.html

Modified: www/trunk/devmtg/2011-11/index.html
URL: http://llvm.org/viewvc/llvm-project/www/trunk/devmtg/2011-11/index.html?rev=146058&r1=146057&r2=146058&view=diff
==============================================================================
--- www/trunk/devmtg/2011-11/index.html (original)
+++ www/trunk/devmtg/2011-11/index.html Wed Dec  7 14:07:50 2011
@@ -4,14 +4,9 @@
 
      
 	
      
 
        
-        
      1. Registration
        2. 
-        
      2. Funding Assistance
        3. 
-        
      3. Location
        4. 
-        
      4. Hacking Session
        5. 
 	
      5. Agenda
        6. 
         
      6. Talk Abstracts
        7. 
         
      7. Poster Abstracts
        8. 
-        
      8. Dinner
        9. 
 
      
       		
 
        
@@ -45,48 +40,10 @@
 
        
 We also invite you to sign up for the official Developer Meeting mailing list to be kept informed of updates concerning the meeting.
 
        
-
        Registration
        
-
-
        
-Registration for the 2011 LLVM Developer Meeting is now filled, but to be added to the waitlist please register at the link below. Note you will a confirmation mail if a space frees up:
-
        
-	http:// qcsurvey.qualcomm.com/survey.asp?pub=y&survey_id=7125
-
        
-
        
-The attendance limit has been increased to 225 this year, but with the growing interest in LLVM, registration has filled up quickly.
-
        
-Please register if you are fairly certain that you will attend; but if you later find out that you are unable to attend, please mail arlenr at qualcomm.com as soon as you know so that we can let someone who is on the waitlist attend. 
-
        
-
-
-
-
        In prior years companies have come forth to sponsor speakers, students, and active contributors in need of travel assistance and likely will do so again. If you need assistance, please submit your requst here. Note, those that receive funding maybe required to present at the meeting and may have additional requirements from their sponsor (i.e. writing a blog post, etc).
 
         
 
-
        Location
        
-
        The LLVM Developers' Meeting is held at the San Jose Marriott.
        
-
-
        San Jose Marriott
         
-301 South Market Street 
        
-San Jose, CA 95113
        
-
        
-
-
        A block of rooms have been reserved for attendees of this year's Developer Meeting at a special rate of $179. Room reservations can be made at http://resweb.passkey.com/go/LLVM
        
-
-
        
-Directions From San Jose Airport
        
-Take Hwy CA-87 South (Guadalupe Parkway). Exit on Park Avenue. Turn left on Park Avenue. Turn right on Market Street. The hotel is one block ahead, on the corner of Market and San Carlos Street.
-
        
-
-
        Hacking Session
        
-
        
-There will be a hacking session the day before the Developer Meeting. This hacking session will run from 2:00 till late. Refreshments and networking provided. Bring your code and laptop. If people are flying in the night before for the Dev Meeting, or available after work, let them know and have them join us.
        
-
        
-San Jose Marriott
-Room 2500
-
        
-
 
        Agenda
        
+
 
        
 
@@ -296,18 +253,6 @@
 The poster will describe our research on the subject of verification of OpenCL kernels using symbolic execution. We present an effective technique for crosschecking a C program against an accelerated OpenCL version, as well as a technique for detecting data races in OpenCL programs. Our techniques are implemented in KLEE-CL, a symbolic execution engine based on KLEE and KLEE-FP that supports symbolic reasoning on the equivalence between symbolic values. Our approach is to symbolically model the OpenCL environment using an OpenCL runtime library targeted to symbolic execution. Using this model we are able to run OpenCL programs symbolically, keeping track of memory accesses for the purpose of race detection. We then compare the symbolic result against the plain C program in order to detect mismatches between the two versions. We applied KLEE-CL to the Parboil benchmark suite, the Bullet physics library and the OP2 library, in which we were able to find a total of seven errors
 : three mismatches between the OpenCL and C implementations, two memory errors, one OpenCL compiler bug and one race condition.
 
        
 
-
        Dinner
        
-
        Dinner attendance is capped at 140 and you must select this option during the registration process in order to attend.
        
-
        Dinner will be held after the meeting from 6:30-9:30. Dinner will be held at Il Fornaio which is across the street from the Marriott.
-
        
-
-
        
-Il Fornaio
        
-302 South Market Street
        
-(at the Sainte Claire)
        
-San Jose, CA 95113 
        
-
        
-
 
        



From ahatanaka at mips.com  Wed Dec  7 14:10:25 2011
From: ahatanaka at mips.com (Akira Hatanaka)
Date: Wed, 07 Dec 2011 20:10:25 -0000
Subject: [llvm-commits] [llvm] r146059 - in /llvm/trunk:
 lib/Target/Mips/Mips64InstrInfo.td lib/Target/Mips/MipsISelDAGToDAG.cpp
 lib/Target/Mips/MipsInstrInfo.td test/CodeGen/Mips/mips64imm.ll
Message-ID: <20111207201025.37A872A6C12C@llvm.org>

Author: ahatanak
Date: Wed Dec  7 14:10:24 2011
New Revision: 146059

URL: http://llvm.org/viewvc/llvm-project?rev=146059&view=rev
Log:
Fix 64-bit immediate patterns.

Added:
    llvm/trunk/test/CodeGen/Mips/mips64imm.ll
Modified:
    llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td
    llvm/trunk/lib/Target/Mips/MipsISelDAGToDAG.cpp
    llvm/trunk/lib/Target/Mips/MipsInstrInfo.td

Modified: llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td?rev=146059&r1=146058&r2=146059&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td (original)
+++ llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td Wed Dec  7 14:10:24 2011
@@ -25,7 +25,7 @@
 
 // Transformation Function - get Imm - 32.
 def Subtract32 : SDNodeXFormgetZExtValue() - 32);
+  return getImm(N, (unsigned)N->getZExtValue() - 32);
 }]>;
 
 // shamt field must fit in 5 bits.
@@ -36,6 +36,19 @@
                        [{return (int32_t)Imm >= 32 && (int32_t)Imm < 64;}],
                        Subtract32>;
 
+// Is a 32-bit int.
+def immSExt32 : ImmLeaf(Imm);}]>;
+
+// Transformation Function - get the higher 16 bits.
+def HIGHER : SDNodeXFormgetZExtValue() >> 32) & 0xFFFF);
+}]>;
+
+// Transformation Function - get the highest 16 bits.
+def HIGHEST : SDNodeXFormgetZExtValue() >> 48) & 0xFFFF);
+}]>;
+
 //===----------------------------------------------------------------------===//
 // Instructions specific format
 //===----------------------------------------------------------------------===//
@@ -219,9 +232,15 @@
 def : Pat<(i64 immZExt16:$in),
           (ORi64 ZERO_64, imm:$in)>;
 
+// 32-bit immediates
+def : Pat<(i64 immSExt32:$imm),
+          (ORi64 (LUi64 (HI16 imm:$imm)), (LO16 imm:$imm))>;
+
 // Arbitrary immediates
 def : Pat<(i64 imm:$imm),
-          (ORi64 (LUi64 (HI16 imm:$imm)), (LO16 imm:$imm))>;
+          (ORi64 (DSLL (ORi64 (DSLL (ORi64 (LUi64 (HIGHEST imm:$imm)),
+           (HIGHER imm:$imm)), 16), (HI16 imm:$imm)), 16),
+           (LO16 imm:$imm))>;
 
 // extended loads
 let Predicates = [NotN64] in {

Modified: llvm/trunk/lib/Target/Mips/MipsISelDAGToDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsISelDAGToDAG.cpp?rev=146059&r1=146058&r2=146059&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsISelDAGToDAG.cpp (original)
+++ llvm/trunk/lib/Target/Mips/MipsISelDAGToDAG.cpp Wed Dec  7 14:10:24 2011
@@ -88,8 +88,8 @@
 
   // getI32Imm - Return a target constant with the specified
   // value, of type i32.
-  inline SDValue getI32Imm(unsigned Imm) {
-    return CurDAG->getTargetConstant(Imm, MVT::i32);
+  inline SDValue getImm(const SDNode *Node, unsigned Imm) {
+    return CurDAG->getTargetConstant(Imm, Node->getValueType(0));
   }
 
   virtual bool SelectInlineAsmMemoryOperand(const SDValue &Op,

Modified: llvm/trunk/lib/Target/Mips/MipsInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsInstrInfo.td?rev=146059&r1=146058&r2=146059&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsInstrInfo.td (original)
+++ llvm/trunk/lib/Target/Mips/MipsInstrInfo.td Wed Dec  7 14:10:24 2011
@@ -194,12 +194,12 @@
 
 // Transformation Function - get the lower 16 bits.
 def LO16 : SDNodeXFormgetZExtValue() & 0xFFFF);
+  return getImm(N, N->getZExtValue() & 0xFFFF);
 }]>;
 
 // Transformation Function - get the higher 16 bits.
 def HI16 : SDNodeXFormgetZExtValue() >> 16);
+  return getImm(N, (N->getZExtValue() >> 16) & 0xFFFF);
 }]>;
 
 // Node immediate fits as 16-bit sign extended on target immediate.

Added: llvm/trunk/test/CodeGen/Mips/mips64imm.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/mips64imm.ll?rev=146059&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/mips64imm.ll (added)
+++ llvm/trunk/test/CodeGen/Mips/mips64imm.ll Wed Dec  7 14:10:24 2011
@@ -0,0 +1,35 @@
+; RUN: llc -march=mips64el -mcpu=mips64 < %s | FileCheck %s
+
+define i64 @foo3() nounwind readnone {
+entry:
+; CHECK: foo3
+; CHECK: lui $[[R0:[0-9]+]], 4660
+; CHECK: ori ${{[0-9]+}}, $[[R0]], 22136
+  ret i64 305419896
+}
+
+define i64 @foo6() nounwind readnone {
+entry:
+; CHECK: foo6
+; CHECK: ori ${{[0-9]+}}, $zero, 33332
+  ret i64 33332
+}
+
+define i64 @foo7() nounwind readnone {
+entry:
+; CHECK: foo7
+; CHECK: daddiu ${{[0-9]+}}, $zero, -32204
+  ret i64 -32204
+}
+
+define i64 @foo9() nounwind readnone {
+entry:
+; CHECK: foo9
+; CHECK: lui $[[R0:[0-9]+]], 4660
+; CHECK: ori $[[R1:[0-9]+]], $[[R0]], 22136
+; CHECK: dsll $[[R2:[0-9]+]], $[[R1]], 16
+; CHECK: ori $[[R3:[0-9]+]], $[[R2]], 36882
+; CHECK: dsll $[[R4:[0-9]+]], $[[R3]], 16
+; CHECK: ori ${{[0-9]+}}, $[[R4]], 13398
+  ret i64 1311768467284833366
+}



From tonic at nondot.org  Wed Dec  7 14:10:47 2011
From: tonic at nondot.org (Tanya Lattner)
Date: Wed, 07 Dec 2011 20:10:47 -0000
Subject: [llvm-commits] [www] r146060 - /www/trunk/devmtg/2010-11/index.html
Message-ID: <20111207201047.5E1C32A6C12C@llvm.org>

Author: tbrethou
Date: Wed Dec  7 14:10:47 2011
New Revision: 146060

URL: http://llvm.org/viewvc/llvm-project?rev=146060&view=rev
Log:
Cleanup outdated information.

Modified:
    www/trunk/devmtg/2010-11/index.html

Modified: www/trunk/devmtg/2010-11/index.html
URL: http://llvm.org/viewvc/llvm-project/www/trunk/devmtg/2010-11/index.html?rev=146060&r1=146059&r2=146060&view=diff
==============================================================================
--- www/trunk/devmtg/2010-11/index.html (original)
+++ www/trunk/devmtg/2010-11/index.html Wed Dec  7 14:10:47 2011
@@ -37,7 +37,6 @@
 We also invite you to sign up for the official Developer Meeting mailing list to be kept informed of updates concerning the meeting:
 
        
 
        Agenda
        
-
        More slides/videos coming.
        
 
        
 
        
 
        TimeTalkLocation
        
 
 
        



From ahatanaka at mips.com  Wed Dec  7 14:13:53 2011
From: ahatanaka at mips.com (Akira Hatanaka)
Date: Wed, 07 Dec 2011 20:13:53 -0000
Subject: [llvm-commits] [llvm] r146062 -
	/llvm/trunk/lib/Target/Mips/MipsISelDAGToDAG.cpp
Message-ID: <20111207201353.972932A6C12C@llvm.org>

Author: ahatanak
Date: Wed Dec  7 14:13:53 2011
New Revision: 146062

URL: http://llvm.org/viewvc/llvm-project?rev=146062&view=rev
Log:
Fix comment.

Modified:
    llvm/trunk/lib/Target/Mips/MipsISelDAGToDAG.cpp

Modified: llvm/trunk/lib/Target/Mips/MipsISelDAGToDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsISelDAGToDAG.cpp?rev=146062&r1=146061&r2=146062&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsISelDAGToDAG.cpp (original)
+++ llvm/trunk/lib/Target/Mips/MipsISelDAGToDAG.cpp Wed Dec  7 14:13:53 2011
@@ -87,7 +87,7 @@
   bool SelectAddr(SDValue N, SDValue &Base, SDValue &Offset);
 
   // getI32Imm - Return a target constant with the specified
-  // value, of type i32.
+  // value.
   inline SDValue getImm(const SDNode *Node, unsigned Imm) {
     return CurDAG->getTargetConstant(Imm, Node->getValueType(0));
   }



From ahatanaka at mips.com  Wed Dec  7 14:15:01 2011
From: ahatanaka at mips.com (Akira Hatanaka)
Date: Wed, 07 Dec 2011 20:15:01 -0000
Subject: [llvm-commits] [llvm] r146063 -
	/llvm/trunk/lib/Target/Mips/MipsISelDAGToDAG.cpp
Message-ID: <20111207201501.EB7022A6C12C@llvm.org>

Author: ahatanak
Date: Wed Dec  7 14:15:01 2011
New Revision: 146063

URL: http://llvm.org/viewvc/llvm-project?rev=146063&view=rev
Log:
Fix comment.

Modified:
    llvm/trunk/lib/Target/Mips/MipsISelDAGToDAG.cpp

Modified: llvm/trunk/lib/Target/Mips/MipsISelDAGToDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsISelDAGToDAG.cpp?rev=146063&r1=146062&r2=146063&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsISelDAGToDAG.cpp (original)
+++ llvm/trunk/lib/Target/Mips/MipsISelDAGToDAG.cpp Wed Dec  7 14:15:01 2011
@@ -86,8 +86,7 @@
   // Complex Pattern.
   bool SelectAddr(SDValue N, SDValue &Base, SDValue &Offset);
 
-  // getI32Imm - Return a target constant with the specified
-  // value.
+  // getImm - Return a target constant with the specified value.
   inline SDValue getImm(const SDNode *Node, unsigned Imm) {
     return CurDAG->getTargetConstant(Imm, Node->getValueType(0));
   }



From tonic at nondot.org  Wed Dec  7 14:23:06 2011
From: tonic at nondot.org (Tanya Lattner)
Date: Wed, 07 Dec 2011 20:23:06 -0000
Subject: [llvm-commits] [www] r146064 - /www/trunk/devmtg/2011-11/index.html
Message-ID: <20111207202306.A88582A6C12C@llvm.org>

Author: tbrethou
Date: Wed Dec  7 14:23:06 2011
New Revision: 146064

URL: http://llvm.org/viewvc/llvm-project?rev=146064&view=rev
Log:
Template for slides/video.

Modified:
    www/trunk/devmtg/2011-11/index.html

Modified: www/trunk/devmtg/2011-11/index.html
URL: http://llvm.org/viewvc/llvm-project/www/trunk/devmtg/2011-11/index.html?rev=146064&r1=146063&r2=146064&view=diff
==============================================================================
--- www/trunk/devmtg/2011-11/index.html (original)
+++ www/trunk/devmtg/2011-11/index.html Wed Dec  7 14:23:06 2011
@@ -46,54 +46,135 @@
 
 
        
 
        
 
        MediaTalk
        
-
 
-
-
+
 
-
-
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
 
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
        TimeTalkLocation
        8:00 - 9:00BreakfastBallroom Foyer
        9:00 - 9:20Welcome
        Chris Lattner, Apple        		Ballroom Salon III/IV
        MediaTalk
        9:20 - 10:05Extending Clang
        Doug Gregor, Apple        		Ballroom Salon III/IV
        Intel OpenCL SDK Vectorizer
        Nadav Rotem, Intel        		Ballroom Salon I/II
        
+[Slides]
+
        [Video] (Computer)
+
        [Video] (Mobile)
        
+        		Extending Clang
        Doug Gregor, Apple
        
+[Slides]
+
        [Video] (Computer)
+
        [Video] (Mobile)
        
+        		Intel OpenCL SDK Vectorizer
        Nadav Rotem, Intel
        [Slides]
+
        [Video] (Computer)
+
        [Video] (Mobile)
        
+        		Clang MapReduce -- Automatic C++ Refactoring at Google Scale
        Chandler Carruth, Google
        [Slides]
+
        [Video] (Computer)
+
        [Video] (Mobile)
        
+        		PTX Back-End: GPU Programming With LLVM
        Just
+in Holewinski, Ohio State
        [Slides]
+
        [Video] (Computer)
+
        [Video] (Mobile)
        
+        		Integrating LLVM into FreeBSD
        Brooks Davis, The FreeBSD Project
        [Slides]
+
        [Video] (Computer)
+
        [Video] (Mobile)
        
+        		Porting LLVM to a Next Generation DSP
        Taylor Simpson, QuIC
        [Slides]
+
        [Video] (Computer)
+
        [Video] (Mobile)
        
+        		DXR: Semantic Code Browsing with Clang
        Joshua Cranmer, Mozilla
        [Slides]
+
        [Video] (Computer)
+
        [Video] (Mobile)
        
+        		LLVM MC In Practice
        Jim Grosbach, Owen Anderson Apple
        [Slides]
+
        [Video] (Computer)
+
        [Video] (Mobile)
        
+        		Using clang in the Chromium project
        Nico Weber, Hans Wennborg, Google
        [Slides]
+
        [Video] (Computer)
+
        [Video] (Mobile)
        
+        		Polly - First successful optimizations - How to proceed?
        Tobias Grosser, ENS/INRIA
        [Slides]
+
        [Video] (Computer)
+
        [Video] (Mobile)
        
+        		Android Renderscript
        Stephen Hines, Google
        [Slides]
+
        [Video] (Computer)
+
        [Video] (Mobile)
        
+        		SKIR: Just-in-Time Compilation for Parallelism with LLVM
+
        Jeff Fifield, University of Colorado
        [Slides]
+
        [Video] (Computer)
+
        [Video] (Mobile)
        
+        		Register Allocation in LLVM 3.0
        Jakob Olesen, Apple
        [Slides]
+
        [Video] (Computer)
+
        [Video] (Mobile)
        
+        		Exporting 3D scenes from Maya to WebGL using clang and LLVM
        Jochen Wilhelmy, consultant
        [Slides]
+
        [Video] (Computer)
+
        [Video] (Mobile)
        
+        		Super-optimizing LLVM IR
        Duncan Sands, DeepBlueCapital
        [Slides]
+
        [Video] (Computer)
+
        [Video] (Mobile)
        
+        		Finding races and memory errors with LLVM instrumentation
        Konstantin Serebryany, Google
        [Slides]
+
        [Video] (Computer)
+
        [Video] (Mobile)
        
+        		Thread Safety Annotations in Clang
        DeLesley Hutchins, Google
        10:05 - 10:50Clang MapReduce -- Automatic C++ Refactoring at Google Scale
        Chandler Carruth, Google        		Ballroom Salon III/IV
        PTX Back-End: GPU Programming With LLVM
        Justin Holewinski, Ohio State        		Ballroom Salon I/II
        Improving LLVM Testing BOF
        David Blaikie        		Ballroom Salon VI
        10:50 - 11:05BreakBallroom Foyer
        11:05 - 11:50Integrating LLVM into FreeBSD
        Brooks Davis, The FreeBSD Project        		Ballroom Salon III/IV
        Porting LLVM to a Next Generation DSP
        Taylor Simpson, QuIC        		Ballroom Salon I/II
        11:50 - 12:35DXR: Semantic Code Browsing with Clang
        Joshua Cranmer, Mozilla        		Ballroom Salon III/IV
        LLVM MC In Practice
        Jim Grosbach, Owen Anderson Apple        		Ballroom Salon I/II
        12:35 - 1:35LunchBallroom Foyer (overflow Salon V)
        1:35 - 2:20Using clang in the Chromium project
        Nico Weber, Hans Wennborg, Google        		Ballroom Salon III/IV
        Polly - First successful optimizations - How to proceed?
        Tobias Grosser, ENS/INRIA        		Ballroom Salon I/II
        MC Linkers BOF
        Luba Tang, Mediatek, Shih-wei Liao, Google        		Ballroom Salon VI
        2:20 - 3:05Android Renderscript
        Stephen Hines, Google        		Ballroom Salon III/IV
        SKIR: Just-in-Time Compilation for Parallelism with LLVM
        Jeff Fifield, University of Colorado        		Ballroom Salon I/II
        Improving the Clang Driver BOF
        James Molloy, ARM        		Ballroom Salon VI
        3:05 - 3:45PostersBallroom Foyer
        LunarGLASS: A LLVM-based shader compiler stack
        Michael Ilseman, LunarG
        Symbolic Testing of OpenCL Code
        Peter Collingbourne, Imperial College London
        Code verification based on attributes annotation - Implementing custom attributes check using Clang
        Michael Han, Autodesk
        Parfait - A Scalable Static Bug-Checking Tool Built on LLVM
        Cristina Cifuentes, Nathan Keynes, Andrew Craik, Lian Li, Nathan Hawes, Andrew Browne, and Manuel Valdiviezo, Oracle Labs
        3:45 - 4:30Register Allocation in LLVM 3.0
        Jakob Olesen, Apple        		Ballroom Salon III/IV
        Exporting 3D scenes from Maya to WebGL using clang and LLVM
        Jochen Wilhelmy, consultant        		Ballroom Salon I/II
        4:30 - 5:15Super-optimizing LLVM IR
        Duncan Sands, DeepBlueCapital        		Ballroom Salon III/IV
        Finding races and memory errors with LLVM instrumentation
        Konstantin Serebryany, Google        		Ballroom Salon I/II
        Bitcode Portability/Versioning BOF
        Stephen Hines, David Sehr, Google        		Ballroom Salon VI
        5:15 - 6:00Thread Safety Annotations in Clang
        DeLesley Hutchins, Google        		Ballroom Salon III/IV
        Backend/Infrastructure Super BoF
        Jim Grosbach, Apple        		Ballroom Salon I/II
        Community Event Planning
        David Kipping, Qualcomm        		Ballroom Salon VI
        6:30 - 9:30Dinner (Il Fornaio - Separate registration required)
        
 
        
 
        
 



From mcrosier at apple.com  Wed Dec  7 14:44:46 2011
From: mcrosier at apple.com (Chad Rosier)
Date: Wed, 07 Dec 2011 20:44:46 -0000
Subject: [llvm-commits] [llvm] r146070 - in /llvm/trunk/lib/Bitcode/Writer:
 ValueEnumerator.cpp ValueEnumerator.h
Message-ID: <20111207204446.E481B2A6C12C@llvm.org>

Author: mcrosier
Date: Wed Dec  7 14:44:46 2011
New Revision: 146070

URL: http://llvm.org/viewvc/llvm-project?rev=146070&view=rev
Log:
ValueEnumerator - debug dump().

Modified:
    llvm/trunk/lib/Bitcode/Writer/ValueEnumerator.cpp
    llvm/trunk/lib/Bitcode/Writer/ValueEnumerator.h

Modified: llvm/trunk/lib/Bitcode/Writer/ValueEnumerator.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Bitcode/Writer/ValueEnumerator.cpp?rev=146070&r1=146069&r2=146070&view=diff
==============================================================================
--- llvm/trunk/lib/Bitcode/Writer/ValueEnumerator.cpp (original)
+++ llvm/trunk/lib/Bitcode/Writer/ValueEnumerator.cpp Wed Dec  7 14:44:46 2011
@@ -19,6 +19,8 @@
 #include "llvm/Module.h"
 #include "llvm/ValueSymbolTable.h"
 #include "llvm/Instructions.h"
+#include "llvm/Support/Debug.h"
+#include "llvm/Support/raw_ostream.h"
 #include 
 using namespace llvm;
 
@@ -107,7 +109,6 @@
   OptimizeConstants(FirstConstant, Values.size());
 }
 
-
 unsigned ValueEnumerator::getInstructionID(const Instruction *Inst) const {
   InstructionMapType::const_iterator I = InstructionMap.find(Inst);
   assert(I != InstructionMap.end() && "Instruction is not mapped!");
@@ -130,6 +131,43 @@
   return I->second-1;
 }
 
+void ValueEnumerator::dump() const {
+  print(dbgs(), ValueMap, "Default");
+  dbgs() << '\n';
+  print(dbgs(), MDValueMap, "MetaData");
+  dbgs() << '\n';
+}
+
+void ValueEnumerator::print(raw_ostream &OS, const ValueMapType &Map,
+                            const char *Name) const {
+
+  OS << "Map Name: " << Name << "\n";
+  OS << "Size: " << Map.size() << "\n";
+  for (ValueMapType::const_iterator I = Map.begin(),
+         E = Map.end(); I != E; ++I) {
+
+    const Value *V = I->first;
+    if (V->hasName())
+      OS << "Value: " << V->getName();
+    else
+      OS << "Value: [null]\n";
+    V->dump();
+
+    OS << " Uses(" << std::distance(V->use_begin(),V->use_end()) << "):";
+    for (Value::const_use_iterator UI = V->use_begin(), UE = V->use_end();
+         UI != UE; ++UI) {
+      if (UI != V->use_begin())
+        OS << ",";
+      if((*UI)->hasName())
+        OS << " " << (*UI)->getName();
+      else
+        OS << " [null]";
+
+    }
+    OS <<  "\n\n";
+  }
+}
+
 // Optimize constant ordering.
 namespace {
   struct CstSortPredicate {

Modified: llvm/trunk/lib/Bitcode/Writer/ValueEnumerator.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Bitcode/Writer/ValueEnumerator.h?rev=146070&r1=146069&r2=146070&view=diff
==============================================================================
--- llvm/trunk/lib/Bitcode/Writer/ValueEnumerator.h (original)
+++ llvm/trunk/lib/Bitcode/Writer/ValueEnumerator.h Wed Dec  7 14:44:46 2011
@@ -32,6 +32,7 @@
 class AttrListPtr;
 class ValueSymbolTable;
 class MDSymbolTable;
+class raw_ostream;
 
 class ValueEnumerator {
 public:
@@ -83,6 +84,9 @@
 public:
   ValueEnumerator(const Module *M);
 
+  void dump() const;
+  void print(raw_ostream &OS, const ValueMapType &Map, const char *Name) const;
+
   unsigned getValueID(const Value *V) const;
 
   unsigned getTypeID(Type *T) const {



From stpworld at narod.ru  Wed Dec  7 14:47:48 2011
From: stpworld at narod.ru (Stepan Dyatkovskiy)
Date: Thu, 08 Dec 2011 00:47:48 +0400
Subject: [llvm-commits] [LLVM, SwitchInst,
 case ranges] Auxiliary patch #1
In-Reply-To: <4EDE7D75.704@narod.ru>
References: <4EAA9B5D.802@narod.ru> <4EAA9DE8.80000@free.fr>
	<485181319805488@web67.yandex.ru> <4EAB079D.6000606@free.fr>
	
	<4EB18F12.6060409@narod.ru> <4EB7C319.1000709@narod.ru>
	<4EDE7D75.704@narod.ru>
Message-ID: <4EDFD0F4.1040204@narod.ru>

Ping.

-Stepan.

Stepan Dyatkovskiy wrote:
> ping.
>
> -Stepan.
>
> Stepan Dyatkovskiy wrote:
>> ping.
>> -Stepan.
>>
>> Stepan Dyatkovskiy wrote:
>>> Hello, Duncan.
>>>
>>> Duncan Sands wrote:
>>>    >   I guess Anton can comment on codegen, but the fact that it doesn't make
>>>    >   codegen
>>>    >   harder has nothing to do with increasing the complexity of the
>>>    >   optimizers, since
>>>    >   they work at the IR level. It may be that case ranges allow the
>>>    >   optimizers to
>>>    >   do a better job. It may be that they simplify the optimizers. But it
>>>    >   also may
>>>    >   be the opposite: they might make switches harder to work with and reason
>>>    >   about
>>>    >   for no advantage. Which is it? Do you have an example where case ranges
>>>    >   would
>>>    >   result in better code, or make it easier to produce better code?
>>>
>>> I made impact analysis for new case ranges feature.
>>> 24 out of more than 100 optimizations are affected. 20 of 24 just
>>> require an integration of a new "case-range" type, i.e. small change of
>>> code without. The remaining 4 requires some bigger changes. All affected
>>> optimizers are listed in attached spreadsheet.
>>>
>>> Patches that are submitted in this branch are just functionality
>>> extension for current classes. These patches doesn't brake any of
>>> existing optimizations and keeps its speed without changes.
>>>
>>> Well. Let's enumerate 4 optimizations that should be reworked.
>>>
>>> 1. LowerSwitch::Clusterify
>>>
>>> This method groups neighbouring cases (by value) that goes to the same
>>> destination.
>>>
>>> For example:
>>>
>>> switch i32 %cond, label %default [
>>> i32 1, label %successorA
>>> i32 2, label %successorA
>>> i32 5, label %successorB
>>> i32 3, label %successorA
>>> i32 6, label %successorB
>>> ]
>>>
>>> will be grouped to the two clusters:
>>>
>>> [[i32 1] .. [i32 3]], label %successorA
>>> [[i32 5] .. [i32 6]], label %successorB
>>>
>>> This method will work faster if clusters will presented explicitly using
>>> new case ranges feature.
>>>
>>> 2. SimplifyCFG.cpp, TurnSwitchRangeIntoICmp (static function)
>>>
>>> "Turns a switch that contains only an integer range comparison into a
>>> sub, an icmp and a branch." (written in method comments). Algorithm that
>>> determines "solid" case range should be changed.
>>>
>>> Now compare two switches (don't look at syntax of second switch, it is
>>> still a subject of another discussion):
>>>
>>> switch i32 %cond, label %default [
>>> i32 1, label %successorA
>>> i32 2, label %successorA
>>> i32 3, label %successorA
>>> ]
>>>
>>> and hypothetical switch:
>>>
>>> switch i32 %cond, label %default [
>>> [[i32 1],[i32 3]], label %successorA ; case range [1..3]
>>> ]
>>>
>>> or even this one:
>>>
>>> switch i32 %cond, label %default [
>>> [[i32 1],[i32 2]], label %successorA ; case range [1..2]
>>> i32 3, label %successorA ; single case value "3"
>>> ]
>>>
>>> Its obvious that last two switches will be processed faster than the
>>> first one. We doesn't need to perform analysis for each separated case
>>> value. We already know - that it is a range.
>>>
>>> 3. SimplifyCFG.cpp, EliminateDeadSwitchCases (static function).
>>>
>>> Here switch condition is analysed. We try to determine "1" and "0" bits
>>> that MUST be in condition value. If we found them, then we look at case
>>> values; if these bits are absent in case value we remove it since it
>>> will be never equal to condition.
>>> I need to think more about the ways of case ranges processing here. At
>>> least we can represent case range as separated values set and apply
>>> current algorithm to it. It slow down the processing a little bit, but
>>> the complexity itself will be not increased. I'm sure that there are
>>> also exists algorithms that allows to eliminate whole case ranges: e.g.
>>> we can apply current algorithm to high bits that are constant in case
>>> range.
>>>
>>> 4. lib/Transforms/Scalar/LoopUnswitch.cpp (the set of methods).
>>>
>>> Just a quote from LoopUnswitch.cpp header
>>>
>>> [quote]
>>> This pass transforms loops that contain branches on loop-invariant
>>> conditions
>>> to have multiple loops. For example, it turns the left into the right code.
>>>
>>> for (...) if (lic)
>>> A for (...)
>>> if (lic) A; B; C
>>> B else
>>> C for (...)
>>> A; C
>>> [/quote]
>>>
>>> I also must think more about case ranges unswithing here.
>>> By now loops with switch instruction are unswitched value-by-value.
>>> There is no any case-values clustering before unswitching. For example
>>> for case range [0..9] we need to run unswitch process 10 times!
>>> Theoretically, explicitly given case ranges and properly implemented
>>> unswitching should make this optimization better.
>>>
>>> So, as you can see complexity will not changed and even some of
>>> optimizations will work faster.
>>>
>>> Regards,
>>> Stepan.
>>>
>>>
>>> _______________________________________________
>>> llvm-commits mailing list
>>> llvm-commits at cs.uiuc.edu
>>> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
>>
>> _______________________________________________
>> llvm-commits mailing list
>> llvm-commits at cs.uiuc.edu
>> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
>
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits


From baldrick at free.fr  Wed Dec  7 14:54:41 2011
From: baldrick at free.fr (Duncan Sands)
Date: Wed, 07 Dec 2011 20:54:41 -0000
Subject: [llvm-commits] [llvm] r146071 - /llvm/trunk/tools/CMakeLists.txt
Message-ID: <20111207205441.749A52A6C12C@llvm.org>

Author: baldrick
Date: Wed Dec  7 14:54:41 2011
New Revision: 146071

URL: http://llvm.org/viewvc/llvm-project?rev=146071&view=rev
Log:
Have cmake build llvm-cov.  Patch by arrowdodger.

Modified:
    llvm/trunk/tools/CMakeLists.txt

Modified: llvm/trunk/tools/CMakeLists.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/CMakeLists.txt?rev=146071&r1=146070&r2=146071&view=diff
==============================================================================
--- llvm/trunk/tools/CMakeLists.txt (original)
+++ llvm/trunk/tools/CMakeLists.txt Wed Dec  7 14:54:41 2011
@@ -28,6 +28,7 @@
 add_subdirectory(llvm-size)
 
 add_subdirectory(llvm-ld)
+add_subdirectory(llvm-cov)
 add_subdirectory(llvm-prof)
 add_subdirectory(llvm-link)
 add_subdirectory(lli)



From baldrick at free.fr  Wed Dec  7 14:58:10 2011
From: baldrick at free.fr (Duncan Sands)
Date: Wed, 07 Dec 2011 21:58:10 +0100
Subject: [llvm-commits] [PATCH][CMake] Connect llvm-cov tool to
	the	build.
In-Reply-To: 
References: 
Message-ID: <4EDFD362.1070805@free.fr>

On 07/12/11 16:49, arrowdodger wrote:
> I've found that llvm-cov tool is not being built by CMake buildsystem, this
> patch fixes this.

Thanks.  Applied in commit 146071.

Ciao, Duncan.

From criswell at uiuc.edu  Wed Dec  7 15:21:42 2011
From: criswell at uiuc.edu (John Criswell)
Date: Wed, 07 Dec 2011 21:21:42 -0000
Subject: [llvm-commits] [www-pubs] r146073 - /www-pubs/trunk/pubs.js
Message-ID: <20111207212142.4DE8A2A6C12C@llvm.org>

Author: criswell
Date: Wed Dec  7 15:21:41 2011
New Revision: 146073

URL: http://llvm.org/viewvc/llvm-project?rev=146073&view=rev
Log:
Added some papers from PLDI, ISMM, SIGCOMM, CGO, and other conferences and 
ournals for year 2011.

Modified:
    www-pubs/trunk/pubs.js

Modified: www-pubs/trunk/pubs.js
URL: http://llvm.org/viewvc/llvm-project/www-pubs/trunk/pubs.js?rev=146073&r1=146072&r2=146073&view=diff
==============================================================================
--- www-pubs/trunk/pubs.js (original)
+++ www-pubs/trunk/pubs.js Wed Dec  7 15:21:41 2011
@@ -1,7 +1,48 @@
 // The array should be sorted reverse-chronologically, and will be displayed on
 // the page in the order listed.
 var PUBS =
-[ { url: "http://homepages.uni-paderborn.de/mgrad/Mariusz_Grad_Homepage/Publications_files/grad11_raw_paper.pdf",
+[
+  { url: "",
+    author: "Haohui Mai, Ahmed Khurshid, Rachit Agarwal, Matthew Caesar, P. Brighten Godfrey, and Samuel T. King",
+    title: "Debugging the Data Plane with Anteater",
+    published: "Annual Conference of the ACM Special Interest Group on Data Communication (SIGCOMM)",
+    month: 8,
+    year: 2011,
+  },
+
+  { url: "http://www.hipeac.net/system/files?file=standaloneopencl.pdf",
+    author: "Pekka Jääskeläinen, Carlos S. de La Lama, Pablo Huerta, and Jarmo Takala",
+    title: "OpenCL-based Design Methodology for Application-Specific Processors",
+    published: "Transactions on HiPEAC",
+    month: 7,
+    year: 2011,
+  },
+
+  { url: "http://liberty.princeton.edu/Publications/index.php?abs=1&setselect=pldi11_cuda",
+    author: "Thomas B. Jablin, Prakash Prabhu, James A. Jablin, Nick P. Johnson, Stephen R. Beard, and David I. August",
+    title: "Automatic CPU-GPU Communication Management and Optimization",
+    published: "ACM SIGPLAN Conference on Programming Language Design and Implementation (PLDI)",
+    month: 6,
+    year: 2011,
+  },
+
+  { url: "http://liberty.princeton.edu/Publications/index.php?abs=1&setselect=pldi11_commset",
+    author: "Prakash Prabhu, Soumyadeep Ghosh, Yun Zhang, Nick P. Johnson, and David I. August",
+    title: "Commutative Set: A Language Extension for Implicit Parallel Programming",
+    published: "ACM SIGPLAN Conference on Programming Language Design and Implementation (PLDI)",
+    month: 6,
+    year: 2011,
+  },
+
+  { url: "",
+    author: "Xiaoming Gu and Chen Ding",
+    title: "On the Theory and Potential of LRU-MRU Collaborative Cache Management",
+    published: "International Symposium on Memory Management (ISMM)",
+    month: 6,
+    year: 2011,
+  },
+
+  { url: "http://homepages.uni-paderborn.de/mgrad/Mariusz_Grad_Homepage/Publications_files/grad11_raw_paper.pdf",
     author: "Mariusz Grad and Christian Plessl",
     title: "Just-in-time Instruction Set Extension - Feasibility and Limitations for an FPGA-based Reconfigurable ASIP Architecture",
     published: "Reconfigurable Architectures Workshop (RAW 2011), Proceedings of the International Parallel and Distributed Processing Symposium",
@@ -10,6 +51,30 @@
     year: 2011
   },
 
+  { url: "",
+    author: "Ben Hardekopf and Calvin Lin",
+    title: "Flow-Sensitive Pointer Analysis for Millions of Lines of Code",
+    published: "International Symposium on Code Generation and Optimization (CGO)",
+    month: 4,
+    year: 2011,
+  },
+
+  { url: "",
+    author: "Ralf Karrenberg",
+    title: "Whole-Function Vectorization",
+    published: "International Symposium on Code Generation and Optimization (CGO)",
+    month: 4,
+    year: 2011,
+  },
+
+  { url: "http://dx.doi.org/10.1002/spe.1059",
+    author: "James Stanier and Des Watson",
+    title: "A study of irreducibility in C programs",
+    published: "Software: Practice and Experience",
+    month: 3,
+    year: 2011,
+  },
+
  { url: "2011-02-FOSDEM-LLVMAndClang.html",
    title: "LLVM and Clang: Advancing Compiler Technology",
    published: "Keynote Talk, FOSDEM 2011: Free and Open Source Developers European Meeting",



From kcc at google.com  Wed Dec  7 15:30:21 2011
From: kcc at google.com (Kostya Serebryany)
Date: Wed, 07 Dec 2011 21:30:21 -0000
Subject: [llvm-commits] [compiler-rt] r146075 - in
 /compiler-rt/trunk/lib/asan: asan_rtl.cc tests/asan_test.cc
Message-ID: <20111207213021.3342C2A6C12C@llvm.org>

Author: kcc
Date: Wed Dec  7 15:30:20 2011
New Revision: 146075

URL: http://llvm.org/viewvc/llvm-project?rev=146075&view=rev
Log:
[asan] fix the error message for 16-byte accesses (it previously printed 'unknown-crash')

Modified:
    compiler-rt/trunk/lib/asan/asan_rtl.cc
    compiler-rt/trunk/lib/asan/tests/asan_test.cc

Modified: compiler-rt/trunk/lib/asan/asan_rtl.cc
URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/lib/asan/asan_rtl.cc?rev=146075&r1=146074&r2=146075&view=diff
==============================================================================
--- compiler-rt/trunk/lib/asan/asan_rtl.cc (original)
+++ compiler-rt/trunk/lib/asan/asan_rtl.cc Wed Dec  7 15:30:20 2011
@@ -556,12 +556,13 @@
   const char *bug_descr = "unknown-crash";
   if (AddrIsInMem(addr)) {
     uint8_t *shadow_addr = (uint8_t*)MemToShadow(addr);
-    uint8_t shadow_byte = shadow_addr[0];
-    if (shadow_byte > 0 && shadow_byte < 128) {
-      // we are in the partial right redzone, look at the next shadow byte.
-      shadow_byte = shadow_addr[1];
-    }
-    switch (shadow_byte) {
+    // If we are accessing 16 bytes, look at the second shadow byte.
+    if (*shadow_addr == 0 && access_size > SHADOW_GRANULARITY)
+      shadow_addr++;
+    // If we are in the partial right redzone, look at the next shadow byte.
+    if (*shadow_addr > 0 && *shadow_addr < 128)
+      shadow_addr++;
+    switch (*shadow_addr) {
       case kAsanHeapLeftRedzoneMagic:
       case kAsanHeapRightRedzoneMagic:
         bug_descr = "heap-buffer-overflow";

Modified: compiler-rt/trunk/lib/asan/tests/asan_test.cc
URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/lib/asan/tests/asan_test.cc?rev=146075&r1=146074&r2=146075&view=diff
==============================================================================
--- compiler-rt/trunk/lib/asan/tests/asan_test.cc (original)
+++ compiler-rt/trunk/lib/asan/tests/asan_test.cc Wed Dec  7 15:30:20 2011
@@ -833,6 +833,8 @@
   assert(((uintptr_t)p % 16) == 0);
   __m128i value_wide = _mm_set1_epi16(0x1234);
   EXPECT_DEATH(_mm_store_si128((__m128i*)p, value_wide),
+               "AddressSanitizer heap-buffer-overflow");
+  EXPECT_DEATH(_mm_store_si128((__m128i*)p, value_wide),
                "WRITE of size 16");
   EXPECT_DEATH(_mm_store_si128((__m128i*)p, value_wide),
                "located 0 bytes to the right of 12-byte");



From nicholas at mxc.ca  Wed Dec  7 15:35:59 2011
From: nicholas at mxc.ca (Nick Lewycky)
Date: Wed, 07 Dec 2011 21:35:59 -0000
Subject: [llvm-commits] [llvm] r146076 -
	/llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
Message-ID: <20111207213559.DD96F2A6C12C@llvm.org>

Author: nicholas
Date: Wed Dec  7 15:35:59 2011
New Revision: 146076

URL: http://llvm.org/viewvc/llvm-project?rev=146076&view=rev
Log:
These global variables aren't thread-safe, STATISTIC is. Andy Trick tells me
that he isn't using these any more, so just delete them.

Modified:
    llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp?rev=146076&r1=146075&r2=146076&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp Wed Dec  7 15:35:59 2011
@@ -102,17 +102,6 @@
   "sched-avg-ipc", cl::Hidden, cl::init(1),
   cl::desc("Average inst/cycle whan no target itinerary exists."));
 
-#ifndef NDEBUG
-namespace {
-  // For sched=list-ilp, Count the number of times each factor comes into play.
-  enum { FactPressureDiff, FactRegUses, FactStall, FactHeight, FactDepth,
-         FactStatic, FactOther, NumFactors };
-}
-static const char *FactorName[NumFactors] =
-{"PressureDiff", "RegUses", "Stall", "Height", "Depth","Static", "Other"};
-static int FactorCount[NumFactors];
-#endif //!NDEBUG
-
 namespace {
 //===----------------------------------------------------------------------===//
 /// ScheduleDAGRRList - The actual register reduction list scheduler
@@ -308,11 +297,6 @@
   DEBUG(dbgs()
         << "********** List Scheduling BB#" << BB->getNumber()
         << " '" << BB->getName() << "' **********\n");
-#ifndef NDEBUG
-  for (int i = 0; i < NumFactors; ++i) {
-    FactorCount[i] = 0;
-  }
-#endif //!NDEBUG
 
   CurCycle = 0;
   IssueCount = 0;
@@ -337,11 +321,6 @@
   // Execute the actual scheduling loop.
   ListScheduleBottomUp();
 
-#ifndef NDEBUG
-  for (int i = 0; i < NumFactors; ++i) {
-    DEBUG(dbgs() << FactorName[i] << "\t" << FactorCount[i] << "\n");
-  }
-#endif // !NDEBUG
   AvailableQueue->releaseState();
 }
 
@@ -2296,28 +2275,20 @@
   // If scheduling either one of the node will cause a pipeline stall, sort
   // them according to their height.
   if (LStall) {
-    if (!RStall) {
-      DEBUG(++FactorCount[FactStall]);
+    if (!RStall)
       return 1;
-    }
-    if (LHeight != RHeight) {
-      DEBUG(++FactorCount[FactStall]);
+    if (LHeight != RHeight)
       return LHeight > RHeight ? 1 : -1;
-    }
-  } else if (RStall) {
-    DEBUG(++FactorCount[FactStall]);
+  } else if (RStall)
     return -1;
-  }
 
   // If either node is scheduling for latency, sort them by height/depth
   // and latency.
   if (!checkPref || (left->SchedulingPref == Sched::ILP ||
                      right->SchedulingPref == Sched::ILP)) {
     if (DisableSchedCycles) {
-      if (LHeight != RHeight) {
-        DEBUG(++FactorCount[FactHeight]);
+      if (LHeight != RHeight)
         return LHeight > RHeight ? 1 : -1;
-      }
     }
     else {
       // If neither instruction stalls (!LStall && !RStall) then
@@ -2326,17 +2297,14 @@
       int LDepth = left->getDepth() - LPenalty;
       int RDepth = right->getDepth() - RPenalty;
       if (LDepth != RDepth) {
-        DEBUG(++FactorCount[FactDepth]);
         DEBUG(dbgs() << "  Comparing latency of SU (" << left->NodeNum
               << ") depth " << LDepth << " vs SU (" << right->NodeNum
               << ") depth " << RDepth << "\n");
         return LDepth < RDepth ? 1 : -1;
       }
     }
-    if (left->Latency != right->Latency) {
-      DEBUG(++FactorCount[FactOther]);
+    if (left->Latency != right->Latency)
       return left->Latency > right->Latency ? 1 : -1;
-    }
   }
   return 0;
 }
@@ -2350,7 +2318,6 @@
     bool LHasPhysReg = left->hasPhysRegDefs;
     bool RHasPhysReg = right->hasPhysRegDefs;
     if (LHasPhysReg != RHasPhysReg) {
-      DEBUG(++FactorCount[FactRegUses]);
       #ifndef NDEBUG
       const char *PhysRegMsg[] = {" has no physreg", " defines a physreg"};
       #endif
@@ -2376,10 +2343,8 @@
     LPriority = (LPriority > LNumVals) ? (LPriority - LNumVals) : 0;
   }
 
-  if (LPriority != RPriority) {
-    DEBUG(++FactorCount[FactStatic]);
+  if (LPriority != RPriority)
     return LPriority > RPriority;
-  }
 
   // One or both of the nodes are calls and their sethi-ullman numbers are the
   // same, then keep source order.
@@ -2412,18 +2377,14 @@
   // This creates more short live intervals.
   unsigned LDist = closestSucc(left);
   unsigned RDist = closestSucc(right);
-  if (LDist != RDist) {
-    DEBUG(++FactorCount[FactOther]);
+  if (LDist != RDist)
     return LDist < RDist;
-  }
 
   // How many registers becomes live when the node is scheduled.
   unsigned LScratch = calcMaxScratches(left);
   unsigned RScratch = calcMaxScratches(right);
-  if (LScratch != RScratch) {
-    DEBUG(++FactorCount[FactOther]);
+  if (LScratch != RScratch)
     return LScratch > RScratch;
-  }
 
   // Comparing latency against a call makes little sense unless the node
   // is register pressure-neutral.
@@ -2438,20 +2399,15 @@
       return result > 0;
   }
   else {
-    if (left->getHeight() != right->getHeight()) {
-      DEBUG(++FactorCount[FactHeight]);
+    if (left->getHeight() != right->getHeight())
       return left->getHeight() > right->getHeight();
-    }
 
-    if (left->getDepth() != right->getDepth()) {
-      DEBUG(++FactorCount[FactDepth]);
+    if (left->getDepth() != right->getDepth())
       return left->getDepth() < right->getDepth();
-    }
   }
 
   assert(left->NodeQueueId && right->NodeQueueId &&
          "NodeQueueId cannot be zero");
-  DEBUG(++FactorCount[FactOther]);
   return (left->NodeQueueId > right->NodeQueueId);
 }
 
@@ -2511,13 +2467,11 @@
   // Avoid causing spills. If register pressure is high, schedule for
   // register pressure reduction.
   if (LHigh && !RHigh) {
-    DEBUG(++FactorCount[FactPressureDiff]);
     DEBUG(dbgs() << "  pressure SU(" << left->NodeNum << ") > SU("
           << right->NodeNum << ")\n");
     return true;
   }
   else if (!LHigh && RHigh) {
-    DEBUG(++FactorCount[FactPressureDiff]);
     DEBUG(dbgs() << "  pressure SU(" << right->NodeNum << ") > SU("
           << left->NodeNum << ")\n");
     return false;
@@ -2581,7 +2535,6 @@
     RPDiff = SPQ->RegPressureDiff(right, RLiveUses);
   }
   if (!DisableSchedRegPressure && LPDiff != RPDiff) {
-    DEBUG(++FactorCount[FactPressureDiff]);
     DEBUG(dbgs() << "RegPressureDiff SU(" << left->NodeNum << "): " << LPDiff
           << " != SU(" << right->NodeNum << "): " << RPDiff << "\n");
     return LPDiff > RPDiff;
@@ -2590,7 +2543,6 @@
   if (!DisableSchedRegPressure && (LPDiff > 0 || RPDiff > 0)) {
     bool LReduce = canEnableCoalescing(left);
     bool RReduce = canEnableCoalescing(right);
-    DEBUG(if (LReduce != RReduce) ++FactorCount[FactPressureDiff]);
     if (LReduce && !RReduce) return false;
     if (RReduce && !LReduce) return true;
   }
@@ -2598,17 +2550,14 @@
   if (!DisableSchedLiveUses && (LLiveUses != RLiveUses)) {
     DEBUG(dbgs() << "Live uses SU(" << left->NodeNum << "): " << LLiveUses
           << " != SU(" << right->NodeNum << "): " << RLiveUses << "\n");
-    DEBUG(++FactorCount[FactRegUses]);
     return LLiveUses < RLiveUses;
   }
 
   if (!DisableSchedStalls) {
     bool LStall = BUHasStall(left, left->getHeight(), SPQ);
     bool RStall = BUHasStall(right, right->getHeight(), SPQ);
-    if (LStall != RStall) {
-      DEBUG(++FactorCount[FactHeight]);
+    if (LStall != RStall)
       return left->getHeight() > right->getHeight();
-    }
   }
 
   if (!DisableSchedCriticalPath) {
@@ -2617,17 +2566,14 @@
       DEBUG(dbgs() << "Depth of SU(" << left->NodeNum << "): "
             << left->getDepth() << " != SU(" << right->NodeNum << "): "
             << right->getDepth() << "\n");
-      DEBUG(++FactorCount[FactDepth]);
       return left->getDepth() < right->getDepth();
     }
   }
 
   if (!DisableSchedHeight && left->getHeight() != right->getHeight()) {
     int spread = (int)left->getHeight() - (int)right->getHeight();
-    if (std::abs(spread) > MaxReorderWindow) {
-      DEBUG(++FactorCount[FactHeight]);
+    if (std::abs(spread) > MaxReorderWindow)
       return left->getHeight() > right->getHeight();
-    }
   }
 
   return BURRSort(left, right, SPQ);



From criswell at uiuc.edu  Wed Dec  7 15:43:20 2011
From: criswell at uiuc.edu (John Criswell)
Date: Wed, 07 Dec 2011 21:43:20 -0000
Subject: [llvm-commits] [www-pubs] r146077 - /www-pubs/trunk/pubs.js
Message-ID: <20111207214320.4E1DC2A6C12C@llvm.org>

Author: criswell
Date: Wed Dec  7 15:43:20 2011
New Revision: 146077

URL: http://llvm.org/viewvc/llvm-project?rev=146077&view=rev
Log:
Added the PEREGRINE paper.

Modified:
    www-pubs/trunk/pubs.js

Modified: www-pubs/trunk/pubs.js
URL: http://llvm.org/viewvc/llvm-project/www-pubs/trunk/pubs.js?rev=146077&r1=146076&r2=146077&view=diff
==============================================================================
--- www-pubs/trunk/pubs.js (original)
+++ www-pubs/trunk/pubs.js Wed Dec  7 15:43:20 2011
@@ -2,6 +2,14 @@
 // the page in the order listed.
 var PUBS =
 [
+  { url: "http://systems.cs.columbia.edu/files/wpid-peregrine-sosp11.pdf",
+    author: "Heming Cui, Jingyue Wu, John Gallagher, Huayang Guo, Junfeng Yang",
+    title: "Efficient Deterministic Multithreading through Schedule Relaxation",
+    published: "ACM Symposium on Operating Systems Principles (SOSP)",
+    month: 10,
+    year: 2011,
+  },
+
   { url: "",
     author: "Haohui Mai, Ahmed Khurshid, Rachit Agarwal, Matthew Caesar, P. Brighten Godfrey, and Samuel T. King",
     title: "Debugging the Data Plane with Anteater",



From mcrosier at apple.com  Wed Dec  7 15:44:13 2011
From: mcrosier at apple.com (Chad Rosier)
Date: Wed, 07 Dec 2011 21:44:13 -0000
Subject: [llvm-commits] [llvm] r146078 - in /llvm/trunk:
 include/llvm/Bitcode/LLVMBitCodes.h lib/Bitcode/Reader/BitcodeReader.cpp
 lib/Bitcode/Reader/BitcodeReader.h lib/Bitcode/Writer/BitcodeWriter.cpp
Message-ID: <20111207214413.23B1C2A6C12C@llvm.org>

Author: mcrosier
Date: Wed Dec  7 15:44:12 2011
New Revision: 146078

URL: http://llvm.org/viewvc/llvm-project?rev=146078&view=rev
Log:
Begin adding experimental support for preserving use-list ordering of bitcode
files.  First, add a new block USELIST_BLOCK to the bitcode format.  This is 
where USELIST_CODE_ENTRYs will be stored.  The format of the USELIST_CODE_ENTRYs
have not yet been defined.  Add support in the BitcodeReader for parsing the
USELIST_BLOCK.
Part of rdar://9860654 and PR5680.

Modified:
    llvm/trunk/include/llvm/Bitcode/LLVMBitCodes.h
    llvm/trunk/lib/Bitcode/Reader/BitcodeReader.cpp
    llvm/trunk/lib/Bitcode/Reader/BitcodeReader.h
    llvm/trunk/lib/Bitcode/Writer/BitcodeWriter.cpp

Modified: llvm/trunk/include/llvm/Bitcode/LLVMBitCodes.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Bitcode/LLVMBitCodes.h?rev=146078&r1=146077&r2=146078&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Bitcode/LLVMBitCodes.h (original)
+++ llvm/trunk/include/llvm/Bitcode/LLVMBitCodes.h Wed Dec  7 15:44:12 2011
@@ -41,7 +41,9 @@
     METADATA_BLOCK_ID,
     METADATA_ATTACHMENT_ID,
     
-    TYPE_BLOCK_ID_NEW
+    TYPE_BLOCK_ID_NEW,
+
+    USELIST_BLOCK_ID
   };
 
 
@@ -311,6 +313,10 @@
     FUNC_CODE_INST_STOREATOMIC = 42  // STORE: [ptrty,ptr,val, align, vol
                                      //         ordering, synchscope]
   };
+
+  enum UseListCodes {
+    USELIST_CODE_ENTRY = 1   // USELIST_CODE_ENTRY: TBD.
+  };
 } // End bitc namespace
 } // End llvm namespace
 

Modified: llvm/trunk/lib/Bitcode/Reader/BitcodeReader.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Bitcode/Reader/BitcodeReader.cpp?rev=146078&r1=146077&r2=146078&view=diff
==============================================================================
--- llvm/trunk/lib/Bitcode/Reader/BitcodeReader.cpp (original)
+++ llvm/trunk/lib/Bitcode/Reader/BitcodeReader.cpp Wed Dec  7 15:44:12 2011
@@ -1287,6 +1287,50 @@
   return false;
 }
 
+bool BitcodeReader::ParseUseLists() {
+  if (Stream.EnterSubBlock(bitc::USELIST_BLOCK_ID))
+    return Error("Malformed block record");
+
+  SmallVector Record;
+  
+  // Read all the records.
+  while (1) {
+    unsigned Code = Stream.ReadCode();
+    if (Code == bitc::END_BLOCK) {
+      if (Stream.ReadBlockEnd())
+        return Error("Error at end of use-list table block");
+      return false;
+    }
+    
+    if (Code == bitc::ENTER_SUBBLOCK) {
+      // No known subblocks, always skip them.
+      Stream.ReadSubBlockID();
+      if (Stream.SkipBlock())
+        return Error("Malformed block record");
+      continue;
+    }
+    
+    if (Code == bitc::DEFINE_ABBREV) {
+      Stream.ReadAbbrevRecord();
+      continue;
+    }
+    
+    // Read a use list record.
+    Record.clear();
+    switch (Stream.ReadRecord(Code, Record)) {
+    default:  // Default behavior: unknown type.
+      break;
+    case bitc::USELIST_CODE_ENTRY: { // USELIST_CODE_ENTRY: TBD.
+      unsigned RecordLength = Record.size();
+      if (RecordLength < 1)
+        return Error ("Invalid UseList reader!");
+      UseListRecords.push_back(Record);
+      break;
+    }
+    }
+  }
+}
+
 /// RememberAndSkipFunctionBody - When we see the block for a function body,
 /// remember where it is and then skip it.  This lets us lazily deserialize the
 /// functions.
@@ -1393,6 +1437,10 @@
         if (RememberAndSkipFunctionBody())
           return true;
         break;
+      case bitc::USELIST_BLOCK_ID:
+        if (ParseUseLists())
+          return true;
+        break;
       }
       continue;
     }
@@ -2746,6 +2794,9 @@
     return 0;
   }
 
+  // TODO: Restore the use-lists to the in-memory state when the bitcode was
+  // written.  We must defer until the Module has been fully materialized.
+
   return M;
 }
 

Modified: llvm/trunk/lib/Bitcode/Reader/BitcodeReader.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Bitcode/Reader/BitcodeReader.h?rev=146078&r1=146077&r2=146078&view=diff
==============================================================================
--- llvm/trunk/lib/Bitcode/Reader/BitcodeReader.h (original)
+++ llvm/trunk/lib/Bitcode/Reader/BitcodeReader.h Wed Dec  7 15:44:12 2011
@@ -135,6 +135,7 @@
   BitcodeReaderValueList ValueList;
   BitcodeReaderMDValueList MDValueList;
   SmallVector InstructionList;
+  SmallVector, 64> UseListRecords;
 
   std::vector > GlobalInits;
   std::vector > AliasInits;
@@ -268,6 +269,7 @@
   bool ParseMetadata();
   bool ParseMetadataAttachment();
   bool ParseModuleTriple(std::string &Triple);
+  bool ParseUseLists();
 };
   
 } // End llvm namespace

Modified: llvm/trunk/lib/Bitcode/Writer/BitcodeWriter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Bitcode/Writer/BitcodeWriter.cpp?rev=146078&r1=146077&r2=146078&view=diff
==============================================================================
--- llvm/trunk/lib/Bitcode/Writer/BitcodeWriter.cpp (original)
+++ llvm/trunk/lib/Bitcode/Writer/BitcodeWriter.cpp Wed Dec  7 15:44:12 2011
@@ -23,6 +23,7 @@
 #include "llvm/Operator.h"
 #include "llvm/ValueSymbolTable.h"
 #include "llvm/ADT/Triple.h"
+#include "llvm/Support/CommandLine.h"
 #include "llvm/Support/ErrorHandling.h"
 #include "llvm/Support/MathExtras.h"
 #include "llvm/Support/raw_ostream.h"
@@ -31,6 +32,12 @@
 #include 
 using namespace llvm;
 
+static cl::opt
+EnablePreserveUseListOrdering("enable-bc-uselist-preserve",
+                              cl::desc("Turn on experimental support for "
+                                       "use-list order preservation."),
+                              cl::init(false), cl::Hidden);
+
 /// These are manifest constants used by the bitcode writer. They do not need to
 /// be kept in sync with the reader, but need to be consistent within this file.
 enum {
@@ -1571,6 +1578,20 @@
   Stream.ExitBlock();
 }
 
+// Emit use-lists.
+static void WriteModuleUseLists(const Module *M, ValueEnumerator &VE,
+                                BitstreamWriter &Stream) {
+  Stream.EnterSubblock(bitc::USELIST_BLOCK_ID, 3);
+
+  // Emit a bogus record for testing purposes.
+  SmallVector Record;
+  Record.push_back(0);
+  Stream.EmitRecord(bitc::USELIST_CODE_ENTRY, Record);
+
+  // TODO: Tons.
+
+  Stream.ExitBlock();
+}
 
 /// WriteModule - Emit the specified module to the bitstream.
 static void WriteModule(const Module *M, BitstreamWriter &Stream) {
@@ -1616,6 +1637,10 @@
   // Emit names for globals/functions etc.
   WriteValueSymbolTable(M->getValueSymbolTable(), VE, Stream);
 
+  // Emit use-lists.
+  if (EnablePreserveUseListOrdering)
+    WriteModuleUseLists(M, VE, Stream);
+
   Stream.ExitBlock();
 }
 



From mcrosier at apple.com  Wed Dec  7 15:45:13 2011
From: mcrosier at apple.com (Chad Rosier)
Date: Wed, 07 Dec 2011 21:45:13 -0000
Subject: [llvm-commits] [llvm] r146079 -
	/llvm/trunk/tools/llvm-bcanalyzer/llvm-bcanalyzer.cpp
Message-ID: <20111207214513.876452A6C12C@llvm.org>

Author: mcrosier
Date: Wed Dec  7 15:45:13 2011
New Revision: 146079

URL: http://llvm.org/viewvc/llvm-project?rev=146079&view=rev
Log:
Update bcanalyzer to handle new USELIST_BLOCK/USELIST_CODE_ENTRY.

Modified:
    llvm/trunk/tools/llvm-bcanalyzer/llvm-bcanalyzer.cpp

Modified: llvm/trunk/tools/llvm-bcanalyzer/llvm-bcanalyzer.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvm-bcanalyzer/llvm-bcanalyzer.cpp?rev=146079&r1=146078&r2=146079&view=diff
==============================================================================
--- llvm/trunk/tools/llvm-bcanalyzer/llvm-bcanalyzer.cpp (original)
+++ llvm/trunk/tools/llvm-bcanalyzer/llvm-bcanalyzer.cpp Wed Dec  7 15:45:13 2011
@@ -108,6 +108,7 @@
   case bitc::VALUE_SYMTAB_BLOCK_ID:  return "VALUE_SYMTAB";
   case bitc::METADATA_BLOCK_ID:      return "METADATA_BLOCK";
   case bitc::METADATA_ATTACHMENT_ID: return "METADATA_ATTACHMENT_BLOCK";
+  case bitc::USELIST_BLOCK_ID:       return "USELIST_BLOCK_ID";
   }
 }
 
@@ -264,6 +265,11 @@
     case bitc::METADATA_FN_NODE:     return "METADATA_FN_NODE";
     case bitc::METADATA_NAMED_NODE:  return "METADATA_NAMED_NODE";
     }
+  case bitc::USELIST_BLOCK_ID:
+    switch(CodeID) {
+    default:return 0;
+    case bitc::USELIST_CODE_ENTRY:   return "USELIST_CODE_ENTRY";
+    }
   }
 }
 



From ahatanaka at mips.com  Wed Dec  7 15:48:50 2011
From: ahatanaka at mips.com (Akira Hatanaka)
Date: Wed, 07 Dec 2011 21:48:50 -0000
Subject: [llvm-commits] [llvm] r146080 - in /llvm/trunk:
 lib/Target/Mips/MipsISelLowering.cpp test/CodeGen/Mips/fcopysign.ll
Message-ID: <20111207214850.72A692A6C12C@llvm.org>

Author: ahatanak
Date: Wed Dec  7 15:48:50 2011
New Revision: 146080

URL: http://llvm.org/viewvc/llvm-project?rev=146080&view=rev
Log:
Modify LowerFCOPYSIGN to handle Mips64.


Modified:
    llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp
    llvm/trunk/test/CodeGen/Mips/fcopysign.ll

Modified: llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp?rev=146080&r1=146079&r2=146080&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp Wed Dec  7 15:48:50 2011
@@ -1683,21 +1683,29 @@
                       MachinePointerInfo(SV),
                       false, false, 0);
 }
-
-static SDValue LowerFCOPYSIGN32(SDValue Op, SelectionDAG &DAG) {
+ 
+// Called if the size of integer registers is large enough to hold the whole
+// floating point number.
+static SDValue LowerFCOPYSIGNLargeIntReg(SDValue Op, SelectionDAG &DAG) {
   // FIXME: Use ext/ins instructions if target architecture is Mips32r2.
+  EVT ValTy = Op.getValueType();
+  EVT IntValTy = MVT::getIntegerVT(ValTy.getSizeInBits());
+  uint64_t Mask = (uint64_t)1 << (ValTy.getSizeInBits() - 1);
   DebugLoc dl = Op.getDebugLoc();
-  SDValue Op0 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op.getOperand(0));
-  SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op.getOperand(1));
-  SDValue And0 = DAG.getNode(ISD::AND, dl, MVT::i32, Op0,
-                             DAG.getConstant(0x7fffffff, MVT::i32));
-  SDValue And1 = DAG.getNode(ISD::AND, dl, MVT::i32, Op1,
-                             DAG.getConstant(0x80000000, MVT::i32));
-  SDValue Result = DAG.getNode(ISD::OR, dl, MVT::i32, And0, And1);
-  return DAG.getNode(ISD::BITCAST, dl, MVT::f32, Result);
+  SDValue Op0 = DAG.getNode(ISD::BITCAST, dl, IntValTy, Op.getOperand(0));
+  SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, IntValTy, Op.getOperand(1));
+  SDValue And0 = DAG.getNode(ISD::AND, dl, IntValTy, Op0,
+                             DAG.getConstant(Mask - 1, IntValTy));
+  SDValue And1 = DAG.getNode(ISD::AND, dl, IntValTy, Op1,
+                             DAG.getConstant(Mask, IntValTy));
+  SDValue Result = DAG.getNode(ISD::OR, dl, IntValTy, And0, And1);
+  return DAG.getNode(ISD::BITCAST, dl, ValTy, Result);
 }
 
-static SDValue LowerFCOPYSIGN64(SDValue Op, SelectionDAG &DAG, bool isLittle) {
+// Called if the size of integer registers is not large enough to hold the whole
+// floating point number (e.g. f64 & 32-bit integer register).
+static SDValue
+LowerFCOPYSIGNSmallIntReg(SDValue Op, SelectionDAG &DAG, bool isLittle) {
   // FIXME:
   //  Use ext/ins instructions if target architecture is Mips32r2.
   //  Eliminate redundant mfc1 and mtc1 instructions.
@@ -1732,10 +1740,10 @@
 
   assert(Ty == MVT::f32 || Ty == MVT::f64);
 
-  if (Ty == MVT::f32)
-    return LowerFCOPYSIGN32(Op, DAG);
+  if (Ty == MVT::f32 || HasMips64)
+    return LowerFCOPYSIGNLargeIntReg(Op, DAG);
   else
-    return LowerFCOPYSIGN64(Op, DAG, Subtarget->isLittle());
+    return LowerFCOPYSIGNSmallIntReg(Op, DAG, Subtarget->isLittle());
 }
 
 SDValue MipsTargetLowering::

Modified: llvm/trunk/test/CodeGen/Mips/fcopysign.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/fcopysign.ll?rev=146080&r1=146079&r2=146080&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/fcopysign.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/fcopysign.ll Wed Dec  7 15:48:50 2011
@@ -1,34 +1,42 @@
-; RUN: llc  < %s -march=mipsel | FileCheck %s -check-prefix=CHECK-EL
-; RUN: llc  < %s -march=mips | FileCheck %s -check-prefix=CHECK-EB
+; RUN: llc  < %s -march=mipsel | FileCheck %s -check-prefix=MIPS32-EL
+; RUN: llc  < %s -march=mips | FileCheck %s -check-prefix=MIPS32-EB
+; RUN: llc  < %s -march=mips64el -mcpu=mips64 -mattr=n64 | FileCheck %s -check-prefix=MIPS64
 
 define double @func0(double %d0, double %d1) nounwind readnone {
 entry:
-; CHECK-EL: func0:
-; CHECK-EL: lui $[[T1:[0-9]+]], 32768
-; CHECK-EL: ori $[[MSK1:[0-9]+]], $[[T1]], 0
-; CHECK-EL: mfc1 $[[HI0:[0-9]+]], $f15
-; CHECK-EL: and $[[AND1:[0-9]+]], $[[HI0]], $[[MSK1]]
-; CHECK-EL: lui $[[T0:[0-9]+]], 32767
-; CHECK-EL: ori $[[MSK0:[0-9]+]], $[[T0]], 65535
-; CHECK-EL: mfc1 $[[HI1:[0-9]+]], $f13
-; CHECK-EL: and $[[AND0:[0-9]+]], $[[HI1]], $[[MSK0]]
-; CHECK-EL: or  $[[OR:[0-9]+]], $[[AND0]], $[[AND1]]
-; CHECK-EL: mfc1 $[[LO0:[0-9]+]], $f12
-; CHECK-EL: mtc1 $[[LO0]], $f0
-; CHECK-EL: mtc1 $[[OR]], $f1
+; MIPS32-EL: func0:
+; MIPS32-EL: lui $[[T1:[0-9]+]], 32768
+; MIPS32-EL: ori $[[MSK1:[0-9]+]], $[[T1]], 0
+; MIPS32-EL: mfc1 $[[HI0:[0-9]+]], $f15
+; MIPS32-EL: and $[[AND1:[0-9]+]], $[[HI0]], $[[MSK1]]
+; MIPS32-EL: lui $[[T0:[0-9]+]], 32767
+; MIPS32-EL: ori $[[MSK0:[0-9]+]], $[[T0]], 65535
+; MIPS32-EL: mfc1 $[[HI1:[0-9]+]], $f13
+; MIPS32-EL: and $[[AND0:[0-9]+]], $[[HI1]], $[[MSK0]]
+; MIPS32-EL: or  $[[OR:[0-9]+]], $[[AND0]], $[[AND1]]
+; MIPS32-EL: mfc1 $[[LO0:[0-9]+]], $f12
+; MIPS32-EL: mtc1 $[[LO0]], $f0
+; MIPS32-EL: mtc1 $[[OR]], $f1
 ;
-; CHECK-EB: lui $[[T1:[0-9]+]], 32768
-; CHECK-EB: ori $[[MSK1:[0-9]+]], $[[T1]], 0
-; CHECK-EB: mfc1 $[[HI1:[0-9]+]], $f14
-; CHECK-EB: and $[[AND1:[0-9]+]], $[[HI1]], $[[MSK1]]
-; CHECK-EB: lui $[[T0:[0-9]+]], 32767
-; CHECK-EB: ori $[[MSK0:[0-9]+]], $[[T0]], 65535
-; CHECK-EB: mfc1 $[[HI0:[0-9]+]], $f12
-; CHECK-EB: and $[[AND0:[0-9]+]], $[[HI0]], $[[MSK0]]
-; CHECK-EB: or  $[[OR:[0-9]+]], $[[AND0]], $[[AND1]]
-; CHECK-EB: mfc1 $[[LO0:[0-9]+]], $f13
-; CHECK-EB: mtc1 $[[OR]], $f0
-; CHECK-EB: mtc1 $[[LO0]], $f1
+; MIPS32-EB: lui $[[T1:[0-9]+]], 32768
+; MIPS32-EB: ori $[[MSK1:[0-9]+]], $[[T1]], 0
+; MIPS32-EB: mfc1 $[[HI1:[0-9]+]], $f14
+; MIPS32-EB: and $[[AND1:[0-9]+]], $[[HI1]], $[[MSK1]]
+; MIPS32-EB: lui $[[T0:[0-9]+]], 32767
+; MIPS32-EB: ori $[[MSK0:[0-9]+]], $[[T0]], 65535
+; MIPS32-EB: mfc1 $[[HI0:[0-9]+]], $f12
+; MIPS32-EB: and $[[AND0:[0-9]+]], $[[HI0]], $[[MSK0]]
+; MIPS32-EB: or  $[[OR:[0-9]+]], $[[AND0]], $[[AND1]]
+; MIPS32-EB: mfc1 $[[LO0:[0-9]+]], $f13
+; MIPS32-EB: mtc1 $[[OR]], $f0
+; MIPS32-EB: mtc1 $[[LO0]], $f1
+
+; MIPS64: dmfc1 $[[R0:[0-9]+]], $f13
+; MIPS64: and $[[R1:[0-9]+]], $[[R0]], ${{[0-9]+}}
+; MIPS64: dmfc1 $[[R2:[0-9]+]], $f12
+; MIPS64: and $[[R3:[0-9]+]], $[[R2]], ${{[0-9]+}}
+; MIPS64: or  $[[R4:[0-9]+]], $[[R3]], $[[R1]]
+; MIPS64: dmtc1 $[[R4]], $f0
   %call = tail call double @copysign(double %d0, double %d1) nounwind readnone
   ret double %call
 }
@@ -37,17 +45,17 @@
 
 define float @func1(float %f0, float %f1) nounwind readnone {
 entry:
-; CHECK-EL: func1:
-; CHECK-EL: lui $[[T1:[0-9]+]], 32768
-; CHECK-EL: ori $[[MSK1:[0-9]+]], $[[T1]], 0
-; CHECK-EL: mfc1 $[[ARG1:[0-9]+]], $f14
-; CHECK-EL: and $[[T3:[0-9]+]], $[[ARG1]], $[[MSK1]]
-; CHECK-EL: lui $[[T0:[0-9]+]], 32767
-; CHECK-EL: ori $[[MSK0:[0-9]+]], $[[T0]], 65535
-; CHECK-EL: mfc1 $[[ARG0:[0-9]+]], $f12
-; CHECK-EL: and $[[T2:[0-9]+]], $[[ARG0]], $[[MSK0]]
-; CHECK-EL: or  $[[T4:[0-9]+]], $[[T2]], $[[T3]]
-; CHECK-EL: mtc1 $[[T4]], $f0
+; MIPS32-EL: func1:
+; MIPS32-EL: lui $[[T1:[0-9]+]], 32768
+; MIPS32-EL: ori $[[MSK1:[0-9]+]], $[[T1]], 0
+; MIPS32-EL: mfc1 $[[ARG1:[0-9]+]], $f14
+; MIPS32-EL: and $[[T3:[0-9]+]], $[[ARG1]], $[[MSK1]]
+; MIPS32-EL: lui $[[T0:[0-9]+]], 32767
+; MIPS32-EL: ori $[[MSK0:[0-9]+]], $[[T0]], 65535
+; MIPS32-EL: mfc1 $[[ARG0:[0-9]+]], $f12
+; MIPS32-EL: and $[[T2:[0-9]+]], $[[ARG0]], $[[MSK0]]
+; MIPS32-EL: or  $[[T4:[0-9]+]], $[[T2]], $[[T3]]
+; MIPS32-EL: mtc1 $[[T4]], $f0
   %call = tail call float @copysignf(float %f0, float %f1) nounwind readnone
   ret float %call
 }



From ahatanaka at mips.com  Wed Dec  7 15:54:54 2011
From: ahatanaka at mips.com (Akira Hatanaka)
Date: Wed, 07 Dec 2011 21:54:54 -0000
Subject: [llvm-commits] [llvm] r146081 -
	/llvm/trunk/lib/Target/Mips/MipsInstrInfo.td
Message-ID: <20111207215454.AF3012A6C12C@llvm.org>

Author: ahatanak
Date: Wed Dec  7 15:54:54 2011
New Revision: 146081

URL: http://llvm.org/viewvc/llvm-project?rev=146081&view=rev
Log:
Define base class for WrapperPICPat.


Modified:
    llvm/trunk/lib/Target/Mips/MipsInstrInfo.td

Modified: llvm/trunk/lib/Target/Mips/MipsInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsInstrInfo.td?rev=146081&r1=146080&r2=146081&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsInstrInfo.td (original)
+++ llvm/trunk/lib/Target/Mips/MipsInstrInfo.td Wed Dec  7 15:54:54 2011
@@ -973,15 +973,15 @@
           (ADDiu CPURegs:$hi, tglobaltlsaddr:$lo)>;
 
 // wrapper_pic
-class WrapperPICPat:
+class WrapperPICPat:
       Pat<(MipsWrapperPIC node:$in),
-          (ADDiu GP, node:$in)>;
+          (ADDiuOp GPReg, node:$in)>;
 
-def : WrapperPICPat;
-def : WrapperPICPat;
-def : WrapperPICPat;
-def : WrapperPICPat;
-def : WrapperPICPat;
+def : WrapperPICPat;
+def : WrapperPICPat;
+def : WrapperPICPat;
+def : WrapperPICPat;
+def : WrapperPICPat;
 
 // Mips does not have "not", so we expand our way
 def : Pat<(not CPURegs:$in),



From eli.friedman at gmail.com  Wed Dec  7 16:06:02 2011
From: eli.friedman at gmail.com (Eli Friedman)
Date: Wed, 07 Dec 2011 22:06:02 -0000
Subject: [llvm-commits] [llvm] r146083 -
	/llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
Message-ID: <20111207220602.7670C2A6C12C@llvm.org>

Author: efriedma
Date: Wed Dec  7 16:06:02 2011
New Revision: 146083

URL: http://llvm.org/viewvc/llvm-project?rev=146083&view=rev
Log:
Fix an assertion in the scheduler.  PR11386.  No testcase included because it's rather delicate.


Modified:
    llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp?rev=146083&r1=146082&r2=146083&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp Wed Dec  7 16:06:02 2011
@@ -811,12 +811,11 @@
   for (SUnit::succ_iterator I = SU->Succs.begin(), E = SU->Succs.end();
        I != E; ++I) {
     if (I->isAssignedRegDep()) {
+      if (!LiveRegDefs[I->getReg()])
+        ++NumLiveRegs;
       // This becomes the nearest def. Note that an earlier def may still be
       // pending if this is a two-address node.
       LiveRegDefs[I->getReg()] = SU;
-      if (!LiveRegDefs[I->getReg()]) {
-        ++NumLiveRegs;
-      }
       if (LiveRegGens[I->getReg()] == NULL ||
           I->getSUnit()->getHeight() < LiveRegGens[I->getReg()]->getHeight())
         LiveRegGens[I->getReg()] = I->getSUnit();



From daniel at zuster.org  Wed Dec  7 16:07:03 2011
From: daniel at zuster.org (Daniel Dunbar)
Date: Wed, 07 Dec 2011 22:07:03 -0000
Subject: [llvm-commits] [llvm] r146084 - in /llvm/trunk:
	autoconf/configure.ac configure
Message-ID: <20111207220703.9B0002A6C12C@llvm.org>

Author: ddunbar
Date: Wed Dec  7 16:07:03 2011
New Revision: 146084

URL: http://llvm.org/viewvc/llvm-project?rev=146084&view=rev
Log:
configure: Don't warn about compiler-rt checked out into projects/.

Modified:
    llvm/trunk/autoconf/configure.ac
    llvm/trunk/configure

Modified: llvm/trunk/autoconf/configure.ac
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/autoconf/configure.ac?rev=146084&r1=146083&r2=146084&view=diff
==============================================================================
--- llvm/trunk/autoconf/configure.ac (original)
+++ llvm/trunk/autoconf/configure.ac Wed Dec  7 16:07:03 2011
@@ -114,6 +114,7 @@
       llvm-tv)      AC_CONFIG_SUBDIRS([projects/llvm-tv])   ;;
       safecode)     AC_CONFIG_SUBDIRS([projects/safecode]) ;;
       llvm-kernel)  AC_CONFIG_SUBDIRS([projects/llvm-kernel]) ;;
+      compiler-rt)       ;;
       llvm-gcc)       ;;
       test-suite)     ;;
       llvm-test)      ;;

Modified: llvm/trunk/configure
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/configure?rev=146084&r1=146083&r2=146084&view=diff
==============================================================================
--- llvm/trunk/configure (original)
+++ llvm/trunk/configure Wed Dec  7 16:07:03 2011
@@ -3493,6 +3493,7 @@
  ;;
       llvm-kernel)  subdirs="$subdirs projects/llvm-kernel"
  ;;
+      compiler-rt)       ;;
       llvm-gcc)       ;;
       test-suite)     ;;
       llvm-test)      ;;
@@ -10489,7 +10490,7 @@
   lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2
   lt_status=$lt_dlunknown
   cat > conftest.$ac_ext <

Author: ahatanak
Date: Wed Dec  7 16:11:43 2011
New Revision: 146086

URL: http://llvm.org/viewvc/llvm-project?rev=146086&view=rev
Log:
64-bit WrapperPICPat patterns.


Modified:
    llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td
    llvm/trunk/test/CodeGen/Mips/cmov.ll

Modified: llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td?rev=146086&r1=146085&r2=146086&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td (original)
+++ llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td Wed Dec  7 16:11:43 2011
@@ -273,6 +273,12 @@
 def : Pat<(add CPU64Regs:$hi, (MipsLo tconstpool:$lo)),
           (DADDiu CPU64Regs:$hi, tconstpool:$lo)>;
 
+def : WrapperPICPat;
+def : WrapperPICPat;
+def : WrapperPICPat;
+def : WrapperPICPat;
+def : WrapperPICPat;
+
 defm : BrcondPats;
 

Modified: llvm/trunk/test/CodeGen/Mips/cmov.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/cmov.ll?rev=146086&r1=146085&r2=146086&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/cmov.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/cmov.ll Wed Dec  7 16:11:43 2011
@@ -1,11 +1,14 @@
-; RUN: llc -march=mips < %s | FileCheck %s
-; RUN: llc -march=mips -regalloc=basic < %s | FileCheck %s
+; RUN: llc -march=mips < %s | FileCheck %s -check-prefix=O32
+; RUN: llc -march=mips -regalloc=basic < %s | FileCheck %s -check-prefix=O32
+; RUN: llc -march=mips64el -mcpu=mips64 -mattr=n64 < %s | FileCheck %s -check-prefix=N64
 
 @i1 = global [3 x i32] [i32 1, i32 2, i32 3], align 4
 @i3 = common global i32* null, align 4
 
-; CHECK:  lw  ${{[0-9]+}}, %got(i3)($gp)
-; CHECK:  addiu ${{[0-9]+}}, $gp, %got(i1)
+; O32:  lw  ${{[0-9]+}}, %got(i3)($gp)
+; O32:  addiu ${{[0-9]+}}, $gp, %got(i1)
+; N64:  ld  ${{[0-9]+}}, %got_disp(i3)($gp)
+; N64:  daddiu ${{[0-9]+}}, $gp, %got_disp(i1)
 define i32* @cmov1(i32 %s) nounwind readonly {
 entry:
   %tobool = icmp ne i32 %s, 0
@@ -17,10 +20,14 @@
 @c = global i32 1, align 4
 @d = global i32 0, align 4
 
-; CHECK: cmov2:
-; CHECK: addiu $[[R1:[0-9]+]], $gp, %got(d)
-; CHECK: addiu $[[R0:[0-9]+]], $gp, %got(c)
-; CHECK: movn  $[[R1]], $[[R0]], ${{[0-9]+}}
+; O32: cmov2:
+; O32: addiu $[[R1:[0-9]+]], $gp, %got(d)
+; O32: addiu $[[R0:[0-9]+]], $gp, %got(c)
+; O32: movn  $[[R1]], $[[R0]], ${{[0-9]+}}
+; N64: cmov2:
+; N64: daddiu $[[R1:[0-9]+]], $gp, %got_disp(d)
+; N64: daddiu $[[R0:[0-9]+]], $gp, %got_disp(c)
+; N64: movn  $[[R1]], $[[R0]], ${{[0-9]+}}
 define i32 @cmov2(i32 %s) nounwind readonly {
 entry:
   %tobool = icmp ne i32 %s, 0



From eli.friedman at gmail.com  Wed Dec  7 16:24:28 2011
From: eli.friedman at gmail.com (Eli Friedman)
Date: Wed, 07 Dec 2011 22:24:28 -0000
Subject: [llvm-commits] [llvm] r146087 -
	/llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
Message-ID: <20111207222428.597D02A6C12C@llvm.org>

Author: efriedma
Date: Wed Dec  7 16:24:28 2011
New Revision: 146087

URL: http://llvm.org/viewvc/llvm-project?rev=146087&view=rev
Log:
Make sure we correctly set LiveRegGens when a call is unscheduled.  .  No testcase because this is very sensitive to scheduling.


Modified:
    llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp?rev=146087&r1=146086&r2=146087&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp Wed Dec  7 16:24:28 2011
@@ -146,6 +146,10 @@
   /// and similar queries.
   ScheduleDAGTopologicalSort Topo;
 
+  // Hack to keep track of the inverse of FindCallSeqStart without more crazy
+  // DAG crawling.
+  DenseMap CallSeqEndForStart;
+
 public:
   ScheduleDAGRRList(MachineFunction &mf, bool needlatency,
                     SchedulingPriorityQueue *availqueue,
@@ -306,6 +310,7 @@
   // to track the virtual resource of a calling sequence.
   LiveRegDefs.resize(TRI->getNumRegs() + 1, NULL);
   LiveRegGens.resize(TRI->getNumRegs() + 1, NULL);
+  CallSeqEndForStart.clear();
 
   // Build the scheduling graph.
   BuildSchedGraph(NULL);
@@ -524,6 +529,8 @@
         SDNode *N = FindCallSeqStart(Node, NestLevel, MaxNest, TII);
 
         SUnit *Def = &SUnits[N->getNodeId()];
+        CallSeqEndForStart[Def] = SU;
+
         ++NumLiveRegs;
         LiveRegDefs[CallResource] = Def;
         LiveRegGens[CallResource] = SU;
@@ -790,7 +797,7 @@
         SUNode->getMachineOpcode() == (unsigned)TII->getCallFrameSetupOpcode()) {
       ++NumLiveRegs;
       LiveRegDefs[CallResource] = SU;
-      LiveRegGens[CallResource] = NULL;
+      LiveRegGens[CallResource] = CallSeqEndForStart[SU];
     }
   }
 



From bruno.cardoso at gmail.com  Wed Dec  7 16:36:28 2011
From: bruno.cardoso at gmail.com (Bruno Cardoso Lopes)
Date: Wed, 7 Dec 2011 20:36:28 -0200
Subject: [llvm-commits] [llvm] r145911 - in /llvm/trunk/lib/MC:
 ELFObjectWriter.cpp ELFObjectWriter.h
In-Reply-To: <4EDEB7A2.5070108@gmail.com>
References: <20111206033442.E04352A6C12C@llvm.org> <4EDEB7A2.5070108@gmail.com>
Message-ID: 

Hi Rafael,

2011/12/6 Rafael ?vila de Esp?ndola :
> On 05/12/11 10:34 PM, Bruno Cardoso Lopes wrote:
>> Author: bruno
>> Date: Mon Dec ?5 21:34:42 2011
>> New Revision: 145911
>>
>> URL: http://llvm.org/viewvc/llvm-project?rev=145911&view=rev
>> Log:
>> Explicit symbols for gnu mimicing relocations. Patch by Jack Carter
>>
>
> testcase?

Jack should provide a testcase soon! Thanks for noticing!

-- 
Bruno Cardoso Lopes
http://www.brunocardoso.cc


From bruno.cardoso at gmail.com  Wed Dec  7 16:35:30 2011
From: bruno.cardoso at gmail.com (Bruno Cardoso Lopes)
Date: Wed, 07 Dec 2011 22:35:30 -0000
Subject: [llvm-commits] [llvm] r146088 - in
 /llvm/trunk/lib/Target/Mips/MCTargetDesc: MipsFixupKinds.h
 MipsMCCodeEmitter.cpp
Message-ID: <20111207223530.945F62A6C12C@llvm.org>

Author: bruno
Date: Wed Dec  7 16:35:30 2011
New Revision: 146088

URL: http://llvm.org/viewvc/llvm-project?rev=146088&view=rev
Log:
Variable cleanup. Based on past patch submittals variable names have
been normalized and more descriptive comments added. Patch by Reed
Kotler and Jack Carter.

Modified:
    llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsFixupKinds.h
    llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp

Modified: llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsFixupKinds.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsFixupKinds.h?rev=146088&r1=146087&r2=146088&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsFixupKinds.h (original)
+++ llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsFixupKinds.h Wed Dec  7 16:35:30 2011
@@ -14,77 +14,82 @@
 
 namespace llvm {
 namespace Mips {
-    enum Fixups {
-        // fixup_Mips_xxx - R_MIPS_NONE
-        fixup_Mips_NONE = FirstTargetFixupKind,
+  // Although most of the current fixup types reflect a unique relocation
+  // one can have multiple fixup types for a given relocation and thus need
+  // to be uniquely named.
+  //
+  // This table *must* be in the save order of
+  // MCFixupKindInfo Infos[Mips::NumTargetFixupKinds]
+  // in MipsAsmBackend.cpp.
+  //
+  enum Fixups {
+    // Branch fixups resulting in R_MIPS_16.
+    fixup_Mips_16 = FirstTargetFixupKind,
 
-        // fixup_Mips_xxx - R_MIPS_16.
-        fixup_Mips_16,
+    // Pure 32 bit data fixup resulting in - R_MIPS_32.
+    fixup_Mips_32,
 
-        // fixup_Mips_xxx - R_MIPS_32.
-        fixup_Mips_32,
+    // Full 32 bit data relative data fixup resulting in - R_MIPS_REL32.
+    fixup_Mips_REL32,
 
-        // fixup_Mips_xxx - R_MIPS_REL32.
-        fixup_Mips_REL32,
+    // Jump 26 bit fixup resulting in - R_MIPS_26.
+    fixup_Mips_26,
 
-        // fixup_Mips_xxx - R_MIPS_26.
-        fixup_Mips_26,
+    // Pure upper 16 bit fixup resulting in - R_MIPS_HI16.
+    fixup_Mips_HI16,
 
-        // fixup_Mips_xxx - R_MIPS_HI16.
-        fixup_Mips_HI16,
+    // Pure lower 16 bit fixup resulting in - R_MIPS_LO16.
+    fixup_Mips_LO16,
 
-        // fixup_Mips_xxx - R_MIPS_LO16.
-        fixup_Mips_LO16,
+    // 16 bit fixup for GP offest resulting in - R_MIPS_GPREL16.
+    fixup_Mips_GPREL16,
 
-        // fixup_Mips_xxx - R_MIPS_GPREL16.
-        fixup_Mips_GPREL16,
+    // 16 bit literal fixup resulting in - R_MIPS_LITERAL.
+    fixup_Mips_LITERAL,
 
-        // fixup_Mips_xxx - R_MIPS_LITERAL.
-        fixup_Mips_LITERAL,
+    // Global symbol fixup resulting in - R_MIPS_GOT16.
+    fixup_Mips_GOT_Global,
 
-        // Global symbol fixup resulting in - R_MIPS_GOT16.
-        fixup_Mips_GOT_Global,
+    // Local symbol fixup resulting in - R_MIPS_GOT16.
+    fixup_Mips_GOT_Local,
 
-        // Local symbol fixup resulting in - R_MIPS_GOT16.
-        fixup_Mips_GOT_Local,
+    // PC relative branch fixup resulting in - R_MIPS_PC16.
+    fixup_Mips_PC16,
 
-        // fixup_Mips_xxx - R_MIPS_PC16.
-        fixup_Mips_PC16,
+    // resulting in - R_MIPS_CALL16.
+    fixup_Mips_CALL16,
 
-        // fixup_Mips_xxx - R_MIPS_CALL16.
-        fixup_Mips_CALL16,
+    // resulting in - R_MIPS_GPREL32.
+    fixup_Mips_GPREL32,
 
-        // fixup_Mips_xxx - R_MIPS_GPREL32.
-        fixup_Mips_GPREL32,
+    // resulting in - R_MIPS_SHIFT5.
+    fixup_Mips_SHIFT5,
 
-        // fixup_Mips_xxx - R_MIPS_SHIFT5.
-        fixup_Mips_SHIFT5,
+    // resulting in - R_MIPS_SHIFT6.
+    fixup_Mips_SHIFT6,
 
-        // fixup_Mips_xxx - R_MIPS_SHIFT6.
-        fixup_Mips_SHIFT6,
+    // Pure 64 bit data fixup resulting in - R_MIPS_64.
+    fixup_Mips_64,
 
-        // fixup_Mips_xxx - R_MIPS_64.
-        fixup_Mips_64,
+    // resulting in - R_MIPS_TLS_GD.
+    fixup_Mips_TLSGD,
 
-        // fixup_Mips_xxx - R_MIPS_TLS_GD.
-        fixup_Mips_TLSGD,
+    // resulting in - R_MIPS_TLS_GOTTPREL.
+    fixup_Mips_GOTTPREL,
 
-        // fixup_Mips_xxx - R_MIPS_TLS_GOTTPREL.
-        fixup_Mips_GOTTPREL,
+    // resulting in - R_MIPS_TLS_TPREL_HI16.
+    fixup_Mips_TPREL_HI,
 
-        // fixup_Mips_xxx - R_MIPS_TLS_TPREL_HI16.
-        fixup_Mips_TPREL_HI,
+    // resulting in - R_MIPS_TLS_TPREL_LO16.
+    fixup_Mips_TPREL_LO,
 
-        // fixup_Mips_xxx - R_MIPS_TLS_TPREL_LO16.
-        fixup_Mips_TPREL_LO,
+    // PC relative branch fixup resulting in - R_MIPS_PC16
+    fixup_Mips_Branch_PCRel,
 
-        // fixup_Mips_xxx - yyy. // This should become R_MIPS_PC16
-        fixup_Mips_Branch_PCRel,
-
-        // Marker
-        LastTargetFixupKind,
-        NumTargetFixupKinds = LastTargetFixupKind - FirstTargetFixupKind
-    };
+    // Marker
+    LastTargetFixupKind,
+    NumTargetFixupKinds = LastTargetFixupKind - FirstTargetFixupKind
+  };
 } // namespace Mips
 } // namespace llvm
 

Modified: llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp?rev=146088&r1=146087&r2=146088&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp (original)
+++ llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp Wed Dec  7 16:35:30 2011
@@ -248,8 +248,8 @@
 MipsMCCodeEmitter::getSizeExtEncoding(const MCInst &MI, unsigned OpNo,
                                       SmallVectorImpl &Fixups) const {
   assert(MI.getOperand(OpNo).isImm());
-  unsigned szEncoding = getMachineOpValue(MI, MI.getOperand(OpNo), Fixups);
-  return szEncoding - 1;
+  unsigned SizeEncoding = getMachineOpValue(MI, MI.getOperand(OpNo), Fixups);
+  return SizeEncoding - 1;
 }
 
 // FIXME: should be called getMSBEncoding
@@ -259,10 +259,10 @@
                                       SmallVectorImpl &Fixups) const {
   assert(MI.getOperand(OpNo-1).isImm());
   assert(MI.getOperand(OpNo).isImm());
-  unsigned pos = getMachineOpValue(MI, MI.getOperand(OpNo-1), Fixups);
-  unsigned sz = getMachineOpValue(MI, MI.getOperand(OpNo), Fixups);
+  unsigned Position = getMachineOpValue(MI, MI.getOperand(OpNo-1), Fixups);
+  unsigned Size = getMachineOpValue(MI, MI.getOperand(OpNo), Fixups);
 
-  return pos + sz - 1;
+  return Position + Size - 1;
 }
 
 #include "MipsGenMCCodeEmitter.inc"



From mcrosier at apple.com  Wed Dec  7 16:49:05 2011
From: mcrosier at apple.com (Chad Rosier)
Date: Wed, 07 Dec 2011 22:49:05 -0000
Subject: [llvm-commits] [llvm] r146090 -
	/llvm/trunk/lib/Bitcode/Writer/BitcodeWriter.cpp
Message-ID: <20111207224905.F0EF02A6C12C@llvm.org>

Author: mcrosier
Date: Wed Dec  7 16:49:05 2011
New Revision: 146090

URL: http://llvm.org/viewvc/llvm-project?rev=146090&view=rev
Log:
Flesh out a bit more of the bitcode use-list ordering preservation code.
Nothing too interesting at this point, but comments are welcome.
Part of rdar://9860654 and PR5680.

Modified:
    llvm/trunk/lib/Bitcode/Writer/BitcodeWriter.cpp

Modified: llvm/trunk/lib/Bitcode/Writer/BitcodeWriter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Bitcode/Writer/BitcodeWriter.cpp?rev=146090&r1=146089&r2=146090&view=diff
==============================================================================
--- llvm/trunk/lib/Bitcode/Writer/BitcodeWriter.cpp (original)
+++ llvm/trunk/lib/Bitcode/Writer/BitcodeWriter.cpp Wed Dec  7 16:49:05 2011
@@ -1578,17 +1578,99 @@
   Stream.ExitBlock();
 }
 
+// Sort the Users based on the order in which the reader parses the bitcode 
+// file.
+static bool bitcodereader_order(const User *lhs, const User *rhs) {
+  // TODO: Implement.
+  return true;
+}
+
+static void WriteUseList(const Value *V, const ValueEnumerator &VE,
+                         BitstreamWriter &Stream) {
+
+  // One or zero uses can't get out of order.
+  if (V->use_empty() || V->hasNUses(1))
+    return;
+
+  // Make a copy of the in-memory use-list for sorting.
+  unsigned UseListSize = std::distance(V->use_begin(), V->use_end());
+  SmallVector UseList;
+  UseList.reserve(UseListSize);
+  for (Value::const_use_iterator I = V->use_begin(), E = V->use_end();
+       I != E; ++I) {
+    const User *U = *I;
+    UseList.push_back(U);
+  }
+
+  // Sort the copy based on the order read by the BitcodeReader.
+  std::sort(UseList.begin(), UseList.end(), bitcodereader_order);
+
+  // TODO: Generate a diff between the BitcodeWriter in-memory use-list and the
+  // sorted list (i.e., the expected BitcodeReader in-memory use-list).
+
+  // TODO: Emit the USELIST_CODE_ENTRYs.
+}
+
+static void WriteFunctionUseList(const Function *F, ValueEnumerator &VE,
+                                 BitstreamWriter &Stream) {
+  VE.incorporateFunction(*F);
+
+  for (Function::const_arg_iterator AI = F->arg_begin(), AE = F->arg_end();
+       AI != AE; ++AI)
+    WriteUseList(AI, VE, Stream);
+  for (Function::const_iterator BB = F->begin(), FE = F->end(); BB != FE;
+       ++BB) {
+    WriteUseList(BB, VE, Stream);
+    for (BasicBlock::const_iterator II = BB->begin(), IE = BB->end(); II != IE;
+         ++II) {
+      WriteUseList(II, VE, Stream);
+      for (User::const_op_iterator OI = II->op_begin(), E = II->op_end();
+           OI != E; ++OI) {
+        if ((isa(*OI) && !isa(*OI)) ||
+            isa(*OI))
+          WriteUseList(*OI, VE, Stream);
+      }
+    }
+  }
+  VE.purgeFunction();
+}
+
 // Emit use-lists.
 static void WriteModuleUseLists(const Module *M, ValueEnumerator &VE,
                                 BitstreamWriter &Stream) {
   Stream.EnterSubblock(bitc::USELIST_BLOCK_ID, 3);
 
-  // Emit a bogus record for testing purposes.
-  SmallVector Record;
-  Record.push_back(0);
-  Stream.EmitRecord(bitc::USELIST_CODE_ENTRY, Record);
+  // XXX: this modifies the module, but in a way that should never change the
+  // behavior of any pass or codegen in LLVM. The problem is that GVs may
+  // contain entries in the use_list that do not exist in the Module and are
+  // not stored in the .bc file.
+  for (Module::const_global_iterator I = M->global_begin(), E = M->global_end();
+       I != E; ++I)
+    I->removeDeadConstantUsers();
+  
+  // Write the global variables.
+  for (Module::const_global_iterator GI = M->global_begin(), 
+         GE = M->global_end(); GI != GE; ++GI) {
+    WriteUseList(GI, VE, Stream);
+
+    // Write the global variable initializers.
+    if (GI->hasInitializer())
+      WriteUseList(GI->getInitializer(), VE, Stream);
+  }
+
+  // Write the functions.
+  for (Module::const_iterator FI = M->begin(), FE = M->end(); FI != FE; ++FI) {
+    WriteUseList(FI, VE, Stream);
+    if (!FI->isDeclaration())
+      WriteFunctionUseList(FI, VE, Stream);
+  }
 
-  // TODO: Tons.
+  // Write the aliases.
+  for (Module::const_alias_iterator AI = M->alias_begin(), AE = M->alias_end();
+       AI != AE; ++AI) {
+    WriteUseList(AI, VE, Stream);
+    WriteUseList(AI->getAliasee(), VE, Stream);
+  }
 
   Stream.ExitBlock();
 }



From grosbach at apple.com  Wed Dec  7 16:52:54 2011
From: grosbach at apple.com (Jim Grosbach)
Date: Wed, 07 Dec 2011 22:52:54 -0000
Subject: [llvm-commits] [llvm] r146091 - in /llvm/trunk:
 lib/Target/ARM/ARMInstrNEON.td test/MC/ARM/neon-add-encoding.s
Message-ID: <20111207225254.9273E2A6C12C@llvm.org>

Author: grosbach
Date: Wed Dec  7 16:52:54 2011
New Revision: 146091

URL: http://llvm.org/viewvc/llvm-project?rev=146091&view=rev
Log:
ARM two-operand aliases for VADD instructions.

Modified:
    llvm/trunk/lib/Target/ARM/ARMInstrNEON.td
    llvm/trunk/test/MC/ARM/neon-add-encoding.s

Modified: llvm/trunk/lib/Target/ARM/ARMInstrNEON.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrNEON.td?rev=146091&r1=146090&r2=146091&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrNEON.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrNEON.td Wed Dec  7 16:52:54 2011
@@ -5297,6 +5297,30 @@
 // Assembler aliases
 //
 
+// VADD two-operand aliases.
+def : NEONInstAlias<"vadd${p}.i8 $Vdn, $Vm",
+                    (VADDv16i8 QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>;
+def : NEONInstAlias<"vadd${p}.i16 $Vdn, $Vm",
+                    (VADDv8i16 QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>;
+def : NEONInstAlias<"vadd${p}.i32 $Vdn, $Vm",
+                    (VADDv4i32 QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>;
+def : NEONInstAlias<"vadd${p}.i64 $Vdn, $Vm",
+                    (VADDv2i64 QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>;
+
+def : NEONInstAlias<"vadd${p}.i8 $Vdn, $Vm",
+                    (VADDv8i8 DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;
+def : NEONInstAlias<"vadd${p}.i16 $Vdn, $Vm",
+                    (VADDv4i16 DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;
+def : NEONInstAlias<"vadd${p}.i32 $Vdn, $Vm",
+                    (VADDv2i32 DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;
+def : NEONInstAlias<"vadd${p}.i64 $Vdn, $Vm",
+                    (VADDv1i64 DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;
+
+def : NEONInstAlias<"vadd${p}.f32 $Vdn, $Vm",
+                    (VADDfd DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;
+def : NEONInstAlias<"vadd${p}.f32 $Vdn, $Vm",
+                    (VADDfq QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>;
+
 // VAND/VEOR/VORR accept but do not require a type suffix.
 defm : VFPDTAnyInstAlias<"vand${p}", "$Vd, $Vn, $Vm",
                          (VANDd DPR:$Vd, DPR:$Vn, DPR:$Vm, pred:$p)>;

Modified: llvm/trunk/test/MC/ARM/neon-add-encoding.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/neon-add-encoding.s?rev=146091&r1=146090&r2=146091&view=diff
==============================================================================
--- llvm/trunk/test/MC/ARM/neon-add-encoding.s (original)
+++ llvm/trunk/test/MC/ARM/neon-add-encoding.s Wed Dec  7 16:52:54 2011
@@ -135,3 +135,26 @@
 	vraddhn.i32	d16, q8, q9
 @ CHECK: vraddhn.i64	d16, q8, q9     @ encoding: [0xa2,0x04,0xe0,0xf3]
 	vraddhn.i64	d16, q8, q9
+
+
+@ Two-operand variants
+
+	vadd.i8  d6, d5
+	vadd.i16 d7, d1
+	vadd.i32 d8, d2
+	vadd.i64 d9, d3
+
+	vadd.i8  q6, q5
+	vadd.i16 q7, q1
+	vadd.i32 q8, q2
+	vadd.i64 q9, q3
+
+@ CHECK: vadd.i8	d6, d6, d5      @ encoding: [0x05,0x68,0x06,0xf2]
+@ CHECK: vadd.i16	d7, d7, d1      @ encoding: [0x01,0x78,0x17,0xf2]
+@ CHECK: vadd.i32	d8, d8, d2      @ encoding: [0x02,0x88,0x28,0xf2]
+@ CHECK: vadd.i64	d9, d9, d3      @ encoding: [0x03,0x98,0x39,0xf2]
+
+@ CHECK: vadd.i8	q6, q6, q5      @ encoding: [0x4a,0xc8,0x0c,0xf2]
+@ CHECK: vadd.i16	q7, q7, q1      @ encoding: [0x42,0xe8,0x1e,0xf2]
+@ CHECK: vadd.i32	q8, q8, q2      @ encoding: [0xc4,0x08,0x60,0xf2]
+@ CHECK: vadd.i64	q9, q9, q3      @ encoding: [0xc6,0x28,0x72,0xf2]



From tonic at nondot.org  Wed Dec  7 16:53:13 2011
From: tonic at nondot.org (Tanya Lattner)
Date: Wed, 07 Dec 2011 22:53:13 -0000
Subject: [llvm-commits] [www] r146092 - /www/trunk/devmtg/2011-11/index.html
Message-ID: <20111207225313.1BC3C2A6C12C@llvm.org>

Author: tbrethou
Date: Wed Dec  7 16:53:12 2011
New Revision: 146092

URL: http://llvm.org/viewvc/llvm-project?rev=146092&view=rev
Log:
Additional information.

Modified:
    www/trunk/devmtg/2011-11/index.html

Modified: www/trunk/devmtg/2011-11/index.html
URL: http://llvm.org/viewvc/llvm-project/www/trunk/devmtg/2011-11/index.html?rev=146092&r1=146091&r2=146092&view=diff
==============================================================================
--- www/trunk/devmtg/2011-11/index.html (original)
+++ www/trunk/devmtg/2011-11/index.html Wed Dec  7 16:53:12 2011
@@ -43,7 +43,7 @@
 
         
 
 
        Agenda
        
-
+Yes, the slides and video links do not work! Adding them shortly.
 
        
 
 



From bruno.cardoso at gmail.com  Wed Dec  7 16:57:18 2011
From: bruno.cardoso at gmail.com (Bruno Cardoso Lopes)
Date: Wed, 7 Dec 2011 20:57:18 -0200
Subject: [llvm-commits] FMA4 cleanup patch
In-Reply-To: <1323273015.33804.YahooMailNeo@web161505.mail.bf1.yahoo.com>
References: <1323273015.33804.YahooMailNeo@web161505.mail.bf1.yahoo.com>
Message-ID: 

LGTM! Can you add testcases?

On Wed, Dec 7, 2011 at 1:50 PM, Jan Sjodin  wrote:
> Patch to clean up the FMA4 encoding. I had accidentally swapped the operands
> in the asm strings for the FMA4 rr patterns, which caused some confusion.
> Ok to commit?
>
> - Jan



-- 
Bruno Cardoso Lopes
http://www.brunocardoso.cc

From grosbach at apple.com  Wed Dec  7 17:01:11 2011
From: grosbach at apple.com (Jim Grosbach)
Date: Wed, 07 Dec 2011 23:01:11 -0000
Subject: [llvm-commits] [llvm] r146093 - in /llvm/trunk:
 lib/Target/ARM/ARMInstrNEON.td test/MC/ARM/neon-add-encoding.s
Message-ID: <20111207230111.46E9F2A6C12C@llvm.org>

Author: grosbach
Date: Wed Dec  7 17:01:10 2011
New Revision: 146093

URL: http://llvm.org/viewvc/llvm-project?rev=146093&view=rev
Log:
ARM two-operand aliases for VADDW instructions.

Modified:
    llvm/trunk/lib/Target/ARM/ARMInstrNEON.td
    llvm/trunk/test/MC/ARM/neon-add-encoding.s

Modified: llvm/trunk/lib/Target/ARM/ARMInstrNEON.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrNEON.td?rev=146093&r1=146092&r2=146093&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrNEON.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrNEON.td Wed Dec  7 17:01:10 2011
@@ -5321,6 +5321,20 @@
 def : NEONInstAlias<"vadd${p}.f32 $Vdn, $Vm",
                     (VADDfq QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>;
 
+// VADDW two-operand aliases.
+def : NEONInstAlias<"vaddw${p}.s8 $Vdn, $Vm",
+                    (VADDWsv8i16 QPR:$Vdn, QPR:$Vdn, DPR:$Vm, pred:$p)>;
+def : NEONInstAlias<"vaddw${p}.s16 $Vdn, $Vm",
+                    (VADDWsv4i32 QPR:$Vdn, QPR:$Vdn, DPR:$Vm, pred:$p)>;
+def : NEONInstAlias<"vaddw${p}.s32 $Vdn, $Vm",
+                    (VADDWsv2i64 QPR:$Vdn, QPR:$Vdn, DPR:$Vm, pred:$p)>;
+def : NEONInstAlias<"vaddw${p}.u8 $Vdn, $Vm",
+                    (VADDWuv8i16 QPR:$Vdn, QPR:$Vdn, DPR:$Vm, pred:$p)>;
+def : NEONInstAlias<"vaddw${p}.u16 $Vdn, $Vm",
+                    (VADDWuv4i32 QPR:$Vdn, QPR:$Vdn, DPR:$Vm, pred:$p)>;
+def : NEONInstAlias<"vaddw${p}.u32 $Vdn, $Vm",
+                    (VADDWuv2i64 QPR:$Vdn, QPR:$Vdn, DPR:$Vm, pred:$p)>;
+
 // VAND/VEOR/VORR accept but do not require a type suffix.
 defm : VFPDTAnyInstAlias<"vand${p}", "$Vd, $Vn, $Vm",
                          (VANDd DPR:$Vd, DPR:$Vn, DPR:$Vm, pred:$p)>;

Modified: llvm/trunk/test/MC/ARM/neon-add-encoding.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/neon-add-encoding.s?rev=146093&r1=146092&r2=146093&view=diff
==============================================================================
--- llvm/trunk/test/MC/ARM/neon-add-encoding.s (original)
+++ llvm/trunk/test/MC/ARM/neon-add-encoding.s Wed Dec  7 17:01:10 2011
@@ -158,3 +158,20 @@
 @ CHECK: vadd.i16	q7, q7, q1      @ encoding: [0x42,0xe8,0x1e,0xf2]
 @ CHECK: vadd.i32	q8, q8, q2      @ encoding: [0xc4,0x08,0x60,0xf2]
 @ CHECK: vadd.i64	q9, q9, q3      @ encoding: [0xc6,0x28,0x72,0xf2]
+
+
+	vaddw.s8  q6, d5
+	vaddw.s16 q7, d1
+	vaddw.s32 q8, d2
+
+	vaddw.u8  q6, d5
+	vaddw.u16 q7, d1
+	vaddw.u32 q8, d2
+
+@ CHECK: vaddw.s8	q6, q6, d5      @ encoding: [0x05,0xc1,0x8c,0xf2]
+@ CHECK: vaddw.s16	q7, q7, d1      @ encoding: [0x01,0xe1,0x9e,0xf2]
+@ CHECK: vaddw.s32	q8, q8, d2      @ encoding: [0x82,0x01,0xe0,0xf2]
+
+@ CHECK: vaddw.u8	q6, q6, d5      @ encoding: [0x05,0xc1,0x8c,0xf3]
+@ CHECK: vaddw.u16	q7, q7, d1      @ encoding: [0x01,0xe1,0x9e,0xf3]
+@ CHECK: vaddw.u32	q8, q8, d2      @ encoding: [0x82,0x01,0xe0,0xf3]



From bruno.cardoso at gmail.com  Wed Dec  7 17:05:55 2011
From: bruno.cardoso at gmail.com (Bruno Cardoso Lopes)
Date: Wed, 7 Dec 2011 21:05:55 -0200
Subject: [llvm-commits] [llvm] r146031 -
	/llvm/trunk/lib/Target/X86/X86InstrSSE.td
In-Reply-To: <20111207083054.2671F1BE003@llvm.org>
References: <20111207083054.2671F1BE003@llvm.org>
Message-ID: 

Testcase?

On Wed, Dec 7, 2011 at 6:30 AM, Craig Topper  wrote:
> Author: ctopper
> Date: Wed Dec ?7 02:30:53 2011
> New Revision: 146031
>
> URL: http://llvm.org/viewvc/llvm-project?rev=146031&view=rev
> Log:
> Fix a bunch of SSE/AVX patterns to use proper memop types. In particular, not using integer loads other than v2i64/v4i64 since the others are all promoted.
>
> Modified:
> ? ?llvm/trunk/lib/Target/X86/X86InstrSSE.td
>
> Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrSSE.td?rev=146031&r1=146030&r2=146031&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/X86/X86InstrSSE.td (original)
> +++ llvm/trunk/lib/Target/X86/X86InstrSSE.td Wed Dec ?7 02:30:53 2011
> @@ -1944,7 +1944,7 @@
> ?// whenever possible to avoid declaring two versions of each one.
> ?def : Pat<(int_x86_avx_cvtdq2_ps_256 VR256:$src),
> ? ? ? ? ? (VCVTDQ2PSYrr VR256:$src)>;
> -def : Pat<(int_x86_avx_cvtdq2_ps_256 (memopv8i32 addr:$src)),
> +def : Pat<(int_x86_avx_cvtdq2_ps_256 (bitconvert (memopv4i64 addr:$src))),
> ? ? ? ? ? (VCVTDQ2PSYrm addr:$src)>;
>
> ?def : Pat<(int_x86_avx_cvt_pd2_ps_256 VR256:$src),
> @@ -3637,6 +3637,8 @@
> ? ? ? ? ? ? ? ? ? ? ? ? ? i128mem, 1, 0>, VEX_4V;
> ?defm VPXOR : PDI_binop_rm<0xEF, "vpxor", xor, v2i64, VR128, memopv2i64,
> ? ? ? ? ? ? ? ? ? ? ? ? ? i128mem, 1, 0>, VEX_4V;
> +defm VPANDN : PDI_binop_rm<0xDF, "vpandn", X86andnp, v2i64, VR128, memopv2i64,
> + ? ? ? ? ? ? ? ? ? ? ? ? ?i128mem, 0, 0>, VEX_4V;
>
> ?let ExeDomain = SSEPackedInt in {
> ? let neverHasSideEffects = 1 in {
> @@ -3651,17 +3653,6 @@
> ? ? ? ? ? ? ? ? ? ? ? VEX_4V;
> ? ? // PSRADQri doesn't exist in SSE[1-3].
> ? }
> - ?def VPANDNrr : PDI<0xDF, MRMSrcReg,
> - ? ? ? ? ? ? ? ? ? ?(outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
> - ? ? ? ? ? ? ? ? ? ?"vpandn\t{$src2, $src1, $dst|$dst, $src1, $src2}",
> - ? ? ? ? ? ? ? ? ? ?[(set VR128:$dst,
> - ? ? ? ? ? ? ? ? ? ? ? ? ?(v2i64 (X86andnp VR128:$src1, VR128:$src2)))]>,VEX_4V;
> -
> - ?def VPANDNrm : PDI<0xDF, MRMSrcMem,
> - ? ? ? ? ? ? ? ? ? ?(outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
> - ? ? ? ? ? ? ? ? ? ?"vpandn\t{$src2, $src1, $dst|$dst, $src1, $src2}",
> - ? ? ? ? ? ? ? ? ? ?[(set VR128:$dst, (X86andnp VR128:$src1,
> - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?(memopv2i64 addr:$src2)))]>, VEX_4V;
> ?}
> ?}
>
> @@ -3699,6 +3690,8 @@
> ? ? ? ? ? ? ? ? ? ? ? ? ? ?i256mem, 1, 0>, VEX_4V;
> ?defm VPXORY : PDI_binop_rm<0xEF, "vpxor", xor, v4i64, VR256, memopv4i64,
> ? ? ? ? ? ? ? ? ? ? ? ? ? ?i256mem, 1, 0>, VEX_4V;
> +defm VPANDNY : PDI_binop_rm<0xDF, "vpandn", X86andnp, v4i64, VR256, memopv4i64,
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ?i256mem, 0, 0>, VEX_4V;
>
> ?let ExeDomain = SSEPackedInt in {
> ? let neverHasSideEffects = 1 in {
> @@ -3713,17 +3706,6 @@
> ? ? ? ? ? ? ? ? ? ? ? VEX_4V;
> ? ? // PSRADQYri doesn't exist in SSE[1-3].
> ? }
> - ?def VPANDNYrr : PDI<0xDF, MRMSrcReg,
> - ? ? ? ? ? ? ? ? ? ? (outs VR256:$dst), (ins VR256:$src1, VR256:$src2),
> - ? ? ? ? ? ? ? ? ? ? "vpandn\t{$src2, $src1, $dst|$dst, $src1, $src2}",
> - ? ? ? ? ? ? ? ? ? ? [(set VR256:$dst,
> - ? ? ? ? ? ? ? ? ? ? ? ? ?(v4i64 (X86andnp VR256:$src1, VR256:$src2)))]>,VEX_4V;
> -
> - ?def VPANDNYrm : PDI<0xDF, MRMSrcMem,
> - ? ? ? ? ? ? ? ? ? ? (outs VR256:$dst), (ins VR256:$src1, i256mem:$src2),
> - ? ? ? ? ? ? ? ? ? ? "vpandn\t{$src2, $src1, $dst|$dst, $src1, $src2}",
> - ? ? ? ? ? ? ? ? ? ? [(set VR256:$dst, (X86andnp VR256:$src1,
> - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?(memopv4i64 addr:$src2)))]>, VEX_4V;
> ?}
> ?}
>
> @@ -3761,6 +3743,8 @@
> ? ? ? ? ? ? ? ? ? ? ? ? ?i128mem, 1>;
> ?defm PXOR : PDI_binop_rm<0xEF, "pxor", xor, v2i64, VR128, memopv2i64,
> ? ? ? ? ? ? ? ? ? ? ? ? ?i128mem, 1>;
> +defm PANDN : PDI_binop_rm<0xDF, "pandn", X86andnp, v2i64, VR128, memopv2i64,
> + ? ? ? ? ? ? ? ? ? ? ? ? ?i128mem, 0>;
>
> ?let ExeDomain = SSEPackedInt in {
> ? let neverHasSideEffects = 1 in {
> @@ -3772,14 +3756,6 @@
> ? ? ? ? ? ? ? ? ? ? ? ? ?(outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
> ? ? ? ? ? ? ? ? ? ? ? ? ?"psrldq\t{$src2, $dst|$dst, $src2}", []>;
> ? ? // PSRADQri doesn't exist in SSE[1-3].
> - ? ?def PANDNrr : PDI<0xDF, MRMSrcReg,
> - ? ? ? ? ? ? ? ? ? ? ?(outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
> - ? ? ? ? ? ? ? ? ? ? ?"pandn\t{$src2, $dst|$dst, $src2}", []>;
> -
> - ? ?let mayLoad = 1 in
> - ? ?def PANDNrm : PDI<0xDF, MRMSrcMem,
> - ? ? ? ? ? ? ? ? ? ? ?(outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
> - ? ? ? ? ? ? ? ? ? ? ?"pandn\t{$src2, $dst|$dst, $src2}", []>;
> ? }
> ?}
> ?} // Constraints = "$src1 = $dst"
> @@ -4791,7 +4767,7 @@
> ?// AVX 256-bit register conversion intrinsics
> ?def : Pat<(int_x86_avx_cvtdq2_pd_256 VR128:$src),
> ? ? ? ? ? ?(VCVTDQ2PDYrr VR128:$src)>;
> -def : Pat<(int_x86_avx_cvtdq2_pd_256 (memopv4i32 addr:$src)),
> +def : Pat<(int_x86_avx_cvtdq2_pd_256 (bitconvert (memopv2i64 addr:$src))),
> ? ? ? ? ? ?(VCVTDQ2PDYrm addr:$src)>;
>
> ?def : Pat<(int_x86_avx_cvt_pd2dq_256 VR256:$src),
> @@ -4801,7 +4777,7 @@
>
> ?def : Pat<(v4f64 (sint_to_fp (v4i32 VR128:$src))),
> ? ? ? ? ? (VCVTDQ2PDYrr VR128:$src)>;
> -def : Pat<(v4f64 (sint_to_fp (memopv4i32 addr:$src))),
> +def : Pat<(v4f64 (sint_to_fp (bc_v4i32 (memopv2i64 addr:$src)))),
> ? ? ? ? ? (VCVTDQ2PDYrm addr:$src)>;
>
> ?//===---------------------------------------------------------------------===//
> @@ -6406,38 +6382,38 @@
> ? let isCommutable = 0 in {
> ? ? let ExeDomain = SSEPackedSingle in {
> ? ? defm VBLENDPS : SS41I_binop_rmi_int<0x0C, "vblendps", int_x86_sse41_blendps,
> - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?VR128, memopv16i8, i128mem, 0>, VEX_4V;
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?VR128, memopv4f32, i128mem, 0>, VEX_4V;
> ? ? defm VBLENDPSY : SS41I_binop_rmi_int<0x0C, "vblendps",
> - ? ? ? ? ? ? ?int_x86_avx_blend_ps_256, VR256, memopv32i8, i256mem, 0>, VEX_4V;
> + ? ? ? ? ? ? ?int_x86_avx_blend_ps_256, VR256, memopv8f32, i256mem, 0>, VEX_4V;
> ? ? }
> ? ? let ExeDomain = SSEPackedDouble in {
> ? ? defm VBLENDPD : SS41I_binop_rmi_int<0x0D, "vblendpd", int_x86_sse41_blendpd,
> - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?VR128, memopv16i8, i128mem, 0>, VEX_4V;
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?VR128, memopv2f64, i128mem, 0>, VEX_4V;
> ? ? defm VBLENDPDY : SS41I_binop_rmi_int<0x0D, "vblendpd",
> - ? ? ? ? ? ? ?int_x86_avx_blend_pd_256, VR256, memopv32i8, i256mem, 0>, VEX_4V;
> + ? ? ? ? ? ? ?int_x86_avx_blend_pd_256, VR256, memopv4f64, i256mem, 0>, VEX_4V;
> ? ? }
> ? defm VPBLENDW : SS41I_binop_rmi_int<0x0E, "vpblendw", int_x86_sse41_pblendw,
> - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?VR128, memopv16i8, i128mem, 0>, VEX_4V;
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?VR128, memopv2i64, i128mem, 0>, VEX_4V;
> ? defm VMPSADBW : SS41I_binop_rmi_int<0x42, "vmpsadbw", int_x86_sse41_mpsadbw,
> - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?VR128, memopv16i8, i128mem, 0>, VEX_4V;
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?VR128, memopv2i64, i128mem, 0>, VEX_4V;
> ? }
> ? let ExeDomain = SSEPackedSingle in
> ? defm VDPPS : SS41I_binop_rmi_int<0x40, "vdpps", int_x86_sse41_dpps,
> - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? VR128, memopv16i8, i128mem, 0>, VEX_4V;
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? VR128, memopv4f32, i128mem, 0>, VEX_4V;
> ? let ExeDomain = SSEPackedDouble in
> ? defm VDPPD : SS41I_binop_rmi_int<0x41, "vdppd", int_x86_sse41_dppd,
> - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? VR128, memopv16i8, i128mem, 0>, VEX_4V;
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? VR128, memopv2f64, i128mem, 0>, VEX_4V;
> ? let ExeDomain = SSEPackedSingle in
> ? defm VDPPSY : SS41I_binop_rmi_int<0x40, "vdpps", int_x86_avx_dp_ps_256,
> - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? VR256, memopv32i8, i256mem, 0>, VEX_4V;
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? VR256, memopv8f32, i256mem, 0>, VEX_4V;
> ?}
>
> ?let Predicates = [HasAVX2] in {
> ? let isCommutable = 0 in {
> ? defm VPBLENDWY : SS41I_binop_rmi_int<0x0E, "vpblendw", int_x86_avx2_pblendw,
> - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? VR256, memopv32i8, i256mem, 0>, VEX_4V;
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? VR256, memopv4i64, i256mem, 0>, VEX_4V;
> ? defm VMPSADBWY : SS41I_binop_rmi_int<0x42, "vmpsadbw", int_x86_avx2_mpsadbw,
> - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? VR256, memopv32i8, i256mem, 0>, VEX_4V;
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? VR256, memopv4i64, i256mem, 0>, VEX_4V;
> ? }
> ?}
>
> @@ -6445,21 +6421,21 @@
> ? let isCommutable = 0 in {
> ? let ExeDomain = SSEPackedSingle in
> ? defm BLENDPS : SS41I_binop_rmi_int<0x0C, "blendps", int_x86_sse41_blendps,
> - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? VR128, memopv16i8, i128mem>;
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? VR128, memopv4f32, i128mem>;
> ? let ExeDomain = SSEPackedDouble in
> ? defm BLENDPD : SS41I_binop_rmi_int<0x0D, "blendpd", int_x86_sse41_blendpd,
> - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? VR128, memopv16i8, i128mem>;
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? VR128, memopv2f64, i128mem>;
> ? defm PBLENDW : SS41I_binop_rmi_int<0x0E, "pblendw", int_x86_sse41_pblendw,
> - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? VR128, memopv16i8, i128mem>;
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? VR128, memopv2i64, i128mem>;
> ? defm MPSADBW : SS41I_binop_rmi_int<0x42, "mpsadbw", int_x86_sse41_mpsadbw,
> - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? VR128, memopv16i8, i128mem>;
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? VR128, memopv2i64, i128mem>;
> ? }
> ? let ExeDomain = SSEPackedSingle in
> ? defm DPPS : SS41I_binop_rmi_int<0x40, "dpps", int_x86_sse41_dpps,
> - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?VR128, memopv16i8, i128mem>;
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?VR128, memopv4f32, i128mem>;
> ? let ExeDomain = SSEPackedDouble in
> ? defm DPPD : SS41I_binop_rmi_int<0x41, "dppd", int_x86_sse41_dppd,
> - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?VR128, memopv16i8, i128mem>;
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?VR128, memopv2f64, i128mem>;
> ?}
>
> ?/// SS41I_quaternary_int_avx - AVX SSE 4.1 with 4 operators
> @@ -6486,23 +6462,23 @@
> ?let Predicates = [HasAVX] in {
> ?let ExeDomain = SSEPackedDouble in {
> ?defm VBLENDVPD ?: SS41I_quaternary_int_avx<0x4B, "vblendvpd", VR128, i128mem,
> - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? memopv16i8, int_x86_sse41_blendvpd>;
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? memopv2f64, int_x86_sse41_blendvpd>;
> ?defm VBLENDVPDY : SS41I_quaternary_int_avx<0x4B, "vblendvpd", VR256, i256mem,
> - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? memopv32i8, int_x86_avx_blendv_pd_256>;
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? memopv4f64, int_x86_avx_blendv_pd_256>;
> ?} // ExeDomain = SSEPackedDouble
> ?let ExeDomain = SSEPackedSingle in {
> ?defm VBLENDVPS ?: SS41I_quaternary_int_avx<0x4A, "vblendvps", VR128, i128mem,
> - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? memopv16i8, int_x86_sse41_blendvps>;
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? memopv4f32, int_x86_sse41_blendvps>;
> ?defm VBLENDVPSY : SS41I_quaternary_int_avx<0x4A, "vblendvps", VR256, i256mem,
> - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? memopv32i8, int_x86_avx_blendv_ps_256>;
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? memopv8f32, int_x86_avx_blendv_ps_256>;
> ?} // ExeDomain = SSEPackedSingle
> ?defm VPBLENDVB ?: SS41I_quaternary_int_avx<0x4C, "vpblendvb", VR128, i128mem,
> - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? memopv16i8, int_x86_sse41_pblendvb>;
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? memopv2i64, int_x86_sse41_pblendvb>;
> ?}
>
> ?let Predicates = [HasAVX2] in {
> ?defm VPBLENDVBY : SS41I_quaternary_int_avx<0x4C, "vpblendvb", VR256, i256mem,
> - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? memopv32i8, int_x86_avx2_pblendvb>;
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? memopv4i64, int_x86_avx2_pblendvb>;
> ?}
>
> ?let Predicates = [HasAVX] in {
> @@ -6543,7 +6519,8 @@
>
> ?/// SS41I_ternary_int - SSE 4.1 ternary operator
> ?let Uses = [XMM0], Constraints = "$src1 = $dst" in {
> - ?multiclass SS41I_ternary_int opc, string OpcodeStr, Intrinsic IntId> {
> + ?multiclass SS41I_ternary_int opc, string OpcodeStr, PatFrag mem_frag,
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? Intrinsic IntId> {
> ? ? def rr0 : SS48I ? ? ? ? ? ? ? ? ? ? (ins VR128:$src1, VR128:$src2),
> ? ? ? ? ? ? ? ? ? ? !strconcat(OpcodeStr,
> @@ -6557,15 +6534,18 @@
> ? ? ? ? ? ? ? ? ? ? ?"\t{$src2, $dst|$dst, $src2}"),
> ? ? ? ? ? ? ? ? ? ? [(set VR128:$dst,
> ? ? ? ? ? ? ? ? ? ? ? (IntId VR128:$src1,
> - ? ? ? ? ? ? ? ? ? ? ? (bitconvert (memopv16i8 addr:$src2)), XMM0))]>, OpSize;
> + ? ? ? ? ? ? ? ? ? ? ? (bitconvert (mem_frag addr:$src2)), XMM0))]>, OpSize;
> ? }
> ?}
>
> ?let ExeDomain = SSEPackedDouble in
> -defm BLENDVPD : SS41I_ternary_int<0x15, "blendvpd", int_x86_sse41_blendvpd>;
> +defm BLENDVPD : SS41I_ternary_int<0x15, "blendvpd", memopv2f64,
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?int_x86_sse41_blendvpd>;
> ?let ExeDomain = SSEPackedSingle in
> -defm BLENDVPS : SS41I_ternary_int<0x14, "blendvps", int_x86_sse41_blendvps>;
> -defm PBLENDVB : SS41I_ternary_int<0x10, "pblendvb", int_x86_sse41_pblendvb>;
> +defm BLENDVPS : SS41I_ternary_int<0x14, "blendvps", memopv4f32,
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?int_x86_sse41_blendvps>;
> +defm PBLENDVB : SS41I_ternary_int<0x10, "pblendvb", memopv2i64,
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?int_x86_sse41_pblendvb>;
>
> ?let Predicates = [HasSSE41] in {
> ? def : Pat<(v16i8 (vselect (v16i8 XMM0), (v16i8 VR128:$src1),
> @@ -6620,8 +6600,7 @@
> ? ? ? ? ? ?!strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
> ? ? ? ? ? ?!strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
> ? ? ? ?[(set VR128:$dst,
> - ? ? ? ? (IntId128 VR128:$src1,
> - ? ? ? ? ?(bitconvert (memopv16i8 addr:$src2))))]>, OpSize;
> + ? ? ? ? (IntId128 VR128:$src1, (memopv2i64 addr:$src2)))]>, OpSize;
> ?}
>
> ?/// SS42I_binop_rm_int - Simple SSE 4.2 binary operator
> @@ -6636,8 +6615,7 @@
> ? ? ? ?(ins VR256:$src1, i256mem:$src2),
> ? ? ? ?!strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
> ? ? ? ?[(set VR256:$dst,
> - ? ? ? ? (IntId256 VR256:$src1,
> - ? ? ? ? ?(bitconvert (memopv32i8 addr:$src2))))]>, OpSize;
> + ? ? ? ? (IntId256 VR256:$src1, (memopv4i64 addr:$src2)))]>, OpSize;
> ?}
>
> ?let Predicates = [HasAVX] in {
> @@ -6919,7 +6897,7 @@
> ? ? ? ? ? ?!strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
> ? ? ? ?[(set VR128:$dst,
> ? ? ? ? ?(IntId128 VR128:$src1,
> - ? ? ? ? ?(bitconvert (memopv16i8 addr:$src2))))]>, OpSize;
> + ? ? ? ? ?(bitconvert (memopv2i64 addr:$src2))))]>, OpSize;
> ?}
>
> ?// Perform One Round of an AES Encryption/Decryption Flow
> @@ -7404,9 +7382,9 @@
>
> ?let isCommutable = 0 in {
> ?defm VPBLENDD : AVX2_binop_rmi_int<0x02, "vpblendd", int_x86_avx2_pblendd_128,
> - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? VR128, memopv16i8, i128mem>;
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? VR128, memopv2i64, i128mem>;
> ?defm VPBLENDDY : AVX2_binop_rmi_int<0x02, "vpblendd", int_x86_avx2_pblendd_256,
> - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?VR256, memopv32i8, i256mem>;
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?VR256, memopv4i64, i256mem>;
> ?}
>
> ?//===----------------------------------------------------------------------===//
>
>
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits



-- 
Bruno Cardoso Lopes
http://www.brunocardoso.cc


From grosbach at apple.com  Wed Dec  7 17:08:12 2011
From: grosbach at apple.com (Jim Grosbach)
Date: Wed, 07 Dec 2011 23:08:12 -0000
Subject: [llvm-commits] [llvm] r146095 - in /llvm/trunk:
 lib/Target/ARM/ARMInstrNEON.td test/MC/ARM/neon-bitwise-encoding.s
Message-ID: <20111207230812.909562A6C12C@llvm.org>

Author: grosbach
Date: Wed Dec  7 17:08:12 2011
New Revision: 146095

URL: http://llvm.org/viewvc/llvm-project?rev=146095&view=rev
Log:
ARM two-operand aliases for VAND/VEOR/VORR instructions.

Modified:
    llvm/trunk/lib/Target/ARM/ARMInstrNEON.td
    llvm/trunk/test/MC/ARM/neon-bitwise-encoding.s

Modified: llvm/trunk/lib/Target/ARM/ARMInstrNEON.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrNEON.td?rev=146095&r1=146094&r2=146095&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrNEON.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrNEON.td Wed Dec  7 17:08:12 2011
@@ -5348,6 +5348,32 @@
                          (VORRd DPR:$Vd, DPR:$Vn, DPR:$Vm, pred:$p)>;
 defm : VFPDTAnyInstAlias<"vorr${p}", "$Vd, $Vn, $Vm",
                          (VORRq QPR:$Vd, QPR:$Vn, QPR:$Vm, pred:$p)>;
+// ... two-operand aliases
+def : NEONInstAlias<"vand${p} $Vdn, $Vm",
+                    (VANDd DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;
+def : NEONInstAlias<"vand${p} $Vdn, $Vm",
+                    (VANDq QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>;
+def : NEONInstAlias<"veor${p} $Vdn, $Vm",
+                    (VEORd DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;
+def : NEONInstAlias<"veor${p} $Vdn, $Vm",
+                    (VEORq QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>;
+def : NEONInstAlias<"vand${p} $Vdn, $Vm",
+                    (VORRd DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;
+def : NEONInstAlias<"vand${p} $Vdn, $Vm",
+                    (VORRq QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>;
+
+defm : VFPDTAnyInstAlias<"vand${p}", "$Vdn, $Vm",
+                         (VANDd DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;
+defm : VFPDTAnyInstAlias<"vand${p}", "$Vdn, $Vm",
+                         (VANDq QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>;
+defm : VFPDTAnyInstAlias<"veor${p}", "$Vdn, $Vm",
+                         (VEORd DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;
+defm : VFPDTAnyInstAlias<"veor${p}", "$Vdn, $Vm",
+                         (VEORq QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>;
+defm : VFPDTAnyInstAlias<"vorr${p}", "$Vdn, $Vm",
+                         (VORRd DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;
+defm : VFPDTAnyInstAlias<"vorr${p}", "$Vdn, $Vm",
+                         (VORRq QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>;
 
 // VMUL two-operand aliases.
 def : NEONInstAlias<"vmul${p}.i16 $Ddn, $Dm$lane",

Modified: llvm/trunk/test/MC/ARM/neon-bitwise-encoding.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/neon-bitwise-encoding.s?rev=146095&r1=146094&r2=146095&view=diff
==============================================================================
--- llvm/trunk/test/MC/ARM/neon-bitwise-encoding.s (original)
+++ llvm/trunk/test/MC/ARM/neon-bitwise-encoding.s Wed Dec  7 17:08:12 2011
@@ -230,3 +230,34 @@
 
 @ CHECK: vorr	q4, q7, q3              @ encoding: [0x56,0x81,0x2e,0xf2]
 @ CHECK: vorr	q4, q7, q3              @ encoding: [0x56,0x81,0x2e,0xf2]
+
+@ Two-operand aliases
+	vand.s8  q6, q5
+	vand.s16 q7, q1
+	vand.s32 q8, q2
+	vand.f64 q8, q2
+
+	veor.8   q6, q5
+	veor.p16 q7, q1
+	veor.u32 q8, q2
+	veor.d   q8, q2
+
+	veor.i8  q6, q5
+	veor.16  q7, q1
+	veor.f   q8, q2
+	veor.i64 q8, q2
+
+@ CHECK: vand	q6, q6, q5              @ encoding: [0x5a,0xc1,0x0c,0xf2]
+@ CHECK: vand	q7, q7, q1              @ encoding: [0x52,0xe1,0x0e,0xf2]
+@ CHECK: vand	q8, q8, q2              @ encoding: [0xd4,0x01,0x40,0xf2]
+@ CHECK: vand	q8, q8, q2              @ encoding: [0xd4,0x01,0x40,0xf2]
+
+@ CHECK: veor	q6, q6, q5              @ encoding: [0x5a,0xc1,0x0c,0xf3]
+@ CHECK: veor	q7, q7, q1              @ encoding: [0x52,0xe1,0x0e,0xf3]
+@ CHECK: veor	q8, q8, q2              @ encoding: [0xd4,0x01,0x40,0xf3]
+@ CHECK: veor	q8, q8, q2              @ encoding: [0xd4,0x01,0x40,0xf3]
+
+@ CHECK: veor	q6, q6, q5              @ encoding: [0x5a,0xc1,0x0c,0xf3]
+@ CHECK: veor	q7, q7, q1              @ encoding: [0x52,0xe1,0x0e,0xf3]
+@ CHECK: veor	q8, q8, q2              @ encoding: [0xd4,0x01,0x40,0xf3]
+@ CHECK: veor	q8, q8, q2              @ encoding: [0xd4,0x01,0x40,0xf3]



From ahatanaka at mips.com  Wed Dec  7 17:14:41 2011
From: ahatanaka at mips.com (Akira Hatanaka)
Date: Wed, 07 Dec 2011 23:14:41 -0000
Subject: [llvm-commits] [llvm] r146096 - in /llvm/trunk:
 lib/Target/Mips/Mips64InstrInfo.td test/CodeGen/Mips/mips64ext.ll
Message-ID: <20111207231441.9D1A92A6C12C@llvm.org>

Author: ahatanak
Date: Wed Dec  7 17:14:41 2011
New Revision: 146096

URL: http://llvm.org/viewvc/llvm-project?rev=146096&view=rev
Log:
32 to 64-bit zext pattern.


Added:
    llvm/trunk/test/CodeGen/Mips/mips64ext.ll
Modified:
    llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td

Modified: llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td?rev=146096&r1=146095&r2=146096&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td (original)
+++ llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td Wed Dec  7 17:14:41 2011
@@ -222,6 +222,9 @@
 def DEXT : ExtBase<3, "dext", CPU64Regs>;
 def DINS : InsBase<7, "dins", CPU64Regs>;
 
+def DSLL64_32 : FR<0x3c, 0x00, (outs CPU64Regs:$rd), (ins CPURegs:$rt),
+                   "dsll32\t$rd, $rt, 0", [], IIAlu>;
+
 //===----------------------------------------------------------------------===//
 //  Arbitrary patterns that map to one or more instructions
 //===----------------------------------------------------------------------===//
@@ -296,3 +299,5 @@
 def : Pat<(i32 (trunc CPU64Regs:$src)),
           (SLL (EXTRACT_SUBREG CPU64Regs:$src, sub_32), 0)>, Requires<[IsN64]>;
  
+// 32-to-64-bit extension
+def : Pat<(i64 (zext CPURegs:$src)), (DSRL32 (DSLL64_32 CPURegs:$src), 0)>;

Added: llvm/trunk/test/CodeGen/Mips/mips64ext.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/mips64ext.ll?rev=146096&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/mips64ext.ll (added)
+++ llvm/trunk/test/CodeGen/Mips/mips64ext.ll Wed Dec  7 17:14:41 2011
@@ -0,0 +1,11 @@
+; RUN: llc  < %s -march=mips64el -mcpu=mips64 -mattr=n64 | FileCheck %s 
+
+define i64 @zext64_32(i32 %a) nounwind readnone {
+entry:
+; CHECK: addiu $[[R0:[0-9]+]], ${{[0-9]+}}, 2
+; CHECK: dsll32 $[[R1:[0-9]+]], $[[R0]], 0
+; CHECK: dsrl32  ${{[0-9]+}}, $[[R1]], 0
+  %add = add i32 %a, 2
+  %conv = zext i32 %add to i64
+  ret i64 %conv
+}



From ahatanaka at mips.com  Wed Dec  7 17:21:20 2011
From: ahatanaka at mips.com (Akira Hatanaka)
Date: Wed, 07 Dec 2011 23:21:20 -0000
Subject: [llvm-commits] [llvm] r146097 -
	/llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td
Message-ID: <20111207232120.218682A6C12C@llvm.org>

Author: ahatanak
Date: Wed Dec  7 17:21:19 2011
New Revision: 146097

URL: http://llvm.org/viewvc/llvm-project?rev=146097&view=rev
Log:
32 to 64-bit anyext pattern.


Modified:
    llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td

Modified: llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td?rev=146097&r1=146096&r2=146097&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td (original)
+++ llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td Wed Dec  7 17:21:19 2011
@@ -225,6 +225,9 @@
 def DSLL64_32 : FR<0x3c, 0x00, (outs CPU64Regs:$rd), (ins CPURegs:$rt),
                    "dsll32\t$rd, $rt, 0", [], IIAlu>;
 
+def SLL64_32 : FR<0x0, 0x00, (outs CPU64Regs:$rd), (ins CPURegs:$rt),
+                  "sll\t$rd, $rt, 0", [], IIAlu>;
+
 //===----------------------------------------------------------------------===//
 //  Arbitrary patterns that map to one or more instructions
 //===----------------------------------------------------------------------===//
@@ -300,4 +303,5 @@
           (SLL (EXTRACT_SUBREG CPU64Regs:$src, sub_32), 0)>, Requires<[IsN64]>;
  
 // 32-to-64-bit extension
+def : Pat<(i64 (anyext CPURegs:$src)), (SLL64_32 CPURegs:$src)>;
 def : Pat<(i64 (zext CPURegs:$src)), (DSRL32 (DSLL64_32 CPURegs:$src), 0)>;



From ahatanaka at mips.com  Wed Dec  7 17:23:53 2011
From: ahatanaka at mips.com (Akira Hatanaka)
Date: Wed, 07 Dec 2011 23:23:53 -0000
Subject: [llvm-commits] [llvm] r146099 -
	/llvm/trunk/lib/Target/Mips/MipsRegisterInfo.td
Message-ID: <20111207232353.467232A6C12C@llvm.org>

Author: ahatanak
Date: Wed Dec  7 17:23:52 2011
New Revision: 146099

URL: http://llvm.org/viewvc/llvm-project?rev=146099&view=rev
Log:
Add 64-bit HWR29 register.


Modified:
    llvm/trunk/lib/Target/Mips/MipsRegisterInfo.td

Modified: llvm/trunk/lib/Target/Mips/MipsRegisterInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsRegisterInfo.td?rev=146099&r1=146098&r2=146099&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsRegisterInfo.td (original)
+++ llvm/trunk/lib/Target/Mips/MipsRegisterInfo.td Wed Dec  7 17:23:52 2011
@@ -239,6 +239,7 @@
 
   // Hardware register $29
   def HWR29 : Register<"29">;
+  def HWR29_64 : Register<"29">;
 }
 
 //===----------------------------------------------------------------------===//
@@ -301,3 +302,4 @@
 
 // Hardware registers
 def HWRegs : RegisterClass<"Mips", [i32], 32, (add HWR29)>;
+def HWRegs64 : RegisterClass<"Mips", [i64], 32, (add HWR29_64)>;
\ No newline at end of file



From ahatanaka at mips.com  Wed Dec  7 17:26:03 2011
From: ahatanaka at mips.com (Akira Hatanaka)
Date: Wed, 07 Dec 2011 23:26:03 -0000
Subject: [llvm-commits] [llvm] r146100 -
	/llvm/trunk/lib/Target/Mips/MipsRegisterInfo.td
Message-ID: <20111207232603.E7E342A6C12C@llvm.org>

Author: ahatanak
Date: Wed Dec  7 17:26:03 2011
New Revision: 146100

URL: http://llvm.org/viewvc/llvm-project?rev=146100&view=rev
Log:
Add newline.

Modified:
    llvm/trunk/lib/Target/Mips/MipsRegisterInfo.td

Modified: llvm/trunk/lib/Target/Mips/MipsRegisterInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsRegisterInfo.td?rev=146100&r1=146099&r2=146100&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsRegisterInfo.td (original)
+++ llvm/trunk/lib/Target/Mips/MipsRegisterInfo.td Wed Dec  7 17:26:03 2011
@@ -302,4 +302,5 @@
 
 // Hardware registers
 def HWRegs : RegisterClass<"Mips", [i32], 32, (add HWR29)>;
-def HWRegs64 : RegisterClass<"Mips", [i64], 32, (add HWR29_64)>;
\ No newline at end of file
+def HWRegs64 : RegisterClass<"Mips", [i64], 32, (add HWR29_64)>;
+



From ahatanaka at mips.com  Wed Dec  7 17:31:26 2011
From: ahatanaka at mips.com (Akira Hatanaka)
Date: Wed, 07 Dec 2011 23:31:26 -0000
Subject: [llvm-commits] [llvm] r146101 - in /llvm/trunk/lib/Target/Mips:
 Mips64InstrInfo.td MipsInstrInfo.td
Message-ID: <20111207233126.8CA542A6C12C@llvm.org>

Author: ahatanak
Date: Wed Dec  7 17:31:26 2011
New Revision: 146101

URL: http://llvm.org/viewvc/llvm-project?rev=146101&view=rev
Log:
Modify class ReadHardware and add definition of 64-bit version of instruction
RDHWR. 


Modified:
    llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td
    llvm/trunk/lib/Target/Mips/MipsInstrInfo.td

Modified: llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td?rev=146101&r1=146100&r2=146101&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td (original)
+++ llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td Wed Dec  7 17:31:26 2011
@@ -219,6 +219,8 @@
 def DynAlloc64 : EffectiveAddress<"daddiu\t$rt, $addr", CPU64Regs, mem_ea_64>,
                  Requires<[IsN64]>;
 
+def RDHWR64 : ReadHardware;
+
 def DEXT : ExtBase<3, "dext", CPU64Regs>;
 def DINS : InsBase<7, "dins", CPU64Regs>;
 

Modified: llvm/trunk/lib/Target/Mips/MipsInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsInstrInfo.td?rev=146101&r1=146100&r2=146101&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsInstrInfo.td (original)
+++ llvm/trunk/lib/Target/Mips/MipsInstrInfo.td Wed Dec  7 17:31:26 2011
@@ -614,8 +614,9 @@
 }
 
 // Read Hardware
-class ReadHardware: FR<0x1f, 0x3b, (outs CPURegs:$rt), (ins HWRegs:$rd),
-    "rdhwr\t$rt, $rd", [], IIAlu> {
+class ReadHardware
+  : FR<0x1f, 0x3b, (outs CPURegClass:$rt), (ins HWRegClass:$rd),
+       "rdhwr\t$rt, $rd", [], IIAlu> {
   let rs = 0;
   let shamt = 0;
 }
@@ -901,7 +902,7 @@
 def MUL   : ArithLogicR<0x1c, 0x02, "mul", mul, IIImul, CPURegs, 1>,
             Requires<[HasMips32]>;
 
-def RDHWR : ReadHardware;
+def RDHWR : ReadHardware;
 
 def EXT : ExtBase<0, "ext", CPURegs>;
 def INS : InsBase<4, "ins", CPURegs>;



From grosbach at apple.com  Wed Dec  7 17:40:58 2011
From: grosbach at apple.com (Jim Grosbach)
Date: Wed, 07 Dec 2011 23:40:58 -0000
Subject: [llvm-commits] [llvm] r146106 - in /llvm/trunk:
 lib/Target/ARM/AsmParser/ARMAsmParser.cpp
 test/MC/ARM/basic-arm-instructions.s
Message-ID: <20111207234058.E27D72A6C12C@llvm.org>

Author: grosbach
Date: Wed Dec  7 17:40:58 2011
New Revision: 146106

URL: http://llvm.org/viewvc/llvm-project?rev=146106&view=rev
Log:
ARM assembly, allow 'asl' as a synonym for 'lsl' in shifted-register operands.

For 'gas' compatibility.

Modified:
    llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
    llvm/trunk/test/MC/ARM/basic-arm-instructions.s

Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp?rev=146106&r1=146105&r2=146106&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp (original)
+++ llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Wed Dec  7 17:40:58 2011
@@ -2140,6 +2140,7 @@
 
   std::string lowerCase = Tok.getString().lower();
   ARM_AM::ShiftOpc ShiftTy = StringSwitch(lowerCase)
+      .Case("asl", ARM_AM::lsl)
       .Case("lsl", ARM_AM::lsl)
       .Case("lsr", ARM_AM::lsr)
       .Case("asr", ARM_AM::asr)
@@ -3901,7 +3902,8 @@
   if (Tok.isNot(AsmToken::Identifier))
     return true;
   StringRef ShiftName = Tok.getString();
-  if (ShiftName == "lsl" || ShiftName == "LSL")
+  if (ShiftName == "lsl" || ShiftName == "LSL" ||
+      ShiftName == "asl" || ShiftName == "ASL")
     St = ARM_AM::lsl;
   else if (ShiftName == "lsr" || ShiftName == "LSR")
     St = ARM_AM::lsr;

Modified: llvm/trunk/test/MC/ARM/basic-arm-instructions.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/basic-arm-instructions.s?rev=146106&r1=146105&r2=146106&view=diff
==============================================================================
--- llvm/trunk/test/MC/ARM/basic-arm-instructions.s (original)
+++ llvm/trunk/test/MC/ARM/basic-arm-instructions.s Wed Dec  7 17:40:58 2011
@@ -153,6 +153,7 @@
         add r4, r5, r6, asr #5
         add r4, r5, r6, ror #5
         add r6, r7, r8, lsl r9
+        add r4, r4, r3, asl r9
         add r6, r7, r8, lsr r9
         add r6, r7, r8, asr r9
         add r6, r7, r8, ror r9
@@ -180,6 +181,7 @@
 @ CHECK: add	r4, r5, r6, asr #5      @ encoding: [0xc6,0x42,0x85,0xe0]
 @ CHECK: add	r4, r5, r6, ror #5      @ encoding: [0xe6,0x42,0x85,0xe0]
 @ CHECK: add	r6, r7, r8, lsl r9      @ encoding: [0x18,0x69,0x87,0xe0]
+@ CHECK: add	r4, r4, r3, lsl r9      @ encoding: [0x13,0x49,0x84,0xe0]
 @ CHECK: add	r6, r7, r8, lsr r9      @ encoding: [0x38,0x69,0x87,0xe0]
 @ CHECK: add	r6, r7, r8, asr r9      @ encoding: [0x58,0x69,0x87,0xe0]
 @ CHECK: add	r6, r7, r8, ror r9      @ encoding: [0x78,0x69,0x87,0xe0]



From mcrosier at apple.com  Wed Dec  7 17:57:55 2011
From: mcrosier at apple.com (Chad Rosier)
Date: Wed, 07 Dec 2011 23:57:55 -0000
Subject: [llvm-commits] [llvm] r146107 - in /llvm/trunk:
 include/llvm/Bitcode/LLVMBitCodes.h lib/Bitcode/Writer/BitcodeWriter.cpp
Message-ID: <20111207235755.573022A6C12C@llvm.org>

Author: mcrosier
Date: Wed Dec  7 17:57:55 2011
New Revision: 146107

URL: http://llvm.org/viewvc/llvm-project?rev=146107&view=rev
Log:
Fix comments.

Modified:
    llvm/trunk/include/llvm/Bitcode/LLVMBitCodes.h
    llvm/trunk/lib/Bitcode/Writer/BitcodeWriter.cpp

Modified: llvm/trunk/include/llvm/Bitcode/LLVMBitCodes.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Bitcode/LLVMBitCodes.h?rev=146107&r1=146106&r2=146107&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Bitcode/LLVMBitCodes.h (original)
+++ llvm/trunk/include/llvm/Bitcode/LLVMBitCodes.h Wed Dec  7 17:57:55 2011
@@ -61,7 +61,7 @@
     MODULE_CODE_GLOBALVAR   = 7,
 
     // FUNCTION:  [type, callingconv, isproto, linkage, paramattrs, alignment,
-    //             section, visibility]
+    //             section, visibility, gc, unnamed_addr]
     MODULE_CODE_FUNCTION    = 8,
 
     // ALIAS: [alias type, aliasee val#, linkage]

Modified: llvm/trunk/lib/Bitcode/Writer/BitcodeWriter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Bitcode/Writer/BitcodeWriter.cpp?rev=146107&r1=146106&r2=146107&view=diff
==============================================================================
--- llvm/trunk/lib/Bitcode/Writer/BitcodeWriter.cpp (original)
+++ llvm/trunk/lib/Bitcode/Writer/BitcodeWriter.cpp Wed Dec  7 17:57:55 2011
@@ -504,8 +504,8 @@
 
   // Emit the function proto information.
   for (Module::const_iterator F = M->begin(), E = M->end(); F != E; ++F) {
-    // FUNCTION:  [type, callingconv, isproto, paramattr,
-    //             linkage, alignment, section, visibility, gc, unnamed_addr]
+    // FUNCTION:  [type, callingconv, isproto, linkage, paramattrs, alignment,
+    //             section, visibility, gc, unnamed_addr]
     Vals.push_back(VE.getTypeID(F->getType()));
     Vals.push_back(F->getCallingConv());
     Vals.push_back(F->isDeclaration());



From peter at pcc.me.uk  Wed Dec  7 17:58:57 2011
From: peter at pcc.me.uk (Peter Collingbourne)
Date: Wed, 07 Dec 2011 23:58:57 -0000
Subject: [llvm-commits] [llvm] r146108 - in /llvm/trunk:
 examples/ExceptionDemo/ExceptionDemo.cpp
 include/llvm/ExecutionEngine/ExecutionEngine.h
 lib/ExecutionEngine/ExecutionEngine.cpp
 lib/ExecutionEngine/TargetSelect.cpp
Message-ID: <20111207235857.C16902A6C12C@llvm.org>

Author: pcc
Date: Wed Dec  7 17:58:57 2011
New Revision: 146108

URL: http://llvm.org/viewvc/llvm-project?rev=146108&view=rev
Log:
EngineBuilder: support for custom TargetOptions.  Fixes the
ExceptionDemo example.

Modified:
    llvm/trunk/examples/ExceptionDemo/ExceptionDemo.cpp
    llvm/trunk/include/llvm/ExecutionEngine/ExecutionEngine.h
    llvm/trunk/lib/ExecutionEngine/ExecutionEngine.cpp
    llvm/trunk/lib/ExecutionEngine/TargetSelect.cpp

Modified: llvm/trunk/examples/ExceptionDemo/ExceptionDemo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/examples/ExceptionDemo/ExceptionDemo.cpp?rev=146108&r1=146107&r2=146108&view=diff
==============================================================================
--- llvm/trunk/examples/ExceptionDemo/ExceptionDemo.cpp (original)
+++ llvm/trunk/examples/ExceptionDemo/ExceptionDemo.cpp Wed Dec  7 17:58:57 2011
@@ -2005,7 +2005,8 @@
   }
   
   // If not set, exception handling will not be turned on
-  llvm::JITExceptionHandling = true;
+  llvm::TargetOptions Opts;
+  Opts.JITExceptionHandling = true;
   
   llvm::InitializeNativeTarget();
   llvm::LLVMContext &context = llvm::getGlobalContext();
@@ -2018,6 +2019,7 @@
   llvm::EngineBuilder factory(module);
   factory.setEngineKind(llvm::EngineKind::JIT);
   factory.setAllocateGVsWithCode(false);
+  factory.setTargetOptions(Opts);
   llvm::ExecutionEngine *executionEngine = factory.create();
   
   {

Modified: llvm/trunk/include/llvm/ExecutionEngine/ExecutionEngine.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/ExecutionEngine/ExecutionEngine.h?rev=146108&r1=146107&r2=146108&view=diff
==============================================================================
--- llvm/trunk/include/llvm/ExecutionEngine/ExecutionEngine.h (original)
+++ llvm/trunk/include/llvm/ExecutionEngine/ExecutionEngine.h Wed Dec  7 17:58:57 2011
@@ -26,6 +26,7 @@
 #include "llvm/Support/ValueHandle.h"
 #include "llvm/Support/Mutex.h"
 #include "llvm/Target/TargetMachine.h"
+#include "llvm/Target/TargetOptions.h"
 
 namespace llvm {
 
@@ -462,6 +463,7 @@
   CodeGenOpt::Level OptLevel;
   JITMemoryManager *JMM;
   bool AllocateGVsWithCode;
+  TargetOptions Options;
   Reloc::Model RelocModel;
   CodeModel::Model CMModel;
   std::string MArch;
@@ -475,6 +477,7 @@
     ErrorStr = NULL;
     OptLevel = CodeGenOpt::Default;
     JMM = NULL;
+    Options = TargetOptions();
     AllocateGVsWithCode = false;
     RelocModel = Reloc::Default;
     CMModel = CodeModel::JITDefault;
@@ -518,6 +521,13 @@
     return *this;
   }
 
+  /// setTargetOptions - Set the target options that the ExecutionEngine
+  /// target is using. Defaults to TargetOptions().
+  EngineBuilder &setTargetOptions(const TargetOptions &Opts) {
+    Options = Opts;
+    return *this;
+  }
+
   /// setRelocationModel - Set the relocation model that the ExecutionEngine
   /// target is using. Defaults to target specific default "Reloc::Default".
   EngineBuilder &setRelocationModel(Reloc::Model RM) {
@@ -578,6 +588,7 @@
                                      StringRef MArch,
                                      StringRef MCPU,
                                      const SmallVectorImpl& MAttrs,
+                                     const TargetOptions &Options,
                                      Reloc::Model RM,
                                      CodeModel::Model CM,
                                      CodeGenOpt::Level OL,

Modified: llvm/trunk/lib/ExecutionEngine/ExecutionEngine.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/ExecutionEngine/ExecutionEngine.cpp?rev=146108&r1=146107&r2=146108&view=diff
==============================================================================
--- llvm/trunk/lib/ExecutionEngine/ExecutionEngine.cpp (original)
+++ llvm/trunk/lib/ExecutionEngine/ExecutionEngine.cpp Wed Dec  7 17:58:57 2011
@@ -436,8 +436,10 @@
   StringRef MCPU = "";
   SmallVector MAttrs;
 
+  // TODO: permit custom TargetOptions here
   TargetMachine *TM =
-    EngineBuilder::selectTarget(M, MArch, MCPU, MAttrs, RM, CMM, OL, ErrorStr);
+    EngineBuilder::selectTarget(M, MArch, MCPU, MAttrs, TargetOptions(), RM,
+                                CMM, OL, ErrorStr);
   if (!TM || (ErrorStr && ErrorStr->length() > 0)) return 0;
 
   return ExecutionEngine::JITCtor(M, ErrorStr, JMM, OL, GVsWithCode, TM);
@@ -466,6 +468,7 @@
   // try making a JIT.
   if (WhichEngine & EngineKind::JIT) {
     if (TargetMachine *TM = EngineBuilder::selectTarget(M, MArch, MCPU, MAttrs,
+                                                        Options,
                                                         RelocModel, CMModel,
                                                         OptLevel, ErrorStr)) {
       if (UseMCJIT && ExecutionEngine::MCJITCtor) {

Modified: llvm/trunk/lib/ExecutionEngine/TargetSelect.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/ExecutionEngine/TargetSelect.cpp?rev=146108&r1=146107&r2=146108&view=diff
==============================================================================
--- llvm/trunk/lib/ExecutionEngine/TargetSelect.cpp (original)
+++ llvm/trunk/lib/ExecutionEngine/TargetSelect.cpp Wed Dec  7 17:58:57 2011
@@ -30,6 +30,7 @@
                               StringRef MArch,
                               StringRef MCPU,
                               const SmallVectorImpl& MAttrs,
+                              const TargetOptions &Options,
                               Reloc::Model RM,
                               CodeModel::Model CM,
                               CodeGenOpt::Level OL,
@@ -86,7 +87,6 @@
   }
 
   // Allocate a target...
-  TargetOptions Options;
   TargetMachine *Target = TheTarget->createTargetMachine(TheTriple.getTriple(),
                                                          MCPU, FeaturesStr,
                                                          Options,



From mcrosier at apple.com  Wed Dec  7 18:11:32 2011
From: mcrosier at apple.com (Chad Rosier)
Date: Thu, 08 Dec 2011 00:11:32 -0000
Subject: [llvm-commits] [llvm] r146109 - in /llvm/trunk:
 include/llvm/Bitcode/LLVMBitCodes.h lib/Bitcode/Writer/BitcodeWriter.cpp
Message-ID: <20111208001132.36DFC2A6C12C@llvm.org>

Author: mcrosier
Date: Wed Dec  7 18:11:31 2011
New Revision: 146109

URL: http://llvm.org/viewvc/llvm-project?rev=146109&view=rev
Log:
Fix comments.

Modified:
    llvm/trunk/include/llvm/Bitcode/LLVMBitCodes.h
    llvm/trunk/lib/Bitcode/Writer/BitcodeWriter.cpp

Modified: llvm/trunk/include/llvm/Bitcode/LLVMBitCodes.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Bitcode/LLVMBitCodes.h?rev=146109&r1=146108&r2=146109&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Bitcode/LLVMBitCodes.h (original)
+++ llvm/trunk/include/llvm/Bitcode/LLVMBitCodes.h Wed Dec  7 18:11:31 2011
@@ -64,7 +64,7 @@
     //             section, visibility, gc, unnamed_addr]
     MODULE_CODE_FUNCTION    = 8,
 
-    // ALIAS: [alias type, aliasee val#, linkage]
+    // ALIAS: [alias type, aliasee val#, linkage, visibility]
     MODULE_CODE_ALIAS       = 9,
 
     /// MODULE_CODE_PURGEVALS: [numvals]

Modified: llvm/trunk/lib/Bitcode/Writer/BitcodeWriter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Bitcode/Writer/BitcodeWriter.cpp?rev=146109&r1=146108&r2=146109&view=diff
==============================================================================
--- llvm/trunk/lib/Bitcode/Writer/BitcodeWriter.cpp (original)
+++ llvm/trunk/lib/Bitcode/Writer/BitcodeWriter.cpp Wed Dec  7 18:11:31 2011
@@ -525,6 +525,7 @@
   // Emit the alias information.
   for (Module::const_alias_iterator AI = M->alias_begin(), E = M->alias_end();
        AI != E; ++AI) {
+    // ALIAS: [alias type, aliasee val#, linkage, visibility]
     Vals.push_back(VE.getTypeID(AI->getType()));
     Vals.push_back(VE.getValueID(AI->getAliasee()));
     Vals.push_back(getEncodedLinkage(AI));



From nicholas at mxc.ca  Wed Dec  7 18:15:41 2011
From: nicholas at mxc.ca (Nick Lewycky)
Date: Thu, 08 Dec 2011 00:15:41 -0000
Subject: [llvm-commits] [llvm] r146110 -
	/llvm/trunk/include/llvm/PassSupport.h
Message-ID: <20111208001541.9BA662A6C12C@llvm.org>

Author: nicholas
Date: Wed Dec  7 18:15:41 2011
New Revision: 146110

URL: http://llvm.org/viewvc/llvm-project?rev=146110&view=rev
Log:
Add Tsan annotations to the pass system.

Perhaps once(&func) should be hoisted into lib/Support.

Modified:
    llvm/trunk/include/llvm/PassSupport.h

Modified: llvm/trunk/include/llvm/PassSupport.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/PassSupport.h?rev=146110&r1=146109&r2=146110&view=diff
==============================================================================
--- llvm/trunk/include/llvm/PassSupport.h (original)
+++ llvm/trunk/include/llvm/PassSupport.h Wed Dec  7 18:15:41 2011
@@ -25,6 +25,7 @@
 #include "llvm/PassRegistry.h"
 #include "llvm/InitializePasses.h"
 #include "llvm/Support/Atomic.h"
+#include "llvm/Support/Valgrind.h"
 #include 
 
 namespace llvm {
@@ -135,7 +136,10 @@
   if (old_val == 0) { \
     function(Registry); \
     sys::MemoryFence(); \
+    TsanIgnoreWritesBegin(); \
+    TsanHappensBefore(&initialized); \
     initialized = 2; \
+    TsanIgnoreWritesEnd(); \
   } else { \
     sys::cas_flag tmp = initialized; \
     sys::MemoryFence(); \
@@ -143,7 +147,8 @@
       tmp = initialized; \
       sys::MemoryFence(); \
     } \
-  }
+  } \
+  TsanHappensAfter(&initialized);
 
 #define INITIALIZE_PASS(passName, arg, name, cfg, analysis) \
   static void* initialize##passName##PassOnce(PassRegistry &Registry) { \



From grosbach at apple.com  Wed Dec  7 18:31:07 2011
From: grosbach at apple.com (Jim Grosbach)
Date: Thu, 08 Dec 2011 00:31:07 -0000
Subject: [llvm-commits] [llvm] r146111 - in /llvm/trunk:
 lib/Target/ARM/ARMInstrInfo.td lib/Target/ARM/ARMInstrThumb2.td
 lib/Target/ARM/AsmParser/ARMAsmParser.cpp
 test/MC/ARM/basic-arm-instructions.s
Message-ID: <20111208003108.1D26F2A6C12C@llvm.org>

Author: grosbach
Date: Wed Dec  7 18:31:07 2011
New Revision: 146111

URL: http://llvm.org/viewvc/llvm-project?rev=146111&view=rev
Log:
ARM assembler aliases for "add Rd, #-imm" to "sub Rd, #imm".

Modified:
    llvm/trunk/lib/Target/ARM/ARMInstrInfo.td
    llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td
    llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
    llvm/trunk/test/MC/ARM/basic-arm-instructions.s

Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.td?rev=146111&r1=146110&r2=146111&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrInfo.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Wed Dec  7 18:31:07 2011
@@ -243,17 +243,18 @@
   return (int32_t)Imm >= 16 && (int32_t)Imm < 32;
 }]>;
 
-def so_imm_neg :
-  PatLeaf<(imm), [{
+def so_imm_neg_asmoperand : AsmOperandClass { let Name = "ARMSOImmNeg"; }
+def so_imm_neg : Operand, PatLeaf<(imm), [{
     return ARM_AM::getSOImmVal(-(uint32_t)N->getZExtValue()) != -1;
-  }], so_imm_neg_XFORM>;
+  }], so_imm_neg_XFORM> {
+  let ParserMatchClass = so_imm_neg_asmoperand;
+}
 
 // Note: this pattern doesn't require an encoder method and such, as it's
 // only used on aliases (Pat<> and InstAlias<>). The actual encoding
 // is handled by the destination instructions, which use t2_so_imm.
 def so_imm_not_asmoperand : AsmOperandClass { let Name = "ARMSOImmNot"; }
-def so_imm_not :
-  Operand, PatLeaf<(imm), [{
+def so_imm_not : Operand, PatLeaf<(imm), [{
     return ARM_AM::getSOImmVal(~(uint32_t)N->getZExtValue()) != -1;
   }], so_imm_not_XFORM> {
   let ParserMatchClass = so_imm_not_asmoperand;
@@ -5041,6 +5042,11 @@
 // for isel.
 def : ARMInstAlias<"mov${s}${p} $Rd, $imm",
                    (MVNi rGPR:$Rd, so_imm_not:$imm, pred:$p, cc_out:$s)>;
+// Likewise, "add Rd, so_imm_neg" -> sub
+def : ARMInstAlias<"add${s}${p} $Rd, $Rn, $imm",
+                 (SUBri GPR:$Rd, GPR:$Rn, so_imm_neg:$imm, pred:$p, cc_out:$s)>;
+def : ARMInstAlias<"add${s}${p} $Rd, $imm",
+                 (SUBri GPR:$Rd, GPR:$Rd, so_imm_neg:$imm, pred:$p, cc_out:$s)>;
 
 // The shifter forms of the MOV instruction are aliased to the ASR, LSL,
 // LSR, ROR, and RRX instructions.

Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td?rev=146111&r1=146110&r2=146111&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td Wed Dec  7 18:31:07 2011
@@ -80,18 +80,19 @@
 // only used on aliases (Pat<> and InstAlias<>). The actual encoding
 // is handled by the destination instructions, which use t2_so_imm.
 def t2_so_imm_not_asmoperand : AsmOperandClass { let Name = "T2SOImmNot"; }
-def t2_so_imm_not : Operand,
-                    PatLeaf<(imm), [{
+def t2_so_imm_not : Operand, PatLeaf<(imm), [{
   return ARM_AM::getT2SOImmVal(~((uint32_t)N->getZExtValue())) != -1;
 }], t2_so_imm_not_XFORM> {
   let ParserMatchClass = t2_so_imm_not_asmoperand;
 }
 
 // t2_so_imm_neg - Match an immediate that is a negation of a t2_so_imm.
-def t2_so_imm_neg : Operand,
-                    PatLeaf<(imm), [{
+def t2_so_imm_neg_asmoperand : AsmOperandClass { let Name = "T2SOImmNeg"; }
+def t2_so_imm_neg : Operand, PatLeaf<(imm), [{
   return ARM_AM::getT2SOImmVal(-((uint32_t)N->getZExtValue())) != -1;
-}], t2_so_imm_neg_XFORM>;
+}], t2_so_imm_neg_XFORM> {
+  let ParserMatchClass = t2_so_imm_neg_asmoperand;
+}
 
 /// imm0_4095 predicate - True if the 32-bit immediate is in the range [0.4095].
 def imm0_4095 : Operand,
@@ -4096,6 +4097,13 @@
 // for isel.
 def : t2InstAlias<"mov${p} $Rd, $imm",
                   (t2MVNi rGPR:$Rd, t2_so_imm_not:$imm, pred:$p, zero_reg)>;
+// Likewise, "add Rd, so_imm_neg" -> sub
+def : t2InstAlias<"add${s}${p} $Rd, $Rn, $imm",
+                  (t2SUBri GPRnopc:$Rd, GPRnopc:$Rn, t2_so_imm_neg:$imm,
+                           pred:$p, cc_out:$s)>;
+def : t2InstAlias<"add${s}${p} $Rd, $imm",
+                  (t2SUBri GPRnopc:$Rd, GPRnopc:$Rd, t2_so_imm_neg:$imm,
+                           pred:$p, cc_out:$s)>;
 
 
 // Wide 'mul' encoding can be specified with only two operands.

Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp?rev=146111&r1=146110&r2=146111&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp (original)
+++ llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Wed Dec  7 18:31:07 2011
@@ -749,6 +749,14 @@
     int64_t Value = CE->getValue();
     return ARM_AM::getSOImmVal(~Value) != -1;
   }
+  bool isARMSOImmNeg() const {
+    if (Kind != k_Immediate)
+      return false;
+    const MCConstantExpr *CE = dyn_cast(getImm());
+    if (!CE) return false;
+    int64_t Value = CE->getValue();
+    return ARM_AM::getSOImmVal(-Value) != -1;
+  }
   bool isT2SOImm() const {
     if (Kind != k_Immediate)
       return false;
@@ -765,6 +773,14 @@
     int64_t Value = CE->getValue();
     return ARM_AM::getT2SOImmVal(~Value) != -1;
   }
+  bool isT2SOImmNeg() const {
+    if (Kind != k_Immediate)
+      return false;
+    const MCConstantExpr *CE = dyn_cast(getImm());
+    if (!CE) return false;
+    int64_t Value = CE->getValue();
+    return ARM_AM::getT2SOImmVal(-Value) != -1;
+  }
   bool isSetEndImm() const {
     if (Kind != k_Immediate)
       return false;
@@ -1321,6 +1337,14 @@
     Inst.addOperand(MCOperand::CreateImm(~CE->getValue()));
   }
 
+  void addT2SOImmNegOperands(MCInst &Inst, unsigned N) const {
+    assert(N == 1 && "Invalid number of operands!");
+    // The operand is actually a t2_so_imm, but we have its
+    // negation in the assembly source, so twiddle it here.
+    const MCConstantExpr *CE = dyn_cast(getImm());
+    Inst.addOperand(MCOperand::CreateImm(-CE->getValue()));
+  }
+
   void addARMSOImmNotOperands(MCInst &Inst, unsigned N) const {
     assert(N == 1 && "Invalid number of operands!");
     // The operand is actually a so_imm, but we have its bitwise
@@ -1329,6 +1353,14 @@
     Inst.addOperand(MCOperand::CreateImm(~CE->getValue()));
   }
 
+  void addARMSOImmNegOperands(MCInst &Inst, unsigned N) const {
+    assert(N == 1 && "Invalid number of operands!");
+    // The operand is actually a so_imm, but we have its
+    // negation in the assembly source, so twiddle it here.
+    const MCConstantExpr *CE = dyn_cast(getImm());
+    Inst.addOperand(MCOperand::CreateImm(-CE->getValue()));
+  }
+
   void addMemBarrierOptOperands(MCInst &Inst, unsigned N) const {
     assert(N == 1 && "Invalid number of operands!");
     Inst.addOperand(MCOperand::CreateImm(unsigned(getMemBarrierOpt())));

Modified: llvm/trunk/test/MC/ARM/basic-arm-instructions.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/basic-arm-instructions.s?rev=146111&r1=146110&r2=146111&view=diff
==============================================================================
--- llvm/trunk/test/MC/ARM/basic-arm-instructions.s (original)
+++ llvm/trunk/test/MC/ARM/basic-arm-instructions.s Wed Dec  7 18:31:07 2011
@@ -173,6 +173,9 @@
         add r6, r7, ror r9
         add r4, r5, rrx
 
+	add r0, #-4
+	add r4, r5, #-21
+
 @ CHECK: add	r4, r5, #61440          @ encoding: [0x0f,0x4a,0x85,0xe2]
 @ CHECK: add	r4, r5, r6              @ encoding: [0x06,0x40,0x85,0xe0]
 @ CHECK: add	r4, r5, r6, lsl #5      @ encoding: [0x86,0x42,0x85,0xe0]
@@ -187,7 +190,6 @@
 @ CHECK: add	r6, r7, r8, ror r9      @ encoding: [0x78,0x69,0x87,0xe0]
 @ CHECK: add	r4, r5, r6, rrx         @ encoding: [0x66,0x40,0x85,0xe0]
 
-
 @ CHECK: add	r5, r5, #61440          @ encoding: [0x0f,0x5a,0x85,0xe2]
 @ CHECK: add	r4, r4, r5              @ encoding: [0x05,0x40,0x84,0xe0]
 @ CHECK: add	r4, r4, r5, lsl #5      @ encoding: [0x85,0x42,0x84,0xe0]
@@ -201,6 +203,9 @@
 @ CHECK: add	r6, r6, r7, ror r9      @ encoding: [0x77,0x69,0x86,0xe0]
 @ CHECK: add	r4, r4, r5, rrx         @ encoding: [0x65,0x40,0x84,0xe0]
 
+@ CHECK: sub	r0, r0, #4              @ encoding: [0x04,0x00,0x40,0xe2]
+@ CHECK: sub	r4, r5, #21             @ encoding: [0x15,0x40,0x45,0xe2]
+
 
 @------------------------------------------------------------------------------
 @ AND



From mcrosier at apple.com  Wed Dec  7 18:38:45 2011
From: mcrosier at apple.com (Chad Rosier)
Date: Thu, 08 Dec 2011 00:38:45 -0000
Subject: [llvm-commits] [llvm] r146112 - in /llvm/trunk:
 include/llvm/Bitcode/LLVMBitCodes.h lib/Bitcode/Writer/BitcodeWriter.cpp
Message-ID: <20111208003845.660E42A6C12C@llvm.org>

Author: mcrosier
Date: Wed Dec  7 18:38:45 2011
New Revision: 146112

URL: http://llvm.org/viewvc/llvm-project?rev=146112&view=rev
Log:
Fix 80-column.
Simplify code.

Modified:
    llvm/trunk/include/llvm/Bitcode/LLVMBitCodes.h
    llvm/trunk/lib/Bitcode/Writer/BitcodeWriter.cpp

Modified: llvm/trunk/include/llvm/Bitcode/LLVMBitCodes.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Bitcode/LLVMBitCodes.h?rev=146112&r1=146111&r2=146112&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Bitcode/LLVMBitCodes.h (original)
+++ llvm/trunk/include/llvm/Bitcode/LLVMBitCodes.h Wed Dec  7 18:38:45 2011
@@ -90,7 +90,9 @@
     TYPE_CODE_OPAQUE   =  6,    // OPAQUE
     TYPE_CODE_INTEGER  =  7,    // INTEGER: [width]
     TYPE_CODE_POINTER  =  8,    // POINTER: [pointee type]
-    TYPE_CODE_FUNCTION_OLD = 9, // FUNCTION: [vararg, attrid, retty, paramty x N]
+
+    TYPE_CODE_FUNCTION_OLD = 9, // FUNCTION: [vararg, attrid, retty,
+                                //            paramty x N]
     
     // Code #10 is unused.
     

Modified: llvm/trunk/lib/Bitcode/Writer/BitcodeWriter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Bitcode/Writer/BitcodeWriter.cpp?rev=146112&r1=146111&r2=146112&view=diff
==============================================================================
--- llvm/trunk/lib/Bitcode/Writer/BitcodeWriter.cpp (original)
+++ llvm/trunk/lib/Bitcode/Writer/BitcodeWriter.cpp Wed Dec  7 18:38:45 2011
@@ -201,11 +201,12 @@
   Stream.EnterSubblock(bitc::TYPE_BLOCK_ID_NEW, 4 /*count from # abbrevs */);
   SmallVector TypeVals;
 
+  uint64_t NumBits = Log2_32_Ceil(VE.getTypes().size()+1);
+
   // Abbrev for TYPE_CODE_POINTER.
   BitCodeAbbrev *Abbv = new BitCodeAbbrev();
   Abbv->Add(BitCodeAbbrevOp(bitc::TYPE_CODE_POINTER));
-  Abbv->Add(BitCodeAbbrevOp(BitCodeAbbrevOp::Fixed,
-                            Log2_32_Ceil(VE.getTypes().size()+1)));
+  Abbv->Add(BitCodeAbbrevOp(BitCodeAbbrevOp::Fixed, NumBits));
   Abbv->Add(BitCodeAbbrevOp(0));  // Addrspace = 0
   unsigned PtrAbbrev = Stream.EmitAbbrev(Abbv);
 
@@ -214,8 +215,8 @@
   Abbv->Add(BitCodeAbbrevOp(bitc::TYPE_CODE_FUNCTION));
   Abbv->Add(BitCodeAbbrevOp(BitCodeAbbrevOp::Fixed, 1));  // isvararg
   Abbv->Add(BitCodeAbbrevOp(BitCodeAbbrevOp::Array));
-  Abbv->Add(BitCodeAbbrevOp(BitCodeAbbrevOp::Fixed,
-                            Log2_32_Ceil(VE.getTypes().size()+1)));
+  Abbv->Add(BitCodeAbbrevOp(BitCodeAbbrevOp::Fixed, NumBits));
+
   unsigned FunctionAbbrev = Stream.EmitAbbrev(Abbv);
 
   // Abbrev for TYPE_CODE_STRUCT_ANON.
@@ -223,8 +224,8 @@
   Abbv->Add(BitCodeAbbrevOp(bitc::TYPE_CODE_STRUCT_ANON));
   Abbv->Add(BitCodeAbbrevOp(BitCodeAbbrevOp::Fixed, 1));  // ispacked
   Abbv->Add(BitCodeAbbrevOp(BitCodeAbbrevOp::Array));
-  Abbv->Add(BitCodeAbbrevOp(BitCodeAbbrevOp::Fixed,
-                            Log2_32_Ceil(VE.getTypes().size()+1)));
+  Abbv->Add(BitCodeAbbrevOp(BitCodeAbbrevOp::Fixed, NumBits));
+
   unsigned StructAnonAbbrev = Stream.EmitAbbrev(Abbv);
 
   // Abbrev for TYPE_CODE_STRUCT_NAME.
@@ -239,16 +240,16 @@
   Abbv->Add(BitCodeAbbrevOp(bitc::TYPE_CODE_STRUCT_NAMED));
   Abbv->Add(BitCodeAbbrevOp(BitCodeAbbrevOp::Fixed, 1));  // ispacked
   Abbv->Add(BitCodeAbbrevOp(BitCodeAbbrevOp::Array));
-  Abbv->Add(BitCodeAbbrevOp(BitCodeAbbrevOp::Fixed,
-                            Log2_32_Ceil(VE.getTypes().size()+1)));
+  Abbv->Add(BitCodeAbbrevOp(BitCodeAbbrevOp::Fixed, NumBits));
+
   unsigned StructNamedAbbrev = Stream.EmitAbbrev(Abbv);
   
   // Abbrev for TYPE_CODE_ARRAY.
   Abbv = new BitCodeAbbrev();
   Abbv->Add(BitCodeAbbrevOp(bitc::TYPE_CODE_ARRAY));
   Abbv->Add(BitCodeAbbrevOp(BitCodeAbbrevOp::VBR, 8));   // size
-  Abbv->Add(BitCodeAbbrevOp(BitCodeAbbrevOp::Fixed,
-                            Log2_32_Ceil(VE.getTypes().size()+1)));
+  Abbv->Add(BitCodeAbbrevOp(BitCodeAbbrevOp::Fixed, NumBits));
+
   unsigned ArrayAbbrev = Stream.EmitAbbrev(Abbv);
 
   // Emit an entry count so the reader can reserve space.



From grosbach at apple.com  Wed Dec  7 18:41:54 2011
From: grosbach at apple.com (Jim Grosbach)
Date: Thu, 08 Dec 2011 00:41:54 -0000
Subject: [llvm-commits] [llvm] r146113 -
	/llvm/trunk/test/MC/ARM/neon-shuffle-encoding.s
Message-ID: <20111208004154.6E7892A6C12C@llvm.org>

Author: grosbach
Date: Wed Dec  7 18:41:54 2011
New Revision: 146113

URL: http://llvm.org/viewvc/llvm-project?rev=146113&view=rev
Log:
Tidy up.

Modified:
    llvm/trunk/test/MC/ARM/neon-shuffle-encoding.s

Modified: llvm/trunk/test/MC/ARM/neon-shuffle-encoding.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/neon-shuffle-encoding.s?rev=146113&r1=146112&r2=146113&view=diff
==============================================================================
--- llvm/trunk/test/MC/ARM/neon-shuffle-encoding.s (original)
+++ llvm/trunk/test/MC/ARM/neon-shuffle-encoding.s Wed Dec  7 18:41:54 2011
@@ -1,50 +1,57 @@
 @ RUN: llvm-mc -mcpu=cortex-a8 -triple arm-unknown-unknown -show-encoding < %s | FileCheck %s
 
-@ CHECK: vext.8	d16, d17, d16, #3       @ encoding: [0xa0,0x03,0xf1,0xf2]
 	vext.8	d16, d17, d16, #3
-@ CHECK: vext.8	d16, d17, d16, #5       @ encoding: [0xa0,0x05,0xf1,0xf2]
 	vext.8	d16, d17, d16, #5
-@ CHECK: vext.8	q8, q9, q8, #3          @ encoding: [0xe0,0x03,0xf2,0xf2]
 	vext.8	q8, q9, q8, #3
-@ CHECK: vext.8	q8, q9, q8, #7          @ encoding: [0xe0,0x07,0xf2,0xf2]
 	vext.8	q8, q9, q8, #7
-@ CHECK: vext.16	d16, d17, d16, #3       @ encoding: [0xa0,0x06,0xf1,0xf2]
 	vext.16	d16, d17, d16, #3
-@ CHECK: vext.32	q8, q9, q8, #3          @ encoding: [0xe0,0x0c,0xf2,0xf2]
 	vext.32	q8, q9, q8, #3
-@ CHECK: vtrn.8	d17, d16                @ encoding: [0xa0,0x10,0xf2,0xf3]
+
+@ CHECK: vext.8	d16, d17, d16, #3       @ encoding: [0xa0,0x03,0xf1,0xf2]
+@ CHECK: vext.8	d16, d17, d16, #5       @ encoding: [0xa0,0x05,0xf1,0xf2]
+@ CHECK: vext.8	q8, q9, q8, #3          @ encoding: [0xe0,0x03,0xf2,0xf2]
+@ CHECK: vext.8	q8, q9, q8, #7          @ encoding: [0xe0,0x07,0xf2,0xf2]
+@ CHECK: vext.16 d16, d17, d16, #3      @ encoding: [0xa0,0x06,0xf1,0xf2]
+@ CHECK: vext.32 q8, q9, q8, #3         @ encoding: [0xe0,0x0c,0xf2,0xf2]
+
+
 	vtrn.8	d17, d16
-@ CHECK: vtrn.16	d17, d16                @ encoding: [0xa0,0x10,0xf6,0xf3]
 	vtrn.16	d17, d16
-@ CHECK: vtrn.32	d17, d16                @ encoding: [0xa0,0x10,0xfa,0xf3]
 	vtrn.32	d17, d16
-@ CHECK: vtrn.8	q9, q8                  @ encoding: [0xe0,0x20,0xf2,0xf3]
 	vtrn.8	q9, q8
-@ CHECK: vtrn.16	q9, q8                  @ encoding: [0xe0,0x20,0xf6,0xf3]
 	vtrn.16	q9, q8
-@ CHECK: vtrn.32	q9, q8                  @ encoding: [0xe0,0x20,0xfa,0xf3]
 	vtrn.32	q9, q8
-@ CHECK: vuzp.8	d17, d16                @ encoding: [0x20,0x11,0xf2,0xf3]
+
+@ CHECK: vtrn.8	d17, d16                @ encoding: [0xa0,0x10,0xf2,0xf3]
+@ CHECK: vtrn.16 d17, d16               @ encoding: [0xa0,0x10,0xf6,0xf3]
+@ CHECK: vtrn.32 d17, d16               @ encoding: [0xa0,0x10,0xfa,0xf3]
+@ CHECK: vtrn.8	q9, q8                  @ encoding: [0xe0,0x20,0xf2,0xf3]
+@ CHECK: vtrn.16 q9, q8                 @ encoding: [0xe0,0x20,0xf6,0xf3]
+@ CHECK: vtrn.32 q9, q8                 @ encoding: [0xe0,0x20,0xfa,0xf3]
+
+
 	vuzp.8	d17, d16
-@ CHECK: vuzp.16	d17, d16                @ encoding: [0x20,0x11,0xf6,0xf3]
 	vuzp.16	d17, d16
-@ CHECK: vuzp.8	q9, q8                  @ encoding: [0x60,0x21,0xf2,0xf3]
 	vuzp.8	q9, q8
-@ CHECK: vuzp.16	q9, q8                  @ encoding: [0x60,0x21,0xf6,0xf3]
 	vuzp.16	q9, q8
-@ CHECK: vuzp.32	q9, q8                  @ encoding: [0x60,0x21,0xfa,0xf3]
 	vuzp.32	q9, q8
-@ CHECK: vzip.8	d17, d16                @ encoding: [0xa0,0x11,0xf2,0xf3]
 	vzip.8	d17, d16
-@ CHECK: vzip.16	d17, d16                @ encoding: [0xa0,0x11,0xf6,0xf3]
 	vzip.16	d17, d16
-@ CHECK: vzip.8	q9, q8                  @ encoding: [0xe0,0x21,0xf2,0xf3]
 	vzip.8	q9, q8
-@ CHECK: vzip.16	q9, q8                  @ encoding: [0xe0,0x21,0xf6,0xf3]
 	vzip.16	q9, q8
-@ CHECK: vzip.32	q9, q8                  @ encoding: [0xe0,0x21,0xfa,0xf3]
 	vzip.32	q9, q8
 
+@ CHECK: vuzp.8	d17, d16                @ encoding: [0x20,0x11,0xf2,0xf3]
+@ CHECK: vuzp.16 d17, d16               @ encoding: [0x20,0x11,0xf6,0xf3]
+@ CHECK: vuzp.8	q9, q8                  @ encoding: [0x60,0x21,0xf2,0xf3]
+@ CHECK: vuzp.16 q9, q8                 @ encoding: [0x60,0x21,0xf6,0xf3]
+@ CHECK: vuzp.32 q9, q8                 @ encoding: [0x60,0x21,0xfa,0xf3]
+@ CHECK: vzip.8	d17, d16                @ encoding: [0xa0,0x11,0xf2,0xf3]
+@ CHECK: vzip.16 d17, d16               @ encoding: [0xa0,0x11,0xf6,0xf3]
+@ CHECK: vzip.8	q9, q8                  @ encoding: [0xe0,0x21,0xf2,0xf3]
+@ CHECK: vzip.16 q9, q8                 @ encoding: [0xe0,0x21,0xf6,0xf3]
+@ CHECK: vzip.32 q9, q8                 @ encoding: [0xe0,0x21,0xfa,0xf3]
+
 
 @ VTRN alternate size suffices
 



From grosbach at apple.com  Wed Dec  7 18:43:47 2011
From: grosbach at apple.com (Jim Grosbach)
Date: Thu, 08 Dec 2011 00:43:47 -0000
Subject: [llvm-commits] [llvm] r146114 - in /llvm/trunk:
 lib/Target/ARM/ARMInstrNEON.td test/MC/ARM/neon-shuffle-encoding.s
Message-ID: <20111208004347.838CF2A6C12C@llvm.org>

Author: grosbach
Date: Wed Dec  7 18:43:47 2011
New Revision: 146114

URL: http://llvm.org/viewvc/llvm-project?rev=146114&view=rev
Log:
ARM optional destination operand variants for VEXT instructions.

Modified:
    llvm/trunk/lib/Target/ARM/ARMInstrNEON.td
    llvm/trunk/test/MC/ARM/neon-shuffle-encoding.s

Modified: llvm/trunk/lib/Target/ARM/ARMInstrNEON.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrNEON.td?rev=146114&r1=146113&r2=146114&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrNEON.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrNEON.td Wed Dec  7 18:43:47 2011
@@ -5491,3 +5491,20 @@
                     (VCGTuv4i32 QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p)>;
 def : NEONInstAlias<"vclt${p}.f32 $Qd, $Qn, $Qm",
                     (VCGTfq QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p)>;
+
+// Two-operand variants for VEXT
+def : NEONInstAlias<"vext${p}.8 $Vdn, $Vm, $imm",
+                  (VEXTd8 DPR:$Vdn, DPR:$Vdn, DPR:$Vm, imm0_7:$imm, pred:$p)>;
+def : NEONInstAlias<"vext${p}.16 $Vdn, $Vm, $imm",
+                  (VEXTd16 DPR:$Vdn, DPR:$Vdn, DPR:$Vm, imm0_3:$imm, pred:$p)>;
+def : NEONInstAlias<"vext${p}.32 $Vdn, $Vm, $imm",
+                  (VEXTd32 DPR:$Vdn, DPR:$Vdn, DPR:$Vm, imm0_1:$imm, pred:$p)>;
+
+def : NEONInstAlias<"vext${p}.8 $Vdn, $Vm, $imm",
+                  (VEXTq8 QPR:$Vdn, QPR:$Vdn, QPR:$Vm, imm0_15:$imm, pred:$p)>;
+def : NEONInstAlias<"vext${p}.16 $Vdn, $Vm, $imm",
+                  (VEXTq16 QPR:$Vdn, QPR:$Vdn, QPR:$Vm, imm0_7:$imm, pred:$p)>;
+def : NEONInstAlias<"vext${p}.32 $Vdn, $Vm, $imm",
+                  (VEXTq32 QPR:$Vdn, QPR:$Vdn, QPR:$Vm, imm0_3:$imm, pred:$p)>;
+def : NEONInstAlias<"vext${p}.64 $Vdn, $Vm, $imm",
+                  (VEXTq64 QPR:$Vdn, QPR:$Vdn, QPR:$Vm, imm0_1:$imm, pred:$p)>;

Modified: llvm/trunk/test/MC/ARM/neon-shuffle-encoding.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/neon-shuffle-encoding.s?rev=146114&r1=146113&r2=146114&view=diff
==============================================================================
--- llvm/trunk/test/MC/ARM/neon-shuffle-encoding.s (original)
+++ llvm/trunk/test/MC/ARM/neon-shuffle-encoding.s Wed Dec  7 18:43:47 2011
@@ -7,6 +7,14 @@
 	vext.16	d16, d17, d16, #3
 	vext.32	q8, q9, q8, #3
 
+	vext.8	d17, d16, #3
+	vext.8	d7, d11, #5
+	vext.8	q3, q8, #3
+	vext.8	q9, q4, #7
+	vext.16	d1, d26, #3
+	vext.32	q5, q8, #3
+
+
 @ CHECK: vext.8	d16, d17, d16, #3       @ encoding: [0xa0,0x03,0xf1,0xf2]
 @ CHECK: vext.8	d16, d17, d16, #5       @ encoding: [0xa0,0x05,0xf1,0xf2]
 @ CHECK: vext.8	q8, q9, q8, #3          @ encoding: [0xe0,0x03,0xf2,0xf2]
@@ -14,6 +22,13 @@
 @ CHECK: vext.16 d16, d17, d16, #3      @ encoding: [0xa0,0x06,0xf1,0xf2]
 @ CHECK: vext.32 q8, q9, q8, #3         @ encoding: [0xe0,0x0c,0xf2,0xf2]
 
+@ CHECK: vext.8	d17, d17, d16, #3       @ encoding: [0xa0,0x13,0xf1,0xf2]
+@ CHECK: vext.8	d7, d7, d11, #5         @ encoding: [0x0b,0x75,0xb7,0xf2]
+@ CHECK: vext.8	q3, q3, q8, #3          @ encoding: [0x60,0x63,0xb6,0xf2]
+@ CHECK: vext.8	q9, q9, q4, #7          @ encoding: [0xc8,0x27,0xf2,0xf2]
+@ CHECK: vext.16 d1, d1, d26, #3        @ encoding: [0x2a,0x16,0xb1,0xf2]
+@ CHECK: vext.32 q5, q5, q8, #3         @ encoding: [0x60,0xac,0xba,0xf2]
+
 
 	vtrn.8	d17, d16
 	vtrn.16	d17, d16



From grosbach at apple.com  Wed Dec  7 18:49:29 2011
From: grosbach at apple.com (Jim Grosbach)
Date: Thu, 08 Dec 2011 00:49:29 -0000
Subject: [llvm-commits] [llvm] r146115 - in /llvm/trunk/lib/Target/ARM:
 ARMInstrVFP.td AsmParser/ARMAsmParser.cpp
Message-ID: <20111208004929.6D80B2A6C12C@llvm.org>

Author: grosbach
Date: Wed Dec  7 18:49:29 2011
New Revision: 146115

URL: http://llvm.org/viewvc/llvm-project?rev=146115&view=rev
Log:
ARM VFP support 'flds/fldd' aliases for 'vldr'

Modified:
    llvm/trunk/lib/Target/ARM/ARMInstrVFP.td
    llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp

Modified: llvm/trunk/lib/Target/ARM/ARMInstrVFP.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrVFP.td?rev=146115&r1=146114&r2=146115&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrVFP.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrVFP.td Wed Dec  7 18:49:29 2011
@@ -1161,6 +1161,12 @@
 // Assembler aliases.
 //
 
+// A few mnemnoic aliases for pre-unifixed syntax. We don't guarantee to
+// support them all, but supporting at least some of the basics is
+// good to be friendly.
+def : MnemonicAlias<"flds", "vldr">;
+def : MnemonicAlias<"fldd", "vldr">;
+
 def : VFP2InstAlias<"fmstat${p}", (FMSTAT pred:$p)>;
 
 // VLDR/VSTR accept an optional type suffix.

Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp?rev=146115&r1=146114&r2=146115&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp (original)
+++ llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Wed Dec  7 18:49:29 2011
@@ -4235,7 +4235,7 @@
         Mnemonic == "mrs" || Mnemonic == "smmls" || Mnemonic == "vabs" ||
         Mnemonic == "vcls" || Mnemonic == "vmls" || Mnemonic == "vmrs" ||
         Mnemonic == "vnmls" || Mnemonic == "vqabs" || Mnemonic == "vrecps" ||
-        Mnemonic == "vrsqrts" || Mnemonic == "srs" ||
+        Mnemonic == "vrsqrts" || Mnemonic == "srs" || Mnemonic == "flds" ||
         (Mnemonic == "movs" && isThumb()))) {
     Mnemonic = Mnemonic.slice(0, Mnemonic.size() - 1);
     CarrySetting = true;



From grosbach at apple.com  Wed Dec  7 18:52:55 2011
From: grosbach at apple.com (Jim Grosbach)
Date: Thu, 08 Dec 2011 00:52:55 -0000
Subject: [llvm-commits] [llvm] r146116 - in /llvm/trunk/lib/Target/ARM:
 ARMInstrVFP.td AsmParser/ARMAsmParser.cpp
Message-ID: <20111208005255.77B182A6C12C@llvm.org>

Author: grosbach
Date: Wed Dec  7 18:52:55 2011
New Revision: 146116

URL: http://llvm.org/viewvc/llvm-project?rev=146116&view=rev
Log:
ARM VFP support 'fmrs/fmsr' aliases for 'vldr'

Modified:
    llvm/trunk/lib/Target/ARM/ARMInstrVFP.td
    llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp

Modified: llvm/trunk/lib/Target/ARM/ARMInstrVFP.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrVFP.td?rev=146116&r1=146115&r2=146116&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrVFP.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrVFP.td Wed Dec  7 18:52:55 2011
@@ -1166,6 +1166,8 @@
 // good to be friendly.
 def : MnemonicAlias<"flds", "vldr">;
 def : MnemonicAlias<"fldd", "vldr">;
+def : MnemonicAlias<"fmrs", "vmov">;
+def : MnemonicAlias<"fmsr", "vmov">;
 
 def : VFP2InstAlias<"fmstat${p}", (FMSTAT pred:$p)>;
 

Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp?rev=146116&r1=146115&r2=146116&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp (original)
+++ llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Wed Dec  7 18:52:55 2011
@@ -4236,6 +4236,7 @@
         Mnemonic == "vcls" || Mnemonic == "vmls" || Mnemonic == "vmrs" ||
         Mnemonic == "vnmls" || Mnemonic == "vqabs" || Mnemonic == "vrecps" ||
         Mnemonic == "vrsqrts" || Mnemonic == "srs" || Mnemonic == "flds" ||
+        Mnemonic == "fmrs" ||
         (Mnemonic == "movs" && isThumb()))) {
     Mnemonic = Mnemonic.slice(0, Mnemonic.size() - 1);
     CarrySetting = true;



From stoklund at 2pi.dk  Wed Dec  7 18:55:02 2011
From: stoklund at 2pi.dk (Jakob Stoklund Olesen)
Date: Thu, 08 Dec 2011 00:55:02 -0000
Subject: [llvm-commits] [llvm] r146118 -
	/llvm/trunk/lib/Target/ARM/ARMConstantIslandPass.cpp
Message-ID: <20111208005502.5BC902A6C12C@llvm.org>

Author: stoklund
Date: Wed Dec  7 18:55:02 2011
New Revision: 146118

URL: http://llvm.org/viewvc/llvm-project?rev=146118&view=rev
Log:
Don't include alignment padding in BBInfo.Size.

Compute alignment padding before and after basic blocks dynamically.

Heed basic block alignment.

This simplifies bookkeeping because we don't have to constantly add and
remove padding from BBInfo.Size.  It also makes it possible to track the
extra known alignment bits we get after a tBR_JTr terminator and when
entering an aligned basic block.

This makes the ARMConstantIslandPass aware of aligned basic blocks.

It is tricky to model block alignment correctly when dealing with inline
assembly and tBR_JTr instructions that have variable size.  If inline
assembly turns out to be smaller than expected, that may cause following
alignment padding to be larger than expected.  This could cause constant
pool entries to move out of range.

To avoid that problem, we use the worst case alignment padding following
inline assembly. This may cause slightly suboptimal constant island
placement in aligned basic blocks following inline assembly.  Normal
functions should be unaffected.

Modified:
    llvm/trunk/lib/Target/ARM/ARMConstantIslandPass.cpp

Modified: llvm/trunk/lib/Target/ARM/ARMConstantIslandPass.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMConstantIslandPass.cpp?rev=146118&r1=146117&r2=146118&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMConstantIslandPass.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMConstantIslandPass.cpp Wed Dec  7 18:55:02 2011
@@ -51,6 +51,28 @@
 AdjustJumpTableBlocks("arm-adjust-jump-tables", cl::Hidden, cl::init(true),
           cl::desc("Adjust basic block layout to better use TB[BH]"));
 
+/// WorstCaseAlign - Assuming only the low KnownBits bits in Offset are exact,
+/// add padding such that:
+///
+/// 1. The result is aligned to 1 << LogAlign.
+///
+/// 2. No other value of the unknown bits would require more padding.
+///
+/// This may add more padding than is required to satisfy just one of the
+/// constraints.  It is necessary to compute alignment this way to guarantee
+/// that we don't underestimate the padding before an aligned block.  If the
+/// real padding before a block is larger than we think, constant pool entries
+/// may go out of range.
+static inline unsigned WorstCaseAlign(unsigned Offset, unsigned LogAlign,
+                                      unsigned KnownBits) {
+  // Add the worst possible padding that the unknown bits could cause.
+  if (KnownBits < LogAlign)
+    Offset += (1u << LogAlign) - (1u << KnownBits);
+
+  // Then align the result.
+  return RoundUpToAlignment(Offset, 1u << LogAlign);
+}
+
 namespace {
   /// ARMConstantIslands - Due to limited PC-relative displacements, ARM
   /// requires constant pool entries to be scattered among the instructions
@@ -70,18 +92,20 @@
       /// Offset - Distance from the beginning of the function to the beginning
       /// of this basic block.
       ///
-      /// The two-byte pads required for Thumb alignment are counted as part of
-      /// the following block.
+      /// The offset is always aligned as required by the basic block.
       unsigned Offset;
 
       /// Size - Size of the basic block in bytes.  If the block contains
       /// inline assembly, this is a worst case estimate.
       ///
-      /// The two-byte pads required for Thumb alignment are counted as part of
-      /// the following block (i.e., the offset and size for a padded block
-      /// will both be ==2 mod 4).
+      /// The size does not include any alignment padding whether from the
+      /// beginning of the block, or from an aligned jump table at the end.
       unsigned Size;
 
+      /// KnownBits - The number of low bits in Offset that are known to be
+      /// exact.  The remaining bits of Offset are an upper bound.
+      uint8_t KnownBits;
+
       /// Unalign - When non-zero, the block contains instructions (inline asm)
       /// of unknown size.  The real size may be smaller than Size bytes by a
       /// multiple of 1 << Unalign.
@@ -92,10 +116,25 @@
       /// bytes.
       uint8_t PostAlign;
 
-      BasicBlockInfo() : Offset(0), Size(0), Unalign(0), PostAlign(0) {}
+      BasicBlockInfo() : Offset(0), Size(0), KnownBits(0), Unalign(0),
+        PostAlign(0) {}
 
       /// Compute the offset immediately following this block.
-      unsigned postOffset() const { return Offset + Size; }
+      unsigned postOffset() const {
+        unsigned PO = Offset + Size;
+        if (!PostAlign)
+          return PO;
+        // Add alignment padding from the terminator.
+        return WorstCaseAlign(PO, PostAlign, Unalign ? Unalign : KnownBits);
+      }
+
+      /// Compute the number of known low bits of postOffset.  If this block
+      /// contains inline asm, the number of known bits drops to the
+      /// instruction alignment.  An aligned terminator may increase the number
+      /// of know bits.
+      unsigned postKnownBits() const {
+        return std::max(PostAlign, Unalign ? Unalign : KnownBits);
+      }
     };
 
     std::vector BBInfo;
@@ -243,7 +282,7 @@
     MachineBasicBlock *AdjustJTTargetBlockForward(MachineBasicBlock *BB,
                                                   MachineBasicBlock *JTBB);
 
-    void ComputeBlockSize(const MachineBasicBlock *MBB);
+    void ComputeBlockSize(MachineBasicBlock *MBB);
     unsigned GetOffsetOf(MachineInstr *MI) const;
     void dumpBBs();
     void verify(MachineFunction &MF);
@@ -253,8 +292,6 @@
 
 /// verify - check BBOffsets, BBSizes, alignment of islands
 void ARMConstantIslands::verify(MachineFunction &MF) {
-  for (unsigned i = 1, e = BBInfo.size(); i != e; ++i)
-    assert(BBInfo[i-1].postOffset() == BBInfo[i].Offset);
   if (!isThumb)
     return;
 #ifndef NDEBUG
@@ -505,46 +542,37 @@
 /// and finding all of the constant pool users.
 void ARMConstantIslands::InitialFunctionScan(MachineFunction &MF,
                                  const std::vector &CPEMIs) {
-  // First thing, see if the function has any inline assembly in it. If so,
-  // we have to be conservative about alignment assumptions, as we don't
-  // know for sure the size of any instructions in the inline assembly.
-  for (MachineFunction::iterator MBBI = MF.begin(), E = MF.end();
-       MBBI != E; ++MBBI) {
-    MachineBasicBlock &MBB = *MBBI;
-    for (MachineBasicBlock::iterator I = MBB.begin(), E = MBB.end();
-         I != E; ++I)
-      if (I->getOpcode() == ARM::INLINEASM)
-        HasInlineAsm = true;
-  }
-
   BBInfo.clear();
   BBInfo.resize(MF.getNumBlockIDs());
 
+  // First thing, compute the size of all basic blocks, and see if the function
+  // has any inline assembly in it. If so, we have to be conservative about
+  // alignment assumptions, as we don't know for sure the size of any
+  // instructions in the inline assembly.
+  for (MachineFunction::iterator I = MF.begin(), E = MF.end(); I != E; ++I)
+    ComputeBlockSize(I);
+
+  // The known bits of the entry block offset are determined by the function
+  // alignment.
+  BBInfo.front().KnownBits = MF.getAlignment();
+
+  // Compute block offsets and known bits.
+  AdjustBBOffsetsAfter(MF.begin());
+
   // Now go back through the instructions and build up our data structures.
-  unsigned Offset = 0;
   for (MachineFunction::iterator MBBI = MF.begin(), E = MF.end();
        MBBI != E; ++MBBI) {
     MachineBasicBlock &MBB = *MBBI;
-    BasicBlockInfo &BBI = BBInfo[MBB.getNumber()];
-    BBI.Offset = Offset;
 
     // If this block doesn't fall through into the next MBB, then this is
     // 'water' that a constant pool island could be placed.
     if (!BBHasFallthrough(&MBB))
       WaterList.push_back(&MBB);
 
-    unsigned MBBSize = 0;
     for (MachineBasicBlock::iterator I = MBB.begin(), E = MBB.end();
          I != E; ++I) {
       if (I->isDebugValue())
         continue;
-      // Add instruction size to MBBSize.
-      MBBSize += TII->GetInstSizeInBytes(I);
-
-      // For inline asm, GetInstSizeInBytes returns a conservative estimate.
-      // The actual size may be smaller, but still a multiple of the instr size.
-      if (I->isInlineAsm())
-        BBI.Unalign = isThumb ? 1 : 2;
 
       int Opc = I->getOpcode();
       if (I->isBranch()) {
@@ -555,19 +583,6 @@
         switch (Opc) {
         default:
           continue;  // Ignore other JT branches
-        case ARM::tBR_JTr:
-          // A Thumb1 table jump may involve padding; for the offsets to
-          // be right, functions containing these must be 4-byte aligned.
-          // tBR_JTr expands to a mov pc followed by .align 2 and then the jump
-          // table entries. So this code checks whether offset of tBR_JTr + 2
-          // is aligned.  That is held in Offset+MBBSize, which already has
-          // 2 added in for the size of the mov pc instruction.
-          MF.EnsureAlignment(2U);
-          BBI.PostAlign = 2;
-          if ((Offset+MBBSize)%4 != 0 || HasInlineAsm)
-            // FIXME: Add a pseudo ALIGN instruction instead.
-            MBBSize += 2;           // padding
-          continue;   // Does not get an entry in ImmBranches
         case ARM::t2BR_JT:
           T2JumpTables.push_back(I);
           continue;   // Does not get an entry in ImmBranches
@@ -685,40 +700,33 @@
           break;
         }
     }
-
-    // In thumb mode, if this block is a constpool island, we may need padding
-    // so it's aligned on 4 byte boundary.
-    if (isThumb &&
-        !MBB.empty() &&
-        MBB.begin()->getOpcode() == ARM::CONSTPOOL_ENTRY &&
-        ((Offset%4) != 0 || HasInlineAsm))
-      MBBSize += 2;
-
-    BBI.Size = MBBSize;
-    Offset += MBBSize;
   }
 }
 
 /// ComputeBlockSize - Compute the size and some alignment information for MBB.
 /// This function updates BBInfo directly.
-void ARMConstantIslands::ComputeBlockSize(const MachineBasicBlock *MBB) {
+void ARMConstantIslands::ComputeBlockSize(MachineBasicBlock *MBB) {
   BasicBlockInfo &BBI = BBInfo[MBB->getNumber()];
   BBI.Size = 0;
   BBI.Unalign = 0;
   BBI.PostAlign = 0;
 
-  for (MachineBasicBlock::const_iterator I = MBB->begin(), E = MBB->end();
-       I != E; ++I) {
+  for (MachineBasicBlock::iterator I = MBB->begin(), E = MBB->end(); I != E;
+       ++I) {
     BBI.Size += TII->GetInstSizeInBytes(I);
     // For inline asm, GetInstSizeInBytes returns a conservative estimate.
     // The actual size may be smaller, but still a multiple of the instr size.
-    if (I->isInlineAsm())
+    if (I->isInlineAsm()) {
       BBI.Unalign = isThumb ? 1 : 2;
+      HasInlineAsm = true;
+    }
   }
 
   // tBR_JTr contains a .align 2 directive.
-  if (!MBB->empty() && MBB->back().getOpcode() == ARM::tBR_JTr)
+  if (!MBB->empty() && MBB->back().getOpcode() == ARM::tBR_JTr) {
     BBI.PostAlign = 2;
+    MBB->getParent()->EnsureAlignment(2);
+  }
 }
 
 /// GetOffsetOf - Return the current offset of the specified machine instruction
@@ -732,13 +740,6 @@
   // it is in.
   unsigned Offset = BBInfo[MBB->getNumber()].Offset;
 
-  // If we're looking for a CONSTPOOL_ENTRY in Thumb, see if this block has
-  // alignment padding, and compensate if so.
-  if (isThumb &&
-      MI->getOpcode() == ARM::CONSTPOOL_ENTRY &&
-      (Offset%4 != 0 || HasInlineAsm))
-    Offset += 2;
-
   // Sum instructions before MI in MBB.
   for (MachineBasicBlock::iterator I = MBB->begin(); ; ++I) {
     assert(I != MBB->end() && "Didn't find MI in its own basic block?");
@@ -831,11 +832,6 @@
     WaterList.insert(IP, OrigBB);
   NewWaterList.insert(OrigBB);
 
-  unsigned OrigBBI = OrigBB->getNumber();
-  unsigned NewBBI = NewBB->getNumber();
-
-  int delta = isThumb1 ? 2 : 4;
-
   // Figure out how large the OrigBB is.  As the first half of the original
   // block, it cannot contain a tablejump.  The size includes
   // the new jump we added.  (It should be possible to do this without
@@ -843,33 +839,12 @@
   // executed.)
   ComputeBlockSize(OrigBB);
 
-  // ...and adjust BBOffsets for NewBB accordingly.
-  BBInfo[NewBBI].Offset = BBInfo[OrigBBI].postOffset();
-
   // Figure out how large the NewMBB is.  As the second half of the original
   // block, it may contain a tablejump.
   ComputeBlockSize(NewBB);
 
-  MachineInstr* ThumbJTMI = prior(NewBB->end());
-  if (ThumbJTMI->getOpcode() == ARM::tBR_JTr) {
-    // We've added another 2-byte instruction before this tablejump, which
-    // means we will always need padding if we didn't before, and vice versa.
-
-    // The original offset of the jump instruction was:
-    unsigned OrigOffset = BBInfo[OrigBBI].postOffset() - delta;
-    if (OrigOffset%4 == 0) {
-      // We had padding before and now we don't.  No net change in code size.
-      delta = 0;
-    } else {
-      // We didn't have padding before and now we do.
-      BBInfo[NewBBI].Size += 2;
-      delta = 4;
-    }
-  }
-
   // All BBOffsets following these blocks must be modified.
-  if (delta)
-    AdjustBBOffsetsAfter(NewBB);
+  AdjustBBOffsetsAfter(OrigBB);
 
   return NewBB;
 }
@@ -968,50 +943,21 @@
 #endif // NDEBUG
 
 void ARMConstantIslands::AdjustBBOffsetsAfter(MachineBasicBlock *BB) {
-  MachineFunction::iterator MBBI = BB; MBBI = llvm::next(MBBI);
-  for(unsigned i = BB->getNumber()+1, e = BB->getParent()->getNumBlockIDs();
-      i < e; ++i) {
-    unsigned OldOffset = BBInfo[i].Offset;
-    BBInfo[i].Offset = BBInfo[i-1].postOffset();
-    int delta = BBInfo[i].Offset - OldOffset;
-    // If some existing blocks have padding, adjust the padding as needed, a
-    // bit tricky.  delta can be negative so don't use % on that.
-    if (!isThumb)
-      continue;
-    MachineBasicBlock *MBB = MBBI;
-    if (!MBB->empty() && !HasInlineAsm) {
-      // Constant pool entries require padding.
-      if (MBB->begin()->getOpcode() == ARM::CONSTPOOL_ENTRY) {
-        if ((OldOffset%4) == 0 && (BBInfo[i].Offset%4) != 0) {
-          // add new padding
-          BBInfo[i].Size += 2;
-          delta += 2;
-        } else if ((OldOffset%4) != 0 && (BBInfo[i].Offset%4) == 0) {
-          // remove existing padding
-          BBInfo[i].Size -= 2;
-          delta -= 2;
-        }
-      }
-      // Thumb1 jump tables require padding.  They should be at the end;
-      // following unconditional branches are removed by AnalyzeBranch.
-      // tBR_JTr expands to a mov pc followed by .align 2 and then the jump
-      // table entries. So this code checks whether offset of tBR_JTr
-      // is aligned; if it is, the offset of the jump table following the
-      // instruction will not be aligned, and we need padding.
-      MachineInstr *ThumbJTMI = prior(MBB->end());
-      if (ThumbJTMI->getOpcode() == ARM::tBR_JTr) {
-        unsigned NewMIOffset = GetOffsetOf(ThumbJTMI);
-        unsigned OldMIOffset = NewMIOffset - delta;
-        if ((OldMIOffset%4) == 0 && (NewMIOffset%4) != 0) {
-          // remove existing padding
-          BBInfo[i].Size -= 2;
-        } else if ((OldMIOffset%4) != 0 && (NewMIOffset%4) == 0) {
-          // add new padding
-          BBInfo[i].Size += 2;
-        }
-      }
+  MachineFunction *MF = BB->getParent();
+  for(unsigned i = BB->getNumber() + 1, e = MF->getNumBlockIDs(); i < e; ++i) {
+    // Get the offset and known bits at the end of the layout predecessor.
+    unsigned Offset = BBInfo[i - 1].postOffset();
+    unsigned KnownBits = BBInfo[i - 1].postKnownBits();
+
+    // Add padding before an aligned block. This may teach us more bits.
+    if (unsigned Align = MF->getBlockNumbered(i)->getAlignment()) {
+      Offset = WorstCaseAlign(Offset, Align, KnownBits);
+      KnownBits = std::max(KnownBits, Align);
     }
-    MBBI = llvm::next(MBBI);
+
+    // This is where block i begins.
+    BBInfo[i].Offset = Offset;
+    BBInfo[i].KnownBits = KnownBits;
   }
 }
 
@@ -1163,7 +1109,6 @@
   MachineInstr *CPEMI  = U.CPEMI;
   MachineBasicBlock *UserMBB = UserMI->getParent();
   unsigned OffsetOfNextBlock = BBInfo[UserMBB->getNumber()].postOffset();
-  assert(OffsetOfNextBlock == BBInfo[UserMBB->getNumber()+1].Offset);
 
   // If the block does not end in an unconditional branch already, and if the
   // end of the block is within range, make new water there.  (The addition
@@ -1351,13 +1296,9 @@
   // Mark the basic block as 4-byte aligned as required by the const-pool entry.
   NewIsland->setAlignment(2);
 
-  BBInfo[NewIsland->getNumber()].Offset = BBInfo[NewMBB->getNumber()].Offset;
-  // Compensate for .align 2 in thumb mode.
-  if (isThumb && (BBInfo[NewIsland->getNumber()].Offset%4 != 0 || HasInlineAsm))
-    Size += 2;
   // Increase the size of the island block to account for the new entry.
   BBInfo[NewIsland->getNumber()].Size += Size;
-  AdjustBBOffsetsAfter(NewIsland);
+  AdjustBBOffsetsAfter(llvm::prior(MachineFunction::iterator(NewIsland)));
 
   // Finally, change the CPI in the instruction operand to be ID.
   for (unsigned i = 0, e = UserMI->getNumOperands(); i != e; ++i)



From grosbach at apple.com  Wed Dec  7 18:59:47 2011
From: grosbach at apple.com (Jim Grosbach)
Date: Thu, 08 Dec 2011 00:59:47 -0000
Subject: [llvm-commits] [llvm] r146119 -
	/llvm/trunk/lib/Target/ARM/ARMInstrNEON.td
Message-ID: <20111208005947.A435F2A6C12C@llvm.org>

Author: grosbach
Date: Wed Dec  7 18:59:47 2011
New Revision: 146119

URL: http://llvm.org/viewvc/llvm-project?rev=146119&view=rev
Log:
ARM NEON two-operand aliases for VMUL.

Modified:
    llvm/trunk/lib/Target/ARM/ARMInstrNEON.td

Modified: llvm/trunk/lib/Target/ARM/ARMInstrNEON.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrNEON.td?rev=146119&r1=146118&r2=146119&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrNEON.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrNEON.td Wed Dec  7 18:59:47 2011
@@ -5376,6 +5376,11 @@
                          (VORRq QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>;
 
 // VMUL two-operand aliases.
+def : NEONInstAlias<"vmul${p}.f32 $Qdn, $Qm",
+                    (VMULfq QPR:$Qdn, QPR:$Qdn, QPR:$Qm, pred:$p)>;
+def : NEONInstAlias<"vmul${p}.f32 $Ddn, $Dm",
+                    (VMULfd DPR:$Ddn, DPR:$Ddn, DPR:$Dm, pred:$p)>;
+
 def : NEONInstAlias<"vmul${p}.i16 $Ddn, $Dm$lane",
                     (VMULslv4i16 DPR:$Ddn, DPR:$Ddn, DPR_8:$Dm,
                                  VectorIndex16:$lane, pred:$p)>;



From grosbach at apple.com  Wed Dec  7 19:02:27 2011
From: grosbach at apple.com (Jim Grosbach)
Date: Thu, 08 Dec 2011 01:02:27 -0000
Subject: [llvm-commits] [llvm] r146120 -
	/llvm/trunk/lib/Target/ARM/ARMInstrNEON.td
Message-ID: <20111208010227.41C992A6C12C@llvm.org>

Author: grosbach
Date: Wed Dec  7 19:02:26 2011
New Revision: 146120

URL: http://llvm.org/viewvc/llvm-project?rev=146120&view=rev
Log:
Fix copy/past-o.

Modified:
    llvm/trunk/lib/Target/ARM/ARMInstrNEON.td

Modified: llvm/trunk/lib/Target/ARM/ARMInstrNEON.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrNEON.td?rev=146120&r1=146119&r2=146120&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrNEON.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrNEON.td Wed Dec  7 19:02:26 2011
@@ -5357,9 +5357,9 @@
                     (VEORd DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;
 def : NEONInstAlias<"veor${p} $Vdn, $Vm",
                     (VEORq QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>;
-def : NEONInstAlias<"vand${p} $Vdn, $Vm",
+def : NEONInstAlias<"vorr${p} $Vdn, $Vm",
                     (VORRd DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;
-def : NEONInstAlias<"vand${p} $Vdn, $Vm",
+def : NEONInstAlias<"vorr${p} $Vdn, $Vm",
                     (VORRq QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>;
 
 defm : VFPDTAnyInstAlias<"vand${p}", "$Vdn, $Vm",



From stoklund at 2pi.dk  Wed Dec  7 19:10:05 2011
From: stoklund at 2pi.dk (Jakob Stoklund Olesen)
Date: Thu, 08 Dec 2011 01:10:05 -0000
Subject: [llvm-commits] [llvm] r146121 -
	/llvm/trunk/lib/Target/ARM/ARMConstantIslandPass.cpp
Message-ID: <20111208011005.661A72A6C12C@llvm.org>

Author: stoklund
Date: Wed Dec  7 19:10:05 2011
New Revision: 146121

URL: http://llvm.org/viewvc/llvm-project?rev=146121&view=rev
Log:
Simplify offset verification.

Modified:
    llvm/trunk/lib/Target/ARM/ARMConstantIslandPass.cpp

Modified: llvm/trunk/lib/Target/ARM/ARMConstantIslandPass.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMConstantIslandPass.cpp?rev=146121&r1=146120&r2=146121&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMConstantIslandPass.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMConstantIslandPass.cpp Wed Dec  7 19:10:05 2011
@@ -292,19 +292,14 @@
 
 /// verify - check BBOffsets, BBSizes, alignment of islands
 void ARMConstantIslands::verify(MachineFunction &MF) {
-  if (!isThumb)
-    return;
 #ifndef NDEBUG
   for (MachineFunction::iterator MBBI = MF.begin(), E = MF.end();
        MBBI != E; ++MBBI) {
     MachineBasicBlock *MBB = MBBI;
-    if (!MBB->empty() &&
-        MBB->begin()->getOpcode() == ARM::CONSTPOOL_ENTRY) {
-      unsigned MBBId = MBB->getNumber();
-      assert(HasInlineAsm ||
-             (BBInfo[MBBId].Offset%4 == 0 && BBInfo[MBBId].Size%4 == 0) ||
-             (BBInfo[MBBId].Offset%4 != 0 && BBInfo[MBBId].Size%4 != 0));
-    }
+    unsigned Align = MBB->getAlignment();
+    unsigned MBBId = MBB->getNumber();
+    assert(BBInfo[MBBId].Offset % (1u << Align) == 0);
+    assert(!MBBId || BBInfo[MBBId - 1].postOffset() <= BBInfo[MBBId].Offset);
   }
   for (unsigned i = 0, e = CPUsers.size(); i != e; ++i) {
     CPUser &U = CPUsers[i];



From grosbach at apple.com  Wed Dec  7 19:12:36 2011
From: grosbach at apple.com (Jim Grosbach)
Date: Thu, 08 Dec 2011 01:12:36 -0000
Subject: [llvm-commits] [llvm] r146123 - in /llvm/trunk:
 lib/Target/ARM/ARMInstrNEON.td test/MC/ARM/neon-shift-encoding.s
Message-ID: <20111208011236.8E36B2A6C12C@llvm.org>

Author: grosbach
Date: Wed Dec  7 19:12:35 2011
New Revision: 146123

URL: http://llvm.org/viewvc/llvm-project?rev=146123&view=rev
Log:
ARM NEON two-operand aliases for VSHL(register).

Modified:
    llvm/trunk/lib/Target/ARM/ARMInstrNEON.td
    llvm/trunk/test/MC/ARM/neon-shift-encoding.s

Modified: llvm/trunk/lib/Target/ARM/ARMInstrNEON.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrNEON.td?rev=146123&r1=146122&r2=146123&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrNEON.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrNEON.td Wed Dec  7 19:12:35 2011
@@ -5402,6 +5402,41 @@
                     (VMULslfq QPR:$Qdn, QPR:$Qdn, DPR_VFP2:$Dm,
                               VectorIndex32:$lane, pred:$p)>;
 
+// VSHL (register) two-operand aliases.
+def : NEONInstAlias<"vshl${p}.s8 $Vdn, $Vm",
+                    (VSHLsv8i8 DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;
+def : NEONInstAlias<"vshl${p}.s16 $Vdn, $Vm",
+                    (VSHLsv4i16 DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;
+def : NEONInstAlias<"vshl${p}.s32 $Vdn, $Vm",
+                    (VSHLsv2i32 DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;
+def : NEONInstAlias<"vshl${p}.s64 $Vdn, $Vm",
+                    (VSHLsv1i64 DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;
+def : NEONInstAlias<"vshl${p}.u8 $Vdn, $Vm",
+                    (VSHLuv8i8 DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;
+def : NEONInstAlias<"vshl${p}.u16 $Vdn, $Vm",
+                    (VSHLuv4i16 DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;
+def : NEONInstAlias<"vshl${p}.u32 $Vdn, $Vm",
+                    (VSHLuv2i32 DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;
+def : NEONInstAlias<"vshl${p}.u64 $Vdn, $Vm",
+                    (VSHLuv1i64 DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;
+
+def : NEONInstAlias<"vshl${p}.s8 $Vdn, $Vm",
+                    (VSHLsv16i8 QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>;
+def : NEONInstAlias<"vshl${p}.s16 $Vdn, $Vm",
+                    (VSHLsv8i16 QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>;
+def : NEONInstAlias<"vshl${p}.s32 $Vdn, $Vm",
+                    (VSHLsv4i32 QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>;
+def : NEONInstAlias<"vshl${p}.s64 $Vdn, $Vm",
+                    (VSHLsv2i64 QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>;
+def : NEONInstAlias<"vshl${p}.u8 $Vdn, $Vm",
+                    (VSHLuv16i8 QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>;
+def : NEONInstAlias<"vshl${p}.u16 $Vdn, $Vm",
+                    (VSHLuv8i16 QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>;
+def : NEONInstAlias<"vshl${p}.u32 $Vdn, $Vm",
+                    (VSHLuv4i32 QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>;
+def : NEONInstAlias<"vshl${p}.u64 $Vdn, $Vm",
+                    (VSHLuv2i64 QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>;
+
 // VLD1 single-lane pseudo-instructions. These need special handling for
 // the lane index that an InstAlias can't handle, so we use these instead.
 defm VLD1LNdAsm : NEONDT8AsmPseudoInst<"vld1${p}", "$list, $addr",

Modified: llvm/trunk/test/MC/ARM/neon-shift-encoding.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/neon-shift-encoding.s?rev=146123&r1=146122&r2=146123&view=diff
==============================================================================
--- llvm/trunk/test/MC/ARM/neon-shift-encoding.s (original)
+++ llvm/trunk/test/MC/ARM/neon-shift-encoding.s Wed Dec  7 19:12:35 2011
@@ -235,3 +235,44 @@
 	vqrshrn.u32	d16, q8, #13
 @ CHECK: vqrshrn.u64	d16, q8, #13  @ encoding: [0x70,0x09,0xf3,0xf3]
 	vqrshrn.u64	d16, q8, #13
+
+@ Optional destination operand variants.
+        vshl.s8 q4, q5
+        vshl.s16 q4, q5
+        vshl.s32 q4, q5
+        vshl.s64 q4, q5
+
+        vshl.u8 q4, q5
+        vshl.u16 q4, q5
+        vshl.u32 q4, q5
+        vshl.u64 q4, q5
+
+        vshl.s8 d4, d5
+        vshl.s16 d4, d5
+        vshl.s32 d4, d5
+        vshl.s64 d4, d5
+
+        vshl.u8 d4, d5
+        vshl.u16 d4, d5
+        vshl.u32 d4, d5
+        vshl.u64 d4, d5
+
+@ CHECK: vshl.s8	q4, q4, q5      @ encoding: [0x48,0x84,0x0a,0xf2]
+@ CHECK: vshl.s16	q4, q4, q5      @ encoding: [0x48,0x84,0x1a,0xf2]
+@ CHECK: vshl.s32	q4, q4, q5      @ encoding: [0x48,0x84,0x2a,0xf2]
+@ CHECK: vshl.s64	q4, q4, q5      @ encoding: [0x48,0x84,0x3a,0xf2]
+
+@ CHECK: vshl.u8	q4, q4, q5      @ encoding: [0x48,0x84,0x0a,0xf3]
+@ CHECK: vshl.u16	q4, q4, q5      @ encoding: [0x48,0x84,0x1a,0xf3]
+@ CHECK: vshl.u32	q4, q4, q5      @ encoding: [0x48,0x84,0x2a,0xf3]
+@ CHECK: vshl.u64	q4, q4, q5      @ encoding: [0x48,0x84,0x3a,0xf3]
+
+@ CHECK: vshl.s8	d4, d4, d5      @ encoding: [0x04,0x44,0x05,0xf2]
+@ CHECK: vshl.s16	d4, d4, d5      @ encoding: [0x04,0x44,0x15,0xf2]
+@ CHECK: vshl.s32	d4, d4, d5      @ encoding: [0x04,0x44,0x25,0xf2]
+@ CHECK: vshl.s64	d4, d4, d5      @ encoding: [0x04,0x44,0x35,0xf2]
+
+@ CHECK: vshl.u8	d4, d4, d5      @ encoding: [0x04,0x44,0x05,0xf3]
+@ CHECK: vshl.u16	d4, d4, d5      @ encoding: [0x04,0x44,0x15,0xf3]
+@ CHECK: vshl.u32	d4, d4, d5      @ encoding: [0x04,0x44,0x25,0xf3]
+@ CHECK: vshl.u64	d4, d4, d5      @ encoding: [0x04,0x44,0x35,0xf3]



From jan_sjodin at yahoo.com  Wed Dec  7 19:15:44 2011
From: jan_sjodin at yahoo.com (Jan Sjodin)
Date: Wed, 7 Dec 2011 17:15:44 -0800 (PST)
Subject: [llvm-commits] FMA4 cleanup patch
In-Reply-To: 
References: <1323273015.33804.YahooMailNeo@web161505.mail.bf1.yahoo.com>
	
Message-ID: <1323306944.72374.YahooMailNeo@web161506.mail.bf1.yahoo.com>

No functional changes with this patch, the existing tests cover it. The coming XOP patches exercise the same code as well with some twists (5 op instructions).

- Jan




>________________________________
> From: Bruno Cardoso Lopes 
>To: Jan Sjodin  
>Cc: "llvm-commits at cs.uiuc.edu"  
>Sent: Wednesday, December 7, 2011 5:57 PM
>Subject: Re: FMA4 cleanup patch
> 
>LGTM! Can you add testcases?
>
>On Wed, Dec 7, 2011 at 1:50 PM, Jan Sjodin  wrote:
>> Patch to clean up the FMA4 encoding. I had accidentally swapped the operands
>> in the asm strings for the FMA4 rr patterns, which caused some confusion.
>> Ok to commit?
>>
>> - Jan
>
>
>
>-- 
>Bruno Cardoso Lopes
>http://www.brunocardoso.cc
>
>
>
-------------- next part --------------
An HTML attachment was scrubbed...
URL: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20111207/9b80033e/attachment.html 

From stoklund at 2pi.dk  Wed Dec  7 19:22:39 2011
From: stoklund at 2pi.dk (Jakob Stoklund Olesen)
Date: Thu, 08 Dec 2011 01:22:39 -0000
Subject: [llvm-commits] [llvm] r146124 -
	/llvm/trunk/lib/Target/ARM/ARMConstantIslandPass.cpp
Message-ID: <20111208012239.CF4902A6C12C@llvm.org>

Author: stoklund
Date: Wed Dec  7 19:22:39 2011
New Revision: 146124

URL: http://llvm.org/viewvc/llvm-project?rev=146124&view=rev
Log:
Drop the HasInlineAsm flag.

It is not used any more. We are tracking inline assembly misalignments
directly through the BBInfo.Unalign and KnownBits fields.

A simple conservative size estimate is not good enough since it can
cause alignment padding to be underestimated.

Modified:
    llvm/trunk/lib/Target/ARM/ARMConstantIslandPass.cpp

Modified: llvm/trunk/lib/Target/ARM/ARMConstantIslandPass.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMConstantIslandPass.cpp?rev=146124&r1=146123&r2=146124&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMConstantIslandPass.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMConstantIslandPass.cpp Wed Dec  7 19:22:39 2011
@@ -226,9 +226,6 @@
     /// the branch fix up pass.
     bool HasFarJump;
 
-    /// HasInlineAsm - True if the function contains inline assembly.
-    bool HasInlineAsm;
-
     const ARMInstrInfo *TII;
     const ARMSubtarget *STI;
     ARMFunctionInfo *AFI;
@@ -338,7 +335,6 @@
   isThumb2 = AFI->isThumb2Function();
 
   HasFarJump = false;
-  HasInlineAsm = false;
 
   // Renumber all of the machine basic blocks in the function, guaranteeing that
   // the numbers agree with the position of the block in the function.
@@ -711,10 +707,8 @@
     BBI.Size += TII->GetInstSizeInBytes(I);
     // For inline asm, GetInstSizeInBytes returns a conservative estimate.
     // The actual size may be smaller, but still a multiple of the instr size.
-    if (I->isInlineAsm()) {
+    if (I->isInlineAsm())
       BBI.Unalign = isThumb ? 1 : 2;
-      HasInlineAsm = true;
-    }
   }
 
   // tBR_JTr contains a .align 2 directive.
@@ -907,7 +901,7 @@
                                       MachineInstr *CPEMI, unsigned MaxDisp,
                                       bool NegOk, bool DoDump) {
   unsigned CPEOffset  = GetOffsetOf(CPEMI);
-  assert((CPEOffset%4 == 0 || HasInlineAsm) && "Misaligned CPE");
+  assert(CPEOffset % 4 == 0 && "Misaligned CPE");
 
   if (DoDump) {
     DEBUG(errs() << "User of CPE#" << CPEMI->getOperand(0).getImm()



From grosbach at apple.com  Wed Dec  7 19:30:05 2011
From: grosbach at apple.com (Jim Grosbach)
Date: Thu, 08 Dec 2011 01:30:05 -0000
Subject: [llvm-commits] [llvm] r146125 - in /llvm/trunk:
 lib/Target/ARM/ARMInstrInfo.td lib/Target/ARM/ARMInstrNEON.td
 lib/Target/ARM/AsmParser/ARMAsmParser.cpp test/MC/ARM/neon-shift-encoding.s
Message-ID: <20111208013005.2F3102A6C12C@llvm.org>

Author: grosbach
Date: Wed Dec  7 19:30:04 2011
New Revision: 146125

URL: http://llvm.org/viewvc/llvm-project?rev=146125&view=rev
Log:
ARM NEON two-operand aliases for VSHL(immediate).

Modified:
    llvm/trunk/lib/Target/ARM/ARMInstrInfo.td
    llvm/trunk/lib/Target/ARM/ARMInstrNEON.td
    llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
    llvm/trunk/test/MC/ARM/neon-shift-encoding.s

Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.td?rev=146125&r1=146124&r2=146125&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrInfo.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Wed Dec  7 19:30:04 2011
@@ -584,6 +584,14 @@
   let ParserMatchClass = Imm0_32AsmOperand;
 }
 
+/// imm0_63 predicate - True if the 32-bit immediate is in the range [0,63].
+def Imm0_63AsmOperand: ImmAsmOperand { let Name = "Imm0_63"; }
+def imm0_63 : Operand, ImmLeaf= 0 && Imm < 64;
+}]> {
+  let ParserMatchClass = Imm0_63AsmOperand;
+}
+
 /// imm0_255 predicate - Immediate in the range [0,255].
 def Imm0_255AsmOperand : ImmAsmOperand { let Name = "Imm0_255"; }
 def imm0_255 : Operand, ImmLeaf= 0 && Imm < 256; }]> {

Modified: llvm/trunk/lib/Target/ARM/ARMInstrNEON.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrNEON.td?rev=146125&r1=146124&r2=146125&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrNEON.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrNEON.td Wed Dec  7 19:30:04 2011
@@ -5402,6 +5402,25 @@
                     (VMULslfq QPR:$Qdn, QPR:$Qdn, DPR_VFP2:$Dm,
                               VectorIndex32:$lane, pred:$p)>;
 
+// VSHL (immediate) two-operand aliases.
+def : NEONInstAlias<"vshl${p}.i8 $Vdn, $imm",
+                    (VSHLiv8i8 DPR:$Vdn, DPR:$Vdn, imm0_7:$imm, pred:$p)>;
+def : NEONInstAlias<"vshl${p}.i16 $Vdn, $imm",
+                    (VSHLiv4i16 DPR:$Vdn, DPR:$Vdn, imm0_15:$imm, pred:$p)>;
+def : NEONInstAlias<"vshl${p}.i32 $Vdn, $imm",
+                    (VSHLiv2i32 DPR:$Vdn, DPR:$Vdn, imm0_31:$imm, pred:$p)>;
+def : NEONInstAlias<"vshl${p}.i64 $Vdn, $imm",
+                    (VSHLiv1i64 DPR:$Vdn, DPR:$Vdn, imm0_63:$imm, pred:$p)>;
+
+def : NEONInstAlias<"vshl${p}.i8 $Vdn, $imm",
+                    (VSHLiv16i8 QPR:$Vdn, QPR:$Vdn, imm0_7:$imm, pred:$p)>;
+def : NEONInstAlias<"vshl${p}.i16 $Vdn, $imm",
+                    (VSHLiv8i16 QPR:$Vdn, QPR:$Vdn, imm0_15:$imm, pred:$p)>;
+def : NEONInstAlias<"vshl${p}.i32 $Vdn, $imm",
+                    (VSHLiv4i32 QPR:$Vdn, QPR:$Vdn, imm0_31:$imm, pred:$p)>;
+def : NEONInstAlias<"vshl${p}.i64 $Vdn, $imm",
+                    (VSHLiv2i64 QPR:$Vdn, QPR:$Vdn, imm0_63:$imm, pred:$p)>;
+
 // VSHL (register) two-operand aliases.
 def : NEONInstAlias<"vshl${p}.s8 $Vdn, $Vm",
                     (VSHLsv8i8 DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;

Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp?rev=146125&r1=146124&r2=146125&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp (original)
+++ llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Wed Dec  7 19:30:04 2011
@@ -611,6 +611,14 @@
     int64_t Value = CE->getValue();
     return Value >= 0 && Value < 32;
   }
+  bool isImm0_63() const {
+    if (Kind != k_Immediate)
+      return false;
+    const MCConstantExpr *CE = dyn_cast(getImm());
+    if (!CE) return false;
+    int64_t Value = CE->getValue();
+    return Value >= 0 && Value < 64;
+  }
   bool isImm8() const {
     if (Kind != k_Immediate)
       return false;

Modified: llvm/trunk/test/MC/ARM/neon-shift-encoding.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/neon-shift-encoding.s?rev=146125&r1=146124&r2=146125&view=diff
==============================================================================
--- llvm/trunk/test/MC/ARM/neon-shift-encoding.s (original)
+++ llvm/trunk/test/MC/ARM/neon-shift-encoding.s Wed Dec  7 19:30:04 2011
@@ -276,3 +276,23 @@
 @ CHECK: vshl.u16	d4, d4, d5      @ encoding: [0x04,0x44,0x15,0xf3]
 @ CHECK: vshl.u32	d4, d4, d5      @ encoding: [0x04,0x44,0x25,0xf3]
 @ CHECK: vshl.u64	d4, d4, d5      @ encoding: [0x04,0x44,0x35,0xf3]
+
+        vshl.s8 q4, #2
+        vshl.s16 q4, #14
+        vshl.s32 q4, #27
+        vshl.s64 q4, #35
+
+        vshl.s8 d4, #6
+        vshl.u16 d4, #10
+        vshl.s32 d4, #17
+        vshl.u64 d4, #43
+
+@ CHECK: vshl.i8	q4, q4, #2      @ encoding: [0x58,0x85,0x8a,0xf2]
+@ CHECK: vshl.i16	q4, q4, #14     @ encoding: [0x58,0x85,0x9e,0xf2]
+@ CHECK: vshl.i32	q4, q4, #27     @ encoding: [0x58,0x85,0xbb,0xf2]
+@ CHECK: vshl.i64	q4, q4, #35     @ encoding: [0xd8,0x85,0xa3,0xf2]
+
+@ CHECK: vshl.i8	d4, d4, #6      @ encoding: [0x14,0x45,0x8e,0xf2]
+@ CHECK: vshl.i16	d4, d4, #10     @ encoding: [0x14,0x45,0x9a,0xf2]
+@ CHECK: vshl.i32	d4, d4, #17     @ encoding: [0x14,0x45,0xb1,0xf2]
+@ CHECK: vshl.i64	d4, d4, #43     @ encoding: [0x94,0x45,0xab,0xf2]



From eli.friedman at gmail.com  Wed Dec  7 19:42:35 2011
From: eli.friedman at gmail.com (Eli Friedman)
Date: Wed, 7 Dec 2011 17:42:35 -0800
Subject: [llvm-commits] [LLVM,
 SelectionDAG] fix for #9905: Failure in code selection for llvm
 intrinsics sqrt/exp
In-Reply-To: <4EDF4307.4060909@narod.ru>
References: <4ED74593.2030003@narod.ru> <4ED9D140.2070504@narod.ru>
	<4EDCC1A2.5010500@narod.ru>
	
	<4EDDE0E1.5060200@narod.ru> <4EDDE47C.4000905@narod.ru>
	
	<4EDF4307.4060909@narod.ru>
Message-ID: 

On Wed, Dec 7, 2011 at 2:42 AM, Stepan Dyatkovskiy  wrote:
> Please, look at fixed patch in attachment.

Looks fine.  Do you need me to commit this for you?

-Eli

> Thanks.
> -Stepan.
>
>
> Eli Friedman wrote:
>>
>> On Tue, Dec 6, 2011 at 1:46 AM, Stepan Dyatkovskiy
>> ?wrote:
>>>
>>> Sorry for previous post. Forgot to remove extra newlines at the end of
>>> file.
>>> Fixed file is attached here.
>>
>>
>> Better... but please try to make it less sensitive to register
>> allocation and scheduler choices.
>>
>> -Eli
>>
>>>
>>> Thanks.
>>> -Stepan.
>>>
>>>
>>> Stepan Dyatkovskiy wrote:
>>>>
>>>>
>>>> OK. Please look at reworked regression test patch in attachment.
>>>>
>>>> -Stepan.
>>>>
>>>> Eli Friedman wrote:
>>>>>
>>>>>
>>>>> The code changes look fine. Please put all the FileCheck tests into
>>>>> one file, and only use CHECK lines for the most important pieces
>>>>> (specifically, that we call sinf etc.).
>>>>>
>>>>> -Eli
>>>>>
>>>>> On Mon, Dec 5, 2011 at 5:05 AM, Stepan Dyatkovskiy
>>>>> wrote:
>>>>>>
>>>>>>
>>>>>> ping.
>>>>>>
>>>>>> -Stepan.
>>>>>>
>>>>>> Stepan Dyatkovskiy wrote:
>>>>>>>
>>>>>>>
>>>>>>> ping.
>>>>>>>
>>>>>>> -Stepan
>>>>>>>
>>>>>>> Stepan Dyatkovskiy wrote:
>>>>>>>>
>>>>>>>>
>>>>>>>> Hi all. Please find the patch and regression tests in attachment for
>>>>>>>> review.
>>>>>>>> This patch for ARM. It fixes selection for several instructions that
>>>>>>>> works with v4f32 arguments: FSQRT, FSIN, FCOS, FPOWI, FPOW, FLOG,
>>>>>>>> FLOG2,
>>>>>>>> FLOG10, FEXP, FEXP2.
>>>>>>>> I'm still worrying about FCOPYSIGN, FNEG, FABS, FCEIL, FTRUNC,
>>>>>>>> FRINT,
>>>>>>>> FNEARBYINT, FFLOOR. I could not found a way to add this instructions
>>>>>>>> with v2f32 argument to DAG. It seems that it is impossible in ToT.
>>>>>>>> So
>>>>>>>> these instructions was not fixed.
>>>>>>>>
>>>>>>>> -Stepan.
>>>>>>>>
>>>>>>>>
>>>>>>>> _______________________________________________
>>>>>>>> llvm-commits mailing list
>>>>>>>> llvm-commits at cs.uiuc.edu
>>>>>>>> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
>>>>>>>
>>>>>>>
>>>>>>>
>>>>>>> _______________________________________________
>>>>>>> llvm-commits mailing list
>>>>>>> llvm-commits at cs.uiuc.edu
>>>>>>> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
>>>>>>
>>>>>>
>>>>>>
>>>>>> _______________________________________________
>>>>>> llvm-commits mailing list
>>>>>> llvm-commits at cs.uiuc.edu
>>>>>> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
>>>>
>>>>
>>>>
>>>>
>>>>
>>>> _______________________________________________
>>>> llvm-commits mailing list
>>>> llvm-commits at cs.uiuc.edu
>>>> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
>>>
>>>
>>>
>


From daniel at zuster.org  Wed Dec  7 20:39:24 2011
From: daniel at zuster.org (Daniel Dunbar)
Date: Thu, 08 Dec 2011 02:39:24 -0000
Subject: [llvm-commits] [compiler-rt] r146131 - in
 /compiler-rt/trunk/SDKs/linux: ./ README.txt usr/ usr/include/
 usr/include/endian.h usr/include/limits.h usr/include/stdio.h
 usr/include/stdlib.h usr/include/string.h usr/include/sys/
 usr/include/sys/mman.h usr/include/sys/stat.h usr/include/sys/types.h
 usr/include/unistd.h
Message-ID: <20111208023924.5F1F52A6C12C@llvm.org>

Author: ddunbar
Date: Wed Dec  7 20:39:23 2011
New Revision: 146131

URL: http://llvm.org/viewvc/llvm-project?rev=146131&view=rev
Log:
SDKs: Sketch an initial stub SDK for Linux, I believe this suffices for building
the main compiler-rt and profile modules, at least on x86.

Added:
    compiler-rt/trunk/SDKs/linux/
    compiler-rt/trunk/SDKs/linux/README.txt
    compiler-rt/trunk/SDKs/linux/usr/
    compiler-rt/trunk/SDKs/linux/usr/include/
    compiler-rt/trunk/SDKs/linux/usr/include/endian.h
    compiler-rt/trunk/SDKs/linux/usr/include/limits.h
    compiler-rt/trunk/SDKs/linux/usr/include/stdio.h
    compiler-rt/trunk/SDKs/linux/usr/include/stdlib.h
    compiler-rt/trunk/SDKs/linux/usr/include/string.h
    compiler-rt/trunk/SDKs/linux/usr/include/sys/
    compiler-rt/trunk/SDKs/linux/usr/include/sys/mman.h
    compiler-rt/trunk/SDKs/linux/usr/include/sys/stat.h
    compiler-rt/trunk/SDKs/linux/usr/include/sys/types.h
    compiler-rt/trunk/SDKs/linux/usr/include/unistd.h

Added: compiler-rt/trunk/SDKs/linux/README.txt
URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/SDKs/linux/README.txt?rev=146131&view=auto
==============================================================================
--- compiler-rt/trunk/SDKs/linux/README.txt (added)
+++ compiler-rt/trunk/SDKs/linux/README.txt Wed Dec  7 20:39:23 2011
@@ -0,0 +1,2 @@
+This is a stub SDK for Linux. Currently, this has only been tested on i386 and
+x86_64 using the Clang compiler.

Added: compiler-rt/trunk/SDKs/linux/usr/include/endian.h
URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/SDKs/linux/usr/include/endian.h?rev=146131&view=auto
==============================================================================
--- compiler-rt/trunk/SDKs/linux/usr/include/endian.h (added)
+++ compiler-rt/trunk/SDKs/linux/usr/include/endian.h Wed Dec  7 20:39:23 2011
@@ -0,0 +1,29 @@
+/* ===-- endian.h - stub SDK header for compiler-rt -------------------------===
+ *
+ *                     The LLVM Compiler Infrastructure
+ *
+ * This file is dual licensed under the MIT and the University of Illinois Open
+ * Source Licenses. See LICENSE.TXT for details.
+ *
+ * ===-----------------------------------------------------------------------===
+ *
+ * This is a stub SDK header file. This file is not part of the interface of
+ * this library nor an official version of the appropriate SDK header. It is
+ * intended only to stub the features of this header required by compiler-rt.
+ *
+ * ===-----------------------------------------------------------------------===
+ */
+
+#ifndef __ENDIAN_H__
+#define __ENDIAN_H__
+
+#define __LITTLE_ENDIAN 1234
+#define __BIG_ENDIAN 4321
+
+#if defined(__LITTLE_ENDIAN__) || defined(__ORDER_LITTLE_ENDIAN__)
+#define __BYTE_ORDER __LITTLE_ENDIAN
+#else
+#define __BYTE_ORDER __BIG_ENDIAN
+#endif
+
+#endif /* __ENDIAN_H__ */

Added: compiler-rt/trunk/SDKs/linux/usr/include/limits.h
URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/SDKs/linux/usr/include/limits.h?rev=146131&view=auto
==============================================================================
--- compiler-rt/trunk/SDKs/linux/usr/include/limits.h (added)
+++ compiler-rt/trunk/SDKs/linux/usr/include/limits.h Wed Dec  7 20:39:23 2011
@@ -0,0 +1,23 @@
+/* ===-- limits.h - stub SDK header for compiler-rt -------------------------===
+ *
+ *                     The LLVM Compiler Infrastructure
+ *
+ * This file is dual licensed under the MIT and the University of Illinois Open
+ * Source Licenses. See LICENSE.TXT for details.
+ *
+ * ===-----------------------------------------------------------------------===
+ *
+ * This is a stub SDK header file. This file is not part of the interface of
+ * this library nor an official version of the appropriate SDK header. It is
+ * intended only to stub the features of this header required by compiler-rt.
+ *
+ * ===-----------------------------------------------------------------------===
+ */
+
+#ifndef __LIMITS_H__
+#define __LIMITS_H__
+
+/* This is only here as a landing pad for the include_next from the compiler's
+   built-in limits.h. */
+
+#endif /* __LIMITS_H__ */

Added: compiler-rt/trunk/SDKs/linux/usr/include/stdio.h
URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/SDKs/linux/usr/include/stdio.h?rev=146131&view=auto
==============================================================================
--- compiler-rt/trunk/SDKs/linux/usr/include/stdio.h (added)
+++ compiler-rt/trunk/SDKs/linux/usr/include/stdio.h Wed Dec  7 20:39:23 2011
@@ -0,0 +1,35 @@
+/* ===-- stdio.h - stub SDK header for compiler-rt --------------------------===
+ *
+ *                     The LLVM Compiler Infrastructure
+ *
+ * This file is dual licensed under the MIT and the University of Illinois Open
+ * Source Licenses. See LICENSE.TXT for details.
+ *
+ * ===-----------------------------------------------------------------------===
+ *
+ * This is a stub SDK header file. This file is not part of the interface of
+ * this library nor an official version of the appropriate SDK header. It is
+ * intended only to stub the features of this header required by compiler-rt.
+ *
+ * ===-----------------------------------------------------------------------===
+ */
+
+#ifndef __STDIO_H__
+#define __STDIO_H__
+
+typedef __SIZE_TYPE__ size_t;
+
+struct _IO_FILE;
+typedef struct _IO_FILE FILE;
+
+extern struct _IO_FILE *stdin;
+extern struct _IO_FILE *stdout;
+extern struct _IO_FILE *stderr;
+
+extern int fclose(FILE *);
+extern int fflush(FILE *);
+extern FILE *fopen(const char * restrict, const char * restrict);
+extern int fprintf(FILE * restrict, const char * restrict, ...);
+extern size_t fwrite(const void * restrict, size_t, size_t, FILE * restrict);
+
+#endif /* __STDIO_H__ */

Added: compiler-rt/trunk/SDKs/linux/usr/include/stdlib.h
URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/SDKs/linux/usr/include/stdlib.h?rev=146131&view=auto
==============================================================================
--- compiler-rt/trunk/SDKs/linux/usr/include/stdlib.h (added)
+++ compiler-rt/trunk/SDKs/linux/usr/include/stdlib.h Wed Dec  7 20:39:23 2011
@@ -0,0 +1,32 @@
+/* ===-- stdlib.h - stub SDK header for compiler-rt -------------------------===
+ *
+ *                     The LLVM Compiler Infrastructure
+ *
+ * This file is dual licensed under the MIT and the University of Illinois Open
+ * Source Licenses. See LICENSE.TXT for details.
+ *
+ * ===-----------------------------------------------------------------------===
+ *
+ * This is a stub SDK header file. This file is not part of the interface of
+ * this library nor an official version of the appropriate SDK header. It is
+ * intended only to stub the features of this header required by compiler-rt.
+ *
+ * ===-----------------------------------------------------------------------===
+ */
+
+#ifndef __STDLIB_H__
+#define __STDLIB_H__
+
+#define NULL ((void *)0)
+
+typedef __SIZE_TYPE__ size_t;
+
+void abort(void) __attribute__((__nothrow__)) __attribute__((__noreturn__));
+void free(void *) __attribute__((__nothrow__));
+char *getenv(const char *) __attribute__((__nothrow__))
+  __attribute__((__nonnull__(1)));
+  __attribute__((__warn_unused_result__));
+void *malloc(size_t) __attribute__((__nothrow__)) __attribute((__malloc__))
+     __attribute__((__warn_unused_result__));
+
+#endif /* __STDLIB_H__ */

Added: compiler-rt/trunk/SDKs/linux/usr/include/string.h
URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/SDKs/linux/usr/include/string.h?rev=146131&view=auto
==============================================================================
--- compiler-rt/trunk/SDKs/linux/usr/include/string.h (added)
+++ compiler-rt/trunk/SDKs/linux/usr/include/string.h Wed Dec  7 20:39:23 2011
@@ -0,0 +1,28 @@
+/* ===-- string.h - stub SDK header for compiler-rt -------------------------===
+ *
+ *                     The LLVM Compiler Infrastructure
+ *
+ * This file is dual licensed under the MIT and the University of Illinois Open
+ * Source Licenses. See LICENSE.TXT for details.
+ *
+ * ===-----------------------------------------------------------------------===
+ *
+ * This is a stub SDK header file. This file is not part of the interface of
+ * this library nor an official version of the appropriate SDK header. It is
+ * intended only to stub the features of this header required by compiler-rt.
+ *
+ * ===-----------------------------------------------------------------------===
+ */
+
+#ifndef __STRING_H__
+#define __STRING_H__
+
+typedef __SIZE_TYPE__ size_t;
+
+char *strcat(char *, const char *);
+char *strcpy(char *, const char *);
+char *strdup(const char *);
+size_t strlen(const char *);
+char *strncpy(char *, const char *, size_t);
+
+#endif /* __STRING_H__ */

Added: compiler-rt/trunk/SDKs/linux/usr/include/sys/mman.h
URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/SDKs/linux/usr/include/sys/mman.h?rev=146131&view=auto
==============================================================================
--- compiler-rt/trunk/SDKs/linux/usr/include/sys/mman.h (added)
+++ compiler-rt/trunk/SDKs/linux/usr/include/sys/mman.h Wed Dec  7 20:39:23 2011
@@ -0,0 +1,29 @@
+/* ===-- limits.h - stub SDK header for compiler-rt -------------------------===
+ *
+ *                     The LLVM Compiler Infrastructure
+ *
+ * This file is dual licensed under the MIT and the University of Illinois Open
+ * Source Licenses. See LICENSE.TXT for details.
+ *
+ * ===-----------------------------------------------------------------------===
+ *
+ * This is a stub SDK header file. This file is not part of the interface of
+ * this library nor an official version of the appropriate SDK header. It is
+ * intended only to stub the features of this header required by compiler-rt.
+ *
+ * ===-----------------------------------------------------------------------===
+ */
+
+#ifndef __SYS_MMAN_H__
+#define __SYS_MMAN_H__
+
+typedef __SIZE_TYPE__ size_t;
+
+#define PROT_READ 0x1
+#define PROT_WRITE 0x1
+#define PROT_EXEC 0x4
+
+extern int mprotect (void *__addr, size_t __len, int __prot)
+  __attribute__((__nothrow__));
+
+#endif /* __SYS_MMAN_H__ */

Added: compiler-rt/trunk/SDKs/linux/usr/include/sys/stat.h
URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/SDKs/linux/usr/include/sys/stat.h?rev=146131&view=auto
==============================================================================
--- compiler-rt/trunk/SDKs/linux/usr/include/sys/stat.h (added)
+++ compiler-rt/trunk/SDKs/linux/usr/include/sys/stat.h Wed Dec  7 20:39:23 2011
@@ -0,0 +1,24 @@
+/* ===-- stat.h - stub SDK header for compiler-rt ---------------------------===
+ *
+ *                     The LLVM Compiler Infrastructure
+ *
+ * This file is dual licensed under the MIT and the University of Illinois Open
+ * Source Licenses. See LICENSE.TXT for details.
+ *
+ * ===-----------------------------------------------------------------------===
+ *
+ * This is a stub SDK header file. This file is not part of the interface of
+ * this library nor an official version of the appropriate SDK header. It is
+ * intended only to stub the features of this header required by compiler-rt.
+ *
+ * ===-----------------------------------------------------------------------===
+ */
+
+#ifndef __SYS_STAT_H__
+#define __SYS_STAT_H__
+
+typedef unsigned int mode_t;
+
+int mkdir(const char *, mode_t);
+
+#endif /* __SYS_STAT_H__ */

Added: compiler-rt/trunk/SDKs/linux/usr/include/sys/types.h
URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/SDKs/linux/usr/include/sys/types.h?rev=146131&view=auto
==============================================================================
--- compiler-rt/trunk/SDKs/linux/usr/include/sys/types.h (added)
+++ compiler-rt/trunk/SDKs/linux/usr/include/sys/types.h Wed Dec  7 20:39:23 2011
@@ -0,0 +1,20 @@
+/* ===-- stat.h - stub SDK header for compiler-rt ---------------------------===
+ *
+ *                     The LLVM Compiler Infrastructure
+ *
+ * This file is dual licensed under the MIT and the University of Illinois Open
+ * Source Licenses. See LICENSE.TXT for details.
+ *
+ * ===-----------------------------------------------------------------------===
+ *
+ * This is a stub SDK header file. This file is not part of the interface of
+ * this library nor an official version of the appropriate SDK header. It is
+ * intended only to stub the features of this header required by compiler-rt.
+ *
+ * ===-----------------------------------------------------------------------===
+ */
+
+#ifndef __SYS_TYPES_H__
+#define __SYS_TYPES_H__
+
+#endif /* __SYS_TYPES_H__ */

Added: compiler-rt/trunk/SDKs/linux/usr/include/unistd.h
URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/SDKs/linux/usr/include/unistd.h?rev=146131&view=auto
==============================================================================
--- compiler-rt/trunk/SDKs/linux/usr/include/unistd.h (added)
+++ compiler-rt/trunk/SDKs/linux/usr/include/unistd.h Wed Dec  7 20:39:23 2011
@@ -0,0 +1,26 @@
+/* ===-- unistd.h - stub SDK header for compiler-rt -------------------------===
+ *
+ *                     The LLVM Compiler Infrastructure
+ *
+ * This file is dual licensed under the MIT and the University of Illinois Open
+ * Source Licenses. See LICENSE.TXT for details.
+ *
+ * ===-----------------------------------------------------------------------===
+ *
+ * This is a stub SDK header file. This file is not part of the interface of
+ * this library nor an official version of the appropriate SDK header. It is
+ * intended only to stub the features of this header required by compiler-rt.
+ *
+ * ===-----------------------------------------------------------------------===
+ */
+
+#ifndef __UNISTD_H__
+#define __UNISTD_H__
+
+enum {
+  _SC_PAGESIZE = 30
+};
+
+extern long int sysconf (int __name) __attribute__ ((__nothrow__));
+
+#endif /* __UNISTD_H__ */



From daniel at zuster.org  Wed Dec  7 20:39:55 2011
From: daniel at zuster.org (Daniel Dunbar)
Date: Thu, 08 Dec 2011 02:39:55 -0000
Subject: [llvm-commits] [compiler-rt] r146132 -
	/compiler-rt/trunk/make/platform/clang_linux.mk
Message-ID: <20111208023955.320302A6C12C@llvm.org>

Author: ddunbar
Date: Wed Dec  7 20:39:54 2011
New Revision: 146132

URL: http://llvm.org/viewvc/llvm-project?rev=146132&view=rev
Log:
platform/clang_linux: Switch builtin and profile libraries to build using the
stub SDK.
 - This allows us to build both the m32 and m64 variants without worrying about
   whether or not the user has the headers for the alternate arch installed.

Modified:
    compiler-rt/trunk/make/platform/clang_linux.mk

Modified: compiler-rt/trunk/make/platform/clang_linux.mk
URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/make/platform/clang_linux.mk?rev=146132&r1=146131&r2=146132&view=diff
==============================================================================
--- compiler-rt/trunk/make/platform/clang_linux.mk (original)
+++ compiler-rt/trunk/make/platform/clang_linux.mk Wed Dec  7 20:39:54 2011
@@ -24,22 +24,16 @@
 ifneq ($(findstring -linux-,$(CompilerTargetTriple)),)
 
 # Configurations which just include all the runtime functions.
-ifeq ($(CompilerTargetArch),i386)
-Configs += full-i386
+ifeq ($(call contains,i386 x86_64,$(CompilerTargetArch)),true)
+Configs += full-i386 full-x86_64
 Arch.full-i386 := i386
-endif
-ifeq ($(CompilerTargetArch),x86_64)
-Configs += full-x86_64
 Arch.full-x86_64 := x86_64
 endif
 
 # Configuration for profile runtime.
-ifeq ($(CompilerTargetArch),i386)
-Configs += profile-i386
+ifeq ($(call contains,i386 x86_64,$(CompilerTargetArch)),true)
+Configs += profile-i386 profile-x86_64
 Arch.profile-i386 := i386
-endif
-ifeq ($(CompilerTargetArch),x86_64)
-Configs += profile-x86_64
 Arch.profile-x86_64 := x86_64
 endif
 
@@ -66,6 +60,14 @@
 CFLAGS.asan-i386 := $(CFLAGS) -m32
 CFLAGS.asan-x86_64 := $(CFLAGS) -m64
 
+# Use our stub SDK as the sysroot to support more portable building. For now we
+# just do this for the non-ASAN modules, because the stub SDK doesn't have
+# enough support to build ASAN.
+CFLAGS.full-i386 += --sysroot=$(ProjSrcRoot)/SDKs/linux
+CFLAGS.full-x86_64 += --sysroot=$(ProjSrcRoot)/SDKs/linux
+CFLAGS.profile-i386 += --sysroot=$(ProjSrcRoot)/SDKs/linux
+CFLAGS.profile-x86_64 += --sysroot=$(ProjSrcRoot)/SDKs/linux
+
 FUNCTIONS.full-i386 := $(CommonFunctions) $(ArchFunctions.i386)
 FUNCTIONS.full-x86_64 := $(CommonFunctions) $(ArchFunctions.x86_64)
 FUNCTIONS.profile-i386 := GCDAProfiling



From peter_cooper at apple.com  Wed Dec  7 21:24:10 2011
From: peter_cooper at apple.com (Pete Cooper)
Date: Thu, 08 Dec 2011 03:24:10 -0000
Subject: [llvm-commits] [llvm] r146136 -
	/llvm/trunk/lib/CodeGen/RegisterCoalescer.cpp
Message-ID: <20111208032410.7EBB82A6C12C@llvm.org>

Author: pete
Date: Wed Dec  7 21:24:10 2011
New Revision: 146136

URL: http://llvm.org/viewvc/llvm-project?rev=146136&view=rev
Log:
Reverting r145899 as it breaks clang self-hosting

Modified:
    llvm/trunk/lib/CodeGen/RegisterCoalescer.cpp

Modified: llvm/trunk/lib/CodeGen/RegisterCoalescer.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/RegisterCoalescer.cpp?rev=146136&r1=146135&r2=146136&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/RegisterCoalescer.cpp (original)
+++ llvm/trunk/lib/CodeGen/RegisterCoalescer.cpp Wed Dec  7 21:24:10 2011
@@ -149,6 +149,14 @@
     /// shouldJoinPhys - Return true if a physreg copy should be joined.
     bool shouldJoinPhys(CoalescerPair &CP);
 
+    /// isWinToJoinCrossClass - Return true if it's profitable to coalesce
+    /// two virtual registers from different register classes.
+    bool isWinToJoinCrossClass(unsigned SrcReg,
+                               unsigned DstReg,
+                               const TargetRegisterClass *SrcRC,
+                               const TargetRegisterClass *DstRC,
+                               const TargetRegisterClass *NewRC);
+
     /// UpdateRegDefsUses - Replace all defs and uses of SrcReg to DstReg and
     /// update the subregister number if it is not zero. If DstReg is a
     /// physical register and the existing subregister number of the def / use
@@ -1087,6 +1095,56 @@
   return true;
 }
 
+/// isWinToJoinCrossClass - Return true if it's profitable to coalesce
+/// two virtual registers from different register classes.
+bool
+RegisterCoalescer::isWinToJoinCrossClass(unsigned SrcReg,
+                                             unsigned DstReg,
+                                             const TargetRegisterClass *SrcRC,
+                                             const TargetRegisterClass *DstRC,
+                                             const TargetRegisterClass *NewRC) {
+  unsigned NewRCCount = RegClassInfo.getNumAllocatableRegs(NewRC);
+  // This heuristics is good enough in practice, but it's obviously not *right*.
+  // 4 is a magic number that works well enough for x86, ARM, etc. It filter
+  // out all but the most restrictive register classes.
+  if (NewRCCount > 4 ||
+      // Early exit if the function is fairly small, coalesce aggressively if
+      // that's the case. For really special register classes with 3 or
+      // fewer registers, be a bit more careful.
+      (LIS->getFuncInstructionCount() / NewRCCount) < 8)
+    return true;
+  LiveInterval &SrcInt = LIS->getInterval(SrcReg);
+  LiveInterval &DstInt = LIS->getInterval(DstReg);
+  unsigned SrcSize = LIS->getApproximateInstructionCount(SrcInt);
+  unsigned DstSize = LIS->getApproximateInstructionCount(DstInt);
+
+  // Coalesce aggressively if the intervals are small compared to the number of
+  // registers in the new class. The number 4 is fairly arbitrary, chosen to be
+  // less aggressive than the 8 used for the whole function size.
+  const unsigned ThresSize = 4 * NewRCCount;
+  if (SrcSize <= ThresSize && DstSize <= ThresSize)
+    return true;
+
+  // Estimate *register use density*. If it doubles or more, abort.
+  unsigned SrcUses = std::distance(MRI->use_nodbg_begin(SrcReg),
+                                   MRI->use_nodbg_end());
+  unsigned DstUses = std::distance(MRI->use_nodbg_begin(DstReg),
+                                   MRI->use_nodbg_end());
+  unsigned NewUses = SrcUses + DstUses;
+  unsigned NewSize = SrcSize + DstSize;
+  if (SrcRC != NewRC && SrcSize > ThresSize) {
+    unsigned SrcRCCount = RegClassInfo.getNumAllocatableRegs(SrcRC);
+    if (NewUses*SrcSize*SrcRCCount > 2*SrcUses*NewSize*NewRCCount)
+      return false;
+  }
+  if (DstRC != NewRC && DstSize > ThresSize) {
+    unsigned DstRCCount = RegClassInfo.getNumAllocatableRegs(DstRC);
+    if (NewUses*DstSize*DstRCCount > 2*DstUses*NewSize*NewRCCount)
+      return false;
+  }
+  return true;
+}
+
 
 /// JoinCopy - Attempt to join intervals corresponding to SrcReg/DstReg,
 /// which are the src/dst of the copy instruction CopyMI.  This returns true
@@ -1144,6 +1202,14 @@
         DEBUG(dbgs() << "\tCross-class joins disabled.\n");
         return false;
       }
+      if (!isWinToJoinCrossClass(CP.getSrcReg(), CP.getDstReg(),
+                                 MRI->getRegClass(CP.getSrcReg()),
+                                 MRI->getRegClass(CP.getDstReg()),
+                                 CP.getNewRC())) {
+        DEBUG(dbgs() << "\tAvoid coalescing to constrained register class.\n");
+        Again = true;  // May be possible to coalesce later.
+        return false;
+      }
     }
 
     // When possible, let DstReg be the larger interval.



From hfinkel at anl.gov  Wed Dec  7 22:32:32 2011
From: hfinkel at anl.gov (Hal Finkel)
Date: Wed, 07 Dec 2011 22:32:32 -0600
Subject: [llvm-commits] [LLVMdev] Dead register (was Re: [llvm] r145819)
In-Reply-To: <1323214755.2507.3294.camel@sapling>
References: <20111205175518.343FF2A6C12C@llvm.org>
	
	<1323112465.2507.3170.camel@sapling>
	<1323118601.2507.3183.camel@sapling>
	
	<1323214755.2507.3294.camel@sapling>
Message-ID: <1323318752.2507.3368.camel@sapling>

On Tue, 2011-12-06 at 17:39 -0600, Hal Finkel wrote:
> On Mon, 2011-12-05 at 13:18 -0800, Jakob Stoklund Olesen wrote:
> > On Dec 5, 2011, at 12:56 PM, Hal Finkel wrote:
> > 
> > > RegScavenger is complaining about use of an undefined register, CTR8, in
> > > the BCTR8 instruction, in the following instance (this is from the PPC
> > > backend):
> > > 
> > > BB#38: derived from LLVM BB %for.end50
> > >    Predecessors according to CFG: BB#36
> > >        %X3 = LD 0, ; mem:LD8[FixedStack27]
> > >        %X4 = RLDICR %X3, 3, 60
> > >        %X5 = LI8 [TF=4]
> > >        %X5 = ADDIS8 %X5, [TF=8]
> > >        %X4 = LDX %X4, %X5; mem:LD8[JumpTable]
> > >        MTCTR8 %X4, %CTR8
> > >        BCTR8 %CTR8, %RM
> > >    Successors according to CFG: BB#23 BB#15 BB#7 BB#8 BB#9 BB#10 BB#11
> > > BB#25 BB#12 BB#16 BB#18 BB#13 BB#17
> > > 
> > > How could CRT8 be marked implicitly-defined and also dead in the same
> > > instruction when it is clearly used in the next instruction?
> > 
> > This is the kind of sloppy liveness, I was talking about ;-)
> > 
> > llc -verify-machineinstrs should give you better info.
> 
> Unfortunately, this just tells me what I already knew:
> 
> *** Bad machine code: Using an undefined physical register ***
> - function:    check
> - basic block: for.end50 0x2bef428 (BB#38)
> - instruction: BCTR8 %CTR8, %RM
> - operand 0:   %CTR8
> LLVM ERROR: Found 1 machine code errors.
> 
> This comes from the following four statements in
> PPCDAGToDAGISel::Select; what's wrong here?
> SDValue Chain = N->getOperand(0);
> SDValue Target = N->getOperand(1);
> unsigned Opc = PPC::MTCTR8;
> unsigned Reg = PPC::BCTR8;
> Chain = SDValue(CurDAG->getMachineNode(Opc, dl, MVT::Other, Target,
>                                            Chain), 0);
> return CurDAG->SelectNodeTo(N, Reg, MVT::Other, Chain);

So it seems that CTR8 is being added through a call to
MachineInstr::addRegisterDead by InstrEmitter::EmitMachineNode, and this
is done for all implicitly-defined registers that don't otherwise seem
to be used. Furthermore, it seems that determining usage is tied to
looking for "glued" nodes. Changing the first MVT::Other to MVT::Glue
solved the problem.

 -Hal

> 
> Thanks again,
> Hal
> 
> > 
> > /jakob
> > 
> 

-- 
Hal Finkel
Postdoctoral Appointee
Leadership Computing Facility
Argonne National Laboratory


From hfinkel at anl.gov  Wed Dec  7 22:36:45 2011
From: hfinkel at anl.gov (Hal Finkel)
Date: Thu, 08 Dec 2011 04:36:45 -0000
Subject: [llvm-commits] [llvm] r146137 -
	/llvm/trunk/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
Message-ID: <20111208043645.289842A6C12C@llvm.org>

Author: hfinkel
Date: Wed Dec  7 22:36:44 2011
New Revision: 146137

URL: http://llvm.org/viewvc/llvm-project?rev=146137&view=rev
Log:
MTCTR needs to be glued to BCTR so that CTR is not marked dead in MTCTR (another find by -verify-machineinstrs)

Modified:
    llvm/trunk/lib/Target/PowerPC/PPCISelDAGToDAG.cpp

Modified: llvm/trunk/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCISelDAGToDAG.cpp?rev=146137&r1=146136&r2=146137&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCISelDAGToDAG.cpp (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCISelDAGToDAG.cpp Wed Dec  7 22:36:44 2011
@@ -1066,7 +1066,7 @@
     SDValue Target = N->getOperand(1);
     unsigned Opc = Target.getValueType() == MVT::i32 ? PPC::MTCTR : PPC::MTCTR8;
     unsigned Reg = Target.getValueType() == MVT::i32 ? PPC::BCTR : PPC::BCTR8;
-    Chain = SDValue(CurDAG->getMachineNode(Opc, dl, MVT::Other, Target,
+    Chain = SDValue(CurDAG->getMachineNode(Opc, dl, MVT::Glue, Target,
                                            Chain), 0);
     return CurDAG->SelectNodeTo(N, Reg, MVT::Other, Chain);
   }



From stpworld at narod.ru  Thu Dec  8 01:55:03 2011
From: stpworld at narod.ru (Stepan Dyatkovskiy)
Date: Thu, 08 Dec 2011 07:55:03 -0000
Subject: [llvm-commits] [llvm] r146143 - in /llvm/trunk:
 lib/Target/ARM/ARMISelLowering.cpp
 test/CodeGen/ARM/2011-11-29-128bitArithmetics.ll
Message-ID: <20111208075503.BA6512A6C12C@llvm.org>

Author: dyatkovskiy
Date: Thu Dec  8 01:55:03 2011
New Revision: 146143

URL: http://llvm.org/viewvc/llvm-project?rev=146143&view=rev
Log:
Fix bug 9905: Failure in code selection for llvm intrinsics sqrt/exp (fix for FSQRT, FSIN, FCOS, FPOWI, FPOW, FLOG, FLOG2, FLOG10, FEXP, FEXP2).

Added:
    llvm/trunk/test/CodeGen/ARM/2011-11-29-128bitArithmetics.ll
Modified:
    llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp

Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp?rev=146143&r1=146142&r2=146143&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp Thu Dec  8 01:55:03 2011
@@ -468,13 +468,23 @@
 
     // v2f64 is legal so that QR subregs can be extracted as f64 elements, but
     // neither Neon nor VFP support any arithmetic operations on it.
+    // The same with v4f32. But keep in mind that vadd, vsub, vmul are natively
+    // supported for v4f32.
     setOperationAction(ISD::FADD, MVT::v2f64, Expand);
     setOperationAction(ISD::FSUB, MVT::v2f64, Expand);
     setOperationAction(ISD::FMUL, MVT::v2f64, Expand);
+    // FIXME: Code duplication: FDIV and FREM are expanded always, see
+    // ARMTargetLowering::addTypeForNEON method for details.
     setOperationAction(ISD::FDIV, MVT::v2f64, Expand);
     setOperationAction(ISD::FREM, MVT::v2f64, Expand);
+    // FIXME: Create unittest.
+    // In another words, find a way when "copysign" appears in DAG with vector
+    // operands.
     setOperationAction(ISD::FCOPYSIGN, MVT::v2f64, Expand);
+    // FIXME: Code duplication: SETCC has custom operation action, see
+    // ARMTargetLowering::addTypeForNEON method for details.
     setOperationAction(ISD::SETCC, MVT::v2f64, Expand);
+    // FIXME: Create unittest for FNEG and for FABS.
     setOperationAction(ISD::FNEG, MVT::v2f64, Expand);
     setOperationAction(ISD::FABS, MVT::v2f64, Expand);
     setOperationAction(ISD::FSQRT, MVT::v2f64, Expand);
@@ -487,11 +497,23 @@
     setOperationAction(ISD::FLOG10, MVT::v2f64, Expand);
     setOperationAction(ISD::FEXP, MVT::v2f64, Expand);
     setOperationAction(ISD::FEXP2, MVT::v2f64, Expand);
+    // FIXME: Create unittest for FCEIL, FTRUNC, FRINT, FNEARBYINT, FFLOOR.
     setOperationAction(ISD::FCEIL, MVT::v2f64, Expand);
     setOperationAction(ISD::FTRUNC, MVT::v2f64, Expand);
     setOperationAction(ISD::FRINT, MVT::v2f64, Expand);
     setOperationAction(ISD::FNEARBYINT, MVT::v2f64, Expand);
     setOperationAction(ISD::FFLOOR, MVT::v2f64, Expand);
+    
+    setOperationAction(ISD::FSQRT, MVT::v4f32, Expand);
+    setOperationAction(ISD::FSIN, MVT::v4f32, Expand);
+    setOperationAction(ISD::FCOS, MVT::v4f32, Expand);
+    setOperationAction(ISD::FPOWI, MVT::v4f32, Expand);
+    setOperationAction(ISD::FPOW, MVT::v4f32, Expand);
+    setOperationAction(ISD::FLOG, MVT::v4f32, Expand);
+    setOperationAction(ISD::FLOG2, MVT::v4f32, Expand);
+    setOperationAction(ISD::FLOG10, MVT::v4f32, Expand);
+    setOperationAction(ISD::FEXP, MVT::v4f32, Expand);
+    setOperationAction(ISD::FEXP2, MVT::v4f32, Expand);
 
     // Neon does not support some operations on v1i64 and v2i64 types.
     setOperationAction(ISD::MUL, MVT::v1i64, Expand);

Added: llvm/trunk/test/CodeGen/ARM/2011-11-29-128bitArithmetics.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/2011-11-29-128bitArithmetics.ll?rev=146143&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/2011-11-29-128bitArithmetics.ll (added)
+++ llvm/trunk/test/CodeGen/ARM/2011-11-29-128bitArithmetics.ll Thu Dec  8 01:55:03 2011
@@ -0,0 +1,302 @@
+; RUN: llc < %s -march=arm -mcpu=cortex-a9 | FileCheck %s
+
+ at A = global <4 x float> 
+
+define void @test_sqrt(<4 x float>* %X) nounwind {
+
+; CHECK: test_sqrt:
+
+; CHECK:      movw    r1, :lower16:A
+; CHECK-NEXT: movt    r1, :upper16:A
+; CHECK:      vldmia  r1, {[[short0:s[0-9]+]], [[short1:s[0-9]+]], [[short2:s[0-9]+]], [[short3:s[0-9]+]]}
+; CHECK:      vsqrt.f32       {{s[0-9]+}}, [[short3]]
+; CHECK:      vsqrt.f32       {{s[0-9]+}}, [[short2]]
+; CHECK:      vsqrt.f32       {{s[0-9]+}}, [[short1]]
+; CHECK:      vsqrt.f32       {{s[0-9]+}}, [[short0]]
+; CHECK-NEXT: vstmia  {{.*}}
+
+L.entry:
+  %0 = load <4 x float>* @A, align 16
+  %1 = call <4 x float> @llvm.sqrt.v4f32(<4 x float> %0)
+  store <4 x float> %1, <4 x float>* %X, align 16
+  ret void
+}
+
+declare <4 x float> @llvm.sqrt.v4f32(<4 x float>) nounwind readonly
+
+
+define void @test_cos(<4 x float>* %X) nounwind {
+
+; CHECK: test_cos:
+
+; CHECK:      movw  [[reg0:r[0-9]+]], :lower16:A
+; CHECK-NEXT: movt  [[reg0]], :upper16:A
+; CHECK:      vldmia [[reg0]], {{.*}}
+
+; CHECK:      {{[v]?mov}}  r0, {{[r|s][0-9]+}}
+; CHECK:      bl  cosf
+
+; CHECK:      {{[v]?mov}}  r0, {{[r|s][0-9]+}}
+; CHECK:      bl  cosf
+
+; CHECK:      {{[v]?mov}}  r0, {{[r|s][0-9]+}}
+; CHECK:      bl  cosf
+
+; CHECK:      {{[v]?mov}}  r0, {{[r|s][0-9]+}}
+; CHECK:      bl  cosf
+
+; CHECK:      vstmia  {{.*}}
+
+L.entry:
+  %0 = load <4 x float>* @A, align 16
+  %1 = call <4 x float> @llvm.cos.v4f32(<4 x float> %0)
+  store <4 x float> %1, <4 x float>* %X, align 16
+  ret void
+}
+
+declare <4 x float> @llvm.cos.v4f32(<4 x float>) nounwind readonly
+
+define void @test_exp(<4 x float>* %X) nounwind {
+
+; CHECK: test_exp:
+
+; CHECK:      movw  [[reg0:r[0-9]+]], :lower16:A
+; CHECK-NEXT: movt  [[reg0]], :upper16:A
+; CHECK:      vldmia [[reg0]], {{.*}}
+
+; CHECK:      {{[v]?mov}}  r0, {{[r|s][0-9]+}}
+; CHECK:      bl  expf
+
+; CHECK:      {{[v]?mov}}  r0, {{[r|s][0-9]+}}
+; CHECK:      bl  expf
+
+; CHECK:      {{[v]?mov}}  r0, {{[r|s][0-9]+}}
+; CHECK:      bl  expf
+
+; CHECK:      {{[v]?mov}}  r0, {{[r|s][0-9]+}}
+; CHECK:      bl  expf
+
+; CHECK:      vstmia  {{.*}}
+
+L.entry:
+  %0 = load <4 x float>* @A, align 16
+  %1 = call <4 x float> @llvm.exp.v4f32(<4 x float> %0)
+  store <4 x float> %1, <4 x float>* %X, align 16
+  ret void
+}
+
+declare <4 x float> @llvm.exp.v4f32(<4 x float>) nounwind readonly
+
+define void @test_exp2(<4 x float>* %X) nounwind {
+
+; CHECK: test_exp2:
+
+; CHECK:      movw  [[reg0:r[0-9]+]], :lower16:A
+; CHECK-NEXT: movt  [[reg0]], :upper16:A
+; CHECK:      vldmia [[reg0]], {{.*}}
+
+; CHECK:      {{[v]?mov}}  r0, {{[r|s][0-9]+}}
+; CHECK:      bl  exp2f
+
+; CHECK:      {{[v]?mov}}  r0, {{[r|s][0-9]+}}
+; CHECK:      bl  exp2f
+
+; CHECK:      {{[v]?mov}}  r0, {{[r|s][0-9]+}}
+; CHECK:      bl  exp2f
+
+; CHECK:      {{[v]?mov}}  r0, {{[r|s][0-9]+}}
+; CHECK:      bl  exp2f
+
+; CHECK:      vstmia  {{.*}}
+
+L.entry:
+  %0 = load <4 x float>* @A, align 16
+  %1 = call <4 x float> @llvm.exp2.v4f32(<4 x float> %0)
+  store <4 x float> %1, <4 x float>* %X, align 16
+  ret void
+}
+
+declare <4 x float> @llvm.exp2.v4f32(<4 x float>) nounwind readonly
+
+define void @test_log10(<4 x float>* %X) nounwind {
+
+; CHECK: test_log10:
+
+; CHECK:      movw  [[reg0:r[0-9]+]], :lower16:A
+; CHECK-NEXT: movt  [[reg0]], :upper16:A
+; CHECK:      vldmia [[reg0]], {{.*}}
+
+; CHECK:      {{[v]?mov}}  r0, {{[r|s][0-9]+}}
+; CHECK:      bl  log10f
+
+; CHECK:      {{[v]?mov}}  r0, {{[r|s][0-9]+}}
+; CHECK:      bl  log10f
+
+; CHECK:      {{[v]?mov}}  r0, {{[r|s][0-9]+}}
+; CHECK:      bl  log10f
+
+; CHECK:      {{[v]?mov}}  r0, {{[r|s][0-9]+}}
+; CHECK:      bl  log10f
+
+; CHECK:      vstmia  {{.*}}
+
+L.entry:
+  %0 = load <4 x float>* @A, align 16
+  %1 = call <4 x float> @llvm.log10.v4f32(<4 x float> %0)
+  store <4 x float> %1, <4 x float>* %X, align 16
+  ret void
+}
+
+declare <4 x float> @llvm.log10.v4f32(<4 x float>) nounwind readonly
+
+define void @test_log(<4 x float>* %X) nounwind {
+
+; CHECK: test_log:
+
+; CHECK:      movw  [[reg0:r[0-9]+]], :lower16:A
+; CHECK-NEXT: movt  [[reg0]], :upper16:A
+; CHECK:      vldmia [[reg0]], {{.*}}
+
+; CHECK:      {{[v]?mov}}  r0, {{[r|s][0-9]+}}
+; CHECK:      bl  logf
+
+; CHECK:      {{[v]?mov}}  r0, {{[r|s][0-9]+}}
+; CHECK:      bl  logf
+
+; CHECK:      {{[v]?mov}}  r0, {{[r|s][0-9]+}}
+; CHECK:      bl  logf
+
+; CHECK:      {{[v]?mov}}  r0, {{[r|s][0-9]+}}
+; CHECK:      bl  logf
+
+; CHECK:      vstmia  {{.*}}
+
+L.entry:
+  %0 = load <4 x float>* @A, align 16
+  %1 = call <4 x float> @llvm.log.v4f32(<4 x float> %0)
+  store <4 x float> %1, <4 x float>* %X, align 16
+  ret void
+}
+
+declare <4 x float> @llvm.log.v4f32(<4 x float>) nounwind readonly
+
+define void @test_log2(<4 x float>* %X) nounwind {
+
+; CHECK: test_log2:
+
+; CHECK:      movw  [[reg0:r[0-9]+]], :lower16:A
+; CHECK-NEXT: movt  [[reg0]], :upper16:A
+; CHECK:      vldmia [[reg0]], {{.*}}
+
+; CHECK:      {{[v]?mov}}  r0, {{[r|s][0-9]+}}
+; CHECK:      bl  log2f
+
+; CHECK:      {{[v]?mov}}  r0, {{[r|s][0-9]+}}
+; CHECK:      bl  log2f
+
+; CHECK:      {{[v]?mov}}  r0, {{[r|s][0-9]+}}
+; CHECK:      bl  log2f
+
+; CHECK:      {{[v]?mov}}  r0, {{[r|s][0-9]+}}
+; CHECK:      bl  log2f
+
+; CHECK:      vstmia  {{.*}}
+
+L.entry:
+  %0 = load <4 x float>* @A, align 16
+  %1 = call <4 x float> @llvm.log2.v4f32(<4 x float> %0)
+  store <4 x float> %1, <4 x float>* %X, align 16
+  ret void
+}
+
+declare <4 x float> @llvm.log2.v4f32(<4 x float>) nounwind readonly
+
+
+define void @test_pow(<4 x float>* %X) nounwind {
+
+; CHECK: test_pow:
+
+; CHECK:      movw  [[reg0:r[0-9]+]], :lower16:A
+; CHECK-NEXT: movt  [[reg0]], :upper16:A
+; CHECK:      vldmia [[reg0]], {{.*}}
+
+; CHECK:      {{[v]?mov}}  r0, {{[r|s][0-9]+}}
+; CHECK:      bl  powf
+
+; CHECK:      {{[v]?mov}}  r0, {{[r|s][0-9]+}}
+; CHECK:      bl  powf
+
+; CHECK:      {{[v]?mov}}  r0, {{[r|s][0-9]+}}
+; CHECK:      bl  powf
+
+; CHECK:      {{[v]?mov}}  r0, {{[r|s][0-9]+}}
+; CHECK:      bl  powf
+
+; CHECK:      vstmia  {{.*}}
+
+L.entry:
+
+  %0 = load <4 x float>* @A, align 16
+  %1 = call <4 x float> @llvm.pow.v4f32(<4 x float> %0, <4 x float> )
+
+  store <4 x float> %1, <4 x float>* %X, align 16
+
+  ret void
+}
+
+declare <4 x float> @llvm.pow.v4f32(<4 x float>, <4 x float>) nounwind readonly
+
+define void @test_powi(<4 x float>* %X) nounwind {
+
+; CHECK: test_powi:
+
+; CHECK:       movw  [[reg0:r[0-9]+]], :lower16:A
+; CHECK-NEXT:  movt  [[reg0]], :upper16:A
+; CHECK-NEXT:  vldmia  [[reg0]], {{.*}}
+; CHECK:       vmul.f32 {{.*}}
+
+; CHECK:      vstmia  {{.*}}
+
+L.entry:
+
+  %0 = load <4 x float>* @A, align 16
+  %1 = call <4 x float> @llvm.powi.v4f32(<4 x float> %0, i32 2)
+
+  store <4 x float> %1, <4 x float>* %X, align 16
+
+  ret void
+}
+
+declare <4 x float> @llvm.powi.v4f32(<4 x float>, i32) nounwind readonly
+
+define void @test_sin(<4 x float>* %X) nounwind {
+
+; CHECK: test_sin:
+
+; CHECK:      movw  [[reg0:r[0-9]+]], :lower16:A
+; CHECK-NEXT: movt  [[reg0]], :upper16:A
+; CHECK:      vldmia [[reg0]], {{.*}}
+
+; CHECK:      {{[v]?mov}}  r0, {{[r|s][0-9]+}}
+; CHECK:      bl  sinf
+
+; CHECK:      {{[v]?mov}}  r0, {{[r|s][0-9]+}}
+; CHECK:      bl  sinf
+
+; CHECK:      {{[v]?mov}}  r0, {{[r|s][0-9]+}}
+; CHECK:      bl  sinf
+
+; CHECK:      {{[v]?mov}}  r0, {{[r|s][0-9]+}}
+; CHECK:      bl  sinf
+
+; CHECK:      vstmia  {{.*}}
+
+L.entry:
+  %0 = load <4 x float>* @A, align 16
+  %1 = call <4 x float> @llvm.sin.v4f32(<4 x float> %0)
+  store <4 x float> %1, <4 x float>* %X, align 16
+  ret void
+}
+
+declare <4 x float> @llvm.sin.v4f32(<4 x float>) nounwind readonly
+



From stpworld at narod.ru  Thu Dec  8 01:59:59 2011
From: stpworld at narod.ru (Stepan Dyatkovskiy)
Date: Thu, 08 Dec 2011 11:59:59 +0400
Subject: [llvm-commits] [LLVM,
 SelectionDAG] fix for #9905: Failure in code selection for llvm
 intrinsics sqrt/exp
In-Reply-To: 
References: <4ED74593.2030003@narod.ru> <4ED9D140.2070504@narod.ru>
	<4EDCC1A2.5010500@narod.ru>
	
	<4EDDE0E1.5060200@narod.ru> <4EDDE47C.4000905@narod.ru>
	
	<4EDF4307.4060909@narod.ru>
	
Message-ID: <4EE06E7F.9000001@narod.ru>

Thanks, Eli.
I have write-access. Committed as r146143.

-Stepan.

Eli Friedman wrote:
> On Wed, Dec 7, 2011 at 2:42 AM, Stepan Dyatkovskiy  wrote:
>> Please, look at fixed patch in attachment.
>
> Looks fine.  Do you need me to commit this for you?
>
> -Eli
>
>> Thanks.
>> -Stepan.
>>
>>
>> Eli Friedman wrote:
>>>
>>> On Tue, Dec 6, 2011 at 1:46 AM, Stepan Dyatkovskiy
>>>   wrote:
>>>>
>>>> Sorry for previous post. Forgot to remove extra newlines at the end of
>>>> file.
>>>> Fixed file is attached here.
>>>
>>>
>>> Better... but please try to make it less sensitive to register
>>> allocation and scheduler choices.
>>>
>>> -Eli
>>>
>>>>
>>>> Thanks.
>>>> -Stepan.
>>>>
>>>>
>>>> Stepan Dyatkovskiy wrote:
>>>>>
>>>>>
>>>>> OK. Please look at reworked regression test patch in attachment.
>>>>>
>>>>> -Stepan.
>>>>>
>>>>> Eli Friedman wrote:
>>>>>>
>>>>>>
>>>>>> The code changes look fine. Please put all the FileCheck tests into
>>>>>> one file, and only use CHECK lines for the most important pieces
>>>>>> (specifically, that we call sinf etc.).
>>>>>>
>>>>>> -Eli
>>>>>>
>>>>>> On Mon, Dec 5, 2011 at 5:05 AM, Stepan Dyatkovskiy
>>>>>> wrote:
>>>>>>>
>>>>>>>
>>>>>>> ping.
>>>>>>>
>>>>>>> -Stepan.
>>>>>>>
>>>>>>> Stepan Dyatkovskiy wrote:
>>>>>>>>
>>>>>>>>
>>>>>>>> ping.
>>>>>>>>
>>>>>>>> -Stepan
>>>>>>>>
>>>>>>>> Stepan Dyatkovskiy wrote:
>>>>>>>>>
>>>>>>>>>
>>>>>>>>> Hi all. Please find the patch and regression tests in attachment for
>>>>>>>>> review.
>>>>>>>>> This patch for ARM. It fixes selection for several instructions that
>>>>>>>>> works with v4f32 arguments: FSQRT, FSIN, FCOS, FPOWI, FPOW, FLOG,
>>>>>>>>> FLOG2,
>>>>>>>>> FLOG10, FEXP, FEXP2.
>>>>>>>>> I'm still worrying about FCOPYSIGN, FNEG, FABS, FCEIL, FTRUNC,
>>>>>>>>> FRINT,
>>>>>>>>> FNEARBYINT, FFLOOR. I could not found a way to add this instructions
>>>>>>>>> with v2f32 argument to DAG. It seems that it is impossible in ToT.
>>>>>>>>> So
>>>>>>>>> these instructions was not fixed.
>>>>>>>>>
>>>>>>>>> -Stepan.
>>>>>>>>>
>>>>>>>>>
>>>>>>>>> _______________________________________________
>>>>>>>>> llvm-commits mailing list
>>>>>>>>> llvm-commits at cs.uiuc.edu
>>>>>>>>> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
>>>>>>>>
>>>>>>>>
>>>>>>>>
>>>>>>>> _______________________________________________
>>>>>>>> llvm-commits mailing list
>>>>>>>> llvm-commits at cs.uiuc.edu
>>>>>>>> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
>>>>>>>
>>>>>>>
>>>>>>>
>>>>>>> _______________________________________________
>>>>>>> llvm-commits mailing list
>>>>>>> llvm-commits at cs.uiuc.edu
>>>>>>> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
>>>>>
>>>>>
>>>>>
>>>>>
>>>>>
>>>>> _______________________________________________
>>>>> llvm-commits mailing list
>>>>> llvm-commits at cs.uiuc.edu
>>>>> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
>>>>
>>>>
>>>>
>>


From grosser at fim.uni-passau.de  Thu Dec  8 07:02:58 2011
From: grosser at fim.uni-passau.de (Tobias Grosser)
Date: Thu, 08 Dec 2011 13:02:58 -0000
Subject: [llvm-commits] [polly] r146149 - in /polly/trunk:
 lib/ScheduleOptimizer.cpp
 test/ScheduleOptimizer/2011-08-25-crash_in_vectorizer.ll
Message-ID: <20111208130258.833C02A6C12C@llvm.org>

Author: grosser
Date: Thu Dec  8 07:02:58 2011
New Revision: 146149

URL: http://llvm.org/viewvc/llvm-project?rev=146149&view=rev
Log:
ScheduleOptimizer: Do not tile bands with just one dimension

Modified:
    polly/trunk/lib/ScheduleOptimizer.cpp
    polly/trunk/test/ScheduleOptimizer/2011-08-25-crash_in_vectorizer.ll

Modified: polly/trunk/lib/ScheduleOptimizer.cpp
URL: http://llvm.org/viewvc/llvm-project/polly/trunk/lib/ScheduleOptimizer.cpp?rev=146149&r1=146148&r2=146149&view=diff
==============================================================================
--- polly/trunk/lib/ScheduleOptimizer.cpp (original)
+++ polly/trunk/lib/ScheduleOptimizer.cpp Thu Dec  8 07:02:58 2011
@@ -200,27 +200,34 @@
 
 // getScheduleForBand - Get the schedule for this band.
 //
-// In case tiling is enabled, the schedule of the band is tiled.
-isl_union_map *getScheduleForBand(isl_band *Band) {
+// Polly applies transformations like tiling on top of the isl calculated value.
+// This can influence the number of scheduling dimension. The number of
+// schedule dimensions is returned in the parameter 'Dimension'.
+isl_union_map *getScheduleForBand(isl_band *Band, int *Dimensions) {
   isl_union_map *PartialSchedule;
-  int Dimensions;
   isl_ctx *ctx;
   isl_space *Space;
   isl_basic_map *TileMap;
   isl_union_map *TileUMap;
 
   PartialSchedule = isl_band_get_partial_schedule(Band);
+  *Dimensions = isl_band_n_member(Band);
 
   if (DisableTiling)
     return PartialSchedule;
 
+  // It does not make any sense to tile a band with just one dimension.
+  if (*Dimensions == 1)
+    return PartialSchedule;
+
   ctx = isl_union_map_get_ctx(PartialSchedule);
   Space = isl_union_map_get_space(PartialSchedule);
-  Dimensions = isl_band_n_member(Band);
 
-  TileMap = getTileMap(ctx, Dimensions, Space);
+  TileMap = getTileMap(ctx, *Dimensions, Space);
   TileUMap = isl_union_map_from_map(isl_map_from_basic_map(TileMap));
   TileUMap = isl_union_map_align_params(TileUMap, Space);
+  *Dimensions = 2 * *Dimensions;
+
   return isl_union_map_apply_range(PartialSchedule, TileUMap);
 }
 
@@ -348,8 +355,7 @@
     isl_space *Space;
 
     Band = isl_band_list_get_band(BandList, i);
-    PartialSchedule = getScheduleForBand(Band);
-    ScheduleDimensions = isl_band_n_member(Band);
+    PartialSchedule = getScheduleForBand(Band, &ScheduleDimensions);
     Space = isl_union_map_get_space(PartialSchedule);
 
     if (isl_band_has_children(Band)) {
@@ -367,8 +373,7 @@
           isl_map *TileMap;
           isl_union_map *TileUMap;
 
-	  TileMap = getPrevectorMap(ctx, ScheduleDimensions + i,
-				    ScheduleDimensions * 2);
+	  TileMap = getPrevectorMap(ctx, i, ScheduleDimensions);
 	  TileUMap = isl_union_map_from_map(TileMap);
           TileUMap = isl_union_map_align_params(TileUMap,
                                                 isl_space_copy(Space));

Modified: polly/trunk/test/ScheduleOptimizer/2011-08-25-crash_in_vectorizer.ll
URL: http://llvm.org/viewvc/llvm-project/polly/trunk/test/ScheduleOptimizer/2011-08-25-crash_in_vectorizer.ll?rev=146149&r1=146148&r2=146149&view=diff
==============================================================================
--- polly/trunk/test/ScheduleOptimizer/2011-08-25-crash_in_vectorizer.ll (original)
+++ polly/trunk/test/ScheduleOptimizer/2011-08-25-crash_in_vectorizer.ll Thu Dec  8 07:02:58 2011
@@ -30,21 +30,15 @@
 }
 
 ; CHECK: if (p_0 >= 1) {
-; CHECK:     for (c1=0;c1<=p_0-1;c1+=32) {
-; CHECK:           for (c2=c1;c2<=min(c1+31,p_0-1);c2++) {
-; CHECK:                   Stmt_bb2(c2);
-; CHECK:           }
+; CHECK:     for (c1=0;c1<=p_0-1;c1++) {
+; CHECK:         Stmt_bb2(c1);
 ; CHECK:     }
 ; CHECK: }
 
 ; VECTOR: if (p_0 >= 1) {
-; VECTOR:   for (c1=0;c1<=p_0-1;c1+=32) {
-; VECTOR:     for (c2=-4*floord(-c1,4);c2<=min(c1+31,p_0-1);c2+=4) {
-; VECTOR:       for (c3=c2;c3<=min(c2+3,p_0-1);c3++) {
-; VECTOR:         Stmt_bb2(c3);
-; VECTOR:       }
+; VECTOR:   for (c1=0;c1<=p_0-1;c1+=4) {
+; VECTOR:     for (c2=c1;c2<=min(c1+3,p_0-1);c2++) {
+; VECTOR:       Stmt_bb2(c2);
 ; VECTOR:     }
 ; VECTOR:   }
 ; VECTOR: }
-
-



From nadav.rotem at intel.com  Thu Dec  8 07:10:01 2011
From: nadav.rotem at intel.com (Nadav Rotem)
Date: Thu, 08 Dec 2011 13:10:01 -0000
Subject: [llvm-commits] [llvm] r146150 - in /llvm/trunk:
 lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
 test/CodeGen/X86/2011-12-8-bitcastintprom.ll
 test/CodeGen/X86/vec_compare-2.ll test/CodeGen/X86/widen_arith-3.ll
Message-ID: <20111208131001.F09742A6C12C@llvm.org>

Author: nadav
Date: Thu Dec  8 07:10:01 2011
New Revision: 146150

URL: http://llvm.org/viewvc/llvm-project?rev=146150&view=rev
Log:
Fix a bug in the integer-promotion of bitcast operations on vector types.
We must not issue a bitcast operation for integer-promotion of vector types, because the
location of the values in the vector may be different.


Added:
    llvm/trunk/test/CodeGen/X86/2011-12-8-bitcastintprom.ll
Modified:
    llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
    llvm/trunk/test/CodeGen/X86/vec_compare-2.ll
    llvm/trunk/test/CodeGen/X86/widen_arith-3.ll

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp?rev=146150&r1=146149&r2=146150&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp Thu Dec  8 07:10:01 2011
@@ -216,7 +216,7 @@
   case TargetLowering::TypeLegal:
     break;
   case TargetLowering::TypePromoteInteger:
-    if (NOutVT.bitsEq(NInVT))
+    if (NOutVT.bitsEq(NInVT) && !NOutVT.isVector() && !NInVT.isVector())
       // The input promotes to the same size.  Convert the promoted value.
       return DAG.getNode(ISD::BITCAST, dl, NOutVT, GetPromotedInteger(InOp));
     break;

Added: llvm/trunk/test/CodeGen/X86/2011-12-8-bitcastintprom.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2011-12-8-bitcastintprom.ll?rev=146150&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/X86/2011-12-8-bitcastintprom.ll (added)
+++ llvm/trunk/test/CodeGen/X86/2011-12-8-bitcastintprom.ll Thu Dec  8 07:10:01 2011
@@ -0,0 +1,15 @@
+; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=corei7 | FileCheck %s
+
+; Make sure that the conversion between v4i8 to v2i16 is not a simple bitcast.
+; CHECK: prom_bug
+; CHECK: movd
+; CHECK: shufb
+; CHECK: movw
+; CHECK: ret
+define void @prom_bug(<4 x i8> %t, i16* %p) {
+  %r = bitcast <4 x i8> %t to <2 x i16>
+  %o = extractelement <2 x i16> %r, i32 0
+  store i16 %o, i16* %p
+  ret void
+}
+

Modified: llvm/trunk/test/CodeGen/X86/vec_compare-2.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/vec_compare-2.ll?rev=146150&r1=146149&r2=146150&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/vec_compare-2.ll (original)
+++ llvm/trunk/test/CodeGen/X86/vec_compare-2.ll Thu Dec  8 07:10:01 2011
@@ -8,6 +8,7 @@
 
 define void @blackDespeckle_wrapper(i8** %args_list, i64* %gtid, i64 %xend) {
 entry:
+; CHECK: cfi_def_cfa_offset
 ; CHECK-NOT: set
 ; CHECK: pcmpgt
 ; CHECK: blendvps

Modified: llvm/trunk/test/CodeGen/X86/widen_arith-3.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/widen_arith-3.ll?rev=146150&r1=146149&r2=146150&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/widen_arith-3.ll (original)
+++ llvm/trunk/test/CodeGen/X86/widen_arith-3.ll Thu Dec  8 07:10:01 2011
@@ -1,5 +1,5 @@
 ; RUN: llc < %s -march=x86 -mattr=+sse42 -post-RA-scheduler=true | FileCheck %s
-; CHECK: incw
+; CHECK: incl
 ; CHECK: incl
 ; CHECK: incl
 ; CHECK: addl



From eugeni.stepanov at gmail.com  Thu Dec  8 08:38:36 2011
From: eugeni.stepanov at gmail.com (Evgeniy Stepanov)
Date: Thu, 8 Dec 2011 18:38:36 +0400
Subject: [llvm-commits] [PATCH] ASan/Android: fall back to the system
 allocator for unexpected deallocations
Message-ID: 

On Android, allocations from static constructors of uninstrumented
libraries occur before we have a chance to replace the allocator. This
patch helps avoid crashing on the matching deallocations.
-------------- next part --------------
A non-text attachment was scrubbed...
Name: android_malloc.patch
Type: text/x-patch
Size: 1017 bytes
Desc: not available
Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20111208/588d343c/attachment.bin 

From jan_sjodin at yahoo.com  Thu Dec  8 09:22:41 2011
From: jan_sjodin at yahoo.com (Jan Sjodin)
Date: Thu, 8 Dec 2011 07:22:41 -0800 (PST)
Subject: [llvm-commits] FMA4 cleanup patch
In-Reply-To: 
References: <1323273015.33804.YahooMailNeo@web161505.mail.bf1.yahoo.com>
	
Message-ID: <1323357761.94437.YahooMailNeo@web161502.mail.bf1.yahoo.com>

Committed?146151

Thanks!

- Jan



>________________________________
> From: Bruno Cardoso Lopes 
>To: Jan Sjodin  
>Cc: "llvm-commits at cs.uiuc.edu"  
>Sent: Wednesday, December 7, 2011 5:57 PM
>Subject: Re: FMA4 cleanup patch
> 
>LGTM! Can you add testcases?
>
>On Wed, Dec 7, 2011 at 1:50 PM, Jan Sjodin  wrote:
>> Patch to clean up the FMA4 encoding. I had accidentally swapped the operands
>> in the asm strings for the FMA4 rr patterns, which caused some confusion.
>> Ok to commit?
>>
>> - Jan
>
>
>
>-- 
>Bruno Cardoso Lopes
>http://www.brunocardoso.cc
>
>
>
-------------- next part --------------
An HTML attachment was scrubbed...
URL: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20111208/a59d8ceb/attachment.html 

From geek4civic at gmail.com  Thu Dec  8 09:24:10 2011
From: geek4civic at gmail.com (NAKAMURA Takumi)
Date: Thu, 08 Dec 2011 15:24:10 -0000
Subject: [llvm-commits] [llvm] r146152 -
	/llvm/trunk/test/CodeGen/X86/vec_compare-2.ll
Message-ID: <20111208152410.1620A2A6C12C@llvm.org>

Author: chapuni
Date: Thu Dec  8 09:24:09 2011
New Revision: 146152

URL: http://llvm.org/viewvc/llvm-project?rev=146152&view=rev
Log:
test/CodeGen/X86/vec_compare-2.ll: Add explicit -mtriple=i686-linux.

Modified:
    llvm/trunk/test/CodeGen/X86/vec_compare-2.ll

Modified: llvm/trunk/test/CodeGen/X86/vec_compare-2.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/vec_compare-2.ll?rev=146152&r1=146151&r2=146152&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/vec_compare-2.ll (original)
+++ llvm/trunk/test/CodeGen/X86/vec_compare-2.ll Thu Dec  8 09:24:09 2011
@@ -1,4 +1,4 @@
-; RUN: llc < %s -march=x86 -mcpu=penryn | FileCheck %s
+; RUN: llc < %s -mtriple=i686-linux -mcpu=penryn | FileCheck %s
 
 declare <4 x float> @llvm.x86.sse41.blendvps(<4 x float>, <4 x float>, <4 x float>) nounwind readnone
 



From glider at google.com  Thu Dec  8 09:15:27 2011
From: glider at google.com (Alexander Potapenko)
Date: Thu, 8 Dec 2011 19:15:27 +0400
Subject: [llvm-commits] [PATCH] fix the version of mach_override/* in
 AddressSanitizer to run on OS X Lion
Message-ID: 

This patch contains several changes to mach_override/* that allow to
build and run AddressSanitizer tests on OS X Lion (10.7):

 -- mach_override.c is merged with the upstream version at
https://github.com/rentzsch/mach_star/tree/f8e0c424b5be5cb641ded67c265e616157ae4bcf
(I've copied it and added the DEBUG_DISASM code and additional opcodes
from our version)
 -- #ifdef __APPLE__ is removed from both files (we shouldn't need it,
because mach_override is used on Mac only)
 -- some opcodes are added in order to parse the library functions on Lion
 -- fixupInstructions() is extended to relocate relative calls, not only jumps


--
Alexander Potapenko
Software Engineer
Google Moscow

From glider at google.com  Thu Dec  8 09:16:14 2011
From: glider at google.com (Alexander Potapenko)
Date: Thu, 8 Dec 2011 19:16:14 +0400
Subject: [llvm-commits] [PATCH] fix the version of mach_override/* in
 AddressSanitizer to run on OS X Lion
In-Reply-To: 
References: 
Message-ID: 

On Thu, Dec 8, 2011 at 7:15 PM, Alexander Potapenko  wrote:
> This patch contains several changes to mach_override/* that allow to
> build and run AddressSanitizer tests on OS X Lion (10.7):
>
> ?-- mach_override.c is merged with the upstream version at
> https://github.com/rentzsch/mach_star/tree/f8e0c424b5be5cb641ded67c265e616157ae4bcf
> (I've copied it and added the DEBUG_DISASM code and additional opcodes
> from our version)
> ?-- #ifdef __APPLE__ is removed from both files (we shouldn't need it,
> because mach_override is used on Mac only)
> ?-- some opcodes are added in order to parse the library functions on Lion
> ?-- fixupInstructions() is extended to relocate relative calls, not only jumps
Oh, and the patch itself. See attached.
-------------- next part --------------
A non-text attachment was scrubbed...
Name: mach_override.patch
Type: text/x-patch
Size: 18270 bytes
Desc: not available
Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20111208/ac19ea05/attachment.bin 

From simbuerg at fim.uni-passau.de  Thu Dec  8 10:08:34 2011
From: simbuerg at fim.uni-passau.de (Andreas Simbuerger)
Date: Thu,  8 Dec 2011 17:08:34 +0100
Subject: [llvm-commits] [PATCH] Fix profile info consistency check.
Message-ID: <1323360514-22792-1-git-send-email-simbuerg@fim.uni-passau.de>

The consistency check for EdgeProfile Info is only
working if the IR code consists of less edges than
the read profile information.

It should work on codes with more edges than read too.
---
 lib/Analysis/ProfileInfoLoaderPass.cpp |    6 ++++--
 1 files changed, 4 insertions(+), 2 deletions(-)

diff --git a/lib/Analysis/ProfileInfoLoaderPass.cpp b/lib/Analysis/ProfileInfoLoaderPass.cpp
index 098079b..0875a2c 100644
--- a/lib/Analysis/ProfileInfoLoaderPass.cpp
+++ b/lib/Analysis/ProfileInfoLoaderPass.cpp
@@ -132,7 +132,7 @@ void LoaderPass::recurseBasicBlock(const BasicBlock *BB) {
 void LoaderPass::readEdge(ProfileInfo::Edge e,
                           std::vector &ECs) {
   if (ReadCount < ECs.size()) {
-    double weight = ECs[ReadCount++];
+    double weight = ECs[ReadCount];
     if (weight != ProfileInfoLoader::Uncounted) {
       // Here the data realm changes from the unsigned of the file to the
       // double of the ProfileInfo. This conversion is save because we know
@@ -141,7 +141,7 @@ void LoaderPass::readEdge(ProfileInfo::Edge e,
       EdgeInformation[getFunction(e)][e] += (double)weight;
 
       DEBUG(dbgs() << "--Read Edge Counter for " << e
-                   << " (# "<< (ReadCount-1) << "): "
+                   << " (# "<< ReadCount << "): "
                    << (unsigned)getEdgeWeight(e) << "\n");
     } else {
       // This happens only if reading optimal profiling information, not when
@@ -149,6 +149,8 @@ void LoaderPass::readEdge(ProfileInfo::Edge e,
       SpanningTree.insert(e);
     }
   }
+
+  ReadCount++;
 }
 
 bool LoaderPass::runOnModule(Module &M) {
-- 
1.7.4.1


From daniel at zuster.org  Thu Dec  8 11:32:18 2011
From: daniel at zuster.org (Daniel Dunbar)
Date: Thu, 08 Dec 2011 17:32:18 -0000
Subject: [llvm-commits] [llvm] r146157 - in /llvm/trunk:
 lib/Target/ARM/ARMISelLowering.cpp
 test/CodeGen/ARM/2011-11-29-128bitArithmetics.ll
Message-ID: <20111208173218.4FECE2A6C12C@llvm.org>

Author: ddunbar
Date: Thu Dec  8 11:32:18 2011
New Revision: 146157

URL: http://llvm.org/viewvc/llvm-project?rev=146157&view=rev
Log:
Revert r146143, "Fix bug 9905: Failure in code selection for llvm intrinsics
sqrt/exp (fix for FSQRT, FSIN, FCOS, FPOWI, FPOW, FLOG, FLOG2, FLOG10, FEXP,
FEXP2).", it is failing tests.

Removed:
    llvm/trunk/test/CodeGen/ARM/2011-11-29-128bitArithmetics.ll
Modified:
    llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp

Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp?rev=146157&r1=146156&r2=146157&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp Thu Dec  8 11:32:18 2011
@@ -468,23 +468,13 @@
 
     // v2f64 is legal so that QR subregs can be extracted as f64 elements, but
     // neither Neon nor VFP support any arithmetic operations on it.
-    // The same with v4f32. But keep in mind that vadd, vsub, vmul are natively
-    // supported for v4f32.
     setOperationAction(ISD::FADD, MVT::v2f64, Expand);
     setOperationAction(ISD::FSUB, MVT::v2f64, Expand);
     setOperationAction(ISD::FMUL, MVT::v2f64, Expand);
-    // FIXME: Code duplication: FDIV and FREM are expanded always, see
-    // ARMTargetLowering::addTypeForNEON method for details.
     setOperationAction(ISD::FDIV, MVT::v2f64, Expand);
     setOperationAction(ISD::FREM, MVT::v2f64, Expand);
-    // FIXME: Create unittest.
-    // In another words, find a way when "copysign" appears in DAG with vector
-    // operands.
     setOperationAction(ISD::FCOPYSIGN, MVT::v2f64, Expand);
-    // FIXME: Code duplication: SETCC has custom operation action, see
-    // ARMTargetLowering::addTypeForNEON method for details.
     setOperationAction(ISD::SETCC, MVT::v2f64, Expand);
-    // FIXME: Create unittest for FNEG and for FABS.
     setOperationAction(ISD::FNEG, MVT::v2f64, Expand);
     setOperationAction(ISD::FABS, MVT::v2f64, Expand);
     setOperationAction(ISD::FSQRT, MVT::v2f64, Expand);
@@ -497,23 +487,11 @@
     setOperationAction(ISD::FLOG10, MVT::v2f64, Expand);
     setOperationAction(ISD::FEXP, MVT::v2f64, Expand);
     setOperationAction(ISD::FEXP2, MVT::v2f64, Expand);
-    // FIXME: Create unittest for FCEIL, FTRUNC, FRINT, FNEARBYINT, FFLOOR.
     setOperationAction(ISD::FCEIL, MVT::v2f64, Expand);
     setOperationAction(ISD::FTRUNC, MVT::v2f64, Expand);
     setOperationAction(ISD::FRINT, MVT::v2f64, Expand);
     setOperationAction(ISD::FNEARBYINT, MVT::v2f64, Expand);
     setOperationAction(ISD::FFLOOR, MVT::v2f64, Expand);
-    
-    setOperationAction(ISD::FSQRT, MVT::v4f32, Expand);
-    setOperationAction(ISD::FSIN, MVT::v4f32, Expand);
-    setOperationAction(ISD::FCOS, MVT::v4f32, Expand);
-    setOperationAction(ISD::FPOWI, MVT::v4f32, Expand);
-    setOperationAction(ISD::FPOW, MVT::v4f32, Expand);
-    setOperationAction(ISD::FLOG, MVT::v4f32, Expand);
-    setOperationAction(ISD::FLOG2, MVT::v4f32, Expand);
-    setOperationAction(ISD::FLOG10, MVT::v4f32, Expand);
-    setOperationAction(ISD::FEXP, MVT::v4f32, Expand);
-    setOperationAction(ISD::FEXP2, MVT::v4f32, Expand);
 
     // Neon does not support some operations on v1i64 and v2i64 types.
     setOperationAction(ISD::MUL, MVT::v1i64, Expand);

Removed: llvm/trunk/test/CodeGen/ARM/2011-11-29-128bitArithmetics.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/2011-11-29-128bitArithmetics.ll?rev=146156&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/2011-11-29-128bitArithmetics.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/2011-11-29-128bitArithmetics.ll (removed)
@@ -1,302 +0,0 @@
-; RUN: llc < %s -march=arm -mcpu=cortex-a9 | FileCheck %s
-
- at A = global <4 x float> 
-
-define void @test_sqrt(<4 x float>* %X) nounwind {
-
-; CHECK: test_sqrt:
-
-; CHECK:      movw    r1, :lower16:A
-; CHECK-NEXT: movt    r1, :upper16:A
-; CHECK:      vldmia  r1, {[[short0:s[0-9]+]], [[short1:s[0-9]+]], [[short2:s[0-9]+]], [[short3:s[0-9]+]]}
-; CHECK:      vsqrt.f32       {{s[0-9]+}}, [[short3]]
-; CHECK:      vsqrt.f32       {{s[0-9]+}}, [[short2]]
-; CHECK:      vsqrt.f32       {{s[0-9]+}}, [[short1]]
-; CHECK:      vsqrt.f32       {{s[0-9]+}}, [[short0]]
-; CHECK-NEXT: vstmia  {{.*}}
-
-L.entry:
-  %0 = load <4 x float>* @A, align 16
-  %1 = call <4 x float> @llvm.sqrt.v4f32(<4 x float> %0)
-  store <4 x float> %1, <4 x float>* %X, align 16
-  ret void
-}
-
-declare <4 x float> @llvm.sqrt.v4f32(<4 x float>) nounwind readonly
-
-
-define void @test_cos(<4 x float>* %X) nounwind {
-
-; CHECK: test_cos:
-
-; CHECK:      movw  [[reg0:r[0-9]+]], :lower16:A
-; CHECK-NEXT: movt  [[reg0]], :upper16:A
-; CHECK:      vldmia [[reg0]], {{.*}}
-
-; CHECK:      {{[v]?mov}}  r0, {{[r|s][0-9]+}}
-; CHECK:      bl  cosf
-
-; CHECK:      {{[v]?mov}}  r0, {{[r|s][0-9]+}}
-; CHECK:      bl  cosf
-
-; CHECK:      {{[v]?mov}}  r0, {{[r|s][0-9]+}}
-; CHECK:      bl  cosf
-
-; CHECK:      {{[v]?mov}}  r0, {{[r|s][0-9]+}}
-; CHECK:      bl  cosf
-
-; CHECK:      vstmia  {{.*}}
-
-L.entry:
-  %0 = load <4 x float>* @A, align 16
-  %1 = call <4 x float> @llvm.cos.v4f32(<4 x float> %0)
-  store <4 x float> %1, <4 x float>* %X, align 16
-  ret void
-}
-
-declare <4 x float> @llvm.cos.v4f32(<4 x float>) nounwind readonly
-
-define void @test_exp(<4 x float>* %X) nounwind {
-
-; CHECK: test_exp:
-
-; CHECK:      movw  [[reg0:r[0-9]+]], :lower16:A
-; CHECK-NEXT: movt  [[reg0]], :upper16:A
-; CHECK:      vldmia [[reg0]], {{.*}}
-
-; CHECK:      {{[v]?mov}}  r0, {{[r|s][0-9]+}}
-; CHECK:      bl  expf
-
-; CHECK:      {{[v]?mov}}  r0, {{[r|s][0-9]+}}
-; CHECK:      bl  expf
-
-; CHECK:      {{[v]?mov}}  r0, {{[r|s][0-9]+}}
-; CHECK:      bl  expf
-
-; CHECK:      {{[v]?mov}}  r0, {{[r|s][0-9]+}}
-; CHECK:      bl  expf
-
-; CHECK:      vstmia  {{.*}}
-
-L.entry:
-  %0 = load <4 x float>* @A, align 16
-  %1 = call <4 x float> @llvm.exp.v4f32(<4 x float> %0)
-  store <4 x float> %1, <4 x float>* %X, align 16
-  ret void
-}
-
-declare <4 x float> @llvm.exp.v4f32(<4 x float>) nounwind readonly
-
-define void @test_exp2(<4 x float>* %X) nounwind {
-
-; CHECK: test_exp2:
-
-; CHECK:      movw  [[reg0:r[0-9]+]], :lower16:A
-; CHECK-NEXT: movt  [[reg0]], :upper16:A
-; CHECK:      vldmia [[reg0]], {{.*}}
-
-; CHECK:      {{[v]?mov}}  r0, {{[r|s][0-9]+}}
-; CHECK:      bl  exp2f
-
-; CHECK:      {{[v]?mov}}  r0, {{[r|s][0-9]+}}
-; CHECK:      bl  exp2f
-
-; CHECK:      {{[v]?mov}}  r0, {{[r|s][0-9]+}}
-; CHECK:      bl  exp2f
-
-; CHECK:      {{[v]?mov}}  r0, {{[r|s][0-9]+}}
-; CHECK:      bl  exp2f
-
-; CHECK:      vstmia  {{.*}}
-
-L.entry:
-  %0 = load <4 x float>* @A, align 16
-  %1 = call <4 x float> @llvm.exp2.v4f32(<4 x float> %0)
-  store <4 x float> %1, <4 x float>* %X, align 16
-  ret void
-}
-
-declare <4 x float> @llvm.exp2.v4f32(<4 x float>) nounwind readonly
-
-define void @test_log10(<4 x float>* %X) nounwind {
-
-; CHECK: test_log10:
-
-; CHECK:      movw  [[reg0:r[0-9]+]], :lower16:A
-; CHECK-NEXT: movt  [[reg0]], :upper16:A
-; CHECK:      vldmia [[reg0]], {{.*}}
-
-; CHECK:      {{[v]?mov}}  r0, {{[r|s][0-9]+}}
-; CHECK:      bl  log10f
-
-; CHECK:      {{[v]?mov}}  r0, {{[r|s][0-9]+}}
-; CHECK:      bl  log10f
-
-; CHECK:      {{[v]?mov}}  r0, {{[r|s][0-9]+}}
-; CHECK:      bl  log10f
-
-; CHECK:      {{[v]?mov}}  r0, {{[r|s][0-9]+}}
-; CHECK:      bl  log10f
-
-; CHECK:      vstmia  {{.*}}
-
-L.entry:
-  %0 = load <4 x float>* @A, align 16
-  %1 = call <4 x float> @llvm.log10.v4f32(<4 x float> %0)
-  store <4 x float> %1, <4 x float>* %X, align 16
-  ret void
-}
-
-declare <4 x float> @llvm.log10.v4f32(<4 x float>) nounwind readonly
-
-define void @test_log(<4 x float>* %X) nounwind {
-
-; CHECK: test_log:
-
-; CHECK:      movw  [[reg0:r[0-9]+]], :lower16:A
-; CHECK-NEXT: movt  [[reg0]], :upper16:A
-; CHECK:      vldmia [[reg0]], {{.*}}
-
-; CHECK:      {{[v]?mov}}  r0, {{[r|s][0-9]+}}
-; CHECK:      bl  logf
-
-; CHECK:      {{[v]?mov}}  r0, {{[r|s][0-9]+}}
-; CHECK:      bl  logf
-
-; CHECK:      {{[v]?mov}}  r0, {{[r|s][0-9]+}}
-; CHECK:      bl  logf
-
-; CHECK:      {{[v]?mov}}  r0, {{[r|s][0-9]+}}
-; CHECK:      bl  logf
-
-; CHECK:      vstmia  {{.*}}
-
-L.entry:
-  %0 = load <4 x float>* @A, align 16
-  %1 = call <4 x float> @llvm.log.v4f32(<4 x float> %0)
-  store <4 x float> %1, <4 x float>* %X, align 16
-  ret void
-}
-
-declare <4 x float> @llvm.log.v4f32(<4 x float>) nounwind readonly
-
-define void @test_log2(<4 x float>* %X) nounwind {
-
-; CHECK: test_log2:
-
-; CHECK:      movw  [[reg0:r[0-9]+]], :lower16:A
-; CHECK-NEXT: movt  [[reg0]], :upper16:A
-; CHECK:      vldmia [[reg0]], {{.*}}
-
-; CHECK:      {{[v]?mov}}  r0, {{[r|s][0-9]+}}
-; CHECK:      bl  log2f
-
-; CHECK:      {{[v]?mov}}  r0, {{[r|s][0-9]+}}
-; CHECK:      bl  log2f
-
-; CHECK:      {{[v]?mov}}  r0, {{[r|s][0-9]+}}
-; CHECK:      bl  log2f
-
-; CHECK:      {{[v]?mov}}  r0, {{[r|s][0-9]+}}
-; CHECK:      bl  log2f
-
-; CHECK:      vstmia  {{.*}}
-
-L.entry:
-  %0 = load <4 x float>* @A, align 16
-  %1 = call <4 x float> @llvm.log2.v4f32(<4 x float> %0)
-  store <4 x float> %1, <4 x float>* %X, align 16
-  ret void
-}
-
-declare <4 x float> @llvm.log2.v4f32(<4 x float>) nounwind readonly
-
-
-define void @test_pow(<4 x float>* %X) nounwind {
-
-; CHECK: test_pow:
-
-; CHECK:      movw  [[reg0:r[0-9]+]], :lower16:A
-; CHECK-NEXT: movt  [[reg0]], :upper16:A
-; CHECK:      vldmia [[reg0]], {{.*}}
-
-; CHECK:      {{[v]?mov}}  r0, {{[r|s][0-9]+}}
-; CHECK:      bl  powf
-
-; CHECK:      {{[v]?mov}}  r0, {{[r|s][0-9]+}}
-; CHECK:      bl  powf
-
-; CHECK:      {{[v]?mov}}  r0, {{[r|s][0-9]+}}
-; CHECK:      bl  powf
-
-; CHECK:      {{[v]?mov}}  r0, {{[r|s][0-9]+}}
-; CHECK:      bl  powf
-
-; CHECK:      vstmia  {{.*}}
-
-L.entry:
-
-  %0 = load <4 x float>* @A, align 16
-  %1 = call <4 x float> @llvm.pow.v4f32(<4 x float> %0, <4 x float> )
-
-  store <4 x float> %1, <4 x float>* %X, align 16
-
-  ret void
-}
-
-declare <4 x float> @llvm.pow.v4f32(<4 x float>, <4 x float>) nounwind readonly
-
-define void @test_powi(<4 x float>* %X) nounwind {
-
-; CHECK: test_powi:
-
-; CHECK:       movw  [[reg0:r[0-9]+]], :lower16:A
-; CHECK-NEXT:  movt  [[reg0]], :upper16:A
-; CHECK-NEXT:  vldmia  [[reg0]], {{.*}}
-; CHECK:       vmul.f32 {{.*}}
-
-; CHECK:      vstmia  {{.*}}
-
-L.entry:
-
-  %0 = load <4 x float>* @A, align 16
-  %1 = call <4 x float> @llvm.powi.v4f32(<4 x float> %0, i32 2)
-
-  store <4 x float> %1, <4 x float>* %X, align 16
-
-  ret void
-}
-
-declare <4 x float> @llvm.powi.v4f32(<4 x float>, i32) nounwind readonly
-
-define void @test_sin(<4 x float>* %X) nounwind {
-
-; CHECK: test_sin:
-
-; CHECK:      movw  [[reg0:r[0-9]+]], :lower16:A
-; CHECK-NEXT: movt  [[reg0]], :upper16:A
-; CHECK:      vldmia [[reg0]], {{.*}}
-
-; CHECK:      {{[v]?mov}}  r0, {{[r|s][0-9]+}}
-; CHECK:      bl  sinf
-
-; CHECK:      {{[v]?mov}}  r0, {{[r|s][0-9]+}}
-; CHECK:      bl  sinf
-
-; CHECK:      {{[v]?mov}}  r0, {{[r|s][0-9]+}}
-; CHECK:      bl  sinf
-
-; CHECK:      {{[v]?mov}}  r0, {{[r|s][0-9]+}}
-; CHECK:      bl  sinf
-
-; CHECK:      vstmia  {{.*}}
-
-L.entry:
-  %0 = load <4 x float>* @A, align 16
-  %1 = call <4 x float> @llvm.sin.v4f32(<4 x float> %0)
-  store <4 x float> %1, <4 x float>* %X, align 16
-  ret void
-}
-
-declare <4 x float> @llvm.sin.v4f32(<4 x float>) nounwind readonly
-



From daniel at zuster.org  Thu Dec  8 11:36:12 2011
From: daniel at zuster.org (Daniel Dunbar)
Date: Thu, 8 Dec 2011 09:36:12 -0800
Subject: [llvm-commits] [llvm] r146143 - in /llvm/trunk:
 lib/Target/ARM/ARMISelLowering.cpp
 test/CodeGen/ARM/2011-11-29-128bitArithmetics.ll
In-Reply-To: <20111208075503.BA6512A6C12C@llvm.org>
References: <20111208075503.BA6512A6C12C@llvm.org>
Message-ID: 

Hi Stepan,

This is failing tests (at least on some darwin platforms). I reverted
it, can you take a look?

Here is the lit output:
--
******************** TEST 'LLVM ::
CodeGen/ARM/2011-11-29-128bitArithmetics.ll' FAILED
********************Script:
--
/Users/buildslave/zorg/buildbot/smooshlab/slave-0.8/build.clang-x86_64-darwin10-gcc42-RA/clang-build/Release+Asserts/bin/llc
< /Users/buildslave/zorg/buildbot/smooshlab/slave-0.8/build.clang-x86_64-darwin10-gcc42-RA/llvm/test/CodeGen/ARM/2011-11-29-128bitArithmetics.ll
-march=arm -mcpu=cortex-a9 |
/Users/buildslave/zorg/buildbot/smooshlab/slave-0.8/build.clang-x86_64-darwin10-gcc42-RA/clang-build/Release+Asserts/bin/FileCheck
/Users/buildslave/zorg/buildbot/smooshlab/slave-0.8/build.clang-x86_64-darwin10-gcc42-RA/llvm/test/CodeGen/ARM/2011-11-29-128bitArithmetics.ll
--
Exit Code: 1
Command Output (stderr):
--
/Users/buildslave/zorg/buildbot/smooshlab/slave-0.8/build.clang-x86_64-darwin10-gcc42-RA/llvm/test/CodeGen/ARM/2011-11-29-128bitArithmetics.ll:9:10:
error: expected string not found in input
; CHECK: movw r1, :lower16:A
         ^
:10:13: note: scanning from here
_test_sqrt: @ @test_sqrt
            ^
:12:2: note: possible intended match here
 movw r1, :lower16:(_A-(LPC0_0+8))
 ^
--

********************
--

 - Daniel


On Wed, Dec 7, 2011 at 11:55 PM, Stepan Dyatkovskiy  wrote:
> Author: dyatkovskiy
> Date: Thu Dec ?8 01:55:03 2011
> New Revision: 146143
>
> URL: http://llvm.org/viewvc/llvm-project?rev=146143&view=rev
> Log:
> Fix bug 9905: Failure in code selection for llvm intrinsics sqrt/exp (fix for FSQRT, FSIN, FCOS, FPOWI, FPOW, FLOG, FLOG2, FLOG10, FEXP, FEXP2).
>
> Added:
> ? ?llvm/trunk/test/CodeGen/ARM/2011-11-29-128bitArithmetics.ll
> Modified:
> ? ?llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
>
> Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp?rev=146143&r1=146142&r2=146143&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp (original)
> +++ llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp Thu Dec ?8 01:55:03 2011
> @@ -468,13 +468,23 @@
>
> ? ? // v2f64 is legal so that QR subregs can be extracted as f64 elements, but
> ? ? // neither Neon nor VFP support any arithmetic operations on it.
> + ? ?// The same with v4f32. But keep in mind that vadd, vsub, vmul are natively
> + ? ?// supported for v4f32.
> ? ? setOperationAction(ISD::FADD, MVT::v2f64, Expand);
> ? ? setOperationAction(ISD::FSUB, MVT::v2f64, Expand);
> ? ? setOperationAction(ISD::FMUL, MVT::v2f64, Expand);
> + ? ?// FIXME: Code duplication: FDIV and FREM are expanded always, see
> + ? ?// ARMTargetLowering::addTypeForNEON method for details.
> ? ? setOperationAction(ISD::FDIV, MVT::v2f64, Expand);
> ? ? setOperationAction(ISD::FREM, MVT::v2f64, Expand);
> + ? ?// FIXME: Create unittest.
> + ? ?// In another words, find a way when "copysign" appears in DAG with vector
> + ? ?// operands.
> ? ? setOperationAction(ISD::FCOPYSIGN, MVT::v2f64, Expand);
> + ? ?// FIXME: Code duplication: SETCC has custom operation action, see
> + ? ?// ARMTargetLowering::addTypeForNEON method for details.
> ? ? setOperationAction(ISD::SETCC, MVT::v2f64, Expand);
> + ? ?// FIXME: Create unittest for FNEG and for FABS.
> ? ? setOperationAction(ISD::FNEG, MVT::v2f64, Expand);
> ? ? setOperationAction(ISD::FABS, MVT::v2f64, Expand);
> ? ? setOperationAction(ISD::FSQRT, MVT::v2f64, Expand);
> @@ -487,11 +497,23 @@
> ? ? setOperationAction(ISD::FLOG10, MVT::v2f64, Expand);
> ? ? setOperationAction(ISD::FEXP, MVT::v2f64, Expand);
> ? ? setOperationAction(ISD::FEXP2, MVT::v2f64, Expand);
> + ? ?// FIXME: Create unittest for FCEIL, FTRUNC, FRINT, FNEARBYINT, FFLOOR.
> ? ? setOperationAction(ISD::FCEIL, MVT::v2f64, Expand);
> ? ? setOperationAction(ISD::FTRUNC, MVT::v2f64, Expand);
> ? ? setOperationAction(ISD::FRINT, MVT::v2f64, Expand);
> ? ? setOperationAction(ISD::FNEARBYINT, MVT::v2f64, Expand);
> ? ? setOperationAction(ISD::FFLOOR, MVT::v2f64, Expand);
> +
> + ? ?setOperationAction(ISD::FSQRT, MVT::v4f32, Expand);
> + ? ?setOperationAction(ISD::FSIN, MVT::v4f32, Expand);
> + ? ?setOperationAction(ISD::FCOS, MVT::v4f32, Expand);
> + ? ?setOperationAction(ISD::FPOWI, MVT::v4f32, Expand);
> + ? ?setOperationAction(ISD::FPOW, MVT::v4f32, Expand);
> + ? ?setOperationAction(ISD::FLOG, MVT::v4f32, Expand);
> + ? ?setOperationAction(ISD::FLOG2, MVT::v4f32, Expand);
> + ? ?setOperationAction(ISD::FLOG10, MVT::v4f32, Expand);
> + ? ?setOperationAction(ISD::FEXP, MVT::v4f32, Expand);
> + ? ?setOperationAction(ISD::FEXP2, MVT::v4f32, Expand);
>
> ? ? // Neon does not support some operations on v1i64 and v2i64 types.
> ? ? setOperationAction(ISD::MUL, MVT::v1i64, Expand);
>
> Added: llvm/trunk/test/CodeGen/ARM/2011-11-29-128bitArithmetics.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/2011-11-29-128bitArithmetics.ll?rev=146143&view=auto
> ==============================================================================
> --- llvm/trunk/test/CodeGen/ARM/2011-11-29-128bitArithmetics.ll (added)
> +++ llvm/trunk/test/CodeGen/ARM/2011-11-29-128bitArithmetics.ll Thu Dec ?8 01:55:03 2011
> @@ -0,0 +1,302 @@
> +; RUN: llc < %s -march=arm -mcpu=cortex-a9 | FileCheck %s
> +
> + at A = global <4 x float> 
> +
> +define void @test_sqrt(<4 x float>* %X) nounwind {
> +
> +; CHECK: test_sqrt:
> +
> +; CHECK: ? ? ?movw ? ?r1, :lower16:A
> +; CHECK-NEXT: movt ? ?r1, :upper16:A
> +; CHECK: ? ? ?vldmia ?r1, {[[short0:s[0-9]+]], [[short1:s[0-9]+]], [[short2:s[0-9]+]], [[short3:s[0-9]+]]}
> +; CHECK: ? ? ?vsqrt.f32 ? ? ? {{s[0-9]+}}, [[short3]]
> +; CHECK: ? ? ?vsqrt.f32 ? ? ? {{s[0-9]+}}, [[short2]]
> +; CHECK: ? ? ?vsqrt.f32 ? ? ? {{s[0-9]+}}, [[short1]]
> +; CHECK: ? ? ?vsqrt.f32 ? ? ? {{s[0-9]+}}, [[short0]]
> +; CHECK-NEXT: vstmia ?{{.*}}
> +
> +L.entry:
> + ?%0 = load <4 x float>* @A, align 16
> + ?%1 = call <4 x float> @llvm.sqrt.v4f32(<4 x float> %0)
> + ?store <4 x float> %1, <4 x float>* %X, align 16
> + ?ret void
> +}
> +
> +declare <4 x float> @llvm.sqrt.v4f32(<4 x float>) nounwind readonly
> +
> +
> +define void @test_cos(<4 x float>* %X) nounwind {
> +
> +; CHECK: test_cos:
> +
> +; CHECK: ? ? ?movw ?[[reg0:r[0-9]+]], :lower16:A
> +; CHECK-NEXT: movt ?[[reg0]], :upper16:A
> +; CHECK: ? ? ?vldmia [[reg0]], {{.*}}
> +
> +; CHECK: ? ? ?{{[v]?mov}} ?r0, {{[r|s][0-9]+}}
> +; CHECK: ? ? ?bl ?cosf
> +
> +; CHECK: ? ? ?{{[v]?mov}} ?r0, {{[r|s][0-9]+}}
> +; CHECK: ? ? ?bl ?cosf
> +
> +; CHECK: ? ? ?{{[v]?mov}} ?r0, {{[r|s][0-9]+}}
> +; CHECK: ? ? ?bl ?cosf
> +
> +; CHECK: ? ? ?{{[v]?mov}} ?r0, {{[r|s][0-9]+}}
> +; CHECK: ? ? ?bl ?cosf
> +
> +; CHECK: ? ? ?vstmia ?{{.*}}
> +
> +L.entry:
> + ?%0 = load <4 x float>* @A, align 16
> + ?%1 = call <4 x float> @llvm.cos.v4f32(<4 x float> %0)
> + ?store <4 x float> %1, <4 x float>* %X, align 16
> + ?ret void
> +}
> +
> +declare <4 x float> @llvm.cos.v4f32(<4 x float>) nounwind readonly
> +
> +define void @test_exp(<4 x float>* %X) nounwind {
> +
> +; CHECK: test_exp:
> +
> +; CHECK: ? ? ?movw ?[[reg0:r[0-9]+]], :lower16:A
> +; CHECK-NEXT: movt ?[[reg0]], :upper16:A
> +; CHECK: ? ? ?vldmia [[reg0]], {{.*}}
> +
> +; CHECK: ? ? ?{{[v]?mov}} ?r0, {{[r|s][0-9]+}}
> +; CHECK: ? ? ?bl ?expf
> +
> +; CHECK: ? ? ?{{[v]?mov}} ?r0, {{[r|s][0-9]+}}
> +; CHECK: ? ? ?bl ?expf
> +
> +; CHECK: ? ? ?{{[v]?mov}} ?r0, {{[r|s][0-9]+}}
> +; CHECK: ? ? ?bl ?expf
> +
> +; CHECK: ? ? ?{{[v]?mov}} ?r0, {{[r|s][0-9]+}}
> +; CHECK: ? ? ?bl ?expf
> +
> +; CHECK: ? ? ?vstmia ?{{.*}}
> +
> +L.entry:
> + ?%0 = load <4 x float>* @A, align 16
> + ?%1 = call <4 x float> @llvm.exp.v4f32(<4 x float> %0)
> + ?store <4 x float> %1, <4 x float>* %X, align 16
> + ?ret void
> +}
> +
> +declare <4 x float> @llvm.exp.v4f32(<4 x float>) nounwind readonly
> +
> +define void @test_exp2(<4 x float>* %X) nounwind {
> +
> +; CHECK: test_exp2:
> +
> +; CHECK: ? ? ?movw ?[[reg0:r[0-9]+]], :lower16:A
> +; CHECK-NEXT: movt ?[[reg0]], :upper16:A
> +; CHECK: ? ? ?vldmia [[reg0]], {{.*}}
> +
> +; CHECK: ? ? ?{{[v]?mov}} ?r0, {{[r|s][0-9]+}}
> +; CHECK: ? ? ?bl ?exp2f
> +
> +; CHECK: ? ? ?{{[v]?mov}} ?r0, {{[r|s][0-9]+}}
> +; CHECK: ? ? ?bl ?exp2f
> +
> +; CHECK: ? ? ?{{[v]?mov}} ?r0, {{[r|s][0-9]+}}
> +; CHECK: ? ? ?bl ?exp2f
> +
> +; CHECK: ? ? ?{{[v]?mov}} ?r0, {{[r|s][0-9]+}}
> +; CHECK: ? ? ?bl ?exp2f
> +
> +; CHECK: ? ? ?vstmia ?{{.*}}
> +
> +L.entry:
> + ?%0 = load <4 x float>* @A, align 16
> + ?%1 = call <4 x float> @llvm.exp2.v4f32(<4 x float> %0)
> + ?store <4 x float> %1, <4 x float>* %X, align 16
> + ?ret void
> +}
> +
> +declare <4 x float> @llvm.exp2.v4f32(<4 x float>) nounwind readonly
> +
> +define void @test_log10(<4 x float>* %X) nounwind {
> +
> +; CHECK: test_log10:
> +
> +; CHECK: ? ? ?movw ?[[reg0:r[0-9]+]], :lower16:A
> +; CHECK-NEXT: movt ?[[reg0]], :upper16:A
> +; CHECK: ? ? ?vldmia [[reg0]], {{.*}}
> +
> +; CHECK: ? ? ?{{[v]?mov}} ?r0, {{[r|s][0-9]+}}
> +; CHECK: ? ? ?bl ?log10f
> +
> +; CHECK: ? ? ?{{[v]?mov}} ?r0, {{[r|s][0-9]+}}
> +; CHECK: ? ? ?bl ?log10f
> +
> +; CHECK: ? ? ?{{[v]?mov}} ?r0, {{[r|s][0-9]+}}
> +; CHECK: ? ? ?bl ?log10f
> +
> +; CHECK: ? ? ?{{[v]?mov}} ?r0, {{[r|s][0-9]+}}
> +; CHECK: ? ? ?bl ?log10f
> +
> +; CHECK: ? ? ?vstmia ?{{.*}}
> +
> +L.entry:
> + ?%0 = load <4 x float>* @A, align 16
> + ?%1 = call <4 x float> @llvm.log10.v4f32(<4 x float> %0)
> + ?store <4 x float> %1, <4 x float>* %X, align 16
> + ?ret void
> +}
> +
> +declare <4 x float> @llvm.log10.v4f32(<4 x float>) nounwind readonly
> +
> +define void @test_log(<4 x float>* %X) nounwind {
> +
> +; CHECK: test_log:
> +
> +; CHECK: ? ? ?movw ?[[reg0:r[0-9]+]], :lower16:A
> +; CHECK-NEXT: movt ?[[reg0]], :upper16:A
> +; CHECK: ? ? ?vldmia [[reg0]], {{.*}}
> +
> +; CHECK: ? ? ?{{[v]?mov}} ?r0, {{[r|s][0-9]+}}
> +; CHECK: ? ? ?bl ?logf
> +
> +; CHECK: ? ? ?{{[v]?mov}} ?r0, {{[r|s][0-9]+}}
> +; CHECK: ? ? ?bl ?logf
> +
> +; CHECK: ? ? ?{{[v]?mov}} ?r0, {{[r|s][0-9]+}}
> +; CHECK: ? ? ?bl ?logf
> +
> +; CHECK: ? ? ?{{[v]?mov}} ?r0, {{[r|s][0-9]+}}
> +; CHECK: ? ? ?bl ?logf
> +
> +; CHECK: ? ? ?vstmia ?{{.*}}
> +
> +L.entry:
> + ?%0 = load <4 x float>* @A, align 16
> + ?%1 = call <4 x float> @llvm.log.v4f32(<4 x float> %0)
> + ?store <4 x float> %1, <4 x float>* %X, align 16
> + ?ret void
> +}
> +
> +declare <4 x float> @llvm.log.v4f32(<4 x float>) nounwind readonly
> +
> +define void @test_log2(<4 x float>* %X) nounwind {
> +
> +; CHECK: test_log2:
> +
> +; CHECK: ? ? ?movw ?[[reg0:r[0-9]+]], :lower16:A
> +; CHECK-NEXT: movt ?[[reg0]], :upper16:A
> +; CHECK: ? ? ?vldmia [[reg0]], {{.*}}
> +
> +; CHECK: ? ? ?{{[v]?mov}} ?r0, {{[r|s][0-9]+}}
> +; CHECK: ? ? ?bl ?log2f
> +
> +; CHECK: ? ? ?{{[v]?mov}} ?r0, {{[r|s][0-9]+}}
> +; CHECK: ? ? ?bl ?log2f
> +
> +; CHECK: ? ? ?{{[v]?mov}} ?r0, {{[r|s][0-9]+}}
> +; CHECK: ? ? ?bl ?log2f
> +
> +; CHECK: ? ? ?{{[v]?mov}} ?r0, {{[r|s][0-9]+}}
> +; CHECK: ? ? ?bl ?log2f
> +
> +; CHECK: ? ? ?vstmia ?{{.*}}
> +
> +L.entry:
> + ?%0 = load <4 x float>* @A, align 16
> + ?%1 = call <4 x float> @llvm.log2.v4f32(<4 x float> %0)
> + ?store <4 x float> %1, <4 x float>* %X, align 16
> + ?ret void
> +}
> +
> +declare <4 x float> @llvm.log2.v4f32(<4 x float>) nounwind readonly
> +
> +
> +define void @test_pow(<4 x float>* %X) nounwind {
> +
> +; CHECK: test_pow:
> +
> +; CHECK: ? ? ?movw ?[[reg0:r[0-9]+]], :lower16:A
> +; CHECK-NEXT: movt ?[[reg0]], :upper16:A
> +; CHECK: ? ? ?vldmia [[reg0]], {{.*}}
> +
> +; CHECK: ? ? ?{{[v]?mov}} ?r0, {{[r|s][0-9]+}}
> +; CHECK: ? ? ?bl ?powf
> +
> +; CHECK: ? ? ?{{[v]?mov}} ?r0, {{[r|s][0-9]+}}
> +; CHECK: ? ? ?bl ?powf
> +
> +; CHECK: ? ? ?{{[v]?mov}} ?r0, {{[r|s][0-9]+}}
> +; CHECK: ? ? ?bl ?powf
> +
> +; CHECK: ? ? ?{{[v]?mov}} ?r0, {{[r|s][0-9]+}}
> +; CHECK: ? ? ?bl ?powf
> +
> +; CHECK: ? ? ?vstmia ?{{.*}}
> +
> +L.entry:
> +
> + ?%0 = load <4 x float>* @A, align 16
> + ?%1 = call <4 x float> @llvm.pow.v4f32(<4 x float> %0, <4 x float> )
> +
> + ?store <4 x float> %1, <4 x float>* %X, align 16
> +
> + ?ret void
> +}
> +
> +declare <4 x float> @llvm.pow.v4f32(<4 x float>, <4 x float>) nounwind readonly
> +
> +define void @test_powi(<4 x float>* %X) nounwind {
> +
> +; CHECK: test_powi:
> +
> +; CHECK: ? ? ? movw ?[[reg0:r[0-9]+]], :lower16:A
> +; CHECK-NEXT: ?movt ?[[reg0]], :upper16:A
> +; CHECK-NEXT: ?vldmia ?[[reg0]], {{.*}}
> +; CHECK: ? ? ? vmul.f32 {{.*}}
> +
> +; CHECK: ? ? ?vstmia ?{{.*}}
> +
> +L.entry:
> +
> + ?%0 = load <4 x float>* @A, align 16
> + ?%1 = call <4 x float> @llvm.powi.v4f32(<4 x float> %0, i32 2)
> +
> + ?store <4 x float> %1, <4 x float>* %X, align 16
> +
> + ?ret void
> +}
> +
> +declare <4 x float> @llvm.powi.v4f32(<4 x float>, i32) nounwind readonly
> +
> +define void @test_sin(<4 x float>* %X) nounwind {
> +
> +; CHECK: test_sin:
> +
> +; CHECK: ? ? ?movw ?[[reg0:r[0-9]+]], :lower16:A
> +; CHECK-NEXT: movt ?[[reg0]], :upper16:A
> +; CHECK: ? ? ?vldmia [[reg0]], {{.*}}
> +
> +; CHECK: ? ? ?{{[v]?mov}} ?r0, {{[r|s][0-9]+}}
> +; CHECK: ? ? ?bl ?sinf
> +
> +; CHECK: ? ? ?{{[v]?mov}} ?r0, {{[r|s][0-9]+}}
> +; CHECK: ? ? ?bl ?sinf
> +
> +; CHECK: ? ? ?{{[v]?mov}} ?r0, {{[r|s][0-9]+}}
> +; CHECK: ? ? ?bl ?sinf
> +
> +; CHECK: ? ? ?{{[v]?mov}} ?r0, {{[r|s][0-9]+}}
> +; CHECK: ? ? ?bl ?sinf
> +
> +; CHECK: ? ? ?vstmia ?{{.*}}
> +
> +L.entry:
> + ?%0 = load <4 x float>* @A, align 16
> + ?%1 = call <4 x float> @llvm.sin.v4f32(<4 x float> %0)
> + ?store <4 x float> %1, <4 x float>* %X, align 16
> + ?ret void
> +}
> +
> +declare <4 x float> @llvm.sin.v4f32(<4 x float>) nounwind readonly
> +
>
>
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits


From matthewbg at google.com  Thu Dec  8 11:47:37 2011
From: matthewbg at google.com (Matt Beaumont-Gay)
Date: Thu, 8 Dec 2011 09:47:37 -0800
Subject: [llvm-commits] [compiler-rt] r146131 - in
 /compiler-rt/trunk/SDKs/linux: ./ README.txt usr/ usr/include/
 usr/include/endian.h usr/include/limits.h usr/include/stdio.h
 usr/include/stdlib.h usr/include/string.h usr/include/sys/
 usr/include/sys/mman
Message-ID: 

On Wed, Dec 7, 2011 at 18:39, Daniel Dunbar  wrote:
> Author: ddunbar
> Date: Wed Dec ?7 20:39:23 2011
> New Revision: 146131
>
> URL: http://llvm.org/viewvc/llvm-project?rev=146131&view=rev
> Log:
> SDKs: Sketch an initial stub SDK for Linux, I believe this suffices for building
> the main compiler-rt and profile modules, at least on x86.
>
> Added:
> ? ?compiler-rt/trunk/SDKs/linux/
> ? ?compiler-rt/trunk/SDKs/linux/README.txt
> ? ?compiler-rt/trunk/SDKs/linux/usr/
> ? ?compiler-rt/trunk/SDKs/linux/usr/include/
> ? ?compiler-rt/trunk/SDKs/linux/usr/include/endian.h
> ? ?compiler-rt/trunk/SDKs/linux/usr/include/limits.h
> ? ?compiler-rt/trunk/SDKs/linux/usr/include/stdio.h
> ? ?compiler-rt/trunk/SDKs/linux/usr/include/stdlib.h
> ? ?compiler-rt/trunk/SDKs/linux/usr/include/string.h
> ? ?compiler-rt/trunk/SDKs/linux/usr/include/sys/
> ? ?compiler-rt/trunk/SDKs/linux/usr/include/sys/mman.h
> ? ?compiler-rt/trunk/SDKs/linux/usr/include/sys/stat.h
> ? ?compiler-rt/trunk/SDKs/linux/usr/include/sys/types.h
> ? ?compiler-rt/trunk/SDKs/linux/usr/include/unistd.h
>
> Added: compiler-rt/trunk/SDKs/linux/README.txt
> URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/SDKs/linux/README.txt?rev=146131&view=auto
> ==============================================================================
> --- compiler-rt/trunk/SDKs/linux/README.txt (added)
> +++ compiler-rt/trunk/SDKs/linux/README.txt Wed Dec ?7 20:39:23 2011
> @@ -0,0 +1,2 @@
> +This is a stub SDK for Linux. Currently, this has only been tested on i386 and
> +x86_64 using the Clang compiler.
>
> Added: compiler-rt/trunk/SDKs/linux/usr/include/endian.h
> URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/SDKs/linux/usr/include/endian.h?rev=146131&view=auto
> ==============================================================================
> --- compiler-rt/trunk/SDKs/linux/usr/include/endian.h (added)
> +++ compiler-rt/trunk/SDKs/linux/usr/include/endian.h Wed Dec ?7 20:39:23 2011
> @@ -0,0 +1,29 @@
> +/* ===-- endian.h - stub SDK header for compiler-rt -------------------------===
> + *
> + * ? ? ? ? ? ? ? ? ? ? The LLVM Compiler Infrastructure
> + *
> + * This file is dual licensed under the MIT and the University of Illinois Open
> + * Source Licenses. See LICENSE.TXT for details.
> + *
> + * ===-----------------------------------------------------------------------===
> + *
> + * This is a stub SDK header file. This file is not part of the interface of
> + * this library nor an official version of the appropriate SDK header. It is
> + * intended only to stub the features of this header required by compiler-rt.
> + *
> + * ===-----------------------------------------------------------------------===
> + */
> +
> +#ifndef __ENDIAN_H__
> +#define __ENDIAN_H__
> +
> +#define __LITTLE_ENDIAN 1234
> +#define __BIG_ENDIAN 4321
> +
> +#if defined(__LITTLE_ENDIAN__) || defined(__ORDER_LITTLE_ENDIAN__)
> +#define __BYTE_ORDER __LITTLE_ENDIAN
> +#else
> +#define __BYTE_ORDER __BIG_ENDIAN
> +#endif
> +
> +#endif /* __ENDIAN_H__ */
>
> Added: compiler-rt/trunk/SDKs/linux/usr/include/limits.h
> URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/SDKs/linux/usr/include/limits.h?rev=146131&view=auto
> ==============================================================================
> --- compiler-rt/trunk/SDKs/linux/usr/include/limits.h (added)
> +++ compiler-rt/trunk/SDKs/linux/usr/include/limits.h Wed Dec ?7 20:39:23 2011
> @@ -0,0 +1,23 @@
> +/* ===-- limits.h - stub SDK header for compiler-rt -------------------------===
> + *
> + * ? ? ? ? ? ? ? ? ? ? The LLVM Compiler Infrastructure
> + *
> + * This file is dual licensed under the MIT and the University of Illinois Open
> + * Source Licenses. See LICENSE.TXT for details.
> + *
> + * ===-----------------------------------------------------------------------===
> + *
> + * This is a stub SDK header file. This file is not part of the interface of
> + * this library nor an official version of the appropriate SDK header. It is
> + * intended only to stub the features of this header required by compiler-rt.
> + *
> + * ===-----------------------------------------------------------------------===
> + */
> +
> +#ifndef __LIMITS_H__
> +#define __LIMITS_H__
> +
> +/* This is only here as a landing pad for the include_next from the compiler's
> + ? built-in limits.h. */
> +
> +#endif /* __LIMITS_H__ */
>
> Added: compiler-rt/trunk/SDKs/linux/usr/include/stdio.h
> URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/SDKs/linux/usr/include/stdio.h?rev=146131&view=auto
> ==============================================================================
> --- compiler-rt/trunk/SDKs/linux/usr/include/stdio.h (added)
> +++ compiler-rt/trunk/SDKs/linux/usr/include/stdio.h Wed Dec ?7 20:39:23 2011
> @@ -0,0 +1,35 @@
> +/* ===-- stdio.h - stub SDK header for compiler-rt --------------------------===
> + *
> + * ? ? ? ? ? ? ? ? ? ? The LLVM Compiler Infrastructure
> + *
> + * This file is dual licensed under the MIT and the University of Illinois Open
> + * Source Licenses. See LICENSE.TXT for details.
> + *
> + * ===-----------------------------------------------------------------------===
> + *
> + * This is a stub SDK header file. This file is not part of the interface of
> + * this library nor an official version of the appropriate SDK header. It is
> + * intended only to stub the features of this header required by compiler-rt.
> + *
> + * ===-----------------------------------------------------------------------===
> + */
> +
> +#ifndef __STDIO_H__
> +#define __STDIO_H__
> +
> +typedef __SIZE_TYPE__ size_t;
> +
> +struct _IO_FILE;
> +typedef struct _IO_FILE FILE;
> +
> +extern struct _IO_FILE *stdin;
> +extern struct _IO_FILE *stdout;
> +extern struct _IO_FILE *stderr;
> +
> +extern int fclose(FILE *);
> +extern int fflush(FILE *);
> +extern FILE *fopen(const char * restrict, const char * restrict);
> +extern int fprintf(FILE * restrict, const char * restrict, ...);
> +extern size_t fwrite(const void * restrict, size_t, size_t, FILE * restrict);
> +
> +#endif /* __STDIO_H__ */
>
> Added: compiler-rt/trunk/SDKs/linux/usr/include/stdlib.h
> URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/SDKs/linux/usr/include/stdlib.h?rev=146131&view=auto
> ==============================================================================
> --- compiler-rt/trunk/SDKs/linux/usr/include/stdlib.h (added)
> +++ compiler-rt/trunk/SDKs/linux/usr/include/stdlib.h Wed Dec ?7 20:39:23 2011
> @@ -0,0 +1,32 @@
> +/* ===-- stdlib.h - stub SDK header for compiler-rt -------------------------===
> + *
> + * ? ? ? ? ? ? ? ? ? ? The LLVM Compiler Infrastructure
> + *
> + * This file is dual licensed under the MIT and the University of Illinois Open
> + * Source Licenses. See LICENSE.TXT for details.
> + *
> + * ===-----------------------------------------------------------------------===
> + *
> + * This is a stub SDK header file. This file is not part of the interface of
> + * this library nor an official version of the appropriate SDK header. It is
> + * intended only to stub the features of this header required by compiler-rt.
> + *
> + * ===-----------------------------------------------------------------------===
> + */
> +
> +#ifndef __STDLIB_H__
> +#define __STDLIB_H__
> +
> +#define NULL ((void *)0)
> +
> +typedef __SIZE_TYPE__ size_t;
> +
> +void abort(void) __attribute__((__nothrow__)) __attribute__((__noreturn__));
> +void free(void *) __attribute__((__nothrow__));
> +char *getenv(const char *) __attribute__((__nothrow__))
> + ?__attribute__((__nonnull__(1)));
> + ?__attribute__((__warn_unused_result__));
> +void *malloc(size_t) __attribute__((__nothrow__)) __attribute((__malloc__))
> + ? ? __attribute__((__warn_unused_result__));
> +
> +#endif /* __STDLIB_H__ */
>
> Added: compiler-rt/trunk/SDKs/linux/usr/include/string.h
> URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/SDKs/linux/usr/include/string.h?rev=146131&view=auto
> ==============================================================================
> --- compiler-rt/trunk/SDKs/linux/usr/include/string.h (added)
> +++ compiler-rt/trunk/SDKs/linux/usr/include/string.h Wed Dec ?7 20:39:23 2011
> @@ -0,0 +1,28 @@
> +/* ===-- string.h - stub SDK header for compiler-rt -------------------------===
> + *
> + * ? ? ? ? ? ? ? ? ? ? The LLVM Compiler Infrastructure
> + *
> + * This file is dual licensed under the MIT and the University of Illinois Open
> + * Source Licenses. See LICENSE.TXT for details.
> + *
> + * ===-----------------------------------------------------------------------===
> + *
> + * This is a stub SDK header file. This file is not part of the interface of
> + * this library nor an official version of the appropriate SDK header. It is
> + * intended only to stub the features of this header required by compiler-rt.
> + *
> + * ===-----------------------------------------------------------------------===
> + */
> +
> +#ifndef __STRING_H__
> +#define __STRING_H__
> +
> +typedef __SIZE_TYPE__ size_t;
> +
> +char *strcat(char *, const char *);
> +char *strcpy(char *, const char *);
> +char *strdup(const char *);
> +size_t strlen(const char *);
> +char *strncpy(char *, const char *, size_t);
> +
> +#endif /* __STRING_H__ */
>
> Added: compiler-rt/trunk/SDKs/linux/usr/include/sys/mman.h
> URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/SDKs/linux/usr/include/sys/mman.h?rev=146131&view=auto
> ==============================================================================
> --- compiler-rt/trunk/SDKs/linux/usr/include/sys/mman.h (added)
> +++ compiler-rt/trunk/SDKs/linux/usr/include/sys/mman.h Wed Dec ?7 20:39:23 2011
> @@ -0,0 +1,29 @@
> +/* ===-- limits.h - stub SDK header for compiler-rt -------------------------===
> + *
> + * ? ? ? ? ? ? ? ? ? ? The LLVM Compiler Infrastructure
> + *
> + * This file is dual licensed under the MIT and the University of Illinois Open
> + * Source Licenses. See LICENSE.TXT for details.
> + *
> + * ===-----------------------------------------------------------------------===
> + *
> + * This is a stub SDK header file. This file is not part of the interface of
> + * this library nor an official version of the appropriate SDK header. It is
> + * intended only to stub the features of this header required by compiler-rt.
> + *
> + * ===-----------------------------------------------------------------------===
> + */
> +
> +#ifndef __SYS_MMAN_H__
> +#define __SYS_MMAN_H__
> +
> +typedef __SIZE_TYPE__ size_t;
> +
> +#define PROT_READ 0x1
> +#define PROT_WRITE 0x1

Err, should be 0x2 I think?

> +#define PROT_EXEC 0x4
> +
> +extern int mprotect (void *__addr, size_t __len, int __prot)
> + ?__attribute__((__nothrow__));
> +
> +#endif /* __SYS_MMAN_H__ */
>
> Added: compiler-rt/trunk/SDKs/linux/usr/include/sys/stat.h
> URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/SDKs/linux/usr/include/sys/stat.h?rev=146131&view=auto
> ==============================================================================
> --- compiler-rt/trunk/SDKs/linux/usr/include/sys/stat.h (added)
> +++ compiler-rt/trunk/SDKs/linux/usr/include/sys/stat.h Wed Dec ?7 20:39:23 2011
> @@ -0,0 +1,24 @@
> +/* ===-- stat.h - stub SDK header for compiler-rt ---------------------------===
> + *
> + * ? ? ? ? ? ? ? ? ? ? The LLVM Compiler Infrastructure
> + *
> + * This file is dual licensed under the MIT and the University of Illinois Open
> + * Source Licenses. See LICENSE.TXT for details.
> + *
> + * ===-----------------------------------------------------------------------===
> + *
> + * This is a stub SDK header file. This file is not part of the interface of
> + * this library nor an official version of the appropriate SDK header. It is
> + * intended only to stub the features of this header required by compiler-rt.
> + *
> + * ===-----------------------------------------------------------------------===
> + */
> +
> +#ifndef __SYS_STAT_H__
> +#define __SYS_STAT_H__
> +
> +typedef unsigned int mode_t;
> +
> +int mkdir(const char *, mode_t);
> +
> +#endif /* __SYS_STAT_H__ */
>
> Added: compiler-rt/trunk/SDKs/linux/usr/include/sys/types.h
> URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/SDKs/linux/usr/include/sys/types.h?rev=146131&view=auto
> ==============================================================================
> --- compiler-rt/trunk/SDKs/linux/usr/include/sys/types.h (added)
> +++ compiler-rt/trunk/SDKs/linux/usr/include/sys/types.h Wed Dec ?7 20:39:23 2011
> @@ -0,0 +1,20 @@
> +/* ===-- stat.h - stub SDK header for compiler-rt ---------------------------===
> + *
> + * ? ? ? ? ? ? ? ? ? ? The LLVM Compiler Infrastructure
> + *
> + * This file is dual licensed under the MIT and the University of Illinois Open
> + * Source Licenses. See LICENSE.TXT for details.
> + *
> + * ===-----------------------------------------------------------------------===
> + *
> + * This is a stub SDK header file. This file is not part of the interface of
> + * this library nor an official version of the appropriate SDK header. It is
> + * intended only to stub the features of this header required by compiler-rt.
> + *
> + * ===-----------------------------------------------------------------------===
> + */
> +
> +#ifndef __SYS_TYPES_H__
> +#define __SYS_TYPES_H__
> +
> +#endif /* __SYS_TYPES_H__ */
>
> Added: compiler-rt/trunk/SDKs/linux/usr/include/unistd.h
> URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/SDKs/linux/usr/include/unistd.h?rev=146131&view=auto
> ==============================================================================
> --- compiler-rt/trunk/SDKs/linux/usr/include/unistd.h (added)
> +++ compiler-rt/trunk/SDKs/linux/usr/include/unistd.h Wed Dec ?7 20:39:23 2011
> @@ -0,0 +1,26 @@
> +/* ===-- unistd.h - stub SDK header for compiler-rt -------------------------===
> + *
> + * ? ? ? ? ? ? ? ? ? ? The LLVM Compiler Infrastructure
> + *
> + * This file is dual licensed under the MIT and the University of Illinois Open
> + * Source Licenses. See LICENSE.TXT for details.
> + *
> + * ===-----------------------------------------------------------------------===
> + *
> + * This is a stub SDK header file. This file is not part of the interface of
> + * this library nor an official version of the appropriate SDK header. It is
> + * intended only to stub the features of this header required by compiler-rt.
> + *
> + * ===-----------------------------------------------------------------------===
> + */
> +
> +#ifndef __UNISTD_H__
> +#define __UNISTD_H__
> +
> +enum {
> + ?_SC_PAGESIZE = 30
> +};
> +
> +extern long int sysconf (int __name) __attribute__ ((__nothrow__));
> +
> +#endif /* __UNISTD_H__ */
>
>
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits


From daniel.malea at intel.com  Thu Dec  8 11:51:18 2011
From: daniel.malea at intel.com (Malea, Daniel)
Date: Thu, 8 Dec 2011 10:51:18 -0700
Subject: [llvm-commits] [PATCH] Add support for JIT profiling tool
 (Intel Parallel Amplifier XE 2011)
Message-ID: <2C2ECF4B05BCF3489866AB805260FEC50630AE07CD@rrsmsx509.amr.corp.intel.com>

Ping

From: Malea, Daniel
Sent: Wednesday, December 07, 2011 12:59 PM
To: 'llvm-commits at cs.uiuc.edu'
Subject: Add support for JIT profiling tool (Intel Parallel Amplifier XE 2011)

Hi all,

Please find the attached patches ready for review which add JIT profiling support for Intel Parallel Amplifier XE 2011 (through the JITEventListener interface) and also fix oprofile support in the CMake build system. The meat (implementation and tests) is in the first patch, and the subsequent patches are the build system changes.

Add Intel JIT Events API compatible JITEventListener, and allow OProfileJITEventListener to load libopagent.so at runtime

-        Removed link-time requirement on libopagent when building with OProfile support

-        Added Intel JIT API and OProfile support to cmake builds (Boolean options LLVM_USE_OPROFILE and LLVM_USE_INTEL_JITEVENTS)

-        Added IntelJITEventListener to connect to Intel JIT API (support for profiling with Parallel Amplifier XE 2011)

-        Added unit tests for both IntelJIT and OProfile JITEventListener implementations which can still be run in the absence the respective 3rd party libraries

Thanks
-------------- next part --------------
An HTML attachment was scrubbed...
URL: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20111208/ecd5495d/attachment.html 

From daniel.malea at intel.com  Thu Dec  8 12:09:53 2011
From: daniel.malea at intel.com (Malea, Daniel)
Date: Thu, 8 Dec 2011 11:09:53 -0700
Subject: [llvm-commits] [PATCH] Add basic ELF Dyld loader (on behalf of
	Andy Kaylor)
Message-ID: <2C2ECF4B05BCF3489866AB805260FEC50630AE0806@rrsmsx509.amr.corp.intel.com>

Hi all,

There was a bug (related to symbol address computation) in the patch I posted here earlier. If anyone's interested in a very minimal runtime ELF loader (with a workaround for the aforementioned bug) please take a look at the attached patch.

Thanks,
Daniel

From: Malea, Daniel
Sent: Wednesday, December 07, 2011 2:13 PM
To: llvm-commits at cs.uiuc.edu
Subject: Add basic ELF Dyld loader (on behalf of Andy Kaylor)

Hi all,

Please find the attached patch for review. It is the first step toward enabling lli -use-mcjit to work with ELF objects.

Basic ELF loader in MCJIT (on behalf of Andy Kaylor):

-        Supports loading ELF object files emitted by MC

-        Adds minimal x86 relocation support (function calls)

Thanks,
Dan
-------------- next part --------------
An HTML attachment was scrubbed...
URL: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20111208/158457c0/attachment.html 
-------------- next part --------------
A non-text attachment was scrubbed...
Name: 0001-basic-runtimedyld-elf-loader_v2.patch
Type: application/octet-stream
Size: 15558 bytes
Desc: 0001-basic-runtimedyld-elf-loader_v2.patch
Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20111208/158457c0/attachment.obj 

From kcc at google.com  Thu Dec  8 12:30:43 2011
From: kcc at google.com (Kostya Serebryany)
Date: Thu, 08 Dec 2011 18:30:43 -0000
Subject: [llvm-commits] [compiler-rt] r146161 - in /compiler-rt/trunk:
 lib/asan/asan_internal.h lib/asan/asan_rtl.cc lib/asan/asan_stack.cc
 make/platform/clang_darwin.mk
Message-ID: <20111208183043.4D1B92A6C12C@llvm.org>

Author: kcc
Date: Thu Dec  8 12:30:42 2011
New Revision: 146161

URL: http://llvm.org/viewvc/llvm-project?rev=146161&view=rev
Log:
[asan] move build-time config options from makefile to source (otherwise we need config options in all makefiles) 

Modified:
    compiler-rt/trunk/lib/asan/asan_internal.h
    compiler-rt/trunk/lib/asan/asan_rtl.cc
    compiler-rt/trunk/lib/asan/asan_stack.cc
    compiler-rt/trunk/make/platform/clang_darwin.mk

Modified: compiler-rt/trunk/lib/asan/asan_internal.h
URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/lib/asan/asan_internal.h?rev=146161&r1=146160&r2=146161&view=diff
==============================================================================
--- compiler-rt/trunk/lib/asan/asan_internal.h (original)
+++ compiler-rt/trunk/lib/asan/asan_internal.h Thu Dec  8 12:30:42 2011
@@ -41,6 +41,29 @@
         " instrumented by AddressSanitizer"
 #endif
 
+// Build-time configuration options.
+
+// If set, sysinfo/sysinfo.h will be used to iterate over /proc/maps.
+#ifndef ASAN_USE_SYSINFO
+# define ASAN_USE_SYSINFO 1
+#endif
+
+// If set, asan will install its own SEGV signal handler.
+#ifndef ASAN_NEEDS_SEGV
+# define ASAN_NEEDS_SEGV 1
+#endif
+
+// If set, asan will intercept C++ exception api call(s).
+#ifndef ASAN_HAS_EXCEPTIONS
+# define ASAN_HAS_EXCEPTIONS 1
+#endif
+
+// If set, asan uses the values of SHADOW_SCALE and SHADOW_OFFSET
+// provided by the instrumented objects. Otherwise constants are used.
+#ifndef ASAN_FLEXIBLE_MAPPING_AND_OFFSET
+# define ASAN_FLEXIBLE_MAPPING_AND_OFFSET 0
+#endif
+
 // All internal functions in asan reside inside the __asan namespace
 // to avoid namespace collisions with the user programs.
 // Seperate namespace also makes it simpler to distinguish the asan run-time

Modified: compiler-rt/trunk/lib/asan/asan_rtl.cc
URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/lib/asan/asan_rtl.cc?rev=146161&r1=146160&r2=146161&view=diff
==============================================================================
--- compiler-rt/trunk/lib/asan/asan_rtl.cc (original)
+++ compiler-rt/trunk/lib/asan/asan_rtl.cc Thu Dec  8 12:30:42 2011
@@ -45,10 +45,6 @@
 #include 
 // must not include  on Linux
 
-#ifndef ASAN_NEEDS_SEGV
-# define ASAN_NEEDS_SEGV 1
-#endif
-
 namespace __asan {
 
 // -------------------------- Flags ------------------------- {{{1
@@ -503,7 +499,7 @@
 
 extern "C" void __cxa_throw(void *a, void *b, void *c);
 
-#if ASAN_HAS_EXCEPTIONS
+#if ASAN_HAS_EXCEPTIONS == 1
 extern "C" void WRAP(__cxa_throw)(void *a, void *b, void *c) {
   CHECK(&real___cxa_throw);
   UnpoisonStackFromHereToTop();
@@ -657,8 +653,7 @@
   FLAG_poison_shadow = IntFlagValue(options, "poison_shadow=", 1);
   FLAG_report_globals = IntFlagValue(options, "report_globals=", 1);
   FLAG_lazy_shadow = IntFlagValue(options, "lazy_shadow=", 0);
-  FLAG_handle_segv = IntFlagValue(options, "handle_segv=",
-                                         ASAN_NEEDS_SEGV);
+  FLAG_handle_segv = IntFlagValue(options, "handle_segv=", ASAN_NEEDS_SEGV);
   FLAG_handle_sigill = IntFlagValue(options, "handle_sigill=", 0);
   FLAG_symbolize = IntFlagValue(options, "symbolize=", 1);
   FLAG_demangle = IntFlagValue(options, "demangle=", 1);

Modified: compiler-rt/trunk/lib/asan/asan_stack.cc
URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/lib/asan/asan_stack.cc?rev=146161&r1=146160&r2=146161&view=diff
==============================================================================
--- compiler-rt/trunk/lib/asan/asan_stack.cc (original)
+++ compiler-rt/trunk/lib/asan/asan_stack.cc Thu Dec  8 12:30:42 2011
@@ -19,7 +19,7 @@
 
 #include 
 
-#ifdef ASAN_USE_SYSINFO
+#if ASAN_USE_SYSINFO == 1
 #include "sysinfo/sysinfo.h"
 #endif
 
@@ -31,7 +31,7 @@
 namespace __asan {
 
 // ----------------------- ProcSelfMaps ----------------------------- {{{1
-#ifdef ASAN_USE_SYSINFO
+#if ASAN_USE_SYSINFO == 1
 class ProcSelfMaps {
  public:
   void Init() {

Modified: compiler-rt/trunk/make/platform/clang_darwin.mk
URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/make/platform/clang_darwin.mk?rev=146161&r1=146160&r2=146161&view=diff
==============================================================================
--- compiler-rt/trunk/make/platform/clang_darwin.mk (original)
+++ compiler-rt/trunk/make/platform/clang_darwin.mk Thu Dec  8 12:30:42 2011
@@ -104,11 +104,6 @@
 CFLAGS.10.4		:= $(CFLAGS) $(OSX_DEPLOYMENT_ARGS)
 # FIXME: We can't build ASAN with our stub SDK yet.
 CFLAGS.asan_osx         := $(CFLAGS) -mmacosx-version-min=10.5
-CFLAGS.asan_osx         += \
-		-DASAN_USE_SYSINFO=1 \
-		-DASAN_NEEDS_SEGV=1 \
-		-DASAN_HAS_EXCEPTIONS=1 \
-		-DASAN_FLEXIBLE_MAPPING_AND_OFFSET=0
 
 CFLAGS.ios.i386		:= $(CFLAGS) $(IOSSIM_DEPLOYMENT_ARGS)
 CFLAGS.ios.x86_64	:= $(CFLAGS) $(IOSSIM_DEPLOYMENT_ARGS)



From kcc at google.com  Thu Dec  8 12:46:33 2011
From: kcc at google.com (Kostya Serebryany)
Date: Thu, 08 Dec 2011 18:46:33 -0000
Subject: [llvm-commits] [compiler-rt] r146162 -
	/compiler-rt/trunk/lib/asan/Makefile.old
Message-ID: <20111208184633.4BA212A6C12C@llvm.org>

Author: kcc
Date: Thu Dec  8 12:46:33 2011
New Revision: 146162

URL: http://llvm.org/viewvc/llvm-project?rev=146162&view=rev
Log:
[asan] update the soon-to-be-depricated asan makefile to use the new path for asan-rt (affects only linux)

Modified:
    compiler-rt/trunk/lib/asan/Makefile.old

Modified: compiler-rt/trunk/lib/asan/Makefile.old
URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/lib/asan/Makefile.old?rev=146162&r1=146161&r2=146162&view=diff
==============================================================================
--- compiler-rt/trunk/lib/asan/Makefile.old (original)
+++ compiler-rt/trunk/lib/asan/Makefile.old Thu Dec  8 12:46:33 2011
@@ -118,8 +118,11 @@
   PIE=-fPIE -pie
 endif
 
-LIBASAN_INST_DIR=$(CLANG_BUILD)/lib/clang/$(OS)/$(ARCH)
-LIBASAN_A=$(LIBASAN_INST_DIR)/libclang_rt.asan.a
+# This will build libasan on linux for both x86_64 and i386 in the
+# desired location. The Mac library is already build by the clang's make.
+# $(CLANG_BUILD)/lib/clang/3.1/lib/$(OS)/libclang_rt.asan-$(ARCH).a
+LIBASAN_INST_DIR=$(CLANG_BUILD)/lib/clang/3.1/lib/$(OS)
+LIBASAN_A=$(LIBASAN_INST_DIR)/libclang_rt.asan-$(ARCH).a
 
 BLACKLIST=
 ifeq ($(ASAN_HAS_BLACKLIST), 1)



From kcc at google.com  Thu Dec  8 13:02:38 2011
From: kcc at google.com (Kostya Serebryany)
Date: Thu, 8 Dec 2011 11:02:38 -0800
Subject: [llvm-commits] [PATCH] ASan/Android: fall back to the system
 allocator for unexpected deallocations
In-Reply-To: 
References: 
Message-ID: 

Having such patch, even under ifdef ANDROID, will be very sad.
It makes free() much slower (linear time + lock, instead of constant time
w/o lock).
We need to figure out some other way (e.g. try to run __asan_init() even
earlier).

--kcc


On Thu, Dec 8, 2011 at 6:38 AM, Evgeniy Stepanov
wrote:

> On Android, allocations from static constructors of uninstrumented
> libraries occur before we have a chance to replace the allocator. This
> patch helps avoid crashing on the matching deallocations.
>
-------------- next part --------------
An HTML attachment was scrubbed...
URL: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20111208/df2af43a/attachment.html 

From evan.cheng at apple.com  Thu Dec  8 13:00:43 2011
From: evan.cheng at apple.com (Evan Cheng)
Date: Thu, 08 Dec 2011 19:00:43 -0000
Subject: [llvm-commits] [llvm] r146163 - in /llvm/trunk/lib/Target/X86:
 X86InstrFormats.td X86InstrInfo.td X86InstrSSE.td X86Subtarget.h
Message-ID: <20111208190043.5926B2A6C12C@llvm.org>

Author: evancheng
Date: Thu Dec  8 13:00:42 2011
New Revision: 146163

URL: http://llvm.org/viewvc/llvm-project?rev=146163&view=rev
Log:
Many of the SSE patterns should not be selected when AVX is available. This led to the following code in X86Subtarget.cpp

  if (HasAVX)
    X86SSELevel = NoMMXSSE;

This is so patterns that are predicated on hasSSE3, etc. would not be selected when avx is available. Instead, the AVX variant is selected.
However, this breaks instructions which do not have AVX variants.

The right way to fix this is for the SSE but not-AVX patterns to predicate on something like hasSSE3() && !hasAVX().
Then we can take out the hack in X86Subtarget.cpp. Patterns which do not have AVX variants do not need to change.

However, we need to audit all the patterns before we make the change. This patch is workaround that fixes one specific case,
the prefetch instructions. rdar://10538297

Modified:
    llvm/trunk/lib/Target/X86/X86InstrFormats.td
    llvm/trunk/lib/Target/X86/X86InstrInfo.td
    llvm/trunk/lib/Target/X86/X86InstrSSE.td
    llvm/trunk/lib/Target/X86/X86Subtarget.h

Modified: llvm/trunk/lib/Target/X86/X86InstrFormats.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrFormats.td?rev=146163&r1=146162&r2=146163&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrFormats.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrFormats.td Thu Dec  8 13:00:42 2011
@@ -334,6 +334,10 @@
            list pattern>
       : I, TB,
         Requires<[HasAVX]>;
+class VoPSI o, Format F, dag outs, dag ins, string asm,
+            list pattern>
+      : I, TB,
+        Requires<[HasSSE1orAVX]>;
 
 // SSE2 Instruction Templates:
 // 

Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.td?rev=146163&r1=146162&r2=146163&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrInfo.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrInfo.td Thu Dec  8 13:00:42 2011
@@ -476,6 +476,8 @@
 def HasXMM       : Predicate<"Subtarget->hasXMM()">;
 def HasXMMInt    : Predicate<"Subtarget->hasXMMInt()">;
 
+def HasSSE1orAVX : Predicate<"Subtarget->hasSSE1orAVX()">;
+
 def HasPOPCNT    : Predicate<"Subtarget->hasPOPCNT()">;
 def HasAES       : Predicate<"Subtarget->hasAES()">;
 def HasCLMUL     : Predicate<"Subtarget->hasCLMUL()">;

Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrSSE.td?rev=146163&r1=146162&r2=146163&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrSSE.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrSSE.td Thu Dec  8 13:00:42 2011
@@ -3183,13 +3183,13 @@
 //===----------------------------------------------------------------------===//
 
 // Prefetch intrinsic.
-def PREFETCHT0   : PSI<0x18, MRM1m, (outs), (ins i8mem:$src),
+def PREFETCHT0   : VoPSI<0x18, MRM1m, (outs), (ins i8mem:$src),
     "prefetcht0\t$src", [(prefetch addr:$src, imm, (i32 3), (i32 1))]>;
-def PREFETCHT1   : PSI<0x18, MRM2m, (outs), (ins i8mem:$src),
+def PREFETCHT1   : VoPSI<0x18, MRM2m, (outs), (ins i8mem:$src),
     "prefetcht1\t$src", [(prefetch addr:$src, imm, (i32 2), (i32 1))]>;
-def PREFETCHT2   : PSI<0x18, MRM3m, (outs), (ins i8mem:$src),
+def PREFETCHT2   : VoPSI<0x18, MRM3m, (outs), (ins i8mem:$src),
     "prefetcht2\t$src", [(prefetch addr:$src, imm, (i32 1), (i32 1))]>;
-def PREFETCHNTA  : PSI<0x18, MRM0m, (outs), (ins i8mem:$src),
+def PREFETCHNTA  : VoPSI<0x18, MRM0m, (outs), (ins i8mem:$src),
     "prefetchnta\t$src", [(prefetch addr:$src, imm, (i32 0), (i32 1))]>;
 
 // Flush cache

Modified: llvm/trunk/lib/Target/X86/X86Subtarget.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86Subtarget.h?rev=146163&r1=146162&r2=146163&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86Subtarget.h (original)
+++ llvm/trunk/lib/Target/X86/X86Subtarget.h Thu Dec  8 13:00:42 2011
@@ -193,6 +193,7 @@
   bool hasAVX2() const { return HasAVX2; }
   bool hasXMM() const { return hasSSE1() || hasAVX(); }
   bool hasXMMInt() const { return hasSSE2() || hasAVX(); }
+  bool hasSSE1orAVX() const { return hasSSE1() || hasAVX(); }
   bool hasSSE3orAVX() const { return hasSSE3() || hasAVX(); }
   bool hasSSSE3orAVX() const { return hasSSSE3() || hasAVX(); }
   bool hasSSE41orAVX() const { return hasSSE41() || hasAVX(); }



From kcc at google.com  Thu Dec  8 13:14:07 2011
From: kcc at google.com (Kostya Serebryany)
Date: Thu, 08 Dec 2011 19:14:07 -0000
Subject: [llvm-commits] [compiler-rt] r146166 - in
 /compiler-rt/trunk/lib/asan/mach_override: README.txt mach_override.c
Message-ID: <20111208191407.96AEA2A6C12C@llvm.org>

Author: kcc
Date: Thu Dec  8 13:14:07 2011
New Revision: 146166

URL: http://llvm.org/viewvc/llvm-project?rev=146166&view=rev
Log:
[asan] fresh version of mach_override; added mach_override/README.txt. Patch by glider at google.com

Added:
    compiler-rt/trunk/lib/asan/mach_override/README.txt
Modified:
    compiler-rt/trunk/lib/asan/mach_override/mach_override.c

Added: compiler-rt/trunk/lib/asan/mach_override/README.txt
URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/lib/asan/mach_override/README.txt?rev=146166&view=auto
==============================================================================
--- compiler-rt/trunk/lib/asan/mach_override/README.txt (added)
+++ compiler-rt/trunk/lib/asan/mach_override/README.txt Thu Dec  8 13:14:07 2011
@@ -0,0 +1,7 @@
+-- mach_override.c is taken from upstream version at
+ https://github.com/rentzsch/mach_star/tree/f8e0c424b5be5cb641ded67c265e616157ae4bcf
+-- Added debugging code under DEBUG_DISASM.
+-- The files are guarded with #ifdef __APPLE__
+-- some opcodes are added in order to parse the library functions on Lion
+-- fixupInstructions() is extended to relocate relative calls, not only jumps
+

Modified: compiler-rt/trunk/lib/asan/mach_override/mach_override.c
URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/lib/asan/mach_override/mach_override.c?rev=146166&r1=146165&r2=146166&view=diff
==============================================================================
--- compiler-rt/trunk/lib/asan/mach_override/mach_override.c (original)
+++ compiler-rt/trunk/lib/asan/mach_override/mach_override.c Thu Dec  8 13:14:07 2011
@@ -4,7 +4,6 @@
 		Some rights reserved: 
 
 	***************************************************************************/
-
 #ifdef __APPLE__
 
 #include "mach_override.h"
@@ -139,7 +138,17 @@
 	unsigned char	*code, 
 	uint64_t		*newInstruction,
 	int				*howManyEaten, 
-	char			*originalInstructions );
+	char			*originalInstructions,
+	int				*originalInstructionCount, 
+	uint8_t			*originalInstructionSizes );
+
+	static void
+fixupInstructions(
+    void		*originalFunction,
+    void		*escapeIsland,
+    void		*instructionsToFix,
+	int			instructionCount,
+	uint8_t		*instructionSizes );
 #endif
 
 /*******************************************************************************
@@ -150,12 +159,12 @@
 #pragma mark	-
 #pragma mark	(Interface)
 
-#if defined(__x86_64__)
+#if defined(__i386__) || defined(__x86_64__)
 mach_error_t makeIslandExecutable(void *address) {
 	mach_error_t err = err_none;
     vm_size_t pageSize;
     host_page_size( mach_host_self(), &pageSize );
-    uint64_t page = (uint64_t)address & ~(uint64_t)(pageSize-1);
+    uintptr_t page = (uintptr_t)address & ~(uintptr_t)(pageSize-1);
     int e = err_none;
     e |= mprotect((void *)page, pageSize, PROT_EXEC | PROT_READ | PROT_WRITE);
     e |= msync((void *)page, pageSize, MS_INVALIDATE );
@@ -174,8 +183,22 @@
 {
 	assert( originalFunctionAddress );
 	assert( overrideFunctionAddress );
-
-	long	*originalFunctionPtr = (long*) originalFunctionAddress;
+	
+	// this addresses overriding such functions as AudioOutputUnitStart()
+	// test with modified DefaultOutputUnit project
+#if defined(__x86_64__)
+    for(;;){
+        if(*(uint16_t*)originalFunctionAddress==0x25FF)    // jmp qword near [rip+0x????????]
+            originalFunctionAddress=*(void**)((char*)originalFunctionAddress+6+*(int32_t *)((uint16_t*)originalFunctionAddress+1));
+        else break;
+    }
+#elif defined(__i386__)
+    for(;;){
+        if(*(uint16_t*)originalFunctionAddress==0x25FF)    // jmp *0x????????
+            originalFunctionAddress=**(void***)((uint16_t*)originalFunctionAddress+1);
+        else break;
+    }
+#endif
 #ifdef DEBUG_DISASM
   {
     fprintf(stderr, "Replacing function at %p\n", originalFunctionAddress);
@@ -186,7 +209,7 @@
        fprintf(stderr, "%x ", (unsigned int) orig[i]);
     }
     fprintf(stderr, "\n");
-    fprintf(stderr,
+    fprintf(stderr, 
             "To disassemble, save the following function as disas.c"
             " and run:\n  gcc -c disas.c && gobjdump -d disas.o\n"
             "The first 16 bytes of the original function will start"
@@ -204,6 +227,7 @@
   }
 #endif
 
+	long	*originalFunctionPtr = (long*) originalFunctionAddress;
 	mach_error_t	err = err_none;
 	
 #if defined(__ppc__) || defined(__POWERPC__)
@@ -216,11 +240,15 @@
 		err = err_cannot_override;
 #elif defined(__i386__) || defined(__x86_64__)
 	int eatenCount = 0;
+	int originalInstructionCount = 0;
 	char originalInstructions[kOriginalInstructionsSize];
+	uint8_t originalInstructionSizes[kOriginalInstructionsSize];
 	uint64_t jumpRelativeInstruction = 0; // JMP
 
 	Boolean overridePossible = eatKnownInstructions ((unsigned char *)originalFunctionPtr, 
-										&jumpRelativeInstruction, &eatenCount, originalInstructions);
+										&jumpRelativeInstruction, &eatenCount, 
+										originalInstructions, &originalInstructionCount, 
+										originalInstructionSizes );
 #ifdef DEBUG_DISASM
   if (!overridePossible) fprintf(stderr, "overridePossible = false @%d\n", __LINE__);
 #endif
@@ -231,26 +259,26 @@
 		overridePossible = false;
 	}
 	if (!overridePossible) err = err_cannot_override;
-	if (err) printf("err = %x %d\n", err, __LINE__);
+	if (err) fprintf(stderr, "err = %x %s:%d\n", err, __FILE__, __LINE__);
 #endif
 	
 	//	Make the original function implementation writable.
 	if( !err ) {
 		err = vm_protect( mach_task_self(),
-				(vm_address_t) originalFunctionPtr,
-				sizeof(long), false, (VM_PROT_ALL | VM_PROT_COPY) );
+				(vm_address_t) originalFunctionPtr, 8, false,
+				(VM_PROT_ALL | VM_PROT_COPY) );
 		if( err )
 			err = vm_protect( mach_task_self(),
-					(vm_address_t) originalFunctionPtr, sizeof(long), false,
+					(vm_address_t) originalFunctionPtr, 8, false,
 					(VM_PROT_DEFAULT | VM_PROT_COPY) );
 	}
-	if (err) printf("err = %x %d\n", err, __LINE__);
+	if (err) fprintf(stderr, "err = %x %s:%d\n", err, __FILE__, __LINE__);
 	
 	//	Allocate and target the escape island to the overriding function.
 	BranchIsland	*escapeIsland = NULL;
 	if( !err )	
 		err = allocateBranchIsland( &escapeIsland, kAllocateHigh, originalFunctionAddress );
-		if (err) printf("err = %x %d\n", err, __LINE__);
+		if (err) fprintf(stderr, "err = %x %s:%d\n", err, __FILE__, __LINE__);
 
 	
 #if defined(__ppc__) || defined(__POWERPC__)
@@ -264,12 +292,12 @@
 		branchAbsoluteInstruction = 0x48000002 | escapeIslandAddress;
 	}
 #elif defined(__i386__) || defined(__x86_64__)
-        if (err) printf("err = %x %d\n", err, __LINE__);
+        if (err) fprintf(stderr, "err = %x %s:%d\n", err, __FILE__, __LINE__);
 
 	if( !err )
 		err = setBranchIslandTarget_i386( escapeIsland, overrideFunctionAddress, 0 );
  
-	if (err) printf("err = %x %d\n", err, __LINE__);
+	if (err) fprintf(stderr, "err = %x %s:%d\n", err, __FILE__, __LINE__);
 	// Build the jump relative instruction to the escape island
 #endif
 
@@ -285,10 +313,13 @@
 	}
 #endif
 	
-	//	Optionally allocate & return the reentry island.
+	//	Optionally allocate & return the reentry island. This may contain relocated
+	//  jmp instructions and so has all the same addressing reachability requirements
+	//  the escape island has to the original function, except the escape island is
+	//  technically our original function.
 	BranchIsland	*reentryIsland = NULL;
 	if( !err && originalFunctionReentryIsland ) {
-		err = allocateBranchIsland( &reentryIsland, kAllocateNormal, NULL);
+		err = allocateBranchIsland( &reentryIsland, kAllocateHigh, escapeIsland);
 		if( !err )
 			*originalFunctionReentryIsland = reentryIsland;
 	}
@@ -331,9 +362,19 @@
 	//
 	// Note that on i386, we do not support someone else changing the code under our feet
 	if ( !err ) {
+		fixupInstructions(originalFunctionPtr, reentryIsland, originalInstructions,
+					originalInstructionCount, originalInstructionSizes );
+	
 		if( reentryIsland )
 			err = setBranchIslandTarget_i386( reentryIsland,
 										 (void*) ((char *)originalFunctionPtr+eatenCount), originalInstructions );
+		// try making islands executable before planting the jmp
+#if defined(__x86_64__) || defined(__i386__)
+        if( !err )
+            err = makeIslandExecutable(escapeIsland);
+        if( !err && reentryIsland )
+            err = makeIslandExecutable(reentryIsland);
+#endif
 		if ( !err )
 			atomic_mov64((uint64_t *)originalFunctionPtr, jumpRelativeInstruction);
 	}
@@ -347,10 +388,6 @@
 			freeBranchIsland( escapeIsland );
 	}
 
-#if defined(__x86_64__)
-        err = makeIslandExecutable(escapeIsland);
-        err = makeIslandExecutable(reentryIsland);
-#endif
 #ifdef DEBUG_DISASM
   {
     fprintf(stderr, "First 16 bytes of the function after slicing: ");
@@ -362,7 +399,6 @@
     fprintf(stderr, "\n");
   }
 #endif
-
 	return err;
 }
 
@@ -400,12 +436,15 @@
 		err = host_page_size( mach_host_self(), &pageSize );
 		if( !err ) {
 			assert( sizeof( BranchIsland ) <= pageSize );
-#if defined(__x86_64__)
+#if defined(__ppc__) || defined(__POWERPC__)
+			vm_address_t first = 0xfeffffff;
+			vm_address_t last = 0xfe000000 + pageSize;
+#elif defined(__x86_64__)
 			vm_address_t first = ((uint64_t)originalFunctionAddress & ~(uint64_t)(((uint64_t)1 << 31) - 1)) | ((uint64_t)1 << 31); // start in the middle of the page?
 			vm_address_t last = 0x0;
 #else
-			vm_address_t first = 0xfeffffff;
-			vm_address_t last = 0xfe000000 + pageSize;
+			vm_address_t first = 0xffc00000;
+			vm_address_t last = 0xfffe0000;
 #endif
 
 			vm_address_t page = first;
@@ -434,7 +473,7 @@
 	} else {
 		void *block = malloc( sizeof( BranchIsland ) );
 		if( block )
-			*island = (BranchIsland*)block;
+			*island = block;
 		else
 			err = KERN_NO_SPACE;
 	}
@@ -577,23 +616,25 @@
 
 #if defined(__i386__)
 static AsmInstructionMatch possibleInstructions[] = {
+	{ 0x5, {0xFF, 0x00, 0x00, 0x00, 0x00}, {0xE9, 0x00, 0x00, 0x00, 0x00} },	// jmp 0x????????
+	{ 0x5, {0xFF, 0xFF, 0xFF, 0xFF, 0xFF}, {0x55, 0x89, 0xe5, 0xc9, 0xc3} },	// push %esp; mov %esp,%ebp; leave; ret
 	{ 0x1, {0xFF}, {0x90} },							// nop
-	{ 0x1, {0xFF}, {0x55} },							// push %esp
+	{ 0x1, {0xF8}, {0x50} },							// push %reg
 	{ 0x2, {0xFF, 0xFF}, {0x89, 0xE5} },				                // mov %esp,%ebp
 	{ 0x3, {0xFF, 0xFF, 0xFF}, {0x89, 0x1C, 0x24} },				                // mov %ebx,(%esp)
-	{ 0x1, {0xFF}, {0x53} },							// push %ebx
 	{ 0x3, {0xFF, 0xFF, 0x00}, {0x83, 0xEC, 0x00} },	                        // sub 0x??, %esp
 	{ 0x6, {0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00}, {0x81, 0xEC, 0x00, 0x00, 0x00, 0x00} },	// sub 0x??, %esp with 32bit immediate
-	{ 0x1, {0xFF}, {0x57} },							// push %edi
-	{ 0x1, {0xFF}, {0x56} },							// push %esi
 	{ 0x2, {0xFF, 0xFF}, {0x31, 0xC0} },						// xor %eax, %eax
 	{ 0x3, {0xFF, 0x4F, 0x00}, {0x8B, 0x45, 0x00} },  // mov $imm(%ebp), %reg
 	{ 0x3, {0xFF, 0x4C, 0x00}, {0x8B, 0x40, 0x00} },  // mov $imm(%eax-%edx), %reg
-        { 0x4, {0xFF, 0x00, 0x00, 0x00}, {0x8B, 0x00, 0x00, 0x00} },  // mov r16,r/m16 or r32,r/m32
-        { 0x5, {0xFF, 0x00, 0x00, 0x00, 0x00}, {0xB9, 0x00, 0x00, 0x00, 0x00} }, // mov $imm, %ecx
-  { 0x5, {0xFF, 0x00, 0x00, 0x00, 0x00}, {0xB8, 0x00, 0x00, 0x00, 0x00} }, // mov $imm, %eax
-        { 0x4, {0xFF, 0xFF, 0xFF, 0x00}, {0x66, 0x0F, 0xEF, 0x00} },             // pxor xmm2/128, xmm1
-        { 0x2, {0xFF, 0xFF}, {0xDB, 0xE3} }, // fninit
+	{ 0x3, {0xFF, 0x4F, 0x00}, {0x8A, 0x4D, 0x00} },  // mov $imm(%ebp), %cl
+	{ 0x4, {0xFF, 0xFF, 0xFF, 0x00}, {0x8B, 0x4C, 0x24, 0x00} },  			// mov $imm(%esp), %ecx
+	{ 0x4, {0xFF, 0x00, 0x00, 0x00}, {0x8B, 0x00, 0x00, 0x00} },  			// mov r16,r/m16 or r32,r/m32
+	{ 0x5, {0xFF, 0x00, 0x00, 0x00, 0x00}, {0xB9, 0x00, 0x00, 0x00, 0x00} }, 	// mov $imm, %ecx
+	{ 0x5, {0xFF, 0x00, 0x00, 0x00, 0x00}, {0xB8, 0x00, 0x00, 0x00, 0x00} }, 	// mov $imm, %eax
+	{ 0x4, {0xFF, 0xFF, 0xFF, 0x00}, {0x66, 0x0F, 0xEF, 0x00} },             	// pxor xmm2/128, xmm1
+	{ 0x2, {0xFF, 0xFF}, {0xDB, 0xE3} }, 						// fninit
+	{ 0x5, {0xFF, 0x00, 0x00, 0x00, 0x00}, {0xE8, 0x00, 0x00, 0x00, 0x00} },	// call $imm
 	{ 0x0 }
 };
 #elif defined(__x86_64__)
@@ -601,26 +642,34 @@
 // If it stops working, refer to http://ref.x86asm.net/geek.html#modrm_byte_32_64 to do it
 // more accurately.
 static AsmInstructionMatch possibleInstructions[] = {
+	{ 0x5, {0xFF, 0x00, 0x00, 0x00, 0x00}, {0xE9, 0x00, 0x00, 0x00, 0x00} },	// jmp 0x????????
 	{ 0x1, {0xFF}, {0x90} },							// nop
 	{ 0x1, {0xF8}, {0x50} },							// push %rX
-  { 0x1, {0xFF}, {0x65} },              // GS prefix
+	{ 0x1, {0xFF}, {0x65} },							// GS prefix
 	{ 0x3, {0xFF, 0xFF, 0xFF}, {0x48, 0x89, 0xE5} },				// mov %rsp,%rbp
 	{ 0x4, {0xFF, 0xFF, 0xFF, 0x00}, {0x48, 0x83, 0xEC, 0x00} },	                // sub 0x??, %rsp
 	{ 0x4, {0xFB, 0xFF, 0x07, 0x00}, {0x48, 0x89, 0x05, 0x00} },	                // move onto rbp
 	{ 0x3, {0xFB, 0xFF, 0x00}, {0x48, 0x89, 0x00} },	                            // mov %reg, %reg
+	{ 0x3, {0xFB, 0xFF, 0x00}, {0x49, 0x89, 0x00} },	                            // mov %reg, %reg (REX.WB)
 	{ 0x2, {0xFF, 0x00}, {0x41, 0x00} },						// push %rXX
 	{ 0x2, {0xFF, 0x00}, {0x85, 0x00} },						// test %rX,%rX
 	{ 0x2, {0xFF, 0x00}, {0x77, 0x00} },						// ja $i8
-	{ 0x5, {0xF8, 0x00, 0x00, 0x00, 0x00}, {0xB8, 0x00, 0x00, 0x00, 0x00} },        // mov $imm, %reg
-  { 0x5, {0xFF, 0x00, 0x00, 0x00, 0x00}, {0x25, 0x00, 0x00, 0x00, 0x00} },  // and $imm, %eax
+	{ 0x2, {0xFF, 0x00}, {0x74, 0x00} },						// je $i8
+	{ 0x5, {0xF8, 0x00, 0x00, 0x00, 0x00}, {0xB8, 0x00, 0x00, 0x00, 0x00} },	// mov $imm, %reg
+	{ 0x3, {0xFF, 0xFF, 0x00}, {0xFF, 0x77, 0x00} },				// pushq $imm(%rdi)
+	{ 0x2, {0xFF, 0xFF}, {0x31, 0xC0} },						// xor %eax, %eax
+	{ 0x5, {0xFF, 0x00, 0x00, 0x00, 0x00}, {0x25, 0x00, 0x00, 0x00, 0x00} },	// and $imm, %eax
 
-  { 0x8, {0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00},
-         {0x48, 0x8B, 0x34, 0x25, 0x00, 0x00, 0x00, 0x00}, },                     // mov $imm, %rsi
+  { 0x8, {0xFF, 0xFF, 0x3F, 0xFF, 0x00, 0x00, 0x00, 0x00},
+         {0x48, 0x8B, 0x04, 0x25, 0x00, 0x00, 0x00, 0x00}, },                     // mov $imm, %{rax,rdx,rsp,rsi}
   { 0x4, {0xFF, 0xFF, 0xFF, 0x00}, {0x48, 0x83, 0xFA, 0x00}, },   // cmp $i8, %rdx
+	{ 0x4, {0xFF, 0xFF, 0x00, 0x00}, {0x83, 0x7f, 0x00, 0x00}, },			// cmpl $imm, $imm(%rdi)
 	{ 0xa, {0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
                {0x48, 0xB8, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} },    // mov $imm, %rax
         { 0x6, {0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00},
                {0x81, 0xE6, 0x00, 0x00, 0x00, 0x00} },                            // and $imm, %esi
+        { 0x6, {0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00},
+               {0xFF, 0x25, 0x00, 0x00, 0x00, 0x00} },                            // jmpq *(%rip)
         { 0x4, {0xFF, 0xFF, 0xFF, 0x00}, {0x66, 0x0F, 0xEF, 0x00} },              // pxor xmm2/128, xmm1
         { 0x2, {0xFF, 0x00}, {0x89, 0x00} },                               // mov r/m32,r32 or r/m16,r16
         { 0x3, {0xFF, 0xFF, 0xFF}, {0x49, 0x89, 0xF8} },                   // mov %rdi,%r8        
@@ -630,30 +679,31 @@
 };
 #endif
 
-static Boolean codeMatchesInstruction(unsigned char *code, AsmInstructionMatch* instruction)
+static Boolean codeMatchesInstruction(unsigned char *code, AsmInstructionMatch* instruction) 
 {
 	Boolean match = true;
+	
 	size_t i;
   assert(instruction);
 #ifdef DEBUG_DISASM
-  fprintf(stderr, "Matching: ");
+	fprintf(stderr, "Matching: ");
 #endif  
 	for (i=0; ilength; i++) {
 		unsigned char mask = instruction->mask[i];
 		unsigned char constraint = instruction->constraint[i];
 		unsigned char codeValue = code[i];
 #ifdef DEBUG_DISASM
-    fprintf(stderr, "%x ", (unsigned)codeValue);
+		fprintf(stderr, "%x ", (unsigned)codeValue);
 #endif    
 		match = ((codeValue & mask) == constraint);
 		if (!match) break;
 	}
 #ifdef DEBUG_DISASM
-  if (match) {
-    fprintf(stderr, " OK\n");
-  } else {
-    fprintf(stderr, " FAIL\n");
-  }
+	if (match) {
+		fprintf(stderr, " OK\n");
+	} else {
+		fprintf(stderr, " FAIL\n");
+	}
 #endif  
 	return match;
 }
@@ -661,17 +711,21 @@
 #if defined(__i386__) || defined(__x86_64__)
 	static Boolean 
 eatKnownInstructions( 
-	unsigned char *code, 
-	uint64_t* newInstruction,
-	int* howManyEaten, 
-	char* originalInstructions )
+	unsigned char	*code, 
+	uint64_t		*newInstruction,
+	int				*howManyEaten, 
+	char			*originalInstructions,
+	int				*originalInstructionCount, 
+	uint8_t			*originalInstructionSizes )
 {
 	Boolean allInstructionsKnown = true;
 	int totalEaten = 0;
 	unsigned char* ptr = code;
 	int remainsToEat = 5; // a JMP instruction takes 5 bytes
+	int instructionIndex = 0;
 	
 	if (howManyEaten) *howManyEaten = 0;
+	if (originalInstructionCount) *originalInstructionCount = 0;
 	while (remainsToEat > 0) {
 		Boolean curInstructionKnown = false;
 		
@@ -685,6 +739,7 @@
 		// if all instruction matches failed, we don't know current instruction then, stop here
 		if (!curInstructionKnown) { 
 			allInstructionsKnown = false;
+			fprintf(stderr, "mach_override: some instructions unknown! Need to update mach_override.c\n");
 			break;
 		}
 		
@@ -693,6 +748,10 @@
 		ptr += eaten;
 		remainsToEat -= eaten;
 		totalEaten += eaten;
+		
+		if (originalInstructionSizes) originalInstructionSizes[instructionIndex] = eaten;
+		instructionIndex += 1;
+		if (originalInstructionCount) *originalInstructionCount = instructionIndex;
 	}
 
 
@@ -705,8 +764,8 @@
 			memset(originalInstructions, 0x90 /* NOP */, kOriginalInstructionsSize); // fill instructions with NOP
 			bcopy(code, originalInstructions, totalEaten);
 		} else {
-#ifdef DEBUG_DISASM    
-			fprintf (stderr, "Not enough space in island to store original instructions. Adapt the island definition and kOriginalInstructionsSize\n");
+#ifdef DEBUG_DISASM
+			fprintf(stderr, "Not enough space in island to store original instructions. Adapt the island definition and kOriginalInstructionsSize\n");
 #endif      
 			return false;
 		}
@@ -725,6 +784,32 @@
 
 	return allInstructionsKnown;
 }
+
+	static void
+fixupInstructions(
+    void		*originalFunction,
+    void		*escapeIsland,
+    void		*instructionsToFix,
+	int			instructionCount,
+	uint8_t		*instructionSizes )
+{
+	int	index;
+	for (index = 0;index < instructionCount;index += 1)
+	{
+		if ((*(uint8_t*)instructionsToFix == 0xE9) || // 32-bit jump relative
+		    (*(uint8_t*)instructionsToFix == 0xE8))   // 32-bit call relative
+		{
+			uint32_t offset = (uintptr_t)originalFunction - (uintptr_t)escapeIsland;
+			uint32_t *jumpOffsetPtr = (uint32_t*)((uintptr_t)instructionsToFix + 1);
+			*jumpOffsetPtr += offset;
+		}
+
+		
+		originalFunction = (void*)((uintptr_t)originalFunction + instructionSizes[index]);
+		escapeIsland = (void*)((uintptr_t)escapeIsland + instructionSizes[index]);
+		instructionsToFix = (void*)((uintptr_t)instructionsToFix + instructionSizes[index]);
+    }
+}
 #endif
 
 #if defined(__i386__)
@@ -771,5 +856,4 @@
 }
 #endif
 #endif
-
 #endif  // __APPLE__



From kcc at google.com  Thu Dec  8 13:18:51 2011
From: kcc at google.com (Kostya Serebryany)
Date: Thu, 8 Dec 2011 11:18:51 -0800
Subject: [llvm-commits] [PATCH] fix the version of mach_override/* in
 AddressSanitizer to run on OS X Lion
In-Reply-To: 
References: 
Message-ID: 

Thanks!
r146166.

Side question: does anyone know how to intercept functions on Darwin
w/o mach_override?

On Thu, Dec 8, 2011 at 7:15 AM, Alexander Potapenko wrote:

> This patch contains several changes to mach_override/* that allow to
> build and run AddressSanitizer tests on OS X Lion (10.7):
>
>  -- mach_override.c is merged with the upstream version at
>
> https://github.com/rentzsch/mach_star/tree/f8e0c424b5be5cb641ded67c265e616157ae4bcf
> (I've copied it and added the DEBUG_DISASM code and additional opcodes
> from our version)
>  -- #ifdef __APPLE__ is removed from both files (we shouldn't need it,
> because mach_override is used on Mac only)
>

We do need #ifdef __APPLE__, all these files are currently compiled on
linux too.

--kcc


>  -- some opcodes are added in order to parse the library functions on Lion
>  -- fixupInstructions() is extended to relocate relative calls, not only
> jumps
>
>
> --
> Alexander Potapenko
> Software Engineer
> Google Moscow
>
-------------- next part --------------
An HTML attachment was scrubbed...
URL: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20111208/7abe7344/attachment.html 

From evan.cheng at apple.com  Thu Dec  8 13:21:39 2011
From: evan.cheng at apple.com (Evan Cheng)
Date: Thu, 08 Dec 2011 19:21:39 -0000
Subject: [llvm-commits] [llvm] r146167 -
	/llvm/trunk/test/CodeGen/X86/prefetch.ll
Message-ID: <20111208192139.5C48F2A6C12C@llvm.org>

Author: evancheng
Date: Thu Dec  8 13:21:39 2011
New Revision: 146167

URL: http://llvm.org/viewvc/llvm-project?rev=146167&view=rev
Log:
Add test for r146163.

Modified:
    llvm/trunk/test/CodeGen/X86/prefetch.ll

Modified: llvm/trunk/test/CodeGen/X86/prefetch.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/prefetch.ll?rev=146167&r1=146166&r2=146167&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/prefetch.ll (original)
+++ llvm/trunk/test/CodeGen/X86/prefetch.ll Thu Dec  8 13:21:39 2011
@@ -1,4 +1,7 @@
 ; RUN: llc < %s -march=x86 -mattr=+sse | FileCheck %s
+; RUN: llc < %s -march=x86 -mattr=+avx | FileCheck %s
+
+; rdar://10538297
 
 define void @t(i8* %ptr) nounwind  {
 entry:



From evan.cheng at apple.com  Thu Dec  8 13:23:10 2011
From: evan.cheng at apple.com (Evan Cheng)
Date: Thu, 08 Dec 2011 19:23:10 -0000
Subject: [llvm-commits] [llvm] r146168 - in /llvm/trunk:
 include/llvm/CodeGen/MachineInstr.h lib/CodeGen/MachineInstr.cpp
Message-ID: <20111208192310.977E82A6C12C@llvm.org>

Author: evancheng
Date: Thu Dec  8 13:23:10 2011
New Revision: 146168

URL: http://llvm.org/viewvc/llvm-project?rev=146168&view=rev
Log:
Make MachineInstr instruction property queries more flexible. This change all
clients to decide whether to look inside bundled instructions and whether
the query should return true if any / all bundled instructions have the
queried property.

Modified:
    llvm/trunk/include/llvm/CodeGen/MachineInstr.h
    llvm/trunk/lib/CodeGen/MachineInstr.cpp

Modified: llvm/trunk/include/llvm/CodeGen/MachineInstr.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/MachineInstr.h?rev=146168&r1=146167&r2=146168&view=diff
==============================================================================
--- llvm/trunk/include/llvm/CodeGen/MachineInstr.h (original)
+++ llvm/trunk/include/llvm/CodeGen/MachineInstr.h Thu Dec  8 13:23:10 2011
@@ -277,6 +277,12 @@
   /// API for querying MachineInstr properties. They are the same as MCInstrDesc
   /// queries but they are bundle aware.
 
+  enum QueryType {
+    IgnoreBundle,    // Ignore bundles
+    AnyInBundle,     // Return true if any instruction in bundle has property
+    AllInBundle      // Return true if all instructions in bundle have property
+  };
+
   /// hasProperty - Return true if the instruction (or in the case of a bundle,
   /// the instructions inside the bundle) has the specified property.
   /// The first argument is the property being queried.
@@ -285,43 +291,42 @@
   /// If the third argument is true, than the query can return true when *any*
   /// of the bundled instructions has the queried property. If it's false, then
   /// this can return true iff *all* of the instructions have the property.
-  bool hasProperty(unsigned Flag,
-                   bool PeekInBundle = true, bool IsOr = true) const;
+  bool hasProperty(unsigned Flag, QueryType Type = AnyInBundle) const;
 
   /// isVariadic - Return true if this instruction can have a variable number of
   /// operands.  In this case, the variable operands will be after the normal
   /// operands but before the implicit definitions and uses (if any are
   /// present).
-  bool isVariadic() const {
-    return hasProperty(MCID::Variadic, false);
+  bool isVariadic(QueryType Type = IgnoreBundle) const {
+    return hasProperty(MCID::Variadic, Type);
   }
 
   /// hasOptionalDef - Set if this instruction has an optional definition, e.g.
   /// ARM instructions which can set condition code if 's' bit is set.
-  bool hasOptionalDef() const {
-    return hasProperty(MCID::HasOptionalDef, false);
+  bool hasOptionalDef(QueryType Type = IgnoreBundle) const {
+    return hasProperty(MCID::HasOptionalDef, Type);
   }
 
   /// isPseudo - Return true if this is a pseudo instruction that doesn't
   /// correspond to a real machine instruction.
   ///
-  bool isPseudo() const {
-    return hasProperty(MCID::Pseudo, false);
+  bool isPseudo(QueryType Type = IgnoreBundle) const {
+    return hasProperty(MCID::Pseudo, Type);
   }
 
-  bool isReturn() const {
-    return hasProperty(MCID::Return);
+  bool isReturn(QueryType Type = AnyInBundle) const {
+    return hasProperty(MCID::Return, Type);
   }
 
-  bool isCall() const {
-    return hasProperty(MCID::Call);
+  bool isCall(QueryType Type = AnyInBundle) const {
+    return hasProperty(MCID::Call, Type);
   }
 
   /// isBarrier - Returns true if the specified instruction stops control flow
   /// from executing the instruction immediately following it.  Examples include
   /// unconditional branches and return instructions.
-  bool isBarrier() const {
-    return hasProperty(MCID::Barrier);
+  bool isBarrier(QueryType Type = AnyInBundle) const {
+    return hasProperty(MCID::Barrier, Type);
   }
 
   /// isTerminator - Returns true if this instruction part of the terminator for
@@ -330,78 +335,78 @@
   ///
   /// Various passes use this to insert code into the bottom of a basic block,
   /// but before control flow occurs.
-  bool isTerminator() const {
-    return hasProperty(MCID::Terminator);
+  bool isTerminator(QueryType Type = AnyInBundle) const {
+    return hasProperty(MCID::Terminator, Type);
   }
 
   /// isBranch - Returns true if this is a conditional, unconditional, or
   /// indirect branch.  Predicates below can be used to discriminate between
   /// these cases, and the TargetInstrInfo::AnalyzeBranch method can be used to
   /// get more information.
-  bool isBranch() const {
-    return hasProperty(MCID::Branch);
+  bool isBranch(QueryType Type = AnyInBundle) const {
+    return hasProperty(MCID::Branch, Type);
   }
 
   /// isIndirectBranch - Return true if this is an indirect branch, such as a
   /// branch through a register.
-  bool isIndirectBranch() const {
-    return hasProperty(MCID::IndirectBranch);
+  bool isIndirectBranch(QueryType Type = AnyInBundle) const {
+    return hasProperty(MCID::IndirectBranch, Type);
   }
 
   /// isConditionalBranch - Return true if this is a branch which may fall
   /// through to the next instruction or may transfer control flow to some other
   /// block.  The TargetInstrInfo::AnalyzeBranch method can be used to get more
   /// information about this branch.
-  bool isConditionalBranch() const {
-    return isBranch() & !isBarrier() & !isIndirectBranch();
+  bool isConditionalBranch(QueryType Type = AnyInBundle) const {
+    return isBranch(Type) & !isBarrier(Type) & !isIndirectBranch(Type);
   }
 
   /// isUnconditionalBranch - Return true if this is a branch which always
   /// transfers control flow to some other block.  The
   /// TargetInstrInfo::AnalyzeBranch method can be used to get more information
   /// about this branch.
-  bool isUnconditionalBranch() const {
-    return isBranch() & isBarrier() & !isIndirectBranch();
+  bool isUnconditionalBranch(QueryType Type = AnyInBundle) const {
+    return isBranch(Type) & isBarrier(Type) & !isIndirectBranch(Type);
   }
 
   // isPredicable - Return true if this instruction has a predicate operand that
   // controls execution.  It may be set to 'always', or may be set to other
   /// values.   There are various methods in TargetInstrInfo that can be used to
   /// control and modify the predicate in this instruction.
-  bool isPredicable() const {
+  bool isPredicable(QueryType Type = AllInBundle) const {
     // If it's a bundle than all bundled instructions must be predicable for this
     // to return true.
-    return hasProperty(MCID::Predicable, true, false);
+    return hasProperty(MCID::Predicable, Type);
   }
 
   /// isCompare - Return true if this instruction is a comparison.
-  bool isCompare() const {
-    return hasProperty(MCID::Compare, false);
+  bool isCompare(QueryType Type = IgnoreBundle) const {
+    return hasProperty(MCID::Compare, Type);
   }
 
   /// isMoveImmediate - Return true if this instruction is a move immediate
   /// (including conditional moves) instruction.
-  bool isMoveImmediate() const {
-    return hasProperty(MCID::MoveImm, false);
+  bool isMoveImmediate(QueryType Type = IgnoreBundle) const {
+    return hasProperty(MCID::MoveImm, Type);
   }
 
   /// isBitcast - Return true if this instruction is a bitcast instruction.
   ///
-  bool isBitcast() const {
-    return hasProperty(MCID::Bitcast, false);
+  bool isBitcast(QueryType Type = IgnoreBundle) const {
+    return hasProperty(MCID::Bitcast, Type);
   }
 
   /// isNotDuplicable - Return true if this instruction cannot be safely
   /// duplicated.  For example, if the instruction has a unique labels attached
   /// to it, duplicating it would cause multiple definition errors.
-  bool isNotDuplicable() const {
-    return hasProperty(MCID::NotDuplicable);
+  bool isNotDuplicable(QueryType Type = AnyInBundle) const {
+    return hasProperty(MCID::NotDuplicable, Type);
   }
 
   /// hasDelaySlot - Returns true if the specified instruction has a delay slot
   /// which must be filled by the code generator.
-  bool hasDelaySlot() const {
-    return hasProperty(MCID::DelaySlot);
+  bool hasDelaySlot(QueryType Type = AnyInBundle) const {
+    return hasProperty(MCID::DelaySlot, Type);
   }
 
   /// canFoldAsLoad - Return true for instructions that can be folded as
@@ -412,8 +417,8 @@
   /// on x86, to allow them to be folded when it is beneficial.
   /// This should only be set on instructions that return a value in their
   /// only virtual register definition.
-  bool canFoldAsLoad() const {
-    return hasProperty(MCID::FoldableAsLoad, false);
+  bool canFoldAsLoad(QueryType Type = IgnoreBundle) const {
+    return hasProperty(MCID::FoldableAsLoad, Type);
   }
 
   //===--------------------------------------------------------------------===//
@@ -423,8 +428,8 @@
   /// mayLoad - Return true if this instruction could possibly read memory.
   /// Instructions with this flag set are not necessarily simple load
   /// instructions, they may load a value and modify it, for example.
-  bool mayLoad() const {
-    return hasProperty(MCID::MayLoad);
+  bool mayLoad(QueryType Type = AnyInBundle) const {
+    return hasProperty(MCID::MayLoad, Type);
   }
 
 
@@ -432,8 +437,8 @@
   /// Instructions with this flag set are not necessarily simple store
   /// instructions, they may store a modified value based on their operands, or
   /// may not actually modify anything, for example.
-  bool mayStore() const {
-    return hasProperty(MCID::MayStore);
+  bool mayStore(QueryType Type = AnyInBundle) const {
+    return hasProperty(MCID::MayStore, Type);
   }
 
   //===--------------------------------------------------------------------===//
@@ -450,8 +455,8 @@
   /// sometimes.  In these cases, the call to commuteInstruction will fail.
   /// Also note that some instructions require non-trivial modification to
   /// commute them.
-  bool isCommutable() const {
-    return hasProperty(MCID::Commutable, false);
+  bool isCommutable(QueryType Type = IgnoreBundle) const {
+    return hasProperty(MCID::Commutable, Type);
   }
 
   /// isConvertibleTo3Addr - Return true if this is a 2-address instruction
@@ -468,8 +473,8 @@
   /// is allowed to fail if the transformation isn't valid for this specific
   /// instruction (e.g. shl reg, 4 on x86).
   ///
-  bool isConvertibleTo3Addr() const {
-    return hasProperty(MCID::ConvertibleTo3Addr, false);
+  bool isConvertibleTo3Addr(QueryType Type = IgnoreBundle) const {
+    return hasProperty(MCID::ConvertibleTo3Addr, Type);
   }
 
   /// usesCustomInsertionHook - Return true if this instruction requires
@@ -480,26 +485,26 @@
   ///
   /// If this is true, the TargetLoweringInfo::InsertAtEndOfBasicBlock method
   /// is used to insert this into the MachineBasicBlock.
-  bool usesCustomInsertionHook() const {
-    return hasProperty(MCID::UsesCustomInserter, false);
+  bool usesCustomInsertionHook(QueryType Type = IgnoreBundle) const {
+    return hasProperty(MCID::UsesCustomInserter, Type);
   }
 
   /// hasPostISelHook - Return true if this instruction requires *adjustment*
   /// after instruction selection by calling a target hook. For example, this
   /// can be used to fill in ARM 's' optional operand depending on whether
   /// the conditional flag register is used.
-  bool hasPostISelHook() const {
-    return hasProperty(MCID::HasPostISelHook, false);
+  bool hasPostISelHook(QueryType Type = IgnoreBundle) const {
+    return hasProperty(MCID::HasPostISelHook, Type);
   }
 
   /// isRematerializable - Returns true if this instruction is a candidate for
   /// remat.  This flag is deprecated, please don't use it anymore.  If this
   /// flag is set, the isReallyTriviallyReMaterializable() method is called to
   /// verify the instruction is really rematable.
-  bool isRematerializable() const {
+  bool isRematerializable(QueryType Type = AllInBundle) const {
     // It's only possible to re-mat a bundle if all bundled instructions are
     // re-materializable.
-    return hasProperty(MCID::Rematerializable, true, false);
+    return hasProperty(MCID::Rematerializable, Type);
   }
 
   /// isAsCheapAsAMove - Returns true if this instruction has the same cost (or
@@ -508,10 +513,10 @@
   /// where we would like to remat or hoist the instruction, but not if it costs
   /// more than moving the instruction into the appropriate register. Note, we
   /// are not marking copies from and to the same register class with this flag.
-  bool isAsCheapAsAMove() const {
+  bool isAsCheapAsAMove(QueryType Type = AllInBundle) const {
     // Only returns true for a bundle if all bundled instructions are cheap.
     // FIXME: This probably requires a target hook.
-    return hasProperty(MCID::CheapAsAMove, true, true);
+    return hasProperty(MCID::CheapAsAMove, Type);
   }
 
   /// hasExtraSrcRegAllocReq - Returns true if this instruction source operands
@@ -520,8 +525,8 @@
   /// even / odd pair, ARM::STM registers have to be in ascending order.
   /// Post-register allocation passes should not attempt to change allocations
   /// for sources of instructions with this flag.
-  bool hasExtraSrcRegAllocReq() const {
-    return hasProperty(MCID::ExtraSrcRegAllocReq);
+  bool hasExtraSrcRegAllocReq(QueryType Type = AnyInBundle) const {
+    return hasProperty(MCID::ExtraSrcRegAllocReq, Type);
   }
 
   /// hasExtraDefRegAllocReq - Returns true if this instruction def operands
@@ -530,8 +535,8 @@
   /// even / odd pair, ARM::LDM registers have to be in ascending order.
   /// Post-register allocation passes should not attempt to change allocations
   /// for definitions of instructions with this flag.
-  bool hasExtraDefRegAllocReq() const {
-    return hasProperty(MCID::ExtraDefRegAllocReq);
+  bool hasExtraDefRegAllocReq(QueryType Type = AnyInBundle) const {
+    return hasProperty(MCID::ExtraDefRegAllocReq, Type);
   }
 
 

Modified: llvm/trunk/lib/CodeGen/MachineInstr.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineInstr.cpp?rev=146168&r1=146167&r2=146168&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/MachineInstr.cpp (original)
+++ llvm/trunk/lib/CodeGen/MachineInstr.cpp Thu Dec  8 13:23:10 2011
@@ -749,24 +749,24 @@
 }
 
 bool
-MachineInstr::hasProperty(unsigned MCFlag, bool PeekInBundle, bool IsOr) const {
-  if (!PeekInBundle || getOpcode() != TargetOpcode::BUNDLE)
+MachineInstr::hasProperty(unsigned MCFlag, QueryType Type) const {
+  if (Type == IgnoreBundle || getOpcode() != TargetOpcode::BUNDLE)
     return getDesc().getFlags() & (1 << MCFlag);
 
   const MachineBasicBlock *MBB = getParent();
   MachineBasicBlock::const_insn_iterator MII = *this; ++MII;
   while (MII != MBB->end() && MII->isInsideBundle()) {
     if (MII->getDesc().getFlags() & (1 << MCFlag)) {
-      if (IsOr)
+      if (Type == AnyInBundle)
         return true;
     } else {
-      if (!IsOr)
+      if (Type == AllInBundle)
         return false;
     }
     ++MII;
   }
 
-  return !IsOr;
+  return Type == AllInBundle;
 }
 
 bool MachineInstr::isIdenticalTo(const MachineInstr *Other,



From grosbach at apple.com  Thu Dec  8 13:27:39 2011
From: grosbach at apple.com (Jim Grosbach)
Date: Thu, 08 Dec 2011 19:27:39 -0000
Subject: [llvm-commits] [llvm] r146170 -
	/llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
Message-ID: <20111208192739.2FD482A6C12C@llvm.org>

Author: grosbach
Date: Thu Dec  8 13:27:38 2011
New Revision: 146170

URL: http://llvm.org/viewvc/llvm-project?rev=146170&view=rev
Log:
ARM assembler support for register name aliases.

rdar://10550084

Modified:
    llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp

Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp?rev=146170&r1=146169&r2=146170&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp (original)
+++ llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Thu Dec  8 13:27:38 2011
@@ -2148,8 +2148,6 @@
   const AsmToken &Tok = Parser.getTok();
   if (Tok.isNot(AsmToken::Identifier)) return -1;
 
-  // FIXME: Validate register for the current architecture; we have to do
-  // validation later, so maybe there is no need for this here.
   std::string lowerCase = Tok.getString().lower();
   unsigned RegNum = MatchRegisterName(lowerCase);
   if (!RegNum) {
@@ -2158,6 +2156,22 @@
       .Case("r14", ARM::LR)
       .Case("r15", ARM::PC)
       .Case("ip", ARM::R12)
+      // Additional register name aliases for 'gas' compatibility.
+      .Case("a1", ARM::R0)
+      .Case("a2", ARM::R1)
+      .Case("a3", ARM::R2)
+      .Case("a4", ARM::R3)
+      .Case("v1", ARM::R4)
+      .Case("v2", ARM::R5)
+      .Case("v3", ARM::R6)
+      .Case("v4", ARM::R7)
+      .Case("v5", ARM::R8)
+      .Case("v6", ARM::R9)
+      .Case("v7", ARM::R10)
+      .Case("v8", ARM::R11)
+      .Case("sb", ARM::R9)
+      .Case("sl", ARM::R10)
+      .Case("fp", ARM::R11)
       .Default(0);
   }
   if (!RegNum) return -1;



From resistor at mac.com  Thu Dec  8 13:32:14 2011
From: resistor at mac.com (Owen Anderson)
Date: Thu, 08 Dec 2011 19:32:14 -0000
Subject: [llvm-commits] [llvm] r146171 - in /llvm/trunk:
 lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
 lib/CodeGen/SelectionDAG/TargetLowering.cpp
 lib/Target/PowerPC/PPCISelLowering.cpp lib/Target/X86/X86ISelLowering.cpp
 test/CodeGen/Thumb2/thumb2-cbnz.ll
Message-ID: <20111208193214.9AF602A6C12C@llvm.org>

Author: resistor
Date: Thu Dec  8 13:32:14 2011
New Revision: 146171

URL: http://llvm.org/viewvc/llvm-project?rev=146171&view=rev
Log:
Teach SelectionDAG to match more calls to libm functions onto existing SDNodes.  Mark these nodes as illegal by default, unless the target declares otherwise.

Modified:
    llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
    llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp
    llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp
    llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
    llvm/trunk/test/CodeGen/Thumb2/thumb2-cbnz.ll

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp?rev=146171&r1=146170&r2=146171&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp Thu Dec  8 13:32:14 2011
@@ -5559,6 +5559,53 @@
                                    Tmp.getValueType(), Tmp));
           return;
         }
+      } else if (Name == "floor" || Name == "floorf" || Name == "floorl") {
+        if (I.getNumArgOperands() == 1 && // Basic sanity checks.
+            I.getArgOperand(0)->getType()->isFloatingPointTy() &&
+            I.getType() == I.getArgOperand(0)->getType()) {
+          SDValue Tmp = getValue(I.getArgOperand(0));
+          setValue(&I, DAG.getNode(ISD::FFLOOR, getCurDebugLoc(),
+                                   Tmp.getValueType(), Tmp));
+          return;
+        }
+      } else if (Name == "nearbyint" || Name == "nearbyintf" ||
+                 Name == "nearbyintl") {
+        if (I.getNumArgOperands() == 1 && // Basic sanity checks.
+            I.getArgOperand(0)->getType()->isFloatingPointTy() &&
+            I.getType() == I.getArgOperand(0)->getType()) {
+          SDValue Tmp = getValue(I.getArgOperand(0));
+          setValue(&I, DAG.getNode(ISD::FNEARBYINT, getCurDebugLoc(),
+                                   Tmp.getValueType(), Tmp));
+          return;
+        }
+      } else if (Name == "ceil" || Name == "ceilf" || Name == "ceill") {
+        if (I.getNumArgOperands() == 1 && // Basic sanity checks.
+            I.getArgOperand(0)->getType()->isFloatingPointTy() &&
+            I.getType() == I.getArgOperand(0)->getType()) {
+          SDValue Tmp = getValue(I.getArgOperand(0));
+          setValue(&I, DAG.getNode(ISD::FCEIL, getCurDebugLoc(),
+                                   Tmp.getValueType(), Tmp));
+          return;
+        }
+      } else if (Name == "rint" || Name == "rintf" || Name == "rintl") {
+        if (I.getNumArgOperands() == 1 && // Basic sanity checks.
+            I.getArgOperand(0)->getType()->isFloatingPointTy() &&
+            I.getType() == I.getArgOperand(0)->getType()) {
+          SDValue Tmp = getValue(I.getArgOperand(0));
+          setValue(&I, DAG.getNode(ISD::FRINT, getCurDebugLoc(),
+                                   Tmp.getValueType(), Tmp));
+          return;
+        }
+      } else if (Name == "trunc" || Name == "truncf" || Name == "truncl") {
+        if (I.getNumArgOperands() == 1 && // Basic sanity checks.
+            I.getArgOperand(0)->getType()->isFloatingPointTy() &&
+            I.getType() == I.getArgOperand(0)->getType()) {
+          SDValue Tmp = getValue(I.getArgOperand(0));
+          setValue(&I, DAG.getNode(ISD::FTRUNC, getCurDebugLoc(),
+                                   Tmp.getValueType(), Tmp));
+          return;
+        }
+
       } else if (Name == "memcmp") {
         if (visitMemCmpCall(I))
           return;

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp?rev=146171&r1=146170&r2=146171&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp Thu Dec  8 13:32:14 2011
@@ -577,16 +577,26 @@
   setOperationAction(ISD::ConstantFP, MVT::f80, Expand);
 
   // These library functions default to expand.
-  setOperationAction(ISD::FLOG , MVT::f64, Expand);
-  setOperationAction(ISD::FLOG2, MVT::f64, Expand);
-  setOperationAction(ISD::FLOG10,MVT::f64, Expand);
-  setOperationAction(ISD::FEXP , MVT::f64, Expand);
-  setOperationAction(ISD::FEXP2, MVT::f64, Expand);
-  setOperationAction(ISD::FLOG , MVT::f32, Expand);
-  setOperationAction(ISD::FLOG2, MVT::f32, Expand);
-  setOperationAction(ISD::FLOG10,MVT::f32, Expand);
-  setOperationAction(ISD::FEXP , MVT::f32, Expand);
-  setOperationAction(ISD::FEXP2, MVT::f32, Expand);
+  setOperationAction(ISD::FLOG ,  MVT::f64, Expand);
+  setOperationAction(ISD::FLOG2,  MVT::f64, Expand);
+  setOperationAction(ISD::FLOG10, MVT::f64, Expand);
+  setOperationAction(ISD::FEXP ,  MVT::f64, Expand);
+  setOperationAction(ISD::FEXP2,  MVT::f64, Expand);
+  setOperationAction(ISD::FFLOOR, MVT::f64, Expand);
+  setOperationAction(ISD::FNEARBYINT, MVT::f64, Expand);
+  setOperationAction(ISD::FCEIL,  MVT::f64, Expand);
+  setOperationAction(ISD::FRINT,  MVT::f64, Expand);
+  setOperationAction(ISD::FTRUNC, MVT::f64, Expand);
+  setOperationAction(ISD::FLOG ,  MVT::f32, Expand);
+  setOperationAction(ISD::FLOG2,  MVT::f32, Expand);
+  setOperationAction(ISD::FLOG10, MVT::f32, Expand);
+  setOperationAction(ISD::FEXP ,  MVT::f32, Expand);
+  setOperationAction(ISD::FEXP2,  MVT::f32, Expand);
+  setOperationAction(ISD::FFLOOR, MVT::f32, Expand);
+  setOperationAction(ISD::FNEARBYINT, MVT::f32, Expand);
+  setOperationAction(ISD::FCEIL,  MVT::f32, Expand);
+  setOperationAction(ISD::FRINT,  MVT::f32, Expand);
+  setOperationAction(ISD::FTRUNC, MVT::f32, Expand);
 
   // Default ISD::TRAP to expand (which turns it into abort).
   setOperationAction(ISD::TRAP, MVT::Other, Expand);

Modified: llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp?rev=146171&r1=146170&r2=146171&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp Thu Dec  8 13:32:14 2011
@@ -103,6 +103,13 @@
   // from FP_ROUND:  that rounds to nearest, this rounds to zero.
   setOperationAction(ISD::FP_ROUND_INREG, MVT::ppcf128, Custom);
 
+  // We do not currently implment this libm ops for PowerPC.
+  setOperationAction(ISD::FFLOOR, MVT::ppcf128, Expand);
+  setOperationAction(ISD::FCEIL,  MVT::ppcf128, Expand);
+  setOperationAction(ISD::FTRUNC, MVT::ppcf128, Expand);
+  setOperationAction(ISD::FRINT,  MVT::ppcf128, Expand);
+  setOperationAction(ISD::FNEARBYINT, MVT::ppcf128, Expand);
+
   // PowerPC has no SREM/UREM instructions
   setOperationAction(ISD::SREM, MVT::i32, Expand);
   setOperationAction(ISD::UREM, MVT::i32, Expand);

Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=146171&r1=146170&r2=146171&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Thu Dec  8 13:32:14 2011
@@ -663,6 +663,11 @@
       setOperationAction(ISD::FCOS           , MVT::f80  , Expand);
     }
 
+    setOperationAction(ISD::FFLOOR, MVT::f80, Expand);
+    setOperationAction(ISD::FCEIL,  MVT::f80, Expand);
+    setOperationAction(ISD::FTRUNC, MVT::f80, Expand);
+    setOperationAction(ISD::FRINT,  MVT::f80, Expand);
+    setOperationAction(ISD::FNEARBYINT, MVT::f80, Expand);
     setOperationAction(ISD::FMA, MVT::f80, Expand);
   }
 

Modified: llvm/trunk/test/CodeGen/Thumb2/thumb2-cbnz.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb2/thumb2-cbnz.ll?rev=146171&r1=146170&r2=146171&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Thumb2/thumb2-cbnz.ll (original)
+++ llvm/trunk/test/CodeGen/Thumb2/thumb2-cbnz.ll Thu Dec  8 13:32:14 2011
@@ -1,7 +1,7 @@
 ; RUN: llc < %s -mtriple=thumbv7-apple-darwin -mcpu=cortex-a8 | FileCheck %s
 ; rdar://7354379
 
-declare double @floor(double) nounwind readnone
+declare double @foo(double) nounwind readnone
 
 define void @t(i32 %c, double %b) {
 entry:
@@ -26,7 +26,7 @@
 ; CHECK:      cmp	r0, #0
 ; CHECK:      cmp	r0, #0
 ; CHECK-NEXT:      cbnz
-  %0 = tail call  double @floor(double %b) nounwind readnone ;  [#uses=0]
+  %0 = tail call  double @foo(double %b) nounwind readnone ;  [#uses=0]
   br label %bb11
 
 bb11:                                             ; preds = %bb9, %bb7



From eugeni.stepanov at gmail.com  Thu Dec  8 13:51:03 2011
From: eugeni.stepanov at gmail.com (Evgeniy Stepanov)
Date: Thu, 8 Dec 2011 23:51:03 +0400
Subject: [llvm-commits] [PATCH] ASan/Android: fall back to the system
 allocator for unexpected deallocations
In-Reply-To: 
References: 
	
Message-ID: 

AFAIK, MacOSX does something like this already. We could speed up
__asan_mz_size significantly and make it lock-free.

I don't see a way to call __asan_init much earlier, other than
patching the linker or something like that.

On Thu, Dec 8, 2011 at 11:02 PM, Kostya Serebryany  wrote:
> Having such patch, even under ifdef ANDROID, will be very sad.
> It makes free() much slower (linear time + lock, instead of constant time
> w/o lock).
> We need to figure out some other way (e.g. try to run __asan_init() even
> earlier).
>
> --kcc
>
>
> On Thu, Dec 8, 2011 at 6:38 AM, Evgeniy Stepanov 
> wrote:
>>
>> On Android, allocations from static constructors of uninstrumented
>> libraries occur before we have a chance to replace the allocator. This
>> patch helps avoid crashing on the matching deallocations.
>
>

From baldrick at free.fr  Thu Dec  8 13:55:58 2011
From: baldrick at free.fr (Duncan Sands)
Date: Thu, 08 Dec 2011 20:55:58 +0100
Subject: [llvm-commits] [llvm] r146171 - in /llvm/trunk:
 lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
 lib/CodeGen/SelectionDAG/TargetLowering.cpp
 lib/Target/PowerPC/PPCISelLowering.cpp lib/Target/X86/X86ISelLowering.cpp
 test/CodeGen/Thumb2/thumb2-cbnz.ll
In-Reply-To: <20111208193214.9AF602A6C12C@llvm.org>
References: <20111208193214.9AF602A6C12C@llvm.org>
Message-ID: <4EE1164E.5000300@free.fr>

Hi Owen,

> Teach SelectionDAG to match more calls to libm functions onto existing SDNodes.  Mark these nodes as illegal by default, unless the target declares otherwise.

shouldn't this logic query TargetLibraryInfo before turning things into
SDNodes?  By making such a node you are assuming that a certain function
name like "floor" actually refers to the standard floor library function.
This is not always correct which is why TargetLibraryInfo exists...

Ciao, Duncan.

From gohman at apple.com  Thu Dec  8 13:57:31 2011
From: gohman at apple.com (Dan Gohman)
Date: Thu, 08 Dec 2011 11:57:31 -0800
Subject: [llvm-commits] [LLVM, loop-unswitch,
 bugfix for #11429] Wrong behaviour for switches.
In-Reply-To: <4EDF700A.3080605@narod.ru>
References: <4ECF4A5A.9030607@narod.ru> <4ED36D99.1080306@narod.ru>
	<4ED51EEC.6050000@narod.ru> <4ED749D0.8030101@narod.ru>
	<4ED88CDF.2020104@narod.ru>
	
	<4EDCC136.1040903@narod.ru>
	<566DBA1B-7099-44E0-B2EB-3413A054F5E3@apple.com>
	<4EDF700A.3080605@narod.ru>
Message-ID: <9F9EFCC2-3F32-49F8-97D6-B8BAC580B6F7@apple.com>


On Dec 7, 2011, at 5:54 AM, Stepan Dyatkovskiy wrote:

> Dan Gohman wrote:
> 
>> This sounds good. How sure are you that the existing size heuristics
>> are actually kicking in for the new unrollings? I don't have a reason
>> to suspect a bug, other than that you're asking code to work in cases
>> that it hasn't before.
> 
> The main reason to suspect a bug is that the pass doesn't work as it was planned initially. I made this conclusion after reading the code and its comments. Especially this ones (LoopUnswitch.cpp, string #277):
>        // FIXME: this should choose the most expensive case!
>        // FIXME: scan for a case with a non-critical edge?
> Programmer placed the stub by now:
> 	Constant *UnswitchVal = SI->getCaseValue(1);
> 
> Probably he missed one thing. Since we selected 1-st case always, all other cases will never unswitched. But there is no comments about it. This "feature" looks unplanned. If not - ok, it is not a bug then. I proposed to insert additional comments though.
> 
> Size heuristics currently analyses the size of loop to be unswitched. If number of instructions, or number of BBs exceeds some threshold, then the loop will skipped. We can also control the number cases to be unswitched.

Oh, I don't doubt it may a bug. And there's no master plan behind
non-trivial loop unswitching for switches. My point was just that
it's been the way it is for a long time, and possibly other things
have become accustomed to it, or accidentally reliant on it,
working that way.

> 
>> Each unswitched case has the potential to increase performance,
>> if conditions are favorable. But if code size is increased, there's
>> also the possibility of decreased performance.
> 
> Before unswitchment, loop executes switch N times. The switch is lowered to several "icmp" checks (let it be "n"). Depending on lowering algorithm selected the "n" is either linear or logarithmic function on cases number ( n=k*num_cases or n=k*log(num_cases) ). Summary we have N*n "icmp" checks.
> 
> After unswitchment all checks will moved out of loop. And we got 1*n_us "icmp" checks in this case. But the "n_us" is always linear after unswitchment. So if (1*n_us < N*n) then performance will increased. Else - it will decreased.

On most architectures, those checks will usually be predictable -- the
conditions are loop-invariant after all -- and thus fairly cheap, depending
on what else is in the loop. But this isn't important here.

> 
> > If you can confirm
>> that that's working as expected, it should be fine.
> 
> Did you mean the regression tests? If yes - they are attached in initial post. These tests checks that all working as expected for loop with single switch instruction and for loop with two switches.
> 
> In my patch I fixed the stub described above. I also can improve the size heuristics if you need.


I just meant that it would be good to have testcases in which the code
size heuristic actually has to kick in and prevent it from unswitching
out of control.

Also, if you could do a rough check of code size on some general real-world
application code, that would be good too.

With these precautions, I think the patch is fine.

Dan


From resistor at mac.com  Thu Dec  8 14:13:10 2011
From: resistor at mac.com (Owen Anderson)
Date: Thu, 08 Dec 2011 12:13:10 -0800
Subject: [llvm-commits] [llvm] r146171 - in /llvm/trunk:
 lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
 lib/CodeGen/SelectionDAG/TargetLowering.cpp
 lib/Target/PowerPC/PPCISelLowering.cpp lib/Target/X86/X86ISelLowering.cpp
 test/CodeGen/Thumb2/thumb2-cbnz.ll
In-Reply-To: <4EE1164E.5000300@free.fr>
References: <20111208193214.9AF602A6C12C@llvm.org> <4EE1164E.5000300@free.fr>
Message-ID: <1A1F4984-8D35-4E8D-9236-F812A6303769@mac.com>


On Dec 8, 2011, at 11:55 AM, Duncan Sands wrote:

> Hi Owen,
> 
>> Teach SelectionDAG to match more calls to libm functions onto existing SDNodes.  Mark these nodes as illegal by default, unless the target declares otherwise.
> 
> shouldn't this logic query TargetLibraryInfo before turning things into
> SDNodes?  By making such a node you are assuming that a certain function
> name like "floor" actually refers to the standard floor library function.
> This is not always correct which is why TargetLibraryInfo exists?

Probably. :-)

This whole section of SelectionDAGBuilder probably needs to be guarded against -fno-builtins.  It matches pow(), sin(), cos() etc. too, which also shouldn't become SDNodes with -fno-builtins.

--Owen

From ahatanaka at mips.com  Thu Dec  8 14:34:32 2011
From: ahatanaka at mips.com (Akira Hatanaka)
Date: Thu, 08 Dec 2011 20:34:32 -0000
Subject: [llvm-commits] [llvm] r146175 - in /llvm/trunk/lib/Target/Mips:
 Mips64InstrInfo.td MipsISelDAGToDAG.cpp MipsISelLowering.cpp
 MipsISelLowering.h MipsInstrInfo.td
Message-ID: <20111208203432.AE1692A6C12C@llvm.org>

Author: ahatanak
Date: Thu Dec  8 14:34:32 2011
New Revision: 146175

URL: http://llvm.org/viewvc/llvm-project?rev=146175&view=rev
Log:
Implement 64-bit support for thread local storage handling.

- Modify lowering of global TLS address nodes.
- Modify isel of ThreadPointer.
- Wrap target global TLS address nodes that are operands of loads with WrapperPIC. 
- Remove Mips-specific DAG nodes TlsGd, TprelHi and TprelLo, which can be
  substituted with other existing nodes.


Modified:
    llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td
    llvm/trunk/lib/Target/Mips/MipsISelDAGToDAG.cpp
    llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp
    llvm/trunk/lib/Target/Mips/MipsISelLowering.h
    llvm/trunk/lib/Target/Mips/MipsInstrInfo.td

Modified: llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td?rev=146175&r1=146174&r2=146175&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td (original)
+++ llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td Thu Dec  8 14:34:32 2011
@@ -266,11 +266,13 @@
 def : Pat<(MipsHi tblockaddress:$in), (LUi64 tblockaddress:$in)>;
 def : Pat<(MipsHi tjumptable:$in), (LUi64 tjumptable:$in)>;
 def : Pat<(MipsHi tconstpool:$in), (LUi64 tconstpool:$in)>;
+def : Pat<(MipsHi tglobaltlsaddr:$in), (LUi64 tglobaltlsaddr:$in)>;
 
 def : Pat<(MipsLo tglobaladdr:$in), (DADDiu ZERO_64, tglobaladdr:$in)>;
 def : Pat<(MipsLo tblockaddress:$in), (DADDiu ZERO_64, tblockaddress:$in)>;
 def : Pat<(MipsLo tjumptable:$in), (DADDiu ZERO_64, tjumptable:$in)>;
 def : Pat<(MipsLo tconstpool:$in), (DADDiu ZERO_64, tconstpool:$in)>;
+def : Pat<(MipsLo tglobaltlsaddr:$in), (DADDiu ZERO_64, tglobaltlsaddr:$in)>;
 
 def : Pat<(add CPU64Regs:$hi, (MipsLo tglobaladdr:$lo)),
           (DADDiu CPU64Regs:$hi, tglobaladdr:$lo)>;
@@ -280,12 +282,15 @@
           (DADDiu CPU64Regs:$hi, tjumptable:$lo)>;
 def : Pat<(add CPU64Regs:$hi, (MipsLo tconstpool:$lo)),
           (DADDiu CPU64Regs:$hi, tconstpool:$lo)>;
+def : Pat<(add CPU64Regs:$hi, (MipsLo tglobaltlsaddr:$lo)),
+          (DADDiu CPU64Regs:$hi, tglobaltlsaddr:$lo)>;
 
 def : WrapperPICPat;
 def : WrapperPICPat;
 def : WrapperPICPat;
 def : WrapperPICPat;
 def : WrapperPICPat;
+def : WrapperPICPat;
 
 defm : BrcondPats;

Modified: llvm/trunk/lib/Target/Mips/MipsISelDAGToDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsISelDAGToDAG.cpp?rev=146175&r1=146174&r2=146175&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsISelDAGToDAG.cpp (original)
+++ llvm/trunk/lib/Target/Mips/MipsISelDAGToDAG.cpp Thu Dec  8 14:34:32 2011
@@ -121,21 +121,16 @@
   }
 
   // on PIC code Load GA
-  if (TM.getRelocationModel() == Reloc::PIC_) {
-    if (Addr.getOpcode() == MipsISD::WrapperPIC) {
-      Base   = CurDAG->getRegister(GPReg, ValTy);
-      Offset = Addr.getOperand(0);
-      return true;
-    }
-  } else {
+  if (Addr.getOpcode() == MipsISD::WrapperPIC) {
+    Base   = CurDAG->getRegister(GPReg, ValTy);
+    Offset = Addr.getOperand(0);
+    return true;
+  }
+
+  if (TM.getRelocationModel() != Reloc::PIC_) {
     if ((Addr.getOpcode() == ISD::TargetExternalSymbol ||
         Addr.getOpcode() == ISD::TargetGlobalAddress))
       return false;
-    else if (Addr.getOpcode() == ISD::TargetGlobalTLSAddress) {
-      Base   = CurDAG->getRegister(GPReg, ValTy);
-      Offset = Addr;
-      return true;
-    }
   }
 
   // Addresses of the form FI+const or FI|const
@@ -309,13 +304,24 @@
     }
 
     case MipsISD::ThreadPointer: {
-      unsigned SrcReg = Mips::HWR29;
-      unsigned DestReg = Mips::V1;
-      SDNode *Rdhwr = CurDAG->getMachineNode(Mips::RDHWR, Node->getDebugLoc(),
-          Node->getValueType(0), CurDAG->getRegister(SrcReg, MVT::i32));
+      EVT PtrVT = TLI.getPointerTy();
+      unsigned RdhwrOpc, SrcReg, DestReg;
+
+      if (PtrVT == MVT::i32) {
+        RdhwrOpc = Mips::RDHWR;
+        SrcReg = Mips::HWR29;
+        DestReg = Mips::V1;
+      } else {
+        RdhwrOpc = Mips::RDHWR64;
+        SrcReg = Mips::HWR29_64;
+        DestReg = Mips::V1_64;
+      }
+      
+      SDNode *Rdhwr = CurDAG->getMachineNode(RdhwrOpc, Node->getDebugLoc(),
+          Node->getValueType(0), CurDAG->getRegister(SrcReg, PtrVT));
       SDValue Chain = CurDAG->getCopyToReg(CurDAG->getEntryNode(), dl, DestReg,
           SDValue(Rdhwr, 0));
-      SDValue ResNode = CurDAG->getCopyFromReg(Chain, dl, DestReg, MVT::i32);
+      SDValue ResNode = CurDAG->getCopyFromReg(Chain, dl, DestReg, PtrVT);
       ReplaceUses(SDValue(Node, 0), ResNode);
       return ResNode.getNode();
     }

Modified: llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp?rev=146175&r1=146174&r2=146175&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp Thu Dec  8 14:34:32 2011
@@ -54,9 +54,6 @@
   case MipsISD::Hi:                return "MipsISD::Hi";
   case MipsISD::Lo:                return "MipsISD::Lo";
   case MipsISD::GPRel:             return "MipsISD::GPRel";
-  case MipsISD::TlsGd:             return "MipsISD::TlsGd";
-  case MipsISD::TprelHi:           return "MipsISD::TprelHi";
-  case MipsISD::TprelLo:           return "MipsISD::TprelLo";
   case MipsISD::ThreadPointer:     return "MipsISD::ThreadPointer";
   case MipsISD::Ret:               return "MipsISD::Ret";
   case MipsISD::FPBrcond:          return "MipsISD::FPBrcond";
@@ -129,6 +126,7 @@
   setOperationAction(ISD::BlockAddress,       MVT::i32,   Custom);
   setOperationAction(ISD::BlockAddress,       MVT::i64,   Custom);
   setOperationAction(ISD::GlobalTLSAddress,   MVT::i32,   Custom);
+  setOperationAction(ISD::GlobalTLSAddress,   MVT::i64,   Custom);
   setOperationAction(ISD::JumpTable,          MVT::i32,   Custom);
   setOperationAction(ISD::JumpTable,          MVT::i64,   Custom);
   setOperationAction(ISD::ConstantPool,       MVT::i32,   Custom);
@@ -1549,23 +1547,22 @@
 
   if (getTargetMachine().getRelocationModel() == Reloc::PIC_) {
     // General Dynamic TLS Model
-    SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, MVT::i32,
+    SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, PtrVT,
                                              0, MipsII::MO_TLSGD);
-    SDValue Tlsgd = DAG.getNode(MipsISD::TlsGd, dl, MVT::i32, TGA);
-    SDValue GP = DAG.getRegister(Mips::GP, MVT::i32);
-    SDValue Argument = DAG.getNode(ISD::ADD, dl, MVT::i32, GP, Tlsgd);
+    SDValue Argument = DAG.getNode(MipsISD::WrapperPIC, dl, PtrVT, TGA);
 
     ArgListTy Args;
     ArgListEntry Entry;
     Entry.Node = Argument;
-    Entry.Ty = (Type *) Type::getInt32Ty(*DAG.getContext());
+    unsigned PtrSize = PtrVT.getSizeInBits();
+    IntegerType *PtrTy = Type::getIntNTy(*DAG.getContext(), PtrSize);
+    Entry.Ty = PtrTy;
     Args.push_back(Entry);
     std::pair CallResult =
-        LowerCallTo(DAG.getEntryNode(),
-                    (Type *) Type::getInt32Ty(*DAG.getContext()),
-                    false, false, false, false, 0, CallingConv::C, false, true,
-                    DAG.getExternalSymbol("__tls_get_addr", PtrVT), Args, DAG,
-                    dl);
+      LowerCallTo(DAG.getEntryNode(), PtrTy,
+                  false, false, false, false, 0, CallingConv::C, false, true,
+                  DAG.getExternalSymbol("__tls_get_addr", PtrVT), Args, DAG,
+                  dl);
 
     return CallResult.first;
   }
@@ -1573,21 +1570,21 @@
   SDValue Offset;
   if (GV->isDeclaration()) {
     // Initial Exec TLS Model
-    SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, MVT::i32, 0,
+    SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
                                              MipsII::MO_GOTTPREL);
-    Offset = DAG.getLoad(MVT::i32, dl,
+    TGA = DAG.getNode(MipsISD::WrapperPIC, dl, PtrVT, TGA);
+    Offset = DAG.getLoad(PtrVT, dl,
                          DAG.getEntryNode(), TGA, MachinePointerInfo(),
                          false, false, false, 0);
   } else {
     // Local Exec TLS Model
-    SDVTList VTs = DAG.getVTList(MVT::i32);
-    SDValue TGAHi = DAG.getTargetGlobalAddress(GV, dl, MVT::i32, 0,
+    SDValue TGAHi = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
                                                MipsII::MO_TPREL_HI);
-    SDValue TGALo = DAG.getTargetGlobalAddress(GV, dl, MVT::i32, 0,
+    SDValue TGALo = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
                                                MipsII::MO_TPREL_LO);
-    SDValue Hi = DAG.getNode(MipsISD::TprelHi, dl, VTs, &TGAHi, 1);
-    SDValue Lo = DAG.getNode(MipsISD::TprelLo, dl, MVT::i32, TGALo);
-    Offset = DAG.getNode(ISD::ADD, dl, MVT::i32, Hi, Lo);
+    SDValue Hi = DAG.getNode(MipsISD::Hi, dl, PtrVT, TGAHi);
+    SDValue Lo = DAG.getNode(MipsISD::Lo, dl, PtrVT, TGALo);
+    Offset = DAG.getNode(ISD::ADD, dl, PtrVT, Hi, Lo);
   }
 
   SDValue ThreadPointer = DAG.getNode(MipsISD::ThreadPointer, dl, PtrVT);

Modified: llvm/trunk/lib/Target/Mips/MipsISelLowering.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsISelLowering.h?rev=146175&r1=146174&r2=146175&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsISelLowering.h (original)
+++ llvm/trunk/lib/Target/Mips/MipsISelLowering.h Thu Dec  8 14:34:32 2011
@@ -40,13 +40,6 @@
       // Handle gp_rel (small data/bss sections) relocation.
       GPRel,
 
-      // General Dynamic TLS
-      TlsGd,
-
-      // Local Exec TLS
-      TprelHi,
-      TprelLo,
-
       // Thread Pointer
       ThreadPointer,
 

Modified: llvm/trunk/lib/Target/Mips/MipsInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsInstrInfo.td?rev=146175&r1=146174&r2=146175&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsInstrInfo.td (original)
+++ llvm/trunk/lib/Target/Mips/MipsInstrInfo.td Thu Dec  8 14:34:32 2011
@@ -942,11 +942,13 @@
 def : Pat<(MipsHi tblockaddress:$in), (LUi tblockaddress:$in)>;
 def : Pat<(MipsHi tjumptable:$in), (LUi tjumptable:$in)>;
 def : Pat<(MipsHi tconstpool:$in), (LUi tconstpool:$in)>;
+def : Pat<(MipsHi tglobaltlsaddr:$in), (LUi tglobaltlsaddr:$in)>;
 
 def : Pat<(MipsLo tglobaladdr:$in), (ADDiu ZERO, tglobaladdr:$in)>;
 def : Pat<(MipsLo tblockaddress:$in), (ADDiu ZERO, tblockaddress:$in)>;
 def : Pat<(MipsLo tjumptable:$in), (ADDiu ZERO, tjumptable:$in)>;
 def : Pat<(MipsLo tconstpool:$in), (ADDiu ZERO, tconstpool:$in)>;
+def : Pat<(MipsLo tglobaltlsaddr:$in), (ADDiu ZERO, tglobaltlsaddr:$in)>;
 
 def : Pat<(add CPURegs:$hi, (MipsLo tglobaladdr:$lo)),
           (ADDiu CPURegs:$hi, tglobaladdr:$lo)>;
@@ -956,6 +958,8 @@
           (ADDiu CPURegs:$hi, tjumptable:$lo)>;
 def : Pat<(add CPURegs:$hi, (MipsLo tconstpool:$lo)),
           (ADDiu CPURegs:$hi, tconstpool:$lo)>;
+def : Pat<(add CPURegs:$hi, (MipsLo tglobaltlsaddr:$lo)),
+          (ADDiu CPURegs:$hi, tglobaltlsaddr:$lo)>;
 
 // gp_rel relocs
 def : Pat<(add CPURegs:$gp, (MipsGPRel tglobaladdr:$in)),
@@ -963,16 +967,6 @@
 def : Pat<(add CPURegs:$gp, (MipsGPRel tconstpool:$in)),
           (ADDiu CPURegs:$gp, tconstpool:$in)>;
 
-// tlsgd
-def : Pat<(add CPURegs:$gp, (MipsTlsGd tglobaltlsaddr:$in)),
-          (ADDiu CPURegs:$gp, tglobaltlsaddr:$in)>;
-
-// tprel hi/lo
-def : Pat<(MipsTprelHi tglobaltlsaddr:$in), (LUi tglobaltlsaddr:$in)>;
-def : Pat<(MipsTprelLo tglobaltlsaddr:$in), (ADDiu ZERO, tglobaltlsaddr:$in)>;
-def : Pat<(add CPURegs:$hi, (MipsTprelLo tglobaltlsaddr:$lo)),
-          (ADDiu CPURegs:$hi, tglobaltlsaddr:$lo)>;
-
 // wrapper_pic
 class WrapperPICPat:
       Pat<(MipsWrapperPIC node:$in),
@@ -983,6 +977,7 @@
 def : WrapperPICPat;
 def : WrapperPICPat;
 def : WrapperPICPat;
+def : WrapperPICPat;
 
 // Mips does not have "not", so we expand our way
 def : Pat<(not CPURegs:$in),



From grosbach at apple.com  Thu Dec  8 14:42:35 2011
From: grosbach at apple.com (Jim Grosbach)
Date: Thu, 08 Dec 2011 20:42:35 -0000
Subject: [llvm-commits] [llvm] r146177 - in /llvm/trunk:
 lib/Target/ARM/ARMInstrNEON.td test/MC/ARM/neon-mul-encoding.s
Message-ID: <20111208204235.DCCEA2A6C12C@llvm.org>

Author: grosbach
Date: Thu Dec  8 14:42:35 2011
New Revision: 146177

URL: http://llvm.org/viewvc/llvm-project?rev=146177&view=rev
Log:
ARM a few more VMUL implied destination operand form aliases.

Modified:
    llvm/trunk/lib/Target/ARM/ARMInstrNEON.td
    llvm/trunk/test/MC/ARM/neon-mul-encoding.s

Modified: llvm/trunk/lib/Target/ARM/ARMInstrNEON.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrNEON.td?rev=146177&r1=146176&r2=146177&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrNEON.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrNEON.td Thu Dec  8 14:42:35 2011
@@ -5376,6 +5376,24 @@
                          (VORRq QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>;
 
 // VMUL two-operand aliases.
+def : NEONInstAlias<"vmul${p}.p8 $Qdn, $Qm",
+                    (VMULpq QPR:$Qdn, QPR:$Qdn, QPR:$Qm, pred:$p)>;
+def : NEONInstAlias<"vmul${p}.i8 $Qdn, $Qm",
+                    (VMULv16i8 QPR:$Qdn, QPR:$Qdn, QPR:$Qm, pred:$p)>;
+def : NEONInstAlias<"vmul${p}.i16 $Qdn, $Qm",
+                    (VMULv8i16 QPR:$Qdn, QPR:$Qdn, QPR:$Qm, pred:$p)>;
+def : NEONInstAlias<"vmul${p}.i32 $Qdn, $Qm",
+                    (VMULv4i32 QPR:$Qdn, QPR:$Qdn, QPR:$Qm, pred:$p)>;
+
+def : NEONInstAlias<"vmul${p}.p8 $Ddn, $Dm",
+                    (VMULpd DPR:$Ddn, DPR:$Ddn, DPR:$Dm, pred:$p)>;
+def : NEONInstAlias<"vmul${p}.i8 $Ddn, $Dm",
+                    (VMULv8i8 DPR:$Ddn, DPR:$Ddn, DPR:$Dm, pred:$p)>;
+def : NEONInstAlias<"vmul${p}.i16 $Ddn, $Dm",
+                    (VMULv4i16 DPR:$Ddn, DPR:$Ddn, DPR:$Dm, pred:$p)>;
+def : NEONInstAlias<"vmul${p}.i32 $Ddn, $Dm",
+                    (VMULv2i32 DPR:$Ddn, DPR:$Ddn, DPR:$Dm, pred:$p)>;
+
 def : NEONInstAlias<"vmul${p}.f32 $Qdn, $Qm",
                     (VMULfq QPR:$Qdn, QPR:$Qdn, QPR:$Qm, pred:$p)>;
 def : NEONInstAlias<"vmul${p}.f32 $Ddn, $Dm",

Modified: llvm/trunk/test/MC/ARM/neon-mul-encoding.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/neon-mul-encoding.s?rev=146177&r1=146176&r2=146177&view=diff
==============================================================================
--- llvm/trunk/test/MC/ARM/neon-mul-encoding.s (original)
+++ llvm/trunk/test/MC/ARM/neon-mul-encoding.s Thu Dec  8 14:42:35 2011
@@ -1,6 +1,5 @@
 @ RUN: llvm-mc -mcpu=cortex-a8 -triple arm-unknown-unknown -show-encoding < %s | FileCheck %s
 
-
 	vmul.i8	d16, d16, d17
 	vmul.i16	d16, d16, d17
 	vmul.i32	d16, d16, d17
@@ -13,6 +12,17 @@
 	vmul.p8	q8, q8, q9
 	vmul.i16	d18, d8, d0[3]
 
+	vmul.i8	d16, d17
+	vmul.i16	d16, d17
+	vmul.i32	d16, d17
+	vmul.f32	d16, d17
+	vmul.i8	q8, q9
+	vmul.i16	q8, q9
+	vmul.i32	q8, q9
+	vmul.f32	q8, q9
+	vmul.p8	d16, d17
+	vmul.p8	q8, q9
+
 @ CHECK: vmul.i8	d16, d16, d17   @ encoding: [0xb1,0x09,0x40,0xf2]
 @ CHECK: vmul.i16	d16, d16, d17   @ encoding: [0xb1,0x09,0x50,0xf2]
 @ CHECK: vmul.i32	d16, d16, d17   @ encoding: [0xb1,0x09,0x60,0xf2]
@@ -25,6 +35,17 @@
 @ CHECK: vmul.p8	q8, q8, q9      @ encoding: [0xf2,0x09,0x40,0xf3]
 @ CHECK: vmul.i16	d18, d8, d0[3]  @ encoding: [0x68,0x28,0xd8,0xf2]
 
+@ CHECK: vmul.i8	d16, d16, d17   @ encoding: [0xb1,0x09,0x40,0xf2]
+@ CHECK: vmul.i16	d16, d16, d17   @ encoding: [0xb1,0x09,0x50,0xf2]
+@ CHECK: vmul.i32	d16, d16, d17   @ encoding: [0xb1,0x09,0x60,0xf2]
+@ CHECK: vmul.f32	d16, d16, d17   @ encoding: [0xb1,0x0d,0x40,0xf3]
+@ CHECK: vmul.i8	q8, q8, q9      @ encoding: [0xf2,0x09,0x40,0xf2]
+@ CHECK: vmul.i16	q8, q8, q9      @ encoding: [0xf2,0x09,0x50,0xf2]
+@ CHECK: vmul.i32	q8, q8, q9      @ encoding: [0xf2,0x09,0x60,0xf2]
+@ CHECK: vmul.f32	q8, q8, q9      @ encoding: [0xf2,0x0d,0x40,0xf3]
+@ CHECK: vmul.p8	d16, d16, d17   @ encoding: [0xb1,0x09,0x40,0xf3]
+@ CHECK: vmul.p8	q8, q8, q9      @ encoding: [0xf2,0x09,0x40,0xf3]
+
 
 	vqdmulh.s16	d16, d16, d17
 	vqdmulh.s32	d16, d16, d17



From jan_sjodin at yahoo.com  Thu Dec  8 14:49:10 2011
From: jan_sjodin at yahoo.com (Jan Sjodin)
Date: Thu, 8 Dec 2011 12:49:10 -0800 (PST)
Subject: [llvm-commits] XOP encoding patch
Message-ID: <1323377350.13027.YahooMailNeo@web161504.mail.bf1.yahoo.com>

This patch handles the encoding of XOP instructions. I included one instruction for each kind including a test.

- Jan
-------------- next part --------------
An HTML attachment was scrubbed...
URL: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20111208/11421e24/attachment.html 
-------------- next part --------------
A non-text attachment was scrubbed...
Name: 0058_xop_encoding.patch
Type: application/octet-stream
Size: 21146 bytes
Desc: not available
Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20111208/11421e24/attachment.obj 

From grosbach at apple.com  Thu Dec  8 14:49:43 2011
From: grosbach at apple.com (Jim Grosbach)
Date: Thu, 08 Dec 2011 20:49:43 -0000
Subject: [llvm-commits] [llvm] r146179 - in /llvm/trunk:
 lib/Target/ARM/ARMInstrNEON.td test/MC/ARM/neon-add-encoding.s
Message-ID: <20111208204943.9F1D52A6C12C@llvm.org>

Author: grosbach
Date: Thu Dec  8 14:49:43 2011
New Revision: 146179

URL: http://llvm.org/viewvc/llvm-project?rev=146179&view=rev
Log:
ARM VQADD implied destination operand form aliases.

Modified:
    llvm/trunk/lib/Target/ARM/ARMInstrNEON.td
    llvm/trunk/test/MC/ARM/neon-add-encoding.s

Modified: llvm/trunk/lib/Target/ARM/ARMInstrNEON.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrNEON.td?rev=146179&r1=146178&r2=146179&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrNEON.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrNEON.td Thu Dec  8 14:49:43 2011
@@ -5420,6 +5420,41 @@
                     (VMULslfq QPR:$Qdn, QPR:$Qdn, DPR_VFP2:$Dm,
                               VectorIndex32:$lane, pred:$p)>;
 
+// VQADD (register) two-operand aliases.
+def : NEONInstAlias<"vqadd${p}.s8 $Vdn, $Vm",
+                    (VQADDsv8i8 DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;
+def : NEONInstAlias<"vqadd${p}.s16 $Vdn, $Vm",
+                    (VQADDsv4i16 DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;
+def : NEONInstAlias<"vqadd${p}.s32 $Vdn, $Vm",
+                    (VQADDsv2i32 DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;
+def : NEONInstAlias<"vqadd${p}.s64 $Vdn, $Vm",
+                    (VQADDsv1i64 DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;
+def : NEONInstAlias<"vqadd${p}.u8 $Vdn, $Vm",
+                    (VQADDuv8i8 DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;
+def : NEONInstAlias<"vqadd${p}.u16 $Vdn, $Vm",
+                    (VQADDuv4i16 DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;
+def : NEONInstAlias<"vqadd${p}.u32 $Vdn, $Vm",
+                    (VQADDuv2i32 DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;
+def : NEONInstAlias<"vqadd${p}.u64 $Vdn, $Vm",
+                    (VQADDuv1i64 DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;
+
+def : NEONInstAlias<"vqadd${p}.s8 $Vdn, $Vm",
+                    (VQADDsv16i8 QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>;
+def : NEONInstAlias<"vqadd${p}.s16 $Vdn, $Vm",
+                    (VQADDsv8i16 QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>;
+def : NEONInstAlias<"vqadd${p}.s32 $Vdn, $Vm",
+                    (VQADDsv4i32 QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>;
+def : NEONInstAlias<"vqadd${p}.s64 $Vdn, $Vm",
+                    (VQADDsv2i64 QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>;
+def : NEONInstAlias<"vqadd${p}.u8 $Vdn, $Vm",
+                    (VQADDuv16i8 QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>;
+def : NEONInstAlias<"vqadd${p}.u16 $Vdn, $Vm",
+                    (VQADDuv8i16 QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>;
+def : NEONInstAlias<"vqadd${p}.u32 $Vdn, $Vm",
+                    (VQADDuv4i32 QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>;
+def : NEONInstAlias<"vqadd${p}.u64 $Vdn, $Vm",
+                    (VQADDuv2i64 QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>;
+
 // VSHL (immediate) two-operand aliases.
 def : NEONInstAlias<"vshl${p}.i8 $Vdn, $imm",
                     (VSHLiv8i8 DPR:$Vdn, DPR:$Vdn, imm0_7:$imm, pred:$p)>;

Modified: llvm/trunk/test/MC/ARM/neon-add-encoding.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/neon-add-encoding.s?rev=146179&r1=146178&r2=146179&view=diff
==============================================================================
--- llvm/trunk/test/MC/ARM/neon-add-encoding.s (original)
+++ llvm/trunk/test/MC/ARM/neon-add-encoding.s Thu Dec  8 14:49:43 2011
@@ -90,39 +90,81 @@
 @ CHECK: vrhadd.u32	q8, q8, q9      @ encoding: [0xe2,0x01,0x60,0xf3]
 	vrhadd.u32	q8, q8, q9
 
-@ CHECK: vqadd.s8	d16, d16, d17   @ encoding: [0xb1,0x00,0x40,0xf2]
 	vqadd.s8	d16, d16, d17
-@ CHECK: vqadd.s16	d16, d16, d17   @ encoding: [0xb1,0x00,0x50,0xf2]
 	vqadd.s16	d16, d16, d17
-@ CHECK: vqadd.s32	d16, d16, d17   @ encoding: [0xb1,0x00,0x60,0xf2]
 	vqadd.s32	d16, d16, d17
-@ CHECK: vqadd.s64	d16, d16, d17   @ encoding: [0xb1,0x00,0x70,0xf2]
 	vqadd.s64	d16, d16, d17
-@ CHECK: vqadd.u8	d16, d16, d17   @ encoding: [0xb1,0x00,0x40,0xf3]
 	vqadd.u8	d16, d16, d17
-@ CHECK: vqadd.u16	d16, d16, d17   @ encoding: [0xb1,0x00,0x50,0xf3]
 	vqadd.u16	d16, d16, d17
-@ CHECK: vqadd.u32	d16, d16, d17   @ encoding: [0xb1,0x00,0x60,0xf3]
 	vqadd.u32	d16, d16, d17
-@ CHECK: vqadd.u64	d16, d16, d17   @ encoding: [0xb1,0x00,0x70,0xf3]
 	vqadd.u64	d16, d16, d17
-@ CHECK: vqadd.s8	q8, q8, q9      @ encoding: [0xf2,0x00,0x40,0xf2]
+
+@ CHECK: vqadd.s8	d16, d16, d17   @ encoding: [0xb1,0x00,0x40,0xf2]
+@ CHECK: vqadd.s16	d16, d16, d17   @ encoding: [0xb1,0x00,0x50,0xf2]
+@ CHECK: vqadd.s32	d16, d16, d17   @ encoding: [0xb1,0x00,0x60,0xf2]
+@ CHECK: vqadd.s64	d16, d16, d17   @ encoding: [0xb1,0x00,0x70,0xf2]
+@ CHECK: vqadd.u8	d16, d16, d17   @ encoding: [0xb1,0x00,0x40,0xf3]
+@ CHECK: vqadd.u16	d16, d16, d17   @ encoding: [0xb1,0x00,0x50,0xf3]
+@ CHECK: vqadd.u32	d16, d16, d17   @ encoding: [0xb1,0x00,0x60,0xf3]
+@ CHECK: vqadd.u64	d16, d16, d17   @ encoding: [0xb1,0x00,0x70,0xf3]
+
 	vqadd.s8	q8, q8, q9
-@ CHECK: vqadd.s16	q8, q8, q9      @ encoding: [0xf2,0x00,0x50,0xf2]
 	vqadd.s16	q8, q8, q9
-@ CHECK: vqadd.s32	q8, q8, q9      @ encoding: [0xf2,0x00,0x60,0xf2]
 	vqadd.s32	q8, q8, q9
-@ CHECK: vqadd.s64	q8, q8, q9      @ encoding: [0xf2,0x00,0x70,0xf2]
 	vqadd.s64	q8, q8, q9
-@ CHECK: vqadd.u8	q8, q8, q9      @ encoding: [0xf2,0x00,0x40,0xf3]
 	vqadd.u8	q8, q8, q9
-@ CHECK: vqadd.u16	q8, q8, q9      @ encoding: [0xf2,0x00,0x50,0xf3]
 	vqadd.u16	q8, q8, q9
-@ CHECK: vqadd.u32	q8, q8, q9      @ encoding: [0xf2,0x00,0x60,0xf3]
 	vqadd.u32	q8, q8, q9
-@ CHECK: vqadd.u64	q8, q8, q9      @ encoding: [0xf2,0x00,0x70,0xf3]
 	vqadd.u64	q8, q8, q9
 
+@ CHECK: vqadd.s8	q8, q8, q9      @ encoding: [0xf2,0x00,0x40,0xf2]
+@ CHECK: vqadd.s16	q8, q8, q9      @ encoding: [0xf2,0x00,0x50,0xf2]
+@ CHECK: vqadd.s32	q8, q8, q9      @ encoding: [0xf2,0x00,0x60,0xf2]
+@ CHECK: vqadd.s64	q8, q8, q9      @ encoding: [0xf2,0x00,0x70,0xf2]
+@ CHECK: vqadd.u8	q8, q8, q9      @ encoding: [0xf2,0x00,0x40,0xf3]
+@ CHECK: vqadd.u16	q8, q8, q9      @ encoding: [0xf2,0x00,0x50,0xf3]
+@ CHECK: vqadd.u32	q8, q8, q9      @ encoding: [0xf2,0x00,0x60,0xf3]
+@ CHECK: vqadd.u64	q8, q8, q9      @ encoding: [0xf2,0x00,0x70,0xf3]
+
+
+@ two-operand variants.
+	vqadd.s8	d16, d17
+	vqadd.s16	d16, d17
+	vqadd.s32	d16, d17
+	vqadd.s64	d16, d17
+	vqadd.u8	d16, d17
+	vqadd.u16	d16, d17
+	vqadd.u32	d16, d17
+	vqadd.u64	d16, d17
+
+@ CHECK: vqadd.s8	d16, d16, d17   @ encoding: [0xb1,0x00,0x40,0xf2]
+@ CHECK: vqadd.s16	d16, d16, d17   @ encoding: [0xb1,0x00,0x50,0xf2]
+@ CHECK: vqadd.s32	d16, d16, d17   @ encoding: [0xb1,0x00,0x60,0xf2]
+@ CHECK: vqadd.s64	d16, d16, d17   @ encoding: [0xb1,0x00,0x70,0xf2]
+@ CHECK: vqadd.u8	d16, d16, d17   @ encoding: [0xb1,0x00,0x40,0xf3]
+@ CHECK: vqadd.u16	d16, d16, d17   @ encoding: [0xb1,0x00,0x50,0xf3]
+@ CHECK: vqadd.u32	d16, d16, d17   @ encoding: [0xb1,0x00,0x60,0xf3]
+@ CHECK: vqadd.u64	d16, d16, d17   @ encoding: [0xb1,0x00,0x70,0xf3]
+
+	vqadd.s8	q8, q9
+	vqadd.s16	q8, q9
+	vqadd.s32	q8, q9
+	vqadd.s64	q8, q9
+	vqadd.u8	q8, q9
+	vqadd.u16	q8, q9
+	vqadd.u32	q8, q9
+	vqadd.u64	q8, q9
+
+@ CHECK: vqadd.s8	q8, q8, q9      @ encoding: [0xf2,0x00,0x40,0xf2]
+@ CHECK: vqadd.s16	q8, q8, q9      @ encoding: [0xf2,0x00,0x50,0xf2]
+@ CHECK: vqadd.s32	q8, q8, q9      @ encoding: [0xf2,0x00,0x60,0xf2]
+@ CHECK: vqadd.s64	q8, q8, q9      @ encoding: [0xf2,0x00,0x70,0xf2]
+@ CHECK: vqadd.u8	q8, q8, q9      @ encoding: [0xf2,0x00,0x40,0xf3]
+@ CHECK: vqadd.u16	q8, q8, q9      @ encoding: [0xf2,0x00,0x50,0xf3]
+@ CHECK: vqadd.u32	q8, q8, q9      @ encoding: [0xf2,0x00,0x60,0xf3]
+@ CHECK: vqadd.u64	q8, q8, q9      @ encoding: [0xf2,0x00,0x70,0xf3]
+
+
 @ CHECK: vaddhn.i16	d16, q8, q9     @ encoding: [0xa2,0x04,0xc0,0xf2]
 	vaddhn.i16	d16, q8, q9
 @ CHECK: vaddhn.i32	d16, q8, q9     @ encoding: [0xa2,0x04,0xd0,0xf2]



From resistor at mac.com  Thu Dec  8 14:51:38 2011
From: resistor at mac.com (Owen Anderson)
Date: Thu, 08 Dec 2011 20:51:38 -0000
Subject: [llvm-commits] [llvm] r146180 -
	/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
Message-ID: <20111208205138.D60AD2A6C12C@llvm.org>

Author: resistor
Date: Thu Dec  8 14:51:38 2011
New Revision: 146180

URL: http://llvm.org/viewvc/llvm-project?rev=146180&view=rev
Log:
Don't explicitly marked libm rounding ops as legal on SSE4.1/AVX.  There don't seem to be patterns for these, so I don't know why they were marked legal in the first place.
Fixes failures caused by r146171.

Modified:
    llvm/trunk/lib/Target/X86/X86ISelLowering.cpp

Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=146180&r1=146179&r2=146180&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Thu Dec  8 14:51:38 2011
@@ -914,17 +914,6 @@
   }
 
   if (Subtarget->hasSSE41orAVX()) {
-    setOperationAction(ISD::FFLOOR,             MVT::f32,   Legal);
-    setOperationAction(ISD::FCEIL,              MVT::f32,   Legal);
-    setOperationAction(ISD::FTRUNC,             MVT::f32,   Legal);
-    setOperationAction(ISD::FRINT,              MVT::f32,   Legal);
-    setOperationAction(ISD::FNEARBYINT,         MVT::f32,   Legal);
-    setOperationAction(ISD::FFLOOR,             MVT::f64,   Legal);
-    setOperationAction(ISD::FCEIL,              MVT::f64,   Legal);
-    setOperationAction(ISD::FTRUNC,             MVT::f64,   Legal);
-    setOperationAction(ISD::FRINT,              MVT::f64,   Legal);
-    setOperationAction(ISD::FNEARBYINT,         MVT::f64,   Legal);
-
     // FIXME: Do we need to handle scalar-to-vector here?
     setOperationAction(ISD::MUL,                MVT::v4i32, Legal);
 



From grosbach at apple.com  Thu Dec  8 14:53:19 2011
From: grosbach at apple.com (Jim Grosbach)
Date: Thu, 08 Dec 2011 20:53:19 -0000
Subject: [llvm-commits] [llvm] r146181 -
	/llvm/trunk/test/MC/ARM/neon-sub-encoding.s
Message-ID: <20111208205320.0433F2A6C12C@llvm.org>

Author: grosbach
Date: Thu Dec  8 14:53:19 2011
New Revision: 146181

URL: http://llvm.org/viewvc/llvm-project?rev=146181&view=rev
Log:
Tidy up a bit.

Modified:
    llvm/trunk/test/MC/ARM/neon-sub-encoding.s

Modified: llvm/trunk/test/MC/ARM/neon-sub-encoding.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/neon-sub-encoding.s?rev=146181&r1=146180&r2=146181&view=diff
==============================================================================
--- llvm/trunk/test/MC/ARM/neon-sub-encoding.s (original)
+++ llvm/trunk/test/MC/ARM/neon-sub-encoding.s Thu Dec  8 14:53:19 2011
@@ -1,26 +1,29 @@
 @ RUN: llvm-mc -mcpu=cortex-a8 -triple arm-unknown-unknown -show-encoding < %s | FileCheck %s
 
-@ CHECK: vsub.i8	d16, d17, d16           @ encoding: [0xa0,0x08,0x41,0xf3]
 	vsub.i8	d16, d17, d16
-@ CHECK: vsub.i16	d16, d17, d16   @ encoding: [0xa0,0x08,0x51,0xf3]
 	vsub.i16	d16, d17, d16
-@ CHECK: vsub.i32	d16, d17, d16   @ encoding: [0xa0,0x08,0x61,0xf3]
 	vsub.i32	d16, d17, d16
-@ CHECK: vsub.i64	d16, d17, d16   @ encoding: [0xa0,0x08,0x71,0xf3]
 	vsub.i64	d16, d17, d16
-@ CHECK: vsub.f32	d16, d16, d17   @ encoding: [0xa1,0x0d,0x60,0xf2]
 	vsub.f32	d16, d16, d17
-@ CHECK: vsub.i8	q8, q8, q9              @ encoding: [0xe2,0x08,0x40,0xf3]
 	vsub.i8	q8, q8, q9
-@ CHECK: vsub.i16	q8, q8, q9      @ encoding: [0xe2,0x08,0x50,0xf3]
 	vsub.i16	q8, q8, q9
-@ CHECK: vsub.i32	q8, q8, q9      @ encoding: [0xe2,0x08,0x60,0xf3]
 	vsub.i32	q8, q8, q9
-@ CHECK: vsub.i64	q8, q8, q9      @ encoding: [0xe2,0x08,0x70,0xf3]
 	vsub.i64	q8, q8, q9
-@ CHECK: vsub.f32	q8, q8, q9      @ encoding: [0xe2,0x0d,0x60,0xf2]
 	vsub.f32	q8, q8, q9
+
+@ CHECK: vsub.i8	d16, d17, d16   @ encoding: [0xa0,0x08,0x41,0xf3]
+@ CHECK: vsub.i16	d16, d17, d16   @ encoding: [0xa0,0x08,0x51,0xf3]
+@ CHECK: vsub.i32	d16, d17, d16   @ encoding: [0xa0,0x08,0x61,0xf3]
+@ CHECK: vsub.i64	d16, d17, d16   @ encoding: [0xa0,0x08,0x71,0xf3]
+@ CHECK: vsub.f32	d16, d16, d17   @ encoding: [0xa1,0x0d,0x60,0xf2]
+@ CHECK: vsub.i8	q8, q8, q9      @ encoding: [0xe2,0x08,0x40,0xf3]
+@ CHECK: vsub.i16	q8, q8, q9      @ encoding: [0xe2,0x08,0x50,0xf3]
+@ CHECK: vsub.i32	q8, q8, q9      @ encoding: [0xe2,0x08,0x60,0xf3]
+@ CHECK: vsub.i64	q8, q8, q9      @ encoding: [0xe2,0x08,0x70,0xf3]
+@ CHECK: vsub.f32	q8, q8, q9      @ encoding: [0xe2,0x0d,0x60,0xf2]
 @ CHECK: vsubl.s8	q8, d17, d16    @ encoding: [0xa0,0x02,0xc1,0xf2]
+
+
 	vsubl.s8	q8, d17, d16
 @ CHECK: vsubl.s16	q8, d17, d16    @ encoding: [0xa0,0x02,0xd1,0xf2]
 	vsubl.s16	q8, d17, d16



From kcc at google.com  Thu Dec  8 14:56:54 2011
From: kcc at google.com (Kostya Serebryany)
Date: Thu, 8 Dec 2011 12:56:54 -0800
Subject: [llvm-commits] [PATCH] ASan/Android: fall back to the system
 allocator for unexpected deallocations
In-Reply-To: 
References: 
	
	
Message-ID: 

On Thu, Dec 8, 2011 at 11:51 AM, Evgeniy Stepanov  wrote:

> AFAIK, MacOSX does something like this already.


Yes, and that is very unfortunate.
Intercepting allocators on mac is much more complicated than on linux.
For Linux, including android, I believe we can do simpler.


> We could speed up
> __asan_mz_size significantly and make it lock-free.
>

Mmm. That'll be non-trivial at least. Especially on 32-bit where we have
scarce address space.
(On 64-bit this can be done by maping a 128G virtual memory chunk and then
allocating only from it).


> I don't see a way to call __asan_init much earlier, other than
> patching the linker or something like that.
>

Why not. having __asan_init be called before everything else is really
important.

--kcc


>
> On Thu, Dec 8, 2011 at 11:02 PM, Kostya Serebryany  wrote:
> > Having such patch, even under ifdef ANDROID, will be very sad.
> > It makes free() much slower (linear time + lock, instead of constant time
> > w/o lock).
> > We need to figure out some other way (e.g. try to run __asan_init() even
> > earlier).
> >
> > --kcc
> >
> >
> > On Thu, Dec 8, 2011 at 6:38 AM, Evgeniy Stepanov <
> eugeni.stepanov at gmail.com>
> > wrote:
> >>
> >> On Android, allocations from static constructors of uninstrumented
> >> libraries occur before we have a chance to replace the allocator. This
> >> patch helps avoid crashing on the matching deallocations.
> >
> >
>
-------------- next part --------------
An HTML attachment was scrubbed...
URL: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20111208/df23545e/attachment-0001.html 

From grosbach at apple.com  Thu Dec  8 14:56:26 2011
From: grosbach at apple.com (Jim Grosbach)
Date: Thu, 08 Dec 2011 20:56:26 -0000
Subject: [llvm-commits] [llvm] r146182 - in /llvm/trunk:
 lib/Target/ARM/ARMInstrNEON.td test/MC/ARM/neon-sub-encoding.s
Message-ID: <20111208205626.76ACE2A6C12C@llvm.org>

Author: grosbach
Date: Thu Dec  8 14:56:26 2011
New Revision: 146182

URL: http://llvm.org/viewvc/llvm-project?rev=146182&view=rev
Log:
ARM VSUB implied destination operand form aliases.

Modified:
    llvm/trunk/lib/Target/ARM/ARMInstrNEON.td
    llvm/trunk/test/MC/ARM/neon-sub-encoding.s

Modified: llvm/trunk/lib/Target/ARM/ARMInstrNEON.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrNEON.td?rev=146182&r1=146181&r2=146182&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrNEON.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrNEON.td Thu Dec  8 14:56:26 2011
@@ -5321,6 +5321,30 @@
 def : NEONInstAlias<"vadd${p}.f32 $Vdn, $Vm",
                     (VADDfq QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>;
 
+// VSUB two-operand aliases.
+def : NEONInstAlias<"vsub${p}.i8 $Vdn, $Vm",
+                    (VSUBv16i8 QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>;
+def : NEONInstAlias<"vsub${p}.i16 $Vdn, $Vm",
+                    (VSUBv8i16 QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>;
+def : NEONInstAlias<"vsub${p}.i32 $Vdn, $Vm",
+                    (VSUBv4i32 QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>;
+def : NEONInstAlias<"vsub${p}.i64 $Vdn, $Vm",
+                    (VSUBv2i64 QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>;
+
+def : NEONInstAlias<"vsub${p}.i8 $Vdn, $Vm",
+                    (VSUBv8i8 DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;
+def : NEONInstAlias<"vsub${p}.i16 $Vdn, $Vm",
+                    (VSUBv4i16 DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;
+def : NEONInstAlias<"vsub${p}.i32 $Vdn, $Vm",
+                    (VSUBv2i32 DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;
+def : NEONInstAlias<"vsub${p}.i64 $Vdn, $Vm",
+                    (VSUBv1i64 DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;
+
+def : NEONInstAlias<"vsub${p}.f32 $Vdn, $Vm",
+                    (VSUBfd DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;
+def : NEONInstAlias<"vsub${p}.f32 $Vdn, $Vm",
+                    (VSUBfq QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>;
+
 // VADDW two-operand aliases.
 def : NEONInstAlias<"vaddw${p}.s8 $Vdn, $Vm",
                     (VADDWsv8i16 QPR:$Vdn, QPR:$Vdn, DPR:$Vm, pred:$p)>;

Modified: llvm/trunk/test/MC/ARM/neon-sub-encoding.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/neon-sub-encoding.s?rev=146182&r1=146181&r2=146182&view=diff
==============================================================================
--- llvm/trunk/test/MC/ARM/neon-sub-encoding.s (original)
+++ llvm/trunk/test/MC/ARM/neon-sub-encoding.s Thu Dec  8 14:56:26 2011
@@ -11,6 +11,17 @@
 	vsub.i64	q8, q8, q9
 	vsub.f32	q8, q8, q9
 
+	vsub.i8  d13, d21
+	vsub.i16 d14, d22
+	vsub.i32 d15, d23
+	vsub.i64 d16, d24
+	vsub.f32 d17, d25
+	vsub.i8  q1, q10
+	vsub.i16 q2, q9
+	vsub.i32 q3, q8
+	vsub.i64 q4, q7
+	vsub.f32 q5, q6
+
 @ CHECK: vsub.i8	d16, d17, d16   @ encoding: [0xa0,0x08,0x41,0xf3]
 @ CHECK: vsub.i16	d16, d17, d16   @ encoding: [0xa0,0x08,0x51,0xf3]
 @ CHECK: vsub.i32	d16, d17, d16   @ encoding: [0xa0,0x08,0x61,0xf3]
@@ -21,9 +32,21 @@
 @ CHECK: vsub.i32	q8, q8, q9      @ encoding: [0xe2,0x08,0x60,0xf3]
 @ CHECK: vsub.i64	q8, q8, q9      @ encoding: [0xe2,0x08,0x70,0xf3]
 @ CHECK: vsub.f32	q8, q8, q9      @ encoding: [0xe2,0x0d,0x60,0xf2]
-@ CHECK: vsubl.s8	q8, d17, d16    @ encoding: [0xa0,0x02,0xc1,0xf2]
+
+@ CHECK: vsub.i8	d13, d13, d21   @ encoding: [0x25,0xd8,0x0d,0xf3]
+@ CHECK: vsub.i16	d14, d14, d22   @ encoding: [0x26,0xe8,0x1e,0xf3]
+@ CHECK: vsub.i32	d15, d15, d23   @ encoding: [0x27,0xf8,0x2f,0xf3]
+@ CHECK: vsub.i64	d16, d16, d24   @ encoding: [0xa8,0x08,0x70,0xf3]
+@ CHECK: vsub.f32	d17, d17, d25   @ encoding: [0xa9,0x1d,0x61,0xf2]
+@ CHECK: vsub.i8	q1, q1, q10     @ encoding: [0x64,0x28,0x02,0xf3]
+@ CHECK: vsub.i16	q2, q2, q9      @ encoding: [0x62,0x48,0x14,0xf3]
+@ CHECK: vsub.i32	q3, q3, q8      @ encoding: [0x60,0x68,0x26,0xf3]
+@ CHECK: vsub.i64	q4, q4, q7      @ encoding: [0x4e,0x88,0x38,0xf3]
+@ CHECK: vsub.f32	q5, q5, q6      @ encoding: [0x4c,0xad,0x2a,0xf2]
 
 
+
+@ CHECK: vsubl.s8	q8, d17, d16    @ encoding: [0xa0,0x02,0xc1,0xf2]
 	vsubl.s8	q8, d17, d16
 @ CHECK: vsubl.s16	q8, d17, d16    @ encoding: [0xa0,0x02,0xd1,0xf2]
 	vsubl.s16	q8, d17, d16



From stpworld at narod.ru  Thu Dec  8 15:05:09 2011
From: stpworld at narod.ru (Stepan Dyatkovskiy)
Date: Fri, 09 Dec 2011 01:05:09 +0400
Subject: [llvm-commits] [llvm] r146143 - in /llvm/trunk:
 lib/Target/ARM/ARMISelLowering.cpp
 test/CodeGen/ARM/2011-11-29-128bitArithmetics.ll
In-Reply-To: 
References: <20111208075503.BA6512A6C12C@llvm.org>
	
Message-ID: <4EE12685.4020607@narod.ru>

Thanks. "load" instruction is generated differently. Currently I check 
the string
"movw r1, :lower16:A"

but ppc generates
"movw r1, :lower16:(_A-(LPC0_0+8))" instead.

I can replace this check with something like this:
; CHECK: movw r1, :lower16:{{.*}}

Or even remove it...

Can I recommit it and check?

-Stepan.

Daniel Dunbar wrote:
> Hi Stepan,
>
> This is failing tests (at least on some darwin platforms). I reverted
> it, can you take a look?
>
> Here is the lit output:
> --
> ******************** TEST 'LLVM ::
> CodeGen/ARM/2011-11-29-128bitArithmetics.ll' FAILED
> ********************Script:
> --
> /Users/buildslave/zorg/buildbot/smooshlab/slave-0.8/build.clang-x86_64-darwin10-gcc42-RA/clang-build/Release+Asserts/bin/llc
> <  /Users/buildslave/zorg/buildbot/smooshlab/slave-0.8/build.clang-x86_64-darwin10-gcc42-RA/llvm/test/CodeGen/ARM/2011-11-29-128bitArithmetics.ll
> -march=arm -mcpu=cortex-a9 |
> /Users/buildslave/zorg/buildbot/smooshlab/slave-0.8/build.clang-x86_64-darwin10-gcc42-RA/clang-build/Release+Asserts/bin/FileCheck
> /Users/buildslave/zorg/buildbot/smooshlab/slave-0.8/build.clang-x86_64-darwin10-gcc42-RA/llvm/test/CodeGen/ARM/2011-11-29-128bitArithmetics.ll
> --
> Exit Code: 1
> Command Output (stderr):
> --
> /Users/buildslave/zorg/buildbot/smooshlab/slave-0.8/build.clang-x86_64-darwin10-gcc42-RA/llvm/test/CodeGen/ARM/2011-11-29-128bitArithmetics.ll:9:10:
> error: expected string not found in input
> ; CHECK: movw r1, :lower16:A
>           ^
> :10:13: note: scanning from here
> _test_sqrt: @ @test_sqrt
>              ^
> :12:2: note: possible intended match here
>   movw r1, :lower16:(_A-(LPC0_0+8))
>   ^
> --
>
> ********************
> --
>
>   - Daniel
>
>
> On Wed, Dec 7, 2011 at 11:55 PM, Stepan Dyatkovskiy  wrote:
>> Author: dyatkovskiy
>> Date: Thu Dec  8 01:55:03 2011
>> New Revision: 146143
>>
>> URL: http://llvm.org/viewvc/llvm-project?rev=146143&view=rev
>> Log:
>> Fix bug 9905: Failure in code selection for llvm intrinsics sqrt/exp (fix for FSQRT, FSIN, FCOS, FPOWI, FPOW, FLOG, FLOG2, FLOG10, FEXP, FEXP2).
>>
>> Added:
>>     llvm/trunk/test/CodeGen/ARM/2011-11-29-128bitArithmetics.ll
>> Modified:
>>     llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
>>
>> Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp?rev=146143&r1=146142&r2=146143&view=diff
>> ==============================================================================
>> --- llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp (original)
>> +++ llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp Thu Dec  8 01:55:03 2011
>> @@ -468,13 +468,23 @@
>>
>>      // v2f64 is legal so that QR subregs can be extracted as f64 elements, but
>>      // neither Neon nor VFP support any arithmetic operations on it.
>> +    // The same with v4f32. But keep in mind that vadd, vsub, vmul are natively
>> +    // supported for v4f32.
>>      setOperationAction(ISD::FADD, MVT::v2f64, Expand);
>>      setOperationAction(ISD::FSUB, MVT::v2f64, Expand);
>>      setOperationAction(ISD::FMUL, MVT::v2f64, Expand);
>> +    // FIXME: Code duplication: FDIV and FREM are expanded always, see
>> +    // ARMTargetLowering::addTypeForNEON method for details.
>>      setOperationAction(ISD::FDIV, MVT::v2f64, Expand);
>>      setOperationAction(ISD::FREM, MVT::v2f64, Expand);
>> +    // FIXME: Create unittest.
>> +    // In another words, find a way when "copysign" appears in DAG with vector
>> +    // operands.
>>      setOperationAction(ISD::FCOPYSIGN, MVT::v2f64, Expand);
>> +    // FIXME: Code duplication: SETCC has custom operation action, see
>> +    // ARMTargetLowering::addTypeForNEON method for details.
>>      setOperationAction(ISD::SETCC, MVT::v2f64, Expand);
>> +    // FIXME: Create unittest for FNEG and for FABS.
>>      setOperationAction(ISD::FNEG, MVT::v2f64, Expand);
>>      setOperationAction(ISD::FABS, MVT::v2f64, Expand);
>>      setOperationAction(ISD::FSQRT, MVT::v2f64, Expand);
>> @@ -487,11 +497,23 @@
>>      setOperationAction(ISD::FLOG10, MVT::v2f64, Expand);
>>      setOperationAction(ISD::FEXP, MVT::v2f64, Expand);
>>      setOperationAction(ISD::FEXP2, MVT::v2f64, Expand);
>> +    // FIXME: Create unittest for FCEIL, FTRUNC, FRINT, FNEARBYINT, FFLOOR.
>>      setOperationAction(ISD::FCEIL, MVT::v2f64, Expand);
>>      setOperationAction(ISD::FTRUNC, MVT::v2f64, Expand);
>>      setOperationAction(ISD::FRINT, MVT::v2f64, Expand);
>>      setOperationAction(ISD::FNEARBYINT, MVT::v2f64, Expand);
>>      setOperationAction(ISD::FFLOOR, MVT::v2f64, Expand);
>> +
>> +    setOperationAction(ISD::FSQRT, MVT::v4f32, Expand);
>> +    setOperationAction(ISD::FSIN, MVT::v4f32, Expand);
>> +    setOperationAction(ISD::FCOS, MVT::v4f32, Expand);
>> +    setOperationAction(ISD::FPOWI, MVT::v4f32, Expand);
>> +    setOperationAction(ISD::FPOW, MVT::v4f32, Expand);
>> +    setOperationAction(ISD::FLOG, MVT::v4f32, Expand);
>> +    setOperationAction(ISD::FLOG2, MVT::v4f32, Expand);
>> +    setOperationAction(ISD::FLOG10, MVT::v4f32, Expand);
>> +    setOperationAction(ISD::FEXP, MVT::v4f32, Expand);
>> +    setOperationAction(ISD::FEXP2, MVT::v4f32, Expand);
>>
>>      // Neon does not support some operations on v1i64 and v2i64 types.
>>      setOperationAction(ISD::MUL, MVT::v1i64, Expand);
>>
>> Added: llvm/trunk/test/CodeGen/ARM/2011-11-29-128bitArithmetics.ll
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/2011-11-29-128bitArithmetics.ll?rev=146143&view=auto
>> ==============================================================================
>> --- llvm/trunk/test/CodeGen/ARM/2011-11-29-128bitArithmetics.ll (added)
>> +++ llvm/trunk/test/CodeGen/ARM/2011-11-29-128bitArithmetics.ll Thu Dec  8 01:55:03 2011
>> @@ -0,0 +1,302 @@
>> +; RUN: llc<  %s -march=arm -mcpu=cortex-a9 | FileCheck %s
>> +
>> + at A = global<4 x float>  
>> +
>> +define void @test_sqrt(<4 x float>* %X) nounwind {
>> +
>> +; CHECK: test_sqrt:
>> +
>> +; CHECK:      movw    r1, :lower16:A
>> +; CHECK-NEXT: movt    r1, :upper16:A
>> +; CHECK:      vldmia  r1, {[[short0:s[0-9]+]], [[short1:s[0-9]+]], [[short2:s[0-9]+]], [[short3:s[0-9]+]]}
>> +; CHECK:      vsqrt.f32       {{s[0-9]+}}, [[short3]]
>> +; CHECK:      vsqrt.f32       {{s[0-9]+}}, [[short2]]
>> +; CHECK:      vsqrt.f32       {{s[0-9]+}}, [[short1]]
>> +; CHECK:      vsqrt.f32       {{s[0-9]+}}, [[short0]]
>> +; CHECK-NEXT: vstmia  {{.*}}
>> +
>> +L.entry:
>> +  %0 = load<4 x float>* @A, align 16
>> +  %1 = call<4 x float>  @llvm.sqrt.v4f32(<4 x float>  %0)
>> +  store<4 x float>  %1,<4 x float>* %X, align 16
>> +  ret void
>> +}
>> +
>> +declare<4 x float>  @llvm.sqrt.v4f32(<4 x float>) nounwind readonly
>> +
>> +
>> +define void @test_cos(<4 x float>* %X) nounwind {
>> +
>> +; CHECK: test_cos:
>> +
>> +; CHECK:      movw  [[reg0:r[0-9]+]], :lower16:A
>> +; CHECK-NEXT: movt  [[reg0]], :upper16:A
>> +; CHECK:      vldmia [[reg0]], {{.*}}
>> +
>> +; CHECK:      {{[v]?mov}}  r0, {{[r|s][0-9]+}}
>> +; CHECK:      bl  cosf
>> +
>> +; CHECK:      {{[v]?mov}}  r0, {{[r|s][0-9]+}}
>> +; CHECK:      bl  cosf
>> +
>> +; CHECK:      {{[v]?mov}}  r0, {{[r|s][0-9]+}}
>> +; CHECK:      bl  cosf
>> +
>> +; CHECK:      {{[v]?mov}}  r0, {{[r|s][0-9]+}}
>> +; CHECK:      bl  cosf
>> +
>> +; CHECK:      vstmia  {{.*}}
>> +
>> +L.entry:
>> +  %0 = load<4 x float>* @A, align 16
>> +  %1 = call<4 x float>  @llvm.cos.v4f32(<4 x float>  %0)
>> +  store<4 x float>  %1,<4 x float>* %X, align 16
>> +  ret void
>> +}
>> +
>> +declare<4 x float>  @llvm.cos.v4f32(<4 x float>) nounwind readonly
>> +
>> +define void @test_exp(<4 x float>* %X) nounwind {
>> +
>> +; CHECK: test_exp:
>> +
>> +; CHECK:      movw  [[reg0:r[0-9]+]], :lower16:A
>> +; CHECK-NEXT: movt  [[reg0]], :upper16:A
>> +; CHECK:      vldmia [[reg0]], {{.*}}
>> +
>> +; CHECK:      {{[v]?mov}}  r0, {{[r|s][0-9]+}}
>> +; CHECK:      bl  expf
>> +
>> +; CHECK:      {{[v]?mov}}  r0, {{[r|s][0-9]+}}
>> +; CHECK:      bl  expf
>> +
>> +; CHECK:      {{[v]?mov}}  r0, {{[r|s][0-9]+}}
>> +; CHECK:      bl  expf
>> +
>> +; CHECK:      {{[v]?mov}}  r0, {{[r|s][0-9]+}}
>> +; CHECK:      bl  expf
>> +
>> +; CHECK:      vstmia  {{.*}}
>> +
>> +L.entry:
>> +  %0 = load<4 x float>* @A, align 16
>> +  %1 = call<4 x float>  @llvm.exp.v4f32(<4 x float>  %0)
>> +  store<4 x float>  %1,<4 x float>* %X, align 16
>> +  ret void
>> +}
>> +
>> +declare<4 x float>  @llvm.exp.v4f32(<4 x float>) nounwind readonly
>> +
>> +define void @test_exp2(<4 x float>* %X) nounwind {
>> +
>> +; CHECK: test_exp2:
>> +
>> +; CHECK:      movw  [[reg0:r[0-9]+]], :lower16:A
>> +; CHECK-NEXT: movt  [[reg0]], :upper16:A
>> +; CHECK:      vldmia [[reg0]], {{.*}}
>> +
>> +; CHECK:      {{[v]?mov}}  r0, {{[r|s][0-9]+}}
>> +; CHECK:      bl  exp2f
>> +
>> +; CHECK:      {{[v]?mov}}  r0, {{[r|s][0-9]+}}
>> +; CHECK:      bl  exp2f
>> +
>> +; CHECK:      {{[v]?mov}}  r0, {{[r|s][0-9]+}}
>> +; CHECK:      bl  exp2f
>> +
>> +; CHECK:      {{[v]?mov}}  r0, {{[r|s][0-9]+}}
>> +; CHECK:      bl  exp2f
>> +
>> +; CHECK:      vstmia  {{.*}}
>> +
>> +L.entry:
>> +  %0 = load<4 x float>* @A, align 16
>> +  %1 = call<4 x float>  @llvm.exp2.v4f32(<4 x float>  %0)
>> +  store<4 x float>  %1,<4 x float>* %X, align 16
>> +  ret void
>> +}
>> +
>> +declare<4 x float>  @llvm.exp2.v4f32(<4 x float>) nounwind readonly
>> +
>> +define void @test_log10(<4 x float>* %X) nounwind {
>> +
>> +; CHECK: test_log10:
>> +
>> +; CHECK:      movw  [[reg0:r[0-9]+]], :lower16:A
>> +; CHECK-NEXT: movt  [[reg0]], :upper16:A
>> +; CHECK:      vldmia [[reg0]], {{.*}}
>> +
>> +; CHECK:      {{[v]?mov}}  r0, {{[r|s][0-9]+}}
>> +; CHECK:      bl  log10f
>> +
>> +; CHECK:      {{[v]?mov}}  r0, {{[r|s][0-9]+}}
>> +; CHECK:      bl  log10f
>> +
>> +; CHECK:      {{[v]?mov}}  r0, {{[r|s][0-9]+}}
>> +; CHECK:      bl  log10f
>> +
>> +; CHECK:      {{[v]?mov}}  r0, {{[r|s][0-9]+}}
>> +; CHECK:      bl  log10f
>> +
>> +; CHECK:      vstmia  {{.*}}
>> +
>> +L.entry:
>> +  %0 = load<4 x float>* @A, align 16
>> +  %1 = call<4 x float>  @llvm.log10.v4f32(<4 x float>  %0)
>> +  store<4 x float>  %1,<4 x float>* %X, align 16
>> +  ret void
>> +}
>> +
>> +declare<4 x float>  @llvm.log10.v4f32(<4 x float>) nounwind readonly
>> +
>> +define void @test_log(<4 x float>* %X) nounwind {
>> +
>> +; CHECK: test_log:
>> +
>> +; CHECK:      movw  [[reg0:r[0-9]+]], :lower16:A
>> +; CHECK-NEXT: movt  [[reg0]], :upper16:A
>> +; CHECK:      vldmia [[reg0]], {{.*}}
>> +
>> +; CHECK:      {{[v]?mov}}  r0, {{[r|s][0-9]+}}
>> +; CHECK:      bl  logf
>> +
>> +; CHECK:      {{[v]?mov}}  r0, {{[r|s][0-9]+}}
>> +; CHECK:      bl  logf
>> +
>> +; CHECK:      {{[v]?mov}}  r0, {{[r|s][0-9]+}}
>> +; CHECK:      bl  logf
>> +
>> +; CHECK:      {{[v]?mov}}  r0, {{[r|s][0-9]+}}
>> +; CHECK:      bl  logf
>> +
>> +; CHECK:      vstmia  {{.*}}
>> +
>> +L.entry:
>> +  %0 = load<4 x float>* @A, align 16
>> +  %1 = call<4 x float>  @llvm.log.v4f32(<4 x float>  %0)
>> +  store<4 x float>  %1,<4 x float>* %X, align 16
>> +  ret void
>> +}
>> +
>> +declare<4 x float>  @llvm.log.v4f32(<4 x float>) nounwind readonly
>> +
>> +define void @test_log2(<4 x float>* %X) nounwind {
>> +
>> +; CHECK: test_log2:
>> +
>> +; CHECK:      movw  [[reg0:r[0-9]+]], :lower16:A
>> +; CHECK-NEXT: movt  [[reg0]], :upper16:A
>> +; CHECK:      vldmia [[reg0]], {{.*}}
>> +
>> +; CHECK:      {{[v]?mov}}  r0, {{[r|s][0-9]+}}
>> +; CHECK:      bl  log2f
>> +
>> +; CHECK:      {{[v]?mov}}  r0, {{[r|s][0-9]+}}
>> +; CHECK:      bl  log2f
>> +
>> +; CHECK:      {{[v]?mov}}  r0, {{[r|s][0-9]+}}
>> +; CHECK:      bl  log2f
>> +
>> +; CHECK:      {{[v]?mov}}  r0, {{[r|s][0-9]+}}
>> +; CHECK:      bl  log2f
>> +
>> +; CHECK:      vstmia  {{.*}}
>> +
>> +L.entry:
>> +  %0 = load<4 x float>* @A, align 16
>> +  %1 = call<4 x float>  @llvm.log2.v4f32(<4 x float>  %0)
>> +  store<4 x float>  %1,<4 x float>* %X, align 16
>> +  ret void
>> +}
>> +
>> +declare<4 x float>  @llvm.log2.v4f32(<4 x float>) nounwind readonly
>> +
>> +
>> +define void @test_pow(<4 x float>* %X) nounwind {
>> +
>> +; CHECK: test_pow:
>> +
>> +; CHECK:      movw  [[reg0:r[0-9]+]], :lower16:A
>> +; CHECK-NEXT: movt  [[reg0]], :upper16:A
>> +; CHECK:      vldmia [[reg0]], {{.*}}
>> +
>> +; CHECK:      {{[v]?mov}}  r0, {{[r|s][0-9]+}}
>> +; CHECK:      bl  powf
>> +
>> +; CHECK:      {{[v]?mov}}  r0, {{[r|s][0-9]+}}
>> +; CHECK:      bl  powf
>> +
>> +; CHECK:      {{[v]?mov}}  r0, {{[r|s][0-9]+}}
>> +; CHECK:      bl  powf
>> +
>> +; CHECK:      {{[v]?mov}}  r0, {{[r|s][0-9]+}}
>> +; CHECK:      bl  powf
>> +
>> +; CHECK:      vstmia  {{.*}}
>> +
>> +L.entry:
>> +
>> +  %0 = load<4 x float>* @A, align 16
>> +  %1 = call<4 x float>  @llvm.pow.v4f32(<4 x float>  %0,<4 x float>  )
>> +
>> +  store<4 x float>  %1,<4 x float>* %X, align 16
>> +
>> +  ret void
>> +}
>> +
>> +declare<4 x float>  @llvm.pow.v4f32(<4 x float>,<4 x float>) nounwind readonly
>> +
>> +define void @test_powi(<4 x float>* %X) nounwind {
>> +
>> +; CHECK: test_powi:
>> +
>> +; CHECK:       movw  [[reg0:r[0-9]+]], :lower16:A
>> +; CHECK-NEXT:  movt  [[reg0]], :upper16:A
>> +; CHECK-NEXT:  vldmia  [[reg0]], {{.*}}
>> +; CHECK:       vmul.f32 {{.*}}
>> +
>> +; CHECK:      vstmia  {{.*}}
>> +
>> +L.entry:
>> +
>> +  %0 = load<4 x float>* @A, align 16
>> +  %1 = call<4 x float>  @llvm.powi.v4f32(<4 x float>  %0, i32 2)
>> +
>> +  store<4 x float>  %1,<4 x float>* %X, align 16
>> +
>> +  ret void
>> +}
>> +
>> +declare<4 x float>  @llvm.powi.v4f32(<4 x float>, i32) nounwind readonly
>> +
>> +define void @test_sin(<4 x float>* %X) nounwind {
>> +
>> +; CHECK: test_sin:
>> +
>> +; CHECK:      movw  [[reg0:r[0-9]+]], :lower16:A
>> +; CHECK-NEXT: movt  [[reg0]], :upper16:A
>> +; CHECK:      vldmia [[reg0]], {{.*}}
>> +
>> +; CHECK:      {{[v]?mov}}  r0, {{[r|s][0-9]+}}
>> +; CHECK:      bl  sinf
>> +
>> +; CHECK:      {{[v]?mov}}  r0, {{[r|s][0-9]+}}
>> +; CHECK:      bl  sinf
>> +
>> +; CHECK:      {{[v]?mov}}  r0, {{[r|s][0-9]+}}
>> +; CHECK:      bl  sinf
>> +
>> +; CHECK:      {{[v]?mov}}  r0, {{[r|s][0-9]+}}
>> +; CHECK:      bl  sinf
>> +
>> +; CHECK:      vstmia  {{.*}}
>> +
>> +L.entry:
>> +  %0 = load<4 x float>* @A, align 16
>> +  %1 = call<4 x float>  @llvm.sin.v4f32(<4 x float>  %0)
>> +  store<4 x float>  %1,<4 x float>* %X, align 16
>> +  ret void
>> +}
>> +
>> +declare<4 x float>  @llvm.sin.v4f32(<4 x float>) nounwind readonly
>> +
>>
>>
>> _______________________________________________
>> llvm-commits mailing list
>> llvm-commits at cs.uiuc.edu
>> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits


From eli.friedman at gmail.com  Thu Dec  8 15:06:39 2011
From: eli.friedman at gmail.com (Eli Friedman)
Date: Thu, 8 Dec 2011 13:06:39 -0800
Subject: [llvm-commits] XOP encoding patch
In-Reply-To: <1323377350.13027.YahooMailNeo@web161504.mail.bf1.yahoo.com>
References: <1323377350.13027.YahooMailNeo@web161504.mail.bf1.yahoo.com>
Message-ID: 

On Thu, Dec 8, 2011 at 12:49 PM, Jan Sjodin  wrote:
> This patch handles the encoding of XOP instructions. I included one
> instruction for each kind including a test.

+multiclass xop4opimm opc, string OpcodeStr> {
+  def ri : IXOPi8

Author: ahatanak
Date: Thu Dec  8 15:05:38 2011
New Revision: 146183

URL: http://llvm.org/viewvc/llvm-project?rev=146183&view=rev
Log:
Pass a GlobalAddress instead of an ExternalSymbol to LowerCallTo in
MipsTargetLowering::LowerGlobalTLSAddress. This is necessary to have
call16(__tls_get_addr) emitted instead of got_disp(__tls_get_addr) when the
target is Mips64.


Modified:
    llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp

Modified: llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp?rev=146183&r1=146182&r2=146183&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp Thu Dec  8 15:05:38 2011
@@ -1550,19 +1550,26 @@
     SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, PtrVT,
                                              0, MipsII::MO_TLSGD);
     SDValue Argument = DAG.getNode(MipsISD::WrapperPIC, dl, PtrVT, TGA);
+    unsigned PtrSize = PtrVT.getSizeInBits();
+    IntegerType *PtrTy = Type::getIntNTy(*DAG.getContext(), PtrSize);
+
+    SmallVector Params;
+    Params.push_back(PtrTy);
+    FunctionType *FuncTy = FunctionType::get(PtrTy, Params, false);
+    Function *Func = Function::Create(FuncTy, GlobalValue::ExternalLinkage,
+                                      "__tls_get_addr");
+    SDValue TlsGetAddr = DAG.getGlobalAddress(Func, dl, PtrVT);
 
     ArgListTy Args;
     ArgListEntry Entry;
     Entry.Node = Argument;
-    unsigned PtrSize = PtrVT.getSizeInBits();
-    IntegerType *PtrTy = Type::getIntNTy(*DAG.getContext(), PtrSize);
     Entry.Ty = PtrTy;
     Args.push_back(Entry);
+    
     std::pair CallResult =
       LowerCallTo(DAG.getEntryNode(), PtrTy,
                   false, false, false, false, 0, CallingConv::C, false, true,
-                  DAG.getExternalSymbol("__tls_get_addr", PtrVT), Args, DAG,
-                  dl);
+                  TlsGetAddr, Args, DAG, dl);
 
     return CallResult.first;
   }



From dpatel at apple.com  Thu Dec  8 15:33:24 2011
From: dpatel at apple.com (Devang Patel)
Date: Thu, 08 Dec 2011 21:33:24 -0000
Subject: [llvm-commits] [llvm] r146184 -
	/llvm/trunk/lib/CodeGen/MachineSink.cpp
Message-ID: <20111208213324.162412A6C12C@llvm.org>

Author: dpatel
Date: Thu Dec  8 15:33:23 2011
New Revision: 146184

URL: http://llvm.org/viewvc/llvm-project?rev=146184&view=rev
Log:
Filter "sink to" candidate blocks sooner. This avoids unnecessary computation to determine whether the block dominates all uses or not.

Modified:
    llvm/trunk/lib/CodeGen/MachineSink.cpp

Modified: llvm/trunk/lib/CodeGen/MachineSink.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineSink.cpp?rev=146184&r1=146183&r2=146184&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/MachineSink.cpp (original)
+++ llvm/trunk/lib/CodeGen/MachineSink.cpp Thu Dec  8 15:33:23 2011
@@ -499,10 +499,21 @@
       // we should sink to.
       for (MachineBasicBlock::succ_iterator SI = ParentBlock->succ_begin(),
            E = ParentBlock->succ_end(); SI != E; ++SI) {
+	MachineBasicBlock *SuccBlock = *SI;
+	// It is not possible to sink an instruction into its own block.  This can
+	// happen with loops.
+	if (ParentBlock == SuccBlock)
+	  continue;
+
+	// It's not safe to sink instructions to EH landing pad. Control flow into
+	// landing pad is implicitly defined.
+	if (SuccBlock->isLandingPad())
+	  continue;
+
         bool LocalUse = false;
-        if (AllUsesDominatedByBlock(Reg, *SI, ParentBlock,
+        if (AllUsesDominatedByBlock(Reg, SuccBlock, ParentBlock,
                                     BreakPHIEdge, LocalUse)) {
-          SuccToSinkTo = *SI;
+          SuccToSinkTo = SuccBlock;
           break;
         }
         if (LocalUse)
@@ -520,15 +531,6 @@
   if (SuccToSinkTo == 0)
     return false;
 
-  // It's not safe to sink instructions to EH landing pad. Control flow into
-  // landing pad is implicitly defined.
-  if (SuccToSinkTo->isLandingPad())
-    return false;
-
-  // It is not possible to sink an instruction into its own block.  This can
-  // happen with loops.
-  if (MI->getParent() == SuccToSinkTo)
-    return false;
 
   // If the instruction to move defines a dead physical register which is live
   // when leaving the basic block, don't move it because it could turn into a



From grosbach at apple.com  Thu Dec  8 15:34:21 2011
From: grosbach at apple.com (Jim Grosbach)
Date: Thu, 08 Dec 2011 21:34:21 -0000
Subject: [llvm-commits] [llvm] r146185 -
	/llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
Message-ID: <20111208213421.1BE992A6C12C@llvm.org>

Author: grosbach
Date: Thu Dec  8 15:34:20 2011
New Revision: 146185

URL: http://llvm.org/viewvc/llvm-project?rev=146185&view=rev
Log:
ARM asm parser, just issue a warning for a duplicate reg in a list.

For better 'gas' compatibility.

Modified:
    llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp

Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp?rev=146185&r1=146184&r2=146185&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp (original)
+++ llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Thu Dec  8 15:34:20 2011
@@ -2596,6 +2596,7 @@
     Parser.Lex(); // Eat the comma.
     RegLoc = Parser.getTok().getLoc();
     int OldReg = Reg;
+    const AsmToken RegTok = Parser.getTok();
     Reg = tryParseRegister();
     if (Reg == -1)
       return Error(RegLoc, "register expected");
@@ -2609,8 +2610,13 @@
     if (!RC->contains(Reg))
       return Error(RegLoc, "invalid register in register list");
     // List must be monotonically increasing.
-    if (getARMRegisterNumbering(Reg) <= getARMRegisterNumbering(OldReg))
+    if (getARMRegisterNumbering(Reg) < getARMRegisterNumbering(OldReg))
       return Error(RegLoc, "register list not in ascending order");
+    if (getARMRegisterNumbering(Reg) == getARMRegisterNumbering(OldReg)) {
+      Warning(RegLoc, "duplicated register (" + RegTok.getString() +
+              ") in register list");
+      continue;
+    }
     // VFP register lists must also be contiguous.
     // It's OK to use the enumeration values directly here rather, as the
     // VFP register classes have the enum sorted properly.



From mcrosier at apple.com  Thu Dec  8 15:37:11 2011
From: mcrosier at apple.com (Chad Rosier)
Date: Thu, 08 Dec 2011 21:37:11 -0000
Subject: [llvm-commits] [llvm] r146186 -
	/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
Message-ID: <20111208213711.243712A6C12C@llvm.org>

Author: mcrosier
Date: Thu Dec  8 15:37:10 2011
New Revision: 146186

URL: http://llvm.org/viewvc/llvm-project?rev=146186&view=rev
Log:
Add rather verbose stats for fast-isel failures.

Modified:
    llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp?rev=146186&r1=146185&r2=146186&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Thu Dec  8 15:37:10 2011
@@ -61,6 +61,77 @@
 STATISTIC(NumDAGBlocks, "Number of blocks selected using DAG");
 STATISTIC(NumDAGIselRetries,"Number of times dag isel has to try another path");
 
+#ifndef NDEBUG
+  // Terminators
+STATISTIC(NumFastIselFailRet,"Fast isel fails on Ret");
+STATISTIC(NumFastIselFailBr,"Fast isel fails on Br");
+STATISTIC(NumFastIselFailSwitch,"Fast isel fails on Switch");
+STATISTIC(NumFastIselFailIndirectBr,"Fast isel fails on IndirectBr");
+STATISTIC(NumFastIselFailInvoke,"Fast isel fails on Invoke");
+STATISTIC(NumFastIselFailResume,"Fast isel fails on Resume");
+STATISTIC(NumFastIselFailUnwind,"Fast isel fails on Unwind");
+STATISTIC(NumFastIselFailUnreachable,"Fast isel fails on Unreachable");
+
+  // Standard binary operators...
+STATISTIC(NumFastIselFailAdd,"Fast isel fails on Add");
+STATISTIC(NumFastIselFailFAdd,"Fast isel fails on FAdd");
+STATISTIC(NumFastIselFailSub,"Fast isel fails on Sub");
+STATISTIC(NumFastIselFailFSub,"Fast isel fails on FSub");
+STATISTIC(NumFastIselFailMul,"Fast isel fails on Mul");
+STATISTIC(NumFastIselFailFMul,"Fast isel fails on FMul");
+STATISTIC(NumFastIselFailUDiv,"Fast isel fails on UDiv");
+STATISTIC(NumFastIselFailSDiv,"Fast isel fails on SDiv");
+STATISTIC(NumFastIselFailFDiv,"Fast isel fails on FDiv");
+STATISTIC(NumFastIselFailURem,"Fast isel fails on URem");
+STATISTIC(NumFastIselFailSRem,"Fast isel fails on SRem");
+STATISTIC(NumFastIselFailFRem,"Fast isel fails on FRem");
+
+  // Logical operators...
+STATISTIC(NumFastIselFailAnd,"Fast isel fails on And");
+STATISTIC(NumFastIselFailOr,"Fast isel fails on Or");
+STATISTIC(NumFastIselFailXor,"Fast isel fails on Xor");
+
+  // Memory instructions...
+STATISTIC(NumFastIselFailAlloca,"Fast isel fails on Alloca");
+STATISTIC(NumFastIselFailLoad,"Fast isel fails on Load");
+STATISTIC(NumFastIselFailStore,"Fast isel fails on Store");
+STATISTIC(NumFastIselFailAtomicCmpXchg,"Fast isel fails on AtomicCmpXchg");
+STATISTIC(NumFastIselFailAtomicRMW,"Fast isel fails on AtomicRWM");
+STATISTIC(NumFastIselFailFence,"Fast isel fails on Frence");
+STATISTIC(NumFastIselFailGetElementPtr,"Fast isel fails on GetElementPtr");
+
+  // Convert instructions...
+STATISTIC(NumFastIselFailTrunc,"Fast isel fails on Trunc");
+STATISTIC(NumFastIselFailZExt,"Fast isel fails on ZExt");
+STATISTIC(NumFastIselFailSExt,"Fast isel fails on SExt");
+STATISTIC(NumFastIselFailFPTrunc,"Fast isel fails on FPTrunc");
+STATISTIC(NumFastIselFailFPExt,"Fast isel fails on FPExt");
+STATISTIC(NumFastIselFailFPToUI,"Fast isel fails on FPToUI");
+STATISTIC(NumFastIselFailFPToSI,"Fast isel fails on FPToSI");
+STATISTIC(NumFastIselFailUIToFP,"Fast isel fails on UIToFP");
+STATISTIC(NumFastIselFailSIToFP,"Fast isel fails on SIToFP");
+STATISTIC(NumFastIselFailIntToPtr,"Fast isel fails on IntToPtr");
+STATISTIC(NumFastIselFailPtrToInt,"Fast isel fails on PtrToInt");
+STATISTIC(NumFastIselFailBitCast,"Fast isel fails on BitCast");
+
+  // Other instructions...
+STATISTIC(NumFastIselFailICmp,"Fast isel fails on ICmp");
+STATISTIC(NumFastIselFailFCmp,"Fast isel fails on FCmp");
+STATISTIC(NumFastIselFailPHI,"Fast isel fails on PHI");
+STATISTIC(NumFastIselFailSelect,"Fast isel fails on Select");
+STATISTIC(NumFastIselFailCall,"Fast isel fails on Call");
+STATISTIC(NumFastIselFailShl,"Fast isel fails on Shl");
+STATISTIC(NumFastIselFailLShr,"Fast isel fails on LShr");
+STATISTIC(NumFastIselFailAShr,"Fast isel fails on AShr");
+STATISTIC(NumFastIselFailVAArg,"Fast isel fails on VAArg");
+STATISTIC(NumFastIselFailExtractElement,"Fast isel fails on ExtractElement");
+STATISTIC(NumFastIselFailInsertElement,"Fast isel fails on InsertElement");
+STATISTIC(NumFastIselFailShuffleVector,"Fast isel fails on ShuffleVector");
+STATISTIC(NumFastIselFailExtractValue,"Fast isel fails on ExtractValue");
+STATISTIC(NumFastIselFailInsertValue,"Fast isel fails on InsertValue");
+STATISTIC(NumFastIselFailLandingPad,"Fast isel fails on LandingPad");
+#endif
+
 static cl::opt
 EnableFastISelVerbose("fast-isel-verbose", cl::Hidden,
           cl::desc("Enable verbose messages in the \"fast\" "
@@ -821,6 +892,84 @@
          !FuncInfo->isExportedInst(I); // Exported instrs must be computed.
 }
 
+#ifndef NDEBUG
+static void collectFailStats(const Instruction *I) {
+  switch (I->getOpcode()) {
+  default: assert (0 && " ");
+
+  // Terminators
+  case Instruction::Ret:         NumFastIselFailRet++; return;
+  case Instruction::Br:          NumFastIselFailBr++; return;
+  case Instruction::Switch:      NumFastIselFailSwitch++; return;
+  case Instruction::IndirectBr:  NumFastIselFailIndirectBr++; return;
+  case Instruction::Invoke:      NumFastIselFailInvoke++; return;
+  case Instruction::Resume:      NumFastIselFailResume++; return;
+  case Instruction::Unwind:      NumFastIselFailUnwind++; return;
+  case Instruction::Unreachable: NumFastIselFailUnreachable++; return;
+
+  // Standard binary operators...
+  case Instruction::Add:  NumFastIselFailAdd++; return;
+  case Instruction::FAdd: NumFastIselFailFAdd++; return;
+  case Instruction::Sub:  NumFastIselFailSub++; return;
+  case Instruction::FSub: NumFastIselFailFSub++; return;
+  case Instruction::Mul:  NumFastIselFailMul++; return;
+  case Instruction::FMul: NumFastIselFailFMul++; return;
+  case Instruction::UDiv: NumFastIselFailUDiv++; return;
+  case Instruction::SDiv: NumFastIselFailSDiv++; return;
+  case Instruction::FDiv: NumFastIselFailFDiv++; return;
+  case Instruction::URem: NumFastIselFailURem++; return;
+  case Instruction::SRem: NumFastIselFailSRem++; return;
+  case Instruction::FRem: NumFastIselFailFRem++; return;
+
+  // Logical operators...
+  case Instruction::And: NumFastIselFailAnd++; return;
+  case Instruction::Or:  NumFastIselFailOr++; return;
+  case Instruction::Xor: NumFastIselFailXor++; return;
+
+  // Memory instructions...
+  case Instruction::Alloca:        NumFastIselFailAlloca++; return;
+  case Instruction::Load:          NumFastIselFailLoad++; return;
+  case Instruction::Store:         NumFastIselFailStore++; return;
+  case Instruction::AtomicCmpXchg: NumFastIselFailAtomicCmpXchg++; return;
+  case Instruction::AtomicRMW:     NumFastIselFailAtomicRMW++; return;
+  case Instruction::Fence:         NumFastIselFailFence++; return;
+  case Instruction::GetElementPtr: NumFastIselFailGetElementPtr++; return;
+
+  // Convert instructions...
+  case Instruction::Trunc:    NumFastIselFailTrunc++; return;
+  case Instruction::ZExt:     NumFastIselFailZExt++; return;
+  case Instruction::SExt:     NumFastIselFailSExt++; return;
+  case Instruction::FPTrunc:  NumFastIselFailFPTrunc++; return;
+  case Instruction::FPExt:    NumFastIselFailFPExt++; return;
+  case Instruction::FPToUI:   NumFastIselFailFPToUI++; return;
+  case Instruction::FPToSI:   NumFastIselFailFPToSI++; return;
+  case Instruction::UIToFP:   NumFastIselFailUIToFP++; return;
+  case Instruction::SIToFP:   NumFastIselFailSIToFP++; return;
+  case Instruction::IntToPtr: NumFastIselFailIntToPtr++; return; 
+  case Instruction::PtrToInt: NumFastIselFailPtrToInt++; return;
+  case Instruction::BitCast:  NumFastIselFailBitCast++; return; 
+
+  // Other instructions...
+  case Instruction::ICmp:           NumFastIselFailICmp++; return;
+  case Instruction::FCmp:           NumFastIselFailFCmp++; return;
+  case Instruction::PHI:            NumFastIselFailPHI++; return;
+  case Instruction::Select:         NumFastIselFailSelect++; return;
+  case Instruction::Call:           NumFastIselFailCall++; return;
+  case Instruction::Shl:            NumFastIselFailShl++; return;
+  case Instruction::LShr:           NumFastIselFailLShr++; return;
+  case Instruction::AShr:           NumFastIselFailAShr++; return;
+  case Instruction::VAArg:          NumFastIselFailVAArg++; return;
+  case Instruction::ExtractElement: NumFastIselFailExtractElement++; return;
+  case Instruction::InsertElement:  NumFastIselFailInsertElement++; return;
+  case Instruction::ShuffleVector:  NumFastIselFailShuffleVector++; return;
+  case Instruction::ExtractValue:   NumFastIselFailExtractValue++; return;
+  case Instruction::InsertValue:    NumFastIselFailInsertValue++; return;
+  case Instruction::LandingPad:     NumFastIselFailLandingPad++; return;
+  }
+  return;
+}
+#endif
+
 void SelectionDAGISel::SelectAllBasicBlocks(const Function &Fn) {
   // Initialize the Fast-ISel state, if needed.
   FastISel *FastIS = 0;
@@ -932,6 +1081,10 @@
           continue;
         }
 
+#ifndef NDEBUG
+        collectFailStats(Inst);
+#endif
+
         // Then handle certain instructions as single-LLVM-Instruction blocks.
         if (isa(Inst)) {
 



From dpatel at apple.com  Thu Dec  8 15:48:02 2011
From: dpatel at apple.com (Devang Patel)
Date: Thu, 08 Dec 2011 21:48:02 -0000
Subject: [llvm-commits] [llvm] r146187 -
	/llvm/trunk/lib/CodeGen/MachineSink.cpp
Message-ID: <20111208214802.270EF2A6C12C@llvm.org>

Author: dpatel
Date: Thu Dec  8 15:48:01 2011
New Revision: 146187

URL: http://llvm.org/viewvc/llvm-project?rev=146187&view=rev
Log:
Refactor. No intentional functionality change.

Modified:
    llvm/trunk/lib/CodeGen/MachineSink.cpp

Modified: llvm/trunk/lib/CodeGen/MachineSink.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineSink.cpp?rev=146187&r1=146186&r2=146187&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/MachineSink.cpp (original)
+++ llvm/trunk/lib/CodeGen/MachineSink.cpp Thu Dec  8 15:48:01 2011
@@ -90,6 +90,8 @@
     bool AllUsesDominatedByBlock(unsigned Reg, MachineBasicBlock *MBB,
                                  MachineBasicBlock *DefMBB,
                                  bool &BreakPHIEdge, bool &LocalUse) const;
+    MachineBasicBlock *FindSuccToSinkTo(MachineInstr *MI, bool &BreakPHIEdge);
+
     bool PerformTrivialForwardCoalescing(MachineInstr *MI,
                                          MachineBasicBlock *MBB);
   };
@@ -401,25 +403,9 @@
   }
 }
 
-/// SinkInstruction - Determine whether it is safe to sink the specified machine
-/// instruction out of its current block into a successor.
-bool MachineSinking::SinkInstruction(MachineInstr *MI, bool &SawStore) {
-  // Don't sink insert_subreg, subreg_to_reg, reg_sequence. These are meant to
-  // be close to the source to make it easier to coalesce.
-  if (AvoidsSinking(MI, MRI))
-    return false;
-
-  // Check if it's safe to move the instruction.
-  if (!MI->isSafeToMove(TII, AA, SawStore))
-    return false;
-
-  // FIXME: This should include support for sinking instructions within the
-  // block they are currently in to shorten the live ranges.  We often get
-  // instructions sunk into the top of a large block, but it would be better to
-  // also sink them down before their first use in the block.  This xform has to
-  // be careful not to *increase* register pressure though, e.g. sinking
-  // "x = y + z" down if it kills y and z would increase the live ranges of y
-  // and z and only shrink the live range of x.
+/// FindSuccToSinkTo - Find a successor to sink this instruction to.
+MachineBasicBlock *MachineSinking::FindSuccToSinkTo(MachineInstr *MI,
+						    bool &BreakPHIEdge) {
 
   // Loop over all the operands of the specified instruction.  If there is
   // anything we can't handle, bail out.
@@ -429,7 +415,6 @@
   // decide.
   MachineBasicBlock *SuccToSinkTo = 0;
 
-  bool BreakPHIEdge = false;
   for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
     const MachineOperand &MO = MI->getOperand(i);
     if (!MO.isReg()) continue;  // Ignore non-register operands.
@@ -443,23 +428,23 @@
         // and we can freely move its uses. Alternatively, if it's allocatable,
         // it could get allocated to something with a def during allocation.
         if (!MRI->def_empty(Reg))
-          return false;
+          return NULL;
 
         if (AllocatableSet.test(Reg))
-          return false;
+          return NULL;
 
         // Check for a def among the register's aliases too.
         for (const unsigned *Alias = TRI->getAliasSet(Reg); *Alias; ++Alias) {
           unsigned AliasReg = *Alias;
           if (!MRI->def_empty(AliasReg))
-            return false;
+            return NULL;
 
           if (AllocatableSet.test(AliasReg))
-            return false;
+            return NULL;
         }
       } else if (!MO.isDead()) {
         // A def that isn't dead. We can't move it.
-        return false;
+        return NULL;
       }
     } else {
       // Virtual register uses are always safe to sink.
@@ -467,7 +452,7 @@
 
       // If it's not safe to move defs of the register class, then abort.
       if (!TII->isSafeToMoveRegClassDefs(MRI->getRegClass(Reg)))
-        return false;
+        return NULL;
 
       // FIXME: This picks a successor to sink into based on having one
       // successor that dominates all the uses.  However, there are cases where
@@ -490,7 +475,7 @@
         bool LocalUse = false;
         if (!AllUsesDominatedByBlock(Reg, SuccToSinkTo, ParentBlock,
                                      BreakPHIEdge, LocalUse))
-          return false;
+          return NULL;
 
         continue;
       }
@@ -518,14 +503,39 @@
         }
         if (LocalUse)
           // Def is used locally, it's never safe to move this def.
-          return false;
+          return NULL;
       }
 
       // If we couldn't find a block to sink to, ignore this instruction.
       if (SuccToSinkTo == 0)
-        return false;
+        return NULL;
     }
   }
+  return SuccToSinkTo;
+}
+
+/// SinkInstruction - Determine whether it is safe to sink the specified machine
+/// instruction out of its current block into a successor.
+bool MachineSinking::SinkInstruction(MachineInstr *MI, bool &SawStore) {
+  // Don't sink insert_subreg, subreg_to_reg, reg_sequence. These are meant to
+  // be close to the source to make it easier to coalesce.
+  if (AvoidsSinking(MI, MRI))
+    return false;
+
+  // Check if it's safe to move the instruction.
+  if (!MI->isSafeToMove(TII, AA, SawStore))
+    return false;
+
+  // FIXME: This should include support for sinking instructions within the
+  // block they are currently in to shorten the live ranges.  We often get
+  // instructions sunk into the top of a large block, but it would be better to
+  // also sink them down before their first use in the block.  This xform has to
+  // be careful not to *increase* register pressure though, e.g. sinking
+  // "x = y + z" down if it kills y and z would increase the live ranges of y
+  // and z and only shrink the live range of x.
+
+  bool BreakPHIEdge = false;
+  MachineBasicBlock *SuccToSinkTo = FindSuccToSinkTo(MI, BreakPHIEdge);
 
   // If there are no outputs, it must have side-effects.
   if (SuccToSinkTo == 0)
@@ -546,6 +556,8 @@
 
   DEBUG(dbgs() << "Sink instr " << *MI << "\tinto block " << *SuccToSinkTo);
 
+  MachineBasicBlock *ParentBlock = MI->getParent();
+
   // If the block has multiple predecessors, this would introduce computation on
   // a path that it doesn't already exist.  We could split the critical edge,
   // but for now we just punt.



From daniel at zuster.org  Thu Dec  8 15:50:03 2011
From: daniel at zuster.org (Daniel Dunbar)
Date: Thu, 08 Dec 2011 21:50:03 -0000
Subject: [llvm-commits] [compiler-rt] r146188 -
	/compiler-rt/trunk/SDKs/linux/usr/include/sys/mman.h
Message-ID: <20111208215003.B95452A6C12C@llvm.org>

Author: ddunbar
Date: Thu Dec  8 15:50:03 2011
New Revision: 146188

URL: http://llvm.org/viewvc/llvm-project?rev=146188&view=rev
Log:
SDK/linux: Fix braindead pasto, caught by Matt Beaumont-Gay.

Modified:
    compiler-rt/trunk/SDKs/linux/usr/include/sys/mman.h

Modified: compiler-rt/trunk/SDKs/linux/usr/include/sys/mman.h
URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/SDKs/linux/usr/include/sys/mman.h?rev=146188&r1=146187&r2=146188&view=diff
==============================================================================
--- compiler-rt/trunk/SDKs/linux/usr/include/sys/mman.h (original)
+++ compiler-rt/trunk/SDKs/linux/usr/include/sys/mman.h Thu Dec  8 15:50:03 2011
@@ -20,7 +20,7 @@
 typedef __SIZE_TYPE__ size_t;
 
 #define PROT_READ 0x1
-#define PROT_WRITE 0x1
+#define PROT_WRITE 0x2
 #define PROT_EXEC 0x4
 
 extern int mprotect (void *__addr, size_t __len, int __prot)



From daniel at zuster.org  Thu Dec  8 15:53:11 2011
From: daniel at zuster.org (Daniel Dunbar)
Date: Thu, 8 Dec 2011 13:53:11 -0800
Subject: [llvm-commits] [compiler-rt] r146131 - in
 /compiler-rt/trunk/SDKs/linux: ./ README.txt usr/ usr/include/
 usr/include/endian.h usr/include/limits.h usr/include/stdio.h
 usr/include/stdlib.h usr/include/string.h usr/include/sys/
 usr/include/sys/mman
In-Reply-To: 
References: 
Message-ID: 

r146188, thanks!

 - Daniel

On Thu, Dec 8, 2011 at 9:47 AM, Matt Beaumont-Gay  wrote:
> On Wed, Dec 7, 2011 at 18:39, Daniel Dunbar  wrote:
>> Author: ddunbar
>> Date: Wed Dec ?7 20:39:23 2011
>> New Revision: 146131
>>
>> URL: http://llvm.org/viewvc/llvm-project?rev=146131&view=rev
>> Log:
>> SDKs: Sketch an initial stub SDK for Linux, I believe this suffices for building
>> the main compiler-rt and profile modules, at least on x86.
>>
>> Added:
>> ? ?compiler-rt/trunk/SDKs/linux/
>> ? ?compiler-rt/trunk/SDKs/linux/README.txt
>> ? ?compiler-rt/trunk/SDKs/linux/usr/
>> ? ?compiler-rt/trunk/SDKs/linux/usr/include/
>> ? ?compiler-rt/trunk/SDKs/linux/usr/include/endian.h
>> ? ?compiler-rt/trunk/SDKs/linux/usr/include/limits.h
>> ? ?compiler-rt/trunk/SDKs/linux/usr/include/stdio.h
>> ? ?compiler-rt/trunk/SDKs/linux/usr/include/stdlib.h
>> ? ?compiler-rt/trunk/SDKs/linux/usr/include/string.h
>> ? ?compiler-rt/trunk/SDKs/linux/usr/include/sys/
>> ? ?compiler-rt/trunk/SDKs/linux/usr/include/sys/mman.h
>> ? ?compiler-rt/trunk/SDKs/linux/usr/include/sys/stat.h
>> ? ?compiler-rt/trunk/SDKs/linux/usr/include/sys/types.h
>> ? ?compiler-rt/trunk/SDKs/linux/usr/include/unistd.h
>>
>> Added: compiler-rt/trunk/SDKs/linux/README.txt
>> URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/SDKs/linux/README.txt?rev=146131&view=auto
>> ==============================================================================
>> --- compiler-rt/trunk/SDKs/linux/README.txt (added)
>> +++ compiler-rt/trunk/SDKs/linux/README.txt Wed Dec ?7 20:39:23 2011
>> @@ -0,0 +1,2 @@
>> +This is a stub SDK for Linux. Currently, this has only been tested on i386 and
>> +x86_64 using the Clang compiler.
>>
>> Added: compiler-rt/trunk/SDKs/linux/usr/include/endian.h
>> URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/SDKs/linux/usr/include/endian.h?rev=146131&view=auto
>> ==============================================================================
>> --- compiler-rt/trunk/SDKs/linux/usr/include/endian.h (added)
>> +++ compiler-rt/trunk/SDKs/linux/usr/include/endian.h Wed Dec ?7 20:39:23 2011
>> @@ -0,0 +1,29 @@
>> +/* ===-- endian.h - stub SDK header for compiler-rt -------------------------===
>> + *
>> + * ? ? ? ? ? ? ? ? ? ? The LLVM Compiler Infrastructure
>> + *
>> + * This file is dual licensed under the MIT and the University of Illinois Open
>> + * Source Licenses. See LICENSE.TXT for details.
>> + *
>> + * ===-----------------------------------------------------------------------===
>> + *
>> + * This is a stub SDK header file. This file is not part of the interface of
>> + * this library nor an official version of the appropriate SDK header. It is
>> + * intended only to stub the features of this header required by compiler-rt.
>> + *
>> + * ===-----------------------------------------------------------------------===
>> + */
>> +
>> +#ifndef __ENDIAN_H__
>> +#define __ENDIAN_H__
>> +
>> +#define __LITTLE_ENDIAN 1234
>> +#define __BIG_ENDIAN 4321
>> +
>> +#if defined(__LITTLE_ENDIAN__) || defined(__ORDER_LITTLE_ENDIAN__)
>> +#define __BYTE_ORDER __LITTLE_ENDIAN
>> +#else
>> +#define __BYTE_ORDER __BIG_ENDIAN
>> +#endif
>> +
>> +#endif /* __ENDIAN_H__ */
>>
>> Added: compiler-rt/trunk/SDKs/linux/usr/include/limits.h
>> URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/SDKs/linux/usr/include/limits.h?rev=146131&view=auto
>> ==============================================================================
>> --- compiler-rt/trunk/SDKs/linux/usr/include/limits.h (added)
>> +++ compiler-rt/trunk/SDKs/linux/usr/include/limits.h Wed Dec ?7 20:39:23 2011
>> @@ -0,0 +1,23 @@
>> +/* ===-- limits.h - stub SDK header for compiler-rt -------------------------===
>> + *
>> + * ? ? ? ? ? ? ? ? ? ? The LLVM Compiler Infrastructure
>> + *
>> + * This file is dual licensed under the MIT and the University of Illinois Open
>> + * Source Licenses. See LICENSE.TXT for details.
>> + *
>> + * ===-----------------------------------------------------------------------===
>> + *
>> + * This is a stub SDK header file. This file is not part of the interface of
>> + * this library nor an official version of the appropriate SDK header. It is
>> + * intended only to stub the features of this header required by compiler-rt.
>> + *
>> + * ===-----------------------------------------------------------------------===
>> + */
>> +
>> +#ifndef __LIMITS_H__
>> +#define __LIMITS_H__
>> +
>> +/* This is only here as a landing pad for the include_next from the compiler's
>> + ? built-in limits.h. */
>> +
>> +#endif /* __LIMITS_H__ */
>>
>> Added: compiler-rt/trunk/SDKs/linux/usr/include/stdio.h
>> URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/SDKs/linux/usr/include/stdio.h?rev=146131&view=auto
>> ==============================================================================
>> --- compiler-rt/trunk/SDKs/linux/usr/include/stdio.h (added)
>> +++ compiler-rt/trunk/SDKs/linux/usr/include/stdio.h Wed Dec ?7 20:39:23 2011
>> @@ -0,0 +1,35 @@
>> +/* ===-- stdio.h - stub SDK header for compiler-rt --------------------------===
>> + *
>> + * ? ? ? ? ? ? ? ? ? ? The LLVM Compiler Infrastructure
>> + *
>> + * This file is dual licensed under the MIT and the University of Illinois Open
>> + * Source Licenses. See LICENSE.TXT for details.
>> + *
>> + * ===-----------------------------------------------------------------------===
>> + *
>> + * This is a stub SDK header file. This file is not part of the interface of
>> + * this library nor an official version of the appropriate SDK header. It is
>> + * intended only to stub the features of this header required by compiler-rt.
>> + *
>> + * ===-----------------------------------------------------------------------===
>> + */
>> +
>> +#ifndef __STDIO_H__
>> +#define __STDIO_H__
>> +
>> +typedef __SIZE_TYPE__ size_t;
>> +
>> +struct _IO_FILE;
>> +typedef struct _IO_FILE FILE;
>> +
>> +extern struct _IO_FILE *stdin;
>> +extern struct _IO_FILE *stdout;
>> +extern struct _IO_FILE *stderr;
>> +
>> +extern int fclose(FILE *);
>> +extern int fflush(FILE *);
>> +extern FILE *fopen(const char * restrict, const char * restrict);
>> +extern int fprintf(FILE * restrict, const char * restrict, ...);
>> +extern size_t fwrite(const void * restrict, size_t, size_t, FILE * restrict);
>> +
>> +#endif /* __STDIO_H__ */
>>
>> Added: compiler-rt/trunk/SDKs/linux/usr/include/stdlib.h
>> URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/SDKs/linux/usr/include/stdlib.h?rev=146131&view=auto
>> ==============================================================================
>> --- compiler-rt/trunk/SDKs/linux/usr/include/stdlib.h (added)
>> +++ compiler-rt/trunk/SDKs/linux/usr/include/stdlib.h Wed Dec ?7 20:39:23 2011
>> @@ -0,0 +1,32 @@
>> +/* ===-- stdlib.h - stub SDK header for compiler-rt -------------------------===
>> + *
>> + * ? ? ? ? ? ? ? ? ? ? The LLVM Compiler Infrastructure
>> + *
>> + * This file is dual licensed under the MIT and the University of Illinois Open
>> + * Source Licenses. See LICENSE.TXT for details.
>> + *
>> + * ===-----------------------------------------------------------------------===
>> + *
>> + * This is a stub SDK header file. This file is not part of the interface of
>> + * this library nor an official version of the appropriate SDK header. It is
>> + * intended only to stub the features of this header required by compiler-rt.
>> + *
>> + * ===-----------------------------------------------------------------------===
>> + */
>> +
>> +#ifndef __STDLIB_H__
>> +#define __STDLIB_H__
>> +
>> +#define NULL ((void *)0)
>> +
>> +typedef __SIZE_TYPE__ size_t;
>> +
>> +void abort(void) __attribute__((__nothrow__)) __attribute__((__noreturn__));
>> +void free(void *) __attribute__((__nothrow__));
>> +char *getenv(const char *) __attribute__((__nothrow__))
>> + ?__attribute__((__nonnull__(1)));
>> + ?__attribute__((__warn_unused_result__));
>> +void *malloc(size_t) __attribute__((__nothrow__)) __attribute((__malloc__))
>> + ? ? __attribute__((__warn_unused_result__));
>> +
>> +#endif /* __STDLIB_H__ */
>>
>> Added: compiler-rt/trunk/SDKs/linux/usr/include/string.h
>> URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/SDKs/linux/usr/include/string.h?rev=146131&view=auto
>> ==============================================================================
>> --- compiler-rt/trunk/SDKs/linux/usr/include/string.h (added)
>> +++ compiler-rt/trunk/SDKs/linux/usr/include/string.h Wed Dec ?7 20:39:23 2011
>> @@ -0,0 +1,28 @@
>> +/* ===-- string.h - stub SDK header for compiler-rt -------------------------===
>> + *
>> + * ? ? ? ? ? ? ? ? ? ? The LLVM Compiler Infrastructure
>> + *
>> + * This file is dual licensed under the MIT and the University of Illinois Open
>> + * Source Licenses. See LICENSE.TXT for details.
>> + *
>> + * ===-----------------------------------------------------------------------===
>> + *
>> + * This is a stub SDK header file. This file is not part of the interface of
>> + * this library nor an official version of the appropriate SDK header. It is
>> + * intended only to stub the features of this header required by compiler-rt.
>> + *
>> + * ===-----------------------------------------------------------------------===
>> + */
>> +
>> +#ifndef __STRING_H__
>> +#define __STRING_H__
>> +
>> +typedef __SIZE_TYPE__ size_t;
>> +
>> +char *strcat(char *, const char *);
>> +char *strcpy(char *, const char *);
>> +char *strdup(const char *);
>> +size_t strlen(const char *);
>> +char *strncpy(char *, const char *, size_t);
>> +
>> +#endif /* __STRING_H__ */
>>
>> Added: compiler-rt/trunk/SDKs/linux/usr/include/sys/mman.h
>> URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/SDKs/linux/usr/include/sys/mman.h?rev=146131&view=auto
>> ==============================================================================
>> --- compiler-rt/trunk/SDKs/linux/usr/include/sys/mman.h (added)
>> +++ compiler-rt/trunk/SDKs/linux/usr/include/sys/mman.h Wed Dec ?7 20:39:23 2011
>> @@ -0,0 +1,29 @@
>> +/* ===-- limits.h - stub SDK header for compiler-rt -------------------------===
>> + *
>> + * ? ? ? ? ? ? ? ? ? ? The LLVM Compiler Infrastructure
>> + *
>> + * This file is dual licensed under the MIT and the University of Illinois Open
>> + * Source Licenses. See LICENSE.TXT for details.
>> + *
>> + * ===-----------------------------------------------------------------------===
>> + *
>> + * This is a stub SDK header file. This file is not part of the interface of
>> + * this library nor an official version of the appropriate SDK header. It is
>> + * intended only to stub the features of this header required by compiler-rt.
>> + *
>> + * ===-----------------------------------------------------------------------===
>> + */
>> +
>> +#ifndef __SYS_MMAN_H__
>> +#define __SYS_MMAN_H__
>> +
>> +typedef __SIZE_TYPE__ size_t;
>> +
>> +#define PROT_READ 0x1
>> +#define PROT_WRITE 0x1
>
> Err, should be 0x2 I think?
>
>> +#define PROT_EXEC 0x4
>> +
>> +extern int mprotect (void *__addr, size_t __len, int __prot)
>> + ?__attribute__((__nothrow__));
>> +
>> +#endif /* __SYS_MMAN_H__ */
>>
>> Added: compiler-rt/trunk/SDKs/linux/usr/include/sys/stat.h
>> URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/SDKs/linux/usr/include/sys/stat.h?rev=146131&view=auto
>> ==============================================================================
>> --- compiler-rt/trunk/SDKs/linux/usr/include/sys/stat.h (added)
>> +++ compiler-rt/trunk/SDKs/linux/usr/include/sys/stat.h Wed Dec ?7 20:39:23 2011
>> @@ -0,0 +1,24 @@
>> +/* ===-- stat.h - stub SDK header for compiler-rt ---------------------------===
>> + *
>> + * ? ? ? ? ? ? ? ? ? ? The LLVM Compiler Infrastructure
>> + *
>> + * This file is dual licensed under the MIT and the University of Illinois Open
>> + * Source Licenses. See LICENSE.TXT for details.
>> + *
>> + * ===-----------------------------------------------------------------------===
>> + *
>> + * This is a stub SDK header file. This file is not part of the interface of
>> + * this library nor an official version of the appropriate SDK header. It is
>> + * intended only to stub the features of this header required by compiler-rt.
>> + *
>> + * ===-----------------------------------------------------------------------===
>> + */
>> +
>> +#ifndef __SYS_STAT_H__
>> +#define __SYS_STAT_H__
>> +
>> +typedef unsigned int mode_t;
>> +
>> +int mkdir(const char *, mode_t);
>> +
>> +#endif /* __SYS_STAT_H__ */
>>
>> Added: compiler-rt/trunk/SDKs/linux/usr/include/sys/types.h
>> URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/SDKs/linux/usr/include/sys/types.h?rev=146131&view=auto
>> ==============================================================================
>> --- compiler-rt/trunk/SDKs/linux/usr/include/sys/types.h (added)
>> +++ compiler-rt/trunk/SDKs/linux/usr/include/sys/types.h Wed Dec ?7 20:39:23 2011
>> @@ -0,0 +1,20 @@
>> +/* ===-- stat.h - stub SDK header for compiler-rt ---------------------------===
>> + *
>> + * ? ? ? ? ? ? ? ? ? ? The LLVM Compiler Infrastructure
>> + *
>> + * This file is dual licensed under the MIT and the University of Illinois Open
>> + * Source Licenses. See LICENSE.TXT for details.
>> + *
>> + * ===-----------------------------------------------------------------------===
>> + *
>> + * This is a stub SDK header file. This file is not part of the interface of
>> + * this library nor an official version of the appropriate SDK header. It is
>> + * intended only to stub the features of this header required by compiler-rt.
>> + *
>> + * ===-----------------------------------------------------------------------===
>> + */
>> +
>> +#ifndef __SYS_TYPES_H__
>> +#define __SYS_TYPES_H__
>> +
>> +#endif /* __SYS_TYPES_H__ */
>>
>> Added: compiler-rt/trunk/SDKs/linux/usr/include/unistd.h
>> URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/SDKs/linux/usr/include/unistd.h?rev=146131&view=auto
>> ==============================================================================
>> --- compiler-rt/trunk/SDKs/linux/usr/include/unistd.h (added)
>> +++ compiler-rt/trunk/SDKs/linux/usr/include/unistd.h Wed Dec ?7 20:39:23 2011
>> @@ -0,0 +1,26 @@
>> +/* ===-- unistd.h - stub SDK header for compiler-rt -------------------------===
>> + *
>> + * ? ? ? ? ? ? ? ? ? ? The LLVM Compiler Infrastructure
>> + *
>> + * This file is dual licensed under the MIT and the University of Illinois Open
>> + * Source Licenses. See LICENSE.TXT for details.
>> + *
>> + * ===-----------------------------------------------------------------------===
>> + *
>> + * This is a stub SDK header file. This file is not part of the interface of
>> + * this library nor an official version of the appropriate SDK header. It is
>> + * intended only to stub the features of this header required by compiler-rt.
>> + *
>> + * ===-----------------------------------------------------------------------===
>> + */
>> +
>> +#ifndef __UNISTD_H__
>> +#define __UNISTD_H__
>> +
>> +enum {
>> + ?_SC_PAGESIZE = 30
>> +};
>> +
>> +extern long int sysconf (int __name) __attribute__ ((__nothrow__));
>> +
>> +#endif /* __UNISTD_H__ */
>>
>>
>> _______________________________________________
>> llvm-commits mailing list
>> llvm-commits at cs.uiuc.edu
>> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits


From daniel at zuster.org  Thu Dec  8 15:53:53 2011
From: daniel at zuster.org (Daniel Dunbar)
Date: Thu, 8 Dec 2011 13:53:53 -0800
Subject: [llvm-commits] [llvm] r146143 - in /llvm/trunk:
 lib/Target/ARM/ARMISelLowering.cpp
 test/CodeGen/ARM/2011-11-29-128bitArithmetics.ll
In-Reply-To: <4EE12685.4020607@narod.ru>
References: <20111208075503.BA6512A6C12C@llvm.org>
	
	<4EE12685.4020607@narod.ru>
Message-ID: 

On Thu, Dec 8, 2011 at 1:05 PM, Stepan Dyatkovskiy  wrote:
> Thanks. "load" instruction is generated differently. Currently I check the
> string
> "movw r1, :lower16:A"
>
> but ppc generates
> "movw r1, :lower16:(_A-(LPC0_0+8))" instead.
>
> I can replace this check with something like this:
> ; CHECK: movw r1, :lower16:{{.*}}
>
> Or even remove it...
>
> Can I recommit it and check?

Sure, or just force the triple in the test (I haven't looked at it at all)?

 - Daniel
>
> -Stepan.
>
>
> Daniel Dunbar wrote:
>>
>> Hi Stepan,
>>
>> This is failing tests (at least on some darwin platforms). I reverted
>> it, can you take a look?
>>
>> Here is the lit output:
>> --
>> ******************** TEST 'LLVM ::
>> CodeGen/ARM/2011-11-29-128bitArithmetics.ll' FAILED
>> ********************Script:
>> --
>>
>> /Users/buildslave/zorg/buildbot/smooshlab/slave-0.8/build.clang-x86_64-darwin10-gcc42-RA/clang-build/Release+Asserts/bin/llc
>> <
>> ?/Users/buildslave/zorg/buildbot/smooshlab/slave-0.8/build.clang-x86_64-darwin10-gcc42-RA/llvm/test/CodeGen/ARM/2011-11-29-128bitArithmetics.ll
>> -march=arm -mcpu=cortex-a9 |
>>
>> /Users/buildslave/zorg/buildbot/smooshlab/slave-0.8/build.clang-x86_64-darwin10-gcc42-RA/clang-build/Release+Asserts/bin/FileCheck
>>
>> /Users/buildslave/zorg/buildbot/smooshlab/slave-0.8/build.clang-x86_64-darwin10-gcc42-RA/llvm/test/CodeGen/ARM/2011-11-29-128bitArithmetics.ll
>> --
>> Exit Code: 1
>> Command Output (stderr):
>> --
>>
>> /Users/buildslave/zorg/buildbot/smooshlab/slave-0.8/build.clang-x86_64-darwin10-gcc42-RA/llvm/test/CodeGen/ARM/2011-11-29-128bitArithmetics.ll:9:10:
>> error: expected string not found in input
>> ; CHECK: movw r1, :lower16:A
>> ? ? ? ? ?^
>> :10:13: note: scanning from here
>> _test_sqrt: @ @test_sqrt
>> ? ? ? ? ? ? ^
>> :12:2: note: possible intended match here
>> ?movw r1, :lower16:(_A-(LPC0_0+8))
>> ?^
>> --
>>
>> ********************
>> --
>>
>> ?- Daniel
>>
>>
>> On Wed, Dec 7, 2011 at 11:55 PM, Stepan Dyatkovskiy
>> ?wrote:
>>>
>>> Author: dyatkovskiy
>>> Date: Thu Dec ?8 01:55:03 2011
>>> New Revision: 146143
>>>
>>> URL: http://llvm.org/viewvc/llvm-project?rev=146143&view=rev
>>> Log:
>>> Fix bug 9905: Failure in code selection for llvm intrinsics sqrt/exp (fix
>>> for FSQRT, FSIN, FCOS, FPOWI, FPOW, FLOG, FLOG2, FLOG10, FEXP, FEXP2).
>>>
>>> Added:
>>> ? ?llvm/trunk/test/CodeGen/ARM/2011-11-29-128bitArithmetics.ll
>>> Modified:
>>> ? ?llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
>>>
>>> Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
>>> URL:
>>> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp?rev=146143&r1=146142&r2=146143&view=diff
>>>
>>> ==============================================================================
>>> --- llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp (original)
>>> +++ llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp Thu Dec ?8 01:55:03
>>> 2011
>>> @@ -468,13 +468,23 @@
>>>
>>> ? ? // v2f64 is legal so that QR subregs can be extracted as f64
>>> elements, but
>>> ? ? // neither Neon nor VFP support any arithmetic operations on it.
>>> + ? ?// The same with v4f32. But keep in mind that vadd, vsub, vmul are
>>> natively
>>> + ? ?// supported for v4f32.
>>> ? ? setOperationAction(ISD::FADD, MVT::v2f64, Expand);
>>> ? ? setOperationAction(ISD::FSUB, MVT::v2f64, Expand);
>>> ? ? setOperationAction(ISD::FMUL, MVT::v2f64, Expand);
>>> + ? ?// FIXME: Code duplication: FDIV and FREM are expanded always, see
>>> + ? ?// ARMTargetLowering::addTypeForNEON method for details.
>>> ? ? setOperationAction(ISD::FDIV, MVT::v2f64, Expand);
>>> ? ? setOperationAction(ISD::FREM, MVT::v2f64, Expand);
>>> + ? ?// FIXME: Create unittest.
>>> + ? ?// In another words, find a way when "copysign" appears in DAG with
>>> vector
>>> + ? ?// operands.
>>> ? ? setOperationAction(ISD::FCOPYSIGN, MVT::v2f64, Expand);
>>> + ? ?// FIXME: Code duplication: SETCC has custom operation action, see
>>> + ? ?// ARMTargetLowering::addTypeForNEON method for details.
>>> ? ? setOperationAction(ISD::SETCC, MVT::v2f64, Expand);
>>> + ? ?// FIXME: Create unittest for FNEG and for FABS.
>>> ? ? setOperationAction(ISD::FNEG, MVT::v2f64, Expand);
>>> ? ? setOperationAction(ISD::FABS, MVT::v2f64, Expand);
>>> ? ? setOperationAction(ISD::FSQRT, MVT::v2f64, Expand);
>>> @@ -487,11 +497,23 @@
>>> ? ? setOperationAction(ISD::FLOG10, MVT::v2f64, Expand);
>>> ? ? setOperationAction(ISD::FEXP, MVT::v2f64, Expand);
>>> ? ? setOperationAction(ISD::FEXP2, MVT::v2f64, Expand);
>>> + ? ?// FIXME: Create unittest for FCEIL, FTRUNC, FRINT, FNEARBYINT,
>>> FFLOOR.
>>> ? ? setOperationAction(ISD::FCEIL, MVT::v2f64, Expand);
>>> ? ? setOperationAction(ISD::FTRUNC, MVT::v2f64, Expand);
>>> ? ? setOperationAction(ISD::FRINT, MVT::v2f64, Expand);
>>> ? ? setOperationAction(ISD::FNEARBYINT, MVT::v2f64, Expand);
>>> ? ? setOperationAction(ISD::FFLOOR, MVT::v2f64, Expand);
>>> +
>>> + ? ?setOperationAction(ISD::FSQRT, MVT::v4f32, Expand);
>>> + ? ?setOperationAction(ISD::FSIN, MVT::v4f32, Expand);
>>> + ? ?setOperationAction(ISD::FCOS, MVT::v4f32, Expand);
>>> + ? ?setOperationAction(ISD::FPOWI, MVT::v4f32, Expand);
>>> + ? ?setOperationAction(ISD::FPOW, MVT::v4f32, Expand);
>>> + ? ?setOperationAction(ISD::FLOG, MVT::v4f32, Expand);
>>> + ? ?setOperationAction(ISD::FLOG2, MVT::v4f32, Expand);
>>> + ? ?setOperationAction(ISD::FLOG10, MVT::v4f32, Expand);
>>> + ? ?setOperationAction(ISD::FEXP, MVT::v4f32, Expand);
>>> + ? ?setOperationAction(ISD::FEXP2, MVT::v4f32, Expand);
>>>
>>> ? ? // Neon does not support some operations on v1i64 and v2i64 types.
>>> ? ? setOperationAction(ISD::MUL, MVT::v1i64, Expand);
>>>
>>> Added: llvm/trunk/test/CodeGen/ARM/2011-11-29-128bitArithmetics.ll
>>> URL:
>>> http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/2011-11-29-128bitArithmetics.ll?rev=146143&view=auto
>>>
>>> ==============================================================================
>>> --- llvm/trunk/test/CodeGen/ARM/2011-11-29-128bitArithmetics.ll (added)
>>> +++ llvm/trunk/test/CodeGen/ARM/2011-11-29-128bitArithmetics.ll Thu Dec
>>> ?8 01:55:03 2011
>>> @@ -0,0 +1,302 @@
>>> +; RUN: llc< ?%s -march=arm -mcpu=cortex-a9 | FileCheck %s
>>> +
>>> + at A = global<4 x float> ?
>>> +
>>> +define void @test_sqrt(<4 x float>* %X) nounwind {
>>> +
>>> +; CHECK: test_sqrt:
>>> +
>>> +; CHECK: ? ? ?movw ? ?r1, :lower16:A
>>> +; CHECK-NEXT: movt ? ?r1, :upper16:A
>>> +; CHECK: ? ? ?vldmia ?r1, {[[short0:s[0-9]+]], [[short1:s[0-9]+]],
>>> [[short2:s[0-9]+]], [[short3:s[0-9]+]]}
>>> +; CHECK: ? ? ?vsqrt.f32 ? ? ? {{s[0-9]+}}, [[short3]]
>>> +; CHECK: ? ? ?vsqrt.f32 ? ? ? {{s[0-9]+}}, [[short2]]
>>> +; CHECK: ? ? ?vsqrt.f32 ? ? ? {{s[0-9]+}}, [[short1]]
>>> +; CHECK: ? ? ?vsqrt.f32 ? ? ? {{s[0-9]+}}, [[short0]]
>>> +; CHECK-NEXT: vstmia ?{{.*}}
>>> +
>>> +L.entry:
>>> + ?%0 = load<4 x float>* @A, align 16
>>> + ?%1 = call<4 x float> ?@llvm.sqrt.v4f32(<4 x float> ?%0)
>>> + ?store<4 x float> ?%1,<4 x float>* %X, align 16
>>> + ?ret void
>>> +}
>>> +
>>> +declare<4 x float> ?@llvm.sqrt.v4f32(<4 x float>) nounwind readonly
>>> +
>>> +
>>> +define void @test_cos(<4 x float>* %X) nounwind {
>>> +
>>> +; CHECK: test_cos:
>>> +
>>> +; CHECK: ? ? ?movw ?[[reg0:r[0-9]+]], :lower16:A
>>> +; CHECK-NEXT: movt ?[[reg0]], :upper16:A
>>> +; CHECK: ? ? ?vldmia [[reg0]], {{.*}}
>>> +
>>> +; CHECK: ? ? ?{{[v]?mov}} ?r0, {{[r|s][0-9]+}}
>>> +; CHECK: ? ? ?bl ?cosf
>>> +
>>> +; CHECK: ? ? ?{{[v]?mov}} ?r0, {{[r|s][0-9]+}}
>>> +; CHECK: ? ? ?bl ?cosf
>>> +
>>> +; CHECK: ? ? ?{{[v]?mov}} ?r0, {{[r|s][0-9]+}}
>>> +; CHECK: ? ? ?bl ?cosf
>>> +
>>> +; CHECK: ? ? ?{{[v]?mov}} ?r0, {{[r|s][0-9]+}}
>>> +; CHECK: ? ? ?bl ?cosf
>>> +
>>> +; CHECK: ? ? ?vstmia ?{{.*}}
>>> +
>>> +L.entry:
>>> + ?%0 = load<4 x float>* @A, align 16
>>> + ?%1 = call<4 x float> ?@llvm.cos.v4f32(<4 x float> ?%0)
>>> + ?store<4 x float> ?%1,<4 x float>* %X, align 16
>>> + ?ret void
>>> +}
>>> +
>>> +declare<4 x float> ?@llvm.cos.v4f32(<4 x float>) nounwind readonly
>>> +
>>> +define void @test_exp(<4 x float>* %X) nounwind {
>>> +
>>> +; CHECK: test_exp:
>>> +
>>> +; CHECK: ? ? ?movw ?[[reg0:r[0-9]+]], :lower16:A
>>> +; CHECK-NEXT: movt ?[[reg0]], :upper16:A
>>> +; CHECK: ? ? ?vldmia [[reg0]], {{.*}}
>>> +
>>> +; CHECK: ? ? ?{{[v]?mov}} ?r0, {{[r|s][0-9]+}}
>>> +; CHECK: ? ? ?bl ?expf
>>> +
>>> +; CHECK: ? ? ?{{[v]?mov}} ?r0, {{[r|s][0-9]+}}
>>> +; CHECK: ? ? ?bl ?expf
>>> +
>>> +; CHECK: ? ? ?{{[v]?mov}} ?r0, {{[r|s][0-9]+}}
>>> +; CHECK: ? ? ?bl ?expf
>>> +
>>> +; CHECK: ? ? ?{{[v]?mov}} ?r0, {{[r|s][0-9]+}}
>>> +; CHECK: ? ? ?bl ?expf
>>> +
>>> +; CHECK: ? ? ?vstmia ?{{.*}}
>>> +
>>> +L.entry:
>>> + ?%0 = load<4 x float>* @A, align 16
>>> + ?%1 = call<4 x float> ?@llvm.exp.v4f32(<4 x float> ?%0)
>>> + ?store<4 x float> ?%1,<4 x float>* %X, align 16
>>> + ?ret void
>>> +}
>>> +
>>> +declare<4 x float> ?@llvm.exp.v4f32(<4 x float>) nounwind readonly
>>> +
>>> +define void @test_exp2(<4 x float>* %X) nounwind {
>>> +
>>> +; CHECK: test_exp2:
>>> +
>>> +; CHECK: ? ? ?movw ?[[reg0:r[0-9]+]], :lower16:A
>>> +; CHECK-NEXT: movt ?[[reg0]], :upper16:A
>>> +; CHECK: ? ? ?vldmia [[reg0]], {{.*}}
>>> +
>>> +; CHECK: ? ? ?{{[v]?mov}} ?r0, {{[r|s][0-9]+}}
>>> +; CHECK: ? ? ?bl ?exp2f
>>> +
>>> +; CHECK: ? ? ?{{[v]?mov}} ?r0, {{[r|s][0-9]+}}
>>> +; CHECK: ? ? ?bl ?exp2f
>>> +
>>> +; CHECK: ? ? ?{{[v]?mov}} ?r0, {{[r|s][0-9]+}}
>>> +; CHECK: ? ? ?bl ?exp2f
>>> +
>>> +; CHECK: ? ? ?{{[v]?mov}} ?r0, {{[r|s][0-9]+}}
>>> +; CHECK: ? ? ?bl ?exp2f
>>> +
>>> +; CHECK: ? ? ?vstmia ?{{.*}}
>>> +
>>> +L.entry:
>>> + ?%0 = load<4 x float>* @A, align 16
>>> + ?%1 = call<4 x float> ?@llvm.exp2.v4f32(<4 x float> ?%0)
>>> + ?store<4 x float> ?%1,<4 x float>* %X, align 16
>>> + ?ret void
>>> +}
>>> +
>>> +declare<4 x float> ?@llvm.exp2.v4f32(<4 x float>) nounwind readonly
>>> +
>>> +define void @test_log10(<4 x float>* %X) nounwind {
>>> +
>>> +; CHECK: test_log10:
>>> +
>>> +; CHECK: ? ? ?movw ?[[reg0:r[0-9]+]], :lower16:A
>>> +; CHECK-NEXT: movt ?[[reg0]], :upper16:A
>>> +; CHECK: ? ? ?vldmia [[reg0]], {{.*}}
>>> +
>>> +; CHECK: ? ? ?{{[v]?mov}} ?r0, {{[r|s][0-9]+}}
>>> +; CHECK: ? ? ?bl ?log10f
>>> +
>>> +; CHECK: ? ? ?{{[v]?mov}} ?r0, {{[r|s][0-9]+}}
>>> +; CHECK: ? ? ?bl ?log10f
>>> +
>>> +; CHECK: ? ? ?{{[v]?mov}} ?r0, {{[r|s][0-9]+}}
>>> +; CHECK: ? ? ?bl ?log10f
>>> +
>>> +; CHECK: ? ? ?{{[v]?mov}} ?r0, {{[r|s][0-9]+}}
>>> +; CHECK: ? ? ?bl ?log10f
>>> +
>>> +; CHECK: ? ? ?vstmia ?{{.*}}
>>> +
>>> +L.entry:
>>> + ?%0 = load<4 x float>* @A, align 16
>>> + ?%1 = call<4 x float> ?@llvm.log10.v4f32(<4 x float> ?%0)
>>> + ?store<4 x float> ?%1,<4 x float>* %X, align 16
>>> + ?ret void
>>> +}
>>> +
>>> +declare<4 x float> ?@llvm.log10.v4f32(<4 x float>) nounwind readonly
>>> +
>>> +define void @test_log(<4 x float>* %X) nounwind {
>>> +
>>> +; CHECK: test_log:
>>> +
>>> +; CHECK: ? ? ?movw ?[[reg0:r[0-9]+]], :lower16:A
>>> +; CHECK-NEXT: movt ?[[reg0]], :upper16:A
>>> +; CHECK: ? ? ?vldmia [[reg0]], {{.*}}
>>> +
>>> +; CHECK: ? ? ?{{[v]?mov}} ?r0, {{[r|s][0-9]+}}
>>> +; CHECK: ? ? ?bl ?logf
>>> +
>>> +; CHECK: ? ? ?{{[v]?mov}} ?r0, {{[r|s][0-9]+}}
>>> +; CHECK: ? ? ?bl ?logf
>>> +
>>> +; CHECK: ? ? ?{{[v]?mov}} ?r0, {{[r|s][0-9]+}}
>>> +; CHECK: ? ? ?bl ?logf
>>> +
>>> +; CHECK: ? ? ?{{[v]?mov}} ?r0, {{[r|s][0-9]+}}
>>> +; CHECK: ? ? ?bl ?logf
>>> +
>>> +; CHECK: ? ? ?vstmia ?{{.*}}
>>> +
>>> +L.entry:
>>> + ?%0 = load<4 x float>* @A, align 16
>>> + ?%1 = call<4 x float> ?@llvm.log.v4f32(<4 x float> ?%0)
>>> + ?store<4 x float> ?%1,<4 x float>* %X, align 16
>>> + ?ret void
>>> +}
>>> +
>>> +declare<4 x float> ?@llvm.log.v4f32(<4 x float>) nounwind readonly
>>> +
>>> +define void @test_log2(<4 x float>* %X) nounwind {
>>> +
>>> +; CHECK: test_log2:
>>> +
>>> +; CHECK: ? ? ?movw ?[[reg0:r[0-9]+]], :lower16:A
>>> +; CHECK-NEXT: movt ?[[reg0]], :upper16:A
>>> +; CHECK: ? ? ?vldmia [[reg0]], {{.*}}
>>> +
>>> +; CHECK: ? ? ?{{[v]?mov}} ?r0, {{[r|s][0-9]+}}
>>> +; CHECK: ? ? ?bl ?log2f
>>> +
>>> +; CHECK: ? ? ?{{[v]?mov}} ?r0, {{[r|s][0-9]+}}
>>> +; CHECK: ? ? ?bl ?log2f
>>> +
>>> +; CHECK: ? ? ?{{[v]?mov}} ?r0, {{[r|s][0-9]+}}
>>> +; CHECK: ? ? ?bl ?log2f
>>> +
>>> +; CHECK: ? ? ?{{[v]?mov}} ?r0, {{[r|s][0-9]+}}
>>> +; CHECK: ? ? ?bl ?log2f
>>> +
>>> +; CHECK: ? ? ?vstmia ?{{.*}}
>>> +
>>> +L.entry:
>>> + ?%0 = load<4 x float>* @A, align 16
>>> + ?%1 = call<4 x float> ?@llvm.log2.v4f32(<4 x float> ?%0)
>>> + ?store<4 x float> ?%1,<4 x float>* %X, align 16
>>> + ?ret void
>>> +}
>>> +
>>> +declare<4 x float> ?@llvm.log2.v4f32(<4 x float>) nounwind readonly
>>> +
>>> +
>>> +define void @test_pow(<4 x float>* %X) nounwind {
>>> +
>>> +; CHECK: test_pow:
>>> +
>>> +; CHECK: ? ? ?movw ?[[reg0:r[0-9]+]], :lower16:A
>>> +; CHECK-NEXT: movt ?[[reg0]], :upper16:A
>>> +; CHECK: ? ? ?vldmia [[reg0]], {{.*}}
>>> +
>>> +; CHECK: ? ? ?{{[v]?mov}} ?r0, {{[r|s][0-9]+}}
>>> +; CHECK: ? ? ?bl ?powf
>>> +
>>> +; CHECK: ? ? ?{{[v]?mov}} ?r0, {{[r|s][0-9]+}}
>>> +; CHECK: ? ? ?bl ?powf
>>> +
>>> +; CHECK: ? ? ?{{[v]?mov}} ?r0, {{[r|s][0-9]+}}
>>> +; CHECK: ? ? ?bl ?powf
>>> +
>>> +; CHECK: ? ? ?{{[v]?mov}} ?r0, {{[r|s][0-9]+}}
>>> +; CHECK: ? ? ?bl ?powf
>>> +
>>> +; CHECK: ? ? ?vstmia ?{{.*}}
>>> +
>>> +L.entry:
>>> +
>>> + ?%0 = load<4 x float>* @A, align 16
>>> + ?%1 = call<4 x float> ?@llvm.pow.v4f32(<4 x float> ?%0,<4 x float>
>>> ?)
>>> +
>>> + ?store<4 x float> ?%1,<4 x float>* %X, align 16
>>> +
>>> + ?ret void
>>> +}
>>> +
>>> +declare<4 x float> ?@llvm.pow.v4f32(<4 x float>,<4 x float>) nounwind
>>> readonly
>>> +
>>> +define void @test_powi(<4 x float>* %X) nounwind {
>>> +
>>> +; CHECK: test_powi:
>>> +
>>> +; CHECK: ? ? ? movw ?[[reg0:r[0-9]+]], :lower16:A
>>> +; CHECK-NEXT: ?movt ?[[reg0]], :upper16:A
>>> +; CHECK-NEXT: ?vldmia ?[[reg0]], {{.*}}
>>> +; CHECK: ? ? ? vmul.f32 {{.*}}
>>> +
>>> +; CHECK: ? ? ?vstmia ?{{.*}}
>>> +
>>> +L.entry:
>>> +
>>> + ?%0 = load<4 x float>* @A, align 16
>>> + ?%1 = call<4 x float> ?@llvm.powi.v4f32(<4 x float> ?%0, i32 2)
>>> +
>>> + ?store<4 x float> ?%1,<4 x float>* %X, align 16
>>> +
>>> + ?ret void
>>> +}
>>> +
>>> +declare<4 x float> ?@llvm.powi.v4f32(<4 x float>, i32) nounwind readonly
>>> +
>>> +define void @test_sin(<4 x float>* %X) nounwind {
>>> +
>>> +; CHECK: test_sin:
>>> +
>>> +; CHECK: ? ? ?movw ?[[reg0:r[0-9]+]], :lower16:A
>>> +; CHECK-NEXT: movt ?[[reg0]], :upper16:A
>>> +; CHECK: ? ? ?vldmia [[reg0]], {{.*}}
>>> +
>>> +; CHECK: ? ? ?{{[v]?mov}} ?r0, {{[r|s][0-9]+}}
>>> +; CHECK: ? ? ?bl ?sinf
>>> +
>>> +; CHECK: ? ? ?{{[v]?mov}} ?r0, {{[r|s][0-9]+}}
>>> +; CHECK: ? ? ?bl ?sinf
>>> +
>>> +; CHECK: ? ? ?{{[v]?mov}} ?r0, {{[r|s][0-9]+}}
>>> +; CHECK: ? ? ?bl ?sinf
>>> +
>>> +; CHECK: ? ? ?{{[v]?mov}} ?r0, {{[r|s][0-9]+}}
>>> +; CHECK: ? ? ?bl ?sinf
>>> +
>>> +; CHECK: ? ? ?vstmia ?{{.*}}
>>> +
>>> +L.entry:
>>> + ?%0 = load<4 x float>* @A, align 16
>>> + ?%1 = call<4 x float> ?@llvm.sin.v4f32(<4 x float> ?%0)
>>> + ?store<4 x float> ?%1,<4 x float>* %X, align 16
>>> + ?ret void
>>> +}
>>> +
>>> +declare<4 x float> ?@llvm.sin.v4f32(<4 x float>) nounwind readonly
>>> +
>>>
>>>
>>> _______________________________________________
>>> llvm-commits mailing list
>>> llvm-commits at cs.uiuc.edu
>>> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
>
>


From grosbach at apple.com  Thu Dec  8 16:04:41 2011
From: grosbach at apple.com (Jim Grosbach)
Date: Thu, 08 Dec 2011 22:04:41 -0000
Subject: [llvm-commits] [llvm] r146190 -
	/llvm/trunk/test/MC/ARM/neon-shift-encoding.s
Message-ID: <20111208220441.1A38A2A6C12C@llvm.org>

Author: grosbach
Date: Thu Dec  8 16:04:40 2011
New Revision: 146190

URL: http://llvm.org/viewvc/llvm-project?rev=146190&view=rev
Log:
Tidy up a bit.

Modified:
    llvm/trunk/test/MC/ARM/neon-shift-encoding.s

Modified: llvm/trunk/test/MC/ARM/neon-shift-encoding.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/neon-shift-encoding.s?rev=146190&r1=146189&r2=146190&view=diff
==============================================================================
--- llvm/trunk/test/MC/ARM/neon-shift-encoding.s (original)
+++ llvm/trunk/test/MC/ARM/neon-shift-encoding.s Thu Dec  8 16:04:40 2011
@@ -1,70 +1,75 @@
 @ RUN: llvm-mc -mcpu=cortex-a8 -triple arm-unknown-unknown -show-encoding < %s | FileCheck %s
 
 _foo:
-@ CHECK: vshl.u8	d16, d17, d16  @ encoding: [0xa1,0x04,0x40,0xf3]
 	vshl.u8	d16, d17, d16
-@ CHECK: vshl.u16	d16, d17, d16  @ encoding: [0xa1,0x04,0x50,0xf3]
 	vshl.u16	d16, d17, d16
-@ CHECK: vshl.u32	d16, d17, d16  @ encoding: [0xa1,0x04,0x60,0xf3]
 	vshl.u32	d16, d17, d16
-@ CHECK: vshl.u64	d16, d17, d16  @ encoding: [0xa1,0x04,0x70,0xf3]
 	vshl.u64	d16, d17, d16
-@ CHECK: vshl.i8	d16, d16, #7  @ encoding: [0x30,0x05,0xcf,0xf2]
 	vshl.i8	d16, d16, #7
-@ CHECK: vshl.i16	d16, d16, #15  @ encoding: [0x30,0x05,0xdf,0xf2]
 	vshl.i16	d16, d16, #15
-@ CHECK: vshl.i32	d16, d16, #31  @ encoding: [0x30,0x05,0xff,0xf2]
 	vshl.i32	d16, d16, #31
-@ CHECK: vshl.i64	d16, d16, #63  @ encoding: [0xb0,0x05,0xff,0xf2]
 	vshl.i64	d16, d16, #63
-@ CHECK: vshl.u8	q8, q9, q8  @ encoding: [0xe2,0x04,0x40,0xf3]
 	vshl.u8	q8, q9, q8
-@ CHECK: vshl.u16	q8, q9, q8  @ encoding: [0xe2,0x04,0x50,0xf3]
 	vshl.u16	q8, q9, q8
-@ CHECK: vshl.u32	q8, q9, q8  @ encoding: [0xe2,0x04,0x60,0xf3]
 	vshl.u32	q8, q9, q8
-@ CHECK: vshl.u64	q8, q9, q8  @ encoding: [0xe2,0x04,0x70,0xf3]
 	vshl.u64	q8, q9, q8
-@ CHECK: vshl.i8	q8, q8, #7  @ encoding: [0x70,0x05,0xcf,0xf2]
 	vshl.i8	q8, q8, #7
-@ CHECK: vshl.i16	q8, q8, #15  @ encoding: [0x70,0x05,0xdf,0xf2]
 	vshl.i16	q8, q8, #15
-@ CHECK: vshl.i32	q8, q8, #31  @ encoding: [0x70,0x05,0xff,0xf2]
 	vshl.i32	q8, q8, #31
-@ CHECK: vshl.i64	q8, q8, #63  @ encoding: [0xf0,0x05,0xff,0xf2]
 	vshl.i64	q8, q8, #63
-@ CHECK: vshr.u8	d16, d16, #7  @ encoding: [0x30,0x00,0xc9,0xf3]
+
+@ CHECK: vshl.u8	d16, d17, d16  @ encoding: [0xa1,0x04,0x40,0xf3]
+@ CHECK: vshl.u16	d16, d17, d16  @ encoding: [0xa1,0x04,0x50,0xf3]
+@ CHECK: vshl.u32	d16, d17, d16  @ encoding: [0xa1,0x04,0x60,0xf3]
+@ CHECK: vshl.u64	d16, d17, d16  @ encoding: [0xa1,0x04,0x70,0xf3]
+@ CHECK: vshl.i8	d16, d16, #7  @ encoding: [0x30,0x05,0xcf,0xf2]
+@ CHECK: vshl.i16	d16, d16, #15  @ encoding: [0x30,0x05,0xdf,0xf2]
+@ CHECK: vshl.i32	d16, d16, #31  @ encoding: [0x30,0x05,0xff,0xf2]
+@ CHECK: vshl.i64	d16, d16, #63  @ encoding: [0xb0,0x05,0xff,0xf2]
+@ CHECK: vshl.u8	q8, q9, q8  @ encoding: [0xe2,0x04,0x40,0xf3]
+@ CHECK: vshl.u16	q8, q9, q8  @ encoding: [0xe2,0x04,0x50,0xf3]
+@ CHECK: vshl.u32	q8, q9, q8  @ encoding: [0xe2,0x04,0x60,0xf3]
+@ CHECK: vshl.u64	q8, q9, q8  @ encoding: [0xe2,0x04,0x70,0xf3]
+@ CHECK: vshl.i8	q8, q8, #7  @ encoding: [0x70,0x05,0xcf,0xf2]
+@ CHECK: vshl.i16	q8, q8, #15  @ encoding: [0x70,0x05,0xdf,0xf2]
+@ CHECK: vshl.i32	q8, q8, #31  @ encoding: [0x70,0x05,0xff,0xf2]
+@ CHECK: vshl.i64	q8, q8, #63  @ encoding: [0xf0,0x05,0xff,0xf2]
+
+
 	vshr.u8	d16, d16, #7
-@ CHECK: vshr.u16	d16, d16, #15  @ encoding: [0x30,0x00,0xd1,0xf3]
 	vshr.u16	d16, d16, #15
-@ CHECK: vshr.u32	d16, d16, #31  @ encoding: [0x30,0x00,0xe1,0xf3]
 	vshr.u32	d16, d16, #31
-@ CHECK: vshr.u64	d16, d16, #63  @ encoding: [0xb0,0x00,0xc1,0xf3]
 	vshr.u64	d16, d16, #63
-@ CHECK: vshr.u8	q8, q8, #7  @ encoding: [0x70,0x00,0xc9,0xf3]
 	vshr.u8	q8, q8, #7
-@ CHECK: vshr.u16	q8, q8, #15  @ encoding: [0x70,0x00,0xd1,0xf3]
 	vshr.u16	q8, q8, #15
-@ CHECK: vshr.u32	q8, q8, #31  @ encoding: [0x70,0x00,0xe1,0xf3]
 	vshr.u32	q8, q8, #31
-@ CHECK: vshr.u64	q8, q8, #63  @ encoding: [0xf0,0x00,0xc1,0xf3]
 	vshr.u64	q8, q8, #63
-@ CHECK: vshr.s8	d16, d16, #7  @ encoding: [0x30,0x00,0xc9,0xf2]
 	vshr.s8	d16, d16, #7
-@ CHECK: vshr.s16	d16, d16, #15  @ encoding: [0x30,0x00,0xd1,0xf2]
 	vshr.s16	d16, d16, #15
-@ CHECK: vshr.s32	d16, d16, #31  @ encoding: [0x30,0x00,0xe1,0xf2]
 	vshr.s32	d16, d16, #31
-@ CHECK: vshr.s64	d16, d16, #63  @ encoding: [0xb0,0x00,0xc1,0xf2]
 	vshr.s64	d16, d16, #63
-@ CHECK: vshr.s8	q8, q8, #7  @ encoding: [0x70,0x00,0xc9,0xf2]
 	vshr.s8	q8, q8, #7
-@ CHECK: vshr.s16	q8, q8, #15  @ encoding: [0x70,0x00,0xd1,0xf2]
 	vshr.s16	q8, q8, #15
-@ CHECK: vshr.s32	q8, q8, #31  @ encoding: [0x70,0x00,0xe1,0xf2]
 	vshr.s32	q8, q8, #31
-@ CHECK: vshr.s64	q8, q8, #63  @ encoding: [0xf0,0x00,0xc1,0xf2]
 	vshr.s64	q8, q8, #63
+
+@ CHECK: vshr.u8	d16, d16, #7  @ encoding: [0x30,0x00,0xc9,0xf3]
+@ CHECK: vshr.u16	d16, d16, #15  @ encoding: [0x30,0x00,0xd1,0xf3]
+@ CHECK: vshr.u32	d16, d16, #31  @ encoding: [0x30,0x00,0xe1,0xf3]
+@ CHECK: vshr.u64	d16, d16, #63  @ encoding: [0xb0,0x00,0xc1,0xf3]
+@ CHECK: vshr.u8	q8, q8, #7  @ encoding: [0x70,0x00,0xc9,0xf3]
+@ CHECK: vshr.u16	q8, q8, #15  @ encoding: [0x70,0x00,0xd1,0xf3]
+@ CHECK: vshr.u32	q8, q8, #31  @ encoding: [0x70,0x00,0xe1,0xf3]
+@ CHECK: vshr.u64	q8, q8, #63  @ encoding: [0xf0,0x00,0xc1,0xf3]
+@ CHECK: vshr.s8	d16, d16, #7  @ encoding: [0x30,0x00,0xc9,0xf2]
+@ CHECK: vshr.s16	d16, d16, #15  @ encoding: [0x30,0x00,0xd1,0xf2]
+@ CHECK: vshr.s32	d16, d16, #31  @ encoding: [0x30,0x00,0xe1,0xf2]
+@ CHECK: vshr.s64	d16, d16, #63  @ encoding: [0xb0,0x00,0xc1,0xf2]
+@ CHECK: vshr.s8	q8, q8, #7  @ encoding: [0x70,0x00,0xc9,0xf2]
+@ CHECK: vshr.s16	q8, q8, #15  @ encoding: [0x70,0x00,0xd1,0xf2]
+@ CHECK: vshr.s32	q8, q8, #31  @ encoding: [0x70,0x00,0xe1,0xf2]
+@ CHECK: vshr.s64	q8, q8, #63  @ encoding: [0xf0,0x00,0xc1,0xf2]
+
 @ CHECK: vsra.u8  d16, d16, #7   @ encoding: [0x30,0x01,0xc9,0xf3]
 	vsra.u8   d16, d16, #7
 @ CHECK: vsra.u16 d16, d16, #15  @ encoding: [0x30,0x01,0xd1,0xf3]



From evan.cheng at apple.com  Thu Dec  8 16:05:28 2011
From: evan.cheng at apple.com (Evan Cheng)
Date: Thu, 08 Dec 2011 22:05:28 -0000
Subject: [llvm-commits] [llvm] r146191 - in /llvm/trunk:
 lib/Target/X86/X86InstrSSE.td test/CodeGen/X86/2011-12-08-AVXISelBugs.ll
Message-ID: <20111208220528.DA5C22A6C12C@llvm.org>

Author: evancheng
Date: Thu Dec  8 16:05:28 2011
New Revision: 146191

URL: http://llvm.org/viewvc/llvm-project?rev=146191&view=rev
Log:
Add various missing AVX patterns which was causing crashes. Sadly, the generated
code looks pretty bad compared to SSE.

rdar://10538793

Added:
    llvm/trunk/test/CodeGen/X86/2011-12-08-AVXISelBugs.ll
Modified:
    llvm/trunk/lib/Target/X86/X86InstrSSE.td

Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrSSE.td?rev=146191&r1=146190&r2=146191&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrSSE.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrSSE.td Thu Dec  8 16:05:28 2011
@@ -561,6 +561,16 @@
                       (EXTRACT_SUBREG (v4i32 VR128:$src), sub_ss))>;
   def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector FR64:$src)))),
             (VMOVSDrr (v2f64 (V_SET0)), FR64:$src)>;
+
+  // Move low f32 and clear high bits.
+  def : Pat<(v8f32 (X86vzmovl (v8f32 VR256:$src))),
+            (SUBREG_TO_REG (i32 0),
+              (VMOVSSrr (v4f32 (V_SET0)),
+                        (EXTRACT_SUBREG (v8f32 VR256:$src), sub_ss)), sub_xmm)>;
+  def : Pat<(v8i32 (X86vzmovl (v8i32 VR256:$src))),
+            (SUBREG_TO_REG (i32 0),
+              (VMOVSSrr (v4i32 (V_SET0)),
+                        (EXTRACT_SUBREG (v8i32 VR256:$src), sub_ss)), sub_xmm)>;
   }
 
   let AddedComplexity = 20 in {
@@ -588,6 +598,9 @@
 
   // Represent the same patterns above but in the form they appear for
   // 256-bit types
+  def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
+                   (v4i32 (scalar_to_vector (loadi32 addr:$src))), (i32 0)))),
+            (SUBREG_TO_REG (i32 0), (VMOVSSrm addr:$src), sub_ss)>;
   def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
                    (v4f32 (scalar_to_vector (loadf32 addr:$src))), (i32 0)))),
             (SUBREG_TO_REG (i32 0), (VMOVSSrm addr:$src), sub_ss)>;
@@ -606,6 +619,12 @@
                            (v2f64 (VMOVSDrr (v2f64 (V_SET0)), FR64:$src)),
                            sub_xmm)>;
 
+  // Move low f64 and clear high bits.
+  def : Pat<(v4f64 (X86vzmovl (v4f64 VR256:$src))),
+            (SUBREG_TO_REG (i32 0),
+              (VMOVSDrr (v2f64 (V_SET0)),
+                        (EXTRACT_SUBREG (v4f64 VR256:$src), sub_sd)), sub_xmm)>;
+
   // Extract and store.
   def : Pat<(store (f32 (vector_extract (v4f32 VR128:$src), (iPTR 0))),
                    addr:$dst),
@@ -756,6 +775,19 @@
                             "movupd\t{$src, $dst|$dst, $src}", []>, VEX;
 }
 
+let Predicates = [HasAVX] in {
+def : Pat<(v8i32 (X86vzmovl
+                        (insert_subvector undef, (v4i32 VR128:$src), (i32 0)))),
+          (SUBREG_TO_REG (i32 0), (VMOVAPSrr VR128:$src), sub_xmm)>;
+def : Pat<(v8f32 (X86vzmovl
+                        (insert_subvector undef, (v4f32 VR128:$src), (i32 0)))),
+          (SUBREG_TO_REG (i32 0), (VMOVAPSrr VR128:$src), sub_xmm)>;
+def : Pat<(v4f64 (X86vzmovl
+                        (insert_subvector undef, (v2f64 VR128:$src), (i32 0)))),
+          (SUBREG_TO_REG (i32 0), (VMOVAPSrr VR128:$src), sub_xmm)>;
+}
+
+
 def : Pat<(int_x86_avx_loadu_ps_256 addr:$src), (VMOVUPSYrm addr:$src)>;
 def : Pat<(int_x86_avx_storeu_ps_256 addr:$dst, VR256:$src),
           (VMOVUPSYmr addr:$dst, VR256:$src)>;

Added: llvm/trunk/test/CodeGen/X86/2011-12-08-AVXISelBugs.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2011-12-08-AVXISelBugs.ll?rev=146191&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/X86/2011-12-08-AVXISelBugs.ll (added)
+++ llvm/trunk/test/CodeGen/X86/2011-12-08-AVXISelBugs.ll Thu Dec  8 16:05:28 2011
@@ -0,0 +1,63 @@
+; RUN: llc < %s -mcpu=corei7-avx -mattr=+avx
+; Various missing patterns causing crashes.
+; rdar://10538793
+
+define void @t1() nounwind {
+entry:
+  br label %loop.cond
+
+loop.cond:                                        ; preds = %t1.exit, %entry
+  br i1 false, label %return, label %loop
+
+loop:                                             ; preds = %loop.cond
+  br i1 undef, label %0, label %t1.exit
+
+;