We have changed the way that the Type Legalizer legalizes vectors. + The type legalizer now attempts to promote integer elements. + This enabled the implementation of vector-select. + Additionally, we see a performance boost on workloads which use vectors of chars and shorts, since they are now promoted + to 32-bit types, which are better supported by the SIMD instruction set. + Floating point types are still widened as before.

+ +

We have put a significant amount of work into the code generator infrastructure, which allows us to implement more aggressive algorithms and make it run faster:

@@ -355,6 +364,8 @@

New features and major changes in the X86 target include:

Bug fixes and improved support for AVX1
Support for AVX2 (still incomplete at this point)
....

From dblaikie at gmail.com Tue Dec 20 02:22:50 2011 From: dblaikie at gmail.com (David Blaikie) Date: Tue, 20 Dec 2011 08:22:50 -0000 Subject: [llvm-commits] [llvm] r146965 - /llvm/trunk/utils/TableGen/TGValueTypes.cpp Message-ID: <20111220082250.34EA21BE003@llvm.org> Author: dblaikie Date: Tue Dec 20 02:22:49 2011 New Revision: 146965 URL: http://llvm.org/viewvc/llvm-project?rev=146965&view=rev Log: Revert pragma clang suppressions that confuse GCC. (I'll worry about how to suppress/fix these problems properly when we figure out how to keep LLVM -Wweak-vtables clean) Modified: llvm/trunk/utils/TableGen/TGValueTypes.cpp Modified: llvm/trunk/utils/TableGen/TGValueTypes.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/TGValueTypes.cpp?rev=146965&r1=146964&r2=146965&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/TGValueTypes.cpp (original) +++ llvm/trunk/utils/TableGen/TGValueTypes.cpp Tue Dec 20 02:22:49 2011 @@ -18,9 +18,6 @@ #include using namespace llvm; -#pragma clang diagnostic push -#pragma clang diagnostic ignored "-Wweak-vtables" - namespace llvm { class Type { @@ -61,8 +58,6 @@ } }; -#pragma clang diagnostic pop - static std::map ExtendedIntegerTypeMap; static std::map, const Type *> From chandlerc at gmail.com Tue Dec 20 02:42:12 2011 From: chandlerc at gmail.com (Chandler Carruth) Date: Tue, 20 Dec 2011 08:42:12 -0000 Subject: [llvm-commits] [llvm] r146966 - in /llvm/trunk: lib/CodeGen/ lib/ExecutionEngine/MCJIT/ lib/Support/ lib/TableGen/ lib/Target/ lib/Target/ARM/ lib/Target/CellSPU/ lib/Target/MBlaze/ lib/Target/MSP430/ lib/Target/Mips/ lib/Target/PTX/ lib/Target/PowerPC/ lib/Target/Sparc/ lib/Target/X86/ lib/Target/XCore/ utils/TableGen/ Message-ID: <20111220084214.7E3AA1BE003@llvm.org> Author: chandlerc Date: Tue Dec 20 02:42:11 2011 New Revision: 146966 URL: http://llvm.org/viewvc/llvm-project?rev=146966&view=rev Log: Fix up the CMake build for the new files added in r146960, they're likely to stay either way that discussion ends up resolving itself. Modified: llvm/trunk/lib/CodeGen/CMakeLists.txt llvm/trunk/lib/ExecutionEngine/MCJIT/CMakeLists.txt llvm/trunk/lib/Support/CMakeLists.txt llvm/trunk/lib/TableGen/CMakeLists.txt llvm/trunk/lib/Target/ARM/CMakeLists.txt llvm/trunk/lib/Target/CMakeLists.txt llvm/trunk/lib/Target/CellSPU/CMakeLists.txt llvm/trunk/lib/Target/MBlaze/CMakeLists.txt llvm/trunk/lib/Target/MSP430/CMakeLists.txt llvm/trunk/lib/Target/Mips/CMakeLists.txt llvm/trunk/lib/Target/PTX/CMakeLists.txt llvm/trunk/lib/Target/PowerPC/CMakeLists.txt llvm/trunk/lib/Target/Sparc/CMakeLists.txt llvm/trunk/lib/Target/X86/CMakeLists.txt llvm/trunk/lib/Target/XCore/CMakeLists.txt llvm/trunk/utils/TableGen/CMakeLists.txt Modified: llvm/trunk/lib/CodeGen/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/CMakeLists.txt?rev=146966&r1=146965&r2=146966&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/CMakeLists.txt (original) +++ llvm/trunk/lib/CodeGen/CMakeLists.txt Tue Dec 20 02:42:11 2011 @@ -24,6 +24,7 @@ InlineSpiller.cpp InterferenceCache.cpp IntrinsicLowering.cpp + JITCodeEmitter.cpp LLVMTargetMachine.cpp LatencyPriorityQueue.cpp LexicalScopes.cpp @@ -40,6 +41,7 @@ MachineBlockFrequencyInfo.cpp MachineBlockPlacement.cpp MachineBranchProbabilityInfo.cpp + MachineCodeEmitter.cpp MachineCSE.cpp MachineDominators.cpp MachineFunction.cpp Modified: llvm/trunk/lib/ExecutionEngine/MCJIT/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/ExecutionEngine/MCJIT/CMakeLists.txt?rev=146966&r1=146965&r2=146966&view=diff ============================================================================== --- llvm/trunk/lib/ExecutionEngine/MCJIT/CMakeLists.txt (original) +++ llvm/trunk/lib/ExecutionEngine/MCJIT/CMakeLists.txt Tue Dec 20 02:42:11 2011 @@ -1,4 +1,5 @@ add_llvm_library(LLVMMCJIT MCJIT.cpp + MCJITMemoryManager.cpp Intercept.cpp ) Modified: llvm/trunk/lib/Support/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Support/CMakeLists.txt?rev=146966&r1=146965&r2=146966&view=diff ============================================================================== --- llvm/trunk/lib/Support/CMakeLists.txt (original) +++ llvm/trunk/lib/Support/CMakeLists.txt Tue Dec 20 02:42:11 2011 @@ -27,6 +27,7 @@ GraphWriter.cpp IntEqClasses.cpp IntervalMap.cpp + IntrusiveRefCntPtr.cpp IsInf.cpp IsNAN.cpp JSONParser.cpp Modified: llvm/trunk/lib/TableGen/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/TableGen/CMakeLists.txt?rev=146966&r1=146965&r2=146966&view=diff ============================================================================== --- llvm/trunk/lib/TableGen/CMakeLists.txt (original) +++ llvm/trunk/lib/TableGen/CMakeLists.txt Tue Dec 20 02:42:11 2011 @@ -6,6 +6,7 @@ Error.cpp Main.cpp Record.cpp + TableGenAction.cpp TableGenBackend.cpp TGLexer.cpp TGParser.cpp Modified: llvm/trunk/lib/Target/ARM/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/CMakeLists.txt?rev=146966&r1=146965&r2=146966&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/CMakeLists.txt (original) +++ llvm/trunk/lib/Target/ARM/CMakeLists.txt Tue Dec 20 02:42:11 2011 @@ -33,6 +33,7 @@ ARMJITInfo.cpp ARMLoadStoreOptimizer.cpp ARMMCInstLower.cpp + ARMMachineFunctionInfo.cpp ARMRegisterInfo.cpp ARMSelectionDAGInfo.cpp ARMSubtarget.cpp Modified: llvm/trunk/lib/Target/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CMakeLists.txt?rev=146966&r1=146965&r2=146966&view=diff ============================================================================== --- llvm/trunk/lib/Target/CMakeLists.txt (original) +++ llvm/trunk/lib/Target/CMakeLists.txt Tue Dec 20 02:42:11 2011 @@ -5,6 +5,7 @@ TargetELFWriterInfo.cpp TargetInstrInfo.cpp TargetIntrinsicInfo.cpp + TargetJITInfo.cpp TargetLibraryInfo.cpp TargetLoweringObjectFile.cpp TargetMachine.cpp Modified: llvm/trunk/lib/Target/CellSPU/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/CMakeLists.txt?rev=146966&r1=146965&r2=146966&view=diff ============================================================================== --- llvm/trunk/lib/Target/CellSPU/CMakeLists.txt (original) +++ llvm/trunk/lib/Target/CellSPU/CMakeLists.txt Tue Dec 20 02:42:11 2011 @@ -16,6 +16,7 @@ SPUISelDAGToDAG.cpp SPUISelLowering.cpp SPUFrameLowering.cpp + SPUMachineFunction.cpp SPURegisterInfo.cpp SPUSubtarget.cpp SPUTargetMachine.cpp Modified: llvm/trunk/lib/Target/MBlaze/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MBlaze/CMakeLists.txt?rev=146966&r1=146965&r2=146966&view=diff ============================================================================== --- llvm/trunk/lib/Target/MBlaze/CMakeLists.txt (original) +++ llvm/trunk/lib/Target/MBlaze/CMakeLists.txt Tue Dec 20 02:42:11 2011 @@ -18,6 +18,7 @@ MBlazeISelDAGToDAG.cpp MBlazeISelLowering.cpp MBlazeFrameLowering.cpp + MBlazeMachineFunction.cpp MBlazeRegisterInfo.cpp MBlazeSubtarget.cpp MBlazeTargetMachine.cpp Modified: llvm/trunk/lib/Target/MSP430/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MSP430/CMakeLists.txt?rev=146966&r1=146965&r2=146966&view=diff ============================================================================== --- llvm/trunk/lib/Target/MSP430/CMakeLists.txt (original) +++ llvm/trunk/lib/Target/MSP430/CMakeLists.txt Tue Dec 20 02:42:11 2011 @@ -14,6 +14,7 @@ MSP430ISelLowering.cpp MSP430InstrInfo.cpp MSP430FrameLowering.cpp + MSP430MachineFunctionInfo.cpp MSP430RegisterInfo.cpp MSP430Subtarget.cpp MSP430TargetMachine.cpp Modified: llvm/trunk/lib/Target/Mips/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/CMakeLists.txt?rev=146966&r1=146965&r2=146966&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/CMakeLists.txt (original) +++ llvm/trunk/lib/Target/Mips/CMakeLists.txt Tue Dec 20 02:42:11 2011 @@ -22,6 +22,7 @@ MipsISelLowering.cpp MipsFrameLowering.cpp MipsMCInstLower.cpp + MipsMachineFunction.cpp MipsRegisterInfo.cpp MipsSubtarget.cpp MipsTargetMachine.cpp Modified: llvm/trunk/lib/Target/PTX/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PTX/CMakeLists.txt?rev=146966&r1=146965&r2=146966&view=diff ============================================================================== --- llvm/trunk/lib/Target/PTX/CMakeLists.txt (original) +++ llvm/trunk/lib/Target/PTX/CMakeLists.txt Tue Dec 20 02:42:11 2011 @@ -17,6 +17,7 @@ PTXMCAsmStreamer.cpp PTXMCInstLower.cpp PTXMFInfoExtract.cpp + PTXMachineFunctionInfo.cpp PTXParamManager.cpp PTXRegAlloc.cpp PTXRegisterInfo.cpp Modified: llvm/trunk/lib/Target/PowerPC/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/CMakeLists.txt?rev=146966&r1=146965&r2=146966&view=diff ============================================================================== --- llvm/trunk/lib/Target/PowerPC/CMakeLists.txt (original) +++ llvm/trunk/lib/Target/PowerPC/CMakeLists.txt Tue Dec 20 02:42:11 2011 @@ -21,6 +21,7 @@ PPCFrameLowering.cpp PPCJITInfo.cpp PPCMCInstLower.cpp + PPCMachineFunctionInfo.cpp PPCRegisterInfo.cpp PPCSubtarget.cpp PPCTargetMachine.cpp Modified: llvm/trunk/lib/Target/Sparc/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/CMakeLists.txt?rev=146966&r1=146965&r2=146966&view=diff ============================================================================== --- llvm/trunk/lib/Target/Sparc/CMakeLists.txt (original) +++ llvm/trunk/lib/Target/Sparc/CMakeLists.txt Tue Dec 20 02:42:11 2011 @@ -16,6 +16,7 @@ SparcISelDAGToDAG.cpp SparcISelLowering.cpp SparcFrameLowering.cpp + SparcMachineFunctionInfo.cpp SparcRegisterInfo.cpp SparcSubtarget.cpp SparcTargetMachine.cpp Modified: llvm/trunk/lib/Target/X86/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/CMakeLists.txt?rev=146966&r1=146965&r2=146966&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/CMakeLists.txt (original) +++ llvm/trunk/lib/Target/X86/CMakeLists.txt Tue Dec 20 02:42:11 2011 @@ -26,6 +26,7 @@ X86InstrInfo.cpp X86JITInfo.cpp X86MCInstLower.cpp + X86MachineFunctionInfo.cpp X86RegisterInfo.cpp X86SelectionDAGInfo.cpp X86Subtarget.cpp Modified: llvm/trunk/lib/Target/XCore/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/XCore/CMakeLists.txt?rev=146966&r1=146965&r2=146966&view=diff ============================================================================== --- llvm/trunk/lib/Target/XCore/CMakeLists.txt (original) +++ llvm/trunk/lib/Target/XCore/CMakeLists.txt Tue Dec 20 02:42:11 2011 @@ -14,6 +14,7 @@ XCoreInstrInfo.cpp XCoreISelDAGToDAG.cpp XCoreISelLowering.cpp + XCoreMachineFunctionInfo.cpp XCoreRegisterInfo.cpp XCoreSubtarget.cpp XCoreTargetMachine.cpp Modified: llvm/trunk/utils/TableGen/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/CMakeLists.txt?rev=146966&r1=146965&r2=146966&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/CMakeLists.txt (original) +++ llvm/trunk/utils/TableGen/CMakeLists.txt Tue Dec 20 02:42:11 2011 @@ -33,5 +33,6 @@ TGValueTypes.cpp TableGen.cpp X86DisassemblerTables.cpp + X86ModRMFilters.cpp X86RecognizableInstr.cpp ) From chandlerc at google.com Tue Dec 20 02:46:59 2011 From: chandlerc at google.com (Chandler Carruth) Date: Tue, 20 Dec 2011 00:46:59 -0800 Subject: [llvm-commits] [llvm] r146960 - in /llvm/trunk: include/llvm/ include/llvm/ADT/ include/llvm/Analysis/ include/llvm/CodeGen/ include/llvm/MC/ include/llvm/Object/ include/llvm/TableGen/ include/llvm/Target/ include/llvm/Transforms/Utils/ lib/Anal Message-ID: On Mon, Dec 19, 2011 at 11:47 PM, Chad Rosier wrote: > David, > Could you please update the CMakeList.txt? > I've fixed them in r146966. -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20111220/ad622aae/attachment.html From mcrosier at apple.com Tue Dec 20 02:54:49 2011 From: mcrosier at apple.com (Chad Rosier) Date: Tue, 20 Dec 2011 00:54:49 -0800 Subject: [llvm-commits] [llvm] r146960 - in /llvm/trunk: include/llvm/ include/llvm/ADT/ include/llvm/Analysis/ include/llvm/CodeGen/ include/llvm/MC/ include/llvm/Object/ include/llvm/TableGen/ include/llvm/Target/ include/llvm/Transforms/Utils/ lib/Anal In-Reply-To: References: Message-ID: <6BE840F7-3D6A-4792-AAE5-6C9333B9CF10@apple.com> Nice. Thanks, Chandler. On Dec 20, 2011, at 12:46 AM, Chandler Carruth wrote: > On Mon, Dec 19, 2011 at 11:47 PM, Chad Rosier wrote: > David, > Could you please update the CMakeList.txt? > > I've fixed them in r146966. -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20111220/dbe5841b/attachment.html From klimek at google.com Tue Dec 20 03:26:26 2011 From: klimek at google.com (Manuel Klimek) Date: Tue, 20 Dec 2011 09:26:26 -0000 Subject: [llvm-commits] [llvm] r146968 - in /llvm/trunk: include/llvm/Support/JSONParser.h lib/Support/JSONParser.cpp Message-ID: <20111220092626.A468C1BE003@llvm.org> Author: klimek Date: Tue Dec 20 03:26:26 2011 New Revision: 146968 URL: http://llvm.org/viewvc/llvm-project?rev=146968&view=rev Log: Addressing style issues in JSON parser. Modified: llvm/trunk/include/llvm/Support/JSONParser.h llvm/trunk/lib/Support/JSONParser.cpp Modified: llvm/trunk/include/llvm/Support/JSONParser.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Support/JSONParser.h?rev=146968&r1=146967&r2=146968&view=diff ============================================================================== --- llvm/trunk/include/llvm/Support/JSONParser.h (original) +++ llvm/trunk/include/llvm/Support/JSONParser.h Tue Dec 20 03:26:26 2011 @@ -1,4 +1,4 @@ -//===--- JsonParser.h - Simple JSON parser ----------------------*- C++ -*-===// +//===--- JSONParser.h - Simple JSON parser ----------------------*- C++ -*-===// // // The LLVM Compiler Infrastructure // @@ -17,15 +17,13 @@ // //===----------------------------------------------------------------------===// -#ifndef LLVM_CLANG_TOOLING_JSON_PARSER_H -#define LLVM_CLANG_TOOLING_JSON_PARSER_H +#ifndef LLVM_SUPPORT_JSON_PARSER_H +#define LLVM_SUPPORT_JSON_PARSER_H #include "llvm/ADT/StringRef.h" #include "llvm/Support/Allocator.h" #include "llvm/Support/ErrorHandling.h" -#include - namespace llvm { class JSONString; @@ -441,4 +439,4 @@ } // end namespace llvm -#endif // LLVM_CLANG_TOOLING_JSON_PARSER_H +#endif // LLVM_SUPPORT_JSON_PARSER_H Modified: llvm/trunk/lib/Support/JSONParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Support/JSONParser.cpp?rev=146968&r1=146967&r2=146968&view=diff ============================================================================== --- llvm/trunk/lib/Support/JSONParser.cpp (original) +++ llvm/trunk/lib/Support/JSONParser.cpp Tue Dec 20 03:26:26 2011 @@ -1,4 +1,4 @@ -//===--- JsonParser.cpp - Simple JSON parser ------------------------------===// +//===--- JSONParser.cpp - Simple JSON parser ------------------------------===// // // The LLVM Compiler Infrastructure // @@ -16,7 +16,7 @@ #include "llvm/ADT/Twine.h" #include "llvm/Support/Casting.h" -namespace llvm { +using namespace llvm; JSONParser::JSONParser(StringRef Input) : Input(Input), Position(Input.begin()) {} @@ -217,5 +217,3 @@ template <> JSONKeyValuePair *JSONParser::parseElement() { return parseKeyValuePair(); } - -} // end namespace llvm From chandlerc at google.com Tue Dec 20 04:03:26 2011 From: chandlerc at google.com (Chandler Carruth) Date: Tue, 20 Dec 2011 02:03:26 -0800 Subject: [llvm-commits] [llvm] r146801 - in /llvm/trunk: include/llvm/MC/MCStreamer.h lib/CodeGen/AsmPrinter/AsmPrinterDwarf.cpp lib/MC/MCAsmStreamer.cpp lib/MC/MCLoggingStreamer.cpp lib/MC/MCNullStreamer.cpp lib/MC/MCParser/COFFAsmParser.cpp lib/MC/MCStr Message-ID: On Fri, Dec 16, 2011 at 5:14 PM, Rafael Espindola < rafael.espindola at gmail.com> wrote: > Modified: llvm/trunk/lib/MC/WinCOFFStreamer.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC > /WinCOFFStreamer.cpp?rev=146801&r1=146800&r2=146801&view=diff > > ============================================================================== > --- llvm/trunk/lib/MC/WinCOFFStreamer.cpp (original) > +++ llvm/trunk/lib/MC/WinCOFFStreamer.cpp Fri Dec 16 19:14:52 2011 > @@ -32,6 +32,9 @@ > #include "llvm/Support/ErrorHandling.h" > #include "llvm/Support/TargetRegistry.h" > #include "llvm/Support/raw_ostream.h" > + > +#include "../Target/X86/MCTargetDesc/X86FixupKinds.h" > + > This is a pretty egregious layering violation. Please fix or revert, this causes all kinds of problems with improper dependencies between various components. -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20111220/35390f5d/attachment.html From klimek at google.com Tue Dec 20 04:34:29 2011 From: klimek at google.com (Manuel Klimek) Date: Tue, 20 Dec 2011 10:34:29 -0000 Subject: [llvm-commits] [llvm] r146970 - /llvm/trunk/utils/json-bench/JSONBench.cpp Message-ID: <20111220103429.CCE2A1BE003@llvm.org> Author: klimek Date: Tue Dec 20 04:34:29 2011 New Revision: 146970 URL: http://llvm.org/viewvc/llvm-project?rev=146970&view=rev Log: Fixing option for JSON benchmark broken since the change to size_t. Modified: llvm/trunk/utils/json-bench/JSONBench.cpp Modified: llvm/trunk/utils/json-bench/JSONBench.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/json-bench/JSONBench.cpp?rev=146970&r1=146969&r2=146970&view=diff ============================================================================== --- llvm/trunk/utils/json-bench/JSONBench.cpp (original) +++ llvm/trunk/utils/json-bench/JSONBench.cpp Tue Dec 20 04:34:29 2011 @@ -23,7 +23,7 @@ "Run a quick verification useful for regression testing"), llvm::cl::init(false)); -static llvm::cl::opt +static llvm::cl::opt MemoryLimitMB("memory-limit", llvm::cl::desc( "Do not use more megabytes of memory"), llvm::cl::init(1000)); From klimek at google.com Tue Dec 20 04:42:53 2011 From: klimek at google.com (Manuel Klimek) Date: Tue, 20 Dec 2011 10:42:53 -0000 Subject: [llvm-commits] [llvm] r146971 - in /llvm/trunk: include/llvm/Support/JSONParser.h lib/Support/JSONParser.cpp Message-ID: <20111220104253.222F81BE003@llvm.org> Author: klimek Date: Tue Dec 20 04:42:52 2011 New Revision: 146971 URL: http://llvm.org/viewvc/llvm-project?rev=146971&view=rev Log: Pulls the implementation of skip() into JSONParser. This is the first step towards migrating more of the parser implementation into the parser class. Modified: llvm/trunk/include/llvm/Support/JSONParser.h llvm/trunk/lib/Support/JSONParser.cpp Modified: llvm/trunk/include/llvm/Support/JSONParser.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Support/JSONParser.h?rev=146971&r1=146970&r2=146971&view=diff ============================================================================== --- llvm/trunk/include/llvm/Support/JSONParser.h (original) +++ llvm/trunk/include/llvm/Support/JSONParser.h Tue Dec 20 04:42:52 2011 @@ -48,10 +48,6 @@ JSONAtom(Kind MyKind) : MyKind(MyKind) {} private: - /// \brief Parses to the end of the object and returns whether parsing - /// was successful. - bool skip() const; - Kind MyKind; friend class JSONParser; @@ -76,8 +72,8 @@ /// \brief Returns the outermost JSON value (either an array or an object). /// /// Can return NULL if the input does not start with an array or an object. - /// The object is not parsed yet - the caller must either iterate over the - /// returned object or call 'skip' to trigger parsing. + /// The object is not parsed yet - the caller must iterate over the + /// returned object to trigger parsing. /// /// A JSONValue can be either a JSONString, JSONObject or JSONArray. JSONValue *parseRoot(); @@ -130,6 +126,13 @@ bool errorIfNotAt(char C, StringRef Message); /// } + /// \brief Skips all elements in the given container. + template + bool skipContainer(const ContainerT &Container); + + /// \brief Skips to the next position behind the given JSON atom. + bool skip(const JSONAtom &Atom); + /// All nodes are allocated by the parser and will be deallocated when the /// parser is destroyed. BumpPtrAllocator ValueAllocator; @@ -191,9 +194,6 @@ private: JSONString(StringRef RawText) : JSONValue(JK_String), RawText(RawText) {} - /// \brief Skips to the next position in the parse stream. - bool skip() const { return true; }; - StringRef RawText; friend class JSONAtom; @@ -223,9 +223,6 @@ JSONKeyValuePair(const JSONString *Key, const JSONValue *Value) : JSONAtom(JK_KeyValuePair), Key(Key), Value(Value) {} - /// \brief Skips to the next position in the parse stream. - bool skip() const { return Value->skip(); }; - friend class JSONAtom; friend class JSONParser; template friend class JSONContainer; @@ -243,8 +240,7 @@ /// \brief Implementation of JSON containers (arrays and objects). /// /// JSONContainers drive the lazy parsing of JSON arrays and objects via -/// forward iterators. Call 'skip' to validate parsing of all elements of the -/// container and to position the parse stream behind the container. +/// forward iterators. template class JSONContainer : public JSONValue { @@ -320,23 +316,13 @@ return const_iterator(this); } - /// \brief Skips to the next position in the parse stream. - bool skip() const { - for (const_iterator I = current(), E = end(); I != E; ++I) { - assert(*I != 0); - if (!(*I)->skip()) - return false; - } - return !Parser->failed(); - } - /// \brief Parse the next element in the container into the Current element. /// /// This routine is called as an iterator into this container walks through /// its elements. It mutates the container's internal current node to point to /// the next atom of the container. void parseNextElement() const { - Current->skip(); + Parser->skip(*Current); Position = Parser->parseNextElement(Current); } Modified: llvm/trunk/lib/Support/JSONParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Support/JSONParser.cpp?rev=146971&r1=146970&r2=146971&view=diff ============================================================================== --- llvm/trunk/lib/Support/JSONParser.cpp (original) +++ llvm/trunk/lib/Support/JSONParser.cpp Tue Dec 20 04:42:52 2011 @@ -40,7 +40,30 @@ } bool JSONParser::validate() { - return parseRoot()->skip(); + return skip(*parseRoot()); +} + +template +bool JSONParser::skipContainer(const ContainerT &Container) { + for (typename ContainerT::const_iterator I = Container.current(), + E = Container.end(); + I != E; ++I) { + assert(*I != 0); + if (!skip(**I)) + return false; + } + return !failed(); +} + +bool JSONParser::skip(const JSONAtom &Atom) { + switch(Atom.getKind()) { + case JSONAtom::JK_Array: return skipContainer(*cast(&Atom)); + case JSONAtom::JK_Object: return skipContainer(*cast(&Atom)); + case JSONAtom::JK_String: return true; + case JSONAtom::JK_KeyValuePair: + return skip(*cast(&Atom)->Value); + } + llvm_unreachable("Impossible enum value."); } // Sets the current error to: @@ -159,16 +182,6 @@ return ErrorMessage; } -bool JSONAtom::skip() const { - switch (MyKind) { - case JK_Array: return cast(this)->skip(); - case JK_Object: return cast(this)->skip(); - case JK_String: return cast(this)->skip(); - case JK_KeyValuePair: return cast(this)->skip(); - } - llvm_unreachable("Impossible enum value."); -} - // Parses a JSONValue, assuming that the current position is at the first // character of the value. JSONValue *JSONParser::parseValue() { From grosser at fim.uni-passau.de Tue Dec 20 04:43:14 2011 From: grosser at fim.uni-passau.de (Tobias Grosser) Date: Tue, 20 Dec 2011 10:43:14 -0000 Subject: [llvm-commits] [polly] r146972 - in /polly/trunk: include/polly/TempScopInfo.h lib/Analysis/ScopDetection.cpp lib/Analysis/ScopInfo.cpp lib/Analysis/TempScopInfo.cpp test/CodeGen/simple_nonaffine_loop.c test/CodeGen/simple_nonaffine_loop.ll test/ScopInfo/simple_nonaffine_loop.ll test/ScopInfo/simple_nonaffine_loop_not.ll Message-ID: <20111220104314.7AA031BE003@llvm.org> Author: grosser Date: Tue Dec 20 04:43:14 2011 New Revision: 146972 URL: http://llvm.org/viewvc/llvm-project?rev=146972&view=rev Log: Support non-affine access functions in Polly. In case we can not analyze an access function, we do not discard the SCoP, but assume conservatively that all memory accesses that can be derived from our base pointer may be accessed. Patch provided by: Marcello Maggioni Added: polly/trunk/test/CodeGen/simple_nonaffine_loop.c polly/trunk/test/CodeGen/simple_nonaffine_loop.ll polly/trunk/test/ScopInfo/simple_nonaffine_loop.ll polly/trunk/test/ScopInfo/simple_nonaffine_loop_not.ll Modified: polly/trunk/include/polly/TempScopInfo.h polly/trunk/lib/Analysis/ScopDetection.cpp polly/trunk/lib/Analysis/ScopInfo.cpp polly/trunk/lib/Analysis/TempScopInfo.cpp Modified: polly/trunk/include/polly/TempScopInfo.h URL: http://llvm.org/viewvc/llvm-project/polly/trunk/include/polly/TempScopInfo.h?rev=146972&r1=146971&r2=146972&view=diff ============================================================================== --- polly/trunk/include/polly/TempScopInfo.h (original) +++ polly/trunk/include/polly/TempScopInfo.h Tue Dec 20 04:43:14 2011 @@ -45,12 +45,13 @@ private: unsigned ElemBytes; TypeKind Type; + bool IsAffine; public: explicit IRAccess (TypeKind Type, const Value *BaseAddress, - const SCEV *Offset, unsigned elemBytes) + const SCEV *Offset, unsigned elemBytes, bool Affine) : BaseAddress(BaseAddress), Offset(Offset), - ElemBytes(elemBytes), Type(Type) {} + ElemBytes(elemBytes), Type(Type), IsAffine(Affine) {} enum TypeKind getType() const { return Type; } @@ -60,7 +61,10 @@ unsigned getElemSizeInBytes() const { return ElemBytes; } + bool isAffine() const { return IsAffine; } + bool isRead() const { return Type == READ; } + }; class Comparison { Modified: polly/trunk/lib/Analysis/ScopDetection.cpp URL: http://llvm.org/viewvc/llvm-project/polly/trunk/lib/Analysis/ScopDetection.cpp?rev=146972&r1=146971&r2=146972&view=diff ============================================================================== --- polly/trunk/lib/Analysis/ScopDetection.cpp (original) +++ polly/trunk/lib/Analysis/ScopDetection.cpp Tue Dec 20 04:43:14 2011 @@ -79,6 +79,11 @@ cl::desc("Ignore possible aliasing of the array bases"), cl::Hidden, cl::init(false)); +static cl::opt +AllowNonAffine("polly-allow-nonaffine", + cl::desc("Allow non affine access functions in arrays"), + cl::Hidden, cl::init(false)); + //===----------------------------------------------------------------------===// // Statistics. @@ -245,7 +250,7 @@ AccessFunction = SE->getMinusSCEV(AccessFunction, BasePointer); - if (!isAffineExpr(&Context.CurRegion, AccessFunction, *SE, BaseValue)) + if (!isAffineExpr(&Context.CurRegion, AccessFunction, *SE, BaseValue) && !AllowNonAffine) INVALID(AffFunc, "Bad memory address " << *AccessFunction); // FIXME: Alias Analysis thinks IntToPtrInst aliases with alloca instructions Modified: polly/trunk/lib/Analysis/ScopInfo.cpp URL: http://llvm.org/viewvc/llvm-project/polly/trunk/lib/Analysis/ScopInfo.cpp?rev=146972&r1=146971&r2=146972&view=diff ============================================================================== --- polly/trunk/lib/Analysis/ScopInfo.cpp (original) +++ polly/trunk/lib/Analysis/ScopInfo.cpp Tue Dec 20 04:43:14 2011 @@ -312,9 +312,16 @@ Type = Access.isRead() ? Read : Write; statement = Statement; - isl_pw_aff *Affine = SCEVAffinator::getPwAff(Statement, Access.getOffset()); BaseAddr = Access.getBase(); + if (!Access.isAffine()) { + Type = (Type == Read) ? Read : MayWrite; + AccessRelation = isl_map_from_basic_map(createBasicAccessMap(Statement)); + return; + } + + isl_pw_aff *Affine = SCEVAffinator::getPwAff(Statement, Access.getOffset()); + setBaseName(); // Devide the access function by the size of the elements in the array. Modified: polly/trunk/lib/Analysis/TempScopInfo.cpp URL: http://llvm.org/viewvc/llvm-project/polly/trunk/lib/Analysis/TempScopInfo.cpp?rev=146972&r1=146971&r2=146972&view=diff ============================================================================== --- polly/trunk/lib/Analysis/TempScopInfo.cpp (original) +++ polly/trunk/lib/Analysis/TempScopInfo.cpp Tue Dec 20 04:43:14 2011 @@ -98,11 +98,15 @@ dyn_cast(SE->getPointerBase(AccessFunction)); assert(BasePointer && "Could not find base pointer"); - AccessFunction = SE->getMinusSCEV(AccessFunction, BasePointer); + + bool IsAffine = isAffineExpr(&R, AccessFunction, *SE, + BasePointer->getValue()); + Functions.push_back(std::make_pair(IRAccess(Type, BasePointer->getValue(), - AccessFunction, Size), + AccessFunction, Size, + IsAffine), &Inst)); } } Added: polly/trunk/test/CodeGen/simple_nonaffine_loop.c URL: http://llvm.org/viewvc/llvm-project/polly/trunk/test/CodeGen/simple_nonaffine_loop.c?rev=146972&view=auto ============================================================================== --- polly/trunk/test/CodeGen/simple_nonaffine_loop.c (added) +++ polly/trunk/test/CodeGen/simple_nonaffine_loop.c Tue Dec 20 04:43:14 2011 @@ -0,0 +1,15 @@ +#include +#include +#include + +int main() +{ + int A[1024*1024]; + int i; + for (i = 0; i < 1024; i++) + A[i*i] = 2*i; + + printf("Random Value: %d", A[rand() % 1024*1024]); + + return 0; +} Added: polly/trunk/test/CodeGen/simple_nonaffine_loop.ll URL: http://llvm.org/viewvc/llvm-project/polly/trunk/test/CodeGen/simple_nonaffine_loop.ll?rev=146972&view=auto ============================================================================== --- polly/trunk/test/CodeGen/simple_nonaffine_loop.ll (added) +++ polly/trunk/test/CodeGen/simple_nonaffine_loop.ll Tue Dec 20 04:43:14 2011 @@ -0,0 +1,43 @@ +; RUN: opt %loadPolly %defaultOpts -O3 -polly-cloog -polly-allow-nonaffine -analyze %s | FileCheck %s +; ModuleID = 'simple_nonaffine_loop.c' +target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128" +target triple = "x86_64-apple-macosx10.7.2" + + at .str = private unnamed_addr constant [17 x i8] c"Random Value: %d\00", align 1 + +define i32 @main() nounwind uwtable ssp { +entry: + %A = alloca [1048576 x i32], align 16 + br label %entry.split + +entry.split: ; preds = %entry + br label %for.body + +for.body: ; preds = %entry.split, %for.body + %0 = phi i32 [ 0, %entry.split ], [ %1, %for.body ] + %mul = mul i32 %0, 2 + %mul1 = mul nsw i32 %0, %0 + %idxprom1 = zext i32 %mul1 to i64 + %arrayidx = getelementptr inbounds [1048576 x i32]* %A, i64 0, i64 %idxprom1 + store i32 %mul, i32* %arrayidx, align 4 + %1 = add nsw i32 %0, 1 + %exitcond = icmp ne i32 %1, 1024 + br i1 %exitcond, label %for.body, label %for.end + +for.end: ; preds = %for.body + %call = call i32 @rand() nounwind + %rem = srem i32 %call, 1024 + %mul2 = shl nsw i32 %rem, 10 + %idxprom3 = sext i32 %mul2 to i64 + %arrayidx4 = getelementptr inbounds [1048576 x i32]* %A, i64 0, i64 %idxprom3 + %2 = load i32* %arrayidx4, align 16 + %call5 = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([17 x i8]* @.str, i64 0, i64 0), i32 %2) nounwind + ret i32 0 +} + +declare i32 @printf(i8*, ...) + +declare i32 @rand() +; CHECK: for (c2=0;c2<=1023;c2++) { +; CHECK: Stmt_for_body(c2); +; CHECK: } Added: polly/trunk/test/ScopInfo/simple_nonaffine_loop.ll URL: http://llvm.org/viewvc/llvm-project/polly/trunk/test/ScopInfo/simple_nonaffine_loop.ll?rev=146972&view=auto ============================================================================== --- polly/trunk/test/ScopInfo/simple_nonaffine_loop.ll (added) +++ polly/trunk/test/ScopInfo/simple_nonaffine_loop.ll Tue Dec 20 04:43:14 2011 @@ -0,0 +1,41 @@ +; RUN: opt %loadPolly %defaultOpts -polly-scops -polly-allow-nonaffine -analyze %s | FileCheck %s +; ModuleID = 'simple_nonaffine_loop.c' +target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128" +target triple = "x86_64-apple-macosx10.7.2" + + at .str = private unnamed_addr constant [17 x i8] c"Random Value: %d\00", align 1 + +define i32 @main() nounwind uwtable ssp { +entry: + %A = alloca [1048576 x i32], align 16 + br label %entry.split + +entry.split: ; preds = %entry + br label %for.body + +for.body: ; preds = %entry.split, %for.body + %0 = phi i32 [ 0, %entry.split ], [ %1, %for.body ] + %mul = mul i32 %0, 2 + %mul1 = mul nsw i32 %0, %0 + %idxprom1 = zext i32 %mul1 to i64 + %arrayidx = getelementptr inbounds [1048576 x i32]* %A, i64 0, i64 %idxprom1 + store i32 %mul, i32* %arrayidx, align 4 + %1 = add nsw i32 %0, 1 + %exitcond = icmp ne i32 %1, 1024 + br i1 %exitcond, label %for.body, label %for.end + +for.end: ; preds = %for.body + %call = call i32 @rand() nounwind + %rem = srem i32 %call, 1024 + %mul2 = shl nsw i32 %rem, 10 + %idxprom3 = sext i32 %mul2 to i64 + %arrayidx4 = getelementptr inbounds [1048576 x i32]* %A, i64 0, i64 %idxprom3 + %2 = load i32* %arrayidx4, align 16 + %call5 = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([17 x i8]* @.str, i64 0, i64 0), i32 %2) nounwind + ret i32 0 +} + +declare i32 @printf(i8*, ...) + +declare i32 @rand() +; CHECK: { Stmt_for_body[i0] -> MemRef_A[o0] }; Added: polly/trunk/test/ScopInfo/simple_nonaffine_loop_not.ll URL: http://llvm.org/viewvc/llvm-project/polly/trunk/test/ScopInfo/simple_nonaffine_loop_not.ll?rev=146972&view=auto ============================================================================== --- polly/trunk/test/ScopInfo/simple_nonaffine_loop_not.ll (added) +++ polly/trunk/test/ScopInfo/simple_nonaffine_loop_not.ll Tue Dec 20 04:43:14 2011 @@ -0,0 +1,41 @@ +; RUN: opt %loadPolly %defaultOpts -polly-scops -analyze %s | not FileCheck %s +; ModuleID = 'simple_nonaffine_loop.c' +target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128" +target triple = "x86_64-apple-macosx10.7.2" + + at .str = private unnamed_addr constant [17 x i8] c"Random Value: %d\00", align 1 + +define i32 @main() nounwind uwtable ssp { +entry: + %A = alloca [1048576 x i32], align 16 + br label %entry.split + +entry.split: ; preds = %entry + br label %for.body + +for.body: ; preds = %entry.split, %for.body + %0 = phi i32 [ 0, %entry.split ], [ %1, %for.body ] + %mul = mul i32 %0, 2 + %mul1 = mul nsw i32 %0, %0 + %idxprom1 = zext i32 %mul1 to i64 + %arrayidx = getelementptr inbounds [1048576 x i32]* %A, i64 0, i64 %idxprom1 + store i32 %mul, i32* %arrayidx, align 4 + %1 = add nsw i32 %0, 1 + %exitcond = icmp ne i32 %1, 1024 + br i1 %exitcond, label %for.body, label %for.end + +for.end: ; preds = %for.body + %call = call i32 @rand() nounwind + %rem = srem i32 %call, 1024 + %mul2 = shl nsw i32 %rem, 10 + %idxprom3 = sext i32 %mul2 to i64 + %arrayidx4 = getelementptr inbounds [1048576 x i32]* %A, i64 0, i64 %idxprom3 + %2 = load i32* %arrayidx4, align 16 + %call5 = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([17 x i8]* @.str, i64 0, i64 0), i32 %2) nounwind + ret i32 0 +} + +declare i32 @printf(i8*, ...) + +declare i32 @rand() +; CHECK: { Stmt_for_body[i0] -> MemRef_A[o0] }; From chandlerc at google.com Tue Dec 20 04:51:51 2011 From: chandlerc at google.com (Chandler Carruth) Date: Tue, 20 Dec 2011 02:51:51 -0800 Subject: [llvm-commits] [llvm] r146971 - in /llvm/trunk: include/llvm/Support/JSONParser.h lib/Support/JSONParser.cpp In-Reply-To: <20111220104253.222F81BE003@llvm.org> References: <20111220104253.222F81BE003@llvm.org> Message-ID: On Tue, Dec 20, 2011 at 2:42 AM, Manuel Klimek wrote: > Modified: llvm/trunk/lib/Support/JSONParser.cpp > URL: > http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Support/JSONParser.cpp?rev=146971&r1=146970&r2=146971&view=diff > > ============================================================================== > --- llvm/trunk/lib/Support/JSONParser.cpp (original) > +++ llvm/trunk/lib/Support/JSONParser.cpp Tue Dec 20 04:42:52 2011 > @@ -40,7 +40,30 @@ > } > > bool JSONParser::validate() { > - return parseRoot()->skip(); > + return skip(*parseRoot()); > +} > + > +template > +bool JSONParser::skipContainer(const ContainerT &Container) { > + for (typename ContainerT::const_iterator I = Container.current(), > + E = Container.end(); > + I != E; ++I) { > + assert(*I != 0); > + if (!skip(**I)) > + return false; > + } > + return !failed(); > +} > Again, you can't just define template functions in the source file. Until this is de-templated, this definition needs to be available in the header. =/ -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20111220/c5952fb5/attachment.html From klimek at google.com Tue Dec 20 05:04:23 2011 From: klimek at google.com (Manuel Klimek) Date: Tue, 20 Dec 2011 11:04:23 -0000 Subject: [llvm-commits] [llvm] r146973 - in /llvm/trunk: include/llvm/Support/JSONParser.h lib/Support/JSONParser.cpp Message-ID: <20111220110423.C75061BE003@llvm.org> Author: klimek Date: Tue Dec 20 05:04:23 2011 New Revision: 146973 URL: http://llvm.org/viewvc/llvm-project?rev=146973&view=rev Log: Fixes a potential compilation error. Pulling the template implementation into the header to guarantee that it's visible to all possible instantiations. Modified: llvm/trunk/include/llvm/Support/JSONParser.h llvm/trunk/lib/Support/JSONParser.cpp Modified: llvm/trunk/include/llvm/Support/JSONParser.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Support/JSONParser.h?rev=146973&r1=146972&r2=146973&view=diff ============================================================================== --- llvm/trunk/include/llvm/Support/JSONParser.h (original) +++ llvm/trunk/include/llvm/Support/JSONParser.h Tue Dec 20 05:04:23 2011 @@ -128,7 +128,16 @@ /// \brief Skips all elements in the given container. template - bool skipContainer(const ContainerT &Container); + bool skipContainer(const ContainerT &Container) { + for (typename ContainerT::const_iterator I = Container.current(), + E = Container.end(); + I != E; ++I) { + assert(*I != 0); + if (!skip(**I)) + return false; + } + return !failed(); + } /// \brief Skips to the next position behind the given JSON atom. bool skip(const JSONAtom &Atom); Modified: llvm/trunk/lib/Support/JSONParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Support/JSONParser.cpp?rev=146973&r1=146972&r2=146973&view=diff ============================================================================== --- llvm/trunk/lib/Support/JSONParser.cpp (original) +++ llvm/trunk/lib/Support/JSONParser.cpp Tue Dec 20 05:04:23 2011 @@ -43,18 +43,6 @@ return skip(*parseRoot()); } -template -bool JSONParser::skipContainer(const ContainerT &Container) { - for (typename ContainerT::const_iterator I = Container.current(), - E = Container.end(); - I != E; ++I) { - assert(*I != 0); - if (!skip(**I)) - return false; - } - return !failed(); -} - bool JSONParser::skip(const JSONAtom &Atom) { switch(Atom.getKind()) { case JSONAtom::JK_Array: return skipContainer(*cast(&Atom)); From klimek at google.com Tue Dec 20 05:07:40 2011 From: klimek at google.com (Manuel Klimek) Date: Tue, 20 Dec 2011 12:07:40 +0100 Subject: [llvm-commits] [llvm] r146971 - in /llvm/trunk: include/llvm/Support/JSONParser.h lib/Support/JSONParser.cpp In-Reply-To: References: <20111220104253.222F81BE003@llvm.org> Message-ID: On Tue, Dec 20, 2011 at 11:51 AM, Chandler Carruth wrote: > On Tue, Dec 20, 2011 at 2:42 AM, Manuel Klimek wrote: >> >> Modified: llvm/trunk/lib/Support/JSONParser.cpp >> URL: >> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Support/JSONParser.cpp?rev=146971&r1=146970&r2=146971&view=diff >> >> ============================================================================== >> --- llvm/trunk/lib/Support/JSONParser.cpp (original) >> +++ llvm/trunk/lib/Support/JSONParser.cpp Tue Dec 20 04:42:52 2011 >> @@ -40,7 +40,30 @@ >> ?} >> >> ?bool JSONParser::validate() { >> - ?return parseRoot()->skip(); >> + ?return skip(*parseRoot()); >> +} >> + >> +template >> +bool JSONParser::skipContainer(const ContainerT &Container) { >> + ?for (typename ContainerT::const_iterator I = Container.current(), >> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? E = Container.end(); >> + ? ? ? I != E; ++I) { >> + ? ?assert(*I != 0); >> + ? ?if (!skip(**I)) >> + ? ? ?return false; >> + ?} >> + ?return !failed(); >> +} > > > Again, you can't just define template functions in the source file. Until > this is de-templated, this definition needs to be available in the header. > =/ Done. From chandlerc at gmail.com Tue Dec 20 05:19:37 2011 From: chandlerc at gmail.com (Chandler Carruth) Date: Tue, 20 Dec 2011 11:19:37 -0000 Subject: [llvm-commits] [llvm] r146974 - in /llvm/trunk: lib/Target/X86/X86ISelLowering.cpp lib/Target/X86/X86InstrCompiler.td test/CodeGen/X86/clz.ll Message-ID: <20111220111937.BE6341BE003@llvm.org> Author: chandlerc Date: Tue Dec 20 05:19:37 2011 New Revision: 146974 URL: http://llvm.org/viewvc/llvm-project?rev=146974&view=rev Log: Begin teaching the X86 target how to efficiently codegen patterns that use the zero-undefined variants of CTTZ and CTLZ. These are just simple patterns for now, there is more to be done to make real world code using these constructs be optimized and codegen'ed properly on X86. The existing tests are spiffed up to check that we no longer generate unnecessary cmov instructions, and that we generate the very important 'xor' to transform bsr which counts the index of the most significant one bit to the number of leading (most significant) zero bits. Also they now check that when the variant with defined zero result is used, the cmov is still produced. Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp llvm/trunk/lib/Target/X86/X86InstrCompiler.td llvm/trunk/test/CodeGen/X86/clz.ll Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=146974&r1=146973&r2=146974&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original) +++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Tue Dec 20 05:19:37 2011 @@ -380,9 +380,6 @@ setOperationAction(ISD::FLT_ROUNDS_ , MVT::i32 , Custom); setOperationAction(ISD::CTTZ_ZERO_UNDEF , MVT::i8 , Expand); - setOperationAction(ISD::CTTZ_ZERO_UNDEF , MVT::i16 , Expand); - setOperationAction(ISD::CTTZ_ZERO_UNDEF , MVT::i32 , Expand); - setOperationAction(ISD::CTTZ_ZERO_UNDEF , MVT::i64 , Expand); if (Subtarget->hasBMI()) { setOperationAction(ISD::CTTZ , MVT::i8 , Promote); } else { @@ -394,9 +391,6 @@ } setOperationAction(ISD::CTLZ_ZERO_UNDEF , MVT::i8 , Expand); - setOperationAction(ISD::CTLZ_ZERO_UNDEF , MVT::i16 , Expand); - setOperationAction(ISD::CTLZ_ZERO_UNDEF , MVT::i32 , Expand); - setOperationAction(ISD::CTLZ_ZERO_UNDEF , MVT::i64 , Expand); if (Subtarget->hasLZCNT()) { setOperationAction(ISD::CTLZ , MVT::i8 , Promote); } else { Modified: llvm/trunk/lib/Target/X86/X86InstrCompiler.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrCompiler.td?rev=146974&r1=146973&r2=146974&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86InstrCompiler.td (original) +++ llvm/trunk/lib/Target/X86/X86InstrCompiler.td Tue Dec 20 05:19:37 2011 @@ -1753,3 +1753,20 @@ (AND64ri8 GR64:$src1, i64immSExt8:$src2)>; def : Pat<(and GR64:$src1, i64immSExt32:$src2), (AND64ri32 GR64:$src1, i64immSExt32:$src2)>; + +// Bit scan instruction patterns to match explicit zero-undef behavior. +def : Pat<(cttz_zero_undef GR16:$src), (BSF16rr GR16:$src)>; +def : Pat<(cttz_zero_undef GR32:$src), (BSF32rr GR32:$src)>; +def : Pat<(cttz_zero_undef GR64:$src), (BSF64rr GR64:$src)>; +def : Pat<(cttz_zero_undef (loadi16 addr:$src)), (BSF16rm addr:$src)>; +def : Pat<(cttz_zero_undef (loadi32 addr:$src)), (BSF32rm addr:$src)>; +def : Pat<(cttz_zero_undef (loadi64 addr:$src)), (BSF64rm addr:$src)>; +def : Pat<(ctlz_zero_undef GR16:$src), (XOR16ri (BSR16rr GR16:$src), 15)>; +def : Pat<(ctlz_zero_undef GR32:$src), (XOR32ri (BSR32rr GR32:$src), 31)>; +def : Pat<(ctlz_zero_undef GR64:$src), (XOR64ri8 (BSR64rr GR64:$src), 63)>; +def : Pat<(ctlz_zero_undef (loadi16 addr:$src)), + (XOR16ri (BSR16rm addr:$src), 15)>; +def : Pat<(ctlz_zero_undef (loadi32 addr:$src)), + (XOR32ri (BSR32rm addr:$src), 31)>; +def : Pat<(ctlz_zero_undef (loadi64 addr:$src)), + (XOR64ri8 (BSR64rm addr:$src), 63)>; Modified: llvm/trunk/test/CodeGen/X86/clz.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/clz.ll?rev=146974&r1=146973&r2=146974&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/X86/clz.ll (original) +++ llvm/trunk/test/CodeGen/X86/clz.ll Tue Dec 20 05:19:37 2011 @@ -1,48 +1,65 @@ ; RUN: llc < %s -march=x86 -mcpu=yonah | FileCheck %s define i32 @t1(i32 %x) nounwind { - %tmp = tail call i32 @llvm.ctlz.i32( i32 %x, i1 true ) - ret i32 %tmp + %tmp = tail call i32 @llvm.ctlz.i32( i32 %x, i1 true ) + ret i32 %tmp ; CHECK: t1: ; CHECK: bsrl -; CHECK: cmov +; CHECK-NOT: cmov +; CHECK: xorl $31, +; CHECK: ret } declare i32 @llvm.ctlz.i32(i32, i1) nounwind readnone define i32 @t2(i32 %x) nounwind { - %tmp = tail call i32 @llvm.cttz.i32( i32 %x, i1 true ) - ret i32 %tmp + %tmp = tail call i32 @llvm.cttz.i32( i32 %x, i1 true ) + ret i32 %tmp ; CHECK: t2: ; CHECK: bsfl -; CHECK: cmov +; CHECK-NOT: cmov +; CHECK: ret } declare i32 @llvm.cttz.i32(i32, i1) nounwind readnone define i16 @t3(i16 %x, i16 %y) nounwind { entry: - %tmp1 = add i16 %x, %y - %tmp2 = tail call i16 @llvm.ctlz.i16( i16 %tmp1, i1 true ) ; [#uses=1] - ret i16 %tmp2 + %tmp1 = add i16 %x, %y + %tmp2 = tail call i16 @llvm.ctlz.i16( i16 %tmp1, i1 true ) ; [#uses=1] + ret i16 %tmp2 ; CHECK: t3: ; CHECK: bsrw -; CHECK: cmov +; CHECK-NOT: cmov +; CHECK: xorw $15, +; CHECK: ret } declare i16 @llvm.ctlz.i16(i16, i1) nounwind readnone -; Don't generate the cmovne when the source is known non-zero (and bsr would -; not set ZF). -; rdar://9490949 - define i32 @t4(i32 %n) nounwind { entry: +; Generate a cmov to handle zero inputs when necessary. ; CHECK: t4: ; CHECK: bsrl +; CHECK: cmov +; CHECK: xorl $31, +; CHECK: ret + %tmp1 = tail call i32 @llvm.ctlz.i32(i32 %n, i1 false) + ret i32 %tmp1 +} + +define i32 @t5(i32 %n) nounwind { +entry: +; Don't generate the cmovne when the source is known non-zero (and bsr would +; not set ZF). +; rdar://9490949 +; CHECK: t5: +; CHECK: bsrl ; CHECK-NOT: cmov +; CHECK: xorl $31, ; CHECK: ret %or = or i32 %n, 1 - %tmp1 = tail call i32 @llvm.ctlz.i32(i32 %or, i1 true) + %tmp1 = tail call i32 @llvm.ctlz.i32(i32 %or, i1 false) ret i32 %tmp1 } From chandlerc at gmail.com Tue Dec 20 05:25:32 2011 From: chandlerc at gmail.com (Chandler Carruth) Date: Tue, 20 Dec 2011 03:25:32 -0800 Subject: [llvm-commits] PATCH: Enable direct selection of bsf and bsr instructions for cttz and ctlz with zero-undef behavior In-Reply-To: <68E0DAB7-2B39-4B4C-816A-4408DCFBAF42@apple.com> References:

<6C5EBBA2-AC05-4F55-871D-D7657848266B@apple.com> <68E0DAB7-2B39-4B4C-816A-4408DCFBAF42@apple.com> Message-ID: On Mon, Dec 19, 2011 at 12:07 PM, Evan Cheng wrote: > > On Dec 17, 2011, at 2:29 AM, Chandler Carruth wrote: > > On Thu, Dec 15, 2011 at 7:52 AM, Stephen Canon wrote: > >> Just for the record, this is in no way unique to AMD. Agner Fog's tables >> list BSF/BSR as 10 ?ops/16 cycles on Atom as well. BSF is a hazard to be >> avoided on an unknown x86 processor. >> > > I really wasn't trying to draw generalizations. I've read the same tables. > =/ I'm not sure what your concerned about here, this patch is orthogonal to > any work on avoiding these instructions on architectures where they just > decode to silly microcode. > > I'd still really appreciate some review on the actual patch. It's pretty > simple. > > > The patch looks fine to me. > Thanks! Testing a boot-strap uncovered a pretty silly miscompile; I'd not correctly modeled the essentially insane semantics of bsr. The fix was spotted by Benjamin Kramer and he checked my (obvious) fix. I've committed the fixed patch, with improved tests in r146974. I'll watch the bots just in case. -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20111220/184bd2d6/attachment.html From elena.demikhovsky at intel.com Tue Dec 20 07:34:29 2011 From: elena.demikhovsky at intel.com (Elena Demikhovsky) Date: Tue, 20 Dec 2011 13:34:29 -0000 Subject: [llvm-commits] [llvm] r146975 - in /llvm/trunk: lib/Target/X86/X86InstrSSE.td test/CodeGen/X86/2011-12-08-AVXISelBugs.ll Message-ID: <20111220133429.48F822A6C12C@llvm.org> Author: delena Date: Tue Dec 20 07:34:28 2011 New Revision: 146975 URL: http://llvm.org/viewvc/llvm-project?rev=146975&view=rev Log: This is the second fix related to VZEXT_MOVL node. The failure that I see in the current version is: LLVM ERROR: Cannot select: 0x18b8f70: v4i64 = X86ISD::VZEXT_MOVL 0x18beee0 [ID=14] 0x18beee0: v4i64 = insert_subvector 0x18b8c70, 0x18b9170, 0x18b9570 [ID=13] 0x18b8c70: v4i64 = insert_subvector 0x18b9870, 0x18bf4e0, 0x18b9970 [ID=12] 0x18b9870: v4i64 = undef [ID=4] 0x18bf4e0: v2i64 = bitcast 0x18bf3e0 [ID=10] 0x18bf3e0: v4i32 = BUILD_VECTOR 0x18b9770, 0x18b9770, 0x18b9770, 0x18b9770 [ID=8] 0x18b9770: i32 = TargetConstant<0> [ID=6] 0x18b9770: i32 = TargetConstant<0> [ID=6] 0x18b9770: i32 = TargetConstant<0> [ID=6] 0x18b9770: i32 = TargetConstant<0> [ID=6] 0x18b9970: i32 = Constant<0> [ID=3] 0x18b9170: v2i64 = undef [ORD=1] [ID=1] 0x18b9570: i32 = Constant<2> [ID=5] Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td llvm/trunk/test/CodeGen/X86/2011-12-08-AVXISelBugs.ll Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrSSE.td?rev=146975&r1=146974&r2=146975&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86InstrSSE.td (original) +++ llvm/trunk/lib/Target/X86/X86InstrSSE.td Tue Dec 20 07:34:28 2011 @@ -628,7 +628,12 @@ (VMOVSDrr (v2f64 (V_SET0)), (EXTRACT_SUBREG (v4f64 VR256:$src), sub_sd)), sub_xmm)>; - // Extract and store. + def : Pat<(v4i64 (X86vzmovl (v4i64 VR256:$src))), + (SUBREG_TO_REG (i32 0), + (VMOVSDrr (v2i64 (V_SET0)), + (EXTRACT_SUBREG (v4i64 VR256:$src), sub_sd)), sub_xmm)>; + +// Extract and store. def : Pat<(store (f32 (vector_extract (v4f32 VR128:$src), (iPTR 0))), addr:$dst), (VMOVSSmr addr:$dst, Modified: llvm/trunk/test/CodeGen/X86/2011-12-08-AVXISelBugs.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2011-12-08-AVXISelBugs.ll?rev=146975&r1=146974&r2=146975&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/X86/2011-12-08-AVXISelBugs.ll (original) +++ llvm/trunk/test/CodeGen/X86/2011-12-08-AVXISelBugs.ll Tue Dec 20 07:34:28 2011 @@ -69,3 +69,12 @@ %2 = insertelement <3 x i64> , i64 %1, i32 0 ret <3 x i64> %2 } + +define void @t5() nounwind { +entry: + %0 = shufflevector <2 x i64> zeroinitializer, <2 x i64> undef, <8 x i32> + %1 = shufflevector <8 x i64> , <8 x i64> %0, <8 x i32> + store <8 x i64> %1, <8 x i64> addrspace(1)* undef, align 64 + + ret void +} From kristof.beyls at arm.com Tue Dec 20 07:43:39 2011 From: kristof.beyls at arm.com (Kristof Beyls) Date: Tue, 20 Dec 2011 13:43:39 -0000 Subject: [llvm-commits] [PATCH] MC ARM Thumb: fix incorrect relocation generation (PR11214) Message-ID: <000001ccbf1d$618f7490$24ae5db0$@beyls@arm.com> Hi, Please find a patch for fixing incorrect generation of relocation information on Thumb function calls. This should fix quite a few incorrect code generation problems in Thumb mode when using the integrated assembler. I believe this fixes PR11214 (http://www.llvm.org/bugs/show_bug.cgi?id=11214). Is this OK? Thanks, Kristof -------------- next part -------------- A non-text attachment was scrubbed... Name: fix_thumbcall_reloc.patch Type: application/octet-stream Size: 1418 bytes Desc: not available Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20111220/b6f2c5f9/attachment-0001.obj From klimek at google.com Tue Dec 20 08:54:16 2011 From: klimek at google.com (Manuel Klimek) Date: Tue, 20 Dec 2011 15:54:16 +0100 Subject: [llvm-commits] PATCH: remove unused variable TheError Message-ID: While searching for an example to model my use of SourceMgr after, I stumbled over LLLexer.h and found what looks like an unused variable - this patch would remove it, if there's not some hidden use of TheError that I'm missing. diff --git a/lib/AsmParser/LLLexer.h b/lib/AsmParser/LLLexer.h index 33b9135..09aea5b 100644 --- a/lib/AsmParser/LLLexer.h +++ b/lib/AsmParser/LLLexer.h @@ -42,7 +42,6 @@ namespace llvm { APFloat APFloatVal; APSInt APSIntVal; - std::string TheError; public: explicit LLLexer(MemoryBuffer *StartBuf, SourceMgr &SM, SMDiagnostic &, LLVMContext &C); From axwalk at gmail.com Tue Dec 20 08:56:09 2011 From: axwalk at gmail.com (Andrew Wilkins) Date: Tue, 20 Dec 2011 22:56:09 +0800 Subject: [llvm-commits] [PATCH] Extend named metadata support in the LLVM C API In-Reply-To: References:

Message-ID: On Tue, Dec 20, 2011 at 2:06 AM, Devang Patel wrote: > > We want to preserve backward compatibility in C API as much as possible. > So we don't want to remove LLVMGetNamedMetadataOperands or change signature > of LLVMGetNamedMetadataNumOperands. > Thanks for the feedback. Fair enough. Attached is a more conservative patch, just adding one new function LLVMAddNamedMetadataOperand. Regards, -- Andrew Wilkins http://awilkins.id.au -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20111220/70673ea3/attachment.html -------------- next part -------------- A non-text attachment was scrubbed... Name: llvm-capi-namedmd-take2.diff Type: application/octet-stream Size: 1356 bytes Desc: not available Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20111220/70673ea3/attachment.obj From hfinkel at anl.gov Tue Dec 20 11:22:20 2011 From: hfinkel at anl.gov (Hal Finkel) Date: Tue, 20 Dec 2011 11:22:20 -0600 Subject: [llvm-commits] [PATCH] Allow SelectionDAGBuilder to reorder loads past stores In-Reply-To: <2264DB7F-F14F-4D93-B6C1-79D69B5F2DBF@apple.com> References: <1324316529.31367.96.camel@sapling> <945273C4-D0AA-4CAF-B0ED-C6D96A52FE02@apple.com> <1324325951.31367.178.camel@sapling> <1324355462.31367.287.camel@sapling> <2264DB7F-F14F-4D93-B6C1-79D69B5F2DBF@apple.com> Message-ID: <1324401740.31367.437.camel@sapling> On Mon, 2011-12-19 at 22:46 -0800, Evan Cheng wrote: > On Dec 19, 2011, at 8:31 PM, Hal Finkel wrote: > > > On Mon, 2011-12-19 at 15:02 -0800, Evan Cheng wrote: > >> On Dec 19, 2011, at 12:19 PM, Hal Finkel wrote: > >> > >>> On Mon, 2011-12-19 at 10:52 -0800, Evan Cheng wrote: > >>>> Hi Hal, > >>>> > >>>> IMHO, this is the wrong way to fix this problem. The fundamental issue here is SelectionDAG is being used by the pre-RA scheduler so the conservative DAG building can have a significant impact on the schedule and the performance of generated code. Changing SelectionDAGBuilder to relax this is one way to go about this. But as you can tell, the current scheduler is not quite ready for this and you can see some large performance regressions. > >>>> > >>> > >>> Fair enough, however, I fear that whether they get the load/store > >>> independence information from the DAG or from their own aliasing > >>> analysis, the results will be equally good (or bad) as with the current > >>> patch. Either way, it is the scheduling heuristics that will need > >>> improving. > >> > >> Right. One of the argument for doing scheduling on MachineInstr's and later in the codegen pipeline is so it can make better decisions. For example, currently the pre-RA scheduler does a decent job of estimating register pressure. However, instructions are moved (LICM, sink), deleted (coalescing, CSE) so by definition the scheduler is working with half accurate information. > >> > >>> > >>> As far as I can tell, most applications exhibit a performance gain from > >>> this patch. So *if* the regressions are caused by deficiencies in > >>> scheduling heuristics (as opposed to problems with DAGCombine or > >>> Legalize), it might be worthwhile eating the performance regressions for > >>> now, and using them as use cases to improve the scheduling heuristics > >>> (once any incorrect code generation is fixed). In the mean time, most > >>> users should be happier ;) > >> > >> Unfortunately, we can't allow changes that cause massive regressions. For example, 88% regressions to LAME encoding. Even if that means a lot of other benchmarks are benefiting from the change. These regressions have to be studied, understood, and fixed before the change can be enabled. > >> > >>> > >>>> We have long understood the current scheduling strategy is wrong. The plan for 2012 is to add a MachineInstr pre-RA scheduler and leave SelectionDAG for legalizer and dag combine. The new scheduler will probably use aliasing information to reorder loads / stores. > >>>> > >>> > >>> The key point here is making sure that the scheduler has enough > >>> information to make full use of the aliasing analysis. This is not > >>> currently the case. The easiest way of doing this would be to make sure > >>> that the scheduler has access to the original IR instructions. > >>> Alternatively, the aliasing analysis could be enhanced to deal with ptr > >>> +offset pairs, etc. > >>> > >>>> The problem with changing SelectionDAGBuilder is this can negatively impact optimizations done during dag combine and legalization. So as it is the patch should not be enabled by default. At best, it can be committed but turned off. Do you have a good understanding what caused the severe regressions you have identified? > >>> > >>> I have not yet looked into all of the regressions in detail. From what I > >>> have seen, the ILP scheduler, once it is revealed that the loads/stores > >>> are independent, tends to schedule many loads together in a big block, > >>> then a block of computation, then a block of stores. This is (highly) > >>> suboptimal compared to the original sequence in some cases. > >> > >> Right and this should be fixed. > > > > I'll investigate this further, but here is a simple example of what can > > happen. Consider the following loop: > > > > __attribute__((aligned(16))) float a[LEN],b[LEN],c[LEN]; > > > > for (int i = 0; i < LEN; i++) { > > a[i] = sin(b[i]) + cos(c[i]); > > } > > > > where the loop is partially unrolled. Without the patch, this compiles > > to: > > movss c-36(,%rbx,4), %xmm0 > > cvtss2sd %xmm0, %xmm0 > > callq cos > > movsd %xmm0, 16(%rsp) # 8-byte Spill > > movss b-36(,%rbx,4), %xmm0 > > cvtss2sd %xmm0, %xmm0 > > callq sin > > addsd 16(%rsp), %xmm0 # 8-byte Folded Reload > > cvtsd2ss %xmm0, %xmm0 > > movss %xmm0, a-36(,%rbx,4) > > ... > > > > With the patch, the scheduler is allowed to schedule the loads for the > > next iteration before the store from the pervious iteration, and it > > does. Unfortunately, it does it like this: > > movss c-36(,%rbx,4), %xmm0 > > cvtss2sd %xmm0, %xmm0 > > callq cos > > movsd %xmm0, 64(%rsp) # 8-byte Spill > > movss b-36(,%rbx,4), %xmm0 > > cvtss2sd %xmm0, %xmm0 > > callq sin > > addsd 64(%rsp), %xmm0 # 8-byte Folded Reload > > cvtsd2ss %xmm0, %xmm0 > > movss %xmm0, 56(%rsp) # 4-byte Spill > > movss c-32(,%rbx,4), %xmm0 > > cvtss2sd %xmm0, %xmm0 > > callq cos > > movsd %xmm0, 64(%rsp) # 8-byte Spill > > movss 56(%rsp), %xmm0 # 4-byte Reload > > movss %xmm0, a-36(,%rbx,4) > > ... > > > > So, in short, it introduces an unnecessary stack spill in order to delay > > the store. Any ideas on why it would do this? > > Not sure. Are nodes being scheduled across call nodes? Please add -debug-only=pre-RA-sched and compare the schedules. I've looked at the debugging output, I am not sure what I am looking for, however. In the good version, because the result is stored immediately, there is no issue with how registers are allocated, etc. across calls. The "bad" version would work fine without the stack spill. There are plenty of unused callee-saved registers that could be used to hold that result instead of spilling it to the stack. The question is just why none of them are being used in favor of the stack spill. Looking at the schedule reveals: SU(31): 0x56a8db0: f64 = ADDSDrr 0x56e3740, 0x56e2a30 [ORD=21] [ID=31] SU(30): 0x56a8bb0: f32 = CVTSD2SSrr 0x56a8db0 [ORD=22] [ID=30] ... (other stuff including a call) ... SU(29): 0x56ada80: ch = MOVSSmr 0x56a97b0, 0x56a95b0, 0x56ad180, 0x56b30f0, 0x56df500, 0x56a8bb0, 0x564dec0 [ORD=28] [ID=29] but that does not explain to me why the spill is there. When SelectionDAGBuilder sees the instruction stream, those calls to cos() and sin() are not really calls, but are intrinsics that get mapped to ISD::FCOS and ISD::FSIN, and so they don't trigger any flushing of the pending-memory-operations queue. When in comes to register allocations, we get something like this: 592B %vreg15 = ADDSDrr %vreg15, %vreg11; FR64:% vreg15,%vreg11 608B %vreg16 = CVTSD2SSrr %vreg15; FR32:%vreg16 FR64:%vreg15 624B ADJCALLSTACKDOWN64 0, %RSP, % EFLAGS, %RSP 640B %vreg17 = MOVSSrm %noreg, 4, %vreg2, , % noreg; mem:LD4[%scevgep25] FR32:%vreg17 GR64_NOSP:%vreg2 656B %vreg18 = CVTSS2SDrr %vreg17; FR64:%vreg18 FR32:%vreg17 672B %XMM0 = COPY %vreg18; FR64:%vreg18 688B CALL64pcrel32 , %XMM0, %RAX, %RDX, %RSI, %RDI, % XMM0, %EFLAGS, %RSP, ... 704B ADJCALLSTACKUP64 0, 0, %RSP, % EFLAGS, %RSP 720B %vreg19 = COPY %XMM0; FR64:%vreg19 736B ADJCALLSTACKDOWN64 0, %RSP, % EFLAGS, %RSP 752B MOVSSmr %noreg, 4, %vreg2, , %noreg, % vreg16; mem:ST4[%scevgep106](align=8)(tbaa=!"float") GR64_NOSP:% vreg2 FR32:%vreg16 then during allocation I see a message: selectOrSplit FR32:%vreg16,3.202614e-01 = [608r,752r:0) 0 at 608r RS_Assign Cascade 0 wait for second round queuing new interval: %vreg16,3.202614e-01 = [608r,752r:0) 0 at 608r and then: selectOrSplit FR32:%vreg16,3.202614e-01 = [608r,752r:0) 0 at 608r RS_Split Cascade 0 Analyze counted 2 instrs in 1 blocks, through 0 blocks. Inline spilling FR32:%vreg16,3.202614e-01 = [608r,752r:0) 0 at 608r >From original %vreg16,3.202614e-01 = [608r,752r:0) 0 at 608r Merged spilled regs: SS#19 = [608r,752r:0) 0 at invalid spillAroundUses %vreg16 rewrite: 608r %vreg128 = CVTSD2SSrr %vreg15; FR32:% vreg128 FR64:%vreg15 spilled: 616r MOVSSmr , 1, %noreg, 0, %noreg, % vreg128; mem:ST4[FixedStack19] FR32:%vreg128 interval: %vreg128,inf = [608r,616r:0) 0 at 608r reload: 744r %vreg129 = MOVSSrm , 1, %noreg, 0, % noreg; mem:LD4[FixedStack19] FR32:%vreg129 rewrite: 752r MOVSSmr %noreg, 4, %vreg104, , % noreg, %vreg129; mem:ST4[%scevgep106](align=8)(tbaa=!"float") GR64_NOSP:%vreg104 FR32:%vreg129 interval: %vreg129,inf = [744r,752r:0) 0 at 744r queuing new interval: %vreg128,inf = [608r,616r:0) 0 at 608r queuing new interval: %vreg129,inf = [744r,752r:0) 0 at 744r when I later look at the register map, only XMM0 and XMM1 are ever assigned to vregs, everything else is spilled. This is wrong. Do you have any ideas on what could be going wrong or other things I should examine? Could the register allocator not be accounting correctly for callee-saved registers when computing live-interval interference information? Thanks again, Hal > > Evan > > > > >> > >>> > >>> I would be fine with submitting the patch such that it is turned off by > >>> default. Especially while there are test-suite failures, I think that it > >>> would need to be this way. > >> > >> That's a reasonable compromise. Someone will have review the patch carefully first though. > >> > >> BTW, what's the compile time impact? > > > > I looked at this quickly with my debug build, and it seemed to have a > > negligible effect (I've put the default cap on the reorder buffer at 8, > > so any effect is bound to be small, it seemed just as small when I set > > the buffer size to 64). I'll do a test suite run with an optimized build > > to get some real timing numbers. > > > > Thanks again, > > Hal > > > >> > >> Evan > >> > >>> > >>> Thanks again, > >>> Hal > >>> > >>>> > >>>> Evan > >>>> > >>>> On Dec 19, 2011, at 9:42 AM, Hal Finkel wrote: > >>>> > >>>>> The current SelectionDAGBuilder does not allow loads to be reordered > >>>>> past stores, and does not allow stores to be reordered. This is a side > >>>>> effect of the way the critical chain is constructed: there is a queue of > >>>>> pending loads that is flushed (in parallel) to the root of the chain > >>>>> upon encountering any store (and that store is also appended to the root > >>>>> of the chain). Among other things, loop unrolling is far less effective > >>>>> than it otherwise could be. > >>>>> > >>>>> The attached patch allows SelectionDAGBuilder to use the available alias > >>>>> analysis to reorder independent loads and stores. It changes the queue > >>>>> of pending loads into a more general queue of pending memory operations, > >>>>> and flushes, in parallel, all potentially-conflicting loads and stores > >>>>> as necessary. > >>>>> > >>>>> This can result in a significant performance boost. On my x86_64 > >>>>> machine, the average percentage decrease in execution time is ~8% (to > >>>>> calculate my performance numbers from the test suite, I've included only > >>>>> the 174 tests with a base execution time of at least 0.1s; the times of > >>>>> the shorter tests seem noisy on my machine). Of these, 131 showed a > >>>>> performance increase and 36 showed a performance decrease. > >>>>> > >>>>> The top-5 winners were: > >>>>> MultiSource/Benchmarks/MiBench/consumer-typeset/consumer-typeset - 92% > >>>>> performance increase ( = runtime decrease) > >>>>> MultiSource/Benchmarks/llubenchmark/llu - 47% performance increase > >>>>> MultiSource/Applications/minisat/minisat - 47% performance increase > >>>>> MultiSource/Benchmarks/sim/sim - 40% performance increase > >>>>> MultiSource/Benchmarks/Prolangs-C++/life/life - 35.7% performance > >>>>> increase > >>>>> The top-5 losers were: > >>>>> MultiSource/Benchmarks/MiBench/consumer-lame/consumer-lame - 88% > >>>>> performance decrease > >>>>> MultiSource/Benchmarks/VersaBench/beamformer/beamformer - 49% > >>>>> performance decrease > >>>>> MultiSource/Benchmarks/MallocBench/espresso/espresso 47% performance > >>>>> decrease > >>>>> MultiSource/Benchmarks/MiBench/automotive-bitcount/automotive-bitcount - > >>>>> 21% performance decrease > >>>>> MultiSource/Benchmarks/MiBench/network-patricia/network-patricia - 20% > >>>>> performance decrease > >>>>> > >>>>> The patch adds a few new options: > >>>>> max-parallel-chains - replaces the old MaxParallelChains constant) > >>>>> max-load-store-reorder - the maximum size of the reorder buffer - > >>>>> previously it was unlimited, but contained only stores > >>>>> no-reordering-past-stores - invokes the previous behavior > >>>>> > >>>>> Some of the regression tests had to be updated because the order of some > >>>>> stores changed. For most of these, I just updated the test to reflect > >>>>> the new instruction sequence. The following tests I've marked as XFAIL > >>>>> because they would require larger changes (and I'd like someone with > >>>>> more experience than me to make sure that they really are okay and make > >>>>> any necessary adjustments): > >>>>> CodeGen/X86/2008-02-22-LocalRegAllocBug.ll > >>>>> CodeGen/X86/2010-09-17-SideEffectsInChain.ll > >>>>> CodeGen/X86/lea-recursion.ll > >>>>> > >>>>> Also, there is one test-suite runtime failure on x86_64: > >>>>> MultiSource/Benchmarks/Ptrdist/ft/ft > >>>>> > >>>>> And several test-suite runtime failures on i686: > >>>>> MultiSource/Benchmarks/tramp3d-v4/tramp3d-v4 > >>>>> SingleSource/Benchmarks/Misc-C++/Large/ray > >>>>> SingleSource/Benchmarks/Misc-C++/stepanov_container > >>>>> SingleSource/Benchmarks/Shootout-C++/lists > >>>>> SingleSource/Benchmarks/Shootout-C++/lists1 > >>>>> SingleSource/Benchmarks/Shootout-C++/sieve > >>>>> > >>>>> Please review (and help with the test-suite failures). > >>>>> > >>>>> Thank you in advance, > >>>>> Hal > >>>>> > >>>>> -- > >>>>> Hal Finkel > >>>>> Postdoctoral Appointee > >>>>> Leadership Computing Facility > >>>>> Argonne National Laboratory > >>>>> > >>>>> _______________________________________________ > >>>>> llvm-commits mailing list > >>>>> llvm-commits at cs.uiuc.edu > >>>>> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits > >>>> > >>> > >>> -- > >>> Hal Finkel > >>> Postdoctoral Appointee > >>> Leadership Computing Facility > >>> Argonne National Laboratory > >>> > >> > > > > -- > > Hal Finkel > > Postdoctoral Appointee > > Leadership Computing Facility > > Argonne National Laboratory > > > -- Hal Finkel Postdoctoral Appointee Leadership Computing Facility Argonne National Laboratory From jason.w.kim.2009 at gmail.com Tue Dec 20 11:38:12 2011 From: jason.w.kim.2009 at gmail.com (Jason W Kim) Date: Tue, 20 Dec 2011 17:38:12 -0000 Subject: [llvm-commits] [llvm] r146977 - /llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Message-ID: <20111220173813.0BD732A6C12C@llvm.org> Author: jasonwkim Date: Tue Dec 20 11:38:12 2011 New Revision: 146977 URL: http://llvm.org/viewvc/llvm-project?rev=146977&view=rev Log: First steps in ARM AsmParser support for .eabi_attribute and .arch (Both used for Linux gnueabi) No behavioral change yet (no tests need so far) Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp?rev=146977&r1=146976&r2=146977&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp (original) +++ llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Tue Dec 20 11:38:12 2011 @@ -101,6 +101,8 @@ bool parseDirectiveSyntax(SMLoc L); bool parseDirectiveReq(StringRef Name, SMLoc L); bool parseDirectiveUnreq(SMLoc L); + bool parseDirectiveArch(SMLoc L); + bool parseDirectiveEabiAttr(SMLoc L); StringRef splitMnemonic(StringRef Mnemonic, unsigned &PredicationCode, bool &CarrySetting, unsigned &ProcessorIMod, @@ -6121,6 +6123,10 @@ return parseDirectiveSyntax(DirectiveID.getLoc()); else if (IDVal == ".unreq") return parseDirectiveUnreq(DirectiveID.getLoc()); + else if (IDVal == ".arch") + return parseDirectiveArch(DirectiveID.getLoc()); + else if (IDVal == ".eabi_attribute") + return parseDirectiveEabiAttr(DirectiveID.getLoc()); return true; } @@ -6300,6 +6306,18 @@ return false; } +/// parseDirectiveArch +/// ::= .arch token +bool ARMAsmParser::parseDirectiveArch(SMLoc L) { + return true; +} + +/// parseDirectiveEabiAttr +/// ::= .eabi_attribute int, int +bool ARMAsmParser::parseDirectiveEabiAttr(SMLoc L) { + return true; +} + extern "C" void LLVMInitializeARMAsmLexer(); /// Force static initialization. From evan.cheng at apple.com Tue Dec 20 11:57:34 2011 From: evan.cheng at apple.com (Evan Cheng) Date: Tue, 20 Dec 2011 09:57:34 -0800 Subject: [llvm-commits] [llvm] r146801 - in /llvm/trunk: include/llvm/MC/MCStreamer.h lib/CodeGen/AsmPrinter/AsmPrinterDwarf.cpp lib/MC/MCAsmStreamer.cpp lib/MC/MCLoggingStreamer.cpp lib/MC/MCNullStreamer.cpp lib/MC/MCParser/COFFAsmParser.cpp lib/MC/MCStr In-Reply-To: References: Message-ID: <365ECA24-CB73-409A-AFB5-7091BB88827C@apple.com> Hi Rafael, Chandler is absolutely right. Please revert the patch. Thanks, Evan On Dec 20, 2011, at 2:03 AM, Chandler Carruth wrote: > On Fri, Dec 16, 2011 at 5:14 PM, Rafael Espindola wrote: > Modified: llvm/trunk/lib/MC/WinCOFFStreamer.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/WinCOFFStreamer.cpp?rev=146801&r1=146800&r2=146801&view=diff > ============================================================================== > --- llvm/trunk/lib/MC/WinCOFFStreamer.cpp (original) > +++ llvm/trunk/lib/MC/WinCOFFStreamer.cpp Fri Dec 16 19:14:52 2011 > @@ -32,6 +32,9 @@ > #include "llvm/Support/ErrorHandling.h" > #include "llvm/Support/TargetRegistry.h" > #include "llvm/Support/raw_ostream.h" > + > +#include "../Target/X86/MCTargetDesc/X86FixupKinds.h" > + > > This is a pretty egregious layering violation. Please fix or revert, this causes all kinds of problems with improper dependencies between various components. > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20111220/cae33586/attachment.html From evan.cheng at apple.com Tue Dec 20 12:26:51 2011 From: evan.cheng at apple.com (Evan Cheng) Date: Tue, 20 Dec 2011 18:26:51 -0000 Subject: [llvm-commits] [llvm] r146981 - in /llvm/trunk: lib/Target/ARM/ test/CodeGen/ARM/ test/CodeGen/Thumb2/ Message-ID: <20111220182651.DE0ED2A6C12C@llvm.org> Author: evancheng Date: Tue Dec 20 12:26:50 2011 New Revision: 146981 URL: http://llvm.org/viewvc/llvm-project?rev=146981&view=rev Log: ARM target code clean up. Check for iOS, not Darwin where it makes sense. Modified: llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp llvm/trunk/lib/Target/ARM/ARMFastISel.cpp llvm/trunk/lib/Target/ARM/ARMInstrInfo.td llvm/trunk/lib/Target/ARM/ARMInstrThumb.td llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp llvm/trunk/lib/Target/ARM/ARMSubtarget.h llvm/trunk/test/CodeGen/ARM/2010-11-29-PrologueBug.ll llvm/trunk/test/CodeGen/ARM/2011-06-16-TailCallByVal.ll llvm/trunk/test/CodeGen/ARM/call-tc.ll llvm/trunk/test/CodeGen/ARM/debug-info-blocks.ll llvm/trunk/test/CodeGen/ARM/fast-isel-br-const.ll llvm/trunk/test/CodeGen/ARM/fast-isel-call.ll llvm/trunk/test/CodeGen/ARM/fast-isel-cmp-imm.ll llvm/trunk/test/CodeGen/ARM/fast-isel-conversion.ll llvm/trunk/test/CodeGen/ARM/fast-isel-deadcode.ll llvm/trunk/test/CodeGen/ARM/fast-isel-icmp.ll llvm/trunk/test/CodeGen/ARM/fast-isel-intrinsic.ll llvm/trunk/test/CodeGen/ARM/fast-isel-ldr-str-thumb-neg-index.ll llvm/trunk/test/CodeGen/ARM/fast-isel-ldrh-strh-arm.ll llvm/trunk/test/CodeGen/ARM/fast-isel-mvn.ll llvm/trunk/test/CodeGen/ARM/fast-isel-ret.ll llvm/trunk/test/CodeGen/ARM/fast-isel-select.ll llvm/trunk/test/CodeGen/ARM/fast-isel.ll llvm/trunk/test/CodeGen/Thumb2/2009-07-21-ISelBug.ll Modified: llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp?rev=146981&r1=146980&r2=146981&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp Tue Dec 20 12:26:50 2011 @@ -72,8 +72,8 @@ 0 }; - static const unsigned DarwinCalleeSavedRegs[] = { - // Darwin ABI deviates from ARM standard ABI. R9 is not a callee-saved + static const unsigned iOSCalleeSavedRegs[] = { + // iOS ABI deviates from ARM standard ABI. R9 is not a callee-saved // register. ARM::LR, ARM::R7, ARM::R6, ARM::R5, ARM::R4, ARM::R11, ARM::R10, ARM::R8, @@ -82,7 +82,7 @@ ARM::D11, ARM::D10, ARM::D9, ARM::D8, 0 }; - return STI.isTargetDarwin() ? DarwinCalleeSavedRegs : CalleeSavedRegs; + return (STI.isTargetIOS()) ? iOSCalleeSavedRegs : CalleeSavedRegs; } BitVector ARMBaseRegisterInfo:: Modified: llvm/trunk/lib/Target/ARM/ARMFastISel.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMFastISel.cpp?rev=146981&r1=146980&r2=146981&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMFastISel.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMFastISel.cpp Tue Dec 20 12:26:50 2011 @@ -2012,12 +2012,12 @@ unsigned ARMFastISel::ARMSelectCallOp(const GlobalValue *GV) { - // Darwin needs the r9 versions of the opcodes. - bool isDarwin = Subtarget->isTargetDarwin(); + // iOS needs the r9 versions of the opcodes. + bool isiOS = Subtarget->isTargetIOS(); if (isThumb2) { - return isDarwin ? ARM::tBLr9 : ARM::tBL; + return isiOS ? ARM::tBLr9 : ARM::tBL; } else { - return isDarwin ? ARM::BLr9 : ARM::BL; + return isiOS ? ARM::BLr9 : ARM::BL; } } @@ -2076,7 +2076,7 @@ if (!ProcessCallArgs(Args, ArgRegs, ArgVTs, ArgFlags, RegArgs, CC, NumBytes)) return false; - // Issue the call, BLr9 for darwin, BL otherwise. + // Issue the call, BLr9 for iOS, BL otherwise. // TODO: Turn this into the table of arm call ops. MachineInstrBuilder MIB; unsigned CallOpc = ARMSelectCallOp(NULL); @@ -2197,7 +2197,7 @@ if (!ProcessCallArgs(Args, ArgRegs, ArgVTs, ArgFlags, RegArgs, CC, NumBytes)) return false; - // Issue the call, BLr9 for darwin, BL otherwise. + // Issue the call, BLr9 for iOS, BL otherwise. // TODO: Turn this into the table of arm call ops. MachineInstrBuilder MIB; unsigned CallOpc = ARMSelectCallOp(GV); @@ -2514,12 +2514,12 @@ namespace llvm { llvm::FastISel *ARM::createFastISel(FunctionLoweringInfo &funcInfo) { - // Completely untested on non-darwin. + // Completely untested on non-iOS. const TargetMachine &TM = funcInfo.MF->getTarget(); // Darwin and thumb1 only for now. const ARMSubtarget *Subtarget = &TM.getSubtarget(); - if (Subtarget->isTargetDarwin() && !Subtarget->isThumb1Only() && + if (Subtarget->isTargetIOS() && !Subtarget->isThumb1Only() && !DisableARMFastISel) return new ARMFastISel(funcInfo); return 0; Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.td?rev=146981&r1=146980&r2=146981&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrInfo.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Tue Dec 20 12:26:50 2011 @@ -206,8 +206,8 @@ AssemblerPredicate<"!FeatureMClass">; def IsARM : Predicate<"!Subtarget->isThumb()">, AssemblerPredicate<"!ModeThumb">; -def IsDarwin : Predicate<"Subtarget->isTargetDarwin()">; -def IsNotDarwin : Predicate<"!Subtarget->isTargetDarwin()">; +def IsIOS : Predicate<"Subtarget->isTargetIOS()">; +def IsNotIOS : Predicate<"!Subtarget->isTargetIOS()">; def IsNaCl : Predicate<"Subtarget->isTargetNaCl()">; // FIXME: Eventually this will be just "hasV6T2Ops". @@ -1896,7 +1896,7 @@ // a use to prevent stack-pointer assignments that appear immediately // before calls from potentially appearing dead. let isCall = 1, - // On non-Darwin platforms R9 is callee-saved. + // On non-IOS platforms R9 is callee-saved. // FIXME: Do we really need a non-predicated version? If so, it should // at least be a pseudo instruction expanding to the predicated version // at MC lowering time. @@ -1905,7 +1905,7 @@ def BL : ABXI<0b1011, (outs), (ins bl_target:$func, variable_ops), IIC_Br, "bl\t$func", [(ARMcall tglobaladdr:$func)]>, - Requires<[IsARM, IsNotDarwin]> { + Requires<[IsARM, IsNotIOS]> { let Inst{31-28} = 0b1110; bits<24> func; let Inst{23-0} = func; @@ -1915,7 +1915,7 @@ def BL_pred : ABI<0b1011, (outs), (ins bl_target:$func, variable_ops), IIC_Br, "bl", "\t$func", [(ARMcall_pred tglobaladdr:$func)]>, - Requires<[IsARM, IsNotDarwin]> { + Requires<[IsARM, IsNotIOS]> { bits<24> func; let Inst{23-0} = func; let DecoderMethod = "DecodeBranchImmInstruction"; @@ -1925,7 +1925,7 @@ def BLX : AXI<(outs), (ins GPR:$func, variable_ops), BrMiscFrm, IIC_Br, "blx\t$func", [(ARMcall GPR:$func)]>, - Requires<[IsARM, HasV5T, IsNotDarwin]> { + Requires<[IsARM, HasV5T, IsNotIOS]> { bits<4> func; let Inst{31-4} = 0b1110000100101111111111110011; let Inst{3-0} = func; @@ -1934,7 +1934,7 @@ def BLX_pred : AI<(outs), (ins GPR:$func, variable_ops), BrMiscFrm, IIC_Br, "blx", "\t$func", [(ARMcall_pred GPR:$func)]>, - Requires<[IsARM, HasV5T, IsNotDarwin]> { + Requires<[IsARM, HasV5T, IsNotIOS]> { bits<4> func; let Inst{27-4} = 0b000100101111111111110011; let Inst{3-0} = func; @@ -1944,16 +1944,16 @@ // Note: Restrict $func to the tGPR regclass to prevent it being in LR. def BX_CALL : ARMPseudoInst<(outs), (ins tGPR:$func, variable_ops), 8, IIC_Br, [(ARMcall_nolink tGPR:$func)]>, - Requires<[IsARM, HasV4T, IsNotDarwin]>; + Requires<[IsARM, HasV4T, IsNotIOS]>; // ARMv4 def BMOVPCRX_CALL : ARMPseudoInst<(outs), (ins tGPR:$func, variable_ops), 8, IIC_Br, [(ARMcall_nolink tGPR:$func)]>, - Requires<[IsARM, NoV4T, IsNotDarwin]>; + Requires<[IsARM, NoV4T, IsNotIOS]>; } let isCall = 1, - // On Darwin R9 is call-clobbered. + // On IOS R9 is call-clobbered. // R7 is marked as a use to prevent frame-pointer assignments from being // moved above / below calls. Defs = [R0, R1, R2, R3, R9, R12, LR, QQQQ0, QQQQ2, QQQQ3, CPSR, FPSCR], @@ -1961,38 +1961,38 @@ def BLr9 : ARMPseudoExpand<(outs), (ins bl_target:$func, variable_ops), 4, IIC_Br, [(ARMcall tglobaladdr:$func)], (BL bl_target:$func)>, - Requires<[IsARM, IsDarwin]>; + Requires<[IsARM, IsIOS]>; def BLr9_pred : ARMPseudoExpand<(outs), (ins bl_target:$func, pred:$p, variable_ops), 4, IIC_Br, [(ARMcall_pred tglobaladdr:$func)], (BL_pred bl_target:$func, pred:$p)>, - Requires<[IsARM, IsDarwin]>; + Requires<[IsARM, IsIOS]>; // ARMv5T and above def BLXr9 : ARMPseudoExpand<(outs), (ins GPR:$func, variable_ops), 4, IIC_Br, [(ARMcall GPR:$func)], (BLX GPR:$func)>, - Requires<[IsARM, HasV5T, IsDarwin]>; + Requires<[IsARM, HasV5T, IsIOS]>; def BLXr9_pred: ARMPseudoExpand<(outs), (ins GPR:$func, pred:$p,variable_ops), 4, IIC_Br, [(ARMcall_pred GPR:$func)], (BLX_pred GPR:$func, pred:$p)>, - Requires<[IsARM, HasV5T, IsDarwin]>; + Requires<[IsARM, HasV5T, IsIOS]>; // ARMv4T // Note: Restrict $func to the tGPR regclass to prevent it being in LR. def BXr9_CALL : ARMPseudoInst<(outs), (ins tGPR:$func, variable_ops), 8, IIC_Br, [(ARMcall_nolink tGPR:$func)]>, - Requires<[IsARM, HasV4T, IsDarwin]>; + Requires<[IsARM, HasV4T, IsIOS]>; // ARMv4 def BMOVPCRXr9_CALL : ARMPseudoInst<(outs), (ins tGPR:$func, variable_ops), 8, IIC_Br, [(ARMcall_nolink tGPR:$func)]>, - Requires<[IsARM, NoV4T, IsDarwin]>; + Requires<[IsARM, NoV4T, IsIOS]>; } let isBranch = 1, isTerminator = 1 in { @@ -2060,45 +2060,45 @@ // Tail calls. let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in { - // Darwin versions. + // IOS versions. let Defs = [R0, R1, R2, R3, R9, R12, QQQQ0, QQQQ2, QQQQ3, PC], Uses = [SP] in { def TCRETURNdi : PseudoInst<(outs), (ins i32imm:$dst, variable_ops), - IIC_Br, []>, Requires<[IsDarwin]>; + IIC_Br, []>, Requires<[IsIOS]>; def TCRETURNri : PseudoInst<(outs), (ins tcGPR:$dst, variable_ops), - IIC_Br, []>, Requires<[IsDarwin]>; + IIC_Br, []>, Requires<[IsIOS]>; def TAILJMPd : ARMPseudoExpand<(outs), (ins br_target:$dst, variable_ops), 4, IIC_Br, [], (Bcc br_target:$dst, (ops 14, zero_reg))>, - Requires<[IsARM, IsDarwin]>; + Requires<[IsARM, IsIOS]>; def TAILJMPr : ARMPseudoExpand<(outs), (ins tcGPR:$dst, variable_ops), 4, IIC_Br, [], (BX GPR:$dst)>, - Requires<[IsARM, IsDarwin]>; + Requires<[IsARM, IsIOS]>; } - // Non-Darwin versions (the difference is R9). + // Non-IOS versions (the difference is R9). let Defs = [R0, R1, R2, R3, R12, QQQQ0, QQQQ2, QQQQ3, PC], Uses = [SP] in { def TCRETURNdiND : PseudoInst<(outs), (ins i32imm:$dst, variable_ops), - IIC_Br, []>, Requires<[IsNotDarwin]>; + IIC_Br, []>, Requires<[IsNotIOS]>; def TCRETURNriND : PseudoInst<(outs), (ins tcGPR:$dst, variable_ops), - IIC_Br, []>, Requires<[IsNotDarwin]>; + IIC_Br, []>, Requires<[IsNotIOS]>; def TAILJMPdND : ARMPseudoExpand<(outs), (ins brtarget:$dst, variable_ops), 4, IIC_Br, [], (Bcc br_target:$dst, (ops 14, zero_reg))>, - Requires<[IsARM, IsNotDarwin]>; + Requires<[IsARM, IsNotIOS]>; def TAILJMPrND : ARMPseudoExpand<(outs), (ins tcGPR:$dst, variable_ops), 4, IIC_Br, [], (BX GPR:$dst)>, - Requires<[IsARM, IsNotDarwin]>; + Requires<[IsARM, IsNotIOS]>; } } @@ -4728,13 +4728,13 @@ Requires<[IsARM, NoVFP]>; } -// FIXME: Non-Darwin version(s) +// FIXME: Non-IOS version(s) let isBarrier = 1, hasSideEffects = 1, isTerminator = 1, Defs = [ R7, LR, SP ] in { def Int_eh_sjlj_longjmp : PseudoInst<(outs), (ins GPR:$src, GPR:$scratch), NoItinerary, [(ARMeh_sjlj_longjmp GPR:$src, GPR:$scratch)]>, - Requires<[IsARM, IsDarwin]>; + Requires<[IsARM, IsIOS]>; } // eh.sjlj.dispatchsetup pseudo-instruction. @@ -4804,28 +4804,28 @@ // Tail calls def : ARMPat<(ARMtcret tcGPR:$dst), - (TCRETURNri tcGPR:$dst)>, Requires<[IsDarwin]>; + (TCRETURNri tcGPR:$dst)>, Requires<[IsIOS]>; def : ARMPat<(ARMtcret (i32 tglobaladdr:$dst)), - (TCRETURNdi texternalsym:$dst)>, Requires<[IsDarwin]>; + (TCRETURNdi texternalsym:$dst)>, Requires<[IsIOS]>; def : ARMPat<(ARMtcret (i32 texternalsym:$dst)), - (TCRETURNdi texternalsym:$dst)>, Requires<[IsDarwin]>; + (TCRETURNdi texternalsym:$dst)>, Requires<[IsIOS]>; def : ARMPat<(ARMtcret tcGPR:$dst), - (TCRETURNriND tcGPR:$dst)>, Requires<[IsNotDarwin]>; + (TCRETURNriND tcGPR:$dst)>, Requires<[IsNotIOS]>; def : ARMPat<(ARMtcret (i32 tglobaladdr:$dst)), - (TCRETURNdiND texternalsym:$dst)>, Requires<[IsNotDarwin]>; + (TCRETURNdiND texternalsym:$dst)>, Requires<[IsNotIOS]>; def : ARMPat<(ARMtcret (i32 texternalsym:$dst)), - (TCRETURNdiND texternalsym:$dst)>, Requires<[IsNotDarwin]>; + (TCRETURNdiND texternalsym:$dst)>, Requires<[IsNotIOS]>; // Direct calls def : ARMPat<(ARMcall texternalsym:$func), (BL texternalsym:$func)>, - Requires<[IsARM, IsNotDarwin]>; + Requires<[IsARM, IsNotIOS]>; def : ARMPat<(ARMcall texternalsym:$func), (BLr9 texternalsym:$func)>, - Requires<[IsARM, IsDarwin]>; + Requires<[IsARM, IsIOS]>; // zextload i1 -> zextload i8 def : ARMPat<(zextloadi1 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>; Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb.td?rev=146981&r1=146980&r2=146981&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrThumb.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrThumb.td Tue Dec 20 12:26:50 2011 @@ -404,7 +404,7 @@ // prevent stack-pointer assignments that appear immediately before calls from // potentially appearing dead. let isCall = 1, - // On non-Darwin platforms R9 is callee-saved. + // On non-IOS platforms R9 is callee-saved. Defs = [R0, R1, R2, R3, R12, LR, QQQQ0, QQQQ2, QQQQ3, CPSR, FPSCR], Uses = [SP] in { // Also used for Thumb2 @@ -412,7 +412,7 @@ (outs), (ins pred:$p, t_bltarget:$func, variable_ops), IIC_Br, "bl${p}\t$func", [(ARMtcall tglobaladdr:$func)]>, - Requires<[IsThumb, IsNotDarwin]> { + Requires<[IsThumb, IsNotIOS]> { bits<22> func; let Inst{26} = func{21}; let Inst{25-16} = func{20-11}; @@ -426,7 +426,7 @@ (outs), (ins pred:$p, t_blxtarget:$func, variable_ops), IIC_Br, "blx${p}\t$func", [(ARMcall tglobaladdr:$func)]>, - Requires<[IsThumb, HasV5T, IsNotDarwin]> { + Requires<[IsThumb, HasV5T, IsNotIOS]> { bits<21> func; let Inst{25-16} = func{20-11}; let Inst{13} = 1; @@ -439,7 +439,7 @@ def tBLXr : TI<(outs), (ins pred:$p, GPR:$func, variable_ops), IIC_Br, "blx${p}\t$func", [(ARMtcall GPR:$func)]>, - Requires<[IsThumb, HasV5T, IsNotDarwin]>, + Requires<[IsThumb, HasV5T, IsNotIOS]>, T1Special<{1,1,1,?}> { // A6.2.3 & A8.6.24; bits<4> func; let Inst{6-3} = func; @@ -450,11 +450,11 @@ def tBX_CALL : tPseudoInst<(outs), (ins tGPR:$func, variable_ops), 4, IIC_Br, [(ARMcall_nolink tGPR:$func)]>, - Requires<[IsThumb, IsThumb1Only, IsNotDarwin]>; + Requires<[IsThumb, IsThumb1Only, IsNotIOS]>; } let isCall = 1, - // On Darwin R9 is call-clobbered. + // On IOS R9 is call-clobbered. // R7 is marked as a use to prevent frame-pointer assignments from being // moved above / below calls. Defs = [R0, R1, R2, R3, R9, R12, LR, QQQQ0, QQQQ2, QQQQ3, CPSR, FPSCR], @@ -463,25 +463,25 @@ def tBLr9 : tPseudoExpand<(outs), (ins pred:$p, t_bltarget:$func, variable_ops), 4, IIC_Br, [(ARMtcall tglobaladdr:$func)], (tBL pred:$p, t_bltarget:$func)>, - Requires<[IsThumb, IsDarwin]>; + Requires<[IsThumb, IsIOS]>; // ARMv5T and above, also used for Thumb2 def tBLXi_r9 : tPseudoExpand<(outs), (ins pred:$p, t_blxtarget:$func, variable_ops), 4, IIC_Br, [(ARMcall tglobaladdr:$func)], (tBLXi pred:$p, t_blxtarget:$func)>, - Requires<[IsThumb, HasV5T, IsDarwin]>; + Requires<[IsThumb, HasV5T, IsIOS]>; // Also used for Thumb2 def tBLXr_r9 : tPseudoExpand<(outs), (ins pred:$p, GPR:$func, variable_ops), 2, IIC_Br, [(ARMtcall GPR:$func)], (tBLXr pred:$p, GPR:$func)>, - Requires<[IsThumb, HasV5T, IsDarwin]>; + Requires<[IsThumb, HasV5T, IsIOS]>; // ARMv4T def tBXr9_CALL : tPseudoInst<(outs), (ins tGPR:$func, variable_ops), 4, IIC_Br, [(ARMcall_nolink tGPR:$func)]>, - Requires<[IsThumb, IsThumb1Only, IsDarwin]>; + Requires<[IsThumb, IsThumb1Only, IsIOS]>; } let isBranch = 1, isTerminator = 1, isBarrier = 1 in { @@ -523,28 +523,28 @@ // Tail calls let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in { - // Darwin versions. + // IOS versions. let Defs = [R0, R1, R2, R3, R9, R12, QQQQ0, QQQQ2, QQQQ3, PC], Uses = [SP] in { - // tTAILJMPd: Darwin version uses a Thumb2 branch (no Thumb1 tail calls - // on Darwin), so it's in ARMInstrThumb2.td. + // tTAILJMPd: IOS version uses a Thumb2 branch (no Thumb1 tail calls + // on IOS), so it's in ARMInstrThumb2.td. def tTAILJMPr : tPseudoExpand<(outs), (ins tcGPR:$dst, variable_ops), 4, IIC_Br, [], (tBX GPR:$dst, (ops 14, zero_reg))>, - Requires<[IsThumb, IsDarwin]>; + Requires<[IsThumb, IsIOS]>; } - // Non-Darwin versions (the difference is R9). + // Non-IOS versions (the difference is R9). let Defs = [R0, R1, R2, R3, R12, QQQQ0, QQQQ2, QQQQ3, PC], Uses = [SP] in { def tTAILJMPdND : tPseudoExpand<(outs), (ins t_brtarget:$dst, pred:$p, variable_ops), 4, IIC_Br, [], (tB t_brtarget:$dst, pred:$p)>, - Requires<[IsThumb, IsNotDarwin]>; + Requires<[IsThumb, IsNotIOS]>; def tTAILJMPrND : tPseudoExpand<(outs), (ins tcGPR:$dst, variable_ops), 4, IIC_Br, [], (tBX GPR:$dst, (ops 14, zero_reg))>, - Requires<[IsThumb, IsNotDarwin]>; + Requires<[IsThumb, IsNotIOS]>; } } @@ -652,7 +652,7 @@ } // Load tconstpool -// FIXME: Use ldr.n to work around a Darwin assembler bug. +// FIXME: Use ldr.n to work around a darwin assembler bug. let canFoldAsLoad = 1, isReMaterializable = 1, isCodeGenOnly = 1 in def tLDRpci : T1pIs<(outs tGPR:$Rt), (ins t_addrmode_pc:$addr), IIC_iLoad_i, "ldr", ".n\t$Rt, $addr", @@ -1262,14 +1262,14 @@ AddrModeNone, 0, NoItinerary, "","", [(set R0, (ARMeh_sjlj_setjmp tGPR:$src, tGPR:$val))]>; -// FIXME: Non-Darwin version(s) +// FIXME: Non-IOS version(s) let isBarrier = 1, hasSideEffects = 1, isTerminator = 1, isCodeGenOnly = 1, Defs = [ R7, LR, SP ] in def tInt_eh_sjlj_longjmp : XI<(outs), (ins GPR:$src, GPR:$scratch), AddrModeNone, 0, IndexModeNone, Pseudo, NoItinerary, "", "", [(ARMeh_sjlj_longjmp GPR:$src, GPR:$scratch)]>, - Requires<[IsThumb, IsDarwin]>; + Requires<[IsThumb, IsIOS]>; //===----------------------------------------------------------------------===// // Non-Instruction Patterns @@ -1307,20 +1307,20 @@ // Direct calls def : T1Pat<(ARMtcall texternalsym:$func), (tBL texternalsym:$func)>, - Requires<[IsThumb, IsNotDarwin]>; + Requires<[IsThumb, IsNotIOS]>; def : T1Pat<(ARMtcall texternalsym:$func), (tBLr9 texternalsym:$func)>, - Requires<[IsThumb, IsDarwin]>; + Requires<[IsThumb, IsIOS]>; def : Tv5Pat<(ARMcall texternalsym:$func), (tBLXi texternalsym:$func)>, - Requires<[IsThumb, HasV5T, IsNotDarwin]>; + Requires<[IsThumb, HasV5T, IsNotIOS]>; def : Tv5Pat<(ARMcall texternalsym:$func), (tBLXi_r9 texternalsym:$func)>, - Requires<[IsThumb, HasV5T, IsDarwin]>; + Requires<[IsThumb, HasV5T, IsIOS]>; // Indirect calls to ARM routines def : Tv5Pat<(ARMcall GPR:$dst), (tBLXr GPR:$dst)>, - Requires<[IsThumb, HasV5T, IsNotDarwin]>; + Requires<[IsThumb, HasV5T, IsNotIOS]>; def : Tv5Pat<(ARMcall GPR:$dst), (tBLXr_r9 GPR:$dst)>, - Requires<[IsThumb, HasV5T, IsDarwin]>; + Requires<[IsThumb, HasV5T, IsIOS]>; // zextload i1 -> zextload i8 def : T1Pat<(zextloadi1 t_addrmode_rrs1:$addr), Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td?rev=146981&r1=146980&r2=146981&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td Tue Dec 20 12:26:50 2011 @@ -3212,17 +3212,17 @@ let DecoderMethod = "DecodeThumb2BCCInstruction"; } -// Tail calls. The Darwin version of thumb tail calls uses a t2 branch, so +// Tail calls. The IOS version of thumb tail calls uses a t2 branch, so // it goes here. let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in { - // Darwin version. + // IOS version. let Defs = [R0, R1, R2, R3, R9, R12, QQQQ0, QQQQ2, QQQQ3, PC], Uses = [SP] in def tTAILJMPd: tPseudoExpand<(outs), (ins uncondbrtarget:$dst, pred:$p, variable_ops), 4, IIC_Br, [], (t2B uncondbrtarget:$dst, pred:$p)>, - Requires<[IsThumb2, IsDarwin]>; + Requires<[IsThumb2, IsIOS]>; } // IT block Modified: llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp?rev=146981&r1=146980&r2=146981&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp Tue Dec 20 12:26:50 2011 @@ -108,13 +108,13 @@ if (isAAPCS_ABI()) stackAlignment = 8; - if (!isTargetDarwin()) + if (!isTargetIOS()) UseMovt = hasV6T2Ops(); else { IsR9Reserved = ReserveR9 | !HasV6Ops; UseMovt = DarwinUseMOVT && hasV6T2Ops(); const Triple &T = getTargetTriple(); - SupportsTailCall = T.getOS() == Triple::IOS && !T.isOSVersionLT(5, 0); + SupportsTailCall = !T.isOSVersionLT(5, 0); } if (!isThumb() || hasThumb2()) Modified: llvm/trunk/lib/Target/ARM/ARMSubtarget.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMSubtarget.h?rev=146981&r1=146980&r2=146981&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMSubtarget.h (original) +++ llvm/trunk/lib/Target/ARM/ARMSubtarget.h Tue Dec 20 12:26:50 2011 @@ -218,6 +218,7 @@ const Triple &getTargetTriple() const { return TargetTriple; } + bool isTargetIOS() const { return TargetTriple.getOS() == Triple::IOS; } bool isTargetDarwin() const { return TargetTriple.isOSDarwin(); } bool isTargetNaCl() const { return TargetTriple.getOS() == Triple::NativeClient; Modified: llvm/trunk/test/CodeGen/ARM/2010-11-29-PrologueBug.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/2010-11-29-PrologueBug.ll?rev=146981&r1=146980&r2=146981&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/ARM/2010-11-29-PrologueBug.ll (original) +++ llvm/trunk/test/CodeGen/ARM/2010-11-29-PrologueBug.ll Tue Dec 20 12:26:50 2011 @@ -1,5 +1,5 @@ -; RUN: llc < %s -mtriple=armv7-apple-darwin | FileCheck %s --check-prefix=ARM -; RUN: llc < %s -mtriple=thumbv7-apple-darwin | FileCheck %s --check-prefix=THUMB2 +; RUN: llc < %s -mtriple=armv7-apple-ios | FileCheck %s --check-prefix=ARM +; RUN: llc < %s -mtriple=thumbv7-apple-ios | FileCheck %s --check-prefix=THUMB2 ; rdar://8690640 define i32* @t(i32* %x) nounwind { Modified: llvm/trunk/test/CodeGen/ARM/2011-06-16-TailCallByVal.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/2011-06-16-TailCallByVal.ll?rev=146981&r1=146980&r2=146981&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/ARM/2011-06-16-TailCallByVal.ll (original) +++ llvm/trunk/test/CodeGen/ARM/2011-06-16-TailCallByVal.ll Tue Dec 20 12:26:50 2011 @@ -1,6 +1,6 @@ ; RUN: llc < %s -arm-tail-calls=1 | FileCheck %s target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:32-f32:32:32-f64:32:32-v64:32:64-v128:32:128-a0:0:32-n32" -target triple = "thumbv7-apple-darwin10" +target triple = "thumbv7-apple-ios" %struct.A = type <{ i16, i16, i32, i16, i16, i32, i16, [8 x %struct.B], [418 x i8], %struct.C }> %struct.B = type <{ i32, i16, i16 }> Modified: llvm/trunk/test/CodeGen/ARM/call-tc.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/call-tc.ll?rev=146981&r1=146980&r2=146981&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/ARM/call-tc.ll (original) +++ llvm/trunk/test/CodeGen/ARM/call-tc.ll Tue Dec 20 12:26:50 2011 @@ -1,6 +1,6 @@ -; RUN: llc < %s -mtriple=armv6-apple-darwin -mattr=+vfp2 -arm-tail-calls | FileCheck %s -check-prefix=CHECKV6 +; RUN: llc < %s -mtriple=armv6-apple-ios -mattr=+vfp2 -arm-tail-calls | FileCheck %s -check-prefix=CHECKV6 ; RUN: llc < %s -mtriple=armv6-linux-gnueabi -relocation-model=pic -mattr=+vfp2 -arm-tail-calls | FileCheck %s -check-prefix=CHECKELF -; RUN: llc < %s -mtriple=thumbv7-apple-darwin -arm-tail-calls | FileCheck %s -check-prefix=CHECKT2D +; RUN: llc < %s -mtriple=thumbv7-apple-ios -arm-tail-calls | FileCheck %s -check-prefix=CHECKT2D ; RUN: llc < %s -mtriple=thumbv7-apple-ios5.0 | FileCheck %s -check-prefix=CHECKT2D ; Enable tailcall optimization for iOS 5.0 Modified: llvm/trunk/test/CodeGen/ARM/debug-info-blocks.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/debug-info-blocks.ll?rev=146981&r1=146980&r2=146981&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/ARM/debug-info-blocks.ll (original) +++ llvm/trunk/test/CodeGen/ARM/debug-info-blocks.ll Tue Dec 20 12:26:50 2011 @@ -2,7 +2,7 @@ ; CHECK: @DEBUG_VALUE: mydata <- [sp+#{{[0-9]+}}]+#0 ; Radar 9331779 target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:32-f32:32:32-f64:32:32-v64:32:64-v128:32:128-a0:0:32-n32" -target triple = "thumbv7-apple-macosx10.7.0" +target triple = "thumbv7-apple-ios" %0 = type opaque %1 = type { [4 x i32] } Modified: llvm/trunk/test/CodeGen/ARM/fast-isel-br-const.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/fast-isel-br-const.ll?rev=146981&r1=146980&r2=146981&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/ARM/fast-isel-br-const.ll (original) +++ llvm/trunk/test/CodeGen/ARM/fast-isel-br-const.ll Tue Dec 20 12:26:50 2011 @@ -1,5 +1,5 @@ -; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-apple-darwin | FileCheck %s --check-prefix=ARM -; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-darwin | FileCheck %s --check-prefix=THUMB +; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-apple-ios | FileCheck %s --check-prefix=ARM +; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-ios | FileCheck %s --check-prefix=THUMB define i32 @t1(i32 %a, i32 %b) nounwind uwtable ssp { entry: Modified: llvm/trunk/test/CodeGen/ARM/fast-isel-call.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/fast-isel-call.ll?rev=146981&r1=146980&r2=146981&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/ARM/fast-isel-call.ll (original) +++ llvm/trunk/test/CodeGen/ARM/fast-isel-call.ll Tue Dec 20 12:26:50 2011 @@ -1,5 +1,5 @@ -; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-apple-darwin | FileCheck %s --check-prefix=ARM -; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-darwin | FileCheck %s --check-prefix=THUMB +; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-apple-ios | FileCheck %s --check-prefix=ARM +; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-ios | FileCheck %s --check-prefix=THUMB define i32 @t0(i1 zeroext %a) nounwind { %1 = zext i1 %a to i32 Modified: llvm/trunk/test/CodeGen/ARM/fast-isel-cmp-imm.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/fast-isel-cmp-imm.ll?rev=146981&r1=146980&r2=146981&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/ARM/fast-isel-cmp-imm.ll (original) +++ llvm/trunk/test/CodeGen/ARM/fast-isel-cmp-imm.ll Tue Dec 20 12:26:50 2011 @@ -1,5 +1,5 @@ -; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-apple-darwin | FileCheck %s --check-prefix=ARM -; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-darwin | FileCheck %s --check-prefix=THUMB +; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-apple-ios | FileCheck %s --check-prefix=ARM +; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-ios | FileCheck %s --check-prefix=THUMB define void @t1a(float %a) uwtable ssp { entry: Modified: llvm/trunk/test/CodeGen/ARM/fast-isel-conversion.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/fast-isel-conversion.ll?rev=146981&r1=146980&r2=146981&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/ARM/fast-isel-conversion.ll (original) +++ llvm/trunk/test/CodeGen/ARM/fast-isel-conversion.ll Tue Dec 20 12:26:50 2011 @@ -1,5 +1,5 @@ -; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-apple-darwin | FileCheck %s --check-prefix=ARM -; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-darwin | FileCheck %s --check-prefix=THUMB +; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-apple-ios | FileCheck %s --check-prefix=ARM +; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-ios | FileCheck %s --check-prefix=THUMB ; Test sitofp Modified: llvm/trunk/test/CodeGen/ARM/fast-isel-deadcode.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/fast-isel-deadcode.ll?rev=146981&r1=146980&r2=146981&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/ARM/fast-isel-deadcode.ll (original) +++ llvm/trunk/test/CodeGen/ARM/fast-isel-deadcode.ll Tue Dec 20 12:26:50 2011 @@ -1,4 +1,4 @@ -; RUN: llc < %s -O0 -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-darwin | FileCheck %s --check-prefix=THUMB +; RUN: llc < %s -O0 -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-ios | FileCheck %s --check-prefix=THUMB ; Target-specific selector can't properly handle the double because it isn't ; being passed via a register, so the materialized arguments become dead code. Modified: llvm/trunk/test/CodeGen/ARM/fast-isel-icmp.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/fast-isel-icmp.ll?rev=146981&r1=146980&r2=146981&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/ARM/fast-isel-icmp.ll (original) +++ llvm/trunk/test/CodeGen/ARM/fast-isel-icmp.ll Tue Dec 20 12:26:50 2011 @@ -1,5 +1,5 @@ -; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-apple-darwin | FileCheck %s --check-prefix=ARM -; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-darwin | FileCheck %s --check-prefix=THUMB +; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-apple-ios | FileCheck %s --check-prefix=ARM +; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-ios | FileCheck %s --check-prefix=THUMB define i32 @icmp_i16_unsigned(i16 %a, i16 %b) nounwind { entry: Modified: llvm/trunk/test/CodeGen/ARM/fast-isel-intrinsic.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/fast-isel-intrinsic.ll?rev=146981&r1=146980&r2=146981&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/ARM/fast-isel-intrinsic.ll (original) +++ llvm/trunk/test/CodeGen/ARM/fast-isel-intrinsic.ll Tue Dec 20 12:26:50 2011 @@ -1,5 +1,5 @@ -; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-apple-darwin | FileCheck %s --check-prefix=ARM -; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-darwin | FileCheck %s --check-prefix=THUMB +; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-apple-ios | FileCheck %s --check-prefix=ARM +; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-ios | FileCheck %s --check-prefix=THUMB @message1 = global [60 x i8] c"The LLVM Compiler Infrastructure\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00", align 1 @temp = common global [60 x i8] zeroinitializer, align 1 Modified: llvm/trunk/test/CodeGen/ARM/fast-isel-ldr-str-thumb-neg-index.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/fast-isel-ldr-str-thumb-neg-index.ll?rev=146981&r1=146980&r2=146981&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/ARM/fast-isel-ldr-str-thumb-neg-index.ll (original) +++ llvm/trunk/test/CodeGen/ARM/fast-isel-ldr-str-thumb-neg-index.ll Tue Dec 20 12:26:50 2011 @@ -1,4 +1,4 @@ -; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-darwin | FileCheck %s --check-prefix=THUMB +; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-ios | FileCheck %s --check-prefix=THUMB define i32 @t1(i32* nocapture %ptr) nounwind readonly { entry: Modified: llvm/trunk/test/CodeGen/ARM/fast-isel-ldrh-strh-arm.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/fast-isel-ldrh-strh-arm.ll?rev=146981&r1=146980&r2=146981&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/ARM/fast-isel-ldrh-strh-arm.ll (original) +++ llvm/trunk/test/CodeGen/ARM/fast-isel-ldrh-strh-arm.ll Tue Dec 20 12:26:50 2011 @@ -1,4 +1,4 @@ -; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-apple-darwin | FileCheck %s --check-prefix=ARM +; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-apple-ios | FileCheck %s --check-prefix=ARM ; rdar://10418009 define zeroext i16 @t1(i16* nocapture %a) nounwind uwtable readonly ssp { Modified: llvm/trunk/test/CodeGen/ARM/fast-isel-mvn.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/fast-isel-mvn.ll?rev=146981&r1=146980&r2=146981&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/ARM/fast-isel-mvn.ll (original) +++ llvm/trunk/test/CodeGen/ARM/fast-isel-mvn.ll Tue Dec 20 12:26:50 2011 @@ -1,5 +1,5 @@ -; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-apple-darwin | FileCheck %s --check-prefix=ARM -; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-darwin | FileCheck %s --check-prefix=THUMB +; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-apple-ios | FileCheck %s --check-prefix=ARM +; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-ios | FileCheck %s --check-prefix=THUMB ; rdar://10412592 ; Note: The Thumb code is being generated by the target-independent selector. @@ -104,4 +104,4 @@ ; THUMB: movt r0, #33023 call void @foo(i32 -2130706433) ret void -} \ No newline at end of file +} Modified: llvm/trunk/test/CodeGen/ARM/fast-isel-ret.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/fast-isel-ret.ll?rev=146981&r1=146980&r2=146981&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/ARM/fast-isel-ret.ll (original) +++ llvm/trunk/test/CodeGen/ARM/fast-isel-ret.ll Tue Dec 20 12:26:50 2011 @@ -1,5 +1,5 @@ -; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-apple-darwin | FileCheck %s -; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-darwin | FileCheck %s +; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-apple-ios | FileCheck %s +; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-ios | FileCheck %s ; Sign-extend of i1 currently not supported by fast-isel ;define signext i1 @ret0(i1 signext %a) nounwind uwtable ssp { Modified: llvm/trunk/test/CodeGen/ARM/fast-isel-select.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/fast-isel-select.ll?rev=146981&r1=146980&r2=146981&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/ARM/fast-isel-select.ll (original) +++ llvm/trunk/test/CodeGen/ARM/fast-isel-select.ll Tue Dec 20 12:26:50 2011 @@ -1,5 +1,5 @@ -; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-apple-darwin | FileCheck %s --check-prefix=ARM -; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-darwin | FileCheck %s --check-prefix=THUMB +; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-apple-ios | FileCheck %s --check-prefix=ARM +; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-ios | FileCheck %s --check-prefix=THUMB define i32 @t1(i1 %c) nounwind readnone { entry: Modified: llvm/trunk/test/CodeGen/ARM/fast-isel.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/fast-isel.ll?rev=146981&r1=146980&r2=146981&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/ARM/fast-isel.ll (original) +++ llvm/trunk/test/CodeGen/ARM/fast-isel.ll Tue Dec 20 12:26:50 2011 @@ -1,5 +1,5 @@ -; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-apple-darwin | FileCheck %s --check-prefix=ARM -; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-darwin | FileCheck %s --check-prefix=THUMB +; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-apple-ios | FileCheck %s --check-prefix=ARM +; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-ios | FileCheck %s --check-prefix=THUMB ; Very basic fast-isel functionality. define i32 @add(i32 %a, i32 %b) nounwind { Modified: llvm/trunk/test/CodeGen/Thumb2/2009-07-21-ISelBug.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb2/2009-07-21-ISelBug.ll?rev=146981&r1=146980&r2=146981&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/Thumb2/2009-07-21-ISelBug.ll (original) +++ llvm/trunk/test/CodeGen/Thumb2/2009-07-21-ISelBug.ll Tue Dec 20 12:26:50 2011 @@ -1,4 +1,4 @@ -; RUN: llc < %s -mtriple=thumbv7-apple-darwin9 -mattr=+vfp2,+thumb2 | FileCheck %s +; RUN: llc < %s -mtriple=thumbv7-apple-ios -mattr=+vfp2,+thumb2 | FileCheck %s ; rdar://7076238 @"\01LC" = external constant [36 x i8], align 1 ; <[36 x i8]*> [#uses=1] From stoklund at 2pi.dk Tue Dec 20 12:44:07 2011 From: stoklund at 2pi.dk (Jakob Stoklund Olesen) Date: Tue, 20 Dec 2011 10:44:07 -0800 Subject: [llvm-commits] [PATCH] Allow SelectionDAGBuilder to reorder loads past stores In-Reply-To: <1324401740.31367.437.camel@sapling> References: <1324316529.31367.96.camel@sapling> <945273C4-D0AA-4CAF-B0ED-C6D96A52FE02@apple.com> <1324325951.31367.178.camel@sapling> <1324355462.31367.287.camel@sapling> <2264DB7F-F14F-4D93-B6C1-79D69B5F2DBF@apple.com> <1324401740.31367.437.camel@sapling> Message-ID: <4B06FCD2-5607-4F5A-989E-C961B6DD6FE4@2pi.dk> On Dec 20, 2011, at 9:22 AM, Hal Finkel wrote: > when I later look at the register map, only XMM0 and XMM1 are ever > assigned to vregs, everything else is spilled. This is wrong. Do you > have any ideas on what could be going wrong or other things I should > examine? Could the register allocator not be accounting correctly for > callee-saved registers when computing live-interval interference > information? There are no callee-saved xmm registers. /jakob From hfinkel at anl.gov Tue Dec 20 12:52:09 2011 From: hfinkel at anl.gov (Hal Finkel) Date: Tue, 20 Dec 2011 12:52:09 -0600 Subject: [llvm-commits] [PATCH] Allow SelectionDAGBuilder to reorder loads past stores In-Reply-To: <4B06FCD2-5607-4F5A-989E-C961B6DD6FE4@2pi.dk> References: <1324316529.31367.96.camel@sapling> <945273C4-D0AA-4CAF-B0ED-C6D96A52FE02@apple.com> <1324325951.31367.178.camel@sapling> <1324355462.31367.287.camel@sapling> <2264DB7F-F14F-4D93-B6C1-79D69B5F2DBF@apple.com> <1324401740.31367.437.camel@sapling> <4B06FCD2-5607-4F5A-989E-C961B6DD6FE4@2pi.dk> Message-ID: <1324407129.31367.481.camel@sapling> On Tue, 2011-12-20 at 10:44 -0800, Jakob Stoklund Olesen wrote: > On Dec 20, 2011, at 9:22 AM, Hal Finkel wrote: > > > when I later look at the register map, only XMM0 and XMM1 are ever > > assigned to vregs, everything else is spilled. This is wrong. Do you > > have any ideas on what could be going wrong or other things I should > > examine? Could the register allocator not be accounting correctly for > > callee-saved registers when computing live-interval interference > > information? > > There are no callee-saved xmm registers. Thanks! I was mixing up the Win64 calling convention with the regular one. That explains things, so, I suppose the right thing to do is to make sure all stores are flushed before any call (which I think it already does), and any intrinsic that will be expanded (which it will not currently do). -Hal > > /jakob > -- Hal Finkel Postdoctoral Appointee Leadership Computing Facility Argonne National Laboratory From mcrosier at apple.com Tue Dec 20 13:06:37 2011 From: mcrosier at apple.com (Chad Rosier) Date: Tue, 20 Dec 2011 11:06:37 -0800 Subject: [llvm-commits] [llvm] r146578 - in /llvm/trunk: lib/Transforms/Scalar/LoopUnswitch.cpp test/Transforms/LoopUnswitch/2011-11-18-SimpleSwitch.ll test/Transforms/LoopUnswitch/2011-11-18-TwoSwitches-Threshold.ll test/Transforms/LoopUnswitch/2011-11-18-TwoSwitches.ll In-Reply-To: <20111214191917.910052A6C12C@llvm.org> References: <20111214191917.910052A6C12C@llvm.org> Message-ID: <01A21900-6703-4740-81EE-EB282C8D02A8@apple.com> Hi Stepan, I noticed this patch caused an ~8% compile-time regression for MultiSource/Benchmarks/Prolangs-C++/shapes/shapes for ARMv7 -O3 -mthumb. If you have a moment would you mind taking a look? The test-suite can be downloaded from the llvm repository (See: http://llvm.org/docs/TestingGuide.html#testsuite). Here are the command line arguments I used to reproduce the regression: /Users/mcrosier/llvm-clean/Release+Asserts/Release+Asserts/bin/clang++ -I/Users/mcrosier/llvm-clean/Release+Asserts/projects/test-suite/MultiSource/Benchmarks/Prolangs-C++/shapes -I/Users/mcrosier/llvm-clean/llvm/projects/test-suite/MultiSource/Benchmarks/Prolangs-C++/shapes -I/Users/mcrosier/llvm-clean/Release+Asserts/projects/test-suite/../../../llvm/projects/test-suite/include -I../../../../include -I/Users/mcrosier/llvm-clean/Release+Asserts/include -I/Users/mcrosier/llvm-clean/llvm/include -D_GNU_SOURCE -D__STDC_LIMIT_MACROS -DNDEBUG -DSMALL_PROBLEM_SIZE -O3 -mthumb -miphoneos-version-min=4.0 -Wl,--no-demangle -ccc-install-dir /Developer/Platforms/iPhoneOS.platform/Developer/usr/bin -arch armv7 -isysroot /Developer/Platforms/iPhoneOS.platform/Developer/SDKs/iPhoneOS6.0.Internal.sdk -c /Users/mcrosier/llvm-clean/llvm/projects/test-suite/MultiSource/Benchmarks/Prolangs-C++/shapes/bjarne.cpp -o Output/bjarne.llvm.o Chad For Apple's record this is being tracked by . On Dec 14, 2011, at 11:19 AM, Stepan Dyatkovskiy wrote: > Author: dyatkovskiy > Date: Wed Dec 14 13:19:17 2011 > New Revision: 146578 > > URL: http://llvm.org/viewvc/llvm-project?rev=146578&view=rev > Log: > Fix for bug #11429: Wrong behaviour for switches. Small improvement for code size heuristics. > > Added: > llvm/trunk/test/Transforms/LoopUnswitch/2011-11-18-SimpleSwitch.ll > llvm/trunk/test/Transforms/LoopUnswitch/2011-11-18-TwoSwitches-Threshold.ll > llvm/trunk/test/Transforms/LoopUnswitch/2011-11-18-TwoSwitches.ll > Modified: > llvm/trunk/lib/Transforms/Scalar/LoopUnswitch.cpp > > Modified: llvm/trunk/lib/Transforms/Scalar/LoopUnswitch.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/LoopUnswitch.cpp?rev=146578&r1=146577&r2=146578&view=diff > ============================================================================== > --- llvm/trunk/lib/Transforms/Scalar/LoopUnswitch.cpp (original) > +++ llvm/trunk/lib/Transforms/Scalar/LoopUnswitch.cpp Wed Dec 14 13:19:17 2011 > @@ -71,7 +71,9 @@ > // LoopProcessWorklist - Used to check if second loop needs processing > // after RewriteLoopBodyWithConditionConstant rewrites first loop. > std::vector LoopProcessWorklist; > - SmallPtrSet UnswitchedVals; > + > + // FIXME: Consider custom class for this. > + std::map > UnswitchedVals; > > bool OptimizeForSize; > bool redoLoop; > @@ -117,7 +119,15 @@ > private: > > virtual void releaseMemory() { > - UnswitchedVals.clear(); > + // We need to forget about all switches in the current loop. > + // FIXME: Do it better than enumerating all blocks of code > + // and see if it is a switch instruction. > + for (Loop::block_iterator I = currentLoop->block_begin(), > + E = currentLoop->block_end(); I != E; ++I) { > + SwitchInst* SI = dyn_cast((*I)->getTerminator()); > + if (SI) > + UnswitchedVals.erase(SI); > + } > } > > /// RemoveLoopFromWorklist - If the specified loop is on the loop worklist, > @@ -128,6 +138,12 @@ > if (I != LoopProcessWorklist.end()) > LoopProcessWorklist.erase(I); > } > + > + /// For new loop switches we clone info about values that was > + /// already unswitched and has redundant successors. > + /// Note, that new loop data is stored inside the VMap. > + void CloneUnswitchedVals(const ValueToValueMapTy& VMap, > + const BasicBlock* SrcBB); > > void initLoopData() { > loopHeader = currentLoop->getHeader(); > @@ -255,13 +271,25 @@ > } else if (SwitchInst *SI = dyn_cast(TI)) { > Value *LoopCond = FindLIVLoopCondition(SI->getCondition(), > currentLoop, Changed); > - if (LoopCond && SI->getNumCases() > 1) { > + unsigned NumCases = SI->getNumCases(); > + if (LoopCond && NumCases > 1) { > // Find a value to unswitch on: > // FIXME: this should chose the most expensive case! > // FIXME: scan for a case with a non-critical edge? > - Constant *UnswitchVal = SI->getCaseValue(1); > + Constant *UnswitchVal = NULL; > + > // Do not process same value again and again. > - if (!UnswitchedVals.insert(UnswitchVal)) > + // At this point we have some cases already unswitched and > + // some not yet unswitched. Let's find the first not yet unswitched one. > + for (unsigned i = 1; i < NumCases; ++i) { > + Constant* UnswitchValCandidate = SI->getCaseValue(i); > + if (!UnswitchedVals[SI].count(UnswitchValCandidate)) { > + UnswitchVal = UnswitchValCandidate; > + break; > + } > + } > + > + if (!UnswitchVal) > continue; > > if (UnswitchIfProfitable(LoopCond, UnswitchVal)) { > @@ -287,6 +315,23 @@ > return Changed; > } > > +/// For new loop switches we clone info about values that was > +/// already unswitched and has redundant successors. > +/// Not that new loop data is stored inside the VMap. > +void LoopUnswitch::CloneUnswitchedVals(const ValueToValueMapTy& VMap, > + const BasicBlock* SrcBB) { > + > + const SwitchInst* SI = dyn_cast(SrcBB->getTerminator()); > + if (SI && UnswitchedVals.count(SI)) { > + // Don't clone a totally simplified switch. > + if (isa(SI->getCondition())) > + return; > + Value* I = VMap.lookup(SI); > + assert(I && "All instructions that are in SrcBB must be in VMap."); > + UnswitchedVals[cast(I)] = UnswitchedVals[SI]; > + } > +} > + > /// isTrivialLoopExitBlock - Check to see if all paths from BB exit the > /// loop with no side effects (including infinite loops). > /// > @@ -378,14 +423,25 @@ > // Check to see if a successor of the switch is guaranteed to go to the > // latch block or exit through a one exit block without having any > // side-effects. If so, determine the value of Cond that causes it to do > - // this. Note that we can't trivially unswitch on the default case. > - for (unsigned i = 1, e = SI->getNumSuccessors(); i != e; ++i) > - if ((LoopExitBB = isTrivialLoopExitBlock(currentLoop, > + // this. > + // Note that we can't trivially unswitch on the default case or > + // on already unswitched cases. > + for (unsigned i = 1, e = SI->getNumSuccessors(); i != e; ++i) { > + BasicBlock* LoopExitCandidate; > + if ((LoopExitCandidate = isTrivialLoopExitBlock(currentLoop, > SI->getSuccessor(i)))) { > // Okay, we found a trivial case, remember the value that is trivial. > - if (Val) *Val = SI->getCaseValue(i); > + ConstantInt* CaseVal = SI->getCaseValue(i); > + > + // Check that it was not unswitched before, since already unswitched > + // trivial vals are looks trivial too. > + if (UnswitchedVals[SI].count(CaseVal)) > + continue; > + LoopExitBB = LoopExitCandidate; > + if (Val) *Val = CaseVal; > break; > } > + } > } > > // If we didn't find a single unique LoopExit block, or if the loop exit block > @@ -447,8 +503,14 @@ > // expansion, and the number of basic blocks, to avoid loops with > // large numbers of branches which cause loop unswitching to go crazy. > // This is a very ad-hoc heuristic. > - if (Metrics.NumInsts > Threshold || > - Metrics.NumBlocks * 5 > Threshold || > + > + unsigned NumUnswitched = > + (NumSwitches + NumBranches) + 1 /*take in account current iteration*/; > + > + unsigned NumInsts = Metrics.NumInsts * NumUnswitched; > + unsigned NumBlocks = Metrics.NumBlocks * NumUnswitched; > + > + if (NumInsts > Threshold || NumBlocks * 5 > Threshold || > Metrics.containsIndirectBr || Metrics.isRecursive) { > DEBUG(dbgs() << "NOT unswitching loop %" > << currentLoop->getHeader()->getName() << ", cost too high: " > @@ -620,6 +682,12 @@ > ValueToValueMapTy VMap; > for (unsigned i = 0, e = LoopBlocks.size(); i != e; ++i) { > BasicBlock *NewBB = CloneBasicBlock(LoopBlocks[i], VMap, ".us", F); > + > + // Inherit simplified switches info for NewBB > + // We needn't pass NewBB since its instructions are already contained > + // inside the VMap. > + CloneUnswitchedVals(VMap, LoopBlocks[i]); > + > NewBlocks.push_back(NewBB); > VMap[LoopBlocks[i]] = NewBB; // Keep the BB mapping. > LPM->cloneBasicBlockSimpleAnalysis(LoopBlocks[i], NewBB, L); > @@ -945,6 +1013,9 @@ > BasicBlock *Switch = SI->getParent(); > BasicBlock *SISucc = SI->getSuccessor(DeadCase); > BasicBlock *Latch = L->getLoopLatch(); > + > + UnswitchedVals[SI].insert(Val); > + > if (!SI->findCaseDest(SISucc)) continue; // Edge is critical. > // If the DeadCase successor dominates the loop latch, then the > // transformation isn't safe since it will delete the sole predecessor edge > > Added: llvm/trunk/test/Transforms/LoopUnswitch/2011-11-18-SimpleSwitch.ll > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/LoopUnswitch/2011-11-18-SimpleSwitch.ll?rev=146578&view=auto > ============================================================================== > --- llvm/trunk/test/Transforms/LoopUnswitch/2011-11-18-SimpleSwitch.ll (added) > +++ llvm/trunk/test/Transforms/LoopUnswitch/2011-11-18-SimpleSwitch.ll Wed Dec 14 13:19:17 2011 > @@ -0,0 +1,91 @@ > +; RUN: opt -loop-unswitch -disable-output -stats -info-output-file - < %s | FileCheck --check-prefix=STATS %s > +; RUN: opt -S -loop-unswitch -verify-loop-info -verify-dom-info %s | FileCheck %s > + > +; STATS: 1 loop-simplify - Number of pre-header or exit blocks inserted > +; STATS: 2 loop-unswitch - Number of switches unswitched > + > +; CHECK: %1 = icmp eq i32 %c, 1 > +; CHECK-NEXT: br i1 %1, label %.split.us, label %..split_crit_edge > + > +; CHECK: ..split_crit_edge: ; preds = %0 > +; CHECK-NEXT: br label %.split > + > +; CHECK: .split.us: ; preds = %0 > +; CHECK-NEXT: br label %loop_begin.us > + > +; CHECK: loop_begin.us: ; preds = %loop_begin.backedge.us, %.split.us > +; CHECK-NEXT: %var_val.us = load i32* %var > +; CHECK-NEXT: switch i32 1, label %default.us-lcssa.us [ > +; CHECK-NEXT: i32 1, label %inc.us > + > +; CHECK: inc.us: ; preds = %loop_begin.us > +; CHECK-NEXT: call void @incf() noreturn nounwind > +; CHECK-NEXT: br label %loop_begin.backedge.us > + > +; CHECK: .split: ; preds = %..split_crit_edge > +; CHECK-NEXT: %2 = icmp eq i32 %c, 2 > +; CHECK-NEXT: br i1 %2, label %.split.split.us, label %.split..split.split_crit_edge > + > +; CHECK: .split..split.split_crit_edge: ; preds = %.split > +; CHECK-NEXT: br label %.split.split > + > +; CHECK: .split.split.us: ; preds = %.split > +; CHECK-NEXT: br label %loop_begin.us1 > + > +; CHECK: loop_begin.us1: ; preds = %loop_begin.backedge.us5, %.split.split.us > +; CHECK-NEXT: %var_val.us2 = load i32* %var > +; CHECK-NEXT: switch i32 2, label %default.us-lcssa.us-lcssa.us [ > +; CHECK-NEXT: i32 1, label %inc.us3 > +; CHECK-NEXT: i32 2, label %dec.us4 > +; CHECK-NEXT: ] > + > +; CHECK: dec.us4: ; preds = %loop_begin.us1 > +; CHECK-NEXT: call void @decf() noreturn nounwind > +; CHECK-NEXT: br label %loop_begin.backedge.us5 > + > +; CHECK: .split.split: ; preds = %.split..split.split_crit_edge > +; CHECK-NEXT: br label %loop_begin > + > +; CHECK: loop_begin: ; preds = %loop_begin.backedge, %.split.split > +; CHECK-NEXT: %var_val = load i32* %var > +; CHECK-NEXT: switch i32 %c, label %default.us-lcssa.us-lcssa [ > +; CHECK-NEXT: i32 1, label %inc > +; CHECK-NEXT: i32 2, label %dec > +; CHECK-NEXT: ] > + > +; CHECK: inc: ; preds = %loop_begin > +; CHECK-NEXT: br i1 true, label %us-unreachable.us-lcssa, label %inc.split > + > +; CHECK: dec: ; preds = %loop_begin > +; CHECK-NEXT: br i1 true, label %us-unreachable6, label %dec.split > + > +define i32 @test(i32* %var) { > + %mem = alloca i32 > + store i32 2, i32* %mem > + %c = load i32* %mem > + > + br label %loop_begin > + > +loop_begin: > + > + %var_val = load i32* %var > + > + switch i32 %c, label %default [ > + i32 1, label %inc > + i32 2, label %dec > + ] > + > +inc: > + call void @incf() noreturn nounwind > + br label %loop_begin > +dec: > + call void @decf() noreturn nounwind > + br label %loop_begin > +default: > + br label %loop_exit > +loop_exit: > + ret i32 0 > +} > + > +declare void @incf() noreturn > +declare void @decf() noreturn > > Added: llvm/trunk/test/Transforms/LoopUnswitch/2011-11-18-TwoSwitches-Threshold.ll > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/LoopUnswitch/2011-11-18-TwoSwitches-Threshold.ll?rev=146578&view=auto > ============================================================================== > --- llvm/trunk/test/Transforms/LoopUnswitch/2011-11-18-TwoSwitches-Threshold.ll (added) > +++ llvm/trunk/test/Transforms/LoopUnswitch/2011-11-18-TwoSwitches-Threshold.ll Wed Dec 14 13:19:17 2011 > @@ -0,0 +1,84 @@ > +; RUN: opt -loop-unswitch -loop-unswitch-threshold 30 -disable-output -stats -info-output-file - < %s | FileCheck --check-prefix=STATS %s > +; RUN: opt -S -loop-unswitch -loop-unswitch-threshold 30 -verify-loop-info -verify-dom-info %s | FileCheck %s > + > +; STATS: 1 loop-simplify - Number of pre-header or exit blocks inserted > +; STATS: 1 loop-unswitch - Number of switches unswitched > + > +; ModuleID = '../llvm/test/Transforms/LoopUnswitch/2011-11-18-TwoSwitches.ll' > + > +; CHECK: %1 = icmp eq i32 %c, 1 > +; CHECK-NEXT: br i1 %1, label %.split.us, label %..split_crit_edge > + > +; CHECK: ..split_crit_edge: ; preds = %0 > +; CHECK-NEXT: br label %.split > + > +; CHECK: .split.us: ; preds = %0 > +; CHECK-NEXT: br label %loop_begin.us > + > +; CHECK: loop_begin.us: ; preds = %loop_begin.backedge.us, %.split.us > +; CHECK: switch i32 1, label %second_switch.us [ > +; CHECK-NEXT: i32 1, label %inc.us > + > +; CHECK: inc.us: ; preds = %second_switch.us, %loop_begin.us > +; CHECK-NEXT: call void @incf() noreturn nounwind > +; CHECK-NEXT: br label %loop_begin.backedge.us > + > +; CHECK: second_switch.us: ; preds = %loop_begin.us > +; CHECK-NEXT: switch i32 %d, label %default.us [ > +; CHECK-NEXT: i32 1, label %inc.us > +; CHECK-NEXT: ] > + > +; CHECK: .split: ; preds = %..split_crit_edge > +; CHECK-NEXT: br label %loop_begin > + > +; CHECK: loop_begin: ; preds = %loop_begin.backedge, %.split > +; CHECK: switch i32 %c, label %second_switch [ > +; CHECK-NEXT: i32 1, label %loop_begin.inc_crit_edge > +; CHECK-NEXT: ] > + > +; CHECK: loop_begin.inc_crit_edge: ; preds = %loop_begin > +; CHECK-NEXT: br i1 true, label %us-unreachable, label %inc > + > +; CHECK: second_switch: ; preds = %loop_begin > +; CHECK-NEXT: switch i32 %d, label %default [ > +; CHECK-NEXT: i32 1, label %inc > +; CHECK-NEXT: ] > + > +; CHECK: inc: ; preds = %loop_begin.inc_crit_edge, %second_switch > +; CHECK-NEXT: call void @incf() noreturn nounwind > +; CHECK-NEXT: br label %loop_begin.backedge > + > +define i32 @test(i32* %var) { > + %mem = alloca i32 > + store i32 2, i32* %mem > + %c = load i32* %mem > + %d = load i32* %mem > + > + br label %loop_begin > + > +loop_begin: > + > + %var_val = load i32* %var > + > + switch i32 %c, label %second_switch [ > + i32 1, label %inc > + ] > + > +second_switch: > + switch i32 %d, label %default [ > + i32 1, label %inc > + ] > + > +inc: > + call void @incf() noreturn nounwind > + br label %loop_begin > + > +default: > + br label %loop_begin > + > +loop_exit: > + ret i32 0 > +} > + > +declare void @incf() noreturn > +declare void @decf() noreturn > > Added: llvm/trunk/test/Transforms/LoopUnswitch/2011-11-18-TwoSwitches.ll > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/LoopUnswitch/2011-11-18-TwoSwitches.ll?rev=146578&view=auto > ============================================================================== > --- llvm/trunk/test/Transforms/LoopUnswitch/2011-11-18-TwoSwitches.ll (added) > +++ llvm/trunk/test/Transforms/LoopUnswitch/2011-11-18-TwoSwitches.ll Wed Dec 14 13:19:17 2011 > @@ -0,0 +1,138 @@ > +; RUN: opt -loop-unswitch -loop-unswitch-threshold 1000 -disable-output -stats -info-output-file - < %s | FileCheck --check-prefix=STATS %s > +; RUN: opt -S -loop-unswitch -loop-unswitch-threshold 1000 -verify-loop-info -verify-dom-info %s | FileCheck %s > + > +; STATS: 1 loop-simplify - Number of pre-header or exit blocks inserted > +; STATS: 3 loop-unswitch - Number of switches unswitched > + > +; CHECK: %1 = icmp eq i32 %c, 1 > +; CHECK-NEXT: br i1 %1, label %.split.us, label %..split_crit_edge > + > +; CHECK: ..split_crit_edge: ; preds = %0 > +; CHECK-NEXT: br label %.split > + > +; CHECK: .split.us: ; preds = %0 > +; CHECK-NEXT: %2 = icmp eq i32 %d, 1 > +; CHECK-NEXT: br i1 %2, label %.split.us.split.us, label %.split.us..split.us.split_crit_edge > + > +; CHECK: .split.us..split.us.split_crit_edge: ; preds = %.split.us > +; CHECK-NEXT: br label %.split.us.split > + > +; CHECK: .split.us.split.us: ; preds = %.split.us > +; CHECK-NEXT: br label %loop_begin.us.us > + > +; CHECK: loop_begin.us.us: ; preds = %loop_begin.backedge.us.us, %.split.us.split.us > +; CHECK-NEXT: %var_val.us.us = load i32* %var > +; CHECK-NEXT: switch i32 1, label %second_switch.us.us [ > +; CHECK-NEXT: i32 1, label %inc.us.us > + > +; CHECK: inc.us.us: ; preds = %second_switch.us.us, %loop_begin.us.us > +; CHECK-NEXT: call void @incf() noreturn nounwind > +; CHECK-NEXT: br label %loop_begin.backedge.us.us > + > +; CHECK: second_switch.us.us: ; preds = %loop_begin.us.us > +; CHECK-NEXT: switch i32 1, label %default.us.us [ > +; CHECK-NEXT: i32 1, label %inc.us.us > + > +; CHECK: .split.us.split: ; preds = %.split.us..split.us.split_crit_edge > +; CHECK-NEXT: br label %loop_begin.us > + > +; CHECK: loop_begin.us: ; preds = %loop_begin.backedge.us, %.split.us.split > +; CHECK-NEXT: %var_val.us = load i32* %var > +; CHECK-NEXT: switch i32 1, label %second_switch.us [ > +; CHECK-NEXT: i32 1, label %inc.us > + > +; CHECK: inc.us: ; preds = %second_switch.us.inc.us_crit_edge, %loop_begin.us > +; CHECK-NEXT: call void @incf() noreturn nounwind > +; CHECK-NEXT: br label %loop_begin.backedge.us > + > +; CHECK: second_switch.us: ; preds = %loop_begin.us > +; CHECK-NEXT: switch i32 %d, label %default.us [ > +; CHECK-NEXT: i32 1, label %second_switch.us.inc.us_crit_edge > +; CHECK-NEXT: ] > + > +; CHECK: second_switch.us.inc.us_crit_edge: ; preds = %second_switch.us > +; CHECK-NEXT: br i1 true, label %us-unreachable8, label %inc.us > + > +; CHECK: .split: ; preds = %..split_crit_edge > +; CHECK-NEXT: %3 = icmp eq i32 %d, 1 > +; CHECK-NEXT: br i1 %3, label %.split.split.us, label %.split..split.split_crit_edge > + > +; CHECK: .split..split.split_crit_edge: ; preds = %.split > +; CHECK-NEXT: br label %.split.split > + > +; CHECK: .split.split.us: ; preds = %.split > +; CHECK-NEXT: br label %loop_begin.us1 > + > +; CHECK: loop_begin.us1: ; preds = %loop_begin.backedge.us6, %.split.split.us > +; CHECK-NEXT: %var_val.us2 = load i32* %var > +; CHECK-NEXT: switch i32 %c, label %second_switch.us4 [ > +; CHECK-NEXT: i32 1, label %loop_begin.inc_crit_edge.us > +; CHECK-NEXT: ] > + > +; CHECK: inc.us3: ; preds = %loop_begin.inc_crit_edge.us, %second_switch.us4 > +; CHECK-NEXT: call void @incf() noreturn nounwind > +; CHECK-NEXT: br label %loop_begin.backedge.us6 > + > +; CHECK: second_switch.us4: ; preds = %loop_begin.us1 > +; CHECK-NEXT: switch i32 1, label %default.us5 [ > +; CHECK-NEXT: i32 1, label %inc.us3 > +; CHECK-NEXT: ] > + > +; CHECK: loop_begin.inc_crit_edge.us: ; preds = %loop_begin.us1 > +; CHECK-NEXT: br i1 true, label %us-unreachable.us-lcssa.us, label %inc.us3 > + > +; CHECK: .split.split: ; preds = %.split..split.split_crit_edge > +; CHECK-NEXT: br label %loop_begin > + > +; CHECK: loop_begin: ; preds = %loop_begin.backedge, %.split.split > +; CHECK-NEXT: %var_val = load i32* %var > +; CHECK-NEXT: switch i32 %c, label %second_switch [ > +; CHECK-NEXT: i32 1, label %loop_begin.inc_crit_edge > +; CHECK-NEXT: ] > + > +; CHECK: loop_begin.inc_crit_edge: ; preds = %loop_begin > +; CHECK-NEXT: br i1 true, label %us-unreachable.us-lcssa, label %inc > + > +; CHECK: second_switch: ; preds = %loop_begin > +; CHECK-NEXT: switch i32 %d, label %default [ > +; CHECK-NEXT: i32 1, label %second_switch.inc_crit_edge > +; CHECK-NEXT: ] > + > +; CHECK: second_switch.inc_crit_edge: ; preds = %second_switch > +; CHECK-NEXT: br i1 true, label %us-unreachable7, label %inc > + > + > +define i32 @test(i32* %var) { > + %mem = alloca i32 > + store i32 2, i32* %mem > + %c = load i32* %mem > + %d = load i32* %mem > + > + br label %loop_begin > + > +loop_begin: > + > + %var_val = load i32* %var > + > + switch i32 %c, label %second_switch [ > + i32 1, label %inc > + ] > + > +second_switch: > + switch i32 %d, label %default [ > + i32 1, label %inc > + ] > + > +inc: > + call void @incf() noreturn nounwind > + br label %loop_begin > + > +default: > + br label %loop_begin > + > +loop_exit: > + ret i32 0 > +} > + > +declare void @incf() noreturn > +declare void @decf() noreturn > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From grosbach at apple.com Tue Dec 20 13:07:21 2011 From: grosbach at apple.com (Jim Grosbach) Date: Tue, 20 Dec 2011 11:07:21 -0800 Subject: [llvm-commits] [PATCH] MC ARM Thumb: fix incorrect relocation generation (PR11214) In-Reply-To: <000001ccbf1d$618f7490$24ae5db0$%beyls@arm.com> References: <000001ccbf1d$618f7490$24ae5db0$%beyls@arm.com> Message-ID: <57817466-3086-4652-85E2-4959AF23D81B@apple.com> Someone with ELF knowledge should look at this. I'm a bit nervous about removing the conditional as it seems to imply that there's an different relocation that should be generated depending on the variant kind. -Jim On Dec 20, 2011, at 5:43 AM, Kristof Beyls wrote: > Hi, > > Please find a patch for fixing incorrect generation of relocation > information on Thumb function calls. > This should fix quite a few incorrect code generation problems in Thumb mode > when using the integrated assembler. > I believe this fixes PR11214 > (http://www.llvm.org/bugs/show_bug.cgi?id=11214). > > Is this OK? > > Thanks, > > Kristof > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From James.Molloy at arm.com Tue Dec 20 13:21:56 2011 From: James.Molloy at arm.com (James Molloy) Date: Tue, 20 Dec 2011 19:21:56 +0000 Subject: [llvm-commits] [PATCH] MC ARM Thumb: fix incorrect relocation generation (PR11214) In-Reply-To: <57817466-3086-4652-85E2-4959AF23D81B@apple.com> References: <000001ccbf1d$618f7490$24ae5db0$%beyls@arm.com>, <57817466-3086-4652-85E2-4959AF23D81B@apple.com> Message-ID: Yeah, I was confused about that too. I couldn't comprehend why that conditional was even there in the first place - an R_ARM_NONE relocation is *never* required for a call (it's a special no-op reloc). The only thing I could think of is that someone wanted to fix the relocation given to PLT entries and decided to keep the a broken behaviour for the default case, perhaps they had no knowledge about it. ________________________________________ From: llvm-commits-bounces at cs.uiuc.edu [llvm-commits-bounces at cs.uiuc.edu] On Behalf Of Jim Grosbach [grosbach at apple.com] Sent: 20 December 2011 19:07 To: Kristof Beyls Cc: llvm-commits at cs.uiuc.edu Subject: Re: [llvm-commits] [PATCH] MC ARM Thumb: fix incorrect relocation generation (PR11214) Someone with ELF knowledge should look at this. I'm a bit nervous about removing the conditional as it seems to imply that there's an different relocation that should be generated depending on the variant kind. -Jim On Dec 20, 2011, at 5:43 AM, Kristof Beyls wrote: > Hi, > > Please find a patch for fixing incorrect generation of relocation > information on Thumb function calls. > This should fix quite a few incorrect code generation problems in Thumb mode > when using the integrated assembler. > I believe this fixes PR11214 > (http://www.llvm.org/bugs/show_bug.cgi?id=11214). > > Is this OK? > > Thanks, > > Kristof > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits _______________________________________________ llvm-commits mailing list llvm-commits at cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits -- IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you. From grosbach at apple.com Tue Dec 20 13:21:27 2011 From: grosbach at apple.com (Jim Grosbach) Date: Tue, 20 Dec 2011 19:21:27 -0000 Subject: [llvm-commits] [llvm] r146983 - in /llvm/trunk: lib/Target/ARM/ARMInstrNEON.td lib/Target/ARM/AsmParser/ARMAsmParser.cpp test/MC/ARM/neon-vld-encoding.s Message-ID: <20111220192127.C72E72A6C12C@llvm.org> Author: grosbach Date: Tue Dec 20 13:21:26 2011 New Revision: 146983 URL: http://llvm.org/viewvc/llvm-project?rev=146983&view=rev Log: ARM assembly parsing and encoding for VLD2 single-element, double spaced. Modified: llvm/trunk/lib/Target/ARM/ARMInstrNEON.td llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp llvm/trunk/test/MC/ARM/neon-vld-encoding.s Modified: llvm/trunk/lib/Target/ARM/ARMInstrNEON.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrNEON.td?rev=146983&r1=146982&r2=146983&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrNEON.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrNEON.td Tue Dec 20 13:21:26 2011 @@ -174,7 +174,7 @@ let ParserMatchClass = VecListOneDWordIndexAsmOperand; let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx); } -// Register list of two D registers, with byte lane subscripting. +// Register list of two D registers with byte lane subscripting. def VecListTwoDByteIndexAsmOperand : AsmOperandClass { let Name = "VecListTwoDByteIndexed"; let ParserMethod = "parseVectorList"; @@ -204,6 +204,26 @@ let ParserMatchClass = VecListTwoDWordIndexAsmOperand; let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx); } +// Register list of two Q registers with half-word lane subscripting. +def VecListTwoQHWordIndexAsmOperand : AsmOperandClass { + let Name = "VecListTwoQHWordIndexed"; + let ParserMethod = "parseVectorList"; + let RenderMethod = "addVecListIndexedOperands"; +} +def VecListTwoQHWordIndexed : Operand { + let ParserMatchClass = VecListTwoQHWordIndexAsmOperand; + let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx); +} +// ...with word lane subscripting. +def VecListTwoQWordIndexAsmOperand : AsmOperandClass { + let Name = "VecListTwoQWordIndexed"; + let ParserMethod = "parseVectorList"; + let RenderMethod = "addVecListIndexedOperands"; +} +def VecListTwoQWordIndexed : Operand { + let ParserMatchClass = VecListTwoQWordIndexAsmOperand; + let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx); +} //===----------------------------------------------------------------------===// // NEON-specific DAG Nodes. @@ -5735,6 +5755,10 @@ (ins VecListTwoDHWordIndexed:$list, addrmode6:$addr, pred:$p)>; defm VLD2LNdAsm : NEONDT32AsmPseudoInst<"vld2${p}", "$list, $addr", (ins VecListTwoDWordIndexed:$list, addrmode6:$addr, pred:$p)>; +defm VLD2LNqAsm : NEONDT16AsmPseudoInst<"vld2${p}", "$list, $addr", + (ins VecListTwoQHWordIndexed:$list, addrmode6:$addr, pred:$p)>; +defm VLD2LNqAsm : NEONDT32AsmPseudoInst<"vld2${p}", "$list, $addr", + (ins VecListTwoQWordIndexed:$list, addrmode6:$addr, pred:$p)>; defm VLD2LNdWB_fixed_Asm : NEONDT8AsmPseudoInst<"vld2${p}", "$list, $addr!", (ins VecListTwoDByteIndexed:$list, addrmode6:$addr, pred:$p)>; @@ -5742,6 +5766,10 @@ (ins VecListTwoDHWordIndexed:$list, addrmode6:$addr, pred:$p)>; defm VLD2LNdWB_fixed_Asm : NEONDT32AsmPseudoInst<"vld2${p}", "$list, $addr!", (ins VecListTwoDWordIndexed:$list, addrmode6:$addr, pred:$p)>; +defm VLD2LNqWB_fixed_Asm : NEONDT16AsmPseudoInst<"vld2${p}", "$list, $addr!", + (ins VecListTwoQHWordIndexed:$list, addrmode6:$addr, pred:$p)>; +defm VLD2LNqWB_fixed_Asm : NEONDT32AsmPseudoInst<"vld2${p}", "$list, $addr!", + (ins VecListTwoQWordIndexed:$list, addrmode6:$addr, pred:$p)>; defm VLD2LNdWB_register_Asm : NEONDT8AsmPseudoInst<"vld2${p}", "$list, $addr, $Rm", (ins VecListTwoDByteIndexed:$list, addrmode6:$addr, @@ -5754,6 +5782,14 @@ NEONDT32AsmPseudoInst<"vld2${p}", "$list, $addr, $Rm", (ins VecListTwoDWordIndexed:$list, addrmode6:$addr, rGPR:$Rm, pred:$p)>; +defm VLD2LNqWB_register_Asm : + NEONDT16AsmPseudoInst<"vld2${p}", "$list, $addr, $Rm", + (ins VecListTwoQHWordIndexed:$list, addrmode6:$addr, + rGPR:$Rm, pred:$p)>; +defm VLD2LNqWB_register_Asm : + NEONDT32AsmPseudoInst<"vld2${p}", "$list, $addr, $Rm", + (ins VecListTwoQWordIndexed:$list, addrmode6:$addr, + rGPR:$Rm, pred:$p)>; // VST2 single-lane pseudo-instructions. These need special handling for Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp?rev=146983&r1=146982&r2=146983&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp (original) +++ llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Tue Dec 20 13:21:26 2011 @@ -1128,33 +1128,49 @@ return VectorList.Count == 2; } + bool isSingleSpacedVectorIndexed() const { + return Kind == k_VectorListIndexed && !VectorList.isDoubleSpaced; + } + bool isDoubleSpacedVectorIndexed() const { + return Kind == k_VectorListIndexed && VectorList.isDoubleSpaced; + } bool isVecListOneDByteIndexed() const { - if (Kind != k_VectorListIndexed) return false; + if (!isSingleSpacedVectorIndexed()) return false; return VectorList.Count == 1 && VectorList.LaneIndex <= 7; } bool isVecListOneDHWordIndexed() const { - if (Kind != k_VectorListIndexed) return false; + if (!isSingleSpacedVectorIndexed()) return false; return VectorList.Count == 1 && VectorList.LaneIndex <= 3; } bool isVecListOneDWordIndexed() const { - if (Kind != k_VectorListIndexed) return false; + if (!isSingleSpacedVectorIndexed()) return false; return VectorList.Count == 1 && VectorList.LaneIndex <= 1; } bool isVecListTwoDByteIndexed() const { - if (Kind != k_VectorListIndexed) return false; + if (!isSingleSpacedVectorIndexed()) return false; return VectorList.Count == 2 && VectorList.LaneIndex <= 7; } bool isVecListTwoDHWordIndexed() const { - if (Kind != k_VectorListIndexed) return false; + if (!isSingleSpacedVectorIndexed()) return false; + return VectorList.Count == 2 && VectorList.LaneIndex <= 3; + } + + bool isVecListTwoQWordIndexed() const { + if (!isDoubleSpacedVectorIndexed()) return false; + return VectorList.Count == 2 && VectorList.LaneIndex <= 1; + } + + bool isVecListTwoQHWordIndexed() const { + if (!isDoubleSpacedVectorIndexed()) return false; return VectorList.Count == 2 && VectorList.LaneIndex <= 3; } bool isVecListTwoDWordIndexed() const { - if (Kind != k_VectorListIndexed) return false; + if (!isSingleSpacedVectorIndexed()) return false; return VectorList.Count == 2 && VectorList.LaneIndex <= 1; } @@ -2035,11 +2051,14 @@ } static ARMOperand *CreateVectorListIndexed(unsigned RegNum, unsigned Count, - unsigned Index, SMLoc S, SMLoc E) { + unsigned Index, + bool isDoubleSpaced, + SMLoc S, SMLoc E) { ARMOperand *Op = new ARMOperand(k_VectorListIndexed); Op->VectorList.RegNum = RegNum; Op->VectorList.Count = Count; Op->VectorList.LaneIndex = Index; + Op->VectorList.isDoubleSpaced = isDoubleSpaced; Op->StartLoc = S; Op->EndLoc = E; return Op; @@ -2849,7 +2868,8 @@ break; case IndexedLane: Operands.push_back(ARMOperand::CreateVectorListIndexed(Reg, 1, - LaneIndex, S,E)); + LaneIndex, + false, S, E)); break; } return MatchOperand_Success; @@ -2872,7 +2892,8 @@ break; case IndexedLane: Operands.push_back(ARMOperand::CreateVectorListIndexed(Reg, 2, - LaneIndex, S,E)); + LaneIndex, + false, S, E)); break; } return MatchOperand_Success; @@ -3020,11 +3041,6 @@ Error(EndLoc, "mismatched lane index in register list"); return MatchOperand_ParseFail; } - if (Spacing == 2 && LaneKind != NoLanes) { - Error(EndLoc, - "lane index specfier invalid in double spaced register list"); - return MatchOperand_ParseFail; - } } SMLoc E = Parser.getTok().getLoc(); @@ -3047,7 +3063,9 @@ break; case IndexedLane: Operands.push_back(ARMOperand::CreateVectorListIndexed(FirstReg, Count, - LaneIndex, S, E)); + LaneIndex, + (Spacing == 2), + S, E)); break; } return MatchOperand_Success; @@ -5181,84 +5199,132 @@ } } -static unsigned getRealVLDLNOpcode(unsigned Opc) { +static unsigned getRealVLDLNOpcode(unsigned Opc, unsigned &Spacing) { switch(Opc) { default: assert(0 && "unexpected opcode!"); // VLD1LN case ARM::VLD1LNdWB_fixed_Asm_8: case ARM::VLD1LNdWB_fixed_Asm_P8: case ARM::VLD1LNdWB_fixed_Asm_I8: case ARM::VLD1LNdWB_fixed_Asm_S8: case ARM::VLD1LNdWB_fixed_Asm_U8: + Spacing = 1; return ARM::VLD1LNd8_UPD; case ARM::VLD1LNdWB_fixed_Asm_16: case ARM::VLD1LNdWB_fixed_Asm_P16: case ARM::VLD1LNdWB_fixed_Asm_I16: case ARM::VLD1LNdWB_fixed_Asm_S16: case ARM::VLD1LNdWB_fixed_Asm_U16: + Spacing = 1; return ARM::VLD1LNd16_UPD; case ARM::VLD1LNdWB_fixed_Asm_32: case ARM::VLD1LNdWB_fixed_Asm_F: case ARM::VLD1LNdWB_fixed_Asm_F32: case ARM::VLD1LNdWB_fixed_Asm_I32: case ARM::VLD1LNdWB_fixed_Asm_S32: case ARM::VLD1LNdWB_fixed_Asm_U32: + Spacing = 1; return ARM::VLD1LNd32_UPD; case ARM::VLD1LNdWB_register_Asm_8: case ARM::VLD1LNdWB_register_Asm_P8: case ARM::VLD1LNdWB_register_Asm_I8: case ARM::VLD1LNdWB_register_Asm_S8: case ARM::VLD1LNdWB_register_Asm_U8: + Spacing = 1; return ARM::VLD1LNd8_UPD; case ARM::VLD1LNdWB_register_Asm_16: case ARM::VLD1LNdWB_register_Asm_P16: case ARM::VLD1LNdWB_register_Asm_I16: case ARM::VLD1LNdWB_register_Asm_S16: case ARM::VLD1LNdWB_register_Asm_U16: + Spacing = 1; return ARM::VLD1LNd16_UPD; case ARM::VLD1LNdWB_register_Asm_32: case ARM::VLD1LNdWB_register_Asm_F: case ARM::VLD1LNdWB_register_Asm_F32: case ARM::VLD1LNdWB_register_Asm_I32: case ARM::VLD1LNdWB_register_Asm_S32: case ARM::VLD1LNdWB_register_Asm_U32: + Spacing = 1; return ARM::VLD1LNd32_UPD; case ARM::VLD1LNdAsm_8: case ARM::VLD1LNdAsm_P8: case ARM::VLD1LNdAsm_I8: case ARM::VLD1LNdAsm_S8: case ARM::VLD1LNdAsm_U8: + Spacing = 1; return ARM::VLD1LNd8; case ARM::VLD1LNdAsm_16: case ARM::VLD1LNdAsm_P16: case ARM::VLD1LNdAsm_I16: case ARM::VLD1LNdAsm_S16: case ARM::VLD1LNdAsm_U16: + Spacing = 1; return ARM::VLD1LNd16; case ARM::VLD1LNdAsm_32: case ARM::VLD1LNdAsm_F: case ARM::VLD1LNdAsm_F32: case ARM::VLD1LNdAsm_I32: case ARM::VLD1LNdAsm_S32: case ARM::VLD1LNdAsm_U32: + Spacing = 1; return ARM::VLD1LNd32; // VLD2LN case ARM::VLD2LNdWB_fixed_Asm_8: case ARM::VLD2LNdWB_fixed_Asm_P8: case ARM::VLD2LNdWB_fixed_Asm_I8: case ARM::VLD2LNdWB_fixed_Asm_S8: case ARM::VLD2LNdWB_fixed_Asm_U8: + Spacing = 1; return ARM::VLD2LNd8_UPD; case ARM::VLD2LNdWB_fixed_Asm_16: case ARM::VLD2LNdWB_fixed_Asm_P16: case ARM::VLD2LNdWB_fixed_Asm_I16: case ARM::VLD2LNdWB_fixed_Asm_S16: case ARM::VLD2LNdWB_fixed_Asm_U16: + Spacing = 1; return ARM::VLD2LNd16_UPD; case ARM::VLD2LNdWB_fixed_Asm_32: case ARM::VLD2LNdWB_fixed_Asm_F: case ARM::VLD2LNdWB_fixed_Asm_F32: case ARM::VLD2LNdWB_fixed_Asm_I32: case ARM::VLD2LNdWB_fixed_Asm_S32: case ARM::VLD2LNdWB_fixed_Asm_U32: + Spacing = 1; return ARM::VLD2LNd32_UPD; + case ARM::VLD2LNqWB_fixed_Asm_16: case ARM::VLD2LNqWB_fixed_Asm_P16: + case ARM::VLD2LNqWB_fixed_Asm_I16: case ARM::VLD2LNqWB_fixed_Asm_S16: + case ARM::VLD2LNqWB_fixed_Asm_U16: + Spacing = 1; + return ARM::VLD2LNq16_UPD; + case ARM::VLD2LNqWB_fixed_Asm_32: case ARM::VLD2LNqWB_fixed_Asm_F: + case ARM::VLD2LNqWB_fixed_Asm_F32: case ARM::VLD2LNqWB_fixed_Asm_I32: + case ARM::VLD2LNqWB_fixed_Asm_S32: case ARM::VLD2LNqWB_fixed_Asm_U32: + Spacing = 2; + return ARM::VLD2LNq32_UPD; case ARM::VLD2LNdWB_register_Asm_8: case ARM::VLD2LNdWB_register_Asm_P8: case ARM::VLD2LNdWB_register_Asm_I8: case ARM::VLD2LNdWB_register_Asm_S8: case ARM::VLD2LNdWB_register_Asm_U8: + Spacing = 1; return ARM::VLD2LNd8_UPD; case ARM::VLD2LNdWB_register_Asm_16: case ARM::VLD2LNdWB_register_Asm_P16: case ARM::VLD2LNdWB_register_Asm_I16: case ARM::VLD2LNdWB_register_Asm_S16: case ARM::VLD2LNdWB_register_Asm_U16: + Spacing = 1; return ARM::VLD2LNd16_UPD; case ARM::VLD2LNdWB_register_Asm_32: case ARM::VLD2LNdWB_register_Asm_F: case ARM::VLD2LNdWB_register_Asm_F32: case ARM::VLD2LNdWB_register_Asm_I32: case ARM::VLD2LNdWB_register_Asm_S32: case ARM::VLD2LNdWB_register_Asm_U32: + Spacing = 1; return ARM::VLD2LNd32_UPD; + case ARM::VLD2LNqWB_register_Asm_16: case ARM::VLD2LNqWB_register_Asm_P16: + case ARM::VLD2LNqWB_register_Asm_I16: case ARM::VLD2LNqWB_register_Asm_S16: + case ARM::VLD2LNqWB_register_Asm_U16: + Spacing = 2; + return ARM::VLD2LNq16_UPD; + case ARM::VLD2LNqWB_register_Asm_32: case ARM::VLD2LNqWB_register_Asm_F: + case ARM::VLD2LNqWB_register_Asm_F32: case ARM::VLD2LNqWB_register_Asm_I32: + case ARM::VLD2LNqWB_register_Asm_S32: case ARM::VLD2LNqWB_register_Asm_U32: + Spacing = 2; + return ARM::VLD2LNq32_UPD; case ARM::VLD2LNdAsm_8: case ARM::VLD2LNdAsm_P8: case ARM::VLD2LNdAsm_I8: case ARM::VLD2LNdAsm_S8: case ARM::VLD2LNdAsm_U8: + Spacing = 1; return ARM::VLD2LNd8; case ARM::VLD2LNdAsm_16: case ARM::VLD2LNdAsm_P16: case ARM::VLD2LNdAsm_I16: case ARM::VLD2LNdAsm_S16: case ARM::VLD2LNdAsm_U16: + Spacing = 1; return ARM::VLD2LNd16; case ARM::VLD2LNdAsm_32: case ARM::VLD2LNdAsm_F: case ARM::VLD2LNdAsm_F32: case ARM::VLD2LNdAsm_I32: case ARM::VLD2LNdAsm_S32: case ARM::VLD2LNdAsm_U32: + Spacing = 1; return ARM::VLD2LNd32; + case ARM::VLD2LNqAsm_16: case ARM::VLD2LNqAsm_P16: + case ARM::VLD2LNqAsm_I16: case ARM::VLD2LNqAsm_S16: + case ARM::VLD2LNqAsm_U16: + Spacing = 2; + return ARM::VLD2LNq16; + case ARM::VLD2LNqAsm_32: case ARM::VLD2LNqAsm_F: + case ARM::VLD2LNqAsm_F32: case ARM::VLD2LNqAsm_I32: + case ARM::VLD2LNqAsm_S32: case ARM::VLD2LNqAsm_U32: + Spacing = 2; + return ARM::VLD2LNq32; } } @@ -5415,7 +5481,8 @@ MCInst TmpInst; // Shuffle the operands around so the lane index operand is in the // right place. - TmpInst.setOpcode(getRealVLDLNOpcode(Inst.getOpcode())); + unsigned Spacing; + TmpInst.setOpcode(getRealVLDLNOpcode(Inst.getOpcode(), Spacing)); TmpInst.addOperand(Inst.getOperand(0)); // Vd TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb TmpInst.addOperand(Inst.getOperand(2)); // Rn @@ -5429,26 +5496,34 @@ return true; } - case ARM::VLD2LNdWB_register_Asm_8: case ARM::VLD2LNdWB_register_Asm_P8: - case ARM::VLD2LNdWB_register_Asm_I8: case ARM::VLD2LNdWB_register_Asm_S8: - case ARM::VLD2LNdWB_register_Asm_U8: case ARM::VLD2LNdWB_register_Asm_16: + case ARM::VLD2LNdWB_register_Asm_8: case ARM::VLD2LNdWB_register_Asm_P8: + case ARM::VLD2LNdWB_register_Asm_I8: case ARM::VLD2LNdWB_register_Asm_S8: + case ARM::VLD2LNdWB_register_Asm_U8: case ARM::VLD2LNdWB_register_Asm_16: case ARM::VLD2LNdWB_register_Asm_P16: case ARM::VLD2LNdWB_register_Asm_I16: case ARM::VLD2LNdWB_register_Asm_S16: case ARM::VLD2LNdWB_register_Asm_U16: - case ARM::VLD2LNdWB_register_Asm_32: case ARM::VLD2LNdWB_register_Asm_F: + case ARM::VLD2LNdWB_register_Asm_32: case ARM::VLD2LNdWB_register_Asm_F: case ARM::VLD2LNdWB_register_Asm_F32: case ARM::VLD2LNdWB_register_Asm_I32: - case ARM::VLD2LNdWB_register_Asm_S32: case ARM::VLD2LNdWB_register_Asm_U32: { + case ARM::VLD2LNdWB_register_Asm_S32: case ARM::VLD2LNdWB_register_Asm_U32: + case ARM::VLD2LNqWB_register_Asm_P16: case ARM::VLD2LNqWB_register_Asm_I16: + case ARM::VLD2LNqWB_register_Asm_S16: case ARM::VLD2LNqWB_register_Asm_U16: + case ARM::VLD2LNqWB_register_Asm_32: case ARM::VLD2LNqWB_register_Asm_F: + case ARM::VLD2LNqWB_register_Asm_F32: case ARM::VLD2LNqWB_register_Asm_I32: + case ARM::VLD2LNqWB_register_Asm_S32: case ARM::VLD2LNqWB_register_Asm_U32: { MCInst TmpInst; // Shuffle the operands around so the lane index operand is in the // right place. - TmpInst.setOpcode(getRealVLDLNOpcode(Inst.getOpcode())); + unsigned Spacing; + TmpInst.setOpcode(getRealVLDLNOpcode(Inst.getOpcode(), Spacing)); TmpInst.addOperand(Inst.getOperand(0)); // Vd - TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg()+1)); + TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + + Spacing)); TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb TmpInst.addOperand(Inst.getOperand(2)); // Rn TmpInst.addOperand(Inst.getOperand(3)); // alignment TmpInst.addOperand(Inst.getOperand(4)); // Rm TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd) - TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg()+1)); + TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + + Spacing)); TmpInst.addOperand(Inst.getOperand(1)); // lane TmpInst.addOperand(Inst.getOperand(5)); // CondCode TmpInst.addOperand(Inst.getOperand(6)); @@ -5467,7 +5542,8 @@ MCInst TmpInst; // Shuffle the operands around so the lane index operand is in the // right place. - TmpInst.setOpcode(getRealVLDLNOpcode(Inst.getOpcode())); + unsigned Spacing; + TmpInst.setOpcode(getRealVLDLNOpcode(Inst.getOpcode(), Spacing)); TmpInst.addOperand(Inst.getOperand(0)); // Vd TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb TmpInst.addOperand(Inst.getOperand(2)); // Rn @@ -5481,26 +5557,34 @@ return true; } - case ARM::VLD2LNdWB_fixed_Asm_8: case ARM::VLD2LNdWB_fixed_Asm_P8: - case ARM::VLD2LNdWB_fixed_Asm_I8: case ARM::VLD2LNdWB_fixed_Asm_S8: - case ARM::VLD2LNdWB_fixed_Asm_U8: case ARM::VLD2LNdWB_fixed_Asm_16: + case ARM::VLD2LNdWB_fixed_Asm_8: case ARM::VLD2LNdWB_fixed_Asm_P8: + case ARM::VLD2LNdWB_fixed_Asm_I8: case ARM::VLD2LNdWB_fixed_Asm_S8: + case ARM::VLD2LNdWB_fixed_Asm_U8: case ARM::VLD2LNdWB_fixed_Asm_16: case ARM::VLD2LNdWB_fixed_Asm_P16: case ARM::VLD2LNdWB_fixed_Asm_I16: case ARM::VLD2LNdWB_fixed_Asm_S16: case ARM::VLD2LNdWB_fixed_Asm_U16: - case ARM::VLD2LNdWB_fixed_Asm_32: case ARM::VLD2LNdWB_fixed_Asm_F: + case ARM::VLD2LNdWB_fixed_Asm_32: case ARM::VLD2LNdWB_fixed_Asm_F: case ARM::VLD2LNdWB_fixed_Asm_F32: case ARM::VLD2LNdWB_fixed_Asm_I32: - case ARM::VLD2LNdWB_fixed_Asm_S32: case ARM::VLD2LNdWB_fixed_Asm_U32: { + case ARM::VLD2LNdWB_fixed_Asm_S32: case ARM::VLD2LNdWB_fixed_Asm_U32: + case ARM::VLD2LNqWB_fixed_Asm_P16: case ARM::VLD2LNqWB_fixed_Asm_I16: + case ARM::VLD2LNqWB_fixed_Asm_S16: case ARM::VLD2LNqWB_fixed_Asm_U16: + case ARM::VLD2LNqWB_fixed_Asm_32: case ARM::VLD2LNqWB_fixed_Asm_F: + case ARM::VLD2LNqWB_fixed_Asm_F32: case ARM::VLD2LNqWB_fixed_Asm_I32: + case ARM::VLD2LNqWB_fixed_Asm_S32: case ARM::VLD2LNqWB_fixed_Asm_U32: { MCInst TmpInst; // Shuffle the operands around so the lane index operand is in the // right place. - TmpInst.setOpcode(getRealVLDLNOpcode(Inst.getOpcode())); + unsigned Spacing; + TmpInst.setOpcode(getRealVLDLNOpcode(Inst.getOpcode(), Spacing)); TmpInst.addOperand(Inst.getOperand(0)); // Vd - TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg()+1)); + TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + + Spacing)); TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb TmpInst.addOperand(Inst.getOperand(2)); // Rn TmpInst.addOperand(Inst.getOperand(3)); // alignment TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd) - TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg()+1)); + TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + + Spacing)); TmpInst.addOperand(Inst.getOperand(1)); // lane TmpInst.addOperand(Inst.getOperand(4)); // CondCode TmpInst.addOperand(Inst.getOperand(5)); @@ -5517,7 +5601,8 @@ MCInst TmpInst; // Shuffle the operands around so the lane index operand is in the // right place. - TmpInst.setOpcode(getRealVLDLNOpcode(Inst.getOpcode())); + unsigned Spacing; + TmpInst.setOpcode(getRealVLDLNOpcode(Inst.getOpcode(), Spacing)); TmpInst.addOperand(Inst.getOperand(0)); // Vd TmpInst.addOperand(Inst.getOperand(2)); // Rn TmpInst.addOperand(Inst.getOperand(3)); // alignment @@ -5529,22 +5614,29 @@ return true; } - case ARM::VLD2LNdAsm_8: case ARM::VLD2LNdAsm_P8: case ARM::VLD2LNdAsm_I8: - case ARM::VLD2LNdAsm_S8: case ARM::VLD2LNdAsm_U8: case ARM::VLD2LNdAsm_16: + case ARM::VLD2LNdAsm_8: case ARM::VLD2LNdAsm_P8: case ARM::VLD2LNdAsm_I8: + case ARM::VLD2LNdAsm_S8: case ARM::VLD2LNdAsm_U8: case ARM::VLD2LNdAsm_16: case ARM::VLD2LNdAsm_P16: case ARM::VLD2LNdAsm_I16: case ARM::VLD2LNdAsm_S16: - case ARM::VLD2LNdAsm_U16: case ARM::VLD2LNdAsm_32: case ARM::VLD2LNdAsm_F: + case ARM::VLD2LNdAsm_U16: case ARM::VLD2LNdAsm_32: case ARM::VLD2LNdAsm_F: case ARM::VLD2LNdAsm_F32: case ARM::VLD2LNdAsm_I32: case ARM::VLD2LNdAsm_S32: - case ARM::VLD2LNdAsm_U32: { + case ARM::VLD2LNdAsm_U32: case ARM::VLD2LNqAsm_16: case ARM::VLD2LNqAsm_P16: + case ARM::VLD2LNqAsm_I16: case ARM::VLD2LNqAsm_S16: case ARM::VLD2LNqAsm_U16: + case ARM::VLD2LNqAsm_32: case ARM::VLD2LNqAsm_F: case ARM::VLD2LNqAsm_F32: + case ARM::VLD2LNqAsm_I32: case ARM::VLD2LNqAsm_S32: + case ARM::VLD2LNqAsm_U32: { MCInst TmpInst; // Shuffle the operands around so the lane index operand is in the // right place. - TmpInst.setOpcode(getRealVLDLNOpcode(Inst.getOpcode())); + unsigned Spacing; + TmpInst.setOpcode(getRealVLDLNOpcode(Inst.getOpcode(), Spacing)); TmpInst.addOperand(Inst.getOperand(0)); // Vd - TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg()+1)); + TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + + Spacing)); TmpInst.addOperand(Inst.getOperand(2)); // Rn TmpInst.addOperand(Inst.getOperand(3)); // alignment TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd) - TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg()+1)); + TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + + Spacing)); TmpInst.addOperand(Inst.getOperand(1)); // lane TmpInst.addOperand(Inst.getOperand(4)); // CondCode TmpInst.addOperand(Inst.getOperand(5)); Modified: llvm/trunk/test/MC/ARM/neon-vld-encoding.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/neon-vld-encoding.s?rev=146983&r1=146982&r2=146983&view=diff ============================================================================== --- llvm/trunk/test/MC/ARM/neon-vld-encoding.s (original) +++ llvm/trunk/test/MC/ARM/neon-vld-encoding.s Tue Dec 20 13:21:26 2011 @@ -230,8 +230,9 @@ vld2.8 {d16[1], d17[1]}, [r0, :16] vld2.16 {d16[1], d17[1]}, [r0, :32] vld2.32 {d16[1], d17[1]}, [r0] -@ vld2.16 {d17[1], d19[1]}, [r0] -@ vld2.32 {d17[0], d19[0]}, [r0, :64] + vld2.16 {d17[1], d19[1]}, [r0] + vld2.32 {d17[0], d19[0]}, [r0, :64] + vld2.32 {d17[0], d19[0]}, [r0, :64]! vld2.8 {d2[4], d3[4]}, [r2], r3 vld2.8 {d2[4], d3[4]}, [r2]! vld2.8 {d2[4], d3[4]}, [r2] @@ -239,8 +240,9 @@ @ CHECK: vld2.8 {d16[1], d17[1]}, [r0, :16] @ encoding: [0x3f,0x01,0xe0,0xf4] @ CHECK: vld2.16 {d16[1], d17[1]}, [r0, :32] @ encoding: [0x5f,0x05,0xe0,0xf4] @ CHECK: vld2.32 {d16[1], d17[1]}, [r0] @ encoding: [0x8f,0x09,0xe0,0xf4] -@ FIXME: vld2.16 {d17[1], d19[1]}, [r0] @ encoding: [0x6f,0x15,0xe0,0xf4] -@ FIXME: vld2.32 {d17[0], d19[0]}, [r0, :64] @ encoding: [0x5f,0x19,0xe0,0xf4] +@ CHECK: vld2.16 {d17[1], d19[1]}, [r0] @ encoding: [0x6f,0x15,0xe0,0xf4] +@ CHECK: vld2.32 {d17[0], d19[0]}, [r0, :64] @ encoding: [0x5f,0x19,0xe0,0xf4] +@ CHECK: vld2.32 {d17[0], d19[0]}, [r0, :64]! @ encoding: [0x5d,0x19,0xe0,0xf4] @ CHECK: vld2.8 {d2[4], d3[4]}, [r2], r3 @ encoding: [0x83,0x21,0xa2,0xf4] @ CHECK: vld2.8 {d2[4], d3[4]}, [r2]! @ encoding: [0x8d,0x21,0xa2,0xf4] @ CHECK: vld2.8 {d2[4], d3[4]}, [r2] @ encoding: [0x8f,0x21,0xa2,0xf4] From grosbach at apple.com Tue Dec 20 13:32:32 2011 From: grosbach at apple.com (Jim Grosbach) Date: Tue, 20 Dec 2011 11:32:32 -0800 Subject: [llvm-commits] [PATCH] MC ARM Thumb: fix incorrect relocation generation (PR11214) In-Reply-To: References: <000001ccbf1d$618f7490$24ae5db0$%beyls@arm.com> <57817466-3086-4652-85E2-4959AF23D81B@apple.com> Message-ID: <107270DB-89BE-4C71-9181-CF7FDD300E25@apple.com> Yeah, that's my guess. An assert(0 "unimplemented non-PLT call!") or something would have been better if that's the case exactly to prevent this sort of head-scratching. :) -Jim On Dec 20, 2011, at 11:21 AM, James Molloy wrote: > Yeah, I was confused about that too. > > I couldn't comprehend why that conditional was even there in the first place - an R_ARM_NONE relocation is *never* required for a call (it's a special no-op reloc). > > The only thing I could think of is that someone wanted to fix the relocation given to PLT entries and decided to keep the a broken behaviour for the default case, perhaps they had no knowledge about it. > ________________________________________ > From: llvm-commits-bounces at cs.uiuc.edu [llvm-commits-bounces at cs.uiuc.edu] On Behalf Of Jim Grosbach [grosbach at apple.com] > Sent: 20 December 2011 19:07 > To: Kristof Beyls > Cc: llvm-commits at cs.uiuc.edu > Subject: Re: [llvm-commits] [PATCH] MC ARM Thumb: fix incorrect relocation generation (PR11214) > > Someone with ELF knowledge should look at this. I'm a bit nervous about removing the conditional as it seems to imply that there's an different relocation that should be generated depending on the variant kind. > > -Jim > > On Dec 20, 2011, at 5:43 AM, Kristof Beyls wrote: > >> Hi, >> >> Please find a patch for fixing incorrect generation of relocation >> information on Thumb function calls. >> This should fix quite a few incorrect code generation problems in Thumb mode >> when using the integrated assembler. >> I believe this fixes PR11214 >> (http://www.llvm.org/bugs/show_bug.cgi?id=11214). >> >> Is this OK? >> >> Thanks, >> >> Kristof >> _______________________________________________ >> llvm-commits mailing list >> llvm-commits at cs.uiuc.edu >> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits > > > -- IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you. > From dpatel at apple.com Tue Dec 20 13:29:36 2011 From: dpatel at apple.com (Devang Patel) Date: Tue, 20 Dec 2011 19:29:36 -0000 Subject: [llvm-commits] [llvm] r146984 - in /llvm/trunk: include/llvm-c/Core.h lib/VMCore/Core.cpp Message-ID: <20111220192936.78B242A6C12C@llvm.org> Author: dpatel Date: Tue Dec 20 13:29:36 2011 New Revision: 146984 URL: http://llvm.org/viewvc/llvm-project?rev=146984&view=rev Log: Add support to add named metadata operand. Patch by Andrew Wilkins! Modified: llvm/trunk/include/llvm-c/Core.h llvm/trunk/lib/VMCore/Core.cpp Modified: llvm/trunk/include/llvm-c/Core.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm-c/Core.h?rev=146984&r1=146983&r2=146984&view=diff ============================================================================== --- llvm/trunk/include/llvm-c/Core.h (original) +++ llvm/trunk/include/llvm-c/Core.h Tue Dec 20 13:29:36 2011 @@ -567,6 +567,8 @@ const char *LLVMGetMDString(LLVMValueRef V, unsigned* Len); unsigned LLVMGetNamedMetadataNumOperands(LLVMModuleRef M, const char* name); void LLVMGetNamedMetadataOperands(LLVMModuleRef M, const char* name, LLVMValueRef *Dest); +void LLVMAddNamedMetadataOperand(LLVMModuleRef M, const char* name, + LLVMValueRef Val); /* Operations on scalar constants */ LLVMValueRef LLVMConstInt(LLVMTypeRef IntTy, unsigned long long N, Modified: llvm/trunk/lib/VMCore/Core.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/Core.cpp?rev=146984&r1=146983&r2=146984&view=diff ============================================================================== --- llvm/trunk/lib/VMCore/Core.cpp (original) +++ llvm/trunk/lib/VMCore/Core.cpp Tue Dec 20 13:29:36 2011 @@ -566,6 +566,17 @@ Dest[i] = wrap(N->getOperand(i)); } +void LLVMAddNamedMetadataOperand(LLVMModuleRef M, const char* name, + LLVMValueRef Val) +{ + NamedMDNode *N = unwrap(M)->getOrInsertNamedMetadata(name); + if (!N) + return; + MDNode *Op = Val ? unwrap(Val) : NULL; + if (Op) + N->addOperand(Op); +} + /*--.. Operations on scalar constants ......................................--*/ LLVMValueRef LLVMConstInt(LLVMTypeRef IntTy, unsigned long long N, From dpatel at apple.com Tue Dec 20 13:33:10 2011 From: dpatel at apple.com (Devang Patel) Date: Tue, 20 Dec 2011 11:33:10 -0800 Subject: [llvm-commits] [PATCH] Extend named metadata support in the LLVM C API In-Reply-To: References:

Message-ID: <4661010B-7543-441D-86F7-57E95C9A0E08@apple.com> On Dec 20, 2011, at 6:56 AM, Andrew Wilkins wrote: > On Tue, Dec 20, 2011 at 2:06 AM, Devang Patel wrote: > We want to preserve backward compatibility in C API as much as possible. So we don't want to remove LLVMGetNamedMetadataOperands or change signature of LLVMGetNamedMetadataNumOperands. > > Thanks for the feedback. Fair enough. Attached is a more conservative patch, just adding one new function LLVMAddNamedMetadataOperand. Looks good. I applied your patch r146984. - Devang > > Regards, > -- > Andrew Wilkins > http://awilkins.id.au > > -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20111220/7f5a9d2f/attachment.html From ahatanak at gmail.com Tue Dec 20 13:39:08 2011 From: ahatanak at gmail.com (Akira Hatanaka) Date: Tue, 20 Dec 2011 11:39:08 -0800 Subject: [llvm-commits] [llvm] r146604 - in /llvm/trunk: lib/CodeGen/MachineSink.cpp test/CodeGen/ARM/2011-12-14-machine-sink.ll In-Reply-To: <618FAA67-0A0A-4D20-9E58-491632F2BA7C@apple.com> References: <20111214232038.E9C9D2A6C12C@llvm.org> <5FF21D31-13D7-4EAA-99FC-EFC1AFA0C8F7@apple.com> <618FAA67-0A0A-4D20-9E58-491632F2BA7C@apple.com> Message-ID: After further investigation, I found a function that is possibly being mis-compiled. This is what I did: 1. Reverted this patch (machine sinking is less conservative now). 2. Turned off machine sinking just for the function. The generated executable segfaults when it is run. Additionally, I found that it produces the expected result and terminates normally if I add the option "-regalloc=basic" to llc to turn off greedy register allocation. Is there anything you can tell from this? Which part of the output should I pay attention to when I am reading llc's outputs when option -debug or -stats is provided? The function in question is fairly large and complicated, so it is difficult to tell which part is being mis-compiled just by looking at the machinefunction dumps or the CFGs viewCFG and viewCFGOnly show. On Fri, Dec 16, 2011 at 3:50 PM, Devang Patel wrote: > > On Dec 16, 2011, at 2:34 PM, Akira Hatanaka wrote: > >> The test still fails after I disable Machine Sink pass, but it passes >> if I revert the patch (just this one, the ones checked in after this >> remain applied). So it looks like MachineSinking is not causing the >> failure, but there is a bug in some other part of the backend that >> gets exposed if the pass doesn't sink instructions at all or is less >> aggresive. >> >> Do you have any idea which pass might be doing something wrong? > > > In the test case, which prompted this patch, machine sink pass was ?increasing distance between reg def and use resulting in unnecessary extra spill. > > However, in your particular case I have no idea what is going wrong. Finding out what exactly is miscompiled may be your best alternative. Do you see any significant (or noticeable) changes in stats for passes that follow machine sink ? >> >> Here are the stats: >> >> (before) >> 15 machine-sink ? ? ?- Number of copies coalesced >> 674 machine-sink ? ? ?- Number of critical edges split >> 3397 machine-sink ? ? ?- Number of machine instructions sunk >> >> (after) >> 15 machine-sink ? ? ?- Number of copies coalesced >> 674 machine-sink ? ? ?- Number of critical edges split >> 2881 machine-sink ? ? ?- Number of machine instructions sunk >> >> On Fri, Dec 16, 2011 at 9:21 AM, Devang Patel wrote: >>> >>> On Dec 15, 2011, at 7:55 PM, Akira Hatanaka wrote: >>> >>>> This commit is causing one the tests in llvm test-suite >>>> (MultiSource/Benchmarks/tramp3d-v4) to fail. >>>> It segfaults during execution. The target architecture is mips32r2. >>>> >>>> Would it be possible to revert this until we can figure out what is >>>> causing the failure? >>> >>> This patch makes machine sink more conservative. Please, >>> >>> 1) Disable Machine Sink pass completely locally and see if the segfaults reproduces or not. >>> 2) Enable stats and see if notice any change before and after the patch. >>> 3) Please file bugzilla with a reproducible test case before reverting the patch. >>> >>> Thanks, >>> - >>> Devang >>> >>> >>>> On Wed, Dec 14, 2011 at 3:20 PM, Devang Patel wrote: >>>>> Author: dpatel >>>>> Date: Wed Dec 14 17:20:38 2011 >>>>> New Revision: 146604 >>>>> >>>>> URL: http://llvm.org/viewvc/llvm-project?rev=146604&view=rev >>>>> Log: >>>>> Do not sink instruction, if it is not profitable. >>>>> >>>>> On ARM, peephole optimization for ABS creates a trivial cfg triangle which tempts machine sink to sink instructions in code which is really straight line code. Sometimes this sinking may alter register allocator input such that use and def of a reg is divided by a branch in between, which may result in extra spills. Now mahine sink avoids sinking if final sink destination is post dominator. >>>>> >>>>> Radar 10266272. >>>>> >>>>> Added: >>>>> ? ?llvm/trunk/test/CodeGen/ARM/2011-12-14-machine-sink.ll >>>>> Modified: >>>>> ? ?llvm/trunk/lib/CodeGen/MachineSink.cpp >>>>> >>>>> Modified: llvm/trunk/lib/CodeGen/MachineSink.cpp >>>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineSink.cpp?rev=146604&r1=146603&r2=146604&view=diff >>>>> ============================================================================== >>>>> --- llvm/trunk/lib/CodeGen/MachineSink.cpp (original) >>>>> +++ llvm/trunk/lib/CodeGen/MachineSink.cpp Wed Dec 14 17:20:38 2011 >>>>> @@ -90,7 +90,11 @@ >>>>> ? ? bool AllUsesDominatedByBlock(unsigned Reg, MachineBasicBlock *MBB, >>>>> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?MachineBasicBlock *DefMBB, >>>>> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?bool &BreakPHIEdge, bool &LocalUse) const; >>>>> - ? ?MachineBasicBlock *FindSuccToSinkTo(MachineInstr *MI, bool &BreakPHIEdge); >>>>> + ? ?MachineBasicBlock *FindSuccToSinkTo(MachineInstr *MI, MachineBasicBlock *MBB, >>>>> + ? ? ? ? ? ? ? bool &BreakPHIEdge); >>>>> + ? ?bool isProfitableToSinkTo(unsigned Reg, MachineInstr *MI, >>>>> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?MachineBasicBlock *MBB, >>>>> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?MachineBasicBlock *SuccToSinkTo); >>>>> >>>>> ? ? bool PerformTrivialForwardCoalescing(MachineInstr *MI, >>>>> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?MachineBasicBlock *MBB); >>>>> @@ -399,18 +403,76 @@ >>>>> ? } >>>>> ?} >>>>> >>>>> +/// isPostDominatedBy - Return true if A is post dominated by B. >>>>> +static bool isPostDominatedBy(MachineBasicBlock *A, MachineBasicBlock *B) { >>>>> + >>>>> + ?// FIXME - Use real post dominator. >>>>> + ?if (A->succ_size() != 2) >>>>> + ? ?return false; >>>>> + ?MachineBasicBlock::succ_iterator I = A->succ_begin(); >>>>> + ?if (B == *I) >>>>> + ? ?++I; >>>>> + ?MachineBasicBlock *OtherSuccBlock = *I; >>>>> + ?if (OtherSuccBlock->succ_size() != 1 || >>>>> + ? ? ?*(OtherSuccBlock->succ_begin()) != B) >>>>> + ? ?return false; >>>>> + >>>>> + ?return true; >>>>> +} >>>>> + >>>>> +/// isProfitableToSinkTo - Return true if it is profitable to sink MI. >>>>> +bool MachineSinking::isProfitableToSinkTo(unsigned Reg, MachineInstr *MI, >>>>> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?MachineBasicBlock *MBB, >>>>> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?MachineBasicBlock *SuccToSinkTo) { >>>>> + ?assert (MI && "Invalid MachineInstr!"); >>>>> + ?assert (SuccToSinkTo && "Invalid SinkTo Candidate BB"); >>>>> + >>>>> + ?if (MBB == SuccToSinkTo) >>>>> + ? ?return false; >>>>> + >>>>> + ?// It is profitable if SuccToSinkTo does not post dominate current block. >>>>> + ?if (!isPostDominatedBy(MBB, SuccToSinkTo)) >>>>> + ? ? ?return true; >>>>> + >>>>> + ?// Check if only use in post dominated block is PHI instruction. >>>>> + ?bool NonPHIUse = false; >>>>> + ?for (MachineRegisterInfo::use_nodbg_iterator >>>>> + ? ? ? ? I = MRI->use_nodbg_begin(Reg), E = MRI->use_nodbg_end(); >>>>> + ? ? ? I != E; ++I) { >>>>> + ? ?MachineInstr *UseInst = &*I; >>>>> + ? ?MachineBasicBlock *UseBlock = UseInst->getParent(); >>>>> + ? ?if (UseBlock == SuccToSinkTo && !UseInst->isPHI()) >>>>> + ? ? ?NonPHIUse = true; >>>>> + ?} >>>>> + ?if (!NonPHIUse) >>>>> + ? ?return true; >>>>> + >>>>> + ?// If SuccToSinkTo post dominates then also it may be profitable if MI >>>>> + ?// can further profitably sinked into another block in next round. >>>>> + ?bool BreakPHIEdge = false; >>>>> + ?// FIXME - If finding successor is compile time expensive then catch results. >>>>> + ?if (MachineBasicBlock *MBB2 = FindSuccToSinkTo(MI, SuccToSinkTo, BreakPHIEdge)) >>>>> + ? ?return isProfitableToSinkTo(Reg, MI, SuccToSinkTo, MBB2); >>>>> + >>>>> + ?// If SuccToSinkTo is final destination and it is a post dominator of current >>>>> + ?// block then it is not profitable to sink MI into SuccToSinkTo block. >>>>> + ?return false; >>>>> +} >>>>> + >>>>> ?/// FindSuccToSinkTo - Find a successor to sink this instruction to. >>>>> ?MachineBasicBlock *MachineSinking::FindSuccToSinkTo(MachineInstr *MI, >>>>> - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? bool &BreakPHIEdge) { >>>>> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? MachineBasicBlock *MBB, >>>>> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? bool &BreakPHIEdge) { >>>>> + >>>>> + ?assert (MI && "Invalid MachineInstr!"); >>>>> + ?assert (MBB && "Invalid MachineBasicBlock!"); >>>>> >>>>> ? // Loop over all the operands of the specified instruction. ?If there is >>>>> ? // anything we can't handle, bail out. >>>>> - ?MachineBasicBlock *ParentBlock = MI->getParent(); >>>>> >>>>> ? // SuccToSinkTo - This is the successor to sink this instruction to, once we >>>>> ? // decide. >>>>> ? MachineBasicBlock *SuccToSinkTo = 0; >>>>> - >>>>> ? for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { >>>>> ? ? const MachineOperand &MO = MI->getOperand(i); >>>>> ? ? if (!MO.isReg()) continue; ?// Ignore non-register operands. >>>>> @@ -469,7 +531,7 @@ >>>>> ? ? ? ? // If a previous operand picked a block to sink to, then this operand >>>>> ? ? ? ? // must be sinkable to the same block. >>>>> ? ? ? ? bool LocalUse = false; >>>>> - ? ? ? ?if (!AllUsesDominatedByBlock(Reg, SuccToSinkTo, ParentBlock, >>>>> + ? ? ? ?if (!AllUsesDominatedByBlock(Reg, SuccToSinkTo, MBB, >>>>> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?BreakPHIEdge, LocalUse)) >>>>> ? ? ? ? ? return NULL; >>>>> >>>>> @@ -478,11 +540,11 @@ >>>>> >>>>> ? ? ? // Otherwise, we should look at all the successors and decide which one >>>>> ? ? ? // we should sink to. >>>>> - ? ? ?for (MachineBasicBlock::succ_iterator SI = ParentBlock->succ_begin(), >>>>> - ? ? ? ? ? E = ParentBlock->succ_end(); SI != E; ++SI) { >>>>> - ? ? ? MachineBasicBlock *SuccBlock = *SI; >>>>> + ? ? ?for (MachineBasicBlock::succ_iterator SI = MBB->succ_begin(), >>>>> + ? ? ? ? ? E = MBB->succ_end(); SI != E; ++SI) { >>>>> + ? ? ? ?MachineBasicBlock *SuccBlock = *SI; >>>>> ? ? ? ? bool LocalUse = false; >>>>> - ? ? ? ?if (AllUsesDominatedByBlock(Reg, SuccBlock, ParentBlock, >>>>> + ? ? ? ?if (AllUsesDominatedByBlock(Reg, SuccBlock, MBB, >>>>> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? BreakPHIEdge, LocalUse)) { >>>>> ? ? ? ? ? SuccToSinkTo = SuccBlock; >>>>> ? ? ? ? ? break; >>>>> @@ -495,12 +557,14 @@ >>>>> ? ? ? // If we couldn't find a block to sink to, ignore this instruction. >>>>> ? ? ? if (SuccToSinkTo == 0) >>>>> ? ? ? ? return NULL; >>>>> + ? ? ?else if (!isProfitableToSinkTo(Reg, MI, MBB, SuccToSinkTo)) >>>>> + ? ? ? ?return NULL; >>>>> ? ? } >>>>> ? } >>>>> >>>>> ? // It is not possible to sink an instruction into its own block. ?This can >>>>> ? // happen with loops. >>>>> - ?if (ParentBlock == SuccToSinkTo) >>>>> + ?if (MBB == SuccToSinkTo) >>>>> ? ? return NULL; >>>>> >>>>> ? // It's not safe to sink instructions to EH landing pad. Control flow into >>>>> @@ -532,7 +596,8 @@ >>>>> ? // and z and only shrink the live range of x. >>>>> >>>>> ? bool BreakPHIEdge = false; >>>>> - ?MachineBasicBlock *SuccToSinkTo = FindSuccToSinkTo(MI, BreakPHIEdge); >>>>> + ?MachineBasicBlock *ParentBlock = MI->getParent(); >>>>> + ?MachineBasicBlock *SuccToSinkTo = FindSuccToSinkTo(MI, ParentBlock, BreakPHIEdge); >>>>> >>>>> ? // If there are no outputs, it must have side-effects. >>>>> ? if (SuccToSinkTo == 0) >>>>> @@ -553,8 +618,6 @@ >>>>> >>>>> ? DEBUG(dbgs() << "Sink instr " << *MI << "\tinto block " << *SuccToSinkTo); >>>>> >>>>> - ?MachineBasicBlock *ParentBlock = MI->getParent(); >>>>> - >>>>> ? // If the block has multiple predecessors, this would introduce computation on >>>>> ? // a path that it doesn't already exist. ?We could split the critical edge, >>>>> ? // but for now we just punt. >>>>> >>>>> Added: llvm/trunk/test/CodeGen/ARM/2011-12-14-machine-sink.ll >>>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/2011-12-14-machine-sink.ll?rev=146604&view=auto >>>>> ============================================================================== >>>>> --- llvm/trunk/test/CodeGen/ARM/2011-12-14-machine-sink.ll (added) >>>>> +++ llvm/trunk/test/CodeGen/ARM/2011-12-14-machine-sink.ll Wed Dec 14 17:20:38 2011 >>>>> @@ -0,0 +1,48 @@ >>>>> +; RUN: llc < %s -o /dev/null -stats |& FileCheck %s -check-prefix=STATS >>>>> +; Radar 10266272 >>>>> +target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:32:64-v128:32:128-a0:0:32-n32-S32" >>>>> +target triple = "thumbv7-apple-ios4.0.0" >>>>> +; STATS-NOT: machine-sink >>>>> + >>>>> +define i32 @foo(i32 %h) nounwind readonly ssp { >>>>> +entry: >>>>> + ?br label %for.cond >>>>> + >>>>> +for.cond: ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ; preds = %for.body, %entry >>>>> + ?%cmp = icmp slt i32 0, %h >>>>> + ?br i1 %cmp, label %for.body, label %if.end299 >>>>> + >>>>> +for.body: ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ; preds = %for.cond >>>>> + ?%v.5 = select i1 undef, i32 undef, i32 0 >>>>> + ?%0 = load i8* undef, align 1, !tbaa !0 >>>>> + ?%conv88 = zext i8 %0 to i32 >>>>> + ?%sub89 = sub nsw i32 0, %conv88 >>>>> + ?%v.8 = select i1 undef, i32 undef, i32 %sub89 >>>>> + ?%1 = load i8* null, align 1, !tbaa !0 >>>>> + ?%conv108 = zext i8 %1 to i32 >>>>> + ?%2 = load i8* undef, align 1, !tbaa !0 >>>>> + ?%conv110 = zext i8 %2 to i32 >>>>> + ?%sub111 = sub nsw i32 %conv108, %conv110 >>>>> + ?%cmp112 = icmp slt i32 %sub111, 0 >>>>> + ?%sub115 = sub nsw i32 0, %sub111 >>>>> + ?%v.10 = select i1 %cmp112, i32 %sub115, i32 %sub111 >>>>> + ?%add62 = add i32 0, %v.5 >>>>> + ?%add73 = add i32 %add62, 0 >>>>> + ?%add84 = add i32 %add73, 0 >>>>> + ?%add95 = add i32 %add84, %v.8 >>>>> + ?%add106 = add i32 %add95, 0 >>>>> + ?%add117 = add i32 %add106, %v.10 >>>>> + ?%add128 = add i32 %add117, 0 >>>>> + ?%add139 = add i32 %add128, 0 >>>>> + ?%add150 = add i32 %add139, 0 >>>>> + ?%add161 = add i32 %add150, 0 >>>>> + ?%add172 = add i32 %add161, 0 >>>>> + ?br i1 undef, label %for.cond, label %if.end299 >>>>> + >>>>> +if.end299: ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?; preds = %for.body, %for.cond >>>>> + ?%s.10 = phi i32 [ %add172, %for.body ], [ 0, %for.cond ] >>>>> + ?ret i32 %s.10 >>>>> +} >>>>> + >>>>> +!0 = metadata !{metadata !"omnipotent char", metadata !1} >>>>> +!1 = metadata !{metadata !"Simple C/C++ TBAA", null} >>>>> >>>>> >>>>> _______________________________________________ >>>>> llvm-commits mailing list >>>>> llvm-commits at cs.uiuc.edu >>>>> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits >>> > From spop at codeaurora.org Tue Dec 20 13:57:05 2011 From: spop at codeaurora.org (Sebastian Pop) Date: Tue, 20 Dec 2011 13:57:05 -0600 Subject: [llvm-commits] [LLVMdev] [PATCH] BasicBlock Autovectorization Pass In-Reply-To: <1323822351.590.1687.camel@sapling> References: <1319909412.23036.851.camel@sapling> <1319914924.23036.852.camel@sapling> <1319919418.23036.881.camel@sapling> <1319928991.23036.957.camel@sapling> <1320108633.23036.1266.camel@sapling> <1320172356.23036.1298.camel@sapling> <4EB0462C.5010209@grosser.es> <1320184739.23036.1334.camel@sapling> <1320191694.23036.1497.camel@sapling> <1320749109.19359.76.camel@sapling> <4EB90E98.4010805@grosser.es> <1320762963.19359.117.camel@sapling> <4EB98207.2070807@grosser.es> <1320791390.19359.262.camel@sapling> <4EBC4B0F.6010609@grosser.es> <1321050998.19359.539.camel@sapling> <4EBDA7F9.9080709@grosser.es> <1321053083.19359.550.camel@sapling> <4EBDB1BF.7090006@grosser.es> <1321400339.19359.782.camel@sapling> <1321486739.19359.1067.camel@sapling> <4EC504B5.2020408@grosser.es> <1321898108.2507.36.camel@sapling> <1321932161.2507.101.camel@sapling> <1322067157.2507.263.camel@sapling> <4ED8F7B0.8050309@grosser.es> <1323822351.590.1687.camel@sapling> Message-ID: Hi, I see that there are two functions in your code that are O(n^2) in number of instructions of the program: getCandidatePairs and buildDepMap. I think that you could make these two functions faster if you work on some form of factored def-use chains for memory, like the VUSE/VDEFs of GCC. I was trying to find a similar representation in LLVM: isn't there already a virtual SSA representation for memory references in LLVM? Thanks, Sebastian -- Qualcomm Innovation Center, Inc is a member of Code Aurora Forum From grosbach at apple.com Tue Dec 20 14:03:00 2011 From: grosbach at apple.com (Jim Grosbach) Date: Tue, 20 Dec 2011 20:03:00 -0000 Subject: [llvm-commits] [llvm] r146985 - /llvm/trunk/test/MC/ARM/neon-vst-encoding.s Message-ID: <20111220200300.9EBB92A6C12C@llvm.org> Author: grosbach Date: Tue Dec 20 14:03:00 2011 New Revision: 146985 URL: http://llvm.org/viewvc/llvm-project?rev=146985&view=rev Log: ARM enable a few more tests. Modified: llvm/trunk/test/MC/ARM/neon-vst-encoding.s Modified: llvm/trunk/test/MC/ARM/neon-vst-encoding.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/neon-vst-encoding.s?rev=146985&r1=146984&r2=146985&view=diff ============================================================================== --- llvm/trunk/test/MC/ARM/neon-vst-encoding.s (original) +++ llvm/trunk/test/MC/ARM/neon-vst-encoding.s Tue Dec 20 14:03:00 2011 @@ -98,8 +98,8 @@ @ FIXME: vst4.32 {d17, d19, d21, d23}, [r0]! @ encoding: [0x8d,0x11,0x40,0xf4] -@ vst2.8 {d16[1], d17[1]}, [r0, :16] -@ vst2.16 {d16[1], d17[1]}, [r0, :32] + vst2.8 {d16[1], d17[1]}, [r0, :16] + vst2.16 {d16[1], d17[1]}, [r0, :32] vst2.32 {d16[1], d17[1]}, [r0] @ vst2.16 {d17[1], d19[1]}, [r0] @ vst2.32 {d17[0], d19[0]}, [r0, :64] @@ -108,8 +108,8 @@ vst2.8 {d2[4], d3[4]}, [r2]! vst2.8 {d2[4], d3[4]}, [r2] -@ FIXME: vst2.8 {d16[1], d17[1]}, [r0, :16] @ encoding: [0x3f,0x01,0xc0,0xf4] -@ FIXME: vst2.16 {d16[1], d17[1]}, [r0, :32] @ encoding: [0x5f,0x05,0xc0,0xf4] +@ CHECK: vst2.8 {d16[1], d17[1]}, [r0, :16] @ encoding: [0x3f,0x01,0xc0,0xf4] +@ CHECK: vst2.16 {d16[1], d17[1]}, [r0, :32] @ encoding: [0x5f,0x05,0xc0,0xf4] @ CHECK: vst2.32 {d16[1], d17[1]}, [r0] @ encoding: [0x8f,0x09,0xc0,0xf4] @ FIXME: vst2.16 {d17[1], d19[1]}, [r0] @ encoding: [0x6f,0x15,0xc0,0xf4] @ FIXME: vst2.32 {d17[0], d19[0]}, [r0, :64] @ encoding: [0x5f,0x19,0xc0,0xf4] From Kristof.Beyls at arm.com Tue Dec 20 14:06:19 2011 From: Kristof.Beyls at arm.com (Kristof Beyls) Date: Tue, 20 Dec 2011 20:06:19 +0000 Subject: [llvm-commits] [PATCH] MC ARM Thumb: fix incorrect relocation generation (PR11214) In-Reply-To: <107270DB-89BE-4C71-9181-CF7FDD300E25@apple.com> References: <000001ccbf1d$618f7490$24ae5db0$%beyls@arm.com> <57817466-3086-4652-85E2-4959AF23D81B@apple.com> <107270DB-89BE-4C71-9181-CF7FDD300E25@apple.com> Message-ID: The reason why I thought the patch would be OK is that the patch only changes the behaviour for the thumb bl and blx instructions (i.e. only for the cases ARM::fixup_arm_thumb_bl and ARM::fixup_arm_thumb_blx. For these instructions, I can't see why R_ARM_NONE would ever be the correct relocation type. The definition of R_ARM_NONE from the AAELF ABI: """ R_ARM_NONE records that the section containing the place to be relocated depends on the section defining the symbol mentioned in the relocation directive in a way otherwise invisible to the static linker. The effect is to prevent removal of sections that might otherwise appear to be unused. """ Thanks, Kristof > -----Original Message----- > From: Jim Grosbach [mailto:grosbach at apple.com] > Sent: 20 December 2011 19:33 > To: James Molloy > Cc: Kristof Beyls; llvm-commits at cs.uiuc.edu > Subject: Re: [llvm-commits] [PATCH] MC ARM Thumb: fix incorrect > relocation generation (PR11214) > > Yeah, that's my guess. An assert(0 "unimplemented non-PLT call!") or > something would have been better if that's the case exactly to prevent > this sort of head-scratching. :) > > -Jim > > On Dec 20, 2011, at 11:21 AM, James Molloy wrote: > > > Yeah, I was confused about that too. > > > > I couldn't comprehend why that conditional was even there in the > first place - an R_ARM_NONE relocation is *never* required for a call > (it's a special no-op reloc). > > > > The only thing I could think of is that someone wanted to fix the > relocation given to PLT entries and decided to keep the a broken > behaviour for the default case, perhaps they had no knowledge about it. > > ________________________________________ > > From: llvm-commits-bounces at cs.uiuc.edu [llvm-commits- > bounces at cs.uiuc.edu] On Behalf Of Jim Grosbach [grosbach at apple.com] > > Sent: 20 December 2011 19:07 > > To: Kristof Beyls > > Cc: llvm-commits at cs.uiuc.edu > > Subject: Re: [llvm-commits] [PATCH] MC ARM Thumb: fix incorrect > relocation generation (PR11214) > > > > Someone with ELF knowledge should look at this. I'm a bit nervous > about removing the conditional as it seems to imply that there's an > different relocation that should be generated depending on the variant > kind. > > > > -Jim > > > > On Dec 20, 2011, at 5:43 AM, Kristof Beyls wrote: > > > >> Hi, > >> > >> Please find a patch for fixing incorrect generation of relocation > >> information on Thumb function calls. > >> This should fix quite a few incorrect code generation problems in > Thumb mode > >> when using the integrated assembler. > >> I believe this fixes PR11214 > >> (http://www.llvm.org/bugs/show_bug.cgi?id=11214). > >> > >> Is this OK? > >> > >> Thanks, > >> > >> Kristof > >> > ____________________________________________ > ___ > >> llvm-commits mailing list > >> llvm-commits at cs.uiuc.edu > >> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits > > > > _______________________________________________ > > llvm-commits mailing list > > llvm-commits at cs.uiuc.edu > > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits > > > > > > -- IMPORTANT NOTICE: The contents of this email and any attachments > are confidential and may also be privileged. If you are not the > intended recipient, please notify the sender immediately and do not > disclose the contents to any other person, use it for any purpose, or > store or copy the information in any medium. Thank you. > > > > -- IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you. From kubastaszak at gmail.com Tue Dec 20 14:03:11 2011 From: kubastaszak at gmail.com (Jakub Staszak) Date: Tue, 20 Dec 2011 20:03:11 -0000 Subject: [llvm-commits] [llvm] r146986 - in /llvm/trunk: include/llvm/Analysis/ include/llvm/CodeGen/ lib/Analysis/ lib/CodeGen/ lib/CodeGen/SelectionDAG/ Message-ID: <20111220200311.347CC2A6C12C@llvm.org> Author: kuba Date: Tue Dec 20 14:03:10 2011 New Revision: 146986 URL: http://llvm.org/viewvc/llvm-project?rev=146986&view=rev Log: Add some constantness to BranchProbabilityInfo and BlockFrequnencyInfo. Modified: llvm/trunk/include/llvm/Analysis/BlockFrequencyImpl.h llvm/trunk/include/llvm/Analysis/BlockFrequencyInfo.h llvm/trunk/include/llvm/CodeGen/MachineBasicBlock.h llvm/trunk/include/llvm/CodeGen/MachineBlockFrequencyInfo.h llvm/trunk/include/llvm/CodeGen/MachineBranchProbabilityInfo.h llvm/trunk/lib/Analysis/BlockFrequencyInfo.cpp llvm/trunk/lib/CodeGen/MachineBasicBlock.cpp llvm/trunk/lib/CodeGen/MachineBlockFrequencyInfo.cpp llvm/trunk/lib/CodeGen/MachineBranchProbabilityInfo.cpp llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.h Modified: llvm/trunk/include/llvm/Analysis/BlockFrequencyImpl.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Analysis/BlockFrequencyImpl.h?rev=146986&r1=146985&r2=146986&view=diff ============================================================================== --- llvm/trunk/include/llvm/Analysis/BlockFrequencyImpl.h (original) +++ llvm/trunk/include/llvm/Analysis/BlockFrequencyImpl.h Tue Dec 20 14:03:10 2011 @@ -40,7 +40,7 @@ template class BlockFrequencyImpl { - DenseMap Freqs; + DenseMap Freqs; BlockProbInfoT *BPI; @@ -308,8 +308,9 @@ public: /// getBlockFreq - Return block frequency. Return 0 if we don't have it. - BlockFrequency getBlockFreq(BlockT *BB) const { - typename DenseMap::const_iterator I = Freqs.find(BB); + BlockFrequency getBlockFreq(const BlockT *BB) const { + typename DenseMap::const_iterator + I = Freqs.find(BB); if (I != Freqs.end()) return I->second; return 0; Modified: llvm/trunk/include/llvm/Analysis/BlockFrequencyInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Analysis/BlockFrequencyInfo.h?rev=146986&r1=146985&r2=146986&view=diff ============================================================================== --- llvm/trunk/include/llvm/Analysis/BlockFrequencyInfo.h (original) +++ llvm/trunk/include/llvm/Analysis/BlockFrequencyInfo.h Tue Dec 20 14:03:10 2011 @@ -47,7 +47,7 @@ /// that we should not rely on the value itself, but only on the comparison to /// the other block frequencies. We do this to avoid using of floating points. /// - BlockFrequency getBlockFreq(BasicBlock *BB) const; + BlockFrequency getBlockFreq(const BasicBlock *BB) const; }; } Modified: llvm/trunk/include/llvm/CodeGen/MachineBasicBlock.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/MachineBasicBlock.h?rev=146986&r1=146985&r2=146986&view=diff ============================================================================== --- llvm/trunk/include/llvm/CodeGen/MachineBasicBlock.h (original) +++ llvm/trunk/include/llvm/CodeGen/MachineBasicBlock.h Tue Dec 20 14:03:10 2011 @@ -77,6 +77,7 @@ /// (disable optimization). std::vector Weights; typedef std::vector::iterator weight_iterator; + typedef std::vector::const_iterator const_weight_iterator; /// LiveIns - Keep track of the physical registers that are livein of /// the basicblock. @@ -589,13 +590,14 @@ /// getWeightIterator - Return weight iterator corresponding to the I /// successor iterator. weight_iterator getWeightIterator(succ_iterator I); + const_weight_iterator getWeightIterator(const_succ_iterator I) const; friend class MachineBranchProbabilityInfo; /// getSuccWeight - Return weight of the edge from this block to MBB. This /// method should NOT be called directly, but by using getEdgeWeight method /// from MachineBranchProbabilityInfo class. - uint32_t getSuccWeight(MachineBasicBlock *succ); + uint32_t getSuccWeight(const MachineBasicBlock *succ) const; // Methods used to maintain doubly linked list of blocks... Modified: llvm/trunk/include/llvm/CodeGen/MachineBlockFrequencyInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/MachineBlockFrequencyInfo.h?rev=146986&r1=146985&r2=146986&view=diff ============================================================================== --- llvm/trunk/include/llvm/CodeGen/MachineBlockFrequencyInfo.h (original) +++ llvm/trunk/include/llvm/CodeGen/MachineBlockFrequencyInfo.h Tue Dec 20 14:03:10 2011 @@ -48,7 +48,7 @@ /// that we should not rely on the value itself, but only on the comparison to /// the other block frequencies. We do this to avoid using of floating points. /// - BlockFrequency getBlockFreq(MachineBasicBlock *MBB) const; + BlockFrequency getBlockFreq(const MachineBasicBlock *MBB) const; }; } Modified: llvm/trunk/include/llvm/CodeGen/MachineBranchProbabilityInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/MachineBranchProbabilityInfo.h?rev=146986&r1=146985&r2=146986&view=diff ============================================================================== --- llvm/trunk/include/llvm/CodeGen/MachineBranchProbabilityInfo.h (original) +++ llvm/trunk/include/llvm/CodeGen/MachineBranchProbabilityInfo.h Tue Dec 20 14:03:10 2011 @@ -49,12 +49,13 @@ // Return edge weight. If we don't have any informations about it - return // DEFAULT_WEIGHT. - uint32_t getEdgeWeight(MachineBasicBlock *Src, MachineBasicBlock *Dst) const; + uint32_t getEdgeWeight(const MachineBasicBlock *Src, + const MachineBasicBlock *Dst) const; // Get sum of the block successors' weights, potentially scaling them to fit // within 32-bits. If scaling is required, sets Scale based on the necessary // adjustment. Any edge weights used with the sum should be divided by Scale. - uint32_t getSumForBlock(MachineBasicBlock *MBB, uint32_t &Scale) const; + uint32_t getSumForBlock(const MachineBasicBlock *MBB, uint32_t &Scale) const; // A 'Hot' edge is an edge which probability is >= 80%. bool isEdgeHot(MachineBasicBlock *Src, MachineBasicBlock *Dst) const; Modified: llvm/trunk/lib/Analysis/BlockFrequencyInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/BlockFrequencyInfo.cpp?rev=146986&r1=146985&r2=146986&view=diff ============================================================================== --- llvm/trunk/lib/Analysis/BlockFrequencyInfo.cpp (original) +++ llvm/trunk/lib/Analysis/BlockFrequencyInfo.cpp Tue Dec 20 14:03:10 2011 @@ -58,6 +58,6 @@ /// that we should not rely on the value itself, but only on the comparison to /// the other block frequencies. We do this to avoid using of floating points. /// -BlockFrequency BlockFrequencyInfo::getBlockFreq(BasicBlock *BB) const { +BlockFrequency BlockFrequencyInfo::getBlockFreq(const BasicBlock *BB) const { return BFI->getBlockFreq(BB); } Modified: llvm/trunk/lib/CodeGen/MachineBasicBlock.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineBasicBlock.cpp?rev=146986&r1=146985&r2=146986&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/MachineBasicBlock.cpp (original) +++ llvm/trunk/lib/CodeGen/MachineBasicBlock.cpp Tue Dec 20 14:03:10 2011 @@ -870,11 +870,11 @@ /// getSuccWeight - Return weight of the edge from this block to MBB. /// -uint32_t MachineBasicBlock::getSuccWeight(MachineBasicBlock *succ) { +uint32_t MachineBasicBlock::getSuccWeight(const MachineBasicBlock *succ) const { if (Weights.empty()) return 0; - succ_iterator I = std::find(Successors.begin(), Successors.end(), succ); + const_succ_iterator I = std::find(Successors.begin(), Successors.end(), succ); return *getWeightIterator(I); } @@ -888,6 +888,16 @@ return Weights.begin() + index; } +/// getWeightIterator - Return wight iterator corresonding to the I successor +/// iterator +MachineBasicBlock::const_weight_iterator MachineBasicBlock:: +getWeightIterator(MachineBasicBlock::const_succ_iterator I) const { + assert(Weights.size() == Successors.size() && "Async weight list!"); + const size_t index = std::distance(Successors.begin(), I); + assert(index < Weights.size() && "Not a current successor!"); + return Weights.begin() + index; +} + void llvm::WriteAsOperand(raw_ostream &OS, const MachineBasicBlock *MBB, bool t) { OS << "BB#" << MBB->getNumber(); Modified: llvm/trunk/lib/CodeGen/MachineBlockFrequencyInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineBlockFrequencyInfo.cpp?rev=146986&r1=146985&r2=146986&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/MachineBlockFrequencyInfo.cpp (original) +++ llvm/trunk/lib/CodeGen/MachineBlockFrequencyInfo.cpp Tue Dec 20 14:03:10 2011 @@ -56,6 +56,6 @@ /// the other block frequencies. We do this to avoid using of floating points. /// BlockFrequency MachineBlockFrequencyInfo:: -getBlockFreq(MachineBasicBlock *MBB) const { +getBlockFreq(const MachineBasicBlock *MBB) const { return MBFI->getBlockFreq(MBB); } Modified: llvm/trunk/lib/CodeGen/MachineBranchProbabilityInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineBranchProbabilityInfo.cpp?rev=146986&r1=146985&r2=146986&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/MachineBranchProbabilityInfo.cpp (original) +++ llvm/trunk/lib/CodeGen/MachineBranchProbabilityInfo.cpp Tue Dec 20 14:03:10 2011 @@ -29,7 +29,7 @@ void MachineBranchProbabilityInfo::anchor() { } uint32_t MachineBranchProbabilityInfo:: -getSumForBlock(MachineBasicBlock *MBB, uint32_t &Scale) const { +getSumForBlock(const MachineBasicBlock *MBB, uint32_t &Scale) const { // First we compute the sum with 64-bits of precision, ensuring that cannot // overflow by bounding the number of weights considered. Hopefully no one // actually needs 2^32 successors. @@ -61,8 +61,8 @@ } uint32_t -MachineBranchProbabilityInfo::getEdgeWeight(MachineBasicBlock *Src, - MachineBasicBlock *Dst) const { +MachineBranchProbabilityInfo::getEdgeWeight(const MachineBasicBlock *Src, + const MachineBasicBlock *Dst) const { uint32_t Weight = Src->getSuccWeight(Dst); if (!Weight) return DEFAULT_WEIGHT; Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp?rev=146986&r1=146985&r2=146986&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp Tue Dec 20 14:03:10 2011 @@ -1287,8 +1287,8 @@ } /// Return branch probability calculated by BranchProbabilityInfo for IR blocks. -uint32_t SelectionDAGBuilder::getEdgeWeight(MachineBasicBlock *Src, - MachineBasicBlock *Dst) { +uint32_t SelectionDAGBuilder::getEdgeWeight(const MachineBasicBlock *Src, + const MachineBasicBlock *Dst) const { BranchProbabilityInfo *BPI = FuncInfo.BPI; if (!BPI) return 0; Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.h?rev=146986&r1=146985&r2=146986&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.h (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.h Tue Dec 20 14:03:10 2011 @@ -454,7 +454,8 @@ MachineBasicBlock* Default, MachineBasicBlock *SwitchBB); - uint32_t getEdgeWeight(MachineBasicBlock *Src, MachineBasicBlock *Dst); + uint32_t getEdgeWeight(const MachineBasicBlock *Src, + const MachineBasicBlock *Dst) const; void addSuccessorWithWeight(MachineBasicBlock *Src, MachineBasicBlock *Dst, uint32_t Weight = 0); public: From hfinkel at anl.gov Tue Dec 20 14:08:56 2011 From: hfinkel at anl.gov (Hal Finkel) Date: Tue, 20 Dec 2011 14:08:56 -0600 Subject: [llvm-commits] [LLVMdev] [PATCH] BasicBlock Autovectorization Pass In-Reply-To: References: <1319909412.23036.851.camel@sapling> <1319914924.23036.852.camel@sapling> <1319919418.23036.881.camel@sapling> <1319928991.23036.957.camel@sapling> <1320108633.23036.1266.camel@sapling> <1320172356.23036.1298.camel@sapling> <4EB0462C.5010209@grosser.es> <1320184739.23036.1334.camel@sapling> <1320191694.23036.1497.camel@sapling> <1320749109.19359.76.camel@sapling> <4EB90E98.4010805@grosser.es> <1320762963.19359.117.camel@sapling> <4EB98207.2070807@grosser.es> <1320791390.19359.262.camel@sapling> <4EBC4B0F.6010609@grosser.es> <1321050998.19359.539.camel@sapling> <4EBDA7F9.9080709@grosser.es> <1321053083.19359.550.camel@sapling> <4EBDB1BF.7090006@grosser.es> <1321400339.19359.782.camel@sapling> <1321486739.19359.1067.camel@sapling> <4EC504B5.2020408@grosser.es> <1321898108.2507.36.camel@sapling> <1321932161.2507.101.camel@sapling> <1322067157.2507.263.camel@sapling> <4ED8F7B0.8050309@grosser.es> <1323822351.590.1687.camel@sapling> Message-ID: <1324411736.31367.485.camel@sapling> On Tue, 2011-12-20 at 13:57 -0600, Sebastian Pop wrote: > Hi, > > I see that there are two functions in your code that are O(n^2) in > number of instructions of the program: getCandidatePairs and > buildDepMap. I think that you could make these two functions faster > if you work on some form of factored def-use chains for memory, like > the VUSE/VDEFs of GCC. Thanks for the comment! I am not aware of anything along these lines, although it would be quite helpful. The pass spends a significant amount of time running the aliasing-analysis queries. -Hal > > I was trying to find a similar representation in LLVM: isn't there already > a virtual SSA representation for memory references in LLVM? > > Thanks, > Sebastian > -- > Qualcomm Innovation Center, Inc is a member of Code Aurora Forum -- Hal Finkel Postdoctoral Appointee Leadership Computing Facility Argonne National Laboratory From lhames at gmail.com Tue Dec 20 14:23:40 2011 From: lhames at gmail.com (Lang Hames) Date: Tue, 20 Dec 2011 20:23:40 -0000 Subject: [llvm-commits] [llvm] r146987 - /llvm/trunk/lib/CodeGen/LiveRangeCalc.cpp Message-ID: <20111220202340.5C4862A6C12C@llvm.org> Author: lhames Date: Tue Dec 20 14:23:40 2011 New Revision: 146987 URL: http://llvm.org/viewvc/llvm-project?rev=146987&view=rev Log: Fix assert condition. Modified: llvm/trunk/lib/CodeGen/LiveRangeCalc.cpp Modified: llvm/trunk/lib/CodeGen/LiveRangeCalc.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/LiveRangeCalc.cpp?rev=146987&r1=146986&r2=146987&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/LiveRangeCalc.cpp (original) +++ llvm/trunk/lib/CodeGen/LiveRangeCalc.cpp Tue Dec 20 14:23:40 2011 @@ -65,7 +65,7 @@ assert(DomTree && "Missing dominator tree"); MachineBasicBlock *KillMBB = Indexes->getMBBFromIndex(Kill.getPrevSlot()); - assert(Kill && "No MBB at Kill"); + assert(KillMBB && "No MBB at Kill"); // Is there a def in the same MBB we can extend? if (LI->extendInBlock(Indexes->getMBBStartIdx(KillMBB), Kill)) From grosbach at apple.com Tue Dec 20 14:46:29 2011 From: grosbach at apple.com (Jim Grosbach) Date: Tue, 20 Dec 2011 20:46:29 -0000 Subject: [llvm-commits] [llvm] r146990 - in /llvm/trunk: lib/Target/ARM/ARMInstrNEON.td lib/Target/ARM/AsmParser/ARMAsmParser.cpp test/MC/ARM/neon-vst-encoding.s Message-ID: <20111220204629.DE1E02A6C12C@llvm.org> Author: grosbach Date: Tue Dec 20 14:46:29 2011 New Revision: 146990 URL: http://llvm.org/viewvc/llvm-project?rev=146990&view=rev Log: ARM assembly parsing and encoding for VST2 single-element, double spaced. Modified: llvm/trunk/lib/Target/ARM/ARMInstrNEON.td llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp llvm/trunk/test/MC/ARM/neon-vst-encoding.s Modified: llvm/trunk/lib/Target/ARM/ARMInstrNEON.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrNEON.td?rev=146990&r1=146989&r2=146990&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrNEON.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrNEON.td Tue Dec 20 14:46:29 2011 @@ -5800,6 +5800,10 @@ (ins VecListTwoDHWordIndexed:$list, addrmode6:$addr, pred:$p)>; defm VST2LNdAsm : NEONDT32AsmPseudoInst<"vst2${p}", "$list, $addr", (ins VecListTwoDWordIndexed:$list, addrmode6:$addr, pred:$p)>; +defm VST2LNqAsm : NEONDT16AsmPseudoInst<"vst2${p}", "$list, $addr", + (ins VecListTwoQHWordIndexed:$list, addrmode6:$addr, pred:$p)>; +defm VST2LNqAsm : NEONDT32AsmPseudoInst<"vst2${p}", "$list, $addr", + (ins VecListTwoQWordIndexed:$list, addrmode6:$addr, pred:$p)>; defm VST2LNdWB_fixed_Asm : NEONDT8AsmPseudoInst<"vst2${p}", "$list, $addr!", (ins VecListTwoDByteIndexed:$list, addrmode6:$addr, pred:$p)>; @@ -5807,6 +5811,10 @@ (ins VecListTwoDHWordIndexed:$list, addrmode6:$addr, pred:$p)>; defm VST2LNdWB_fixed_Asm : NEONDT32AsmPseudoInst<"vst2${p}", "$list, $addr!", (ins VecListTwoDWordIndexed:$list, addrmode6:$addr, pred:$p)>; +defm VST2LNqWB_fixed_Asm : NEONDT16AsmPseudoInst<"vst2${p}", "$list, $addr!", + (ins VecListTwoQHWordIndexed:$list, addrmode6:$addr, pred:$p)>; +defm VST2LNqWB_fixed_Asm : NEONDT32AsmPseudoInst<"vst2${p}", "$list, $addr!", + (ins VecListTwoQWordIndexed:$list, addrmode6:$addr, pred:$p)>; defm VST2LNdWB_register_Asm : NEONDT8AsmPseudoInst<"vst2${p}", "$list, $addr, $Rm", (ins VecListTwoDByteIndexed:$list, addrmode6:$addr, @@ -5819,6 +5827,14 @@ NEONDT32AsmPseudoInst<"vst2${p}", "$list, $addr, $Rm", (ins VecListTwoDWordIndexed:$list, addrmode6:$addr, rGPR:$Rm, pred:$p)>; +defm VST2LNqWB_register_Asm : + NEONDT16AsmPseudoInst<"vst2${p}", "$list, $addr, $Rm", + (ins VecListTwoQHWordIndexed:$list, addrmode6:$addr, + rGPR:$Rm, pred:$p)>; +defm VST2LNqWB_register_Asm : + NEONDT32AsmPseudoInst<"vst2${p}", "$list, $addr, $Rm", + (ins VecListTwoQWordIndexed:$list, addrmode6:$addr, + rGPR:$Rm, pred:$p)>; // VMOV takes an optional datatype suffix defm : VFPDTAnyInstAlias<"vmov${p}", "$Vd, $Vm", Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp?rev=146990&r1=146989&r2=146990&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp (original) +++ llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Tue Dec 20 14:46:29 2011 @@ -5118,84 +5118,134 @@ return false; } -static unsigned getRealVSTLNOpcode(unsigned Opc) { +static unsigned getRealVSTLNOpcode(unsigned Opc, unsigned &Spacing) { switch(Opc) { default: assert(0 && "unexpected opcode!"); // VST1LN case ARM::VST1LNdWB_fixed_Asm_8: case ARM::VST1LNdWB_fixed_Asm_P8: case ARM::VST1LNdWB_fixed_Asm_I8: case ARM::VST1LNdWB_fixed_Asm_S8: case ARM::VST1LNdWB_fixed_Asm_U8: + Spacing = 1; return ARM::VST1LNd8_UPD; case ARM::VST1LNdWB_fixed_Asm_16: case ARM::VST1LNdWB_fixed_Asm_P16: case ARM::VST1LNdWB_fixed_Asm_I16: case ARM::VST1LNdWB_fixed_Asm_S16: case ARM::VST1LNdWB_fixed_Asm_U16: + Spacing = 1; return ARM::VST1LNd16_UPD; case ARM::VST1LNdWB_fixed_Asm_32: case ARM::VST1LNdWB_fixed_Asm_F: case ARM::VST1LNdWB_fixed_Asm_F32: case ARM::VST1LNdWB_fixed_Asm_I32: case ARM::VST1LNdWB_fixed_Asm_S32: case ARM::VST1LNdWB_fixed_Asm_U32: + Spacing = 1; return ARM::VST1LNd32_UPD; case ARM::VST1LNdWB_register_Asm_8: case ARM::VST1LNdWB_register_Asm_P8: case ARM::VST1LNdWB_register_Asm_I8: case ARM::VST1LNdWB_register_Asm_S8: case ARM::VST1LNdWB_register_Asm_U8: + Spacing = 1; return ARM::VST1LNd8_UPD; case ARM::VST1LNdWB_register_Asm_16: case ARM::VST1LNdWB_register_Asm_P16: case ARM::VST1LNdWB_register_Asm_I16: case ARM::VST1LNdWB_register_Asm_S16: case ARM::VST1LNdWB_register_Asm_U16: + Spacing = 1; return ARM::VST1LNd16_UPD; case ARM::VST1LNdWB_register_Asm_32: case ARM::VST1LNdWB_register_Asm_F: case ARM::VST1LNdWB_register_Asm_F32: case ARM::VST1LNdWB_register_Asm_I32: case ARM::VST1LNdWB_register_Asm_S32: case ARM::VST1LNdWB_register_Asm_U32: + Spacing = 1; return ARM::VST1LNd32_UPD; case ARM::VST1LNdAsm_8: case ARM::VST1LNdAsm_P8: case ARM::VST1LNdAsm_I8: case ARM::VST1LNdAsm_S8: case ARM::VST1LNdAsm_U8: + Spacing = 1; return ARM::VST1LNd8; case ARM::VST1LNdAsm_16: case ARM::VST1LNdAsm_P16: case ARM::VST1LNdAsm_I16: case ARM::VST1LNdAsm_S16: case ARM::VST1LNdAsm_U16: + Spacing = 1; return ARM::VST1LNd16; case ARM::VST1LNdAsm_32: case ARM::VST1LNdAsm_F: case ARM::VST1LNdAsm_F32: case ARM::VST1LNdAsm_I32: case ARM::VST1LNdAsm_S32: case ARM::VST1LNdAsm_U32: + Spacing = 1; return ARM::VST1LNd32; // VST2LN case ARM::VST2LNdWB_fixed_Asm_8: case ARM::VST2LNdWB_fixed_Asm_P8: case ARM::VST2LNdWB_fixed_Asm_I8: case ARM::VST2LNdWB_fixed_Asm_S8: case ARM::VST2LNdWB_fixed_Asm_U8: + Spacing = 1; return ARM::VST2LNd8_UPD; case ARM::VST2LNdWB_fixed_Asm_16: case ARM::VST2LNdWB_fixed_Asm_P16: case ARM::VST2LNdWB_fixed_Asm_I16: case ARM::VST2LNdWB_fixed_Asm_S16: case ARM::VST2LNdWB_fixed_Asm_U16: + Spacing = 1; return ARM::VST2LNd16_UPD; case ARM::VST2LNdWB_fixed_Asm_32: case ARM::VST2LNdWB_fixed_Asm_F: case ARM::VST2LNdWB_fixed_Asm_F32: case ARM::VST2LNdWB_fixed_Asm_I32: case ARM::VST2LNdWB_fixed_Asm_S32: case ARM::VST2LNdWB_fixed_Asm_U32: + Spacing = 1; return ARM::VST2LNd32_UPD; + case ARM::VST2LNqWB_fixed_Asm_16: case ARM::VST2LNqWB_fixed_Asm_P16: + case ARM::VST2LNqWB_fixed_Asm_I16: case ARM::VST2LNqWB_fixed_Asm_S16: + case ARM::VST2LNqWB_fixed_Asm_U16: + Spacing = 2; + return ARM::VST2LNq16_UPD; + case ARM::VST2LNqWB_fixed_Asm_32: case ARM::VST2LNqWB_fixed_Asm_F: + case ARM::VST2LNqWB_fixed_Asm_F32: case ARM::VST2LNqWB_fixed_Asm_I32: + case ARM::VST2LNqWB_fixed_Asm_S32: case ARM::VST2LNqWB_fixed_Asm_U32: + Spacing = 2; + return ARM::VST2LNq32_UPD; + case ARM::VST2LNdWB_register_Asm_8: case ARM::VST2LNdWB_register_Asm_P8: case ARM::VST2LNdWB_register_Asm_I8: case ARM::VST2LNdWB_register_Asm_S8: case ARM::VST2LNdWB_register_Asm_U8: + Spacing = 1; return ARM::VST2LNd8_UPD; case ARM::VST2LNdWB_register_Asm_16: case ARM::VST2LNdWB_register_Asm_P16: case ARM::VST2LNdWB_register_Asm_I16: case ARM::VST2LNdWB_register_Asm_S16: case ARM::VST2LNdWB_register_Asm_U16: + Spacing = 1; return ARM::VST2LNd16_UPD; case ARM::VST2LNdWB_register_Asm_32: case ARM::VST2LNdWB_register_Asm_F: case ARM::VST2LNdWB_register_Asm_F32: case ARM::VST2LNdWB_register_Asm_I32: case ARM::VST2LNdWB_register_Asm_S32: case ARM::VST2LNdWB_register_Asm_U32: + Spacing = 1; return ARM::VST2LNd32_UPD; + case ARM::VST2LNqWB_register_Asm_16: case ARM::VST2LNqWB_register_Asm_P16: + case ARM::VST2LNqWB_register_Asm_I16: case ARM::VST2LNqWB_register_Asm_S16: + case ARM::VST2LNqWB_register_Asm_U16: + Spacing = 2; + return ARM::VST2LNq16_UPD; + case ARM::VST2LNqWB_register_Asm_32: case ARM::VST2LNqWB_register_Asm_F: + case ARM::VST2LNqWB_register_Asm_F32: case ARM::VST2LNqWB_register_Asm_I32: + case ARM::VST2LNqWB_register_Asm_S32: case ARM::VST2LNqWB_register_Asm_U32: + Spacing = 2; + return ARM::VST2LNq32_UPD; + case ARM::VST2LNdAsm_8: case ARM::VST2LNdAsm_P8: case ARM::VST2LNdAsm_I8: case ARM::VST2LNdAsm_S8: case ARM::VST2LNdAsm_U8: + Spacing = 1; return ARM::VST2LNd8; case ARM::VST2LNdAsm_16: case ARM::VST2LNdAsm_P16: case ARM::VST2LNdAsm_I16: case ARM::VST2LNdAsm_S16: case ARM::VST2LNdAsm_U16: + Spacing = 1; return ARM::VST2LNd16; case ARM::VST2LNdAsm_32: case ARM::VST2LNdAsm_F: case ARM::VST2LNdAsm_F32: case ARM::VST2LNdAsm_I32: case ARM::VST2LNdAsm_S32: case ARM::VST2LNdAsm_U32: + Spacing = 1; return ARM::VST2LNd32; + case ARM::VST2LNqAsm_16: case ARM::VST2LNqAsm_P16: + case ARM::VST2LNqAsm_I16: case ARM::VST2LNqAsm_S16: + case ARM::VST2LNqAsm_U16: + Spacing = 2; + return ARM::VST2LNq16; + case ARM::VST2LNqAsm_32: case ARM::VST2LNqAsm_F: + case ARM::VST2LNqAsm_F32: case ARM::VST2LNqAsm_I32: + case ARM::VST2LNqAsm_S32: case ARM::VST2LNqAsm_U32: + Spacing = 2; + return ARM::VST2LNq32; } } @@ -5344,7 +5394,8 @@ MCInst TmpInst; // Shuffle the operands around so the lane index operand is in the // right place. - TmpInst.setOpcode(getRealVSTLNOpcode(Inst.getOpcode())); + unsigned Spacing; + TmpInst.setOpcode(getRealVSTLNOpcode(Inst.getOpcode(), Spacing)); TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb TmpInst.addOperand(Inst.getOperand(2)); // Rn TmpInst.addOperand(Inst.getOperand(3)); // alignment @@ -5357,24 +5408,32 @@ return true; } - case ARM::VST2LNdWB_register_Asm_8: case ARM::VST2LNdWB_register_Asm_P8: - case ARM::VST2LNdWB_register_Asm_I8: case ARM::VST2LNdWB_register_Asm_S8: - case ARM::VST2LNdWB_register_Asm_U8: case ARM::VST2LNdWB_register_Asm_16: + case ARM::VST2LNdWB_register_Asm_8: case ARM::VST2LNdWB_register_Asm_P8: + case ARM::VST2LNdWB_register_Asm_I8: case ARM::VST2LNdWB_register_Asm_S8: + case ARM::VST2LNdWB_register_Asm_U8: case ARM::VST2LNdWB_register_Asm_16: case ARM::VST2LNdWB_register_Asm_P16: case ARM::VST2LNdWB_register_Asm_I16: case ARM::VST2LNdWB_register_Asm_S16: case ARM::VST2LNdWB_register_Asm_U16: - case ARM::VST2LNdWB_register_Asm_32: case ARM::VST2LNdWB_register_Asm_F: + case ARM::VST2LNdWB_register_Asm_32: case ARM::VST2LNdWB_register_Asm_F: case ARM::VST2LNdWB_register_Asm_F32: case ARM::VST2LNdWB_register_Asm_I32: - case ARM::VST2LNdWB_register_Asm_S32: case ARM::VST2LNdWB_register_Asm_U32: { + case ARM::VST2LNdWB_register_Asm_S32: case ARM::VST2LNdWB_register_Asm_U32: + case ARM::VST2LNqWB_register_Asm_16: case ARM::VST2LNqWB_register_Asm_P16: + case ARM::VST2LNqWB_register_Asm_I16: case ARM::VST2LNqWB_register_Asm_S16: + case ARM::VST2LNqWB_register_Asm_U16: case ARM::VST2LNqWB_register_Asm_32: + case ARM::VST2LNqWB_register_Asm_F: case ARM::VST2LNqWB_register_Asm_F32: + case ARM::VST2LNqWB_register_Asm_I32: case ARM::VST2LNqWB_register_Asm_S32: + case ARM::VST2LNqWB_register_Asm_U32: { MCInst TmpInst; // Shuffle the operands around so the lane index operand is in the // right place. - TmpInst.setOpcode(getRealVSTLNOpcode(Inst.getOpcode())); + unsigned Spacing; + TmpInst.setOpcode(getRealVSTLNOpcode(Inst.getOpcode(), Spacing)); TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb TmpInst.addOperand(Inst.getOperand(2)); // Rn TmpInst.addOperand(Inst.getOperand(3)); // alignment TmpInst.addOperand(Inst.getOperand(4)); // Rm TmpInst.addOperand(Inst.getOperand(0)); // Vd - TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg()+1)); + TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + + Spacing)); TmpInst.addOperand(Inst.getOperand(1)); // lane TmpInst.addOperand(Inst.getOperand(5)); // CondCode TmpInst.addOperand(Inst.getOperand(6)); @@ -5392,7 +5451,8 @@ MCInst TmpInst; // Shuffle the operands around so the lane index operand is in the // right place. - TmpInst.setOpcode(getRealVSTLNOpcode(Inst.getOpcode())); + unsigned Spacing; + TmpInst.setOpcode(getRealVSTLNOpcode(Inst.getOpcode(), Spacing)); TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb TmpInst.addOperand(Inst.getOperand(2)); // Rn TmpInst.addOperand(Inst.getOperand(3)); // alignment @@ -5405,24 +5465,32 @@ return true; } - case ARM::VST2LNdWB_fixed_Asm_8: case ARM::VST2LNdWB_fixed_Asm_P8: - case ARM::VST2LNdWB_fixed_Asm_I8: case ARM::VST2LNdWB_fixed_Asm_S8: - case ARM::VST2LNdWB_fixed_Asm_U8: case ARM::VST2LNdWB_fixed_Asm_16: + case ARM::VST2LNdWB_fixed_Asm_8: case ARM::VST2LNdWB_fixed_Asm_P8: + case ARM::VST2LNdWB_fixed_Asm_I8: case ARM::VST2LNdWB_fixed_Asm_S8: + case ARM::VST2LNdWB_fixed_Asm_U8: case ARM::VST2LNdWB_fixed_Asm_16: case ARM::VST2LNdWB_fixed_Asm_P16: case ARM::VST2LNdWB_fixed_Asm_I16: case ARM::VST2LNdWB_fixed_Asm_S16: case ARM::VST2LNdWB_fixed_Asm_U16: - case ARM::VST2LNdWB_fixed_Asm_32: case ARM::VST2LNdWB_fixed_Asm_F: + case ARM::VST2LNdWB_fixed_Asm_32: case ARM::VST2LNdWB_fixed_Asm_F: case ARM::VST2LNdWB_fixed_Asm_F32: case ARM::VST2LNdWB_fixed_Asm_I32: - case ARM::VST2LNdWB_fixed_Asm_S32: case ARM::VST2LNdWB_fixed_Asm_U32: { + case ARM::VST2LNdWB_fixed_Asm_S32: case ARM::VST2LNdWB_fixed_Asm_U32: + case ARM::VST2LNqWB_fixed_Asm_16: case ARM::VST2LNqWB_fixed_Asm_P16: + case ARM::VST2LNqWB_fixed_Asm_I16: case ARM::VST2LNqWB_fixed_Asm_S16: + case ARM::VST2LNqWB_fixed_Asm_U16: case ARM::VST2LNqWB_fixed_Asm_32: + case ARM::VST2LNqWB_fixed_Asm_F: case ARM::VST2LNqWB_fixed_Asm_F32: + case ARM::VST2LNqWB_fixed_Asm_I32: case ARM::VST2LNqWB_fixed_Asm_S32: + case ARM::VST2LNqWB_fixed_Asm_U32: { MCInst TmpInst; // Shuffle the operands around so the lane index operand is in the // right place. - TmpInst.setOpcode(getRealVSTLNOpcode(Inst.getOpcode())); + unsigned Spacing; + TmpInst.setOpcode(getRealVSTLNOpcode(Inst.getOpcode(), Spacing)); TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb TmpInst.addOperand(Inst.getOperand(2)); // Rn TmpInst.addOperand(Inst.getOperand(3)); // alignment TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm TmpInst.addOperand(Inst.getOperand(0)); // Vd - TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg()+1)); + TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + + Spacing)); TmpInst.addOperand(Inst.getOperand(1)); // lane TmpInst.addOperand(Inst.getOperand(4)); // CondCode TmpInst.addOperand(Inst.getOperand(5)); @@ -5438,7 +5506,8 @@ MCInst TmpInst; // Shuffle the operands around so the lane index operand is in the // right place. - TmpInst.setOpcode(getRealVSTLNOpcode(Inst.getOpcode())); + unsigned Spacing; + TmpInst.setOpcode(getRealVSTLNOpcode(Inst.getOpcode(), Spacing)); TmpInst.addOperand(Inst.getOperand(2)); // Rn TmpInst.addOperand(Inst.getOperand(3)); // alignment TmpInst.addOperand(Inst.getOperand(0)); // Vd @@ -5449,20 +5518,25 @@ return true; } - case ARM::VST2LNdAsm_8: case ARM::VST2LNdAsm_P8: case ARM::VST2LNdAsm_I8: - case ARM::VST2LNdAsm_S8: case ARM::VST2LNdAsm_U8: case ARM::VST2LNdAsm_16: + case ARM::VST2LNdAsm_8: case ARM::VST2LNdAsm_P8: case ARM::VST2LNdAsm_I8: + case ARM::VST2LNdAsm_S8: case ARM::VST2LNdAsm_U8: case ARM::VST2LNdAsm_16: case ARM::VST2LNdAsm_P16: case ARM::VST2LNdAsm_I16: case ARM::VST2LNdAsm_S16: - case ARM::VST2LNdAsm_U16: case ARM::VST2LNdAsm_32: case ARM::VST2LNdAsm_F: + case ARM::VST2LNdAsm_U16: case ARM::VST2LNdAsm_32: case ARM::VST2LNdAsm_F: case ARM::VST2LNdAsm_F32: case ARM::VST2LNdAsm_I32: case ARM::VST2LNdAsm_S32: - case ARM::VST2LNdAsm_U32: { + case ARM::VST2LNdAsm_U32: case ARM::VST2LNqAsm_16: case ARM::VST2LNqAsm_P16: + case ARM::VST2LNqAsm_I16: case ARM::VST2LNqAsm_S16: case ARM::VST2LNqAsm_U16: + case ARM::VST2LNqAsm_32: case ARM::VST2LNqAsm_F: case ARM::VST2LNqAsm_F32: + case ARM::VST2LNqAsm_I32: case ARM::VST2LNqAsm_S32: case ARM::VST2LNqAsm_U32:{ MCInst TmpInst; // Shuffle the operands around so the lane index operand is in the // right place. - TmpInst.setOpcode(getRealVSTLNOpcode(Inst.getOpcode())); + unsigned Spacing; + TmpInst.setOpcode(getRealVSTLNOpcode(Inst.getOpcode(), Spacing)); TmpInst.addOperand(Inst.getOperand(2)); // Rn TmpInst.addOperand(Inst.getOperand(3)); // alignment TmpInst.addOperand(Inst.getOperand(0)); // Vd - TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg()+1)); + TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + + Spacing)); TmpInst.addOperand(Inst.getOperand(1)); // lane TmpInst.addOperand(Inst.getOperand(4)); // CondCode TmpInst.addOperand(Inst.getOperand(5)); @@ -5504,11 +5578,12 @@ case ARM::VLD2LNdWB_register_Asm_32: case ARM::VLD2LNdWB_register_Asm_F: case ARM::VLD2LNdWB_register_Asm_F32: case ARM::VLD2LNdWB_register_Asm_I32: case ARM::VLD2LNdWB_register_Asm_S32: case ARM::VLD2LNdWB_register_Asm_U32: - case ARM::VLD2LNqWB_register_Asm_P16: case ARM::VLD2LNqWB_register_Asm_I16: - case ARM::VLD2LNqWB_register_Asm_S16: case ARM::VLD2LNqWB_register_Asm_U16: - case ARM::VLD2LNqWB_register_Asm_32: case ARM::VLD2LNqWB_register_Asm_F: - case ARM::VLD2LNqWB_register_Asm_F32: case ARM::VLD2LNqWB_register_Asm_I32: - case ARM::VLD2LNqWB_register_Asm_S32: case ARM::VLD2LNqWB_register_Asm_U32: { + case ARM::VLD2LNqWB_register_Asm_16: case ARM::VLD2LNqWB_register_Asm_P16: + case ARM::VLD2LNqWB_register_Asm_I16: case ARM::VLD2LNqWB_register_Asm_S16: + case ARM::VLD2LNqWB_register_Asm_U16: case ARM::VLD2LNqWB_register_Asm_32: + case ARM::VLD2LNqWB_register_Asm_F: case ARM::VLD2LNqWB_register_Asm_F32: + case ARM::VLD2LNqWB_register_Asm_I32: case ARM::VLD2LNqWB_register_Asm_S32: + case ARM::VLD2LNqWB_register_Asm_U32: { MCInst TmpInst; // Shuffle the operands around so the lane index operand is in the // right place. @@ -5565,11 +5640,12 @@ case ARM::VLD2LNdWB_fixed_Asm_32: case ARM::VLD2LNdWB_fixed_Asm_F: case ARM::VLD2LNdWB_fixed_Asm_F32: case ARM::VLD2LNdWB_fixed_Asm_I32: case ARM::VLD2LNdWB_fixed_Asm_S32: case ARM::VLD2LNdWB_fixed_Asm_U32: - case ARM::VLD2LNqWB_fixed_Asm_P16: case ARM::VLD2LNqWB_fixed_Asm_I16: - case ARM::VLD2LNqWB_fixed_Asm_S16: case ARM::VLD2LNqWB_fixed_Asm_U16: - case ARM::VLD2LNqWB_fixed_Asm_32: case ARM::VLD2LNqWB_fixed_Asm_F: - case ARM::VLD2LNqWB_fixed_Asm_F32: case ARM::VLD2LNqWB_fixed_Asm_I32: - case ARM::VLD2LNqWB_fixed_Asm_S32: case ARM::VLD2LNqWB_fixed_Asm_U32: { + case ARM::VLD2LNqWB_fixed_Asm_16: case ARM::VLD2LNqWB_fixed_Asm_P16: + case ARM::VLD2LNqWB_fixed_Asm_I16: case ARM::VLD2LNqWB_fixed_Asm_S16: + case ARM::VLD2LNqWB_fixed_Asm_U16: case ARM::VLD2LNqWB_fixed_Asm_32: + case ARM::VLD2LNqWB_fixed_Asm_F: case ARM::VLD2LNqWB_fixed_Asm_F32: + case ARM::VLD2LNqWB_fixed_Asm_I32: case ARM::VLD2LNqWB_fixed_Asm_S32: + case ARM::VLD2LNqWB_fixed_Asm_U32: { MCInst TmpInst; // Shuffle the operands around so the lane index operand is in the // right place. @@ -5592,10 +5668,10 @@ return true; } - case ARM::VLD1LNdAsm_8: case ARM::VLD1LNdAsm_P8: case ARM::VLD1LNdAsm_I8: - case ARM::VLD1LNdAsm_S8: case ARM::VLD1LNdAsm_U8: case ARM::VLD1LNdAsm_16: + case ARM::VLD1LNdAsm_8: case ARM::VLD1LNdAsm_P8: case ARM::VLD1LNdAsm_I8: + case ARM::VLD1LNdAsm_S8: case ARM::VLD1LNdAsm_U8: case ARM::VLD1LNdAsm_16: case ARM::VLD1LNdAsm_P16: case ARM::VLD1LNdAsm_I16: case ARM::VLD1LNdAsm_S16: - case ARM::VLD1LNdAsm_U16: case ARM::VLD1LNdAsm_32: case ARM::VLD1LNdAsm_F: + case ARM::VLD1LNdAsm_U16: case ARM::VLD1LNdAsm_32: case ARM::VLD1LNdAsm_F: case ARM::VLD1LNdAsm_F32: case ARM::VLD1LNdAsm_I32: case ARM::VLD1LNdAsm_S32: case ARM::VLD1LNdAsm_U32: { MCInst TmpInst; Modified: llvm/trunk/test/MC/ARM/neon-vst-encoding.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/neon-vst-encoding.s?rev=146990&r1=146989&r2=146990&view=diff ============================================================================== --- llvm/trunk/test/MC/ARM/neon-vst-encoding.s (original) +++ llvm/trunk/test/MC/ARM/neon-vst-encoding.s Tue Dec 20 14:46:29 2011 @@ -101,23 +101,37 @@ vst2.8 {d16[1], d17[1]}, [r0, :16] vst2.16 {d16[1], d17[1]}, [r0, :32] vst2.32 {d16[1], d17[1]}, [r0] -@ vst2.16 {d17[1], d19[1]}, [r0] -@ vst2.32 {d17[0], d19[0]}, [r0, :64] + vst2.16 {d17[1], d19[1]}, [r0] + vst2.32 {d17[0], d19[0]}, [r0, :64] vst2.8 {d2[4], d3[4]}, [r2], r3 vst2.8 {d2[4], d3[4]}, [r2]! vst2.8 {d2[4], d3[4]}, [r2] + vst2.16 {d17[1], d19[1]}, [r0] + vst2.32 {d17[0], d19[0]}, [r0, :64] + vst2.16 {d7[1], d9[1]}, [r1]! + vst2.32 {d6[0], d8[0]}, [r2, :64]! + vst2.16 {d2[1], d4[1]}, [r3], r5 + vst2.32 {d5[0], d7[0]}, [r4, :64], r7 + @ CHECK: vst2.8 {d16[1], d17[1]}, [r0, :16] @ encoding: [0x3f,0x01,0xc0,0xf4] @ CHECK: vst2.16 {d16[1], d17[1]}, [r0, :32] @ encoding: [0x5f,0x05,0xc0,0xf4] @ CHECK: vst2.32 {d16[1], d17[1]}, [r0] @ encoding: [0x8f,0x09,0xc0,0xf4] -@ FIXME: vst2.16 {d17[1], d19[1]}, [r0] @ encoding: [0x6f,0x15,0xc0,0xf4] -@ FIXME: vst2.32 {d17[0], d19[0]}, [r0, :64] @ encoding: [0x5f,0x19,0xc0,0xf4] +@ CHECK: vst2.16 {d17[1], d19[1]}, [r0] @ encoding: [0x6f,0x15,0xc0,0xf4] +@ CHECK: vst2.32 {d17[0], d19[0]}, [r0, :64] @ encoding: [0x5f,0x19,0xc0,0xf4] @ CHECK: vst2.8 {d2[4], d3[4]}, [r2], r3 @ encoding: [0x83,0x21,0x82,0xf4] @ CHECK: vst2.8 {d2[4], d3[4]}, [r2]! @ encoding: [0x8d,0x21,0x82,0xf4] @ CHECK: vst2.8 {d2[4], d3[4]}, [r2] @ encoding: [0x8f,0x21,0x82,0xf4] +@ CHECK: vst2.16 {d17[1], d19[1]}, [r0] @ encoding: [0x6f,0x15,0xc0,0xf4] +@ CHECK: vst2.32 {d17[0], d19[0]}, [r0, :64] @ encoding: [0x5f,0x19,0xc0,0xf4] +@ CHECK: vst2.16 {d7[1], d9[1]}, [r1]! @ encoding: [0x6d,0x75,0x81,0xf4] +@ CHECK: vst2.32 {d6[0], d8[0]}, [r2, :64]! @ encoding: [0x5d,0x69,0x82,0xf4] +@ CHECK: vst2.16 {d2[1], d4[1]}, [r3], r5 @ encoding: [0x65,0x25,0x83,0xf4] +@ CHECK: vst2.32 {d5[0], d7[0]}, [r4, :64], r7 @ encoding: [0x57,0x59,0x84,0xf4] + @ vst3.8 {d16[1], d17[1], d18[1]}, [r0] @ vst3.16 {d16[1], d17[1], d18[1]}, [r0] From grosbach at apple.com Tue Dec 20 15:08:01 2011 From: grosbach at apple.com (Jim Grosbach) Date: Tue, 20 Dec 2011 13:08:01 -0800 Subject: [llvm-commits] [PATCH] MC ARM Thumb: fix incorrect relocation generation (PR11214) In-Reply-To: References: <000001ccbf1d$618f7490$24ae5db0$%beyls@arm.com> <57817466-3086-4652-85E2-4959AF23D81B@apple.com> <107270DB-89BE-4C71-9181-CF7FDD300E25@apple.com> Message-ID: <854417BF-9EFC-4743-A8F3-249712BC9ADD@apple.com> Right. I agree it's fairly clear that R_ARM_NONE is wrong. It's not clear, however, that R_ARM_THM_CALL is correct for non-PLT relocations. I suspect it's not else that conditional wouldn't have been there in the first place. I'm hoping that an ELF knowledgeable person will chime in and let us know for sure one way or the other. -Jim On Dec 20, 2011, at 12:06 PM, Kristof Beyls wrote: > The reason why I thought the patch would be OK is that the patch only > changes the behaviour for the thumb bl and blx instructions (i.e. only for > the cases ARM::fixup_arm_thumb_bl and ARM::fixup_arm_thumb_blx. > > For these instructions, I can't see why R_ARM_NONE would ever be the correct > relocation type. The definition of R_ARM_NONE from the AAELF ABI: > """ > R_ARM_NONE records that the section containing the place to be relocated depends on the section defining the symbol mentioned in the relocation directive in a way otherwise invisible to the static linker. The effect is to prevent removal of sections that might otherwise appear to be unused. > """ > > Thanks, > > Kristof > >> -----Original Message----- >> From: Jim Grosbach [mailto:grosbach at apple.com] >> Sent: 20 December 2011 19:33 >> To: James Molloy >> Cc: Kristof Beyls; llvm-commits at cs.uiuc.edu >> Subject: Re: [llvm-commits] [PATCH] MC ARM Thumb: fix incorrect >> relocation generation (PR11214) >> >> Yeah, that's my guess. An assert(0 "unimplemented non-PLT call!") or >> something would have been better if that's the case exactly to prevent >> this sort of head-scratching. :) >> >> -Jim >> >> On Dec 20, 2011, at 11:21 AM, James Molloy wrote: >> >>> Yeah, I was confused about that too. >>> >>> I couldn't comprehend why that conditional was even there in the >> first place - an R_ARM_NONE relocation is *never* required for a call >> (it's a special no-op reloc). >>> >>> The only thing I could think of is that someone wanted to fix the >> relocation given to PLT entries and decided to keep the a broken >> behaviour for the default case, perhaps they had no knowledge about it. >>> ________________________________________ >>> From: llvm-commits-bounces at cs.uiuc.edu [llvm-commits- >> bounces at cs.uiuc.edu] On Behalf Of Jim Grosbach [grosbach at apple.com] >>> Sent: 20 December 2011 19:07 >>> To: Kristof Beyls >>> Cc: llvm-commits at cs.uiuc.edu >>> Subject: Re: [llvm-commits] [PATCH] MC ARM Thumb: fix incorrect >> relocation generation (PR11214) >>> >>> Someone with ELF knowledge should look at this. I'm a bit nervous >> about removing the conditional as it seems to imply that there's an >> different relocation that should be generated depending on the variant >> kind. >>> >>> -Jim >>> >>> On Dec 20, 2011, at 5:43 AM, Kristof Beyls wrote: >>> >>>> Hi, >>>> >>>> Please find a patch for fixing incorrect generation of relocation >>>> information on Thumb function calls. >>>> This should fix quite a few incorrect code generation problems in >> Thumb mode >>>> when using the integrated assembler. >>>> I believe this fixes PR11214 >>>> (http://www.llvm.org/bugs/show_bug.cgi?id=11214). >>>> >>>> Is this OK? >>>> >>>> Thanks, >>>> >>>> Kristof >>>> >> ____________________________________________ >> ___ >>>> llvm-commits mailing list >>>> llvm-commits at cs.uiuc.edu >>>> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits >>> >>> _______________________________________________ >>> llvm-commits mailing list >>> llvm-commits at cs.uiuc.edu >>> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits >>> >>> >>> -- IMPORTANT NOTICE: The contents of this email and any attachments >> are confidential and may also be privileged. If you are not the >> intended recipient, please notify the sender immediately and do not >> disclose the contents to any other person, use it for any purpose, or >> store or copy the information in any medium. Thank you. >>> >> >> > > > -- IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you. > From ahatanaka at mips.com Tue Dec 20 15:50:50 2011 From: ahatanaka at mips.com (Akira Hatanaka) Date: Tue, 20 Dec 2011 21:50:50 -0000 Subject: [llvm-commits] [llvm] r146992 - /llvm/trunk/lib/Target/Mips/MipsInstrInfo.td Message-ID: <20111220215050.0BC072A6C12C@llvm.org> Author: ahatanak Date: Tue Dec 20 15:50:49 2011 New Revision: 146992 URL: http://llvm.org/viewvc/llvm-project?rev=146992&view=rev Log: Add a pattern for matching zero-store with 64-bit address. The pattern is enabled only when the target ABI is N64. Modified: llvm/trunk/lib/Target/Mips/MipsInstrInfo.td Modified: llvm/trunk/lib/Target/Mips/MipsInstrInfo.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsInstrInfo.td?rev=146992&r1=146991&r2=146992&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/MipsInstrInfo.td (original) +++ llvm/trunk/lib/Target/Mips/MipsInstrInfo.td Tue Dec 20 15:50:49 2011 @@ -1015,7 +1015,10 @@ def : Pat<(extloadi16_u addr:$src), (ULHu addr:$src)>; // peepholes -def : Pat<(store (i32 0), addr:$dst), (SW ZERO, addr:$dst)>; +def : Pat<(store (i32 0), addr:$dst), (SW ZERO, addr:$dst)>, + Requires<[NotN64]>; +def : Pat<(store (i32 0), addr:$dst), (SW_P8 ZERO, addr:$dst)>, + Requires<[IsN64]>; // brcond patterns multiclass BrcondPats Author: ahatanak Date: Tue Dec 20 16:06:20 2011 New Revision: 146995 URL: http://llvm.org/viewvc/llvm-project?rev=146995&view=rev Log: 32-to-64-bit sign extension pattern. Modified: llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td llvm/trunk/lib/Target/Mips/MipsISelDAGToDAG.cpp Modified: llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td?rev=146995&r1=146994&r2=146995&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td (original) +++ llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td Tue Dec 20 16:06:20 2011 @@ -299,3 +299,5 @@ // 32-to-64-bit extension def : Pat<(i64 (anyext CPURegs:$src)), (SLL64_32 CPURegs:$src)>; def : Pat<(i64 (zext CPURegs:$src)), (DSRL (DSLL64_32 CPURegs:$src), 32)>; +def : Pat<(i64 (sext CPURegs:$src)), (SLL64_32 CPURegs:$src)>; + Modified: llvm/trunk/lib/Target/Mips/MipsISelDAGToDAG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsISelDAGToDAG.cpp?rev=146995&r1=146994&r2=146995&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/MipsISelDAGToDAG.cpp (original) +++ llvm/trunk/lib/Target/Mips/MipsISelDAGToDAG.cpp Tue Dec 20 16:06:20 2011 @@ -293,6 +293,12 @@ case ISD::ConstantFP: { ConstantFPSDNode *CN = dyn_cast(Node); if (Node->getValueType(0) == MVT::f64 && CN->isExactlyValue(+0.0)) { + if (Subtarget.hasMips64()) { + SDValue Zero = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl, + Mips::ZERO_64, MVT::i64); + return CurDAG->getMachineNode(Mips::DMTC1, dl, MVT::f64, Zero); + } + SDValue Zero = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl, Mips::ZERO, MVT::i32); return CurDAG->getMachineNode(Mips::BuildPairF64, dl, MVT::f64, Zero, From ahatanaka at mips.com Tue Dec 20 16:09:36 2011 From: ahatanaka at mips.com (Akira Hatanaka) Date: Tue, 20 Dec 2011 22:09:36 -0000 Subject: [llvm-commits] [llvm] r146996 - /llvm/trunk/lib/Target/Mips/MipsISelDAGToDAG.cpp Message-ID: <20111220220936.8C9192A6C12C@llvm.org> Author: ahatanak Date: Tue Dec 20 16:09:36 2011 New Revision: 146996 URL: http://llvm.org/viewvc/llvm-project?rev=146996&view=rev Log: Revert part of r146995 that was accidentally commmitted. Modified: llvm/trunk/lib/Target/Mips/MipsISelDAGToDAG.cpp Modified: llvm/trunk/lib/Target/Mips/MipsISelDAGToDAG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsISelDAGToDAG.cpp?rev=146996&r1=146995&r2=146996&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/MipsISelDAGToDAG.cpp (original) +++ llvm/trunk/lib/Target/Mips/MipsISelDAGToDAG.cpp Tue Dec 20 16:09:36 2011 @@ -293,12 +293,6 @@ case ISD::ConstantFP: { ConstantFPSDNode *CN = dyn_cast(Node); if (Node->getValueType(0) == MVT::f64 && CN->isExactlyValue(+0.0)) { - if (Subtarget.hasMips64()) { - SDValue Zero = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl, - Mips::ZERO_64, MVT::i64); - return CurDAG->getMachineNode(Mips::DMTC1, dl, MVT::f64, Zero); - } - SDValue Zero = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl, Mips::ZERO, MVT::i32); return CurDAG->getMachineNode(Mips::BuildPairF64, dl, MVT::f64, Zero, From stoklund at 2pi.dk Tue Dec 20 16:15:04 2011 From: stoklund at 2pi.dk (Jakob Stoklund Olesen) Date: Tue, 20 Dec 2011 22:15:04 -0000 Subject: [llvm-commits] [llvm] r146997 - in /llvm/trunk: lib/Target/ARM/ARMBaseInstrInfo.cpp lib/Target/ARM/ARMBaseRegisterInfo.cpp test/CodeGen/ARM/fast-isel-deadcode.ll test/CodeGen/Thumb2/aligned-spill.ll Message-ID: <20111220221504.878B42A6C12C@llvm.org> Author: stoklund Date: Tue Dec 20 16:15:04 2011 New Revision: 146997 URL: http://llvm.org/viewvc/llvm-project?rev=146997&view=rev Log: Heed spill slot alignment on ARM. Use the spill slot alignment as well as the local variable alignment to determine when the stack needs to be realigned. This works now that the ARM target can always realign the stack by using a base pointer. Still respect the ARMBaseRegisterInfo::canRealignStack() function vetoing a realigned stack. Don't use aligned spill code in that case. Added: llvm/trunk/test/CodeGen/Thumb2/aligned-spill.ll Modified: llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp llvm/trunk/test/CodeGen/ARM/fast-isel-deadcode.ll Modified: llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp?rev=146997&r1=146996&r2=146997&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp Tue Dec 20 16:15:04 2011 @@ -765,7 +765,8 @@ break; case 16: if (ARM::QPRRegClass.hasSubClassEq(RC)) { - if (Align >= 16 && getRegisterInfo().needsStackRealignment(MF)) { + // Use aligned spills if the stack can be realigned. + if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) { AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VST1q64Pseudo)) .addFrameIndex(FI).addImm(16) .addReg(SrcReg, getKillRegState(isKill)) @@ -914,7 +915,7 @@ break; case 16: if (ARM::QPRRegClass.hasSubClassEq(RC)) { - if (Align >= 16 && getRegisterInfo().needsStackRealignment(MF)) { + if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) { AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLD1q64Pseudo), DestReg) .addFrameIndex(FI).addImm(16) .addMemOperand(MMO)); Modified: llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp?rev=146997&r1=146996&r2=146997&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp Tue Dec 20 16:15:04 2011 @@ -542,7 +542,7 @@ const MachineFrameInfo *MFI = MF.getFrameInfo(); const Function *F = MF.getFunction(); unsigned StackAlign = MF.getTarget().getFrameLowering()->getStackAlignment(); - bool requiresRealignment = ((MFI->getLocalFrameMaxAlign() > StackAlign) || + bool requiresRealignment = ((MFI->getMaxAlignment() > StackAlign) || F->hasFnAttr(Attribute::StackAlignment)); return requiresRealignment && canRealignStack(MF); Modified: llvm/trunk/test/CodeGen/ARM/fast-isel-deadcode.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/fast-isel-deadcode.ll?rev=146997&r1=146996&r2=146997&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/ARM/fast-isel-deadcode.ll (original) +++ llvm/trunk/test/CodeGen/ARM/fast-isel-deadcode.ll Tue Dec 20 16:15:04 2011 @@ -15,8 +15,7 @@ ; THUMB-NOT: sxtb ; THUMB: movs r0, #0 ; THUMB: movt r0, #0 -; THUMB: add sp, #32 -; THUMb: pop {r7, pc} +; THUMB: pop ret i32 0 } Added: llvm/trunk/test/CodeGen/Thumb2/aligned-spill.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb2/aligned-spill.ll?rev=146997&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/Thumb2/aligned-spill.ll (added) +++ llvm/trunk/test/CodeGen/Thumb2/aligned-spill.ll Tue Dec 20 16:15:04 2011 @@ -0,0 +1,22 @@ +; RUN: llc < %s -mcpu=cortex-a8 | FileCheck %s +target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:32:64-v128:32:128-a0:0:32-n32-S32" +target triple = "thumbv7-apple-ios" + +; CHECK: f +; This function is forced to spill a double. +; Verify that the spill slot is properly aligned. +; +; The caller-saved r4 is used as a scratch register for stack realignment. +; CHECK: push {r4, r7, lr} +; CHECK: bic r4, r4, #7 +; CHECK: mov sp, r4 +define void @f(double* nocapture %p) nounwind ssp { +entry: + %0 = load double* %p, align 4 + tail call void asm sideeffect "", "~{d8},~{d9},~{d10},~{d11},~{d12},~{d13},~{d14},~{d15}"() nounwind + tail call void @g() nounwind + store double %0, double* %p, align 4 + ret void +} + +declare void @g() From ahatanaka at mips.com Tue Dec 20 16:25:51 2011 From: ahatanaka at mips.com (Akira Hatanaka) Date: Tue, 20 Dec 2011 22:25:51 -0000 Subject: [llvm-commits] [llvm] r146999 - in /llvm/trunk: lib/Target/Mips/MipsISelDAGToDAG.cpp test/CodeGen/Mips/mips64fpimm0.ll Message-ID: <20111220222551.1FA342A6C12C@llvm.org> Author: ahatanak Date: Tue Dec 20 16:25:50 2011 New Revision: 146999 URL: http://llvm.org/viewvc/llvm-project?rev=146999&view=rev Log: Add code in MipsDAGToDAGISel for selecting constant +0.0. MIPS64 can generate constant +0.0 with a single DMTC1 instruction. Added: llvm/trunk/test/CodeGen/Mips/mips64fpimm0.ll Modified: llvm/trunk/lib/Target/Mips/MipsISelDAGToDAG.cpp Modified: llvm/trunk/lib/Target/Mips/MipsISelDAGToDAG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsISelDAGToDAG.cpp?rev=146999&r1=146998&r2=146999&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/MipsISelDAGToDAG.cpp (original) +++ llvm/trunk/lib/Target/Mips/MipsISelDAGToDAG.cpp Tue Dec 20 16:25:50 2011 @@ -293,6 +293,12 @@ case ISD::ConstantFP: { ConstantFPSDNode *CN = dyn_cast(Node); if (Node->getValueType(0) == MVT::f64 && CN->isExactlyValue(+0.0)) { + if (Subtarget.hasMips64()) { + SDValue Zero = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl, + Mips::ZERO_64, MVT::i64); + return CurDAG->getMachineNode(Mips::DMTC1, dl, MVT::f64, Zero); + } + SDValue Zero = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl, Mips::ZERO, MVT::i32); return CurDAG->getMachineNode(Mips::BuildPairF64, dl, MVT::f64, Zero, Added: llvm/trunk/test/CodeGen/Mips/mips64fpimm0.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/mips64fpimm0.ll?rev=146999&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/Mips/mips64fpimm0.ll (added) +++ llvm/trunk/test/CodeGen/Mips/mips64fpimm0.ll Tue Dec 20 16:25:50 2011 @@ -0,0 +1,7 @@ +; RUN: llc < %s -march=mips64el -mcpu=mips64 -mattr=n64 | FileCheck %s + +define double @foo1() nounwind readnone { +entry: +; CHECK: dmtc1 $zero + ret double 0.000000e+00 +} From grosbach at apple.com Tue Dec 20 16:26:38 2011 From: grosbach at apple.com (Jim Grosbach) Date: Tue, 20 Dec 2011 22:26:38 -0000 Subject: [llvm-commits] [llvm] r147000 - /llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Message-ID: <20111220222638.AD31A2A6C12C@llvm.org> Author: grosbach Date: Tue Dec 20 16:26:38 2011 New Revision: 147000 URL: http://llvm.org/viewvc/llvm-project?rev=147000&view=rev Log: Move comment to appropriate place. Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp?rev=147000&r1=146999&r2=147000&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp (original) +++ llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Tue Dec 20 16:26:38 2011 @@ -4297,7 +4297,6 @@ Error(Parser.getTok().getLoc(), "unexpected token in operand"); return true; case AsmToken::Identifier: { - // If this is VMRS, check for the apsr_nzcv operand. if (!tryParseRegisterWithWriteBack(Operands)) return false; int Res = tryParseShiftRegister(Operands); @@ -4305,6 +4304,7 @@ return false; else if (Res == -1) // irrecoverable error return true; + // If this is VMRS, check for the apsr_nzcv operand. if (Mnemonic == "vmrs" && Parser.getTok().getString() == "apsr_nzcv") { S = Parser.getTok().getLoc(); Parser.Lex(); From ahatanaka at mips.com Tue Dec 20 16:33:53 2011 From: ahatanaka at mips.com (Akira Hatanaka) Date: Tue, 20 Dec 2011 22:33:53 -0000 Subject: [llvm-commits] [llvm] r147001 - /llvm/trunk/lib/Target/Mips/MipsInstrInfo.td Message-ID: <20111220223353.6447C2A6C12C@llvm.org> Author: ahatanak Date: Tue Dec 20 16:33:53 2011 New Revision: 147001 URL: http://llvm.org/viewvc/llvm-project?rev=147001&view=rev Log: Add patterns for matching extloads with 64-bit address. The patterns are enabled only when the target ABI is N64. Modified: llvm/trunk/lib/Target/Mips/MipsInstrInfo.td Modified: llvm/trunk/lib/Target/Mips/MipsInstrInfo.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsInstrInfo.td?rev=147001&r1=147000&r2=147001&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/MipsInstrInfo.td (original) +++ llvm/trunk/lib/Target/Mips/MipsInstrInfo.td Tue Dec 20 16:33:53 2011 @@ -1008,11 +1008,19 @@ def : Pat<(not CPURegs:$in), (NOR CPURegs:$in, ZERO)>; -// extended load and stores -def : Pat<(extloadi1 addr:$src), (LBu addr:$src)>; -def : Pat<(extloadi8 addr:$src), (LBu addr:$src)>; -def : Pat<(extloadi16_a addr:$src), (LHu addr:$src)>; -def : Pat<(extloadi16_u addr:$src), (ULHu addr:$src)>; +// extended loads +let Predicates = [NotN64] in { + def : Pat<(i32 (extloadi1 addr:$src)), (LBu addr:$src)>; + def : Pat<(i32 (extloadi8 addr:$src)), (LBu addr:$src)>; + def : Pat<(i32 (extloadi16_a addr:$src)), (LHu addr:$src)>; + def : Pat<(i32 (extloadi16_u addr:$src)), (ULHu addr:$src)>; +} +let Predicates = [IsN64] in { + def : Pat<(i32 (extloadi1 addr:$src)), (LBu_P8 addr:$src)>; + def : Pat<(i32 (extloadi8 addr:$src)), (LBu_P8 addr:$src)>; + def : Pat<(i32 (extloadi16_a addr:$src)), (LHu_P8 addr:$src)>; + def : Pat<(i32 (extloadi16_u addr:$src)), (ULHu_P8 addr:$src)>; +} // peepholes def : Pat<(store (i32 0), addr:$dst), (SW ZERO, addr:$dst)>, From ahatanaka at mips.com Tue Dec 20 16:36:08 2011 From: ahatanaka at mips.com (Akira Hatanaka) Date: Tue, 20 Dec 2011 22:36:08 -0000 Subject: [llvm-commits] [llvm] r147003 - /llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td Message-ID: <20111220223609.070D62A6C12C@llvm.org> Author: ahatanak Date: Tue Dec 20 16:36:08 2011 New Revision: 147003 URL: http://llvm.org/viewvc/llvm-project?rev=147003&view=rev Log: Add 64-bit extload patterns. Modified: llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td Modified: llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td?rev=147003&r1=147002&r2=147003&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td (original) +++ llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td Tue Dec 20 16:36:08 2011 @@ -240,11 +240,21 @@ // extended loads let Predicates = [NotN64] in { - def : Pat<(extloadi32_a addr:$a), (DSRL (DSLL (LW64 addr:$a), 32), 32)>; + def : Pat<(i64 (extloadi1 addr:$src)), (LB64 addr:$src)>; + def : Pat<(i64 (extloadi8 addr:$src)), (LB64 addr:$src)>; + def : Pat<(i64 (extloadi16_a addr:$src)), (LH64 addr:$src)>; + def : Pat<(i64 (extloadi16_u addr:$src)), (ULH64 addr:$src)>; + def : Pat<(i64 (extloadi32_a addr:$src)), (LW64 addr:$src)>; + def : Pat<(i64 (extloadi32_u addr:$src)), (ULW64 addr:$src)>; def : Pat<(zextloadi32_u addr:$a), (DSRL (DSLL (ULW64 addr:$a), 32), 32)>; } let Predicates = [IsN64] in { - def : Pat<(extloadi32_a addr:$a), (DSRL (DSLL (LW64_P8 addr:$a), 32), 32)>; + def : Pat<(i64 (extloadi1 addr:$src)), (LB64_P8 addr:$src)>; + def : Pat<(i64 (extloadi8 addr:$src)), (LB64_P8 addr:$src)>; + def : Pat<(i64 (extloadi16_a addr:$src)), (LH64_P8 addr:$src)>; + def : Pat<(i64 (extloadi16_u addr:$src)), (ULH64_P8 addr:$src)>; + def : Pat<(i64 (extloadi32_a addr:$src)), (LW64_P8 addr:$src)>; + def : Pat<(i64 (extloadi32_u addr:$src)), (ULW64_P8 addr:$src)>; def : Pat<(zextloadi32_u addr:$a), (DSRL (DSLL (ULW64_P8 addr:$a), 32), 32)>; } From ahatanaka at mips.com Tue Dec 20 16:40:40 2011 From: ahatanaka at mips.com (Akira Hatanaka) Date: Tue, 20 Dec 2011 22:40:40 -0000 Subject: [llvm-commits] [llvm] r147004 - in /llvm/trunk: lib/Target/Mips/Mips64InstrInfo.td test/CodeGen/Mips/mips64ext.ll Message-ID: <20111220224040.B1A9F2A6C12C@llvm.org> Author: ahatanak Date: Tue Dec 20 16:40:40 2011 New Revision: 147004 URL: http://llvm.org/viewvc/llvm-project?rev=147004&view=rev Log: 32-to-64-bit sext_inreg pattern. Modified: llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td llvm/trunk/test/CodeGen/Mips/mips64ext.ll Modified: llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td?rev=147004&r1=147003&r2=147004&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td (original) +++ llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td Tue Dec 20 16:40:40 2011 @@ -215,6 +215,8 @@ def SLL64_32 : FR<0x0, 0x00, (outs CPU64Regs:$rd), (ins CPURegs:$rt), "sll\t$rd, $rt, 0", [], IIAlu>; +def SLL64_64 : FR<0x0, 0x00, (outs CPU64Regs:$rd), (ins CPU64Regs:$rt), + "sll\t$rd, $rt, 0", [], IIAlu>; //===----------------------------------------------------------------------===// // Arbitrary patterns that map to one or more instructions @@ -311,3 +313,6 @@ def : Pat<(i64 (zext CPURegs:$src)), (DSRL (DSLL64_32 CPURegs:$src), 32)>; def : Pat<(i64 (sext CPURegs:$src)), (SLL64_32 CPURegs:$src)>; +// Sign extend in register +def : Pat<(i64 (sext_inreg CPU64Regs:$src, i32)), (SLL64_64 CPU64Regs:$src)>; + Modified: llvm/trunk/test/CodeGen/Mips/mips64ext.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/mips64ext.ll?rev=147004&r1=147003&r2=147004&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/Mips/mips64ext.ll (original) +++ llvm/trunk/test/CodeGen/Mips/mips64ext.ll Tue Dec 20 16:40:40 2011 @@ -9,3 +9,11 @@ %conv = zext i32 %add to i64 ret i64 %conv } + +define i64 @sext64_32(i32 %a) nounwind readnone { +entry: +; CHECK: sll ${{[0-9]+}}, ${{[0-9]+}}, 0 + %conv = sext i32 %a to i64 + ret i64 %conv +} + From ahatanaka at mips.com Tue Dec 20 16:52:19 2011 From: ahatanaka at mips.com (Akira Hatanaka) Date: Tue, 20 Dec 2011 22:52:19 -0000 Subject: [llvm-commits] [llvm] r147005 - in /llvm/trunk: lib/Target/Mips/MCTargetDesc/MipsMCAsmInfo.cpp test/CodeGen/Mips/mips64directive.ll Message-ID: <20111220225219.83D572A6C12C@llvm.org> Author: ahatanak Date: Tue Dec 20 16:52:19 2011 New Revision: 147005 URL: http://llvm.org/viewvc/llvm-project?rev=147005&view=rev Log: 64-bit data directive. Added: llvm/trunk/test/CodeGen/Mips/mips64directive.ll Modified: llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsMCAsmInfo.cpp Modified: llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsMCAsmInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsMCAsmInfo.cpp?rev=147005&r1=147004&r2=147005&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsMCAsmInfo.cpp (original) +++ llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsMCAsmInfo.cpp Tue Dec 20 16:52:19 2011 @@ -27,7 +27,7 @@ AlignmentIsInBytes = false; Data16bitsDirective = "\t.2byte\t"; Data32bitsDirective = "\t.4byte\t"; - Data64bitsDirective = 0; + Data64bitsDirective = "\t.8byte\t"; PrivateGlobalPrefix = "$"; CommentString = "#"; ZeroDirective = "\t.space\t"; Added: llvm/trunk/test/CodeGen/Mips/mips64directive.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/mips64directive.ll?rev=147005&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/Mips/mips64directive.ll (added) +++ llvm/trunk/test/CodeGen/Mips/mips64directive.ll Tue Dec 20 16:52:19 2011 @@ -0,0 +1,11 @@ +; RUN: llc < %s -march=mips64el -mcpu=mips64 -mattr=n64 | FileCheck %s + + at gl = global i64 1250999896321, align 8 + +; CHECK: 8byte +define i64 @foo1() nounwind readonly { +entry: + %0 = load i64* @gl, align 8 + ret i64 %0 +} + From ahatanaka at mips.com Tue Dec 20 16:58:01 2011 From: ahatanaka at mips.com (Akira Hatanaka) Date: Tue, 20 Dec 2011 22:58:01 -0000 Subject: [llvm-commits] [llvm] r147007 - /llvm/trunk/lib/Target/Mips/MipsISelDAGToDAG.cpp Message-ID: <20111220225801.AF76E2A6C12C@llvm.org> Author: ahatanak Date: Tue Dec 20 16:58:01 2011 New Revision: 147007 URL: http://llvm.org/viewvc/llvm-project?rev=147007&view=rev Log: Fix indentation. Modified: llvm/trunk/lib/Target/Mips/MipsISelDAGToDAG.cpp Modified: llvm/trunk/lib/Target/Mips/MipsISelDAGToDAG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsISelDAGToDAG.cpp?rev=147007&r1=147006&r2=147007&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/MipsISelDAGToDAG.cpp (original) +++ llvm/trunk/lib/Target/Mips/MipsISelDAGToDAG.cpp Tue Dec 20 16:58:01 2011 @@ -196,141 +196,141 @@ // tablegen selection should be handled here. /// switch(Opcode) { - default: break; + default: break; - case ISD::SUBE: - case ISD::ADDE: { - SDValue InFlag = Node->getOperand(2), CmpLHS; - unsigned Opc = InFlag.getOpcode(); (void)Opc; - assert(((Opc == ISD::ADDC || Opc == ISD::ADDE) || - (Opc == ISD::SUBC || Opc == ISD::SUBE)) && - "(ADD|SUB)E flag operand must come from (ADD|SUB)C/E insn"); - - unsigned MOp; - if (Opcode == ISD::ADDE) { - CmpLHS = InFlag.getValue(0); - MOp = Mips::ADDu; - } else { - CmpLHS = InFlag.getOperand(0); - MOp = Mips::SUBu; - } + case ISD::SUBE: + case ISD::ADDE: { + SDValue InFlag = Node->getOperand(2), CmpLHS; + unsigned Opc = InFlag.getOpcode(); (void)Opc; + assert(((Opc == ISD::ADDC || Opc == ISD::ADDE) || + (Opc == ISD::SUBC || Opc == ISD::SUBE)) && + "(ADD|SUB)E flag operand must come from (ADD|SUB)C/E insn"); + + unsigned MOp; + if (Opcode == ISD::ADDE) { + CmpLHS = InFlag.getValue(0); + MOp = Mips::ADDu; + } else { + CmpLHS = InFlag.getOperand(0); + MOp = Mips::SUBu; + } - SDValue Ops[] = { CmpLHS, InFlag.getOperand(1) }; + SDValue Ops[] = { CmpLHS, InFlag.getOperand(1) }; - SDValue LHS = Node->getOperand(0); - SDValue RHS = Node->getOperand(1); + SDValue LHS = Node->getOperand(0); + SDValue RHS = Node->getOperand(1); - EVT VT = LHS.getValueType(); - SDNode *Carry = CurDAG->getMachineNode(Mips::SLTu, dl, VT, Ops, 2); - SDNode *AddCarry = CurDAG->getMachineNode(Mips::ADDu, dl, VT, - SDValue(Carry,0), RHS); + EVT VT = LHS.getValueType(); + SDNode *Carry = CurDAG->getMachineNode(Mips::SLTu, dl, VT, Ops, 2); + SDNode *AddCarry = CurDAG->getMachineNode(Mips::ADDu, dl, VT, + SDValue(Carry,0), RHS); - return CurDAG->SelectNodeTo(Node, MOp, VT, MVT::Glue, - LHS, SDValue(AddCarry,0)); - } + return CurDAG->SelectNodeTo(Node, MOp, VT, MVT::Glue, + LHS, SDValue(AddCarry,0)); + } - /// Mul with two results - case ISD::SMUL_LOHI: - case ISD::UMUL_LOHI: { - assert(Node->getValueType(0) != MVT::i64 && - "64-bit multiplication with two results not handled."); - SDValue Op1 = Node->getOperand(0); - SDValue Op2 = Node->getOperand(1); - - unsigned Op; - Op = (Opcode == ISD::UMUL_LOHI ? Mips::MULTu : Mips::MULT); - - SDNode *Mul = CurDAG->getMachineNode(Op, dl, MVT::Glue, Op1, Op2); - - SDValue InFlag = SDValue(Mul, 0); - SDNode *Lo = CurDAG->getMachineNode(Mips::MFLO, dl, MVT::i32, - MVT::Glue, InFlag); - InFlag = SDValue(Lo,1); - SDNode *Hi = CurDAG->getMachineNode(Mips::MFHI, dl, MVT::i32, InFlag); + /// Mul with two results + case ISD::SMUL_LOHI: + case ISD::UMUL_LOHI: { + assert(Node->getValueType(0) != MVT::i64 && + "64-bit multiplication with two results not handled."); + SDValue Op1 = Node->getOperand(0); + SDValue Op2 = Node->getOperand(1); + + unsigned Op; + Op = (Opcode == ISD::UMUL_LOHI ? Mips::MULTu : Mips::MULT); + + SDNode *Mul = CurDAG->getMachineNode(Op, dl, MVT::Glue, Op1, Op2); + + SDValue InFlag = SDValue(Mul, 0); + SDNode *Lo = CurDAG->getMachineNode(Mips::MFLO, dl, MVT::i32, + MVT::Glue, InFlag); + InFlag = SDValue(Lo,1); + SDNode *Hi = CurDAG->getMachineNode(Mips::MFHI, dl, MVT::i32, InFlag); - if (!SDValue(Node, 0).use_empty()) - ReplaceUses(SDValue(Node, 0), SDValue(Lo,0)); + if (!SDValue(Node, 0).use_empty()) + ReplaceUses(SDValue(Node, 0), SDValue(Lo,0)); - if (!SDValue(Node, 1).use_empty()) - ReplaceUses(SDValue(Node, 1), SDValue(Hi,0)); + if (!SDValue(Node, 1).use_empty()) + ReplaceUses(SDValue(Node, 1), SDValue(Hi,0)); - return NULL; - } + return NULL; + } - /// Special Muls - case ISD::MUL: - // Mips32 has a 32-bit three operand mul instruction. - if (Subtarget.hasMips32() && Node->getValueType(0) == MVT::i32) - break; - case ISD::MULHS: - case ISD::MULHU: { - assert((Opcode == ISD::MUL || Node->getValueType(0) != MVT::i64) && - "64-bit MULH* not handled."); - EVT Ty = Node->getValueType(0); - SDValue MulOp1 = Node->getOperand(0); - SDValue MulOp2 = Node->getOperand(1); - - unsigned MulOp = (Opcode == ISD::MULHU ? - Mips::MULTu : - (Ty == MVT::i32 ? Mips::MULT : Mips::DMULT)); - SDNode *MulNode = CurDAG->getMachineNode(MulOp, dl, - MVT::Glue, MulOp1, MulOp2); - - SDValue InFlag = SDValue(MulNode, 0); - - if (Opcode == ISD::MUL) { - unsigned Opc = (Ty == MVT::i32 ? Mips::MFLO : Mips::MFLO64); - return CurDAG->getMachineNode(Opc, dl, Ty, InFlag); - } - else - return CurDAG->getMachineNode(Mips::MFHI, dl, MVT::i32, InFlag); + /// Special Muls + case ISD::MUL: + // Mips32 has a 32-bit three operand mul instruction. + if (Subtarget.hasMips32() && Node->getValueType(0) == MVT::i32) + break; + case ISD::MULHS: + case ISD::MULHU: { + assert((Opcode == ISD::MUL || Node->getValueType(0) != MVT::i64) && + "64-bit MULH* not handled."); + EVT Ty = Node->getValueType(0); + SDValue MulOp1 = Node->getOperand(0); + SDValue MulOp2 = Node->getOperand(1); + + unsigned MulOp = (Opcode == ISD::MULHU ? + Mips::MULTu : + (Ty == MVT::i32 ? Mips::MULT : Mips::DMULT)); + SDNode *MulNode = CurDAG->getMachineNode(MulOp, dl, + MVT::Glue, MulOp1, MulOp2); + + SDValue InFlag = SDValue(MulNode, 0); + + if (Opcode == ISD::MUL) { + unsigned Opc = (Ty == MVT::i32 ? Mips::MFLO : Mips::MFLO64); + return CurDAG->getMachineNode(Opc, dl, Ty, InFlag); } + else + return CurDAG->getMachineNode(Mips::MFHI, dl, MVT::i32, InFlag); + } - // Get target GOT address. - case ISD::GLOBAL_OFFSET_TABLE: - return getGlobalBaseReg(); - - case ISD::ConstantFP: { - ConstantFPSDNode *CN = dyn_cast(Node); - if (Node->getValueType(0) == MVT::f64 && CN->isExactlyValue(+0.0)) { - if (Subtarget.hasMips64()) { - SDValue Zero = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl, - Mips::ZERO_64, MVT::i64); - return CurDAG->getMachineNode(Mips::DMTC1, dl, MVT::f64, Zero); - } - + // Get target GOT address. + case ISD::GLOBAL_OFFSET_TABLE: + return getGlobalBaseReg(); + + case ISD::ConstantFP: { + ConstantFPSDNode *CN = dyn_cast(Node); + if (Node->getValueType(0) == MVT::f64 && CN->isExactlyValue(+0.0)) { + if (Subtarget.hasMips64()) { SDValue Zero = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl, - Mips::ZERO, MVT::i32); - return CurDAG->getMachineNode(Mips::BuildPairF64, dl, MVT::f64, Zero, - Zero); + Mips::ZERO_64, MVT::i64); + return CurDAG->getMachineNode(Mips::DMTC1, dl, MVT::f64, Zero); } - break; + + SDValue Zero = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl, + Mips::ZERO, MVT::i32); + return CurDAG->getMachineNode(Mips::BuildPairF64, dl, MVT::f64, Zero, + Zero); } + break; + } - case MipsISD::ThreadPointer: { - EVT PtrVT = TLI.getPointerTy(); - unsigned RdhwrOpc, SrcReg, DestReg; - - if (PtrVT == MVT::i32) { - RdhwrOpc = Mips::RDHWR; - SrcReg = Mips::HWR29; - DestReg = Mips::V1; - } else { - RdhwrOpc = Mips::RDHWR64; - SrcReg = Mips::HWR29_64; - DestReg = Mips::V1_64; - } - - SDNode *Rdhwr = - CurDAG->getMachineNode(RdhwrOpc, Node->getDebugLoc(), - Node->getValueType(0), - CurDAG->getRegister(SrcReg, PtrVT)); - SDValue Chain = CurDAG->getCopyToReg(CurDAG->getEntryNode(), dl, DestReg, - SDValue(Rdhwr, 0)); - SDValue ResNode = CurDAG->getCopyFromReg(Chain, dl, DestReg, PtrVT); - ReplaceUses(SDValue(Node, 0), ResNode); - return ResNode.getNode(); + case MipsISD::ThreadPointer: { + EVT PtrVT = TLI.getPointerTy(); + unsigned RdhwrOpc, SrcReg, DestReg; + + if (PtrVT == MVT::i32) { + RdhwrOpc = Mips::RDHWR; + SrcReg = Mips::HWR29; + DestReg = Mips::V1; + } else { + RdhwrOpc = Mips::RDHWR64; + SrcReg = Mips::HWR29_64; + DestReg = Mips::V1_64; } + + SDNode *Rdhwr = + CurDAG->getMachineNode(RdhwrOpc, Node->getDebugLoc(), + Node->getValueType(0), + CurDAG->getRegister(SrcReg, PtrVT)); + SDValue Chain = CurDAG->getCopyToReg(CurDAG->getEntryNode(), dl, DestReg, + SDValue(Rdhwr, 0)); + SDValue ResNode = CurDAG->getCopyFromReg(Chain, dl, DestReg, PtrVT); + ReplaceUses(SDValue(Node, 0), ResNode); + return ResNode.getNode(); + } } // Select the default instruction From chandlerc at google.com Tue Dec 20 17:09:25 2011 From: chandlerc at google.com (Chandler Carruth) Date: Tue, 20 Dec 2011 15:09:25 -0800 Subject: [llvm-commits] [llvm] r146977 - /llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp In-Reply-To: <20111220173813.0BD732A6C12C@llvm.org> References: <20111220173813.0BD732A6C12C@llvm.org> Message-ID: Cool! On Tue, Dec 20, 2011 at 9:38 AM, Jason W Kim wrote: > First steps in ARM AsmParser support for .eabi_attribute and .arch > (Both used for Linux gnueabi) > No behavioral change yet (no tests need so far) > Why no tests needed? We should have tests that just exercise the parsing, no? If not, I think it would be good to wait on commit until enough functionality is there to at least have a sanity test. Essentially, you should have enough tests here to ensure you didn't commit an 'abort()' or a divide by zero. -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20111220/138d1670/attachment.html From ahatanaka at mips.com Tue Dec 20 17:10:57 2011 From: ahatanaka at mips.com (Akira Hatanaka) Date: Tue, 20 Dec 2011 23:10:57 -0000 Subject: [llvm-commits] [llvm] r147008 - in /llvm/trunk: lib/Target/Mips/MipsISelDAGToDAG.cpp test/CodeGen/Mips/mips64muldiv.ll Message-ID: <20111220231057.6CE0D2A6C12C@llvm.org> Author: ahatanak Date: Tue Dec 20 17:10:57 2011 New Revision: 147008 URL: http://llvm.org/viewvc/llvm-project?rev=147008&view=rev Log: Add function MipsDAGToDAGISel::SelectMULT and factor out code that generates nodes needed for multiplication. Add code for selecting 64-bit MULHS and MULHU nodes. Modified: llvm/trunk/lib/Target/Mips/MipsISelDAGToDAG.cpp llvm/trunk/test/CodeGen/Mips/mips64muldiv.ll Modified: llvm/trunk/lib/Target/Mips/MipsISelDAGToDAG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsISelDAGToDAG.cpp?rev=147008&r1=147007&r2=147008&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/MipsISelDAGToDAG.cpp (original) +++ llvm/trunk/lib/Target/Mips/MipsISelDAGToDAG.cpp Tue Dec 20 17:10:57 2011 @@ -81,6 +81,10 @@ } SDNode *getGlobalBaseReg(); + + std::pair SelectMULT(SDNode *N, unsigned Opc, DebugLoc dl, + EVT Ty, bool HasLo, bool HasHi); + SDNode *Select(SDNode *N); // Complex Pattern. @@ -176,6 +180,28 @@ return true; } +/// Select multiply instructions. +std::pair +MipsDAGToDAGISel::SelectMULT(SDNode *N, unsigned Opc, DebugLoc dl, EVT Ty, + bool HasLo, bool HasHi) { + SDNode *Lo, *Hi; + SDNode *Mul = CurDAG->getMachineNode(Opc, dl, MVT::Glue, N->getOperand(0), + N->getOperand(1)); + SDValue InFlag = SDValue(Mul, 0); + + if (HasLo) { + Lo = CurDAG->getMachineNode(Ty == MVT::i32 ? Mips::MFLO : Mips::MFLO64, dl, + Ty, MVT::Glue, InFlag); + InFlag = SDValue(Lo, 1); + } + if (HasHi) + Hi = CurDAG->getMachineNode(Ty == MVT::i32 ? Mips::MFHI : Mips::MFHI64, dl, + Ty, InFlag); + + return std::make_pair(Lo, Hi); +} + + /// Select instructions not customized! Used for /// expanded, promoted and normal instructions SDNode* MipsDAGToDAGISel::Select(SDNode *Node) { @@ -195,6 +221,9 @@ // Instruction Selection not handled by the auto-generated // tablegen selection should be handled here. /// + EVT NodeTy = Node->getValueType(0); + unsigned MultOpc; + switch(Opcode) { default: break; @@ -232,58 +261,39 @@ /// Mul with two results case ISD::SMUL_LOHI: case ISD::UMUL_LOHI: { - assert(Node->getValueType(0) != MVT::i64 && - "64-bit multiplication with two results not handled."); - SDValue Op1 = Node->getOperand(0); - SDValue Op2 = Node->getOperand(1); - - unsigned Op; - Op = (Opcode == ISD::UMUL_LOHI ? Mips::MULTu : Mips::MULT); - - SDNode *Mul = CurDAG->getMachineNode(Op, dl, MVT::Glue, Op1, Op2); - - SDValue InFlag = SDValue(Mul, 0); - SDNode *Lo = CurDAG->getMachineNode(Mips::MFLO, dl, MVT::i32, - MVT::Glue, InFlag); - InFlag = SDValue(Lo,1); - SDNode *Hi = CurDAG->getMachineNode(Mips::MFHI, dl, MVT::i32, InFlag); + if (NodeTy == MVT::i32) + MultOpc = (Opcode == ISD::UMUL_LOHI ? Mips::MULTu : Mips::MULT); + else + MultOpc = (Opcode == ISD::UMUL_LOHI ? Mips::DMULTu : Mips::DMULT); + + std::pair LoHi = SelectMULT(Node, MultOpc, dl, NodeTy, + true, true); if (!SDValue(Node, 0).use_empty()) - ReplaceUses(SDValue(Node, 0), SDValue(Lo,0)); + ReplaceUses(SDValue(Node, 0), SDValue(LoHi.first, 0)); if (!SDValue(Node, 1).use_empty()) - ReplaceUses(SDValue(Node, 1), SDValue(Hi,0)); + ReplaceUses(SDValue(Node, 1), SDValue(LoHi.second, 0)); return NULL; } /// Special Muls - case ISD::MUL: + case ISD::MUL: { // Mips32 has a 32-bit three operand mul instruction. - if (Subtarget.hasMips32() && Node->getValueType(0) == MVT::i32) + if (Subtarget.hasMips32() && NodeTy == MVT::i32) break; + return SelectMULT(Node, NodeTy == MVT::i32 ? Mips::MULT : Mips::DMULT, + dl, NodeTy, true, false).first; + } case ISD::MULHS: case ISD::MULHU: { - assert((Opcode == ISD::MUL || Node->getValueType(0) != MVT::i64) && - "64-bit MULH* not handled."); - EVT Ty = Node->getValueType(0); - SDValue MulOp1 = Node->getOperand(0); - SDValue MulOp2 = Node->getOperand(1); - - unsigned MulOp = (Opcode == ISD::MULHU ? - Mips::MULTu : - (Ty == MVT::i32 ? Mips::MULT : Mips::DMULT)); - SDNode *MulNode = CurDAG->getMachineNode(MulOp, dl, - MVT::Glue, MulOp1, MulOp2); - - SDValue InFlag = SDValue(MulNode, 0); - - if (Opcode == ISD::MUL) { - unsigned Opc = (Ty == MVT::i32 ? Mips::MFLO : Mips::MFLO64); - return CurDAG->getMachineNode(Opc, dl, Ty, InFlag); - } + if (NodeTy == MVT::i32) + MultOpc = (Opcode == ISD::MULHU ? Mips::MULTu : Mips::MULT); else - return CurDAG->getMachineNode(Mips::MFHI, dl, MVT::i32, InFlag); + MultOpc = (Opcode == ISD::MULHU ? Mips::DMULTu : Mips::DMULT); + + return SelectMULT(Node, MultOpc, dl, NodeTy, false, true).second; } // Get target GOT address. Modified: llvm/trunk/test/CodeGen/Mips/mips64muldiv.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/mips64muldiv.ll?rev=147008&r1=147007&r2=147008&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/Mips/mips64muldiv.ll (original) +++ llvm/trunk/test/CodeGen/Mips/mips64muldiv.ll Tue Dec 20 17:10:57 2011 @@ -8,6 +8,14 @@ ret i64 %mul } +define i64 @m1(i64 %a) nounwind readnone { +entry: +; CHECK: dmult +; CHECK: mfhi + %div = sdiv i64 %a, 3 + ret i64 %div +} + define i64 @d0(i64 %a0, i64 %a1) nounwind readnone { entry: ; CHECK: ddivu From grosbach at apple.com Tue Dec 20 17:11:01 2011 From: grosbach at apple.com (Jim Grosbach) Date: Tue, 20 Dec 2011 23:11:01 -0000 Subject: [llvm-commits] [llvm] r147009 - /llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Message-ID: <20111220231101.32FB52A6C12C@llvm.org> Author: grosbach Date: Tue Dec 20 17:11:00 2011 New Revision: 147009 URL: http://llvm.org/viewvc/llvm-project?rev=147009&view=rev Log: ARM .req register name aliases are case insensitive, just like regnames. Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp?rev=147009&r1=147008&r2=147009&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp (original) +++ llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Tue Dec 20 17:11:00 2011 @@ -2325,9 +2325,10 @@ .Default(0); } if (!RegNum) { - // Check for aliases registered via .req. - StringMap::const_iterator Entry = - RegisterReqs.find(Tok.getIdentifier()); + // Check for aliases registered via .req. Canonicalize to lower case. + // That's more consistent since register names are case insensitive, and + // it's how the original entry was passed in from MC/MCParser/AsmParser. + StringMap::const_iterator Entry = RegisterReqs.find(lowerCase); // If no match, return failure. if (Entry == RegisterReqs.end()) return -1; From chandlerc at google.com Tue Dec 20 17:16:35 2011 From: chandlerc at google.com (Chandler Carruth) Date: Tue, 20 Dec 2011 15:16:35 -0800 Subject: [llvm-commits] PATCH: remove unused variable TheError In-Reply-To: References: Message-ID: On Tue, Dec 20, 2011 at 6:54 AM, Manuel Klimek wrote: > While searching for an example to model my use of SourceMgr after, I > stumbled over LLLexer.h and found what looks like an unused variable - > this patch would remove it, if there's not some hidden use of TheError > that I'm missing. > Looks good. As long as this kind of change doesn't break the build in some way, always feel free to commit as "obvious". > > diff --git a/lib/AsmParser/LLLexer.h b/lib/AsmParser/LLLexer.h > index 33b9135..09aea5b 100644 > --- a/lib/AsmParser/LLLexer.h > +++ b/lib/AsmParser/LLLexer.h > @@ -42,7 +42,6 @@ namespace llvm { > APFloat APFloatVal; > APSInt APSIntVal; > > - std::string TheError; > public: > explicit LLLexer(MemoryBuffer *StartBuf, SourceMgr &SM, SMDiagnostic &, > LLVMContext &C); > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits > -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20111220/503fabca/attachment.html From sabre at nondot.org Tue Dec 20 17:14:57 2011 From: sabre at nondot.org (Chris Lattner) Date: Tue, 20 Dec 2011 23:14:57 -0000 Subject: [llvm-commits] [llvm] r147010 - /llvm/trunk/lib/Linker/LinkModules.cpp Message-ID: <20111220231457.AE3482A6C12C@llvm.org> Author: lattner Date: Tue Dec 20 17:14:57 2011 New Revision: 147010 URL: http://llvm.org/viewvc/llvm-project?rev=147010&view=rev Log: Fix a nasty bug in the type remapping stuff that I added that is breaking kc++ on the build bot in some cases. The basic issue happens when a source module contains both a "%foo" type and a "%foo.42" type. It will see the later one, check to see if the destination module contains a "%foo" type, and it will return true... because both the source and destination modules are in the same LLVMContext. We don't want to map source types to other source types, so don't do the remapping if the mapped type came from the source module. Unfortunately, I've been unable to reduce a decent testcase for this, kc++ is pretty great that way. Modified: llvm/trunk/lib/Linker/LinkModules.cpp Modified: llvm/trunk/lib/Linker/LinkModules.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Linker/LinkModules.cpp?rev=147010&r1=147009&r2=147010&view=diff ============================================================================== --- llvm/trunk/lib/Linker/LinkModules.cpp (original) +++ llvm/trunk/lib/Linker/LinkModules.cpp Tue Dec 20 17:14:57 2011 @@ -148,6 +148,7 @@ if (PointerType *PT = dyn_cast(DstTy)) { if (PT->getAddressSpace() != cast(SrcTy)->getAddressSpace()) return false; + } else if (FunctionType *FT = dyn_cast(DstTy)) { if (FT->isVarArg() != cast(SrcTy)->isVarArg()) return false; @@ -567,6 +568,9 @@ std::vector SrcStructTypes; SrcM->findUsedStructTypes(SrcStructTypes); + SmallPtrSet SrcStructTypesSet(SrcStructTypes.begin(), + SrcStructTypes.end()); + for (unsigned i = 0, e = SrcStructTypes.size(); i != e; ++i) { StructType *ST = SrcStructTypes[i]; if (!ST->hasName()) continue; @@ -579,7 +583,10 @@ // Check to see if the destination module has a struct with the prefix name. if (StructType *DST = DstM->getTypeByName(ST->getName().substr(0, DotPos))) - TypeMap.addTypeMapping(DST, ST); + // Don't use it if this actually came from the source module. They're in + // the same LLVMContext after all. + if (!SrcStructTypesSet.count(DST)) + TypeMap.addTypeMapping(DST, ST); } From grosbach at apple.com Tue Dec 20 17:20:00 2011 From: grosbach at apple.com (Jim Grosbach) Date: Tue, 20 Dec 2011 23:20:00 -0000 Subject: [llvm-commits] [llvm] r147011 - /llvm/trunk/test/MC/ARM/neont2-mul-encoding.s Message-ID: <20111220232000.9ADDF2A6C12C@llvm.org> Author: grosbach Date: Tue Dec 20 17:20:00 2011 New Revision: 147011 URL: http://llvm.org/viewvc/llvm-project?rev=147011&view=rev Log: Enable and fix a test. Modified: llvm/trunk/test/MC/ARM/neont2-mul-encoding.s Modified: llvm/trunk/test/MC/ARM/neont2-mul-encoding.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/neont2-mul-encoding.s?rev=147011&r1=147010&r2=147011&view=diff ============================================================================== --- llvm/trunk/test/MC/ARM/neont2-mul-encoding.s (original) +++ llvm/trunk/test/MC/ARM/neont2-mul-encoding.s Tue Dec 20 17:20:00 2011 @@ -70,9 +70,9 @@ vqdmull.s16 q8, d16, d17 vqdmull.s32 q8, d16, d17 -@ vqdmull.s16 q1, d7, d1[1] + vqdmull.s16 q1, d7, d1[1] @ CHECK: vqdmull.s16 q8, d16, d17 @ encoding: [0xd0,0xef,0xa1,0x0d] @ CHECK: vqdmull.s32 q8, d16, d17 @ encoding: [0xe0,0xef,0xa1,0x0d] -@ FIXME: vqdmull.s16 q1, d7, d1[1] @ encoding: [0x97,0xef,0x49,0x3b] +@ CHECK: vqdmull.s16 q1, d7, d1[1] @ encoding: [0x97,0xef,0x49,0x2b] From James.Molloy at arm.com Tue Dec 20 17:30:07 2011 From: James.Molloy at arm.com (James Molloy) Date: Tue, 20 Dec 2011 23:30:07 +0000 Subject: [llvm-commits] PATCH: remove unused variable TheError In-Reply-To: References: , Message-ID: Manuel, Do you have commit access? If not, I can commit for you. James ________________________________________ From: llvm-commits-bounces at cs.uiuc.edu [llvm-commits-bounces at cs.uiuc.edu] On Behalf Of Chandler Carruth [chandlerc at google.com] Sent: 20 December 2011 23:16 To: Manuel Klimek Cc: llvm-commits at cs.uiuc.edu Subject: Re: [llvm-commits] PATCH: remove unused variable TheError On Tue, Dec 20, 2011 at 6:54 AM, Manuel Klimek > wrote: While searching for an example to model my use of SourceMgr after, I stumbled over LLLexer.h and found what looks like an unused variable - this patch would remove it, if there's not some hidden use of TheError that I'm missing. Looks good. As long as this kind of change doesn't break the build in some way, always feel free to commit as "obvious". diff --git a/lib/AsmParser/LLLexer.h b/lib/AsmParser/LLLexer.h index 33b9135..09aea5b 100644 --- a/lib/AsmParser/LLLexer.h +++ b/lib/AsmParser/LLLexer.h @@ -42,7 +42,6 @@ namespace llvm { APFloat APFloatVal; APSInt APSIntVal; - std::string TheError; public: explicit LLLexer(MemoryBuffer *StartBuf, SourceMgr &SM, SMDiagnostic &, LLVMContext &C); _______________________________________________ llvm-commits mailing list llvm-commits at cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits -- IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you. From ahatanaka at mips.com Tue Dec 20 17:28:36 2011 From: ahatanaka at mips.com (Akira Hatanaka) Date: Tue, 20 Dec 2011 23:28:36 -0000 Subject: [llvm-commits] [llvm] r147012 - /llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp Message-ID: <20111220232836.6AE2C2A6C12C@llvm.org> Author: ahatanak Date: Tue Dec 20 17:28:36 2011 New Revision: 147012 URL: http://llvm.org/viewvc/llvm-project?rev=147012&view=rev Log: Set the correct stack pointer register that should be saved or restored. Modified: llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp Modified: llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp?rev=147012&r1=147011&r2=147012&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp (original) +++ llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp Tue Dec 20 17:28:36 2011 @@ -231,7 +231,7 @@ setMinFunctionAlignment(2); - setStackPointerRegisterToSaveRestore(Mips::SP); + setStackPointerRegisterToSaveRestore(HasMips64 ? Mips::SP_64 : Mips::SP); computeRegisterProperties(); setExceptionPointerRegister(Mips::A0); From jvoung at google.com Tue Dec 20 17:35:10 2011 From: jvoung at google.com (Jan Voung) Date: Tue, 20 Dec 2011 15:35:10 -0800 Subject: [llvm-commits] patch for "puzzle" in llvm-test suite -- use of rand (PR11629) Message-ID: For http://llvm.org/bugs/show_bug.cgi?id=11629 See attached patch. -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20111220/191e388e/attachment.html -------------- next part -------------- A non-text attachment was scrubbed... Name: puzzle_test.patch Type: text/x-patch Size: 1535 bytes Desc: not available Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20111220/191e388e/attachment.bin From ahatanaka at mips.com Tue Dec 20 17:35:46 2011 From: ahatanaka at mips.com (Akira Hatanaka) Date: Tue, 20 Dec 2011 23:35:46 -0000 Subject: [llvm-commits] [llvm] r147013 - /llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp Message-ID: <20111220233547.01D8F2A6C12C@llvm.org> Author: ahatanak Date: Tue Dec 20 17:35:46 2011 New Revision: 147013 URL: http://llvm.org/viewvc/llvm-project?rev=147013&view=rev Log: Enable custom lowering DYNAMIC_STACKALLOC nodes. Modified: llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp Modified: llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp?rev=147013&r1=147012&r2=147013&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp (original) +++ llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp Tue Dec 20 17:35:46 2011 @@ -136,6 +136,7 @@ setOperationAction(ISD::SELECT, MVT::i32, Custom); setOperationAction(ISD::BRCOND, MVT::Other, Custom); setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Custom); + setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Custom); setOperationAction(ISD::VASTART, MVT::Other, Custom); setOperationAction(ISD::SDIV, MVT::i32, Expand); From ahatanaka at mips.com Tue Dec 20 17:40:56 2011 From: ahatanaka at mips.com (Akira Hatanaka) Date: Tue, 20 Dec 2011 23:40:56 -0000 Subject: [llvm-commits] [llvm] r147014 - /llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp Message-ID: <20111220234056.69D132A6C12C@llvm.org> Author: ahatanak Date: Tue Dec 20 17:40:56 2011 New Revision: 147014 URL: http://llvm.org/viewvc/llvm-project?rev=147014&view=rev Log: 64-bit uint-fp conversion nodes are expanded. Modified: llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp Modified: llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp?rev=147014&r1=147013&r2=147014&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp (original) +++ llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp Tue Dec 20 17:40:56 2011 @@ -153,7 +153,9 @@ setOperationAction(ISD::BR_CC, MVT::Other, Expand); setOperationAction(ISD::SELECT_CC, MVT::Other, Expand); setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand); + setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand); setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand); + setOperationAction(ISD::FP_TO_UINT, MVT::i64, Expand); setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand); setOperationAction(ISD::CTPOP, MVT::i32, Expand); setOperationAction(ISD::CTTZ, MVT::i32, Expand); From ahatanaka at mips.com Tue Dec 20 17:47:45 2011 From: ahatanaka at mips.com (Akira Hatanaka) Date: Tue, 20 Dec 2011 23:47:45 -0000 Subject: [llvm-commits] [llvm] r147015 - in /llvm/trunk/lib/Target/Mips: Mips.td MipsInstrInfo.td Message-ID: <20111220234745.1A5E72A6C12C@llvm.org> Author: ahatanak Date: Tue Dec 20 17:47:44 2011 New Revision: 147015 URL: http://llvm.org/viewvc/llvm-project?rev=147015&view=rev Log: Add definition of WSBH (Word Swap Bytes within Halfwords), which is an instruction supported by mips32r2, and add a pattern which replaces bswap with a ROTR and WSBH pair. WSBW is removed since it is not an instruction the current architectures support. Modified: llvm/trunk/lib/Target/Mips/Mips.td llvm/trunk/lib/Target/Mips/MipsInstrInfo.td Modified: llvm/trunk/lib/Target/Mips/Mips.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/Mips.td?rev=147015&r1=147014&r2=147015&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/Mips.td (original) +++ llvm/trunk/lib/Target/Mips/Mips.td Tue Dec 20 17:47:44 2011 @@ -63,7 +63,7 @@ [FeatureCondMov, FeatureBitCount]>; def FeatureMips32r2 : SubtargetFeature<"mips32r2", "MipsArchVersion", "Mips32r2", "Mips32r2 ISA Support", - [FeatureMips32, FeatureSEInReg]>; + [FeatureMips32, FeatureSEInReg, FeatureSwap]>; def FeatureMips64 : SubtargetFeature<"mips64", "MipsArchVersion", "Mips64", "Mips64 ISA Support", [FeatureGP64Bit, FeatureFP64Bit, Modified: llvm/trunk/lib/Target/Mips/MipsInstrInfo.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsInstrInfo.td?rev=147015&r1=147014&r2=147015&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/MipsInstrInfo.td (original) +++ llvm/trunk/lib/Target/Mips/MipsInstrInfo.td Tue Dec 20 17:47:44 2011 @@ -625,11 +625,10 @@ let Predicates = [HasSEInReg]; } -// Byte Swap -class ByteSwap func, bits<5> sa, string instr_asm>: - FR<0x1f, func, (outs CPURegs:$rd), (ins CPURegs:$rt), - !strconcat(instr_asm, "\t$rd, $rt"), - [(set CPURegs:$rd, (bswap CPURegs:$rt))], NoItinerary> { +// Subword Swap +class SubwordSwap func, bits<5> sa, string instr_asm, RegisterClass RC>: + FR<0x1f, func, (outs RC:$rd), (ins RC:$rt), + !strconcat(instr_asm, "\t$rd, $rt"), [], NoItinerary> { let rs = 0; let shamt = sa; let Predicates = [HasSwap]; @@ -895,8 +894,8 @@ def CLZ : CountLeading0<0x20, "clz", CPURegs>; def CLO : CountLeading1<0x21, "clo", CPURegs>; -/// Byte Swap -def WSBW : ByteSwap<0x20, 0x2, "wsbw">; +/// Word Swap Bytes Within Halfwords +def WSBH : SubwordSwap<0x20, 0x2, "wsbh", CPURegs>; /// No operation let addr=0 in @@ -1104,6 +1103,9 @@ // select MipsDynAlloc def : Pat<(MipsDynAlloc addr:$f), (DynAlloc addr:$f)>; +// bswap pattern +def : Pat<(bswap CPURegs:$rt), (ROTR (WSBH CPURegs:$rt), 16)>; + //===----------------------------------------------------------------------===// // Floating Point Support //===----------------------------------------------------------------------===// From dpatel at apple.com Tue Dec 20 17:52:41 2011 From: dpatel at apple.com (Devang Patel) Date: Tue, 20 Dec 2011 15:52:41 -0800 Subject: [llvm-commits] [llvm] r146604 - in /llvm/trunk: lib/CodeGen/MachineSink.cpp test/CodeGen/ARM/2011-12-14-machine-sink.ll In-Reply-To: References: <20111214232038.E9C9D2A6C12C@llvm.org> <5FF21D31-13D7-4EAA-99FC-EFC1AFA0C8F7@apple.com> <618FAA67-0A0A-4D20-9E58-491632F2BA7C@apple.com> Message-ID: <91FF2423-D67D-4E80-985B-532E27DF3799@apple.com> Akira, On Dec 20, 2011, at 11:39 AM, Akira Hatanaka wrote: > After further investigation, I found a function that is possibly being > mis-compiled. This is what I did: > > 1. Reverted this patch (machine sinking is less conservative now). > 2. Turned off machine sinking just for the function. > > The generated executable segfaults when it is run. > > Additionally, I found that it produces the expected result and > terminates normally if I add the option "-regalloc=basic" to llc to > turn off greedy register allocation. > > Is there anything you can tell from this? Which part of the output > should I pay attention to when I am reading llc's outputs when option > -debug or -stats is provided? The function in question is fairly large > and complicated, so it is difficult to tell which part is being > mis-compiled just by looking at the machinefunction dumps or the CFGs > viewCFG and viewCFGOnly show. One alternative for you is to reproduce segfault in debugger and investigate what is being compiled. Other alternative is to narrow down the particular MI sink that is difference maker. You can do this by disabling this patch and adding a artificial threshold in Machine Sink pass to control how many instructions are sinked. One you know the critical MI sink, you can investigate how it impacts other passes, including register allocator, down the road. I am afraid, there is not any easy answer. - Devang > > On Fri, Dec 16, 2011 at 3:50 PM, Devang Patel wrote: >> >> On Dec 16, 2011, at 2:34 PM, Akira Hatanaka wrote: >> >>> The test still fails after I disable Machine Sink pass, but it passes >>> if I revert the patch (just this one, the ones checked in after this >>> remain applied). So it looks like MachineSinking is not causing the >>> failure, but there is a bug in some other part of the backend that >>> gets exposed if the pass doesn't sink instructions at all or is less >>> aggresive. >>> >>> Do you have any idea which pass might be doing something wrong? >> >> >> In the test case, which prompted this patch, machine sink pass was increasing distance between reg def and use resulting in unnecessary extra spill. >> >> However, in your particular case I have no idea what is going wrong. Finding out what exactly is miscompiled may be your best alternative. Do you see any significant (or noticeable) changes in stats for passes that follow machine sink ? >>> >>> Here are the stats: >>> >>> (before) >>> 15 machine-sink - Number of copies coalesced >>> 674 machine-sink - Number of critical edges split >>> 3397 machine-sink - Number of machine instructions sunk >>> >>> (after) >>> 15 machine-sink - Number of copies coalesced >>> 674 machine-sink - Number of critical edges split >>> 2881 machine-sink - Number of machine instructions sunk >>> >>> On Fri, Dec 16, 2011 at 9:21 AM, Devang Patel wrote: >>>> >>>> On Dec 15, 2011, at 7:55 PM, Akira Hatanaka wrote: >>>> >>>>> This commit is causing one the tests in llvm test-suite >>>>> (MultiSource/Benchmarks/tramp3d-v4) to fail. >>>>> It segfaults during execution. The target architecture is mips32r2. >>>>> >>>>> Would it be possible to revert this until we can figure out what is >>>>> causing the failure? >>>> >>>> This patch makes machine sink more conservative. Please, >>>> >>>> 1) Disable Machine Sink pass completely locally and see if the segfaults reproduces or not. >>>> 2) Enable stats and see if notice any change before and after the patch. >>>> 3) Please file bugzilla with a reproducible test case before reverting the patch. >>>> >>>> Thanks, >>>> - >>>> Devang >>>> >>>> >>>>> On Wed, Dec 14, 2011 at 3:20 PM, Devang Patel wrote: >>>>>> Author: dpatel >>>>>> Date: Wed Dec 14 17:20:38 2011 >>>>>> New Revision: 146604 >>>>>> >>>>>> URL: http://llvm.org/viewvc/llvm-project?rev=146604&view=rev >>>>>> Log: >>>>>> Do not sink instruction, if it is not profitable. >>>>>> >>>>>> On ARM, peephole optimization for ABS creates a trivial cfg triangle which tempts machine sink to sink instructions in code which is really straight line code. Sometimes this sinking may alter register allocator input such that use and def of a reg is divided by a branch in between, which may result in extra spills. Now mahine sink avoids sinking if final sink destination is post dominator. >>>>>> >>>>>> Radar 10266272. >>>>>> >>>>>> Added: >>>>>> llvm/trunk/test/CodeGen/ARM/2011-12-14-machine-sink.ll >>>>>> Modified: >>>>>> llvm/trunk/lib/CodeGen/MachineSink.cpp >>>>>> >>>>>> Modified: llvm/trunk/lib/CodeGen/MachineSink.cpp >>>>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineSink.cpp?rev=146604&r1=146603&r2=146604&view=diff >>>>>> ============================================================================== >>>>>> --- llvm/trunk/lib/CodeGen/MachineSink.cpp (original) >>>>>> +++ llvm/trunk/lib/CodeGen/MachineSink.cpp Wed Dec 14 17:20:38 2011 >>>>>> @@ -90,7 +90,11 @@ >>>>>> bool AllUsesDominatedByBlock(unsigned Reg, MachineBasicBlock *MBB, >>>>>> MachineBasicBlock *DefMBB, >>>>>> bool &BreakPHIEdge, bool &LocalUse) const; >>>>>> - MachineBasicBlock *FindSuccToSinkTo(MachineInstr *MI, bool &BreakPHIEdge); >>>>>> + MachineBasicBlock *FindSuccToSinkTo(MachineInstr *MI, MachineBasicBlock *MBB, >>>>>> + bool &BreakPHIEdge); >>>>>> + bool isProfitableToSinkTo(unsigned Reg, MachineInstr *MI, >>>>>> + MachineBasicBlock *MBB, >>>>>> + MachineBasicBlock *SuccToSinkTo); >>>>>> >>>>>> bool PerformTrivialForwardCoalescing(MachineInstr *MI, >>>>>> MachineBasicBlock *MBB); >>>>>> @@ -399,18 +403,76 @@ >>>>>> } >>>>>> } >>>>>> >>>>>> +/// isPostDominatedBy - Return true if A is post dominated by B. >>>>>> +static bool isPostDominatedBy(MachineBasicBlock *A, MachineBasicBlock *B) { >>>>>> + >>>>>> + // FIXME - Use real post dominator. >>>>>> + if (A->succ_size() != 2) >>>>>> + return false; >>>>>> + MachineBasicBlock::succ_iterator I = A->succ_begin(); >>>>>> + if (B == *I) >>>>>> + ++I; >>>>>> + MachineBasicBlock *OtherSuccBlock = *I; >>>>>> + if (OtherSuccBlock->succ_size() != 1 || >>>>>> + *(OtherSuccBlock->succ_begin()) != B) >>>>>> + return false; >>>>>> + >>>>>> + return true; >>>>>> +} >>>>>> + >>>>>> +/// isProfitableToSinkTo - Return true if it is profitable to sink MI. >>>>>> +bool MachineSinking::isProfitableToSinkTo(unsigned Reg, MachineInstr *MI, >>>>>> + MachineBasicBlock *MBB, >>>>>> + MachineBasicBlock *SuccToSinkTo) { >>>>>> + assert (MI && "Invalid MachineInstr!"); >>>>>> + assert (SuccToSinkTo && "Invalid SinkTo Candidate BB"); >>>>>> + >>>>>> + if (MBB == SuccToSinkTo) >>>>>> + return false; >>>>>> + >>>>>> + // It is profitable if SuccToSinkTo does not post dominate current block. >>>>>> + if (!isPostDominatedBy(MBB, SuccToSinkTo)) >>>>>> + return true; >>>>>> + >>>>>> + // Check if only use in post dominated block is PHI instruction. >>>>>> + bool NonPHIUse = false; >>>>>> + for (MachineRegisterInfo::use_nodbg_iterator >>>>>> + I = MRI->use_nodbg_begin(Reg), E = MRI->use_nodbg_end(); >>>>>> + I != E; ++I) { >>>>>> + MachineInstr *UseInst = &*I; >>>>>> + MachineBasicBlock *UseBlock = UseInst->getParent(); >>>>>> + if (UseBlock == SuccToSinkTo && !UseInst->isPHI()) >>>>>> + NonPHIUse = true; >>>>>> + } >>>>>> + if (!NonPHIUse) >>>>>> + return true; >>>>>> + >>>>>> + // If SuccToSinkTo post dominates then also it may be profitable if MI >>>>>> + // can further profitably sinked into another block in next round. >>>>>> + bool BreakPHIEdge = false; >>>>>> + // FIXME - If finding successor is compile time expensive then catch results. >>>>>> + if (MachineBasicBlock *MBB2 = FindSuccToSinkTo(MI, SuccToSinkTo, BreakPHIEdge)) >>>>>> + return isProfitableToSinkTo(Reg, MI, SuccToSinkTo, MBB2); >>>>>> + >>>>>> + // If SuccToSinkTo is final destination and it is a post dominator of current >>>>>> + // block then it is not profitable to sink MI into SuccToSinkTo block. >>>>>> + return false; >>>>>> +} >>>>>> + >>>>>> /// FindSuccToSinkTo - Find a successor to sink this instruction to. >>>>>> MachineBasicBlock *MachineSinking::FindSuccToSinkTo(MachineInstr *MI, >>>>>> - bool &BreakPHIEdge) { >>>>>> + MachineBasicBlock *MBB, >>>>>> + bool &BreakPHIEdge) { >>>>>> + >>>>>> + assert (MI && "Invalid MachineInstr!"); >>>>>> + assert (MBB && "Invalid MachineBasicBlock!"); >>>>>> >>>>>> // Loop over all the operands of the specified instruction. If there is >>>>>> // anything we can't handle, bail out. >>>>>> - MachineBasicBlock *ParentBlock = MI->getParent(); >>>>>> >>>>>> // SuccToSinkTo - This is the successor to sink this instruction to, once we >>>>>> // decide. >>>>>> MachineBasicBlock *SuccToSinkTo = 0; >>>>>> - >>>>>> for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { >>>>>> const MachineOperand &MO = MI->getOperand(i); >>>>>> if (!MO.isReg()) continue; // Ignore non-register operands. >>>>>> @@ -469,7 +531,7 @@ >>>>>> // If a previous operand picked a block to sink to, then this operand >>>>>> // must be sinkable to the same block. >>>>>> bool LocalUse = false; >>>>>> - if (!AllUsesDominatedByBlock(Reg, SuccToSinkTo, ParentBlock, >>>>>> + if (!AllUsesDominatedByBlock(Reg, SuccToSinkTo, MBB, >>>>>> BreakPHIEdge, LocalUse)) >>>>>> return NULL; >>>>>> >>>>>> @@ -478,11 +540,11 @@ >>>>>> >>>>>> // Otherwise, we should look at all the successors and decide which one >>>>>> // we should sink to. >>>>>> - for (MachineBasicBlock::succ_iterator SI = ParentBlock->succ_begin(), >>>>>> - E = ParentBlock->succ_end(); SI != E; ++SI) { >>>>>> - MachineBasicBlock *SuccBlock = *SI; >>>>>> + for (MachineBasicBlock::succ_iterator SI = MBB->succ_begin(), >>>>>> + E = MBB->succ_end(); SI != E; ++SI) { >>>>>> + MachineBasicBlock *SuccBlock = *SI; >>>>>> bool LocalUse = false; >>>>>> - if (AllUsesDominatedByBlock(Reg, SuccBlock, ParentBlock, >>>>>> + if (AllUsesDominatedByBlock(Reg, SuccBlock, MBB, >>>>>> BreakPHIEdge, LocalUse)) { >>>>>> SuccToSinkTo = SuccBlock; >>>>>> break; >>>>>> @@ -495,12 +557,14 @@ >>>>>> // If we couldn't find a block to sink to, ignore this instruction. >>>>>> if (SuccToSinkTo == 0) >>>>>> return NULL; >>>>>> + else if (!isProfitableToSinkTo(Reg, MI, MBB, SuccToSinkTo)) >>>>>> + return NULL; >>>>>> } >>>>>> } >>>>>> >>>>>> // It is not possible to sink an instruction into its own block. This can >>>>>> // happen with loops. >>>>>> - if (ParentBlock == SuccToSinkTo) >>>>>> + if (MBB == SuccToSinkTo) >>>>>> return NULL; >>>>>> >>>>>> // It's not safe to sink instructions to EH landing pad. Control flow into >>>>>> @@ -532,7 +596,8 @@ >>>>>> // and z and only shrink the live range of x. >>>>>> >>>>>> bool BreakPHIEdge = false; >>>>>> - MachineBasicBlock *SuccToSinkTo = FindSuccToSinkTo(MI, BreakPHIEdge); >>>>>> + MachineBasicBlock *ParentBlock = MI->getParent(); >>>>>> + MachineBasicBlock *SuccToSinkTo = FindSuccToSinkTo(MI, ParentBlock, BreakPHIEdge); >>>>>> >>>>>> // If there are no outputs, it must have side-effects. >>>>>> if (SuccToSinkTo == 0) >>>>>> @@ -553,8 +618,6 @@ >>>>>> >>>>>> DEBUG(dbgs() << "Sink instr " << *MI << "\tinto block " << *SuccToSinkTo); >>>>>> >>>>>> - MachineBasicBlock *ParentBlock = MI->getParent(); >>>>>> - >>>>>> // If the block has multiple predecessors, this would introduce computation on >>>>>> // a path that it doesn't already exist. We could split the critical edge, >>>>>> // but for now we just punt. >>>>>> >>>>>> Added: llvm/trunk/test/CodeGen/ARM/2011-12-14-machine-sink.ll >>>>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/2011-12-14-machine-sink.ll?rev=146604&view=auto >>>>>> ============================================================================== >>>>>> --- llvm/trunk/test/CodeGen/ARM/2011-12-14-machine-sink.ll (added) >>>>>> +++ llvm/trunk/test/CodeGen/ARM/2011-12-14-machine-sink.ll Wed Dec 14 17:20:38 2011 >>>>>> @@ -0,0 +1,48 @@ >>>>>> +; RUN: llc < %s -o /dev/null -stats |& FileCheck %s -check-prefix=STATS >>>>>> +; Radar 10266272 >>>>>> +target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:32:64-v128:32:128-a0:0:32-n32-S32" >>>>>> +target triple = "thumbv7-apple-ios4.0.0" >>>>>> +; STATS-NOT: machine-sink >>>>>> + >>>>>> +define i32 @foo(i32 %h) nounwind readonly ssp { >>>>>> +entry: >>>>>> + br label %for.cond >>>>>> + >>>>>> +for.cond: ; preds = %for.body, %entry >>>>>> + %cmp = icmp slt i32 0, %h >>>>>> + br i1 %cmp, label %for.body, label %if.end299 >>>>>> + >>>>>> +for.body: ; preds = %for.cond >>>>>> + %v.5 = select i1 undef, i32 undef, i32 0 >>>>>> + %0 = load i8* undef, align 1, !tbaa !0 >>>>>> + %conv88 = zext i8 %0 to i32 >>>>>> + %sub89 = sub nsw i32 0, %conv88 >>>>>> + %v.8 = select i1 undef, i32 undef, i32 %sub89 >>>>>> + %1 = load i8* null, align 1, !tbaa !0 >>>>>> + %conv108 = zext i8 %1 to i32 >>>>>> + %2 = load i8* undef, align 1, !tbaa !0 >>>>>> + %conv110 = zext i8 %2 to i32 >>>>>> + %sub111 = sub nsw i32 %conv108, %conv110 >>>>>> + %cmp112 = icmp slt i32 %sub111, 0 >>>>>> + %sub115 = sub nsw i32 0, %sub111 >>>>>> + %v.10 = select i1 %cmp112, i32 %sub115, i32 %sub111 >>>>>> + %add62 = add i32 0, %v.5 >>>>>> + %add73 = add i32 %add62, 0 >>>>>> + %add84 = add i32 %add73, 0 >>>>>> + %add95 = add i32 %add84, %v.8 >>>>>> + %add106 = add i32 %add95, 0 >>>>>> + %add117 = add i32 %add106, %v.10 >>>>>> + %add128 = add i32 %add117, 0 >>>>>> + %add139 = add i32 %add128, 0 >>>>>> + %add150 = add i32 %add139, 0 >>>>>> + %add161 = add i32 %add150, 0 >>>>>> + %add172 = add i32 %add161, 0 >>>>>> + br i1 undef, label %for.cond, label %if.end299 >>>>>> + >>>>>> +if.end299: ; preds = %for.body, %for.cond >>>>>> + %s.10 = phi i32 [ %add172, %for.body ], [ 0, %for.cond ] >>>>>> + ret i32 %s.10 >>>>>> +} >>>>>> + >>>>>> +!0 = metadata !{metadata !"omnipotent char", metadata !1} >>>>>> +!1 = metadata !{metadata !"Simple C/C++ TBAA", null} >>>>>> >>>>>> >>>>>> _______________________________________________ >>>>>> llvm-commits mailing list >>>>>> llvm-commits at cs.uiuc.edu >>>>>> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits >>>> >> From rafael.espindola at gmail.com Tue Dec 20 17:58:09 2011 From: rafael.espindola at gmail.com (=?UTF-8?B?UmFmYWVsIMOBdmlsYSBkZSBFc3DDrW5kb2xh?=) Date: Tue, 20 Dec 2011 18:58:09 -0500 Subject: [llvm-commits] [llvm] r146801 - in /llvm/trunk: include/llvm/MC/MCStreamer.h lib/CodeGen/AsmPrinter/AsmPrinterDwarf.cpp lib/MC/MCAsmStreamer.cpp lib/MC/MCLoggingStreamer.cpp lib/MC/MCNullStreamer.cpp lib/MC/MCParser/COFFAsmParser.cpp lib/MC/MCStr In-Reply-To: References: Message-ID: <4EF12111.2000806@gmail.com> > + > +#include "../Target/X86/MCTargetDesc/X86FixupKinds.h" > + > > > This is a pretty egregious layering violation. Please fix or revert, > this causes all kinds of problems with improper dependencies between > various components. This is not making library dependencies any worse: grep -r X86FixupKinds.h lib/MC/ lib/MC/ELFObjectWriter.cpp:#include "../Target/X86/MCTargetDesc/X86FixupKinds.h" lib/MC/WinCOFFStreamer.cpp:#include "../Target/X86/MCTargetDesc/X86FixupKinds.h" lib/MC/WinCOFFObjectWriter.cpp:#include "../Target/X86/MCTargetDesc/X86FixupKinds.h" I will take a look at this this week, but reverting this will break codegen of an empty main on windows with -g, so it seems like bit harsh for what it is. Cheers, Rafael From ahatanaka at mips.com Tue Dec 20 17:56:43 2011 From: ahatanaka at mips.com (Akira Hatanaka) Date: Tue, 20 Dec 2011 23:56:43 -0000 Subject: [llvm-commits] [llvm] r147017 - in /llvm/trunk/lib/Target/Mips: Mips64InstrInfo.td MipsISelLowering.cpp Message-ID: <20111220235643.BB0D52A6C12C@llvm.org> Author: ahatanak Date: Tue Dec 20 17:56:43 2011 New Revision: 147017 URL: http://llvm.org/viewvc/llvm-project?rev=147017&view=rev Log: Add definition of DSBH (Double Swap Bytes within Halfwords) and DSHD (Double Swap Halfwords within Doublewords). Add a pattern which replaces 64-bit bswap with a DSBH and DSHD pair. Modified: llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp Modified: llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td?rev=147017&r1=147016&r2=147017&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td (original) +++ llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td Tue Dec 20 17:56:43 2011 @@ -199,6 +199,10 @@ def DCLZ : CountLeading0<0x24, "dclz", CPU64Regs>; def DCLO : CountLeading1<0x25, "dclo", CPU64Regs>; +/// Double Word Swap Bytes/HalfWords +def DSBH : SubwordSwap<0x24, 0x2, "dsbh", CPU64Regs>; +def DSHD : SubwordSwap<0x24, 0x5, "dshd", CPU64Regs>; + def LEA_ADDiu64 : EffectiveAddress<"addiu\t$rt, $addr", CPU64Regs, mem_ea_64>; let Uses = [SP_64] in @@ -316,3 +320,5 @@ // Sign extend in register def : Pat<(i64 (sext_inreg CPU64Regs:$src, i32)), (SLL64_64 CPU64Regs:$src)>; +// bswap pattern +def : Pat<(bswap CPU64Regs:$rt), (DSHD (DSBH CPU64Regs:$rt))>; Modified: llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp?rev=147017&r1=147016&r2=147017&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp (original) +++ llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp Tue Dec 20 17:56:43 2011 @@ -221,8 +221,10 @@ if (!Subtarget->hasBitCount()) setOperationAction(ISD::CTLZ, MVT::i32, Expand); - if (!Subtarget->hasSwap()) + if (!Subtarget->hasSwap()) { setOperationAction(ISD::BSWAP, MVT::i32, Expand); + setOperationAction(ISD::BSWAP, MVT::i64, Expand); + } setTargetDAGCombine(ISD::ADDE); setTargetDAGCombine(ISD::SUBE); From ahatanaka at mips.com Tue Dec 20 17:58:37 2011 From: ahatanaka at mips.com (Akira Hatanaka) Date: Tue, 20 Dec 2011 23:58:37 -0000 Subject: [llvm-commits] [llvm] r147018 - /llvm/trunk/test/CodeGen/Mips/bswap.ll Message-ID: <20111220235837.0C02D2A6C12C@llvm.org> Author: ahatanak Date: Tue Dec 20 17:58:36 2011 New Revision: 147018 URL: http://llvm.org/viewvc/llvm-project?rev=147018&view=rev Log: Test case for r147017. Added: llvm/trunk/test/CodeGen/Mips/bswap.ll Added: llvm/trunk/test/CodeGen/Mips/bswap.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/bswap.ll?rev=147018&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/Mips/bswap.ll (added) +++ llvm/trunk/test/CodeGen/Mips/bswap.ll Tue Dec 20 17:58:36 2011 @@ -0,0 +1,25 @@ +; RUN: llc < %s -march=mipsel -mcpu=mips32r2 | FileCheck %s -check-prefix=MIPS32 +; RUN: llc < %s -march=mips64el -mcpu=mips64r2 | FileCheck %s -check-prefix=MIPS64 + +define i32 @bswap32(i32 %x) nounwind readnone { +entry: +; MIPS32: bswap32: +; MIPS32: wsbh $[[R0:[0-9]+]] +; MIPS32: rotr ${{[0-9]+}}, $[[R0]], 16 + %or.3 = call i32 @llvm.bswap.i32(i32 %x) + ret i32 %or.3 +} + +define i64 @bswap64(i64 %x) nounwind readnone { +entry: +; MIPS64: bswap64: +; MIPS64: dsbh $[[R0:[0-9]+]] +; MIPS64: dshd ${{[0-9]+}}, $[[R0]] + %or.7 = call i64 @llvm.bswap.i64(i64 %x) + ret i64 %or.7 +} + +declare i32 @llvm.bswap.i32(i32) nounwind readnone + +declare i64 @llvm.bswap.i64(i64) nounwind readnone + From ahatanaka at mips.com Tue Dec 20 18:02:58 2011 From: ahatanaka at mips.com (Akira Hatanaka) Date: Wed, 21 Dec 2011 00:02:58 -0000 Subject: [llvm-commits] [llvm] r147019 - /llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp Message-ID: <20111221000258.9C5342A6C12C@llvm.org> Author: ahatanak Date: Tue Dec 20 18:02:58 2011 New Revision: 147019 URL: http://llvm.org/viewvc/llvm-project?rev=147019&view=rev Log: Expand 64-bit atomic load and store. Modified: llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp Modified: llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp?rev=147019&r1=147018&r2=147019&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp (original) +++ llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp Tue Dec 20 18:02:58 2011 @@ -206,7 +206,9 @@ setOperationAction(ISD::ATOMIC_FENCE, MVT::Other, Custom); setOperationAction(ISD::ATOMIC_LOAD, MVT::i32, Expand); + setOperationAction(ISD::ATOMIC_LOAD, MVT::i64, Expand); setOperationAction(ISD::ATOMIC_STORE, MVT::i32, Expand); + setOperationAction(ISD::ATOMIC_STORE, MVT::i64, Expand); setInsertFencesForAtomic(true); From ahatanaka at mips.com Tue Dec 20 18:14:05 2011 From: ahatanaka at mips.com (Akira Hatanaka) Date: Wed, 21 Dec 2011 00:14:05 -0000 Subject: [llvm-commits] [llvm] r147021 - /llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp Message-ID: <20111221001405.6679D2A6C12C@llvm.org> Author: ahatanak Date: Tue Dec 20 18:14:05 2011 New Revision: 147021 URL: http://llvm.org/viewvc/llvm-project?rev=147021&view=rev Log: Expand 64-bit CTPOP and CTTZ. Modified: llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp Modified: llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp?rev=147021&r1=147020&r2=147021&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp (original) +++ llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp Tue Dec 20 18:14:05 2011 @@ -158,7 +158,9 @@ setOperationAction(ISD::FP_TO_UINT, MVT::i64, Expand); setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand); setOperationAction(ISD::CTPOP, MVT::i32, Expand); + setOperationAction(ISD::CTPOP, MVT::i64, Expand); setOperationAction(ISD::CTTZ, MVT::i32, Expand); + setOperationAction(ISD::CTTZ, MVT::i64, Expand); setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32, Expand); setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand); setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32, Expand); From ahatanaka at mips.com Tue Dec 20 18:20:28 2011 From: ahatanaka at mips.com (Akira Hatanaka) Date: Wed, 21 Dec 2011 00:20:28 -0000 Subject: [llvm-commits] [llvm] r147022 - in /llvm/trunk: lib/Target/Mips/MipsISelLowering.cpp test/CodeGen/Mips/mips64countleading.ll Message-ID: <20111221002028.1D5B12A6C12C@llvm.org> Author: ahatanak Date: Tue Dec 20 18:20:27 2011 New Revision: 147022 URL: http://llvm.org/viewvc/llvm-project?rev=147022&view=rev Log: Expand 64-bit CTLZ nodes if target architecture does not support it. Add test case for DCLO and DCLZ. Added: llvm/trunk/test/CodeGen/Mips/mips64countleading.ll Modified: llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp Modified: llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp?rev=147022&r1=147021&r2=147022&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp (original) +++ llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp Tue Dec 20 18:20:27 2011 @@ -222,8 +222,10 @@ setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand); } - if (!Subtarget->hasBitCount()) + if (!Subtarget->hasBitCount()) { setOperationAction(ISD::CTLZ, MVT::i32, Expand); + setOperationAction(ISD::CTLZ, MVT::i64, Expand); + } if (!Subtarget->hasSwap()) { setOperationAction(ISD::BSWAP, MVT::i32, Expand); Added: llvm/trunk/test/CodeGen/Mips/mips64countleading.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/mips64countleading.ll?rev=147022&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/Mips/mips64countleading.ll (added) +++ llvm/trunk/test/CodeGen/Mips/mips64countleading.ll Tue Dec 20 18:20:27 2011 @@ -0,0 +1,19 @@ +; RUN: llc -march=mips64el -mcpu=mips64 < %s | FileCheck %s + +define i64 @t1(i64 %X) nounwind readnone { +entry: +; CHECK: dclz + %tmp1 = tail call i64 @llvm.ctlz.i64(i64 %X, i1 true) + ret i64 %tmp1 +} + +declare i64 @llvm.ctlz.i64(i64, i1) nounwind readnone + +define i64 @t3(i64 %X) nounwind readnone { +entry: +; CHECK: dclo + %neg = xor i64 %X, -1 + %tmp1 = tail call i64 @llvm.ctlz.i64(i64 %neg, i1 true) + ret i64 %tmp1 +} + From ahatanaka at mips.com Tue Dec 20 18:31:10 2011 From: ahatanaka at mips.com (Akira Hatanaka) Date: Wed, 21 Dec 2011 00:31:10 -0000 Subject: [llvm-commits] [llvm] r147024 - in /llvm/trunk: lib/Target/Mips/MipsInstrInfo.td test/CodeGen/Mips/swzero.ll Message-ID: <20111221003110.C8BE92A6C12C@llvm.org> Author: ahatanak Date: Tue Dec 20 18:31:10 2011 New Revision: 147024 URL: http://llvm.org/viewvc/llvm-project?rev=147024&view=rev Log: Fix bug in zero-store peephole pattern reported in pr11615. The patch and test case were originally written by Mans Rullgard. Added: llvm/trunk/test/CodeGen/Mips/swzero.ll Modified: llvm/trunk/lib/Target/Mips/MipsInstrInfo.td Modified: llvm/trunk/lib/Target/Mips/MipsInstrInfo.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsInstrInfo.td?rev=147024&r1=147023&r2=147024&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/MipsInstrInfo.td (original) +++ llvm/trunk/lib/Target/Mips/MipsInstrInfo.td Tue Dec 20 18:31:10 2011 @@ -1022,10 +1022,14 @@ } // peepholes -def : Pat<(store (i32 0), addr:$dst), (SW ZERO, addr:$dst)>, - Requires<[NotN64]>; -def : Pat<(store (i32 0), addr:$dst), (SW_P8 ZERO, addr:$dst)>, - Requires<[IsN64]>; +let Predicates = [NotN64] in { + def : Pat<(store_a (i32 0), addr:$dst), (SW ZERO, addr:$dst)>; + def : Pat<(store_u (i32 0), addr:$dst), (USW ZERO, addr:$dst)>; +} +let Predicates = [IsN64] in { + def : Pat<(store_a (i32 0), addr:$dst), (SW_P8 ZERO, addr:$dst)>; + def : Pat<(store_u (i32 0), addr:$dst), (USW_P8 ZERO, addr:$dst)>; +} // brcond patterns multiclass BrcondPats + +define void @zero_u(%struct.unaligned* nocapture %p) nounwind { +entry: +; CHECK: usw $zero + %x = getelementptr inbounds %struct.unaligned* %p, i32 0, i32 0 + store i32 0, i32* %x, align 1 + ret void +} + +define void @zero_a(i32* nocapture %p) nounwind { +entry: +; CHECK: sw $zero + store i32 0, i32* %p, align 4 + ret void +} + From grosbach at apple.com Tue Dec 20 18:38:54 2011 From: grosbach at apple.com (Jim Grosbach) Date: Wed, 21 Dec 2011 00:38:54 -0000 Subject: [llvm-commits] [llvm] r147025 - in /llvm/trunk: lib/Target/ARM/ARMExpandPseudoInsts.cpp lib/Target/ARM/ARMInstrNEON.td lib/Target/ARM/AsmParser/ARMAsmParser.cpp lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp lib/Target/ARM/InstPrinter/ARMInstPrinter.h test/MC/ARM/neon-vld-encoding.s utils/TableGen/EDEmitter.cpp Message-ID: <20111221003854.DCFA32A6C12C@llvm.org> Author: grosbach Date: Tue Dec 20 18:38:54 2011 New Revision: 147025 URL: http://llvm.org/viewvc/llvm-project?rev=147025&view=rev Log: ARM NEON VLD2 assembly parsing for structure to all lanes, non-writeback. Modified: llvm/trunk/lib/Target/ARM/ARMExpandPseudoInsts.cpp llvm/trunk/lib/Target/ARM/ARMInstrNEON.td llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.h llvm/trunk/test/MC/ARM/neon-vld-encoding.s llvm/trunk/utils/TableGen/EDEmitter.cpp Modified: llvm/trunk/lib/Target/ARM/ARMExpandPseudoInsts.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMExpandPseudoInsts.cpp?rev=147025&r1=147024&r2=147025&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMExpandPseudoInsts.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMExpandPseudoInsts.cpp Tue Dec 20 18:38:54 2011 @@ -161,11 +161,11 @@ { ARM::VLD1q8PseudoWB_fixed, ARM::VLD1q8wb_fixed,true,false, false, SingleSpc, 2, 8 ,false}, { ARM::VLD1q8PseudoWB_register, ARM::VLD1q8wb_register,true,true, true,SingleSpc,2,8,false}, -{ ARM::VLD2DUPd16Pseudo, ARM::VLD2DUPd16, true, false, false, SingleSpc, 2, 4,true}, +{ ARM::VLD2DUPd16Pseudo, ARM::VLD2DUPd16, true, false, false, SingleSpc, 2, 4,false}, { ARM::VLD2DUPd16Pseudo_UPD, ARM::VLD2DUPd16_UPD, true, true, true, SingleSpc, 2, 4,true}, -{ ARM::VLD2DUPd32Pseudo, ARM::VLD2DUPd32, true, false, false, SingleSpc, 2, 2,true}, +{ ARM::VLD2DUPd32Pseudo, ARM::VLD2DUPd32, true, false, false, SingleSpc, 2, 2,false}, { ARM::VLD2DUPd32Pseudo_UPD, ARM::VLD2DUPd32_UPD, true, true, true, SingleSpc, 2, 2,true}, -{ ARM::VLD2DUPd8Pseudo, ARM::VLD2DUPd8, true, false, false, SingleSpc, 2, 8,true}, +{ ARM::VLD2DUPd8Pseudo, ARM::VLD2DUPd8, true, false, false, SingleSpc, 2, 8,false}, { ARM::VLD2DUPd8Pseudo_UPD, ARM::VLD2DUPd8_UPD, true, true, true, SingleSpc, 2, 8,true}, { ARM::VLD2LNd16Pseudo, ARM::VLD2LNd16, true, false, false, SingleSpc, 2, 4 ,true}, Modified: llvm/trunk/lib/Target/ARM/ARMInstrNEON.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrNEON.td?rev=147025&r1=147024&r2=147025&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrNEON.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrNEON.td Tue Dec 20 18:38:54 2011 @@ -143,6 +143,16 @@ def VecListTwoDAllLanes : RegisterOperand { let ParserMatchClass = VecListTwoDAllLanesAsmOperand; } +// Register list of two D registers spaced by 2 (two sequential Q registers). +def VecListTwoQAllLanesAsmOperand : AsmOperandClass { + let Name = "VecListTwoQAllLanes"; + let ParserMethod = "parseVectorList"; + let RenderMethod = "addVecListOperands"; +} +def VecListTwoQAllLanes : RegisterOperand { + let ParserMatchClass = VecListTwoQAllLanesAsmOperand; +} // Register list of one D register, with byte lane subscripting. def VecListOneDByteIndexAsmOperand : AsmOperandClass { @@ -1221,27 +1231,27 @@ def VLD1DUPq32PseudoWB_register : VLDQWBregisterPseudo; // VLD2DUP : Vector Load (single 2-element structure to all lanes) -class VLD2DUP op7_4, string Dt> - : NLdSt<1, 0b10, 0b1101, op7_4, (outs DPR:$Vd, DPR:$dst2), +class VLD2DUP op7_4, string Dt, RegisterOperand VdTy> + : NLdSt<1, 0b10, 0b1101, op7_4, (outs VdTy:$Vd), (ins addrmode6dup:$Rn), IIC_VLD2dup, - "vld2", Dt, "\\{$Vd[], $dst2[]\\}, $Rn", "", []> { + "vld2", Dt, "$Vd, $Rn", "", []> { let Rm = 0b1111; let Inst{4} = Rn{4}; let DecoderMethod = "DecodeVLD2DupInstruction"; } -def VLD2DUPd8 : VLD2DUP<{0,0,0,?}, "8">; -def VLD2DUPd16 : VLD2DUP<{0,1,0,?}, "16">; -def VLD2DUPd32 : VLD2DUP<{1,0,0,?}, "32">; +def VLD2DUPd8 : VLD2DUP<{0,0,0,?}, "8", VecListTwoDAllLanes>; +def VLD2DUPd16 : VLD2DUP<{0,1,0,?}, "16", VecListTwoDAllLanes>; +def VLD2DUPd32 : VLD2DUP<{1,0,0,?}, "32", VecListTwoDAllLanes>; def VLD2DUPd8Pseudo : VLDQPseudo; def VLD2DUPd16Pseudo : VLDQPseudo; def VLD2DUPd32Pseudo : VLDQPseudo; // ...with double-spaced registers (not used for codegen): -def VLD2DUPd8x2 : VLD2DUP<{0,0,1,?}, "8">; -def VLD2DUPd16x2 : VLD2DUP<{0,1,1,?}, "16">; -def VLD2DUPd32x2 : VLD2DUP<{1,0,1,?}, "32">; +def VLD2DUPd8x2 : VLD2DUP<{0,0,1,?}, "8", VecListTwoQAllLanes>; +def VLD2DUPd16x2 : VLD2DUP<{0,1,1,?}, "16", VecListTwoQAllLanes>; +def VLD2DUPd32x2 : VLD2DUP<{1,0,1,?}, "32", VecListTwoQAllLanes>; // ...with address register writeback: class VLD2DUPWB op7_4, string Dt> Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp?rev=147025&r1=147024&r2=147025&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp (original) +++ llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Tue Dec 20 18:38:54 2011 @@ -1118,13 +1118,24 @@ return VectorList.Count == 2; } + bool isSingleSpacedVectorAllLanes() const { + return Kind == k_VectorListAllLanes && !VectorList.isDoubleSpaced; + } + bool isDoubleSpacedVectorAllLanes() const { + return Kind == k_VectorListAllLanes && VectorList.isDoubleSpaced; + } bool isVecListOneDAllLanes() const { - if (Kind != k_VectorListAllLanes) return false; + if (!isSingleSpacedVectorAllLanes()) return false; return VectorList.Count == 1; } bool isVecListTwoDAllLanes() const { - if (Kind != k_VectorListAllLanes) return false; + if (!isSingleSpacedVectorAllLanes()) return false; + return VectorList.Count == 2; + } + + bool isVecListTwoQAllLanes() const { + if (!isDoubleSpacedVectorAllLanes()) return false; return VectorList.Count == 2; } @@ -2041,10 +2052,12 @@ } static ARMOperand *CreateVectorListAllLanes(unsigned RegNum, unsigned Count, + bool isDoubleSpaced, SMLoc S, SMLoc E) { ARMOperand *Op = new ARMOperand(k_VectorListAllLanes); Op->VectorList.RegNum = RegNum; Op->VectorList.Count = Count; + Op->VectorList.isDoubleSpaced = isDoubleSpaced; Op->StartLoc = S; Op->EndLoc = E; return Op; @@ -2865,7 +2878,8 @@ break; case AllLanes: E = Parser.getTok().getLoc(); - Operands.push_back(ARMOperand::CreateVectorListAllLanes(Reg, 1, S, E)); + Operands.push_back(ARMOperand::CreateVectorListAllLanes(Reg, 1, false, + S, E)); break; case IndexedLane: Operands.push_back(ARMOperand::CreateVectorListIndexed(Reg, 1, @@ -2889,7 +2903,8 @@ break; case AllLanes: E = Parser.getTok().getLoc(); - Operands.push_back(ARMOperand::CreateVectorListAllLanes(Reg, 2, S, E)); + Operands.push_back(ARMOperand::CreateVectorListAllLanes(Reg, 2, false, + S, E)); break; case IndexedLane: Operands.push_back(ARMOperand::CreateVectorListIndexed(Reg, 2, @@ -3060,6 +3075,7 @@ break; case AllLanes: Operands.push_back(ARMOperand::CreateVectorListAllLanes(FirstReg, Count, + (Spacing == 2), S, E)); break; case IndexedLane: Modified: llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp?rev=147025&r1=147024&r2=147025&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp (original) +++ llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp Tue Dec 20 18:38:54 2011 @@ -1066,3 +1066,13 @@ << getRegisterName(MI->getOperand(OpNum).getReg() + 2) << "}"; } +void ARMInstPrinter::printVectorListTwoSpacedAllLanes(const MCInst *MI, + unsigned OpNum, + raw_ostream &O) { + // Normally, it's not safe to use register enum values directly with + // addition to get the next register, but for VFP registers, the + // sort order is guaranteed because they're all of the form D. + O << "{" << getRegisterName(MI->getOperand(OpNum).getReg()) << "[], " + << getRegisterName(MI->getOperand(OpNum).getReg() + 2) << "[]}"; +} + Modified: llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.h?rev=147025&r1=147024&r2=147025&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.h (original) +++ llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.h Tue Dec 20 18:38:54 2011 @@ -139,6 +139,8 @@ raw_ostream &O); void printVectorListTwoSpaced(const MCInst *MI, unsigned OpNum, raw_ostream &O); + void printVectorListTwoSpacedAllLanes(const MCInst *MI, unsigned OpNum, + raw_ostream &O); }; } // end namespace llvm Modified: llvm/trunk/test/MC/ARM/neon-vld-encoding.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/neon-vld-encoding.s?rev=147025&r1=147024&r2=147025&view=diff ============================================================================== --- llvm/trunk/test/MC/ARM/neon-vld-encoding.s (original) +++ llvm/trunk/test/MC/ARM/neon-vld-encoding.s Tue Dec 20 18:38:54 2011 @@ -236,6 +236,8 @@ vld2.8 {d2[4], d3[4]}, [r2], r3 vld2.8 {d2[4], d3[4]}, [r2]! vld2.8 {d2[4], d3[4]}, [r2] + vld2.32 {d22[], d23[]}, [r1] + vld2.32 {d22[], d24[]}, [r1] @ CHECK: vld2.8 {d16[1], d17[1]}, [r0, :16] @ encoding: [0x3f,0x01,0xe0,0xf4] @ CHECK: vld2.16 {d16[1], d17[1]}, [r0, :32] @ encoding: [0x5f,0x05,0xe0,0xf4] @@ -246,7 +248,8 @@ @ CHECK: vld2.8 {d2[4], d3[4]}, [r2], r3 @ encoding: [0x83,0x21,0xa2,0xf4] @ CHECK: vld2.8 {d2[4], d3[4]}, [r2]! @ encoding: [0x8d,0x21,0xa2,0xf4] @ CHECK: vld2.8 {d2[4], d3[4]}, [r2] @ encoding: [0x8f,0x21,0xa2,0xf4] - +@ CHECK: vld2.32 {d22[], d23[]}, [r1] @ encoding: [0x8f,0x6d,0xe1,0xf4] +@ CHECK: vld2.32 {d22[], d24[]}, [r1] @ encoding: [0xaf,0x6d,0xe1,0xf4] @ vld3.8 {d16[1], d17[1], d18[1]}, [r0] Modified: llvm/trunk/utils/TableGen/EDEmitter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/EDEmitter.cpp?rev=147025&r1=147024&r2=147025&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/EDEmitter.cpp (original) +++ llvm/trunk/utils/TableGen/EDEmitter.cpp Tue Dec 20 18:38:54 2011 @@ -578,6 +578,7 @@ REG("VecListTwoQ"); REG("VecListOneDAllLanes"); REG("VecListTwoDAllLanes"); + REG("VecListTwoQAllLanes"); IMM("i32imm"); IMM("i32imm_hilo16"); From echristo at apple.com Tue Dec 20 18:52:44 2011 From: echristo at apple.com (Eric Christopher) Date: Wed, 21 Dec 2011 00:52:44 -0000 Subject: [llvm-commits] [llvm] r147027 - /llvm/trunk/configure Message-ID: <20111221005244.BFF4A2A6C12C@llvm.org> Author: echristo Date: Tue Dec 20 18:52:44 2011 New Revision: 147027 URL: http://llvm.org/viewvc/llvm-project?rev=147027&view=rev Log: Regenerate. Modified: llvm/trunk/configure Modified: llvm/trunk/configure URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/configure?rev=147027&r1=147026&r2=147027&view=diff ============================================================================== --- llvm/trunk/configure (original) +++ llvm/trunk/configure Tue Dec 20 18:52:44 2011 @@ -1,8 +1,8 @@ #! /bin/sh # Guess values for system-dependent variables and create Makefiles. -# Generated by GNU Autoconf 2.60 for llvm 3.1svn. +# Generated by GNU Autoconf 2.60 for LLVM 3.1svn. # -# Report bugs to . +# Report bugs to . # # Copyright (C) 1992, 1993, 1994, 1995, 1996, 1998, 1999, 2000, 2001, # 2002, 2003, 2004, 2005, 2006 Free Software Foundation, Inc. @@ -559,11 +559,11 @@ SHELL=${CONFIG_SHELL-/bin/sh} # Identity of this package. -PACKAGE_NAME='llvm' -PACKAGE_TARNAME='-llvm-' +PACKAGE_NAME='LLVM' +PACKAGE_TARNAME='llvm' PACKAGE_VERSION='3.1svn' -PACKAGE_STRING='llvm 3.1svn' -PACKAGE_BUGREPORT='llvmbugs at cs.uiuc.edu' +PACKAGE_STRING='LLVM 3.1svn' +PACKAGE_BUGREPORT='http://llvm.org/bugs/' ac_unique_file="lib/VMCore/Module.cpp" # Factoring default headers for most tests. @@ -1317,7 +1317,7 @@ # Omit some internal or obsolete options to make the list less imposing. # This message is too long to be a string in the A/UX 3.1 sh. cat <<_ACEOF -\`configure' configures llvm 3.1svn to adapt to many kinds of systems. +\`configure' configures LLVM 3.1svn to adapt to many kinds of systems. Usage: $0 [OPTION]... [VAR=VALUE]... @@ -1365,7 +1365,7 @@ --infodir=DIR info documentation [DATAROOTDIR/info] --localedir=DIR locale-dependent data [DATAROOTDIR/locale] --mandir=DIR man documentation [DATAROOTDIR/man] - --docdir=DIR documentation root [DATAROOTDIR/doc/-llvm-] + --docdir=DIR documentation root [DATAROOTDIR/doc/llvm] --htmldir=DIR html documentation [DOCDIR] --dvidir=DIR dvi documentation [DOCDIR] --pdfdir=DIR pdf documentation [DOCDIR] @@ -1383,7 +1383,7 @@ if test -n "$ac_init_help"; then case $ac_init_help in - short | recursive ) echo "Configuration of llvm 3.1svn:";; + short | recursive ) echo "Configuration of LLVM 3.1svn:";; esac cat <<\_ACEOF @@ -1418,8 +1418,8 @@ (default is YES) --enable-targets Build specific host targets: all or target1,target2,... Valid targets are: host, x86, - x86_64, sparc, powerpc, arm, mips, spu, xcore, - hexagon, msp430, ptx, cbe, and cpp (default=all) + x86_64, sparc, powerpc, arm, mips, spu, hexagon, + xcore, msp430, ptx, cbe, and cpp (default=all) --enable-cbe-printf-a Enable C Backend output with hex floating point via %a (default is YES) --enable-bindings Build specific language bindings: @@ -1472,7 +1472,7 @@ Use these variables to override the choices made by `configure' or to help it to find libraries and programs with nonstandard names/locations. -Report bugs to . +Report bugs to . _ACEOF ac_status=$? fi @@ -1533,7 +1533,7 @@ test -n "$ac_init_help" && exit $ac_status if $ac_init_version; then cat <<\_ACEOF -llvm configure 3.1svn +LLVM configure 3.1svn generated by GNU Autoconf 2.60 Copyright (C) 1992, 1993, 1994, 1995, 1996, 1998, 1999, 2000, 2001, @@ -1549,7 +1549,7 @@ This file contains any messages produced by compilers while running configure, to aid debugging if configure makes a mistake. -It was created by llvm $as_me 3.1svn, which was +It was created by LLVM $as_me 3.1svn, which was generated by GNU Autoconf 2.60. Invocation command line was $ $0 $@ @@ -8682,9 +8682,9 @@ { echo "$as_me:$LINENO: WARNING: $ac_header: in the future, the compiler will take precedence" >&5 echo "$as_me: WARNING: $ac_header: in the future, the compiler will take precedence" >&2;} ( cat <<\_ASBOX -## ----------------------------------- ## -## Report this to llvmbugs at cs.uiuc.edu ## -## ----------------------------------- ## +## ------------------------------------ ## +## Report this to http://llvm.org/bugs/ ## +## ------------------------------------ ## _ASBOX ) | sed "s/^/$as_me: WARNING: /" >&2 ;; @@ -10495,7 +10495,7 @@ lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2 lt_status=$lt_dlunknown cat > conftest.$ac_ext <&5 echo "$as_me: WARNING: $ac_header: in the future, the compiler will take precedence" >&2;} ( cat <<\_ASBOX -## ----------------------------------- ## -## Report this to llvmbugs at cs.uiuc.edu ## -## ----------------------------------- ## +## ------------------------------------ ## +## Report this to http://llvm.org/bugs/ ## +## ------------------------------------ ## _ASBOX ) | sed "s/^/$as_me: WARNING: /" >&2 ;; @@ -11226,9 +11226,9 @@ { echo "$as_me:$LINENO: WARNING: $ac_header: in the future, the compiler will take precedence" >&5 echo "$as_me: WARNING: $ac_header: in the future, the compiler will take precedence" >&2;} ( cat <<\_ASBOX -## ----------------------------------- ## -## Report this to llvmbugs at cs.uiuc.edu ## -## ----------------------------------- ## +## ------------------------------------ ## +## Report this to http://llvm.org/bugs/ ## +## ------------------------------------ ## _ASBOX ) | sed "s/^/$as_me: WARNING: /" >&2 ;; @@ -11398,9 +11398,9 @@ { echo "$as_me:$LINENO: WARNING: $ac_header: in the future, the compiler will take precedence" >&5 echo "$as_me: WARNING: $ac_header: in the future, the compiler will take precedence" >&2;} ( cat <<\_ASBOX -## ----------------------------------- ## -## Report this to llvmbugs at cs.uiuc.edu ## -## ----------------------------------- ## +## ------------------------------------ ## +## Report this to http://llvm.org/bugs/ ## +## ------------------------------------ ## _ASBOX ) | sed "s/^/$as_me: WARNING: /" >&2 ;; @@ -11568,9 +11568,9 @@ { echo "$as_me:$LINENO: WARNING: $ac_header: in the future, the compiler will take precedence" >&5 echo "$as_me: WARNING: $ac_header: in the future, the compiler will take precedence" >&2;} ( cat <<\_ASBOX -## ----------------------------------- ## -## Report this to llvmbugs at cs.uiuc.edu ## -## ----------------------------------- ## +## ------------------------------------ ## +## Report this to http://llvm.org/bugs/ ## +## ------------------------------------ ## _ASBOX ) | sed "s/^/$as_me: WARNING: /" >&2 ;; @@ -13699,9 +13699,9 @@ { echo "$as_me:$LINENO: WARNING: opagent.h: in the future, the compiler will take precedence" >&5 echo "$as_me: WARNING: opagent.h: in the future, the compiler will take precedence" >&2;} ( cat <<\_ASBOX -## ----------------------------------- ## -## Report this to llvmbugs at cs.uiuc.edu ## -## ----------------------------------- ## +## ------------------------------------ ## +## Report this to http://llvm.org/bugs/ ## +## ------------------------------------ ## _ASBOX ) | sed "s/^/$as_me: WARNING: /" >&2 ;; @@ -14489,9 +14489,9 @@ { echo "$as_me:$LINENO: WARNING: $ac_header: in the future, the compiler will take precedence" >&5 echo "$as_me: WARNING: $ac_header: in the future, the compiler will take precedence" >&2;} ( cat <<\_ASBOX -## ----------------------------------- ## -## Report this to llvmbugs at cs.uiuc.edu ## -## ----------------------------------- ## +## ------------------------------------ ## +## Report this to http://llvm.org/bugs/ ## +## ------------------------------------ ## _ASBOX ) | sed "s/^/$as_me: WARNING: /" >&2 ;; @@ -14663,9 +14663,9 @@ { echo "$as_me:$LINENO: WARNING: $ac_header: in the future, the compiler will take precedence" >&5 echo "$as_me: WARNING: $ac_header: in the future, the compiler will take precedence" >&2;} ( cat <<\_ASBOX -## ----------------------------------- ## -## Report this to llvmbugs at cs.uiuc.edu ## -## ----------------------------------- ## +## ------------------------------------ ## +## Report this to http://llvm.org/bugs/ ## +## ------------------------------------ ## _ASBOX ) | sed "s/^/$as_me: WARNING: /" >&2 ;; @@ -14833,9 +14833,9 @@ { echo "$as_me:$LINENO: WARNING: $ac_header: in the future, the compiler will take precedence" >&5 echo "$as_me: WARNING: $ac_header: in the future, the compiler will take precedence" >&2;} ( cat <<\_ASBOX -## ----------------------------------- ## -## Report this to llvmbugs at cs.uiuc.edu ## -## ----------------------------------- ## +## ------------------------------------ ## +## Report this to http://llvm.org/bugs/ ## +## ------------------------------------ ## _ASBOX ) | sed "s/^/$as_me: WARNING: /" >&2 ;; @@ -15006,9 +15006,9 @@ { echo "$as_me:$LINENO: WARNING: $ac_header: in the future, the compiler will take precedence" >&5 echo "$as_me: WARNING: $ac_header: in the future, the compiler will take precedence" >&2;} ( cat <<\_ASBOX -## ----------------------------------- ## -## Report this to llvmbugs at cs.uiuc.edu ## -## ----------------------------------- ## +## ------------------------------------ ## +## Report this to http://llvm.org/bugs/ ## +## ------------------------------------ ## _ASBOX ) | sed "s/^/$as_me: WARNING: /" >&2 ;; @@ -15178,9 +15178,9 @@ { echo "$as_me:$LINENO: WARNING: $ac_header: in the future, the compiler will take precedence" >&5 echo "$as_me: WARNING: $ac_header: in the future, the compiler will take precedence" >&2;} ( cat <<\_ASBOX -## ----------------------------------- ## -## Report this to llvmbugs at cs.uiuc.edu ## -## ----------------------------------- ## +## ------------------------------------ ## +## Report this to http://llvm.org/bugs/ ## +## ------------------------------------ ## _ASBOX ) | sed "s/^/$as_me: WARNING: /" >&2 ;; @@ -15347,9 +15347,9 @@ { echo "$as_me:$LINENO: WARNING: $ac_header: in the future, the compiler will take precedence" >&5 echo "$as_me: WARNING: $ac_header: in the future, the compiler will take precedence" >&2;} ( cat <<\_ASBOX -## ----------------------------------- ## -## Report this to llvmbugs at cs.uiuc.edu ## -## ----------------------------------- ## +## ------------------------------------ ## +## Report this to http://llvm.org/bugs/ ## +## ------------------------------------ ## _ASBOX ) | sed "s/^/$as_me: WARNING: /" >&2 ;; @@ -15516,9 +15516,9 @@ { echo "$as_me:$LINENO: WARNING: $ac_header: in the future, the compiler will take precedence" >&5 echo "$as_me: WARNING: $ac_header: in the future, the compiler will take precedence" >&2;} ( cat <<\_ASBOX -## ----------------------------------- ## -## Report this to llvmbugs at cs.uiuc.edu ## -## ----------------------------------- ## +## ------------------------------------ ## +## Report this to http://llvm.org/bugs/ ## +## ------------------------------------ ## _ASBOX ) | sed "s/^/$as_me: WARNING: /" >&2 ;; @@ -15686,9 +15686,9 @@ { echo "$as_me:$LINENO: WARNING: $ac_header: in the future, the compiler will take precedence" >&5 echo "$as_me: WARNING: $ac_header: in the future, the compiler will take precedence" >&2;} ( cat <<\_ASBOX -## ----------------------------------- ## -## Report this to llvmbugs at cs.uiuc.edu ## -## ----------------------------------- ## +## ------------------------------------ ## +## Report this to http://llvm.org/bugs/ ## +## ------------------------------------ ## _ASBOX ) | sed "s/^/$as_me: WARNING: /" >&2 ;; @@ -15866,9 +15866,9 @@ { echo "$as_me:$LINENO: WARNING: $ac_header: in the future, the compiler will take precedence" >&5 echo "$as_me: WARNING: $ac_header: in the future, the compiler will take precedence" >&2;} ( cat <<\_ASBOX -## ----------------------------------- ## -## Report this to llvmbugs at cs.uiuc.edu ## -## ----------------------------------- ## +## ------------------------------------ ## +## Report this to http://llvm.org/bugs/ ## +## ------------------------------------ ## _ASBOX ) | sed "s/^/$as_me: WARNING: /" >&2 ;; @@ -16037,9 +16037,9 @@ { echo "$as_me:$LINENO: WARNING: $ac_header: in the future, the compiler will take precedence" >&5 echo "$as_me: WARNING: $ac_header: in the future, the compiler will take precedence" >&2;} ( cat <<\_ASBOX -## ----------------------------------- ## -## Report this to llvmbugs at cs.uiuc.edu ## -## ----------------------------------- ## +## ------------------------------------ ## +## Report this to http://llvm.org/bugs/ ## +## ------------------------------------ ## _ASBOX ) | sed "s/^/$as_me: WARNING: /" >&2 ;; @@ -20078,9 +20078,9 @@ { echo "$as_me:$LINENO: WARNING: $ac_header: in the future, the compiler will take precedence" >&5 echo "$as_me: WARNING: $ac_header: in the future, the compiler will take precedence" >&2;} ( cat <<\_ASBOX -## ----------------------------------- ## -## Report this to llvmbugs at cs.uiuc.edu ## -## ----------------------------------- ## +## ------------------------------------ ## +## Report this to http://llvm.org/bugs/ ## +## ------------------------------------ ## _ASBOX ) | sed "s/^/$as_me: WARNING: /" >&2 ;; @@ -21548,7 +21548,7 @@ # report actual input values of CONFIG_FILES etc. instead of their # values after options handling. ac_log=" -This file was extended by llvm $as_me 3.1svn, which was +This file was extended by LLVM $as_me 3.1svn, which was generated by GNU Autoconf 2.60. Invocation command line was CONFIG_FILES = $CONFIG_FILES @@ -21601,7 +21601,7 @@ _ACEOF cat >>$CONFIG_STATUS <<_ACEOF ac_cs_version="\\ -llvm config.status 3.1svn +LLVM config.status 3.1svn configured by $0, generated by GNU Autoconf 2.60, with options \\"`echo "$ac_configure_args" | sed 's/^ //; s/[\\""\`\$]/\\\\&/g'`\\" From wendling at apple.com Tue Dec 20 19:07:32 2011 From: wendling at apple.com (Bill Wendling) Date: Tue, 20 Dec 2011 17:07:32 -0800 Subject: [llvm-commits] [llvm] r147010 - /llvm/trunk/lib/Linker/LinkModules.cpp In-Reply-To: <20111220231457.AE3482A6C12C@llvm.org> References: <20111220231457.AE3482A6C12C@llvm.org> Message-ID: <111A2708-481E-4117-8FD8-983DA49FCE34@apple.com> Yay! This was also making LTO fail. -bw On Dec 20, 2011, at 3:14 PM, Chris Lattner wrote: > Author: lattner > Date: Tue Dec 20 17:14:57 2011 > New Revision: 147010 > > URL: http://llvm.org/viewvc/llvm-project?rev=147010&view=rev > Log: > Fix a nasty bug in the type remapping stuff that I added that is breaking kc++ on > the build bot in some cases. The basic issue happens when a source module contains > both a "%foo" type and a "%foo.42" type. It will see the later one, check to see if > the destination module contains a "%foo" type, and it will return true... because > both the source and destination modules are in the same LLVMContext. We don't want > to map source types to other source types, so don't do the remapping if the mapped > type came from the source module. > > Unfortunately, I've been unable to reduce a decent testcase for this, kc++ is > pretty great that way. > > Modified: > llvm/trunk/lib/Linker/LinkModules.cpp > > Modified: llvm/trunk/lib/Linker/LinkModules.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Linker/LinkModules.cpp?rev=147010&r1=147009&r2=147010&view=diff > ============================================================================== > --- llvm/trunk/lib/Linker/LinkModules.cpp (original) > +++ llvm/trunk/lib/Linker/LinkModules.cpp Tue Dec 20 17:14:57 2011 > @@ -148,6 +148,7 @@ > if (PointerType *PT = dyn_cast(DstTy)) { > if (PT->getAddressSpace() != cast(SrcTy)->getAddressSpace()) > return false; > + > } else if (FunctionType *FT = dyn_cast(DstTy)) { > if (FT->isVarArg() != cast(SrcTy)->isVarArg()) > return false; > @@ -567,6 +568,9 @@ > std::vector SrcStructTypes; > SrcM->findUsedStructTypes(SrcStructTypes); > > + SmallPtrSet SrcStructTypesSet(SrcStructTypes.begin(), > + SrcStructTypes.end()); > + > for (unsigned i = 0, e = SrcStructTypes.size(); i != e; ++i) { > StructType *ST = SrcStructTypes[i]; > if (!ST->hasName()) continue; > @@ -579,7 +583,10 @@ > > // Check to see if the destination module has a struct with the prefix name. > if (StructType *DST = DstM->getTypeByName(ST->getName().substr(0, DotPos))) > - TypeMap.addTypeMapping(DST, ST); > + // Don't use it if this actually came from the source module. They're in > + // the same LLVMContext after all. > + if (!SrcStructTypesSet.count(DST)) > + TypeMap.addTypeMapping(DST, ST); > } > > > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From grosbach at apple.com Tue Dec 20 19:19:23 2011 From: grosbach at apple.com (Jim Grosbach) Date: Wed, 21 Dec 2011 01:19:23 -0000 Subject: [llvm-commits] [llvm] r147028 - /llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Message-ID: <20111221011923.E2F7C2A6C12C@llvm.org> Author: grosbach Date: Tue Dec 20 19:19:23 2011 New Revision: 147028 URL: http://llvm.org/viewvc/llvm-project?rev=147028&view=rev Log: ARM assembly parsing allows constant expressions for lane indices. Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp?rev=147028&r1=147027&r2=147028&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp (original) +++ llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Tue Dec 20 19:19:23 2011 @@ -2831,21 +2831,32 @@ Parser.Lex(); // Eat the ']'. return MatchOperand_Success; } - if (Parser.getTok().is(AsmToken::Integer)) { - int64_t Val = Parser.getTok().getIntVal(); - // Make this range check context sensitive for .8, .16, .32. - if (Val < 0 && Val > 7) - Error(Parser.getTok().getLoc(), "lane index out of range"); - Index = Val; - LaneKind = IndexedLane; - Parser.Lex(); // Eat the token; - if (Parser.getTok().isNot(AsmToken::RBrac)) - Error(Parser.getTok().getLoc(), "']' expected"); - Parser.Lex(); // Eat the ']'. - return MatchOperand_Success; + const MCExpr *LaneIndex; + SMLoc Loc = Parser.getTok().getLoc(); + if (getParser().ParseExpression(LaneIndex)) { + Error(Loc, "illegal expression"); + return MatchOperand_ParseFail; } - Error(Parser.getTok().getLoc(), "lane index must be empty or an integer"); - return MatchOperand_ParseFail; + const MCConstantExpr *CE = dyn_cast(LaneIndex); + if (!CE) { + Error(Loc, "lane index must be empty or an integer"); + return MatchOperand_ParseFail; + } + if (Parser.getTok().isNot(AsmToken::RBrac)) { + Error(Parser.getTok().getLoc(), "']' expected"); + return MatchOperand_ParseFail; + } + Parser.Lex(); // Eat the ']'. + int64_t Val = CE->getValue(); + + // FIXME: Make this range check context sensitive for .8, .16, .32. + if (Val < 0 || Val > 7) { + Error(Parser.getTok().getLoc(), "lane index out of range"); + return MatchOperand_ParseFail; + } + Index = Val; + LaneKind = IndexedLane; + return MatchOperand_Success; } LaneKind = NoLanes; return MatchOperand_Success; From evan.cheng at apple.com Tue Dec 20 19:38:48 2011 From: evan.cheng at apple.com (Evan Cheng) Date: Tue, 20 Dec 2011 17:38:48 -0800 Subject: [llvm-commits] [llvm] r146801 - in /llvm/trunk: include/llvm/MC/MCStreamer.h lib/CodeGen/AsmPrinter/AsmPrinterDwarf.cpp lib/MC/MCAsmStreamer.cpp lib/MC/MCLoggingStreamer.cpp lib/MC/MCNullStreamer.cpp lib/MC/MCParser/COFFAsmParser.cpp lib/MC/MCStr In-Reply-To: <4EF12111.2000806@gmail.com> References: <4EF12111.2000806@gmail.com> Message-ID: On Dec 20, 2011, at 3:58 PM, Rafael ?vila de Esp?ndola wrote: >> + >> +#include "../Target/X86/MCTargetDesc/X86FixupKinds.h" >> + >> >> >> This is a pretty egregious layering violation. Please fix or revert, >> this causes all kinds of problems with improper dependencies between >> various components. > > This is not making library dependencies any worse: > > grep -r X86FixupKinds.h lib/MC/ > lib/MC/ELFObjectWriter.cpp:#include > "../Target/X86/MCTargetDesc/X86FixupKinds.h" > lib/MC/WinCOFFStreamer.cpp:#include > "../Target/X86/MCTargetDesc/X86FixupKinds.h" > lib/MC/WinCOFFObjectWriter.cpp:#include > "../Target/X86/MCTargetDesc/X86FixupKinds.h" > > I will take a look at this this week, but reverting this will break > codegen of an empty main on windows with -g, so it seems like bit harsh > for what it is. Yuck. You're right. Evan > > Cheers, > Rafael > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From evan.cheng at apple.com Tue Dec 20 21:04:10 2011 From: evan.cheng at apple.com (Evan Cheng) Date: Wed, 21 Dec 2011 03:04:10 -0000 Subject: [llvm-commits] [llvm] r147032 - in /llvm/trunk: lib/Target/ARM/ARMInstrInfo.td test/CodeGen/ARM/atomic-op.ll Message-ID: <20111221030410.E8DBE2A6C12C@llvm.org> Author: evancheng Date: Tue Dec 20 21:04:10 2011 New Revision: 147032 URL: http://llvm.org/viewvc/llvm-project?rev=147032&view=rev Log: Fix a couple of copy-n-paste bugs. Noticed by George Russell. Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td llvm/trunk/test/CodeGen/ARM/atomic-op.ll Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.td?rev=147032&r1=147031&r2=147032&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrInfo.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Tue Dec 20 21:04:10 2011 @@ -4212,10 +4212,10 @@ [(set GPR:$dst, (atomic_load_max_32 GPR:$ptr, GPR:$val))]>; def ATOMIC_LOAD_UMIN_I32 : PseudoInst< (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary, - [(set GPR:$dst, (atomic_load_min_32 GPR:$ptr, GPR:$val))]>; + [(set GPR:$dst, (atomic_load_umin_32 GPR:$ptr, GPR:$val))]>; def ATOMIC_LOAD_UMAX_I32 : PseudoInst< (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary, - [(set GPR:$dst, (atomic_load_max_32 GPR:$ptr, GPR:$val))]>; + [(set GPR:$dst, (atomic_load_umax_32 GPR:$ptr, GPR:$val))]>; def ATOMIC_SWAP_I8 : PseudoInst< (outs GPR:$dst), (ins GPR:$ptr, GPR:$new), NoItinerary, Modified: llvm/trunk/test/CodeGen/ARM/atomic-op.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/atomic-op.ll?rev=147032&r1=147031&r2=147032&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/ARM/atomic-op.ll (original) +++ llvm/trunk/test/CodeGen/ARM/atomic-op.ll Tue Dec 20 21:04:10 2011 @@ -1,5 +1,5 @@ -; RUN: llc < %s -mtriple=armv7-apple-darwin10 -verify-machineinstrs | FileCheck %s -; RUN: llc < %s -mtriple=thumbv7-apple-darwin10 -verify-machineinstrs | FileCheck %s +; RUN: llc < %s -mtriple=armv7-apple-ios -verify-machineinstrs | FileCheck %s +; RUN: llc < %s -mtriple=thumbv7-apple-ios -verify-machineinstrs | FileCheck %s define void @func(i32 %argc, i8** %argv) nounwind { entry: @@ -61,7 +61,7 @@ ; CHECK: strex %7 = atomicrmw min i32* %val2, i32 16 monotonic store i32 %7, i32* %old - %neg = sub i32 0, 1 ; [#uses=1] + %neg = sub i32 0, 1 ; CHECK: ldrex ; CHECK: cmp ; CHECK: strex @@ -77,5 +77,27 @@ ; CHECK: strex %10 = atomicrmw max i32* %val2, i32 0 monotonic store i32 %10, i32* %old - ret void + ; CHECK: ldrex + ; CHECK: cmp + ; CHECK: strex + %11 = atomicrmw umin i32* %val2, i32 16 monotonic + store i32 %11, i32* %old + %uneg = sub i32 0, 1 + ; CHECK: ldrex + ; CHECK: cmp + ; CHECK: strex + %12 = atomicrmw umin i32* %val2, i32 %uneg monotonic + store i32 %12, i32* %old + ; CHECK: ldrex + ; CHECK: cmp + ; CHECK: strex + %13 = atomicrmw umax i32* %val2, i32 1 monotonic + store i32 %13, i32* %old + ; CHECK: ldrex + ; CHECK: cmp + ; CHECK: strex + %14 = atomicrmw umax i32* %val2, i32 0 monotonic + store i32 %14, i32* %old + + ret void } From nicholas at mxc.ca Tue Dec 20 23:52:02 2011 From: nicholas at mxc.ca (Nick Lewycky) Date: Wed, 21 Dec 2011 05:52:02 -0000 Subject: [llvm-commits] [llvm] r147036 - in /llvm/trunk: lib/Analysis/ValueTracking.cpp lib/Transforms/Utils/SimplifyCFG.cpp test/Transforms/SimplifyCFG/SpeculativeExec.ll Message-ID: <20111221055202.885DE2A6C12C@llvm.org> Author: nicholas Date: Tue Dec 20 23:52:02 2011 New Revision: 147036 URL: http://llvm.org/viewvc/llvm-project?rev=147036&view=rev Log: Make some intrinsics safe to speculatively execute. Modified: llvm/trunk/lib/Analysis/ValueTracking.cpp llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp llvm/trunk/test/Transforms/SimplifyCFG/SpeculativeExec.ll Modified: llvm/trunk/lib/Analysis/ValueTracking.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/ValueTracking.cpp?rev=147036&r1=147035&r2=147036&view=diff ============================================================================== --- llvm/trunk/lib/Analysis/ValueTracking.cpp (original) +++ llvm/trunk/lib/Analysis/ValueTracking.cpp Tue Dec 20 23:52:02 2011 @@ -1912,11 +1912,31 @@ return false; return LI->getPointerOperand()->isDereferenceablePointer(); } - case Instruction::Call: + case Instruction::Call: { + if (const IntrinsicInst *II = dyn_cast(Inst)) { + switch (II->getIntrinsicID()) { + case Intrinsic::bswap: + case Intrinsic::ctlz: + case Intrinsic::ctpop: + case Intrinsic::cttz: + case Intrinsic::objectsize: + case Intrinsic::sadd_with_overflow: + case Intrinsic::smul_with_overflow: + case Intrinsic::ssub_with_overflow: + case Intrinsic::uadd_with_overflow: + case Intrinsic::umul_with_overflow: + case Intrinsic::usub_with_overflow: + return true; + // TODO: some fp intrinsics are marked as having the same error handling + // as libm. They're safe to speculate when they won't error. + // TODO: are convert_{from,to}_fp16 safe? + // TODO: can we list target-specific intrinsics here? + default: break; + } + } return false; // The called function could have undefined behavior or - // side-effects. - // FIXME: We should special-case some intrinsics (bswap, - // overflow-checking arithmetic, etc.) + // side-effects, even if marked readnone nounwind. + } case Instruction::VAArg: case Instruction::Alloca: case Instruction::Invoke: Modified: llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp?rev=147036&r1=147035&r2=147036&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp (original) +++ llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp Tue Dec 20 23:52:02 2011 @@ -293,6 +293,7 @@ Cost = 1; break; // These are all cheap and non-trapping instructions. + case Instruction::Call: case Instruction::Select: Cost = 2; break; Modified: llvm/trunk/test/Transforms/SimplifyCFG/SpeculativeExec.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/SimplifyCFG/SpeculativeExec.ll?rev=147036&r1=147035&r2=147036&view=diff ============================================================================== --- llvm/trunk/test/Transforms/SimplifyCFG/SpeculativeExec.ll (original) +++ llvm/trunk/test/Transforms/SimplifyCFG/SpeculativeExec.ll Tue Dec 20 23:52:02 2011 @@ -1,7 +1,10 @@ -; RUN: opt < %s -simplifycfg -S | grep select -; RUN: opt < %s -simplifycfg -S | grep br | count 2 +; RUN: opt < %s -simplifycfg -phi-node-folding-threshold=2 -S | FileCheck %s -define i32 @t2(i32 %a, i32 %b, i32 %c) nounwind { +target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128" +target triple = "x86_64-unknown-linux-gnu" + +define i32 @test1(i32 %a, i32 %b, i32 %c) nounwind { +; CHECK: @test1 entry: %tmp1 = icmp eq i32 %b, 0 br i1 %tmp1, label %bb1, label %bb3 @@ -9,6 +12,11 @@ bb1: ; preds = %entry %tmp2 = icmp sgt i32 %c, 1 br i1 %tmp2, label %bb2, label %bb3 +; CHECK: bb1: +; CHECK-NEXT: add i32 %a, 1 +; CHECK-NEXT: icmp sgt i32 %c, 1 +; CHECK-NEXT: select i1 %tmp2, i32 %tmp3, i32 %a +; CHECK-NEXT: br label %bb3 bb2: ; preds = bb1 %tmp3 = add i32 %a, 1 @@ -19,3 +27,20 @@ %tmp5 = sub i32 %tmp4, 1 ret i32 %tmp5 } + +declare i8 @llvm.cttz.i8(i8, i1) + +define i8 @test2(i8 %a) { +; CHECK: @test2 + br i1 undef, label %bb_true, label %bb_false +bb_true: + %b = tail call i8 @llvm.cttz.i8(i8 %a, i1 false) + br label %join +bb_false: + br label %join +join: + %c = phi i8 [%b, %bb_true], [%a, %bb_false] +; CHECK: select + ret i8 %c +} + From nicholas at mxc.ca Wed Dec 21 00:06:30 2011 From: nicholas at mxc.ca (Nick Lewycky) Date: Wed, 21 Dec 2011 06:06:30 -0000 Subject: [llvm-commits] [llvm] r147037 - /llvm/trunk/lib/Analysis/InlineCost.cpp Message-ID: <20111221060630.8F5FD2A6C12C@llvm.org> Author: nicholas Date: Wed Dec 21 00:06:30 2011 New Revision: 147037 URL: http://llvm.org/viewvc/llvm-project?rev=147037&view=rev Log: A call to a function marked 'noinline' is not an inline candidate. The sole call site of an intrinsic is also not an inline candidate. While here, make it more obvious that this code ignores all intrinsics. Noticed by inspection! Modified: llvm/trunk/lib/Analysis/InlineCost.cpp Modified: llvm/trunk/lib/Analysis/InlineCost.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/InlineCost.cpp?rev=147037&r1=147036&r2=147037&view=diff ============================================================================== --- llvm/trunk/lib/Analysis/InlineCost.cpp (original) +++ llvm/trunk/lib/Analysis/InlineCost.cpp Wed Dec 21 00:06:30 2011 @@ -63,8 +63,8 @@ // Special handling for calls. if (isa(II) || isa(II)) { - if (isa(II)) - continue; // Debug intrinsics don't count as size. + if (isa(II)) + continue; // Intrinsics have no argument setup and can't be inlined. ImmutableCallSite CS(cast(II)); @@ -72,7 +72,7 @@ // If a function is both internal and has a single use, then it is // extremely likely to get inlined in the future (it was probably // exposed by an interleaved devirtualization pass). - if (F->hasInternalLinkage() && F->hasOneUse()) + if (!CS.isNoInline() && F->hasInternalLinkage() && F->hasOneUse()) ++NumInlineCandidates; // If this call is to function itself, then the function is recursive. @@ -83,7 +83,7 @@ isRecursive = true; } - if (!isa(II) && !callIsSmall(CS.getCalledFunction())) { + if (!callIsSmall(CS.getCalledFunction())) { // Each argument to a call takes on average one instruction to set up. NumInsts += CS.arg_size(); From daniel at zuster.org Wed Dec 21 00:21:56 2011 From: daniel at zuster.org (Daniel Dunbar) Date: Wed, 21 Dec 2011 06:21:56 -0000 Subject: [llvm-commits] [zorg] r147038 - /zorg/trunk/lnt/lnt/lnttool/create.py Message-ID: <20111221062156.4BBF52A6C12C@llvm.org> Author: ddunbar Date: Wed Dec 21 00:21:56 2011 New Revision: 147038 URL: http://llvm.org/viewvc/llvm-project?rev=147038&view=rev Log: [lnt/v0.4] lnt create: Fix up some errors in the default NT test suite definition. Modified: zorg/trunk/lnt/lnt/lnttool/create.py Modified: zorg/trunk/lnt/lnt/lnttool/create.py URL: http://llvm.org/viewvc/llvm-project/zorg/trunk/lnt/lnt/lnttool/create.py?rev=147038&r1=147037&r2=147038&view=diff ============================================================================== --- zorg/trunk/lnt/lnt/lnttool/create.py (original) +++ zorg/trunk/lnt/lnt/lnttool/create.py Wed Dec 21 00:21:56 2011 @@ -107,11 +107,11 @@ # We are only interested in simple runs, so we expect exactly four fields # per test. ts.sample_fields.append(testsuite.SampleField( - "compile_time", real_sample_type, ".compile.time")) + "compile_time", real_sample_type, ".compile")) ts.sample_fields.append(testsuite.SampleField( "compile_status", status_sample_type, ".compile.status")) ts.sample_fields.append(testsuite.SampleField( - "execution_time", real_sample_type, ".exec.time")) + "execution_time", real_sample_type, ".exec")) ts.sample_fields.append(testsuite.SampleField( "execution_status", status_sample_type, ".exec.status")) From daniel at zuster.org Wed Dec 21 00:21:59 2011 From: daniel at zuster.org (Daniel Dunbar) Date: Wed, 21 Dec 2011 06:21:59 -0000 Subject: [llvm-commits] [zorg] r147039 - /zorg/trunk/lnt/lnt/server/db/testsuitedb.py Message-ID: <20111221062159.714B12A6C12C@llvm.org> Author: ddunbar Date: Wed Dec 21 00:21:59 2011 New Revision: 147039 URL: http://llvm.org/viewvc/llvm-project?rev=147039&view=rev Log: [lnt/v0.4] lnt.server.db.testsuitedb: Finish first draft of import implementation. - Probably not very fast, but I believe it is functionally complete. Modified: zorg/trunk/lnt/lnt/server/db/testsuitedb.py Modified: zorg/trunk/lnt/lnt/server/db/testsuitedb.py URL: http://llvm.org/viewvc/llvm-project/zorg/trunk/lnt/lnt/server/db/testsuitedb.py?rev=147039&r1=147038&r2=147039&view=diff ============================================================================== --- zorg/trunk/lnt/lnt/server/db/testsuitedb.py (original) +++ zorg/trunk/lnt/lnt/server/db/testsuitedb.py Wed Dec 21 00:21:59 2011 @@ -60,7 +60,7 @@ def __repr__(self): return '%s_%s%r' % (db_key_name, self.__class__.__name__, (self.name,)) - + class Order(self.base): __tablename__ = db_key_name + '_Order' @@ -144,7 +144,7 @@ def __repr__(self): return '%s_%s%r' % (db_key_name, self.__class__.__name__, - (self.name)) + (self.name,)) class Sample(self.base): __tablename__ = db_key_name + '_Sample' @@ -183,13 +183,21 @@ class_dict[item.name] = item.column - def __init__(self, run, test): + def __init__(self, run, test, **kwargs): self.run = run self.test = test + # Initialize sample fields (defaulting to 0, for now). + for item in test_suite.sample_fields: + setattr(self, item.name, kwargs.get(item.name, 0)) + def __repr__(self): - return '%s_%s%r' % (db_key_name, self.__class__.__name__, - (self.run, self.test, self.value)) + fields = dict((item.name, getattr(self, item.name)) + for item in test_suite.sample_fields) + + return '%s_%s(%r, %r, **%r)' % ( + db_key_name, self.__class__.__name__, + self.run, self.test, fields) self.Machine = Machine self.Run = Run @@ -370,6 +378,62 @@ return run,True + def _importSampleValues(self, tests_data, run): + # We now need to transform the old schema data (composite samples split + # into multiple tests) into the V4DB format where each sample is a + # complete record. + + # Load a map of all the tests, which we will extend when we find tests + # that need to be added. + test_cache = dict((test.name, test) + for test in self.query(self.Test)) + + # We build a map of test name to sample values, by scanning all the + # tests. This is complicated by the interchange's support of multiple + # values, which we cannot properly aggregate. We handle this by keying + # off of the test name and the sample index. + # + # Note that the above strategy only works if reports don't report the + # same test name multiple times. That was possible in the schema, but I + # believe never used. + sample_records = {} + for test_data in tests_data: + if test_data['Info']: + raise ValueError,"""\ +test parameter sets are not supported by V4DB databases""" + + name = test_data['Name'] + + # Map this reported test name into a test name and a sample field. + # + # FIXME: This is really slow. + for item in self.test_suite.sample_fields: + if name.endswith(item.info_key): + test_name = name[:-len(item.info_key)] + sample_field = item + break + else: + # Disallow tests which do not map to a sample field. + raise ValueError,"""\ +test %r does not map to a sample field in the reported suite""" % ( + name) + + # Get or create the test. + test = test_cache.get(test_name) + if test is None: + test_cache[test_name] = test = self.Test(test_name) + self.add(test) + + for i,value in enumerate(test_data['Data']): + record_key = (test_name, i) + record = sample_records.get(record_key) + if record is None: + sample_records[record_key] = sample = self.Sample(run, test) + self.add(sample) + + # FIXME: Avoid setattr. + setattr(sample, sample_field.name, value) + def importDataFromDict(self, data): """ importDataFromDict(data) -> Run, bool @@ -392,7 +456,6 @@ if not inserted: return False, run - # FIXME: Insert tests and samples. - raise NotImplementedError + self._importSampleValues(data['Tests'], run) return True, run From daniel at zuster.org Wed Dec 21 00:22:04 2011 From: daniel at zuster.org (Daniel Dunbar) Date: Wed, 21 Dec 2011 06:22:04 -0000 Subject: [llvm-commits] [zorg] r147040 - in /zorg/trunk/lnt/lnt: db/perfdb.py server/db/v4db.py server/ui/app.py server/ui/templates/index.html server/ui/views.py Message-ID: <20111221062204.535BF2A6C12C@llvm.org> Author: ddunbar Date: Wed Dec 21 00:22:04 2011 New Revision: 147040 URL: http://llvm.org/viewvc/llvm-project?rev=147040&view=rev Log: [lnt/v0.4] lnt.server.ui/index: Start work on UI for V4 databases. Modified: zorg/trunk/lnt/lnt/db/perfdb.py zorg/trunk/lnt/lnt/server/db/v4db.py zorg/trunk/lnt/lnt/server/ui/app.py zorg/trunk/lnt/lnt/server/ui/templates/index.html zorg/trunk/lnt/lnt/server/ui/views.py Modified: zorg/trunk/lnt/lnt/db/perfdb.py URL: http://llvm.org/viewvc/llvm-project/zorg/trunk/lnt/lnt/db/perfdb.py?rev=147040&r1=147039&r2=147040&view=diff ============================================================================== --- zorg/trunk/lnt/lnt/db/perfdb.py (original) +++ zorg/trunk/lnt/lnt/db/perfdb.py Wed Dec 21 00:22:04 2011 @@ -344,6 +344,10 @@ def importDataFromDict(self, data): return importDataFromDict(self, data) + def get_db_summary(self): + import perfdbsummary + return perfdbsummary.PerfDBSummary.fromdb(self) + def importDataFromDict(db, data): # FIXME: Validate data machineData = data['Machine'] Modified: zorg/trunk/lnt/lnt/server/db/v4db.py URL: http://llvm.org/viewvc/llvm-project/zorg/trunk/lnt/lnt/server/db/v4db.py?rev=147040&r1=147039&r2=147040&view=diff ============================================================================== --- zorg/trunk/lnt/lnt/server/db/v4db.py (original) +++ zorg/trunk/lnt/lnt/server/db/v4db.py Wed Dec 21 00:22:04 2011 @@ -113,3 +113,23 @@ db = self.testsuite.get(db_name) return db.importDataFromDict(data) + + def get_db_summary(self): + return V4DBSummary(self) + +class V4DBSummary(object): + class SuiteSummary(object): + def __init__(self, name, path): + self.name = name + self.path = path + + def __init__(self, db): + self.db = db + + @property + def suites(self): + for name in self.db.testsuite: + yield V4DBSummary.SuiteSummary(name, ("v4", name)) + + def is_up_to_date(self, db): + return True Modified: zorg/trunk/lnt/lnt/server/ui/app.py URL: http://llvm.org/viewvc/llvm-project/zorg/trunk/lnt/lnt/server/ui/app.py?rev=147040&r1=147039&r2=147040&view=diff ============================================================================== --- zorg/trunk/lnt/lnt/server/ui/app.py (original) +++ zorg/trunk/lnt/lnt/server/ui/app.py Wed Dec 21 00:22:04 2011 @@ -12,6 +12,7 @@ import lnt.server.config import lnt.server.ui.filters import lnt.server.ui.views +import lnt.server.db.v4db from lnt.db import perfdbsummary from lnt.db import perfdb @@ -41,7 +42,10 @@ def get_db(self): if self.db is None: - self.db = perfdb.PerfDB(g.db_info.path) + if g.db_info.db_version == '0.3': + self.db = perfdb.PerfDB(g.db_info.path) + else: + self.db = lnt.server.db.v4db.V4DB(g.db_info.path) # Enable SQL logging with db_log. # @@ -110,9 +114,10 @@ old_config=self.old_config) def get_db_summary(self, db_name, db): + # FIXME/v3removal: Eliminate this, V4DB style has no need for summary + # abstraction. db_summary = self.db_summaries.get(db_name) if db_summary is None or not db_summary.is_up_to_date(db): - self.db_summaries[db_name] = db_summary = \ - perfdbsummary.PerfDBSummary.fromdb(db) + self.db_summaries[db_name] = db_summary = db.get_db_summary() return db_summary Modified: zorg/trunk/lnt/lnt/server/ui/templates/index.html URL: http://llvm.org/viewvc/llvm-project/zorg/trunk/lnt/lnt/server/ui/templates/index.html?rev=147040&r1=147039&r2=147040&view=diff ============================================================================== --- zorg/trunk/lnt/lnt/server/ui/templates/index.html (original) +++ zorg/trunk/lnt/lnt/server/ui/templates/index.html Wed Dec 21 00:22:04 2011 @@ -5,12 +5,12 @@ {# Display available test result suites. #} {% set summary = request.get_db_summary() %} -

Test Results

Test Suites

{% for suite in summary.suites %} {{suite.name}}
{% endfor %} -{% if g.db_info.showGeneral %} +{% if g.db_info.db_version == '0.3' and g.db_info.showGeneral %}

General Database Access

Modified: zorg/trunk/lnt/lnt/server/ui/views.py URL: http://llvm.org/viewvc/llvm-project/zorg/trunk/lnt/lnt/server/ui/views.py?rev=147040&r1=147039&r2=147040&view=diff ============================================================================== --- zorg/trunk/lnt/lnt/server/ui/views.py (original) +++ zorg/trunk/lnt/lnt/server/ui/views.py Wed Dec 21 00:22:04 2011 @@ -46,7 +46,7 @@ # Per-Database Routes # Decorator for implementing per-database routes. -def db_route(rule, **options): +def db_route(rule, only_v3 = True, **options): """ LNT specific route for endpoints which always refer to some database object. @@ -62,12 +62,13 @@ if g.db_info is None: abort(404) - # Currently the UI has absolutely no support for non-v0.3 databases. - if g.db_info.db_version != '0.3': + # Disable non-v0.3 database support, if requested. + if only_v3 and g.db_info.db_version != '0.3': return render_template("error.html", message="""\ UI support for database with version %r is not yet implemented.""" % ( g.db_info.db_version)) + return f(**args) frontend.add_url_rule(rule, f.__name__, wrap, **options) @@ -77,7 +78,7 @@ return wrap return decorator - at db_route('/') + at db_route('/', only_v3 = False) def index(): return render_template("index.html") From daniel at zuster.org Wed Dec 21 00:22:14 2011 From: daniel at zuster.org (Daniel Dunbar) Date: Wed, 21 Dec 2011 06:22:14 -0000 Subject: [llvm-commits] [zorg] r147043 - /zorg/trunk/lnt/lnt/server/db/testsuitedb.py Message-ID: <20111221062214.345782A6C12E@llvm.org> Author: ddunbar Date: Wed Dec 21 00:22:13 2011 New Revision: 147043 URL: http://llvm.org/viewvc/llvm-project?rev=147043&view=rev Log: [lnt/v0.4] lnt.server.db.testsuitedb: Add helper methods for TestSuiteDB model classes to support easier access to parameterized fields. Modified: zorg/trunk/lnt/lnt/server/db/testsuitedb.py Modified: zorg/trunk/lnt/lnt/server/db/testsuitedb.py URL: http://llvm.org/viewvc/llvm-project/zorg/trunk/lnt/lnt/server/db/testsuitedb.py?rev=147043&r1=147042&r2=147043&view=diff ============================================================================== --- zorg/trunk/lnt/lnt/server/db/testsuitedb.py (original) +++ zorg/trunk/lnt/lnt/server/db/testsuitedb.py Wed Dec 21 00:22:13 2011 @@ -42,6 +42,7 @@ class Machine(self.base): __tablename__ = db_key_name + '_Machine' + fields = self.machine_fields id = Column("ID", Integer, primary_key=True) name = Column("Name", String(256), index=True) @@ -53,7 +54,7 @@ # Dynamically create fields for all of the test suite defined # machine fields. class_dict = locals() - for item in self.machine_fields: + for item in fields: if item.name in class_dict: raise ValueError,"test suite defines reserved key %r" % ( name,) @@ -68,9 +69,19 @@ return '%s_%s%r' % (db_key_name, self.__class__.__name__, (self.name,)) + def get_field(self, field): + return getattr(self, field.name) + + def set_field(self, field, value): + return setattr(self, field.name, value) + + def get_parameters(self): + return json.loads(self.parameters) + class Order(self.base): __tablename__ = db_key_name + '_Order' + fields = self.order_fields id = Column("ID", Integer, primary_key=True) # Dynamically create fields for all of the test suite defined order @@ -87,16 +98,31 @@ class_dict[item.name] = item.column = Column( item.name, String(256)) - def __init__(self): - pass + def __init__(self, **kwargs): + for item in self.fields: + self.set_field(item, kwargs[item.name]) def __repr__(self): return '%s_%s%r' % (db_key_name, self.__class__.__name__, ()) + def __repr__(self): + fields = dict((item.name, self.get_field(item)) + for item in self.fields) + + return '%s_%s(**%r)' % ( + db_key_name, self.__class__.__name__, fields) + + def get_field(self, field): + return getattr(self, field.name) + + def set_field(self, field, value): + return setattr(self, field.name, value) + class Run(self.base): __tablename__ = db_key_name + '_Run' + fields = self.run_fields id = Column("ID", Integer, primary_key=True) machine_id = Column("MachineID", Integer, ForeignKey(Machine.id), index=True) @@ -120,7 +146,7 @@ # FIXME: We are probably going to want to index on some of these, # but need a bit for that in the test suite definition. class_dict = locals() - for item in self.run_fields: + for item in fields: if item.name in class_dict: raise ValueError,"test suite defines reserved key %r" % ( name,) @@ -140,6 +166,15 @@ (self.machine, self.order, self.start_time, self.end_time)) + def get_field(self, field): + return getattr(self, field.name) + + def set_field(self, field, value): + return setattr(self, field.name, value) + + def get_parameters(self): + return json.loads(self.parameters) + class Test(self.base): __tablename__ = db_key_name + '_Test' @@ -153,9 +188,16 @@ return '%s_%s%r' % (db_key_name, self.__class__.__name__, (self.name,)) + def get_field(self, field): + return getattr(self, field.name) + + def set_field(self, field, value): + return setattr(self, field.name, value) + class Sample(self.base): __tablename__ = db_key_name + '_Sample' + fields = self.sample_fields id = Column("ID", Integer, primary_key=True) # We do not need an index on run_id, this is covered by the compound # (Run(ID),Test(ID)) index we create below. @@ -195,17 +237,23 @@ self.test = test # Initialize sample fields (defaulting to 0, for now). - for item in testsuitedb.sample_fields: - setattr(self, item.name, kwargs.get(item.name, 0)) + for item in self.fields: + self.set_field(item, kwargs.get(item.name, 0)) def __repr__(self): - fields = dict((item.name, getattr(self, item.name)) - for item in self.sample_fields) + fields = dict((item.name, self.get_field(item)) + for item in self.fields) return '%s_%s(%r, %r, **%r)' % ( db_key_name, self.__class__.__name__, self.run, self.test, fields) + def get_field(self, field): + return getattr(self, field.name) + + def set_field(self, field, value): + return setattr(self, field.name, value) + self.Machine = Machine self.Run = Run self.Test = Test @@ -263,9 +311,8 @@ # suite to define defaults. value = '' - # FIXME: Avoid setattr. query = query.filter(item.column == value) - setattr(machine, item.name, value) + machine.set_field(item.name, value) # Convert any remaining machine_parameters into a JSON encoded blob. We # encode this as an array to avoid a potential ambiguity on the key @@ -309,9 +356,8 @@ supplied run is missing required run parameter: %r""" % ( item.info_key) - # FIXME: Avoid setattr. query = query.filter(item.column == value) - setattr(order, item.name, value) + order.set_field(item, value) # Execute the query to see if we already have this order. try: @@ -368,9 +414,8 @@ # suite to define defaults. value = '' - # FIXME: Avoid setattr. query = query.filter(item.column == value) - setattr(run, item.name, value) + run.set_field(item, value) # Any remaining parameters are saved as a JSON encoded array. run.parameters = json.dumps(sorted(run_parameters.items())) @@ -438,8 +483,7 @@ sample_records[record_key] = sample = self.Sample(run, test) self.add(sample) - # FIXME: Avoid setattr. - setattr(sample, sample_field.name, value) + sample.set_field(sample_field, value) def importDataFromDict(self, data): """ @@ -466,3 +510,14 @@ self._importSampleValues(data['Tests'], run) return True, run + + # Simple query support (mostly used by templates) + + def machines(self, name=None): + q = self.query(self.Machine) + if name: + q = q.filter_by(name=name) + return q + + def getMachine(self, id): + return self.query(self.Machine).filter_by(id=id).one() From daniel at zuster.org Wed Dec 21 00:22:07 2011 From: daniel at zuster.org (Daniel Dunbar) Date: Wed, 21 Dec 2011 06:22:07 -0000 Subject: [llvm-commits] [zorg] r147041 - /zorg/trunk/lnt/lnt/server/db/testsuitedb.py Message-ID: <20111221062207.7781A2A6C12C@llvm.org> Author: ddunbar Date: Wed Dec 21 00:22:07 2011 New Revision: 147041 URL: http://llvm.org/viewvc/llvm-project?rev=147041&view=rev Log: [lnt/v0.4] lnt.server.db.testsuitedb: Cache the assorted fields lists, important particularly because we save the column in the particular model instance during initialization. Modified: zorg/trunk/lnt/lnt/server/db/testsuitedb.py Modified: zorg/trunk/lnt/lnt/server/db/testsuitedb.py URL: http://llvm.org/viewvc/llvm-project/zorg/trunk/lnt/lnt/server/db/testsuitedb.py?rev=147041&r1=147040&r2=147041&view=diff ============================================================================== --- zorg/trunk/lnt/lnt/server/db/testsuitedb.py (original) +++ zorg/trunk/lnt/lnt/server/db/testsuitedb.py Wed Dec 21 00:22:07 2011 @@ -25,9 +25,16 @@ """ def __init__(self, v4db, test_suite): + testsuitedb = self self.v4db = v4db self.test_suite = test_suite + # Save caches of the various fields. + self.machine_fields = list(self.test_suite.machine_fields) + self.order_fields = list(self.test_suite.order_fields) + self.run_fields = list(self.test_suite.run_fields) + self.sample_fields = list(self.test_suite.sample_fields) + self.base = sqlalchemy.ext.declarative.declarative_base() # Create parameterized model classes for this test suite. @@ -46,7 +53,7 @@ # Dynamically create fields for all of the test suite defined # machine fields. class_dict = locals() - for item in test_suite.machine_fields: + for item in self.machine_fields: if item.name in class_dict: raise ValueError,"test suite defines reserved key %r" % ( name,) @@ -72,7 +79,7 @@ # FIXME: We are probably going to want to index on some of these, # but need a bit for that in the test suite definition. class_dict = locals() - for item in test_suite.order_fields: + for item in self.order_fields: if item.name in class_dict: raise ValueError,"test suite defines reserved key %r" % ( name,) @@ -113,7 +120,7 @@ # FIXME: We are probably going to want to index on some of these, # but need a bit for that in the test suite definition. class_dict = locals() - for item in test_suite.run_fields: + for item in self.run_fields: if item.name in class_dict: raise ValueError,"test suite defines reserved key %r" % ( name,) @@ -166,7 +173,7 @@ # index below into a covering index. We should evaluate this once # the new UI is up. class_dict = locals() - for item in test_suite.sample_fields: + for item in self.sample_fields: if item.name in class_dict: raise ValueError,"test suite defines reserved key %r" % ( name,) @@ -188,12 +195,12 @@ self.test = test # Initialize sample fields (defaulting to 0, for now). - for item in test_suite.sample_fields: + for item in testsuitedb.sample_fields: setattr(self, item.name, kwargs.get(item.name, 0)) def __repr__(self): fields = dict((item.name, getattr(self, item.name)) - for item in test_suite.sample_fields) + for item in self.sample_fields) return '%s_%s(%r, %r, **%r)' % ( db_key_name, self.__class__.__name__, @@ -211,7 +218,7 @@ # Create the index we use to ensure machine uniqueness. args = [Machine.name, Machine.parameters] - for item in self.test_suite.machine_fields: + for item in self.machine_fields: args.append(item.column) sqlalchemy.schema.Index("ix_%s_Machine_Unique" % db_key_name, *args, unique = True) @@ -247,7 +254,7 @@ machine_parameters = machine_data['Info'].copy() # First, extract all of the specified machine fields. - for item in self.test_suite.machine_fields: + for item in self.machine_fields: if item.info_key in machine_parameters: value = machine_parameters.pop(item.info_key) else: @@ -293,7 +300,7 @@ order = self.Order() # First, extract all of the specified order fields. - for item in self.test_suite.order_fields: + for item in self.order_fields: if item.info_key in run_parameters: value = run_parameters.pop(item.info_key) else: @@ -352,7 +359,7 @@ run = self.Run(machine, order, start_time, end_time) # First, extract all of the specified run fields. - for item in self.test_suite.run_fields: + for item in self.run_fields: if item.info_key in run_parameters: value = run_parameters.pop(item.info_key) else: @@ -407,7 +414,7 @@ # Map this reported test name into a test name and a sample field. # # FIXME: This is really slow. - for item in self.test_suite.sample_fields: + for item in self.sample_fields: if name.endswith(item.info_key): test_name = name[:-len(item.info_key)] sample_field = item From daniel at zuster.org Wed Dec 21 00:22:11 2011 From: daniel at zuster.org (Daniel Dunbar) Date: Wed, 21 Dec 2011 06:22:11 -0000 Subject: [llvm-commits] [zorg] r147042 - in /zorg/trunk/lnt/lnt/server/ui: app.py templates/v4_overview.html views.py Message-ID: <20111221062211.351772A6C12D@llvm.org> Author: ddunbar Date: Wed Dec 21 00:22:10 2011 New Revision: 147042 URL: http://llvm.org/viewvc/llvm-project?rev=147042&view=rev Log: [lnt/v0.4] lnt.server.ui/v4/: Implement V4 overview page. Added: zorg/trunk/lnt/lnt/server/ui/templates/v4_overview.html Modified: zorg/trunk/lnt/lnt/server/ui/app.py zorg/trunk/lnt/lnt/server/ui/views.py Modified: zorg/trunk/lnt/lnt/server/ui/app.py URL: http://llvm.org/viewvc/llvm-project/zorg/trunk/lnt/lnt/server/ui/app.py?rev=147042&r1=147041&r2=147042&view=diff ============================================================================== --- zorg/trunk/lnt/lnt/server/ui/app.py (original) +++ zorg/trunk/lnt/lnt/server/ui/app.py Wed Dec 21 00:22:10 2011 @@ -34,6 +34,7 @@ self.request_time = time.time() self.db = None self.db_summary = None + self.testsuite = None def elapsed_time(self): return time.time() - self.request_time @@ -59,6 +60,12 @@ return self.db + def get_testsuite(self): + if self.testsuite is None: + self.testsuite = self.get_db().testsuite[g.testsuite_name] + + return self.testsuite + def get_db_summary(self): return current_app.get_db_summary(g.db_name, self.get_db()) @@ -68,6 +75,14 @@ """ return url_