We have changed the way that the Type Legalizer legalizes vectors. + The type legalizer now attempts to promote integer elements. + This enabled the implementation of vector-select. + Additionally, we see a performance boost on workloads which use vectors of chars and shorts, since they are now promoted + to 32-bit types, which are better supported by the SIMD instruction set. + Floating point types are still widened as before.

+ +

We have put a significant amount of work into the code generator infrastructure, which allows us to implement more aggressive algorithms and make it run faster:

@@ -355,6 +364,8 @@

New features and major changes in the X86 target include:

Bug fixes and improved support for AVX1
Support for AVX2 (still incomplete at this point)
....

From dblaikie at gmail.com Tue Dec 20 02:22:50 2011 From: dblaikie at gmail.com (David Blaikie) Date: Tue, 20 Dec 2011 08:22:50 -0000 Subject: [llvm-commits] [llvm] r146965 - /llvm/trunk/utils/TableGen/TGValueTypes.cpp Message-ID: <20111220082250.34EA21BE003@llvm.org> Author: dblaikie Date: Tue Dec 20 02:22:49 2011 New Revision: 146965 URL: http://llvm.org/viewvc/llvm-project?rev=146965&view=rev Log: Revert pragma clang suppressions that confuse GCC. (I'll worry about how to suppress/fix these problems properly when we figure out how to keep LLVM -Wweak-vtables clean) Modified: llvm/trunk/utils/TableGen/TGValueTypes.cpp Modified: llvm/trunk/utils/TableGen/TGValueTypes.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/TGValueTypes.cpp?rev=146965&r1=146964&r2=146965&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/TGValueTypes.cpp (original) +++ llvm/trunk/utils/TableGen/TGValueTypes.cpp Tue Dec 20 02:22:49 2011 @@ -18,9 +18,6 @@ #include using namespace llvm; -#pragma clang diagnostic push -#pragma clang diagnostic ignored "-Wweak-vtables" - namespace llvm { class Type { @@ -61,8 +58,6 @@ } }; -#pragma clang diagnostic pop - static std::map ExtendedIntegerTypeMap; static std::map, const Type *> From chandlerc at gmail.com Tue Dec 20 02:42:12 2011 From: chandlerc at gmail.com (Chandler Carruth) Date: Tue, 20 Dec 2011 08:42:12 -0000 Subject: [llvm-commits] [llvm] r146966 - in /llvm/trunk: lib/CodeGen/ lib/ExecutionEngine/MCJIT/ lib/Support/ lib/TableGen/ lib/Target/ lib/Target/ARM/ lib/Target/CellSPU/ lib/Target/MBlaze/ lib/Target/MSP430/ lib/Target/Mips/ lib/Target/PTX/ lib/Target/PowerPC/ lib/Target/Sparc/ lib/Target/X86/ lib/Target/XCore/ utils/TableGen/ Message-ID: <20111220084214.7E3AA1BE003@llvm.org> Author: chandlerc Date: Tue Dec 20 02:42:11 2011 New Revision: 146966 URL: http://llvm.org/viewvc/llvm-project?rev=146966&view=rev Log: Fix up the CMake build for the new files added in r146960, they're likely to stay either way that discussion ends up resolving itself. Modified: llvm/trunk/lib/CodeGen/CMakeLists.txt llvm/trunk/lib/ExecutionEngine/MCJIT/CMakeLists.txt llvm/trunk/lib/Support/CMakeLists.txt llvm/trunk/lib/TableGen/CMakeLists.txt llvm/trunk/lib/Target/ARM/CMakeLists.txt llvm/trunk/lib/Target/CMakeLists.txt llvm/trunk/lib/Target/CellSPU/CMakeLists.txt llvm/trunk/lib/Target/MBlaze/CMakeLists.txt llvm/trunk/lib/Target/MSP430/CMakeLists.txt llvm/trunk/lib/Target/Mips/CMakeLists.txt llvm/trunk/lib/Target/PTX/CMakeLists.txt llvm/trunk/lib/Target/PowerPC/CMakeLists.txt llvm/trunk/lib/Target/Sparc/CMakeLists.txt llvm/trunk/lib/Target/X86/CMakeLists.txt llvm/trunk/lib/Target/XCore/CMakeLists.txt llvm/trunk/utils/TableGen/CMakeLists.txt Modified: llvm/trunk/lib/CodeGen/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/CMakeLists.txt?rev=146966&r1=146965&r2=146966&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/CMakeLists.txt (original) +++ llvm/trunk/lib/CodeGen/CMakeLists.txt Tue Dec 20 02:42:11 2011 @@ -24,6 +24,7 @@ InlineSpiller.cpp InterferenceCache.cpp IntrinsicLowering.cpp + JITCodeEmitter.cpp LLVMTargetMachine.cpp LatencyPriorityQueue.cpp LexicalScopes.cpp @@ -40,6 +41,7 @@ MachineBlockFrequencyInfo.cpp MachineBlockPlacement.cpp MachineBranchProbabilityInfo.cpp + MachineCodeEmitter.cpp MachineCSE.cpp MachineDominators.cpp MachineFunction.cpp Modified: llvm/trunk/lib/ExecutionEngine/MCJIT/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/ExecutionEngine/MCJIT/CMakeLists.txt?rev=146966&r1=146965&r2=146966&view=diff ============================================================================== --- llvm/trunk/lib/ExecutionEngine/MCJIT/CMakeLists.txt (original) +++ llvm/trunk/lib/ExecutionEngine/MCJIT/CMakeLists.txt Tue Dec 20 02:42:11 2011 @@ -1,4 +1,5 @@ add_llvm_library(LLVMMCJIT MCJIT.cpp + MCJITMemoryManager.cpp Intercept.cpp ) Modified: llvm/trunk/lib/Support/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Support/CMakeLists.txt?rev=146966&r1=146965&r2=146966&view=diff ============================================================================== --- llvm/trunk/lib/Support/CMakeLists.txt (original) +++ llvm/trunk/lib/Support/CMakeLists.txt Tue Dec 20 02:42:11 2011 @@ -27,6 +27,7 @@ GraphWriter.cpp IntEqClasses.cpp IntervalMap.cpp + IntrusiveRefCntPtr.cpp IsInf.cpp IsNAN.cpp JSONParser.cpp Modified: llvm/trunk/lib/TableGen/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/TableGen/CMakeLists.txt?rev=146966&r1=146965&r2=146966&view=diff ============================================================================== --- llvm/trunk/lib/TableGen/CMakeLists.txt (original) +++ llvm/trunk/lib/TableGen/CMakeLists.txt Tue Dec 20 02:42:11 2011 @@ -6,6 +6,7 @@ Error.cpp Main.cpp Record.cpp + TableGenAction.cpp TableGenBackend.cpp TGLexer.cpp TGParser.cpp Modified: llvm/trunk/lib/Target/ARM/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/CMakeLists.txt?rev=146966&r1=146965&r2=146966&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/CMakeLists.txt (original) +++ llvm/trunk/lib/Target/ARM/CMakeLists.txt Tue Dec 20 02:42:11 2011 @@ -33,6 +33,7 @@ ARMJITInfo.cpp ARMLoadStoreOptimizer.cpp ARMMCInstLower.cpp + ARMMachineFunctionInfo.cpp ARMRegisterInfo.cpp ARMSelectionDAGInfo.cpp ARMSubtarget.cpp Modified: llvm/trunk/lib/Target/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CMakeLists.txt?rev=146966&r1=146965&r2=146966&view=diff ============================================================================== --- llvm/trunk/lib/Target/CMakeLists.txt (original) +++ llvm/trunk/lib/Target/CMakeLists.txt Tue Dec 20 02:42:11 2011 @@ -5,6 +5,7 @@ TargetELFWriterInfo.cpp TargetInstrInfo.cpp TargetIntrinsicInfo.cpp + TargetJITInfo.cpp TargetLibraryInfo.cpp TargetLoweringObjectFile.cpp TargetMachine.cpp Modified: llvm/trunk/lib/Target/CellSPU/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/CMakeLists.txt?rev=146966&r1=146965&r2=146966&view=diff ============================================================================== --- llvm/trunk/lib/Target/CellSPU/CMakeLists.txt (original) +++ llvm/trunk/lib/Target/CellSPU/CMakeLists.txt Tue Dec 20 02:42:11 2011 @@ -16,6 +16,7 @@ SPUISelDAGToDAG.cpp SPUISelLowering.cpp SPUFrameLowering.cpp + SPUMachineFunction.cpp SPURegisterInfo.cpp SPUSubtarget.cpp SPUTargetMachine.cpp Modified: llvm/trunk/lib/Target/MBlaze/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MBlaze/CMakeLists.txt?rev=146966&r1=146965&r2=146966&view=diff ============================================================================== --- llvm/trunk/lib/Target/MBlaze/CMakeLists.txt (original) +++ llvm/trunk/lib/Target/MBlaze/CMakeLists.txt Tue Dec 20 02:42:11 2011 @@ -18,6 +18,7 @@ MBlazeISelDAGToDAG.cpp MBlazeISelLowering.cpp MBlazeFrameLowering.cpp + MBlazeMachineFunction.cpp MBlazeRegisterInfo.cpp MBlazeSubtarget.cpp MBlazeTargetMachine.cpp Modified: llvm/trunk/lib/Target/MSP430/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MSP430/CMakeLists.txt?rev=146966&r1=146965&r2=146966&view=diff ============================================================================== --- llvm/trunk/lib/Target/MSP430/CMakeLists.txt (original) +++ llvm/trunk/lib/Target/MSP430/CMakeLists.txt Tue Dec 20 02:42:11 2011 @@ -14,6 +14,7 @@ MSP430ISelLowering.cpp MSP430InstrInfo.cpp MSP430FrameLowering.cpp + MSP430MachineFunctionInfo.cpp MSP430RegisterInfo.cpp MSP430Subtarget.cpp MSP430TargetMachine.cpp Modified: llvm/trunk/lib/Target/Mips/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/CMakeLists.txt?rev=146966&r1=146965&r2=146966&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/CMakeLists.txt (original) +++ llvm/trunk/lib/Target/Mips/CMakeLists.txt Tue Dec 20 02:42:11 2011 @@ -22,6 +22,7 @@ MipsISelLowering.cpp MipsFrameLowering.cpp MipsMCInstLower.cpp + MipsMachineFunction.cpp MipsRegisterInfo.cpp MipsSubtarget.cpp MipsTargetMachine.cpp Modified: llvm/trunk/lib/Target/PTX/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PTX/CMakeLists.txt?rev=146966&r1=146965&r2=146966&view=diff ============================================================================== --- llvm/trunk/lib/Target/PTX/CMakeLists.txt (original) +++ llvm/trunk/lib/Target/PTX/CMakeLists.txt Tue Dec 20 02:42:11 2011 @@ -17,6 +17,7 @@ PTXMCAsmStreamer.cpp PTXMCInstLower.cpp PTXMFInfoExtract.cpp + PTXMachineFunctionInfo.cpp PTXParamManager.cpp PTXRegAlloc.cpp PTXRegisterInfo.cpp Modified: llvm/trunk/lib/Target/PowerPC/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/CMakeLists.txt?rev=146966&r1=146965&r2=146966&view=diff ============================================================================== --- llvm/trunk/lib/Target/PowerPC/CMakeLists.txt (original) +++ llvm/trunk/lib/Target/PowerPC/CMakeLists.txt Tue Dec 20 02:42:11 2011 @@ -21,6 +21,7 @@ PPCFrameLowering.cpp PPCJITInfo.cpp PPCMCInstLower.cpp + PPCMachineFunctionInfo.cpp PPCRegisterInfo.cpp PPCSubtarget.cpp PPCTargetMachine.cpp Modified: llvm/trunk/lib/Target/Sparc/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/CMakeLists.txt?rev=146966&r1=146965&r2=146966&view=diff ============================================================================== --- llvm/trunk/lib/Target/Sparc/CMakeLists.txt (original) +++ llvm/trunk/lib/Target/Sparc/CMakeLists.txt Tue Dec 20 02:42:11 2011 @@ -16,6 +16,7 @@ SparcISelDAGToDAG.cpp SparcISelLowering.cpp SparcFrameLowering.cpp + SparcMachineFunctionInfo.cpp SparcRegisterInfo.cpp SparcSubtarget.cpp SparcTargetMachine.cpp Modified: llvm/trunk/lib/Target/X86/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/CMakeLists.txt?rev=146966&r1=146965&r2=146966&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/CMakeLists.txt (original) +++ llvm/trunk/lib/Target/X86/CMakeLists.txt Tue Dec 20 02:42:11 2011 @@ -26,6 +26,7 @@ X86InstrInfo.cpp X86JITInfo.cpp X86MCInstLower.cpp + X86MachineFunctionInfo.cpp X86RegisterInfo.cpp X86SelectionDAGInfo.cpp X86Subtarget.cpp Modified: llvm/trunk/lib/Target/XCore/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/XCore/CMakeLists.txt?rev=146966&r1=146965&r2=146966&view=diff ============================================================================== --- llvm/trunk/lib/Target/XCore/CMakeLists.txt (original) +++ llvm/trunk/lib/Target/XCore/CMakeLists.txt Tue Dec 20 02:42:11 2011 @@ -14,6 +14,7 @@ XCoreInstrInfo.cpp XCoreISelDAGToDAG.cpp XCoreISelLowering.cpp + XCoreMachineFunctionInfo.cpp XCoreRegisterInfo.cpp XCoreSubtarget.cpp XCoreTargetMachine.cpp Modified: llvm/trunk/utils/TableGen/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/CMakeLists.txt?rev=146966&r1=146965&r2=146966&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/CMakeLists.txt (original) +++ llvm/trunk/utils/TableGen/CMakeLists.txt Tue Dec 20 02:42:11 2011 @@ -33,5 +33,6 @@ TGValueTypes.cpp TableGen.cpp X86DisassemblerTables.cpp + X86ModRMFilters.cpp X86RecognizableInstr.cpp ) From chandlerc at google.com Tue Dec 20 02:46:59 2011 From: chandlerc at google.com (Chandler Carruth) Date: Tue, 20 Dec 2011 00:46:59 -0800 Subject: [llvm-commits] [llvm] r146960 - in /llvm/trunk: include/llvm/ include/llvm/ADT/ include/llvm/Analysis/ include/llvm/CodeGen/ include/llvm/MC/ include/llvm/Object/ include/llvm/TableGen/ include/llvm/Target/ include/llvm/Transforms/Utils/ lib/Anal Message-ID: On Mon, Dec 19, 2011 at 11:47 PM, Chad Rosier wrote: > David, > Could you please update the CMakeList.txt? > I've fixed them in r146966. -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20111220/ad622aae/attachment.html From mcrosier at apple.com Tue Dec 20 02:54:49 2011 From: mcrosier at apple.com (Chad Rosier) Date: Tue, 20 Dec 2011 00:54:49 -0800 Subject: [llvm-commits] [llvm] r146960 - in /llvm/trunk: include/llvm/ include/llvm/ADT/ include/llvm/Analysis/ include/llvm/CodeGen/ include/llvm/MC/ include/llvm/Object/ include/llvm/TableGen/ include/llvm/Target/ include/llvm/Transforms/Utils/ lib/Anal In-Reply-To: References: Message-ID: <6BE840F7-3D6A-4792-AAE5-6C9333B9CF10@apple.com> Nice. Thanks, Chandler. On Dec 20, 2011, at 12:46 AM, Chandler Carruth wrote: > On Mon, Dec 19, 2011 at 11:47 PM, Chad Rosier wrote: > David, > Could you please update the CMakeList.txt? > > I've fixed them in r146966. -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20111220/dbe5841b/attachment.html From klimek at google.com Tue Dec 20 03:26:26 2011 From: klimek at google.com (Manuel Klimek) Date: Tue, 20 Dec 2011 09:26:26 -0000 Subject: [llvm-commits] [llvm] r146968 - in /llvm/trunk: include/llvm/Support/JSONParser.h lib/Support/JSONParser.cpp Message-ID: <20111220092626.A468C1BE003@llvm.org> Author: klimek Date: Tue Dec 20 03:26:26 2011 New Revision: 146968 URL: http://llvm.org/viewvc/llvm-project?rev=146968&view=rev Log: Addressing style issues in JSON parser. Modified: llvm/trunk/include/llvm/Support/JSONParser.h llvm/trunk/lib/Support/JSONParser.cpp Modified: llvm/trunk/include/llvm/Support/JSONParser.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Support/JSONParser.h?rev=146968&r1=146967&r2=146968&view=diff ============================================================================== --- llvm/trunk/include/llvm/Support/JSONParser.h (original) +++ llvm/trunk/include/llvm/Support/JSONParser.h Tue Dec 20 03:26:26 2011 @@ -1,4 +1,4 @@ -//===--- JsonParser.h - Simple JSON parser ----------------------*- C++ -*-===// +//===--- JSONParser.h - Simple JSON parser ----------------------*- C++ -*-===// // // The LLVM Compiler Infrastructure // @@ -17,15 +17,13 @@ // //===----------------------------------------------------------------------===// -#ifndef LLVM_CLANG_TOOLING_JSON_PARSER_H -#define LLVM_CLANG_TOOLING_JSON_PARSER_H +#ifndef LLVM_SUPPORT_JSON_PARSER_H +#define LLVM_SUPPORT_JSON_PARSER_H #include "llvm/ADT/StringRef.h" #include "llvm/Support/Allocator.h" #include "llvm/Support/ErrorHandling.h" -#include - namespace llvm { class JSONString; @@ -441,4 +439,4 @@ } // end namespace llvm -#endif // LLVM_CLANG_TOOLING_JSON_PARSER_H +#endif // LLVM_SUPPORT_JSON_PARSER_H Modified: llvm/trunk/lib/Support/JSONParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Support/JSONParser.cpp?rev=146968&r1=146967&r2=146968&view=diff ============================================================================== --- llvm/trunk/lib/Support/JSONParser.cpp (original) +++ llvm/trunk/lib/Support/JSONParser.cpp Tue Dec 20 03:26:26 2011 @@ -1,4 +1,4 @@ -//===--- JsonParser.cpp - Simple JSON parser ------------------------------===// +//===--- JSONParser.cpp - Simple JSON parser ------------------------------===// // // The LLVM Compiler Infrastructure // @@ -16,7 +16,7 @@ #include "llvm/ADT/Twine.h" #include "llvm/Support/Casting.h" -namespace llvm { +using namespace llvm; JSONParser::JSONParser(StringRef Input) : Input(Input), Position(Input.begin()) {} @@ -217,5 +217,3 @@ template <> JSONKeyValuePair *JSONParser::parseElement() { return parseKeyValuePair(); } - -} // end namespace llvm From chandlerc at google.com Tue Dec 20 04:03:26 2011 From: chandlerc at google.com (Chandler Carruth) Date: Tue, 20 Dec 2011 02:03:26 -0800 Subject: [llvm-commits] [llvm] r146801 - in /llvm/trunk: include/llvm/MC/MCStreamer.h lib/CodeGen/AsmPrinter/AsmPrinterDwarf.cpp lib/MC/MCAsmStreamer.cpp lib/MC/MCLoggingStreamer.cpp lib/MC/MCNullStreamer.cpp lib/MC/MCParser/COFFAsmParser.cpp lib/MC/MCStr Message-ID: On Fri, Dec 16, 2011 at 5:14 PM, Rafael Espindola < rafael.espindola at gmail.com> wrote: > Modified: llvm/trunk/lib/MC/WinCOFFStreamer.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC > /WinCOFFStreamer.cpp?rev=146801&r1=146800&r2=146801&view=diff > > ============================================================================== > --- llvm/trunk/lib/MC/WinCOFFStreamer.cpp (original) > +++ llvm/trunk/lib/MC/WinCOFFStreamer.cpp Fri Dec 16 19:14:52 2011 > @@ -32,6 +32,9 @@ > #include "llvm/Support/ErrorHandling.h" > #include "llvm/Support/TargetRegistry.h" > #include "llvm/Support/raw_ostream.h" > + > +#include "../Target/X86/MCTargetDesc/X86FixupKinds.h" > + > This is a pretty egregious layering violation. Please fix or revert, this causes all kinds of problems with improper dependencies between various components. -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20111220/35390f5d/attachment.html From klimek at google.com Tue Dec 20 04:34:29 2011 From: klimek at google.com (Manuel Klimek) Date: Tue, 20 Dec 2011 10:34:29 -0000 Subject: [llvm-commits] [llvm] r146970 - /llvm/trunk/utils/json-bench/JSONBench.cpp Message-ID: <20111220103429.CCE2A1BE003@llvm.org> Author: klimek Date: Tue Dec 20 04:34:29 2011 New Revision: 146970 URL: http://llvm.org/viewvc/llvm-project?rev=146970&view=rev Log: Fixing option for JSON benchmark broken since the change to size_t. Modified: llvm/trunk/utils/json-bench/JSONBench.cpp Modified: llvm/trunk/utils/json-bench/JSONBench.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/json-bench/JSONBench.cpp?rev=146970&r1=146969&r2=146970&view=diff ============================================================================== --- llvm/trunk/utils/json-bench/JSONBench.cpp (original) +++ llvm/trunk/utils/json-bench/JSONBench.cpp Tue Dec 20 04:34:29 2011 @@ -23,7 +23,7 @@ "Run a quick verification useful for regression testing"), llvm::cl::init(false)); -static llvm::cl::opt +static llvm::cl::opt MemoryLimitMB("memory-limit", llvm::cl::desc( "Do not use more megabytes of memory"), llvm::cl::init(1000)); From klimek at google.com Tue Dec 20 04:42:53 2011 From: klimek at google.com (Manuel Klimek) Date: Tue, 20 Dec 2011 10:42:53 -0000 Subject: [llvm-commits] [llvm] r146971 - in /llvm/trunk: include/llvm/Support/JSONParser.h lib/Support/JSONParser.cpp Message-ID: <20111220104253.222F81BE003@llvm.org> Author: klimek Date: Tue Dec 20 04:42:52 2011 New Revision: 146971 URL: http://llvm.org/viewvc/llvm-project?rev=146971&view=rev Log: Pulls the implementation of skip() into JSONParser. This is the first step towards migrating more of the parser implementation into the parser class. Modified: llvm/trunk/include/llvm/Support/JSONParser.h llvm/trunk/lib/Support/JSONParser.cpp Modified: llvm/trunk/include/llvm/Support/JSONParser.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Support/JSONParser.h?rev=146971&r1=146970&r2=146971&view=diff ============================================================================== --- llvm/trunk/include/llvm/Support/JSONParser.h (original) +++ llvm/trunk/include/llvm/Support/JSONParser.h Tue Dec 20 04:42:52 2011 @@ -48,10 +48,6 @@ JSONAtom(Kind MyKind) : MyKind(MyKind) {} private: - /// \brief Parses to the end of the object and returns whether parsing - /// was successful. - bool skip() const; - Kind MyKind; friend class JSONParser; @@ -76,8 +72,8 @@ /// \brief Returns the outermost JSON value (either an array or an object). /// /// Can return NULL if the input does not start with an array or an object. - /// The object is not parsed yet - the caller must either iterate over the - /// returned object or call 'skip' to trigger parsing. + /// The object is not parsed yet - the caller must iterate over the + /// returned object to trigger parsing. /// /// A JSONValue can be either a JSONString, JSONObject or JSONArray. JSONValue *parseRoot(); @@ -130,6 +126,13 @@ bool errorIfNotAt(char C, StringRef Message); /// } + /// \brief Skips all elements in the given container. + template + bool skipContainer(const ContainerT &Container); + + /// \brief Skips to the next position behind the given JSON atom. + bool skip(const JSONAtom &Atom); + /// All nodes are allocated by the parser and will be deallocated when the /// parser is destroyed. BumpPtrAllocator ValueAllocator; @@ -191,9 +194,6 @@ private: JSONString(StringRef RawText) : JSONValue(JK_String), RawText(RawText) {} - /// \brief Skips to the next position in the parse stream. - bool skip() const { return true; }; - StringRef RawText; friend class JSONAtom; @@ -223,9 +223,6 @@ JSONKeyValuePair(const JSONString *Key, const JSONValue *Value) : JSONAtom(JK_KeyValuePair), Key(Key), Value(Value) {} - /// \brief Skips to the next position in the parse stream. - bool skip() const { return Value->skip(); }; - friend class JSONAtom; friend class JSONParser; template friend class JSONContainer; @@ -243,8 +240,7 @@ /// \brief Implementation of JSON containers (arrays and objects). /// /// JSONContainers drive the lazy parsing of JSON arrays and objects via -/// forward iterators. Call 'skip' to validate parsing of all elements of the -/// container and to position the parse stream behind the container. +/// forward iterators. template class JSONContainer : public JSONValue { @@ -320,23 +316,13 @@ return const_iterator(this); } - /// \brief Skips to the next position in the parse stream. - bool skip() const { - for (const_iterator I = current(), E = end(); I != E; ++I) { - assert(*I != 0); - if (!(*I)->skip()) - return false; - } - return !Parser->failed(); - } - /// \brief Parse the next element in the container into the Current element. /// /// This routine is called as an iterator into this container walks through /// its elements. It mutates the container's internal current node to point to /// the next atom of the container. void parseNextElement() const { - Current->skip(); + Parser->skip(*Current); Position = Parser->parseNextElement(Current); } Modified: llvm/trunk/lib/Support/JSONParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Support/JSONParser.cpp?rev=146971&r1=146970&r2=146971&view=diff ============================================================================== --- llvm/trunk/lib/Support/JSONParser.cpp (original) +++ llvm/trunk/lib/Support/JSONParser.cpp Tue Dec 20 04:42:52 2011 @@ -40,7 +40,30 @@ } bool JSONParser::validate() { - return parseRoot()->skip(); + return skip(*parseRoot()); +} + +template +bool JSONParser::skipContainer(const ContainerT &Container) { + for (typename ContainerT::const_iterator I = Container.current(), + E = Container.end(); + I != E; ++I) { + assert(*I != 0); + if (!skip(**I)) + return false; + } + return !failed(); +} + +bool JSONParser::skip(const JSONAtom &Atom) { + switch(Atom.getKind()) { + case JSONAtom::JK_Array: return skipContainer(*cast(&Atom)); + case JSONAtom::JK_Object: return skipContainer(*cast(&Atom)); + case JSONAtom::JK_String: return true; + case JSONAtom::JK_KeyValuePair: + return skip(*cast(&Atom)->Value); + } + llvm_unreachable("Impossible enum value."); } // Sets the current error to: @@ -159,16 +182,6 @@ return ErrorMessage; } -bool JSONAtom::skip() const { - switch (MyKind) { - case JK_Array: return cast(this)->skip(); - case JK_Object: return cast(this)->skip(); - case JK_String: return cast(this)->skip(); - case JK_KeyValuePair: return cast(this)->skip(); - } - llvm_unreachable("Impossible enum value."); -} - // Parses a JSONValue, assuming that the current position is at the first // character of the value. JSONValue *JSONParser::parseValue() { From grosser at fim.uni-passau.de Tue Dec 20 04:43:14 2011 From: grosser at fim.uni-passau.de (Tobias Grosser) Date: Tue, 20 Dec 2011 10:43:14 -0000 Subject: [llvm-commits] [polly] r146972 - in /polly/trunk: include/polly/TempScopInfo.h lib/Analysis/ScopDetection.cpp lib/Analysis/ScopInfo.cpp lib/Analysis/TempScopInfo.cpp test/CodeGen/simple_nonaffine_loop.c test/CodeGen/simple_nonaffine_loop.ll test/ScopInfo/simple_nonaffine_loop.ll test/ScopInfo/simple_nonaffine_loop_not.ll Message-ID: <20111220104314.7AA031BE003@llvm.org> Author: grosser Date: Tue Dec 20 04:43:14 2011 New Revision: 146972 URL: http://llvm.org/viewvc/llvm-project?rev=146972&view=rev Log: Support non-affine access functions in Polly. In case we can not analyze an access function, we do not discard the SCoP, but assume conservatively that all memory accesses that can be derived from our base pointer may be accessed. Patch provided by: Marcello Maggioni Added: polly/trunk/test/CodeGen/simple_nonaffine_loop.c polly/trunk/test/CodeGen/simple_nonaffine_loop.ll polly/trunk/test/ScopInfo/simple_nonaffine_loop.ll polly/trunk/test/ScopInfo/simple_nonaffine_loop_not.ll Modified: polly/trunk/include/polly/TempScopInfo.h polly/trunk/lib/Analysis/ScopDetection.cpp polly/trunk/lib/Analysis/ScopInfo.cpp polly/trunk/lib/Analysis/TempScopInfo.cpp Modified: polly/trunk/include/polly/TempScopInfo.h URL: http://llvm.org/viewvc/llvm-project/polly/trunk/include/polly/TempScopInfo.h?rev=146972&r1=146971&r2=146972&view=diff ============================================================================== --- polly/trunk/include/polly/TempScopInfo.h (original) +++ polly/trunk/include/polly/TempScopInfo.h Tue Dec 20 04:43:14 2011 @@ -45,12 +45,13 @@ private: unsigned ElemBytes; TypeKind Type; + bool IsAffine; public: explicit IRAccess (TypeKind Type, const Value *BaseAddress, - const SCEV *Offset, unsigned elemBytes) + const SCEV *Offset, unsigned elemBytes, bool Affine) : BaseAddress(BaseAddress), Offset(Offset), - ElemBytes(elemBytes), Type(Type) {} + ElemBytes(elemBytes), Type(Type), IsAffine(Affine) {} enum TypeKind getType() const { return Type; } @@ -60,7 +61,10 @@ unsigned getElemSizeInBytes() const { return ElemBytes; } + bool isAffine() const { return IsAffine; } + bool isRead() const { return Type == READ; } + }; class Comparison { Modified: polly/trunk/lib/Analysis/ScopDetection.cpp URL: http://llvm.org/viewvc/llvm-project/polly/trunk/lib/Analysis/ScopDetection.cpp?rev=146972&r1=146971&r2=146972&view=diff ============================================================================== --- polly/trunk/lib/Analysis/ScopDetection.cpp (original) +++ polly/trunk/lib/Analysis/ScopDetection.cpp Tue Dec 20 04:43:14 2011 @@ -79,6 +79,11 @@ cl::desc("Ignore possible aliasing of the array bases"), cl::Hidden, cl::init(false)); +static cl::opt +AllowNonAffine("polly-allow-nonaffine", + cl::desc("Allow non affine access functions in arrays"), + cl::Hidden, cl::init(false)); + //===----------------------------------------------------------------------===// // Statistics. @@ -245,7 +250,7 @@ AccessFunction = SE->getMinusSCEV(AccessFunction, BasePointer); - if (!isAffineExpr(&Context.CurRegion, AccessFunction, *SE, BaseValue)) + if (!isAffineExpr(&Context.CurRegion, AccessFunction, *SE, BaseValue) && !AllowNonAffine) INVALID(AffFunc, "Bad memory address " << *AccessFunction); // FIXME: Alias Analysis thinks IntToPtrInst aliases with alloca instructions Modified: polly/trunk/lib/Analysis/ScopInfo.cpp URL: http://llvm.org/viewvc/llvm-project/polly/trunk/lib/Analysis/ScopInfo.cpp?rev=146972&r1=146971&r2=146972&view=diff ============================================================================== --- polly/trunk/lib/Analysis/ScopInfo.cpp (original) +++ polly/trunk/lib/Analysis/ScopInfo.cpp Tue Dec 20 04:43:14 2011 @@ -312,9 +312,16 @@ Type = Access.isRead() ? Read : Write; statement = Statement; - isl_pw_aff *Affine = SCEVAffinator::getPwAff(Statement, Access.getOffset()); BaseAddr = Access.getBase(); + if (!Access.isAffine()) { + Type = (Type == Read) ? Read : MayWrite; + AccessRelation = isl_map_from_basic_map(createBasicAccessMap(Statement)); + return; + } + + isl_pw_aff *Affine = SCEVAffinator::getPwAff(Statement, Access.getOffset()); + setBaseName(); // Devide the access function by the size of the elements in the array. Modified: polly/trunk/lib/Analysis/TempScopInfo.cpp URL: http://llvm.org/viewvc/llvm-project/polly/trunk/lib/Analysis/TempScopInfo.cpp?rev=146972&r1=146971&r2=146972&view=diff ============================================================================== --- polly/trunk/lib/Analysis/TempScopInfo.cpp (original) +++ polly/trunk/lib/Analysis/TempScopInfo.cpp Tue Dec 20 04:43:14 2011 @@ -98,11 +98,15 @@ dyn_cast(SE->getPointerBase(AccessFunction)); assert(BasePointer && "Could not find base pointer"); - AccessFunction = SE->getMinusSCEV(AccessFunction, BasePointer); + + bool IsAffine = isAffineExpr(&R, AccessFunction, *SE, + BasePointer->getValue()); + Functions.push_back(std::make_pair(IRAccess(Type, BasePointer->getValue(), - AccessFunction, Size), + AccessFunction, Size, + IsAffine), &Inst)); } } Added: polly/trunk/test/CodeGen/simple_nonaffine_loop.c URL: http://llvm.org/viewvc/llvm-project/polly/trunk/test/CodeGen/simple_nonaffine_loop.c?rev=146972&view=auto ============================================================================== --- polly/trunk/test/CodeGen/simple_nonaffine_loop.c (added) +++ polly/trunk/test/CodeGen/simple_nonaffine_loop.c Tue Dec 20 04:43:14 2011 @@ -0,0 +1,15 @@ +#include +#include +#include + +int main() +{ + int A[1024*1024]; + int i; + for (i = 0; i < 1024; i++) + A[i*i] = 2*i; + + printf("Random Value: %d", A[rand() % 1024*1024]); + + return 0; +} Added: polly/trunk/test/CodeGen/simple_nonaffine_loop.ll URL: http://llvm.org/viewvc/llvm-project/polly/trunk/test/CodeGen/simple_nonaffine_loop.ll?rev=146972&view=auto ============================================================================== --- polly/trunk/test/CodeGen/simple_nonaffine_loop.ll (added) +++ polly/trunk/test/CodeGen/simple_nonaffine_loop.ll Tue Dec 20 04:43:14 2011 @@ -0,0 +1,43 @@ +; RUN: opt %loadPolly %defaultOpts -O3 -polly-cloog -polly-allow-nonaffine -analyze %s | FileCheck %s +; ModuleID = 'simple_nonaffine_loop.c' +target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128" +target triple = "x86_64-apple-macosx10.7.2" + + at .str = private unnamed_addr constant [17 x i8] c"Random Value: %d\00", align 1 + +define i32 @main() nounwind uwtable ssp { +entry: + %A = alloca [1048576 x i32], align 16 + br label %entry.split + +entry.split: ; preds = %entry + br label %for.body + +for.body: ; preds = %entry.split, %for.body + %0 = phi i32 [ 0, %entry.split ], [ %1, %for.body ] + %mul = mul i32 %0, 2 + %mul1 = mul nsw i32 %0, %0 + %idxprom1 = zext i32 %mul1 to i64 + %arrayidx = getelementptr inbounds [1048576 x i32]* %A, i64 0, i64 %idxprom1 + store i32 %mul, i32* %arrayidx, align 4 + %1 = add nsw i32 %0, 1 + %exitcond = icmp ne i32 %1, 1024 + br i1 %exitcond, label %for.body, label %for.end + +for.end: ; preds = %for.body + %call = call i32 @rand() nounwind + %rem = srem i32 %call, 1024 + %mul2 = shl nsw i32 %rem, 10 + %idxprom3 = sext i32 %mul2 to i64 + %arrayidx4 = getelementptr inbounds [1048576 x i32]* %A, i64 0, i64 %idxprom3 + %2 = load i32* %arrayidx4, align 16 + %call5 = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([17 x i8]* @.str, i64 0, i64 0), i32 %2) nounwind + ret i32 0 +} + +declare i32 @printf(i8*, ...) + +declare i32 @rand() +; CHECK: for (c2=0;c2<=1023;c2++) { +; CHECK: Stmt_for_body(c2); +; CHECK: } Added: polly/trunk/test/ScopInfo/simple_nonaffine_loop.ll URL: http://llvm.org/viewvc/llvm-project/polly/trunk/test/ScopInfo/simple_nonaffine_loop.ll?rev=146972&view=auto ============================================================================== --- polly/trunk/test/ScopInfo/simple_nonaffine_loop.ll (added) +++ polly/trunk/test/ScopInfo/simple_nonaffine_loop.ll Tue Dec 20 04:43:14 2011 @@ -0,0 +1,41 @@ +; RUN: opt %loadPolly %defaultOpts -polly-scops -polly-allow-nonaffine -analyze %s | FileCheck %s +; ModuleID = 'simple_nonaffine_loop.c' +target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128" +target triple = "x86_64-apple-macosx10.7.2" + + at .str = private unnamed_addr constant [17 x i8] c"Random Value: %d\00", align 1 + +define i32 @main() nounwind uwtable ssp { +entry: + %A = alloca [1048576 x i32], align 16 + br label %entry.split + +entry.split: ; preds = %entry + br label %for.body + +for.body: ; preds = %entry.split, %for.body + %0 = phi i32 [ 0, %entry.split ], [ %1, %for.body ] + %mul = mul i32 %0, 2 + %mul1 = mul nsw i32 %0, %0 + %idxprom1 = zext i32 %mul1 to i64 + %arrayidx = getelementptr inbounds [1048576 x i32]* %A, i64 0, i64 %idxprom1 + store i32 %mul, i32* %arrayidx, align 4 + %1 = add nsw i32 %0, 1 + %exitcond = icmp ne i32 %1, 1024 + br i1 %exitcond, label %for.body, label %for.end + +for.end: ; preds = %for.body + %call = call i32 @rand() nounwind + %rem = srem i32 %call, 1024 + %mul2 = shl nsw i32 %rem, 10 + %idxprom3 = sext i32 %mul2 to i64 + %arrayidx4 = getelementptr inbounds [1048576 x i32]* %A, i64 0, i64 %idxprom3 + %2 = load i32* %arrayidx4, align 16 + %call5 = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([17 x i8]* @.str, i64 0, i64 0), i32 %2) nounwind + ret i32 0 +} + +declare i32 @printf(i8*, ...) + +declare i32 @rand() +; CHECK: { Stmt_for_body[i0] -> MemRef_A[o0] }; Added: polly/trunk/test/ScopInfo/simple_nonaffine_loop_not.ll URL: http://llvm.org/viewvc/llvm-project/polly/trunk/test/ScopInfo/simple_nonaffine_loop_not.ll?rev=146972&view=auto ============================================================================== --- polly/trunk/test/ScopInfo/simple_nonaffine_loop_not.ll (added) +++ polly/trunk/test/ScopInfo/simple_nonaffine_loop_not.ll Tue Dec 20 04:43:14 2011 @@ -0,0 +1,41 @@ +; RUN: opt %loadPolly %defaultOpts -polly-scops -analyze %s | not FileCheck %s +; ModuleID = 'simple_nonaffine_loop.c' +target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128" +target triple = "x86_64-apple-macosx10.7.2" + + at .str = private unnamed_addr constant [17 x i8] c"Random Value: %d\00", align 1 + +define i32 @main() nounwind uwtable ssp { +entry: + %A = alloca [1048576 x i32], align 16 + br label %entry.split + +entry.split: ; preds = %entry + br label %for.body + +for.body: ; preds = %entry.split, %for.body + %0 = phi i32 [ 0, %entry.split ], [ %1, %for.body ] + %mul = mul i32 %0, 2 + %mul1 = mul nsw i32 %0, %0 + %idxprom1 = zext i32 %mul1 to i64 + %arrayidx = getelementptr inbounds [1048576 x i32]* %A, i64 0, i64 %idxprom1 + store i32 %mul, i32* %arrayidx, align 4 + %1 = add nsw i32 %0, 1 + %exitcond = icmp ne i32 %1, 1024 + br i1 %exitcond, label %for.body, label %for.end + +for.end: ; preds = %for.body + %call = call i32 @rand() nounwind + %rem = srem i32 %call, 1024 + %mul2 = shl nsw i32 %rem, 10 + %idxprom3 = sext i32 %mul2 to i64 + %arrayidx4 = getelementptr inbounds [1048576 x i32]* %A, i64 0, i64 %idxprom3 + %2 = load i32* %arrayidx4, align 16 + %call5 = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([17 x i8]* @.str, i64 0, i64 0), i32 %2) nounwind + ret i32 0 +} + +declare i32 @printf(i8*, ...) + +declare i32 @rand() +; CHECK: { Stmt_for_body[i0] -> MemRef_A[o0] }; From chandlerc at google.com Tue Dec 20 04:51:51 2011 From: chandlerc at google.com (Chandler Carruth) Date: Tue, 20 Dec 2011 02:51:51 -0800 Subject: [llvm-commits] [llvm] r146971 - in /llvm/trunk: include/llvm/Support/JSONParser.h lib/Support/JSONParser.cpp In-Reply-To: <20111220104253.222F81BE003@llvm.org> References: <20111220104253.222F81BE003@llvm.org> Message-ID: On Tue, Dec 20, 2011 at 2:42 AM, Manuel Klimek wrote: > Modified: llvm/trunk/lib/Support/JSONParser.cpp > URL: > http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Support/JSONParser.cpp?rev=146971&r1=146970&r2=146971&view=diff > > ============================================================================== > --- llvm/trunk/lib/Support/JSONParser.cpp (original) > +++ llvm/trunk/lib/Support/JSONParser.cpp Tue Dec 20 04:42:52 2011 > @@ -40,7 +40,30 @@ > } > > bool JSONParser::validate() { > - return parseRoot()->skip(); > + return skip(*parseRoot()); > +} > + > +template > +bool JSONParser::skipContainer(const ContainerT &Container) { > + for (typename ContainerT::const_iterator I = Container.current(), > + E = Container.end(); > + I != E; ++I) { > + assert(*I != 0); > + if (!skip(**I)) > + return false; > + } > + return !failed(); > +} > Again, you can't just define template functions in the source file. Until this is de-templated, this definition needs to be available in the header. =/ -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20111220/c5952fb5/attachment.html From klimek at google.com Tue Dec 20 05:04:23 2011 From: klimek at google.com (Manuel Klimek) Date: Tue, 20 Dec 2011 11:04:23 -0000 Subject: [llvm-commits] [llvm] r146973 - in /llvm/trunk: include/llvm/Support/JSONParser.h lib/Support/JSONParser.cpp Message-ID: <20111220110423.C75061BE003@llvm.org> Author: klimek Date: Tue Dec 20 05:04:23 2011 New Revision: 146973 URL: http://llvm.org/viewvc/llvm-project?rev=146973&view=rev Log: Fixes a potential compilation error. Pulling the template implementation into the header to guarantee that it's visible to all possible instantiations. Modified: llvm/trunk/include/llvm/Support/JSONParser.h llvm/trunk/lib/Support/JSONParser.cpp Modified: llvm/trunk/include/llvm/Support/JSONParser.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Support/JSONParser.h?rev=146973&r1=146972&r2=146973&view=diff ============================================================================== --- llvm/trunk/include/llvm/Support/JSONParser.h (original) +++ llvm/trunk/include/llvm/Support/JSONParser.h Tue Dec 20 05:04:23 2011 @@ -128,7 +128,16 @@ /// \brief Skips all elements in the given container. template - bool skipContainer(const ContainerT &Container); + bool skipContainer(const ContainerT &Container) { + for (typename ContainerT::const_iterator I = Container.current(), + E = Container.end(); + I != E; ++I) { + assert(*I != 0); + if (!skip(**I)) + return false; + } + return !failed(); + } /// \brief Skips to the next position behind the given JSON atom. bool skip(const JSONAtom &Atom); Modified: llvm/trunk/lib/Support/JSONParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Support/JSONParser.cpp?rev=146973&r1=146972&r2=146973&view=diff ============================================================================== --- llvm/trunk/lib/Support/JSONParser.cpp (original) +++ llvm/trunk/lib/Support/JSONParser.cpp Tue Dec 20 05:04:23 2011 @@ -43,18 +43,6 @@ return skip(*parseRoot()); } -template -bool JSONParser::skipContainer(const ContainerT &Container) { - for (typename ContainerT::const_iterator I = Container.current(), - E = Container.end(); - I != E; ++I) { - assert(*I != 0); - if (!skip(**I)) - return false; - } - return !failed(); -} - bool JSONParser::skip(const JSONAtom &Atom) { switch(Atom.getKind()) { case JSONAtom::JK_Array: return skipContainer(*cast(&Atom)); From klimek at google.com Tue Dec 20 05:07:40 2011 From: klimek at google.com (Manuel Klimek) Date: Tue, 20 Dec 2011 12:07:40 +0100 Subject: [llvm-commits] [llvm] r146971 - in /llvm/trunk: include/llvm/Support/JSONParser.h lib/Support/JSONParser.cpp In-Reply-To: References: <20111220104253.222F81BE003@llvm.org> Message-ID: On Tue, Dec 20, 2011 at 11:51 AM, Chandler Carruth wrote: > On Tue, Dec 20, 2011 at 2:42 AM, Manuel Klimek wrote: >> >> Modified: llvm/trunk/lib/Support/JSONParser.cpp >> URL: >> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Support/JSONParser.cpp?rev=146971&r1=146970&r2=146971&view=diff >> >> ============================================================================== >> --- llvm/trunk/lib/Support/JSONParser.cpp (original) >> +++ llvm/trunk/lib/Support/JSONParser.cpp Tue Dec 20 04:42:52 2011 >> @@ -40,7 +40,30 @@ >> ?} >> >> ?bool JSONParser::validate() { >> - ?return parseRoot()->skip(); >> + ?return skip(*parseRoot()); >> +} >> + >> +template >> +bool JSONParser::skipContainer(const ContainerT &Container) { >> + ?for (typename ContainerT::const_iterator I = Container.current(), >> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? E = Container.end(); >> + ? ? ? I != E; ++I) { >> + ? ?assert(*I != 0); >> + ? ?if (!skip(**I)) >> + ? ? ?return false; >> + ?} >> + ?return !failed(); >> +} > > > Again, you can't just define template functions in the source file. Until > this is de-templated, this definition needs to be available in the header. > =/ Done. From chandlerc at gmail.com Tue Dec 20 05:19:37 2011 From: chandlerc at gmail.com (Chandler Carruth) Date: Tue, 20 Dec 2011 11:19:37 -0000 Subject: [llvm-commits] [llvm] r146974 - in /llvm/trunk: lib/Target/X86/X86ISelLowering.cpp lib/Target/X86/X86InstrCompiler.td test/CodeGen/X86/clz.ll Message-ID: <20111220111937.BE6341BE003@llvm.org> Author: chandlerc Date: Tue Dec 20 05:19:37 2011 New Revision: 146974 URL: http://llvm.org/viewvc/llvm-project?rev=146974&view=rev Log: Begin teaching the X86 target how to efficiently codegen patterns that use the zero-undefined variants of CTTZ and CTLZ. These are just simple patterns for now, there is more to be done to make real world code using these constructs be optimized and codegen'ed properly on X86. The existing tests are spiffed up to check that we no longer generate unnecessary cmov instructions, and that we generate the very important 'xor' to transform bsr which counts the index of the most significant one bit to the number of leading (most significant) zero bits. Also they now check that when the variant with defined zero result is used, the cmov is still produced. Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp llvm/trunk/lib/Target/X86/X86InstrCompiler.td llvm/trunk/test/CodeGen/X86/clz.ll Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=146974&r1=146973&r2=146974&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original) +++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Tue Dec 20 05:19:37 2011 @@ -380,9 +380,6 @@ setOperationAction(ISD::FLT_ROUNDS_ , MVT::i32 , Custom); setOperationAction(ISD::CTTZ_ZERO_UNDEF , MVT::i8 , Expand); - setOperationAction(ISD::CTTZ_ZERO_UNDEF , MVT::i16 , Expand); - setOperationAction(ISD::CTTZ_ZERO_UNDEF , MVT::i32 , Expand); - setOperationAction(ISD::CTTZ_ZERO_UNDEF , MVT::i64 , Expand); if (Subtarget->hasBMI()) { setOperationAction(ISD::CTTZ , MVT::i8 , Promote); } else { @@ -394,9 +391,6 @@ } setOperationAction(ISD::CTLZ_ZERO_UNDEF , MVT::i8 , Expand); - setOperationAction(ISD::CTLZ_ZERO_UNDEF , MVT::i16 , Expand); - setOperationAction(ISD::CTLZ_ZERO_UNDEF , MVT::i32 , Expand); - setOperationAction(ISD::CTLZ_ZERO_UNDEF , MVT::i64 , Expand); if (Subtarget->hasLZCNT()) { setOperationAction(ISD::CTLZ , MVT::i8 , Promote); } else { Modified: llvm/trunk/lib/Target/X86/X86InstrCompiler.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrCompiler.td?rev=146974&r1=146973&r2=146974&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86InstrCompiler.td (original) +++ llvm/trunk/lib/Target/X86/X86InstrCompiler.td Tue Dec 20 05:19:37 2011 @@ -1753,3 +1753,20 @@ (AND64ri8 GR64:$src1, i64immSExt8:$src2)>; def : Pat<(and GR64:$src1, i64immSExt32:$src2), (AND64ri32 GR64:$src1, i64immSExt32:$src2)>; + +// Bit scan instruction patterns to match explicit zero-undef behavior. +def : Pat<(cttz_zero_undef GR16:$src), (BSF16rr GR16:$src)>; +def : Pat<(cttz_zero_undef GR32:$src), (BSF32rr GR32:$src)>; +def : Pat<(cttz_zero_undef GR64:$src), (BSF64rr GR64:$src)>; +def : Pat<(cttz_zero_undef (loadi16 addr:$src)), (BSF16rm addr:$src)>; +def : Pat<(cttz_zero_undef (loadi32 addr:$src)), (BSF32rm addr:$src)>; +def : Pat<(cttz_zero_undef (loadi64 addr:$src)), (BSF64rm addr:$src)>; +def : Pat<(ctlz_zero_undef GR16:$src), (XOR16ri (BSR16rr GR16:$src), 15)>; +def : Pat<(ctlz_zero_undef GR32:$src), (XOR32ri (BSR32rr GR32:$src), 31)>; +def : Pat<(ctlz_zero_undef GR64:$src), (XOR64ri8 (BSR64rr GR64:$src), 63)>; +def : Pat<(ctlz_zero_undef (loadi16 addr:$src)), + (XOR16ri (BSR16rm addr:$src), 15)>; +def : Pat<(ctlz_zero_undef (loadi32 addr:$src)), + (XOR32ri (BSR32rm addr:$src), 31)>; +def : Pat<(ctlz_zero_undef (loadi64 addr:$src)), + (XOR64ri8 (BSR64rm addr:$src), 63)>; Modified: llvm/trunk/test/CodeGen/X86/clz.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/clz.ll?rev=146974&r1=146973&r2=146974&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/X86/clz.ll (original) +++ llvm/trunk/test/CodeGen/X86/clz.ll Tue Dec 20 05:19:37 2011 @@ -1,48 +1,65 @@ ; RUN: llc < %s -march=x86 -mcpu=yonah | FileCheck %s define i32 @t1(i32 %x) nounwind { - %tmp = tail call i32 @llvm.ctlz.i32( i32 %x, i1 true ) - ret i32 %tmp + %tmp = tail call i32 @llvm.ctlz.i32( i32 %x, i1 true ) + ret i32 %tmp ; CHECK: t1: ; CHECK: bsrl -; CHECK: cmov +; CHECK-NOT: cmov +; CHECK: xorl $31, +; CHECK: ret } declare i32 @llvm.ctlz.i32(i32, i1) nounwind readnone define i32 @t2(i32 %x) nounwind { - %tmp = tail call i32 @llvm.cttz.i32( i32 %x, i1 true ) - ret i32 %tmp + %tmp = tail call i32 @llvm.cttz.i32( i32 %x, i1 true ) + ret i32 %tmp ; CHECK: t2: ; CHECK: bsfl -; CHECK: cmov +; CHECK-NOT: cmov +; CHECK: ret } declare i32 @llvm.cttz.i32(i32, i1) nounwind readnone define i16 @t3(i16 %x, i16 %y) nounwind { entry: - %tmp1 = add i16 %x, %y - %tmp2 = tail call i16 @llvm.ctlz.i16( i16 %tmp1, i1 true ) ; [#uses=1] - ret i16 %tmp2 + %tmp1 = add i16 %x, %y + %tmp2 = tail call i16 @llvm.ctlz.i16( i16 %tmp1, i1 true ) ; [#uses=1] + ret i16 %tmp2 ; CHECK: t3: ; CHECK: bsrw -; CHECK: cmov +; CHECK-NOT: cmov +; CHECK: xorw $15, +; CHECK: ret } declare i16 @llvm.ctlz.i16(i16, i1) nounwind readnone -; Don't generate the cmovne when the source is known non-zero (and bsr would -; not set ZF). -; rdar://9490949 - define i32 @t4(i32 %n) nounwind { entry: +; Generate a cmov to handle zero inputs when necessary. ; CHECK: t4: ; CHECK: bsrl +; CHECK: cmov +; CHECK: xorl $31, +; CHECK: ret + %tmp1 = tail call i32 @llvm.ctlz.i32(i32 %n, i1 false) + ret i32 %tmp1 +} + +define i32 @t5(i32 %n) nounwind { +entry: +; Don't generate the cmovne when the source is known non-zero (and bsr would +; not set ZF). +; rdar://9490949 +; CHECK: t5: +; CHECK: bsrl ; CHECK-NOT: cmov +; CHECK: xorl $31, ; CHECK: ret %or = or i32 %n, 1 - %tmp1 = tail call i32 @llvm.ctlz.i32(i32 %or, i1 true) + %tmp1 = tail call i32 @llvm.ctlz.i32(i32 %or, i1 false) ret i32 %tmp1 } From chandlerc at gmail.com Tue Dec 20 05:25:32 2011 From: chandlerc at gmail.com (Chandler Carruth) Date: Tue, 20 Dec 2011 03:25:32 -0800 Subject: [llvm-commits] PATCH: Enable direct selection of bsf and bsr instructions for cttz and ctlz with zero-undef behavior In-Reply-To: <68E0DAB7-2B39-4B4C-816A-4408DCFBAF42@apple.com> References:

<6C5EBBA2-AC05-4F55-871D-D7657848266B@apple.com> <68E0DAB7-2B39-4B4C-816A-4408DCFBAF42@apple.com> Message-ID: On Mon, Dec 19, 2011 at 12:07 PM, Evan Cheng wrote: > > On Dec 17, 2011, at 2:29 AM, Chandler Carruth wrote: > > On Thu, Dec 15, 2011 at 7:52 AM, Stephen Canon wrote: > >> Just for the record, this is in no way unique to AMD. Agner Fog's tables >> list BSF/BSR as 10 ?ops/16 cycles on Atom as well. BSF is a hazard to be >> avoided on an unknown x86 processor. >> > > I really wasn't trying to draw generalizations. I've read the same tables. > =/ I'm not sure what your concerned about here, this patch is orthogonal to > any work on avoiding these instructions on architectures where they just > decode to silly microcode. > > I'd still really appreciate some review on the actual patch. It's pretty > simple. > > > The patch looks fine to me. > Thanks! Testing a boot-strap uncovered a pretty silly miscompile; I'd not correctly modeled the essentially insane semantics of bsr. The fix was spotted by Benjamin Kramer and he checked my (obvious) fix. I've committed the fixed patch, with improved tests in r146974. I'll watch the bots just in case. -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20111220/184bd2d6/attachment.html From elena.demikhovsky at intel.com Tue Dec 20 07:34:29 2011 From: elena.demikhovsky at intel.com (Elena Demikhovsky) Date: Tue, 20 Dec 2011 13:34:29 -0000 Subject: [llvm-commits] [llvm] r146975 - in /llvm/trunk: lib/Target/X86/X86InstrSSE.td test/CodeGen/X86/2011-12-08-AVXISelBugs.ll Message-ID: <20111220133429.48F822A6C12C@llvm.org> Author: delena Date: Tue Dec 20 07:34:28 2011 New Revision: 146975 URL: http://llvm.org/viewvc/llvm-project?rev=146975&view=rev Log: This is the second fix related to VZEXT_MOVL node. The failure that I see in the current version is: LLVM ERROR: Cannot select: 0x18b8f70: v4i64 = X86ISD::VZEXT_MOVL 0x18beee0 [ID=14] 0x18beee0: v4i64 = insert_subvector 0x18b8c70, 0x18b9170, 0x18b9570 [ID=13] 0x18b8c70: v4i64 = insert_subvector 0x18b9870, 0x18bf4e0, 0x18b9970 [ID=12] 0x18b9870: v4i64 = undef [ID=4] 0x18bf4e0: v2i64 = bitcast 0x18bf3e0 [ID=10] 0x18bf3e0: v4i32 = BUILD_VECTOR 0x18b9770, 0x18b9770, 0x18b9770, 0x18b9770 [ID=8] 0x18b9770: i32 = TargetConstant<0> [ID=6] 0x18b9770: i32 = TargetConstant<0> [ID=6] 0x18b9770: i32 = TargetConstant<0> [ID=6] 0x18b9770: i32 = TargetConstant<0> [ID=6] 0x18b9970: i32 = Constant<0> [ID=3] 0x18b9170: v2i64 = undef [ORD=1] [ID=1] 0x18b9570: i32 = Constant<2> [ID=5] Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td llvm/trunk/test/CodeGen/X86/2011-12-08-AVXISelBugs.ll Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrSSE.td?rev=146975&r1=146974&r2=146975&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86InstrSSE.td (original) +++ llvm/trunk/lib/Target/X86/X86InstrSSE.td Tue Dec 20 07:34:28 2011 @@ -628,7 +628,12 @@ (VMOVSDrr (v2f64 (V_SET0)), (EXTRACT_SUBREG (v4f64 VR256:$src), sub_sd)), sub_xmm)>; - // Extract and store. + def : Pat<(v4i64 (X86vzmovl (v4i64 VR256:$src))), + (SUBREG_TO_REG (i32 0), + (VMOVSDrr (v2i64 (V_SET0)), + (EXTRACT_SUBREG (v4i64 VR256:$src), sub_sd)), sub_xmm)>; + +// Extract and store. def : Pat<(store (f32 (vector_extract (v4f32 VR128:$src), (iPTR 0))), addr:$dst), (VMOVSSmr addr:$dst, Modified: llvm/trunk/test/CodeGen/X86/2011-12-08-AVXISelBugs.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2011-12-08-AVXISelBugs.ll?rev=146975&r1=146974&r2=146975&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/X86/2011-12-08-AVXISelBugs.ll (original) +++ llvm/trunk/test/CodeGen/X86/2011-12-08-AVXISelBugs.ll Tue Dec 20 07:34:28 2011 @@ -69,3 +69,12 @@ %2 = insertelement <3 x i64> , i64 %1, i32 0 ret <3 x i64> %2 } + +define void @t5() nounwind { +entry: + %0 = shufflevector <2 x i64> zeroinitializer, <2 x i64> undef, <8 x i32> + %1 = shufflevector <8 x i64> , <8 x i64> %0, <8 x i32> + store <8 x i64> %1, <8 x i64> addrspace(1)* undef, align 64 + + ret void +} From kristof.beyls at arm.com Tue Dec 20 07:43:39 2011 From: kristof.beyls at arm.com (Kristof Beyls) Date: Tue, 20 Dec 2011 13:43:39 -0000 Subject: [llvm-commits] [PATCH] MC ARM Thumb: fix incorrect relocation generation (PR11214) Message-ID: <000001ccbf1d$618f7490$24ae5db0$@beyls@arm.com> Hi, Please find a patch for fixing incorrect generation of relocation information on Thumb function calls. This should fix quite a few incorrect code generation problems in Thumb mode when using the integrated assembler. I believe this fixes PR11214 (http://www.llvm.org/bugs/show_bug.cgi?id=11214). Is this OK? Thanks, Kristof -------------- next part -------------- A non-text attachment was scrubbed... Name: fix_thumbcall_reloc.patch Type: application/octet-stream Size: 1418 bytes Desc: not available Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20111220/b6f2c5f9/attachment-0001.obj From klimek at google.com Tue Dec 20 08:54:16 2011 From: klimek at google.com (Manuel Klimek) Date: Tue, 20 Dec 2011 15:54:16 +0100 Subject: [llvm-commits] PATCH: remove unused variable TheError Message-ID: While searching for an example to model my use of SourceMgr after, I stumbled over LLLexer.h and found what looks like an unused variable - this patch would remove it, if there's not some hidden use of TheError that I'm missing. diff --git a/lib/AsmParser/LLLexer.h b/lib/AsmParser/LLLexer.h index 33b9135..09aea5b 100644 --- a/lib/AsmParser/LLLexer.h +++ b/lib/AsmParser/LLLexer.h @@ -42,7 +42,6 @@ namespace llvm { APFloat APFloatVal; APSInt APSIntVal; - std::string TheError; public: explicit LLLexer(MemoryBuffer *StartBuf, SourceMgr &SM, SMDiagnostic &, LLVMContext &C); From axwalk at gmail.com Tue Dec 20 08:56:09 2011 From: axwalk at gmail.com (Andrew Wilkins) Date: Tue, 20 Dec 2011 22:56:09 +0800 Subject: [llvm-commits] [PATCH] Extend named metadata support in the LLVM C API In-Reply-To: References:

Message-ID: On Tue, Dec 20, 2011 at 2:06 AM, Devang Patel wrote: > > We want to preserve backward compatibility in C API as much as possible. > So we don't want to remove LLVMGetNamedMetadataOperands or change signature > of LLVMGetNamedMetadataNumOperands. > Thanks for the feedback. Fair enough. Attached is a more conservative patch, just adding one new function LLVMAddNamedMetadataOperand. Regards, -- Andrew Wilkins http://awilkins.id.au -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20111220/70673ea3/attachment.html -------------- next part -------------- A non-text attachment was scrubbed... Name: llvm-capi-namedmd-take2.diff Type: application/octet-stream Size: 1356 bytes Desc: not available Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20111220/70673ea3/attachment.obj From hfinkel at anl.gov Tue Dec 20 11:22:20 2011 From: hfinkel at anl.gov (Hal Finkel) Date: Tue, 20 Dec 2011 11:22:20 -0600 Subject: [llvm-commits] [PATCH] Allow SelectionDAGBuilder to reorder loads past stores In-Reply-To: <2264DB7F-F14F-4D93-B6C1-79D69B5F2DBF@apple.com> References: <1324316529.31367.96.camel@sapling> <945273C4-D0AA-4CAF-B0ED-C6D96A52FE02@apple.com> <1324325951.31367.178.camel@sapling> <1324355462.31367.287.camel@sapling> <2264DB7F-F14F-4D93-B6C1-79D69B5F2DBF@apple.com> Message-ID: <1324401740.31367.437.camel@sapling> On Mon, 2011-12-19 at 22:46 -0800, Evan Cheng wrote: > On Dec 19, 2011, at 8:31 PM, Hal Finkel wrote: > > > On Mon, 2011-12-19 at 15:02 -0800, Evan Cheng wrote: > >> On Dec 19, 2011, at 12:19 PM, Hal Finkel wrote: > >> > >>> On Mon, 2011-12-19 at 10:52 -0800, Evan Cheng wrote: > >>>> Hi Hal, > >>>> > >>>> IMHO, this is the wrong way to fix this problem. The fundamental issue here is SelectionDAG is being used by the pre-RA scheduler so the conservative DAG building can have a significant impact on the schedule and the performance of generated code. Changing SelectionDAGBuilder to relax this is one way to go about this. But as you can tell, the current scheduler is not quite ready for this and you can see some large performance regressions. > >>>> > >>> > >>> Fair enough, however, I fear that whether they get the load/store > >>> independence information from the DAG or from their own aliasing > >>> analysis, the results will be equally good (or bad) as with the current > >>> patch. Either way, it is the scheduling heuristics that will need > >>> improving. > >> > >> Right. One of the argument for doing scheduling on MachineInstr's and later in the codegen pipeline is so it can make better decisions. For example, currently the pre-RA scheduler does a decent job of estimating register pressure. However, instructions are moved (LICM, sink), deleted (coalescing, CSE) so by definition the scheduler is working with half accurate information. > >> > >>> > >>> As far as I can tell, most applications exhibit a performance gain from > >>> this patch. So *if* the regressions are caused by deficiencies in > >>> scheduling heuristics (as opposed to problems with DAGCombine or > >>> Legalize), it might be worthwhile eating the performance regressions for > >>> now, and using them as use cases to improve the scheduling heuristics > >>> (once any incorrect code generation is fixed). In the mean time, most > >>> users should be happier ;) > >> > >> Unfortunately, we can't allow changes that cause massive regressions. For example, 88% regressions to LAME encoding. Even if that means a lot of other benchmarks are benefiting from the change. These regressions have to be studied, understood, and fixed before the change can be enabled. > >> > >>> > >>>> We have long understood the current scheduling strategy is wrong. The plan for 2012 is to add a MachineInstr pre-RA scheduler and leave SelectionDAG for legalizer and dag combine. The new scheduler will probably use aliasing information to reorder loads / stores. > >>>> > >>> > >>> The key point here is making sure that the scheduler has enough > >>> information to make full use of the aliasing analysis. This is not > >>> currently the case. The easiest way of doing this would be to make sure > >>> that the scheduler has access to the original IR instructions. > >>> Alternatively, the aliasing analysis could be enhanced to deal with ptr > >>> +offset pairs, etc. > >>> > >>>> The problem with changing SelectionDAGBuilder is this can negatively impact optimizations done during dag combine and legalization. So as it is the patch should not be enabled by default. At best, it can be committed but turned off. Do you have a good understanding what caused the severe regressions you have identified? > >>> > >>> I have not yet looked into all of the regressions in detail. From what I > >>> have seen, the ILP scheduler, once it is revealed that the loads/stores > >>> are independent, tends to schedule many loads together in a big block, > >>> then a block of computation, then a block of stores. This is (highly) > >>> suboptimal compared to the original sequence in some cases. > >> > >> Right and this should be fixed. > > > > I'll investigate this further, but here is a simple example of what can > > happen. Consider the following loop: > > > > __attribute__((aligned(16))) float a[LEN],b[LEN],c[LEN]; > > > > for (int i = 0; i < LEN; i++) { > > a[i] = sin(b[i]) + cos(c[i]); > > } > > > > where the loop is partially unrolled. Without the patch, this compiles > > to: > > movss c-36(,%rbx,4), %xmm0 > > cvtss2sd %xmm0, %xmm0 > > callq cos > > movsd %xmm0, 16(%rsp) # 8-byte Spill > > movss b-36(,%rbx,4), %xmm0 > > cvtss2sd %xmm0, %xmm0 > > callq sin > > addsd 16(%rsp), %xmm0 # 8-byte Folded Reload > > cvtsd2ss %xmm0, %xmm0 > > movss %xmm0, a-36(,%rbx,4) > > ... > > > > With the patch, the scheduler is allowed to schedule the loads for the > > next iteration before the store from the pervious iteration, and it > > does. Unfortunately, it does it like this: > > movss c-36(,%rbx,4), %xmm0 > > cvtss2sd %xmm0, %xmm0 > > callq cos > > movsd %xmm0, 64(%rsp) # 8-byte Spill > > movss b-36(,%rbx,4), %xmm0 > > cvtss2sd %xmm0, %xmm0 > > callq sin > > addsd 64(%rsp), %xmm0 # 8-byte Folded Reload > > cvtsd2ss %xmm0, %xmm0 > > movss %xmm0, 56(%rsp) # 4-byte Spill > > movss c-32(,%rbx,4), %xmm0 > > cvtss2sd %xmm0, %xmm0 > > callq cos > > movsd %xmm0, 64(%rsp) # 8-byte Spill > > movss 56(%rsp), %xmm0 # 4-byte Reload > > movss %xmm0, a-36(,%rbx,4) > > ... > > > > So, in short, it introduces an unnecessary stack spill in order to delay > > the store. Any ideas on why it would do this? > > Not sure. Are nodes being scheduled across call nodes? Please add -debug-only=pre-RA-sched and compare the schedules. I've looked at the debugging output, I am not sure what I am looking for, however. In the good version, because the result is stored immediately, there is no issue with how registers are allocated, etc. across calls. The "bad" version would work fine without the stack spill. There are plenty of unused callee-saved registers that could be used to hold that result instead of spilling it to the stack. The question is just why none of them are being used in favor of the stack spill. Looking at the schedule reveals: SU(31): 0x56a8db0: f64 = ADDSDrr 0x56e3740, 0x56e2a30 [ORD=21] [ID=31] SU(30): 0x56a8bb0: f32 = CVTSD2SSrr 0x56a8db0 [ORD=22] [ID=30] ... (other stuff including a call) ... SU(29): 0x56ada80: ch = MOVSSmr 0x56a97b0, 0x56a95b0, 0x56ad180, 0x56b30f0, 0x56df500, 0x56a8bb0, 0x564dec0 [ORD=28] [ID=29] but that does not explain to me why the spill is there. When SelectionDAGBuilder sees the instruction stream, those calls to cos() and sin() are not really calls, but are intrinsics that get mapped to ISD::FCOS and ISD::FSIN, and so they don't trigger any flushing of the pending-memory-operations queue. When in comes to register allocations, we get something like this: 592B %vreg15 = ADDSDrr %vreg15, %vreg11; FR64:% vreg15,%vreg11 608B %vreg16 = CVTSD2SSrr %vreg15; FR32:%vreg16 FR64:%vreg15 624B ADJCALLSTACKDOWN64 0, %RSP, % EFLAGS, %RSP 640B %vreg17 = MOVSSrm %noreg, 4, %vreg2, , % noreg; mem:LD4[%scevgep25] FR32:%vreg17 GR64_NOSP:%vreg2 656B %vreg18 = CVTSS2SDrr %vreg17; FR64:%vreg18 FR32:%vreg17 672B %XMM0 = COPY %vreg18; FR64:%vreg18 688B CALL64pcrel32 , %XMM0, %RAX, %RDX, %RSI, %RDI, % XMM0, %EFLAGS, %RSP, ... 704B ADJCALLSTACKUP64 0, 0, %RSP, % EFLAGS, %RSP 720B %vreg19 = COPY %XMM0; FR64:%vreg19 736B ADJCALLSTACKDOWN64 0, %RSP, % EFLAGS, %RSP 752B MOVSSmr %noreg, 4, %vreg2, , %noreg, % vreg16; mem:ST4[%scevgep106](align=8)(tbaa=!"float") GR64_NOSP:% vreg2 FR32:%vreg16 then during allocation I see a message: selectOrSplit FR32:%vreg16,3.202614e-01 = [608r,752r:0) 0 at 608r RS_Assign Cascade 0 wait for second round queuing new interval: %vreg16,3.202614e-01 = [608r,752r:0) 0 at 608r and then: selectOrSplit FR32:%vreg16,3.202614e-01 = [608r,752r:0) 0 at 608r RS_Split Cascade 0 Analyze counted 2 instrs in 1 blocks, through 0 blocks. Inline spilling FR32:%vreg16,3.202614e-01 = [608r,752r:0) 0 at 608r >From original %vreg16,3.202614e-01 = [608r,752r:0) 0 at 608r Merged spilled regs: SS#19 = [608r,752r:0) 0 at invalid spillAroundUses %vreg16 rewrite: 608r %vreg128 = CVTSD2SSrr %vreg15; FR32:% vreg128 FR64:%vreg15 spilled: 616r MOVSSmr , 1, %noreg, 0, %noreg, % vreg128; mem:ST4[FixedStack19] FR32:%vreg128 interval: %vreg128,inf = [608r,616r:0) 0 at 608r reload: 744r %vreg129 = MOVSSrm , 1, %noreg, 0, % noreg; mem:LD4[FixedStack19] FR32:%vreg129 rewrite: 752r MOVSSmr %noreg, 4, %vreg104, , % noreg, %vreg129; mem:ST4[%scevgep106](align=8)(tbaa=!"float") GR64_NOSP:%vreg104 FR32:%vreg129 interval: %vreg129,inf = [744r,752r:0) 0 at 744r queuing new interval: %vreg128,inf = [608r,616r:0) 0 at 608r queuing new interval: %vreg129,inf = [744r,752r:0) 0 at 744r when I later look at the register map, only XMM0 and XMM1 are ever assigned to vregs, everything else is spilled. This is wrong. Do you have any ideas on what could be going wrong or other things I should examine? Could the register allocator not be accounting correctly for callee-saved registers when computing live-interval interference information? Thanks again, Hal > > Evan > > > > >> > >>> > >>> I would be fine with submitting the patch such that it is turned off by > >>> default. Especially while there are test-suite failures, I think that it > >>> would need to be this way. > >> > >> That's a reasonable compromise. Someone will have review the patch carefully first though. > >> > >> BTW, what's the compile time impact? > > > > I looked at this quickly with my debug build, and it seemed to have a > > negligible effect (I've put the default cap on the reorder buffer at 8, > > so any effect is bound to be small, it seemed just as small when I set > > the buffer size to 64). I'll do a test suite run with an optimized build > > to get some real timing numbers. > > > > Thanks again, > > Hal > > > >> > >> Evan > >> > >>> > >>> Thanks again, > >>> Hal > >>> > >>>> > >>>> Evan > >>>> > >>>> On Dec 19, 2011, at 9:42 AM, Hal Finkel wrote: > >>>> > >>>>> The current SelectionDAGBuilder does not allow loads to be reordered > >>>>> past stores, and does not allow stores to be reordered. This is a side > >>>>> effect of the way the critical chain is constructed: there is a queue of > >>>>> pending loads that is flushed (in parallel) to the root of the chain > >>>>> upon encountering any store (and that store is also appended to the root > >>>>> of the chain). Among other things, loop unrolling is far less effective > >>>>> than it otherwise could be. > >>>>> > >>>>> The attached patch allows SelectionDAGBuilder to use the available alias > >>>>> analysis to reorder independent loads and stores. It changes the queue > >>>>> of pending loads into a more general queue of pending memory operations, > >>>>> and flushes, in parallel, all potentially-conflicting loads and stores > >>>>> as necessary. > >>>>> > >>>>> This can result in a significant performance boost. On my x86_64 > >>>>> machine, the average percentage decrease in execution time is ~8% (to > >>>>> calculate my performance numbers from the test suite, I've included only > >>>>> the 174 tests with a base execution time of at least 0.1s; the times of > >>>>> the shorter tests seem noisy on my machine). Of these, 131 showed a > >>>>> performance increase and 36 showed a performance decrease. > >>>>> > >>>>> The top-5 winners were: > >>>>> MultiSource/Benchmarks/MiBench/consumer-typeset/consumer-typeset - 92% > >>>>> performance increase ( = runtime decrease) > >>>>> MultiSource/Benchmarks/llubenchmark/llu - 47% performance increase > >>>>> MultiSource/Applications/minisat/minisat - 47% performance increase > >>>>> MultiSource/Benchmarks/sim/sim - 40% performance increase > >>>>> MultiSource/Benchmarks/Prolangs-C++/life/life - 35.7% performance > >>>>> increase > >>>>> The top-5 losers were: > >>>>> MultiSource/Benchmarks/MiBench/consumer-lame/consumer-lame - 88% > >>>>> performance decrease > >>>>> MultiSource/Benchmarks/VersaBench/beamformer/beamformer - 49% > >>>>> performance decrease > >>>>> MultiSource/Benchmarks/MallocBench/espresso/espresso 47% performance > >>>>> decrease > >>>>> MultiSource/Benchmarks/MiBench/automotive-bitcount/automotive-bitcount - > >>>>> 21% performance decrease > >>>>> MultiSource/Benchmarks/MiBench/network-patricia/network-patricia - 20% > >>>>> performance decrease > >>>>> > >>>>> The patch adds a few new options: > >>>>> max-parallel-chains - replaces the old MaxParallelChains constant) > >>>>> max-load-store-reorder - the maximum size of the reorder buffer - > >>>>> previously it was unlimited, but contained only stores > >>>>> no-reordering-past-stores - invokes the previous behavior > >>>>> > >>>>> Some of the regression tests had to be updated because the order of some > >>>>> stores changed. For most of these, I just updated the test to reflect > >>>>> the new instruction sequence. The following tests I've marked as XFAIL > >>>>> because they would require larger changes (and I'd like someone with > >>>>> more experience than me to make sure that they really are okay and make > >>>>> any necessary adjustments): > >>>>> CodeGen/X86/2008-02-22-LocalRegAllocBug.ll > >>>>> CodeGen/X86/2010-09-17-SideEffectsInChain.ll > >>>>> CodeGen/X86/lea-recursion.ll > >>>>> > >>>>> Also, there is one test-suite runtime failure on x86_64: > >>>>> MultiSource/Benchmarks/Ptrdist/ft/ft > >>>>> > >>>>> And several test-suite runtime failures on i686: > >>>>> MultiSource/Benchmarks/tramp3d-v4/tramp3d-v4 > >>>>> SingleSource/Benchmarks/Misc-C++/Large/ray > >>>>> SingleSource/Benchmarks/Misc-C++/stepanov_container > >>>>> SingleSource/Benchmarks/Shootout-C++/lists > >>>>> SingleSource/Benchmarks/Shootout-C++/lists1 > >>>>> SingleSource/Benchmarks/Shootout-C++/sieve > >>>>> > >>>>> Please review (and help with the test-suite failures). > >>>>> > >>>>> Thank you in advance, > >>>>> Hal > >>>>> > >>>>> -- > >>>>> Hal Finkel > >>>>> Postdoctoral Appointee > >>>>> Leadership Computing Facility > >>>>> Argonne National Laboratory > >>>>> > >>>>> _______________________________________________ > >>>>> llvm-commits mailing list > >>>>> llvm-commits at cs.uiuc.edu > >>>>> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits > >>>> > >>> > >>> -- > >>> Hal Finkel > >>> Postdoctoral Appointee > >>> Leadership Computing Facility > >>> Argonne National Laboratory > >>> > >> > > > > -- > > Hal Finkel > > Postdoctoral Appointee > > Leadership Computing Facility > > Argonne National Laboratory > > > -- Hal Finkel Postdoctoral Appointee Leadership Computing Facility Argonne National Laboratory From jason.w.kim.2009 at gmail.com Tue Dec 20 11:38:12 2011 From: jason.w.kim.2009 at gmail.com (Jason W Kim) Date: Tue, 20 Dec 2011 17:38:12 -0000 Subject: [llvm-commits] [llvm] r146977 - /llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Message-ID: <20111220173813.0BD732A6C12C@llvm.org> Author: jasonwkim Date: Tue Dec 20 11:38:12 2011 New Revision: 146977 URL: http://llvm.org/viewvc/llvm-project?rev=146977&view=rev Log: First steps in ARM AsmParser support for .eabi_attribute and .arch (Both used for Linux gnueabi) No behavioral change yet (no tests need so far) Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp?rev=146977&r1=146976&r2=146977&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp (original) +++ llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Tue Dec 20 11:38:12 2011 @@ -101,6 +101,8 @@ bool parseDirectiveSyntax(SMLoc L); bool parseDirectiveReq(StringRef Name, SMLoc L); bool parseDirectiveUnreq(SMLoc L); + bool parseDirectiveArch(SMLoc L); + bool parseDirectiveEabiAttr(SMLoc L); StringRef splitMnemonic(StringRef Mnemonic, unsigned &PredicationCode, bool &CarrySetting, unsigned &ProcessorIMod, @@ -6121,6 +6123,10 @@ return parseDirectiveSyntax(DirectiveID.getLoc()); else if (IDVal == ".unreq") return parseDirectiveUnreq(DirectiveID.getLoc()); + else if (IDVal == ".arch") + return parseDirectiveArch(DirectiveID.getLoc()); + else if (IDVal == ".eabi_attribute") + return parseDirectiveEabiAttr(DirectiveID.getLoc()); return true; } @@ -6300,6 +6306,18 @@ return false; } +/// parseDirectiveArch +/// ::= .arch token +bool ARMAsmParser::parseDirectiveArch(SMLoc L) { + return true; +} + +/// parseDirectiveEabiAttr +/// ::= .eabi_attribute int, int +bool ARMAsmParser::parseDirectiveEabiAttr(SMLoc L) { + return true; +} + extern "C" void LLVMInitializeARMAsmLexer(); /// Force static initialization. From evan.cheng at apple.com Tue Dec 20 11:57:34 2011 From: evan.cheng at apple.com (Evan Cheng) Date: Tue, 20 Dec 2011 09:57:34 -0800 Subject: [llvm-commits] [llvm] r146801 - in /llvm/trunk: include/llvm/MC/MCStreamer.h lib/CodeGen/AsmPrinter/AsmPrinterDwarf.cpp lib/MC/MCAsmStreamer.cpp lib/MC/MCLoggingStreamer.cpp lib/MC/MCNullStreamer.cpp lib/MC/MCParser/COFFAsmParser.cpp lib/MC/MCStr In-Reply-To: References: Message-ID: <365ECA24-CB73-409A-AFB5-7091BB88827C@apple.com> Hi Rafael, Chandler is absolutely right. Please revert the patch. Thanks, Evan On Dec 20, 2011, at 2:03 AM, Chandler Carruth wrote: > On Fri, Dec 16, 2011 at 5:14 PM, Rafael Espindola wrote: > Modified: llvm/trunk/lib/MC/WinCOFFStreamer.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/WinCOFFStreamer.cpp?rev=146801&r1=146800&r2=146801&view=diff > ============================================================================== > --- llvm/trunk/lib/MC/WinCOFFStreamer.cpp (original) > +++ llvm/trunk/lib/MC/WinCOFFStreamer.cpp Fri Dec 16 19:14:52 2011 > @@ -32,6 +32,9 @@ > #include "llvm/Support/ErrorHandling.h" > #include "llvm/Support/TargetRegistry.h" > #include "llvm/Support/raw_ostream.h" > + > +#include "../Target/X86/MCTargetDesc/X86FixupKinds.h" > + > > This is a pretty egregious layering violation. Please fix or revert, this causes all kinds of problems with improper dependencies between various components. > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20111220/cae33586/attachment.html From evan.cheng at apple.com Tue Dec 20 12:26:51 2011 From: evan.cheng at apple.com (Evan Cheng) Date: Tue, 20 Dec 2011 18:26:51 -0000 Subject: [llvm-commits] [llvm] r146981 - in /llvm/trunk: lib/Target/ARM/ test/CodeGen/ARM/ test/CodeGen/Thumb2/ Message-ID: <20111220182651.DE0ED2A6C12C@llvm.org> Author: evancheng Date: Tue Dec 20 12:26:50 2011 New Revision: 146981 URL: http://llvm.org/viewvc/llvm-project?rev=146981&view=rev Log: ARM target code clean up. Check for iOS, not Darwin where it makes sense. Modified: llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp llvm/trunk/lib/Target/ARM/ARMFastISel.cpp llvm/trunk/lib/Target/ARM/ARMInstrInfo.td llvm/trunk/lib/Target/ARM/ARMInstrThumb.td llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp llvm/trunk/lib/Target/ARM/ARMSubtarget.h llvm/trunk/test/CodeGen/ARM/2010-11-29-PrologueBug.ll llvm/trunk/test/CodeGen/ARM/2011-06-16-TailCallByVal.ll llvm/trunk/test/CodeGen/ARM/call-tc.ll llvm/trunk/test/CodeGen/ARM/debug-info-blocks.ll llvm/trunk/test/CodeGen/ARM/fast-isel-br-const.ll llvm/trunk/test/CodeGen/ARM/fast-isel-call.ll llvm/trunk/test/CodeGen/ARM/fast-isel-cmp-imm.ll llvm/trunk/test/CodeGen/ARM/fast-isel-conversion.ll llvm/trunk/test/CodeGen/ARM/fast-isel-deadcode.ll llvm/trunk/test/CodeGen/ARM/fast-isel-icmp.ll llvm/trunk/test/CodeGen/ARM/fast-isel-intrinsic.ll llvm/trunk/test/CodeGen/ARM/fast-isel-ldr-str-thumb-neg-index.ll llvm/trunk/test/CodeGen/ARM/fast-isel-ldrh-strh-arm.ll llvm/trunk/test/CodeGen/ARM/fast-isel-mvn.ll llvm/trunk/test/CodeGen/ARM/fast-isel-ret.ll llvm/trunk/test/CodeGen/ARM/fast-isel-select.ll llvm/trunk/test/CodeGen/ARM/fast-isel.ll llvm/trunk/test/CodeGen/Thumb2/2009-07-21-ISelBug.ll Modified: llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp?rev=146981&r1=146980&r2=146981&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp Tue Dec 20 12:26:50 2011 @@ -72,8 +72,8 @@ 0 }; - static const unsigned DarwinCalleeSavedRegs[] = { - // Darwin ABI deviates from ARM standard ABI. R9 is not a callee-saved + static const unsigned iOSCalleeSavedRegs[] = { + // iOS ABI deviates from ARM standard ABI. R9 is not a callee-saved // register. ARM::LR, ARM::R7, ARM::R6, ARM::R5, ARM::R4, ARM::R11, ARM::R10, ARM::R8, @@ -82,7 +82,7 @@ ARM::D11, ARM::D10, ARM::D9, ARM::D8, 0 }; - return STI.isTargetDarwin() ? DarwinCalleeSavedRegs : CalleeSavedRegs; + return (STI.isTargetIOS()) ? iOSCalleeSavedRegs : CalleeSavedRegs; } BitVector ARMBaseRegisterInfo:: Modified: llvm/trunk/lib/Target/ARM/ARMFastISel.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMFastISel.cpp?rev=146981&r1=146980&r2=146981&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMFastISel.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMFastISel.cpp Tue Dec 20 12:26:50 2011 @@ -2012,12 +2012,12 @@ unsigned ARMFastISel::ARMSelectCallOp(const GlobalValue *GV) { - // Darwin needs the r9 versions of the opcodes. - bool isDarwin = Subtarget->isTargetDarwin(); + // iOS needs the r9 versions of the opcodes. + bool isiOS = Subtarget->isTargetIOS(); if (isThumb2) { - return isDarwin ? ARM::tBLr9 : ARM::tBL; + return isiOS ? ARM::tBLr9 : ARM::tBL; } else { - return isDarwin ? ARM::BLr9 : ARM::BL; + return isiOS ? ARM::BLr9 : ARM::BL; } } @@ -2076,7 +2076,7 @@ if (!ProcessCallArgs(Args, ArgRegs, ArgVTs, ArgFlags, RegArgs, CC, NumBytes)) return false; - // Issue the call, BLr9 for darwin, BL otherwise. + // Issue the call, BLr9 for iOS, BL otherwise. // TODO: Turn this into the table of arm call ops. MachineInstrBuilder MIB; unsigned CallOpc = ARMSelectCallOp(NULL); @@ -2197,7 +2197,7 @@ if (!ProcessCallArgs(Args, ArgRegs, ArgVTs, ArgFlags, RegArgs, CC, NumBytes)) return false; - // Issue the call, BLr9 for darwin, BL otherwise. + // Issue the call, BLr9 for iOS, BL otherwise. // TODO: Turn this into the table of arm call ops. MachineInstrBuilder MIB; unsigned CallOpc = ARMSelectCallOp(GV); @@ -2514,12 +2514,12 @@ namespace llvm { llvm::FastISel *ARM::createFastISel(FunctionLoweringInfo &funcInfo) { - // Completely untested on non-darwin. + // Completely untested on non-iOS. const TargetMachine &TM = funcInfo.MF->getTarget(); // Darwin and thumb1 only for now. const ARMSubtarget *Subtarget = &TM.getSubtarget(); - if (Subtarget->isTargetDarwin() && !Subtarget->isThumb1Only() && + if (Subtarget->isTargetIOS() && !Subtarget->isThumb1Only() && !DisableARMFastISel) return new ARMFastISel(funcInfo); return 0; Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.td?rev=146981&r1=146980&r2=146981&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrInfo.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Tue Dec 20 12:26:50 2011 @@ -206,8 +206,8 @@ AssemblerPredicate<"!FeatureMClass">; def IsARM : Predicate<"!Subtarget->isThumb()">, AssemblerPredicate<"!ModeThumb">; -def IsDarwin : Predicate<"Subtarget->isTargetDarwin()">; -def IsNotDarwin : Predicate<"!Subtarget->isTargetDarwin()">; +def IsIOS : Predicate<"Subtarget->isTargetIOS()">; +def IsNotIOS : Predicate<"!Subtarget->isTargetIOS()">; def IsNaCl : Predicate<"Subtarget->isTargetNaCl()">; // FIXME: Eventually this will be just "hasV6T2Ops". @@ -1896,7 +1896,7 @@ // a use to prevent stack-pointer assignments that appear immediately // before calls from potentially appearing dead. let isCall = 1, - // On non-Darwin platforms R9 is callee-saved. + // On non-IOS platforms R9 is callee-saved. // FIXME: Do we really need a non-predicated version? If so, it should // at least be a pseudo instruction expanding to the predicated version // at MC lowering time. @@ -1905,7 +1905,7 @@ def BL : ABXI<0b1011, (outs), (ins bl_target:$func, variable_ops), IIC_Br, "bl\t$func", [(ARMcall tglobaladdr:$func)]>, - Requires<[IsARM, IsNotDarwin]> { + Requires<[IsARM, IsNotIOS]> { let Inst{31-28} = 0b1110; bits<24> func; let Inst{23-0} = func; @@ -1915,7 +1915,7 @@ def BL_pred : ABI<0b1011, (outs), (ins bl_target:$func, variable_ops), IIC_Br, "bl", "\t$func", [(ARMcall_pred tglobaladdr:$func)]>, - Requires<[IsARM, IsNotDarwin]> { + Requires<[IsARM, IsNotIOS]> { bits<24> func; let Inst{23-0} = func; let DecoderMethod = "DecodeBranchImmInstruction"; @@ -1925,7 +1925,7 @@ def BLX : AXI<(outs), (ins GPR:$func, variable_ops), BrMiscFrm, IIC_Br, "blx\t$func", [(ARMcall GPR:$func)]>, - Requires<[IsARM, HasV5T, IsNotDarwin]> { + Requires<[IsARM, HasV5T, IsNotIOS]> { bits<4> func; let Inst{31-4} = 0b1110000100101111111111110011; let Inst{3-0} = func; @@ -1934,7 +1934,7 @@ def BLX_pred : AI<(outs), (ins GPR:$func, variable_ops), BrMiscFrm, IIC_Br, "blx", "\t$func", [(ARMcall_pred GPR:$func)]>, - Requires<[IsARM, HasV5T, IsNotDarwin]> { + Requires<[IsARM, HasV5T, IsNotIOS]> { bits<4> func; let Inst{27-4} = 0b000100101111111111110011; let Inst{3-0} = func; @@ -1944,16 +1944,16 @@ // Note: Restrict $func to the tGPR regclass to prevent it being in LR. def BX_CALL : ARMPseudoInst<(outs), (ins tGPR:$func, variable_ops), 8, IIC_Br, [(ARMcall_nolink tGPR:$func)]>, - Requires<[IsARM, HasV4T, IsNotDarwin]>; + Requires<[IsARM, HasV4T, IsNotIOS]>; // ARMv4 def BMOVPCRX_CALL : ARMPseudoInst<(outs), (ins tGPR:$func, variable_ops), 8, IIC_Br, [(ARMcall_nolink tGPR:$func)]>, - Requires<[IsARM, NoV4T, IsNotDarwin]>; + Requires<[IsARM, NoV4T, IsNotIOS]>; } let isCall = 1, - // On Darwin R9 is call-clobbered. + // On IOS R9 is call-clobbered. // R7 is marked as a use to prevent frame-pointer assignments from being // moved above / below calls. Defs = [R0, R1, R2, R3, R9, R12, LR, QQQQ0, QQQQ2, QQQQ3, CPSR, FPSCR], @@ -1961,38 +1961,38 @@ def BLr9 : ARMPseudoExpand<(outs), (ins bl_target:$func, variable_ops), 4, IIC_Br, [(ARMcall tglobaladdr:$func)], (BL bl_target:$func)>, - Requires<[IsARM, IsDarwin]>; + Requires<[IsARM, IsIOS]>; def BLr9_pred : ARMPseudoExpand<(outs), (ins bl_target:$func, pred:$p, variable_ops), 4, IIC_Br, [(ARMcall_pred tglobaladdr:$func)], (BL_pred bl_target:$func, pred:$p)>, - Requires<[IsARM, IsDarwin]>; + Requires<[IsARM, IsIOS]>; // ARMv5T and above def BLXr9 : ARMPseudoExpand<(outs), (ins GPR:$func, variable_ops), 4, IIC_Br, [(ARMcall GPR:$func)], (BLX GPR:$func)>, - Requires<[IsARM, HasV5T, IsDarwin]>; + Requires<[IsARM, HasV5T, IsIOS]>; def BLXr9_pred: ARMPseudoExpand<(outs), (ins GPR:$func, pred:$p,variable_ops), 4, IIC_Br, [(ARMcall_pred GPR:$func)], (BLX_pred GPR:$func, pred:$p)>, - Requires<[IsARM, HasV5T, IsDarwin]>; + Requires<[IsARM, HasV5T, IsIOS]>; // ARMv4T // Note: Restrict $func to the tGPR regclass to prevent it being in LR. def BXr9_CALL : ARMPseudoInst<(outs), (ins tGPR:$func, variable_ops), 8, IIC_Br, [(ARMcall_nolink tGPR:$func)]>, - Requires<[IsARM, HasV4T, IsDarwin]>; + Requires<[IsARM, HasV4T, IsIOS]>; // ARMv4 def BMOVPCRXr9_CALL : ARMPseudoInst<(outs), (ins tGPR:$func, variable_ops), 8, IIC_Br, [(ARMcall_nolink tGPR:$func)]>, - Requires<[IsARM, NoV4T, IsDarwin]>; + Requires<[IsARM, NoV4T, IsIOS]>; } let isBranch = 1, isTerminator = 1 in { @@ -2060,45 +2060,45 @@ // Tail calls. let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in { - // Darwin versions. + // IOS versions. let Defs = [R0, R1, R2, R3, R9, R12, QQQQ0, QQQQ2, QQQQ3, PC], Uses = [SP] in { def TCRETURNdi : PseudoInst<(outs), (ins i32imm:$dst, variable_ops), - IIC_Br, []>, Requires<[IsDarwin]>; + IIC_Br, []>, Requires<[IsIOS]>; def TCRETURNri : PseudoInst<(outs), (ins tcGPR:$dst, variable_ops), - IIC_Br, []>, Requires<[IsDarwin]>; + IIC_Br, []>, Requires<[IsIOS]>; def TAILJMPd : ARMPseudoExpand<(outs), (ins br_target:$dst, variable_ops), 4, IIC_Br, [], (Bcc br_target:$dst, (ops 14, zero_reg))>, - Requires<[IsARM, IsDarwin]>; + Requires<[IsARM, IsIOS]>; def TAILJMPr : ARMPseudoExpand<(outs), (ins tcGPR:$dst, variable_ops), 4, IIC_Br, [], (BX GPR:$dst)>, - Requires<[IsARM, IsDarwin]>; + Requires<[IsARM, IsIOS]>; } - // Non-Darwin versions (the difference is R9). + // Non-IOS versions (the difference is R9). let Defs = [R0, R1, R2, R3, R12, QQQQ0, QQQQ2, QQQQ3, PC], Uses = [SP] in { def TCRETURNdiND : PseudoInst<(outs), (ins i32imm:$dst, variable_ops), - IIC_Br, []>, Requires<[IsNotDarwin]>; + IIC_Br, []>, Requires<[IsNotIOS]>; def TCRETURNriND : PseudoInst<(outs), (ins tcGPR:$dst, variable_ops), - IIC_Br, []>, Requires<[IsNotDarwin]>; + IIC_Br, []>, Requires<[IsNotIOS]>; def TAILJMPdND : ARMPseudoExpand<(outs), (ins brtarget:$dst, variable_ops), 4, IIC_Br, [], (Bcc br_target:$dst, (ops 14, zero_reg))>, - Requires<[IsARM, IsNotDarwin]>; + Requires<[IsARM, IsNotIOS]>; def TAILJMPrND : ARMPseudoExpand<(outs), (ins tcGPR:$dst, variable_ops), 4, IIC_Br, [], (BX GPR:$dst)>, - Requires<[IsARM, IsNotDarwin]>; + Requires<[IsARM, IsNotIOS]>; } } @@ -4728,13 +4728,13 @@ Requires<[IsARM, NoVFP]>; } -// FIXME: Non-Darwin version(s) +// FIXME: Non-IOS version(s) let isBarrier = 1, hasSideEffects = 1, isTerminator = 1, Defs = [ R7, LR, SP ] in { def Int_eh_sjlj_longjmp : PseudoInst<(outs), (ins GPR:$src, GPR:$scratch), NoItinerary, [(ARMeh_sjlj_longjmp GPR:$src, GPR:$scratch)]>, - Requires<[IsARM, IsDarwin]>; + Requires<[IsARM, IsIOS]>; } // eh.sjlj.dispatchsetup pseudo-instruction. @@ -4804,28 +4804,28 @@ // Tail calls def : ARMPat<(ARMtcret tcGPR:$dst), - (TCRETURNri tcGPR:$dst)>, Requires<[IsDarwin]>; + (TCRETURNri tcGPR:$dst)>, Requires<[IsIOS]>; def : ARMPat<(ARMtcret (i32 tglobaladdr:$dst)), - (TCRETURNdi texternalsym:$dst)>, Requires<[IsDarwin]>; + (TCRETURNdi texternalsym:$dst)>, Requires<[IsIOS]>; def : ARMPat<(ARMtcret (i32 texternalsym:$dst)), - (TCRETURNdi texternalsym:$dst)>, Requires<[IsDarwin]>; + (TCRETURNdi texternalsym:$dst)>, Requires<[IsIOS]>; def : ARMPat<(ARMtcret tcGPR:$dst), - (TCRETURNriND tcGPR:$dst)>, Requires<[IsNotDarwin]>; + (TCRETURNriND tcGPR:$dst)>, Requires<[IsNotIOS]>; def : ARMPat<(ARMtcret (i32 tglobaladdr:$dst)), - (TCRETURNdiND texternalsym:$dst)>, Requires<[IsNotDarwin]>; + (TCRETURNdiND texternalsym:$dst)>, Requires<[IsNotIOS]>; def : ARMPat<(ARMtcret (i32 texternalsym:$dst)), - (TCRETURNdiND texternalsym:$dst)>, Requires<[IsNotDarwin]>; + (TCRETURNdiND texternalsym:$dst)>, Requires<[IsNotIOS]>; // Direct calls def : ARMPat<(ARMcall texternalsym:$func), (BL texternalsym:$func)>, - Requires<[IsARM, IsNotDarwin]>; + Requires<[IsARM, IsNotIOS]>; def : ARMPat<(ARMcall texternalsym:$func), (BLr9 texternalsym:$func)>, - Requires<[IsARM, IsDarwin]>; + Requires<[IsARM, IsIOS]>; // zextload i1 -> zextload i8 def : ARMPat<(zextloadi1 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>; Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb.td?rev=146981&r1=146980&r2=146981&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrThumb.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrThumb.td Tue Dec 20 12:26:50 2011 @@ -404,7 +404,7 @@ // prevent stack-pointer assignments that appear immediately before calls from // potentially appearing dead. let isCall = 1, - // On non-Darwin platforms R9 is callee-saved. + // On non-IOS platforms R9 is callee-saved. Defs = [R0, R1, R2, R3, R12, LR, QQQQ0, QQQQ2, QQQQ3, CPSR, FPSCR], Uses = [SP] in { // Also used for Thumb2 @@ -412,7 +412,7 @@ (outs), (ins pred:$p, t_bltarget:$func, variable_ops), IIC_Br, "bl${p}\t$func", [(ARMtcall tglobaladdr:$func)]>, - Requires<[IsThumb, IsNotDarwin]> { + Requires<[IsThumb, IsNotIOS]> { bits<22> func; let Inst{26} = func{21}; let Inst{25-16} = func{20-11}; @@ -426,7 +426,7 @@ (outs), (ins pred:$p, t_blxtarget:$func, variable_ops), IIC_Br, "blx${p}\t$func", [(ARMcall tglobaladdr:$func)]>, - Requires<[IsThumb, HasV5T, IsNotDarwin]> { + Requires<[IsThumb, HasV5T, IsNotIOS]> { bits<21> func; let Inst{25-16} = func{20-11}; let Inst{13} = 1; @@ -439,7 +439,7 @@ def tBLXr : TI<(outs), (ins pred:$p, GPR:$func, variable_ops), IIC_Br, "blx${p}\t$func", [(ARMtcall GPR:$func)]>, - Requires<[IsThumb, HasV5T, IsNotDarwin]>, + Requires<[IsThumb, HasV5T, IsNotIOS]>, T1Special<{1,1,1,?}> { // A6.2.3 & A8.6.24; bits<4> func; let Inst{6-3} = func; @@ -450,11 +450,11 @@ def tBX_CALL : tPseudoInst<(outs), (ins tGPR:$func, variable_ops), 4, IIC_Br, [(ARMcall_nolink tGPR:$func)]>, - Requires<[IsThumb, IsThumb1Only, IsNotDarwin]>; + Requires<[IsThumb, IsThumb1Only, IsNotIOS]>; } let isCall = 1, - // On Darwin R9 is call-clobbered. + // On IOS R9 is call-clobbered. // R7 is marked as a use to prevent frame-pointer assignments from being // moved above / below calls. Defs = [R0, R1, R2, R3, R9, R12, LR, QQQQ0, QQQQ2, QQQQ3, CPSR, FPSCR], @@ -463,25 +463,25 @@ def tBLr9 : tPseudoExpand<(outs), (ins pred:$p, t_bltarget:$func, variable_ops), 4, IIC_Br, [(ARMtcall tglobaladdr:$func)], (tBL pred:$p, t_bltarget:$func)>, - Requires<[IsThumb, IsDarwin]>; + Requires<[IsThumb, IsIOS]>; // ARMv5T and above, also used for Thumb2 def tBLXi_r9 : tPseudoExpand<(outs), (ins pred:$p, t_blxtarget:$func, variable_ops), 4, IIC_Br, [(ARMcall tglobaladdr:$func)], (tBLXi pred:$p, t_blxtarget:$func)>, - Requires<[IsThumb, HasV5T, IsDarwin]>; + Requires<[IsThumb, HasV5T, IsIOS]>; // Also used for Thumb2 def tBLXr_r9 : tPseudoExpand<(outs), (ins pred:$p, GPR:$func, variable_ops), 2, IIC_Br, [(ARMtcall GPR:$func)], (tBLXr pred:$p, GPR:$func)>, - Requires<[IsThumb, HasV5T, IsDarwin]>; + Requires<[IsThumb, HasV5T, IsIOS]>; // ARMv4T def tBXr9_CALL : tPseudoInst<(outs), (ins tGPR:$func, variable_ops), 4, IIC_Br, [(ARMcall_nolink tGPR:$func)]>, - Requires<[IsThumb, IsThumb1Only, IsDarwin]>; + Requires<[IsThumb, IsThumb1Only, IsIOS]>; } let isBranch = 1, isTerminator = 1, isBarrier = 1 in { @@ -523,28 +523,28 @@ // Tail calls let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in { - // Darwin versions. + // IOS versions. let Defs = [R0, R1, R2, R3, R9, R12, QQQQ0, QQQQ2, QQQQ3, PC], Uses = [SP] in { - // tTAILJMPd: Darwin version uses a Thumb2 branch (no Thumb1 tail calls - // on Darwin), so it's in ARMInstrThumb2.td. + // tTAILJMPd: IOS version uses a Thumb2 branch (no Thumb1 tail calls + // on IOS), so it's in ARMInstrThumb2.td. def tTAILJMPr : tPseudoExpand<(outs), (ins tcGPR:$dst, variable_ops), 4, IIC_Br, [], (tBX GPR:$dst, (ops 14, zero_reg))>, - Requires<[IsThumb, IsDarwin]>; + Requires<[IsThumb, IsIOS]>; } - // Non-Darwin versions (the difference is R9). + // Non-IOS versions (the difference is R9). let Defs = [R0, R1, R2, R3, R12, QQQQ0, QQQQ2, QQQQ3, PC], Uses = [SP] in { def tTAILJMPdND : tPseudoExpand<(outs), (ins t_brtarget:$dst, pred:$p, variable_ops), 4, IIC_Br, [], (tB t_brtarget:$dst, pred:$p)>, - Requires<[IsThumb, IsNotDarwin]>; + Requires<[IsThumb, IsNotIOS]>; def tTAILJMPrND : tPseudoExpand<(outs), (ins tcGPR:$dst, variable_ops), 4, IIC_Br, [], (tBX GPR:$dst, (ops 14, zero_reg))>, - Requires<[IsThumb, IsNotDarwin]>; + Requires<[IsThumb, IsNotIOS]>; } } @@ -652,7 +652,7 @@ } // Load tconstpool -// FIXME: Use ldr.n to work around a Darwin assembler bug. +// FIXME: Use ldr.n to work around a darwin assembler bug. let canFoldAsLoad = 1, isReMaterializable = 1, isCodeGenOnly = 1 in def tLDRpci : T1pIs<(outs tGPR:$Rt), (ins t_addrmode_pc:$addr), IIC_iLoad_i, "ldr", ".n\t$Rt, $addr", @@ -1262,14 +1262,14 @@ AddrModeNone, 0, NoItinerary, "","", [(set R0, (ARMeh_sjlj_setjmp tGPR:$src, tGPR:$val))]>; -// FIXME: Non-Darwin version(s) +// FIXME: Non-IOS version(s) let isBarrier = 1, hasSideEffects = 1, isTerminator = 1, isCodeGenOnly = 1, Defs = [ R7, LR, SP ] in def tInt_eh_sjlj_longjmp : XI<(outs), (ins GPR:$src, GPR:$scratch), AddrModeNone, 0, IndexModeNone, Pseudo, NoItinerary, "", "", [(ARMeh_sjlj_longjmp GPR:$src, GPR:$scratch)]>, - Requires<[IsThumb, IsDarwin]>; + Requires<[IsThumb, IsIOS]>; //===----------------------------------------------------------------------===// // Non-Instruction Patterns @@ -1307,20 +1307,20 @@ // Direct calls def : T1Pat<(ARMtcall texternalsym:$func), (tBL texternalsym:$func)>, - Requires<[IsThumb, IsNotDarwin]>; + Requires<[IsThumb, IsNotIOS]>; def : T1Pat<(ARMtcall texternalsym:$func), (tBLr9 texternalsym:$func)>, - Requires<[IsThumb, IsDarwin]>; + Requires<[IsThumb, IsIOS]>; def : Tv5Pat<(ARMcall texternalsym:$func), (tBLXi texternalsym:$func)>, - Requires<[IsThumb, HasV5T, IsNotDarwin]>; + Requires<[IsThumb, HasV5T, IsNotIOS]>; def : Tv5Pat<(ARMcall texternalsym:$func), (tBLXi_r9 texternalsym:$func)>, - Requires<[IsThumb, HasV5T, IsDarwin]>; + Requires<[IsThumb, HasV5T, IsIOS]>; // Indirect calls to ARM routines def : Tv5Pat<(ARMcall GPR:$dst), (tBLXr GPR:$dst)>, - Requires<[IsThumb, HasV5T, IsNotDarwin]>; + Requires<[IsThumb, HasV5T, IsNotIOS]>; def : Tv5Pat<(ARMcall GPR:$dst), (tBLXr_r9 GPR:$dst)>, - Requires<[IsThumb, HasV5T, IsDarwin]>; + Requires<[IsThumb, HasV5T, IsIOS]>; // zextload i1 -> zextload i8 def : T1Pat<(zextloadi1 t_addrmode_rrs1:$addr), Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td?rev=146981&r1=146980&r2=146981&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td Tue Dec 20 12:26:50 2011 @@ -3212,17 +3212,17 @@ let DecoderMethod = "DecodeThumb2BCCInstruction"; } -// Tail calls. The Darwin version of thumb tail calls uses a t2 branch, so +// Tail calls. The IOS version of thumb tail calls uses a t2 branch, so // it goes here. let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in { - // Darwin version. + // IOS version. let Defs = [R0, R1, R2, R3, R9, R12, QQQQ0, QQQQ2, QQQQ3, PC], Uses = [SP] in def tTAILJMPd: tPseudoExpand<(outs), (ins uncondbrtarget:$dst, pred:$p, variable_ops), 4, IIC_Br, [], (t2B uncondbrtarget:$dst, pred:$p)>, - Requires<[IsThumb2, IsDarwin]>; + Requires<[IsThumb2, IsIOS]>; } // IT block Modified: llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp?rev=146981&r1=146980&r2=146981&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp Tue Dec 20 12:26:50 2011 @@ -108,13 +108,13 @@ if (isAAPCS_ABI()) stackAlignment = 8; - if (!isTargetDarwin()) + if (!isTargetIOS()) UseMovt = hasV6T2Ops(); else { IsR9Reserved = ReserveR9 | !HasV6Ops; UseMovt = DarwinUseMOVT && hasV6T2Ops(); const Triple &T = getTargetTriple(); - SupportsTailCall = T.getOS() == Triple::IOS && !T.isOSVersionLT(5, 0); + SupportsTailCall = !T.isOSVersionLT(5, 0); } if (!isThumb() || hasThumb2()) Modified: llvm/trunk/lib/Target/ARM/ARMSubtarget.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMSubtarget.h?rev=146981&r1=146980&r2=146981&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMSubtarget.h (original) +++ llvm/trunk/lib/Target/ARM/ARMSubtarget.h Tue Dec 20 12:26:50 2011 @@ -218,6 +218,7 @@ const Triple &getTargetTriple() const { return TargetTriple; } + bool isTargetIOS() const { return TargetTriple.getOS() == Triple::IOS; } bool isTargetDarwin() const { return TargetTriple.isOSDarwin(); } bool isTargetNaCl() const { return TargetTriple.getOS() == Triple::NativeClient; Modified: llvm/trunk/test/CodeGen/ARM/2010-11-29-PrologueBug.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/2010-11-29-PrologueBug.ll?rev=146981&r1=146980&r2=146981&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/ARM/2010-11-29-PrologueBug.ll (original) +++ llvm/trunk/test/CodeGen/ARM/2010-11-29-PrologueBug.ll Tue Dec 20 12:26:50 2011 @@ -1,5 +1,5 @@ -; RUN: llc < %s -mtriple=armv7-apple-darwin | FileCheck %s --check-prefix=ARM -; RUN: llc < %s -mtriple=thumbv7-apple-darwin | FileCheck %s --check-prefix=THUMB2 +; RUN: llc < %s -mtriple=armv7-apple-ios | FileCheck %s --check-prefix=ARM +; RUN: llc < %s -mtriple=thumbv7-apple-ios | FileCheck %s --check-prefix=THUMB2 ; rdar://8690640 define i32* @t(i32* %x) nounwind { Modified: llvm/trunk/test/CodeGen/ARM/2011-06-16-TailCallByVal.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/2011-06-16-TailCallByVal.ll?rev=146981&r1=146980&r2=146981&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/ARM/2011-06-16-TailCallByVal.ll (original) +++ llvm/trunk/test/CodeGen/ARM/2011-06-16-TailCallByVal.ll Tue Dec 20 12:26:50 2011 @@ -1,6 +1,6 @@ ; RUN: llc < %s -arm-tail-calls=1 | FileCheck %s target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:32-f32:32:32-f64:32:32-v64:32:64-v128:32:128-a0:0:32-n32" -target triple = "thumbv7-apple-darwin10" +target triple = "thumbv7-apple-ios" %struct.A = type <{ i16, i16, i32, i16, i16, i32, i16, [8 x %struct.B], [418 x i8], %struct.C }> %struct.B = type <{ i32, i16, i16 }> Modified: llvm/trunk/test/CodeGen/ARM/call-tc.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/call-tc.ll?rev=146981&r1=146980&r2=146981&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/ARM/call-tc.ll (original) +++ llvm/trunk/test/CodeGen/ARM/call-tc.ll Tue Dec 20 12:26:50 2011 @@ -1,6 +1,6 @@ -; RUN: llc < %s -mtriple=armv6-apple-darwin -mattr=+vfp2 -arm-tail-calls | FileCheck %s -check-prefix=CHECKV6 +; RUN: llc < %s -mtriple=armv6-apple-ios -mattr=+vfp2 -arm-tail-calls | FileCheck %s -check-prefix=CHECKV6 ; RUN: llc < %s -mtriple=armv6-linux-gnueabi -relocation-model=pic -mattr=+vfp2 -arm-tail-calls | FileCheck %s -check-prefix=CHECKELF -; RUN: llc < %s -mtriple=thumbv7-apple-darwin -arm-tail-calls | FileCheck %s -check-prefix=CHECKT2D +; RUN: llc < %s -mtriple=thumbv7-apple-ios -arm-tail-calls | FileCheck %s -check-prefix=CHECKT2D ; RUN: llc < %s -mtriple=thumbv7-apple-ios5.0 | FileCheck %s -check-prefix=CHECKT2D ; Enable tailcall optimization for iOS 5.0 Modified: llvm/trunk/test/CodeGen/ARM/debug-info-blocks.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/debug-info-blocks.ll?rev=146981&r1=146980&r2=146981&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/ARM/debug-info-blocks.ll (original) +++ llvm/trunk/test/CodeGen/ARM/debug-info-blocks.ll Tue Dec 20 12:26:50 2011 @@ -2,7 +2,7 @@ ; CHECK: @DEBUG_VALUE: mydata <- [sp+#{{[0-9]+}}]+#0 ; Radar 9331779 target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:32-f32:32:32-f64:32:32-v64:32:64-v128:32:128-a0:0:32-n32" -target triple = "thumbv7-apple-macosx10.7.0" +target triple = "thumbv7-apple-ios" %0 = type opaque %1 = type { [4 x i32] } Modified: llvm/trunk/test/CodeGen/ARM/fast-isel-br-const.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/fast-isel-br-const.ll?rev=146981&r1=146980&r2=146981&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/ARM/fast-isel-br-const.ll (original) +++ llvm/trunk/test/CodeGen/ARM/fast-isel-br-const.ll Tue Dec 20 12:26:50 2011 @@ -1,5 +1,5 @@ -; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-apple-darwin | FileCheck %s --check-prefix=ARM -; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-darwin | FileCheck %s --check-prefix=THUMB +; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-apple-ios | FileCheck %s --check-prefix=ARM +; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-ios | FileCheck %s --check-prefix=THUMB define i32 @t1(i32 %a, i32 %b) nounwind uwtable ssp { entry: Modified: llvm/trunk/test/CodeGen/ARM/fast-isel-call.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/fast-isel-call.ll?rev=146981&r1=146980&r2=146981&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/ARM/fast-isel-call.ll (original) +++ llvm/trunk/test/CodeGen/ARM/fast-isel-call.ll Tue Dec 20 12:26:50 2011 @@ -1,5 +1,5 @@ -; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-apple-darwin | FileCheck %s --check-prefix=ARM -; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-darwin | FileCheck %s --check-prefix=THUMB +; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-apple-ios | FileCheck %s --check-prefix=ARM +; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-ios | FileCheck %s --check-prefix=THUMB define i32 @t0(i1 zeroext %a) nounwind { %1 = zext i1 %a to i32 Modified: llvm/trunk/test/CodeGen/ARM/fast-isel-cmp-imm.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/fast-isel-cmp-imm.ll?rev=146981&r1=146980&r2=146981&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/ARM/fast-isel-cmp-imm.ll (original) +++ llvm/trunk/test/CodeGen/ARM/fast-isel-cmp-imm.ll Tue Dec 20 12:26:50 2011 @@ -1,5 +1,5 @@ -; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-apple-darwin | FileCheck %s --check-prefix=ARM -; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-darwin | FileCheck %s --check-prefix=THUMB +; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-apple-ios | FileCheck %s --check-prefix=ARM +; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-ios | FileCheck %s --check-prefix=THUMB define void @t1a(float %a) uwtable ssp { entry: Modified: llvm/trunk/test/CodeGen/ARM/fast-isel-conversion.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/fast-isel-conversion.ll?rev=146981&r1=146980&r2=146981&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/ARM/fast-isel-conversion.ll (original) +++ llvm/trunk/test/CodeGen/ARM/fast-isel-conversion.ll Tue Dec 20 12:26:50 2011 @@ -1,5 +1,5 @@ -; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-apple-darwin | FileCheck %s --check-prefix=ARM -; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-darwin | FileCheck %s --check-prefix=THUMB +; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-apple-ios | FileCheck %s --check-prefix=ARM +; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-ios | FileCheck %s --check-prefix=THUMB ; Test sitofp Modified: llvm/trunk/test/CodeGen/ARM/fast-isel-deadcode.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/fast-isel-deadcode.ll?rev=146981&r1=146980&r2=146981&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/ARM/fast-isel-deadcode.ll (original) +++ llvm/trunk/test/CodeGen/ARM/fast-isel-deadcode.ll Tue Dec 20 12:26:50 2011 @@ -1,4 +1,4 @@ -; RUN: llc < %s -O0 -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-darwin | FileCheck %s --check-prefix=THUMB +; RUN: llc < %s -O0 -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-ios | FileCheck %s --check-prefix=THUMB ; Target-specific selector can't properly handle the double because it isn't ; being passed via a register, so the materialized arguments become dead code. Modified: llvm/trunk/test/CodeGen/ARM/fast-isel-icmp.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/fast-isel-icmp.ll?rev=146981&r1=146980&r2=146981&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/ARM/fast-isel-icmp.ll (original) +++ llvm/trunk/test/CodeGen/ARM/fast-isel-icmp.ll Tue Dec 20 12:26:50 2011 @@ -1,5 +1,5 @@ -; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-apple-darwin | FileCheck %s --check-prefix=ARM -; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-darwin | FileCheck %s --check-prefix=THUMB +; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-apple-ios | FileCheck %s --check-prefix=ARM +; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-ios | FileCheck %s --check-prefix=THUMB define i32 @icmp_i16_unsigned(i16 %a, i16 %b) nounwind { entry: Modified: llvm/trunk/test/CodeGen/ARM/fast-isel-intrinsic.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/fast-isel-intrinsic.ll?rev=146981&r1=146980&r2=146981&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/ARM/fast-isel-intrinsic.ll (original) +++ llvm/trunk/test/CodeGen/ARM/fast-isel-intrinsic.ll Tue Dec 20 12:26:50 2011 @@ -1,5 +1,5 @@ -; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-apple-darwin | FileCheck %s --check-prefix=ARM -; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-darwin | FileCheck %s --check-prefix=THUMB +; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-apple-ios | FileCheck %s --check-prefix=ARM +; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-ios | FileCheck %s --check-prefix=THUMB @message1 = global [60 x i8] c"The LLVM Compiler Infrastructure\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00", align 1 @temp = common global [60 x i8] zeroinitializer, align 1 Modified: llvm/trunk/test/CodeGen/ARM/fast-isel-ldr-str-thumb-neg-index.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/fast-isel-ldr-str-thumb-neg-index.ll?rev=146981&r1=146980&r2=146981&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/ARM/fast-isel-ldr-str-thumb-neg-index.ll (original) +++ llvm/trunk/test/CodeGen/ARM/fast-isel-ldr-str-thumb-neg-index.ll Tue Dec 20 12:26:50 2011 @@ -1,4 +1,4 @@ -; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-darwin | FileCheck %s --check-prefix=THUMB +; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-ios | FileCheck %s --check-prefix=THUMB define i32 @t1(i32* nocapture %ptr) nounwind readonly { entry: Modified: llvm/trunk/test/CodeGen/ARM/fast-isel-ldrh-strh-arm.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/fast-isel-ldrh-strh-arm.ll?rev=146981&r1=146980&r2=146981&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/ARM/fast-isel-ldrh-strh-arm.ll (original) +++ llvm/trunk/test/CodeGen/ARM/fast-isel-ldrh-strh-arm.ll Tue Dec 20 12:26:50 2011 @@ -1,4 +1,4 @@ -; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-apple-darwin | FileCheck %s --check-prefix=ARM +; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-apple-ios | FileCheck %s --check-prefix=ARM ; rdar://10418009 define zeroext i16 @t1(i16* nocapture %a) nounwind uwtable readonly ssp { Modified: llvm/trunk/test/CodeGen/ARM/fast-isel-mvn.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/fast-isel-mvn.ll?rev=146981&r1=146980&r2=146981&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/ARM/fast-isel-mvn.ll (original) +++ llvm/trunk/test/CodeGen/ARM/fast-isel-mvn.ll Tue Dec 20 12:26:50 2011 @@ -1,5 +1,5 @@ -; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-apple-darwin | FileCheck %s --check-prefix=ARM -; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-darwin | FileCheck %s --check-prefix=THUMB +; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-apple-ios | FileCheck %s --check-prefix=ARM +; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-ios | FileCheck %s --check-prefix=THUMB ; rdar://10412592 ; Note: The Thumb code is being generated by the target-independent selector. @@ -104,4 +104,4 @@ ; THUMB: movt r0, #33023 call void @foo(i32 -2130706433) ret void -} \ No newline at end of file +} Modified: llvm/trunk/test/CodeGen/ARM/fast-isel-ret.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/fast-isel-ret.ll?rev=146981&r1=146980&r2=146981&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/ARM/fast-isel-ret.ll (original) +++ llvm/trunk/test/CodeGen/ARM/fast-isel-ret.ll Tue Dec 20 12:26:50 2011 @@ -1,5 +1,5 @@ -; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-apple-darwin | FileCheck %s -; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-darwin | FileCheck %s +; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-apple-ios | FileCheck %s +; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-ios | FileCheck %s ; Sign-extend of i1 currently not supported by fast-isel ;define signext i1 @ret0(i1 signext %a) nounwind uwtable ssp { Modified: llvm/trunk/test/CodeGen/ARM/fast-isel-select.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/fast-isel-select.ll?rev=146981&r1=146980&r2=146981&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/ARM/fast-isel-select.ll (original) +++ llvm/trunk/test/CodeGen/ARM/fast-isel-select.ll Tue Dec 20 12:26:50 2011 @@ -1,5 +1,5 @@ -; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-apple-darwin | FileCheck %s --check-prefix=ARM -; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-darwin | FileCheck %s --check-prefix=THUMB +; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-apple-ios | FileCheck %s --check-prefix=ARM +; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-ios | FileCheck %s --check-prefix=THUMB define i32 @t1(i1 %c) nounwind readnone { entry: Modified: llvm/trunk/test/CodeGen/ARM/fast-isel.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/fast-isel.ll?rev=146981&r1=146980&r2=146981&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/ARM/fast-isel.ll (original) +++ llvm/trunk/test/CodeGen/ARM/fast-isel.ll Tue Dec 20 12:26:50 2011 @@ -1,5 +1,5 @@ -; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-apple-darwin | FileCheck %s --check-prefix=ARM -; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-darwin | FileCheck %s --check-prefix=THUMB +; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-apple-ios | FileCheck %s --check-prefix=ARM +; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-ios | FileCheck %s --check-prefix=THUMB ; Very basic fast-isel functionality. define i32 @add(i32 %a, i32 %b) nounwind { Modified: llvm/trunk/test/CodeGen/Thumb2/2009-07-21-ISelBug.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb2/2009-07-21-ISelBug.ll?rev=146981&r1=146980&r2=146981&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/Thumb2/2009-07-21-ISelBug.ll (original) +++ llvm/trunk/test/CodeGen/Thumb2/2009-07-21-ISelBug.ll Tue Dec 20 12:26:50 2011 @@ -1,4 +1,4 @@ -; RUN: llc < %s -mtriple=thumbv7-apple-darwin9 -mattr=+vfp2,+thumb2 | FileCheck %s +; RUN: llc < %s -mtriple=thumbv7-apple-ios -mattr=+vfp2,+thumb2 | FileCheck %s ; rdar://7076238 @"\01LC" = external constant [36 x i8], align 1 ; <[36 x i8]*> [#uses=1] From stoklund at 2pi.dk Tue Dec 20 12:44:07 2011 From: stoklund at 2pi.dk (Jakob Stoklund Olesen) Date: Tue, 20 Dec 2011 10:44:07 -0800 Subject: [llvm-commits] [PATCH] Allow SelectionDAGBuilder to reorder loads past stores In-Reply-To: <1324401740.31367.437.camel@sapling> References: <1324316529.31367.96.camel@sapling> <945273C4-D0AA-4CAF-B0ED-C6D96A52FE02@apple.com> <1324325951.31367.178.camel@sapling> <1324355462.31367.287.camel@sapling> <2264DB7F-F14F-4D93-B6C1-79D69B5F2DBF@apple.com> <1324401740.31367.437.camel@sapling> Message-ID: <4B06FCD2-5607-4F5A-989E-C961B6DD6FE4@2pi.dk> On Dec 20, 2011, at 9:22 AM, Hal Finkel wrote: > when I later look at the register map, only XMM0 and XMM1 are ever > assigned to vregs, everything else is spilled. This is wrong. Do you > have any ideas on what could be going wrong or other things I should > examine? Could the register allocator not be accounting correctly for > callee-saved registers when computing live-interval interference > information? There are no callee-saved xmm registers. /jakob From hfinkel at anl.gov Tue Dec 20 12:52:09 2011 From: hfinkel at anl.gov (Hal Finkel) Date: Tue, 20 Dec 2011 12:52:09 -0600 Subject: [llvm-commits] [PATCH] Allow SelectionDAGBuilder to reorder loads past stores In-Reply-To: <4B06FCD2-5607-4F5A-989E-C961B6DD6FE4@2pi.dk> References: <1324316529.31367.96.camel@sapling> <945273C4-D0AA-4CAF-B0ED-C6D96A52FE02@apple.com> <1324325951.31367.178.camel@sapling> <1324355462.31367.287.camel@sapling> <2264DB7F-F14F-4D93-B6C1-79D69B5F2DBF@apple.com> <1324401740.31367.437.camel@sapling> <4B06FCD2-5607-4F5A-989E-C961B6DD6FE4@2pi.dk> Message-ID: <1324407129.31367.481.camel@sapling> On Tue, 2011-12-20 at 10:44 -0800, Jakob Stoklund Olesen wrote: > On Dec 20, 2011, at 9:22 AM, Hal Finkel wrote: > > > when I later look at the register map, only XMM0 and XMM1 are ever > > assigned to vregs, everything else is spilled. This is wrong. Do you > > have any ideas on what could be going wrong or other things I should > > examine? Could the register allocator not be accounting correctly for > > callee-saved registers when computing live-interval interference > > information? > > There are no callee-saved xmm registers. Thanks! I was mixing up the Win64 calling convention with the regular one. That explains things, so, I suppose the right thing to do is to make sure all stores are flushed before any call (which I think it already does), and any intrinsic that will be expanded (which it will not currently do). -Hal > > /jakob > -- Hal Finkel Postdoctoral Appointee Leadership Computing Facility Argonne National Laboratory From mcrosier at apple.com Tue Dec 20 13:06:37 2011 From: mcrosier at apple.com (Chad Rosier) Date: Tue, 20 Dec 2011 11:06:37 -0800 Subject: [llvm-commits] [llvm] r146578 - in /llvm/trunk: lib/Transforms/Scalar/LoopUnswitch.cpp test/Transforms/LoopUnswitch/2011-11-18-SimpleSwitch.ll test/Transforms/LoopUnswitch/2011-11-18-TwoSwitches-Threshold.ll test/Transforms/LoopUnswitch/2011-11-18-TwoSwitches.ll In-Reply-To: <20111214191917.910052A6C12C@llvm.org> References: <20111214191917.910052A6C12C@llvm.org> Message-ID: <01A21900-6703-4740-81EE-EB282C8D02A8@apple.com> Hi Stepan, I noticed this patch caused an ~8% compile-time regression for MultiSource/Benchmarks/Prolangs-C++/shapes/shapes for ARMv7 -O3 -mthumb. If you have a moment would you mind taking a look? The test-suite can be downloaded from the llvm repository (See: http://llvm.org/docs/TestingGuide.html#testsuite). Here are the command line arguments I used to reproduce the regression: /Users/mcrosier/llvm-clean/Release+Asserts/Release+Asserts/bin/clang++ -I/Users/mcrosier/llvm-clean/Release+Asserts/projects/test-suite/MultiSource/Benchmarks/Prolangs-C++/shapes -I/Users/mcrosier/llvm-clean/llvm/projects/test-suite/MultiSource/Benchmarks/Prolangs-C++/shapes -I/Users/mcrosier/llvm-clean/Release+Asserts/projects/test-suite/../../../llvm/projects/test-suite/include -I../../../../include -I/Users/mcrosier/llvm-clean/Release+Asserts/include -I/Users/mcrosier/llvm-clean/llvm/include -D_GNU_SOURCE -D__STDC_LIMIT_MACROS -DNDEBUG -DSMALL_PROBLEM_SIZE -O3 -mthumb -miphoneos-version-min=4.0 -Wl,--no-demangle -ccc-install-dir /Developer/Platforms/iPhoneOS.platform/Developer/usr/bin -arch armv7 -isysroot /Developer/Platforms/iPhoneOS.platform/Developer/SDKs/iPhoneOS6.0.Internal.sdk -c /Users/mcrosier/llvm-clean/llvm/projects/test-suite/MultiSource/Benchmarks/Prolangs-C++/shapes/bjarne.cpp -o Output/bjarne.llvm.o Chad For Apple's record this is being tracked by . On Dec 14, 2011, at 11:19 AM, Stepan Dyatkovskiy wrote: > Author: dyatkovskiy > Date: Wed Dec 14 13:19:17 2011 > New Revision: 146578 > > URL: http://llvm.org/viewvc/llvm-project?rev=146578&view=rev > Log: > Fix for bug #11429: Wrong behaviour for switches. Small improvement for code size heuristics. > > Added: > llvm/trunk/test/Transforms/LoopUnswitch/2011-11-18-SimpleSwitch.ll > llvm/trunk/test/Transforms/LoopUnswitch/2011-11-18-TwoSwitches-Threshold.ll > llvm/trunk/test/Transforms/LoopUnswitch/2011-11-18-TwoSwitches.ll > Modified: > llvm/trunk/lib/Transforms/Scalar/LoopUnswitch.cpp > > Modified: llvm/trunk/lib/Transforms/Scalar/LoopUnswitch.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/LoopUnswitch.cpp?rev=146578&r1=146577&r2=146578&view=diff > ============================================================================== > --- llvm/trunk/lib/Transforms/Scalar/LoopUnswitch.cpp (original) > +++ llvm/trunk/lib/Transforms/Scalar/LoopUnswitch.cpp Wed Dec 14 13:19:17 2011 > @@ -71,7 +71,9 @@ > // LoopProcessWorklist - Used to check if second loop needs processing > // after RewriteLoopBodyWithConditionConstant rewrites first loop. > std::vector LoopProcessWorklist; > - SmallPtrSet UnswitchedVals; > + > + // FIXME: Consider custom class for this. > + std::map > UnswitchedVals; > > bool OptimizeForSize; > bool redoLoop; > @@ -117,7 +119,15 @@ > private: > > virtual void releaseMemory() { > - UnswitchedVals.clear(); > + // We need to forget about all switches in the current loop. > + // FIXME: Do it better than enumerating all blocks of code > + // and see if it is a switch instruction. > + for (Loop::block_iterator I = currentLoop->block_begin(), > + E = currentLoop->block_end(); I != E; ++I) { > + SwitchInst* SI = dyn_cast((*I)->getTerminator()); > + if (SI) > + UnswitchedVals.erase(SI); > + } > } > > /// RemoveLoopFromWorklist - If the specified loop is on the loop worklist, > @@ -128,6 +138,12 @@ > if (I != LoopProcessWorklist.end()) > LoopProcessWorklist.erase(I); > } > + > + /// For new loop switches we clone info about values that was > + /// already unswitched and has redundant successors. > + /// Note, that new loop data is stored inside the VMap. > + void CloneUnswitchedVals(const ValueToValueMapTy& VMap, > + const BasicBlock* SrcBB); > > void initLoopData() { > loopHeader = currentLoop->getHeader(); > @@ -255,13 +271,25 @@ > } else if (SwitchInst *SI = dyn_cast(TI)) { > Value *LoopCond = FindLIVLoopCondition(SI->getCondition(), > currentLoop, Changed); > - if (LoopCond && SI->getNumCases() > 1) { > + unsigned NumCases = SI->getNumCases(); > + if (LoopCond && NumCases > 1) { > // Find a value to unswitch on: > // FIXME: this should chose the most expensive case! > // FIXME: scan for a case with a non-critical edge? > - Constant *UnswitchVal = SI->getCaseValue(1); > + Constant *UnswitchVal = NULL; > + > // Do not process same value again and again. > - if (!UnswitchedVals.insert(UnswitchVal)) > + // At this point we have some cases already unswitched and > + // some not yet unswitched. Let's find the first not yet unswitched one. > + for (unsigned i = 1; i < NumCases; ++i) { > + Constant* UnswitchValCandidate = SI->getCaseValue(i); > + if (!UnswitchedVals[SI].count(UnswitchValCandidate)) { > + UnswitchVal = UnswitchValCandidate; > + break; > + } > + } > + > + if (!UnswitchVal) > continue; > > if (UnswitchIfProfitable(LoopCond, UnswitchVal)) { > @@ -287,6 +315,23 @@ > return Changed; > } > > +/// For new loop switches we clone info about values that was > +/// already unswitched and has redundant successors. > +/// Not that new loop data is stored inside the VMap. > +void LoopUnswitch::CloneUnswitchedVals(const ValueToValueMapTy& VMap, > + const BasicBlock* SrcBB) { > + > + const SwitchInst* SI = dyn_cast(SrcBB->getTerminator()); > + if (SI && UnswitchedVals.count(SI)) { > + // Don't clone a totally simplified switch. > + if (isa(SI->getCondition())) > + return; > + Value* I = VMap.lookup(SI); > + assert(I && "All instructions that are in SrcBB must be in VMap."); > + UnswitchedVals[cast(I)] = UnswitchedVals[SI]; > + } > +} > + > /// isTrivialLoopExitBlock - Check to see if all paths from BB exit the > /// loop with no side effects (including infinite loops). > /// > @@ -378,14 +423,25 @@ > // Check to see if a successor of the switch is guaranteed to go to the > // latch block or exit through a one exit block without having any > // side-effects. If so, determine the value of Cond that causes it to do > - // this. Note that we can't trivially unswitch on the default case. > - for (unsigned i = 1, e = SI->getNumSuccessors(); i != e; ++i) > - if ((LoopExitBB = isTrivialLoopExitBlock(currentLoop, > + // this. > + // Note that we can't trivially unswitch on the default case or > + // on already unswitched cases. > + for (unsigned i = 1, e = SI->getNumSuccessors(); i != e; ++i) { > + BasicBlock* LoopExitCandidate; > + if ((LoopExitCandidate = isTrivialLoopExitBlock(currentLoop, > SI->getSuccessor(i)))) { > // Okay, we found a trivial case, remember the value that is trivial. > - if (Val) *Val = SI->getCaseValue(i); > + ConstantInt* CaseVal = SI->getCaseValue(i); > + > + // Check that it was not unswitched before, since already unswitched > + // trivial vals are looks trivial too. > + if (UnswitchedVals[SI].count(CaseVal)) > + continue; > + LoopExitBB = LoopExitCandidate; > + if (Val) *Val = CaseVal; > break; > } > + } > } > > // If we didn't find a single unique LoopExit block, or if the loop exit block > @@ -447,8 +503,14 @@ > // expansion, and the number of basic blocks, to avoid loops with > // large numbers of branches which cause loop unswitching to go crazy. > // This is a very ad-hoc heuristic. > - if (Metrics.NumInsts > Threshold || > - Metrics.NumBlocks * 5 > Threshold || > + > + unsigned NumUnswitched = > + (NumSwitches + NumBranches) + 1 /*take in account current iteration*/; > + > + unsigned NumInsts = Metrics.NumInsts * NumUnswitched; > + unsigned NumBlocks = Metrics.NumBlocks * NumUnswitched; > + > + if (NumInsts > Threshold || NumBlocks * 5 > Threshold || > Metrics.containsIndirectBr || Metrics.isRecursive) { > DEBUG(dbgs() << "NOT unswitching loop %" > << currentLoop->getHeader()->getName() << ", cost too high: " > @@ -620,6 +682,12 @@ > ValueToValueMapTy VMap; > for (unsigned i = 0, e = LoopBlocks.size(); i != e; ++i) { > BasicBlock *NewBB = CloneBasicBlock(LoopBlocks[i], VMap, ".us", F); > + > + // Inherit simplified switches info for NewBB > + // We needn't pass NewBB since its instructions are already contained > + // inside the VMap. > + CloneUnswitchedVals(VMap, LoopBlocks[i]); > + > NewBlocks.push_back(NewBB); > VMap[LoopBlocks[i]] = NewBB; // Keep the BB mapping. > LPM->cloneBasicBlockSimpleAnalysis(LoopBlocks[i], NewBB, L); > @@ -945,6 +1013,9 @@ > BasicBlock *Switch = SI->getParent(); > BasicBlock *SISucc = SI->getSuccessor(DeadCase); > BasicBlock *Latch = L->getLoopLatch(); > + > + UnswitchedVals[SI].insert(Val); > + > if (!SI->findCaseDest(SISucc)) continue; // Edge is critical. > // If the DeadCase successor dominates the loop latch, then the > // transformation isn't safe since it will delete the sole predecessor edge > > Added: llvm/trunk/test/Transforms/LoopUnswitch/2011-11-18-SimpleSwitch.ll > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/LoopUnswitch/2011-11-18-SimpleSwitch.ll?rev=146578&view=auto > ============================================================================== > --- llvm/trunk/test/Transforms/LoopUnswitch/2011-11-18-SimpleSwitch.ll (added) > +++ llvm/trunk/test/Transforms/LoopUnswitch/2011-11-18-SimpleSwitch.ll Wed Dec 14 13:19:17 2011 > @@ -0,0 +1,91 @@ > +; RUN: opt -loop-unswitch -disable-output -stats -info-output-file - < %s | FileCheck --check-prefix=STATS %s > +; RUN: opt -S -loop-unswitch -verify-loop-info -verify-dom-info %s | FileCheck %s > + > +; STATS: 1 loop-simplify - Number of pre-header or exit blocks inserted > +; STATS: 2 loop-unswitch - Number of switches unswitched > + > +; CHECK: %1 = icmp eq i32 %c, 1 > +; CHECK-NEXT: br i1 %1, label %.split.us, label %..split_crit_edge > + > +; CHECK: ..split_crit_edge: ; preds = %0 > +; CHECK-NEXT: br label %.split > + > +; CHECK: .split.us: ; preds = %0 > +; CHECK-NEXT: br label %loop_begin.us > + > +; CHECK: loop_begin.us: ; preds = %loop_begin.backedge.us, %.split.us > +; CHECK-NEXT: %var_val.us = load i32* %var > +; CHECK-NEXT: switch i32 1, label %default.us-lcssa.us [ > +; CHECK-NEXT: i32 1, label %inc.us > + > +; CHECK: inc.us: ; preds = %loop_begin.us > +; CHECK-NEXT: call void @incf() noreturn nounwind > +; CHECK-NEXT: br label %loop_begin.backedge.us > + > +; CHECK: .split: ; preds = %..split_crit_edge > +; CHECK-NEXT: %2 = icmp eq i32 %c, 2 > +; CHECK-NEXT: br i1 %2, label %.split.split.us, label %.split..split.split_crit_edge > + > +; CHECK: .split..split.split_crit_edge: ; preds = %.split > +; CHECK-NEXT: br label %.split.split > + > +; CHECK: .split.split.us: ; preds = %.split > +; CHECK-NEXT: br label %loop_begin.us1 > + > +; CHECK: loop_begin.us1: ; preds = %loop_begin.backedge.us5, %.split.split.us > +; CHECK-NEXT: %var_val.us2 = load i32* %var > +; CHECK-NEXT: switch i32 2, label %default.us-lcssa.us-lcssa.us [ > +; CHECK-NEXT: i32 1, label %inc.us3 > +; CHECK-NEXT: i32 2, label %dec.us4 > +; CHECK-NEXT: ] > + > +; CHECK: dec.us4: ; preds = %loop_begin.us1 > +; CHECK-NEXT: call void @decf() noreturn nounwind > +; CHECK-NEXT: br label %loop_begin.backedge.us5 > + > +; CHECK: .split.split: ; preds = %.split..split.split_crit_edge > +; CHECK-NEXT: br label %loop_begin > + > +; CHECK: loop_begin: ; preds = %loop_begin.backedge, %.split.split > +; CHECK-NEXT: %var_val = load i32* %var > +; CHECK-NEXT: switch i32 %c, label %default.us-lcssa.us-lcssa [ > +; CHECK-NEXT: i32 1, label %inc > +; CHECK-NEXT: i32 2, label %dec > +; CHECK-NEXT: ] > + > +; CHECK: inc: ; preds = %loop_begin > +; CHECK-NEXT: br i1 true, label %us-unreachable.us-lcssa, label %inc.split > + > +; CHECK: dec: ; preds = %loop_begin > +; CHECK-NEXT: br i1 true, label %us-unreachable6, label %dec.split > + > +define i32 @test(i32* %var) { > + %mem = alloca i32 > + store i32 2, i32* %mem > + %c = load i32* %mem > + > + br label %loop_begin > + > +loop_begin: > + > + %var_val = load i32* %var > + > + switch i32 %c, label %default [ > + i32 1, label %inc > + i32 2, label %dec > + ] > + > +inc: > + call void @incf() noreturn nounwind > + br label %loop_begin > +dec: > + call void @decf() noreturn nounwind > + br label %loop_begin > +default: > + br label %loop_exit > +loop_exit: > + ret i32 0 > +} > + > +declare void @incf() noreturn > +declare void @decf() noreturn > > Added: llvm/trunk/test/Transforms/LoopUnswitch/2011-11-18-TwoSwitches-Threshold.ll > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/LoopUnswitch/2011-11-18-TwoSwitches-Threshold.ll?rev=146578&view=auto > ============================================================================== > --- llvm/trunk/test/Transforms/LoopUnswitch/2011-11-18-TwoSwitches-Threshold.ll (added) > +++ llvm/trunk/test/Transforms/LoopUnswitch/2011-11-18-TwoSwitches-Threshold.ll Wed Dec 14 13:19:17 2011 > @@ -0,0 +1,84 @@ > +; RUN: opt -loop-unswitch -loop-unswitch-threshold 30 -disable-output -stats -info-output-file - < %s | FileCheck --check-prefix=STATS %s > +; RUN: opt -S -loop-unswitch -loop-unswitch-threshold 30 -verify-loop-info -verify-dom-info %s | FileCheck %s > + > +; STATS: 1 loop-simplify - Number of pre-header or exit blocks inserted > +; STATS: 1 loop-unswitch - Number of switches unswitched > + > +; ModuleID = '../llvm/test/Transforms/LoopUnswitch/2011-11-18-TwoSwitches.ll' > + > +; CHECK: %1 = icmp eq i32 %c, 1 > +; CHECK-NEXT: br i1 %1, label %.split.us, label %..split_crit_edge > + > +; CHECK: ..split_crit_edge: ; preds = %0 > +; CHECK-NEXT: br label %.split > + > +; CHECK: .split.us: ; preds = %0 > +; CHECK-NEXT: br label %loop_begin.us > + > +; CHECK: loop_begin.us: ; preds = %loop_begin.backedge.us, %.split.us > +; CHECK: switch i32 1, label %second_switch.us [ > +; CHECK-NEXT: i32 1, label %inc.us > + > +; CHECK: inc.us: ; preds = %second_switch.us, %loop_begin.us > +; CHECK-NEXT: call void @incf() noreturn nounwind > +; CHECK-NEXT: br label %loop_begin.backedge.us > + > +; CHECK: second_switch.us: ; preds = %loop_begin.us > +; CHECK-NEXT: switch i32 %d, label %default.us [ > +; CHECK-NEXT: i32 1, label %inc.us > +; CHECK-NEXT: ] > + > +; CHECK: .split: ; preds = %..split_crit_edge > +; CHECK-NEXT: br label %loop_begin > + > +; CHECK: loop_begin: ; preds = %loop_begin.backedge, %.split > +; CHECK: switch i32 %c, label %second_switch [ > +; CHECK-NEXT: i32 1, label %loop_begin.inc_crit_edge > +; CHECK-NEXT: ] > + > +; CHECK: loop_begin.inc_crit_edge: ; preds = %loop_begin > +; CHECK-NEXT: br i1 true, label %us-unreachable, label %inc > + > +; CHECK: second_switch: ; preds = %loop_begin > +; CHECK-NEXT: switch i32 %d, label %default [ > +; CHECK-NEXT: i32 1, label %inc > +; CHECK-NEXT: ] > + > +; CHECK: inc: ; preds = %loop_begin.inc_crit_edge, %second_switch > +; CHECK-NEXT: call void @incf() noreturn nounwind > +; CHECK-NEXT: br label %loop_begin.backedge > + > +define i32 @test(i32* %var) { > + %mem = alloca i32 > + store i32 2, i32* %mem > + %c = load i32* %mem > + %d = load i32* %mem > + > + br label %loop_begin > + > +loop_begin: > + > + %var_val = load i32* %var > + > + switch i32 %c, label %second_switch [ > + i32 1, label %inc > + ] > + > +second_switch: > + switch i32 %d, label %default [ > + i32 1, label %inc > + ] > + > +inc: > + call void @incf() noreturn nounwind > + br label %loop_begin > + > +default: > + br label %loop_begin > + > +loop_exit: > + ret i32 0 > +} > + > +declare void @incf() noreturn > +declare void @decf() noreturn > > Added: llvm/trunk/test/Transforms/LoopUnswitch/2011-11-18-TwoSwitches.ll > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/LoopUnswitch/2011-11-18-TwoSwitches.ll?rev=146578&view=auto > ============================================================================== > --- llvm/trunk/test/Transforms/LoopUnswitch/2011-11-18-TwoSwitches.ll (added) > +++ llvm/trunk/test/Transforms/LoopUnswitch/2011-11-18-TwoSwitches.ll Wed Dec 14 13:19:17 2011 > @@ -0,0 +1,138 @@ > +; RUN: opt -loop-unswitch -loop-unswitch-threshold 1000 -disable-output -stats -info-output-file - < %s | FileCheck --check-prefix=STATS %s > +; RUN: opt -S -loop-unswitch -loop-unswitch-threshold 1000 -verify-loop-info -verify-dom-info %s | FileCheck %s > + > +; STATS: 1 loop-simplify - Number of pre-header or exit blocks inserted > +; STATS: 3 loop-unswitch - Number of switches unswitched > + > +; CHECK: %1 = icmp eq i32 %c, 1 > +; CHECK-NEXT: br i1 %1, label %.split.us, label %..split_crit_edge > + > +; CHECK: ..split_crit_edge: ; preds = %0 > +; CHECK-NEXT: br label %.split > + > +; CHECK: .split.us: ; preds = %0 > +; CHECK-NEXT: %2 = icmp eq i32 %d, 1 > +; CHECK-NEXT: br i1 %2, label %.split.us.split.us, label %.split.us..split.us.split_crit_edge > + > +; CHECK: .split.us..split.us.split_crit_edge: ; preds = %.split.us > +; CHECK-NEXT: br label %.split.us.split > + > +; CHECK: .split.us.split.us: ; preds = %.split.us > +; CHECK-NEXT: br label %loop_begin.us.us > + > +; CHECK: loop_begin.us.us: ; preds = %loop_begin.backedge.us.us, %.split.us.split.us > +; CHECK-NEXT: %var_val.us.us = load i32* %var > +; CHECK-NEXT: switch i32 1, label %second_switch.us.us [ > +; CHECK-NEXT: i32 1, label %inc.us.us > + > +; CHECK: inc.us.us: ; preds = %second_switch.us.us, %loop_begin.us.us > +; CHECK-NEXT: call void @incf() noreturn nounwind > +; CHECK-NEXT: br label %loop_begin.backedge.us.us > + > +; CHECK: second_switch.us.us: ; preds = %loop_begin.us.us > +; CHECK-NEXT: switch i32 1, label %default.us.us [ > +; CHECK-NEXT: i32 1, label %inc.us.us > + > +; CHECK: .split.us.split: ; preds = %.split.us..split.us.split_crit_edge > +; CHECK-NEXT: br label %loop_begin.us > + > +; CHECK: loop_begin.us: ; preds = %loop_begin.backedge.us, %.split.us.split > +; CHECK-NEXT: %var_val.us = load i32* %var > +; CHECK-NEXT: switch i32 1, label %second_switch.us [ > +; CHECK-NEXT: i32 1, label %inc.us > + > +; CHECK: inc.us: ; preds = %second_switch.us.inc.us_crit_edge, %loop_begin.us > +; CHECK-NEXT: call void @incf() noreturn nounwind > +; CHECK-NEXT: br label %loop_begin.backedge.us > + > +; CHECK: second_switch.us: ; preds = %loop_begin.us > +; CHECK-NEXT: switch i32 %d, label %default.us [ > +; CHECK-NEXT: i32 1, label %second_switch.us.inc.us_crit_edge > +; CHECK-NEXT: ] > + > +; CHECK: second_switch.us.inc.us_crit_edge: ; preds = %second_switch.us > +; CHECK-NEXT: br i1 true, label %us-unreachable8, label %inc.us > + > +; CHECK: .split: ; preds = %..split_crit_edge > +; CHECK-NEXT: %3 = icmp eq i32 %d, 1 > +; CHECK-NEXT: br i1 %3, label %.split.split.us, label %.split..split.split_crit_edge > + > +; CHECK: .split..split.split_crit_edge: ; preds = %.split > +; CHECK-NEXT: br label %.split.split > + > +; CHECK: .split.split.us: ; preds = %.split > +; CHECK-NEXT: br label %loop_begin.us1 > + > +; CHECK: loop_begin.us1: ; preds = %loop_begin.backedge.us6, %.split.split.us > +; CHECK-NEXT: %var_val.us2 = load i32* %var > +; CHECK-NEXT: switch i32 %c, label %second_switch.us4 [ > +; CHECK-NEXT: i32 1, label %loop_begin.inc_crit_edge.us > +; CHECK-NEXT: ] > + > +; CHECK: inc.us3: ; preds = %loop_begin.inc_crit_edge.us, %second_switch.us4 > +; CHECK-NEXT: call void @incf() noreturn nounwind > +; CHECK-NEXT: br label %loop_begin.backedge.us6 > + > +; CHECK: second_switch.us4: ; preds = %loop_begin.us1 > +; CHECK-NEXT: switch i32 1, label %default.us5 [ > +; CHECK-NEXT: i32 1, label %inc.us3 > +; CHECK-NEXT: ] > + > +; CHECK: loop_begin.inc_crit_edge.us: ; preds = %loop_begin.us1 > +; CHECK-NEXT: br i1 true, label %us-unreachable.us-lcssa.us, label %inc.us3 > + > +; CHECK: .split.split: ; preds = %.split..split.split_crit_edge > +; CHECK-NEXT: br label %loop_begin > + > +; CHECK: loop_begin: ; preds = %loop_begin.backedge, %.split.split > +; CHECK-NEXT: %var_val = load i32* %var > +; CHECK-NEXT: switch i32 %c, label %second_switch [ > +; CHECK-NEXT: i32 1, label %loop_begin.inc_crit_edge > +; CHECK-NEXT: ] > + > +; CHECK: loop_begin.inc_crit_edge: ; preds = %loop_begin > +; CHECK-NEXT: br i1 true, label %us-unreachable.us-lcssa, label %inc > + > +; CHECK: second_switch: ; preds = %loop_begin > +; CHECK-NEXT: switch i32 %d, label %default [ > +; CHECK-NEXT: i32 1, label %second_switch.inc_crit_edge > +; CHECK-NEXT: ] > + > +; CHECK: second_switch.inc_crit_edge: ; preds = %second_switch > +; CHECK-NEXT: br i1 true, label %us-unreachable7, label %inc > + > + > +define i32 @test(i32* %var) { > + %mem = alloca i32 > + store i32 2, i32* %mem > + %c = load i32* %mem > + %d = load i32* %mem > + > + br label %loop_begin > + > +loop_begin: > + > + %var_val = load i32* %var > + > + switch i32 %c, label %second_switch [ > + i32 1, label %inc > + ] > + > +second_switch: > + switch i32 %d, label %default [ > + i32 1, label %inc > + ] > + > +inc: > + call void @incf() noreturn nounwind > + br label %loop_begin > + > +default: > + br label %loop_begin > + > +loop_exit: > + ret i32 0 > +} > + > +declare void @incf() noreturn > +declare void @decf() noreturn > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From grosbach at apple.com Tue Dec 20 13:07:21 2011 From: grosbach at apple.com (Jim Grosbach) Date: Tue, 20 Dec 2011 11:07:21 -0800 Subject: [llvm-commits] [PATCH] MC ARM Thumb: fix incorrect relocation generation (PR11214) In-Reply-To: <000001ccbf1d$618f7490$24ae5db0$%beyls@arm.com> References: <000001ccbf1d$618f7490$24ae5db0$%beyls@arm.com> Message-ID: <57817466-3086-4652-85E2-4959AF23D81B@apple.com> Someone with ELF knowledge should look at this. I'm a bit nervous about removing the conditional as it seems to imply that there's an different relocation that should be generated depending on the variant kind. -Jim On Dec 20, 2011, at 5:43 AM, Kristof Beyls wrote: > Hi, > > Please find a patch for fixing incorrect generation of relocation > information on Thumb function calls. > This should fix quite a few incorrect code generation problems in Thumb mode > when using the integrated assembler. > I believe this fixes PR11214 > (http://www.llvm.org/bugs/show_bug.cgi?id=11214). > > Is this OK? > > Thanks, > > Kristof > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From James.Molloy at arm.com Tue Dec 20 13:21:56 2011 From: James.Molloy at arm.com (James Molloy) Date: Tue, 20 Dec 2011 19:21:56 +0000 Subject: [llvm-commits] [PATCH] MC ARM Thumb: fix incorrect relocation generation (PR11214) In-Reply-To: <57817466-3086-4652-85E2-4959AF23D81B@apple.com> References: <000001ccbf1d$618f7490$24ae5db0$%beyls@arm.com>, <57817466-3086-4652-85E2-4959AF23D81B@apple.com> Message-ID: Yeah, I was confused about that too. I couldn't comprehend why that conditional was even there in the first place - an R_ARM_NONE relocation is *never* required for a call (it's a special no-op reloc). The only thing I could think of is that someone wanted to fix the relocation given to PLT entries and decided to keep the a broken behaviour for the default case, perhaps they had no knowledge about it. ________________________________________ From: llvm-commits-bounces at cs.uiuc.edu [llvm-commits-bounces at cs.uiuc.edu] On Behalf Of Jim Grosbach [grosbach at apple.com] Sent: 20 December 2011 19:07 To: Kristof Beyls Cc: llvm-commits at cs.uiuc.edu Subject: Re: [llvm-commits] [PATCH] MC ARM Thumb: fix incorrect relocation generation (PR11214) Someone with ELF knowledge should look at this. I'm a bit nervous about removing the conditional as it seems to imply that there's an different relocation that should be generated depending on the variant kind. -Jim On Dec 20, 2011, at 5:43 AM, Kristof Beyls wrote: > Hi, > > Please find a patch for fixing incorrect generation of relocation > information on Thumb function calls. > This should fix quite a few incorrect code generation problems in Thumb mode > when using the integrated assembler. > I believe this fixes PR11214 > (http://www.llvm.org/bugs/show_bug.cgi?id=11214). > > Is this OK? > > Thanks, > > Kristof > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits _______________________________________________ llvm-commits mailing list llvm-commits at cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits -- IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you. From grosbach at apple.com Tue Dec 20 13:21:27 2011 From: grosbach at apple.com (Jim Grosbach) Date: Tue, 20 Dec 2011 19:21:27 -0000 Subject: [llvm-commits] [llvm] r146983 - in /llvm/trunk: lib/Target/ARM/ARMInstrNEON.td lib/Target/ARM/AsmParser/ARMAsmParser.cpp test/MC/ARM/neon-vld-encoding.s Message-ID: <20111220192127.C72E72A6C12C@llvm.org> Author: grosbach Date: Tue Dec 20 13:21:26 2011 New Revision: 146983 URL: http://llvm.org/viewvc/llvm-project?rev=146983&view=rev Log: ARM assembly parsing and encoding for VLD2 single-element, double spaced. Modified: llvm/trunk/lib/Target/ARM/ARMInstrNEON.td llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp llvm/trunk/test/MC/ARM/neon-vld-encoding.s Modified: llvm/trunk/lib/Target/ARM/ARMInstrNEON.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrNEON.td?rev=146983&r1=146982&r2=146983&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrNEON.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrNEON.td Tue Dec 20 13:21:26 2011 @@ -174,7 +174,7 @@ let ParserMatchClass = VecListOneDWordIndexAsmOperand; let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx); } -// Register list of two D registers, with byte lane subscripting. +// Register list of two D registers with byte lane subscripting. def VecListTwoDByteIndexAsmOperand : AsmOperandClass { let Name = "VecListTwoDByteIndexed"; let ParserMethod = "parseVectorList"; @@ -204,6 +204,26 @@ let ParserMatchClass = VecListTwoDWordIndexAsmOperand; let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx); } +// Register list of two Q registers with half-word lane subscripting. +def VecListTwoQHWordIndexAsmOperand : AsmOperandClass { + let Name = "VecListTwoQHWordIndexed"; + let ParserMethod = "parseVectorList"; + let RenderMethod = "addVecListIndexedOperands"; +} +def VecListTwoQHWordIndexed : Operand { + let ParserMatchClass = VecListTwoQHWordIndexAsmOperand; + let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx); +} +// ...with word lane subscripting. +def VecListTwoQWordIndexAsmOperand : AsmOperandClass { + let Name = "VecListTwoQWordIndexed"; + let ParserMethod = "parseVectorList"; + let RenderMethod = "addVecListIndexedOperands"; +} +def VecListTwoQWordIndexed : Operand { + let ParserMatchClass = VecListTwoQWordIndexAsmOperand; + let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx); +} //===----------------------------------------------------------------------===// // NEON-specific DAG Nodes. @@ -5735,6 +5755,10 @@ (ins VecListTwoDHWordIndexed:$list, addrmode6:$addr, pred:$p)>; defm VLD2LNdAsm : NEONDT32AsmPseudoInst<"vld2${p}", "$list, $addr", (ins VecListTwoDWordIndexed:$list, addrmode6:$addr, pred:$p)>; +defm VLD2LNqAsm : NEONDT16AsmPseudoInst<"vld2${p}", "$list, $addr", + (ins VecListTwoQHWordIndexed:$list, addrmode6:$addr, pred:$p)>; +defm VLD2LNqAsm : NEONDT32AsmPseudoInst<"vld2${p}", "$list, $addr", + (ins VecListTwoQWordIndexed:$list, addrmode6:$addr, pred:$p)>; defm VLD2LNdWB_fixed_Asm : NEONDT8AsmPseudoInst<"vld2${p}", "$list, $addr!", (ins VecListTwoDByteIndexed:$list, addrmode6:$addr, pred:$p)>; @@ -5742,6 +5766,10 @@ (ins VecListTwoDHWordIndexed:$list, addrmode6:$addr, pred:$p)>; defm VLD2LNdWB_fixed_Asm : NEONDT32AsmPseudoInst<"vld2${p}", "$list, $addr!", (ins VecListTwoDWordIndexed:$list, addrmode6:$addr, pred:$p)>; +defm VLD2LNqWB_fixed_Asm : NEONDT16AsmPseudoInst<"vld2${p}", "$list, $addr!", + (ins VecListTwoQHWordIndexed:$list, addrmode6:$addr, pred:$p)>; +defm VLD2LNqWB_fixed_Asm : NEONDT32AsmPseudoInst<"vld2${p}", "$list, $addr!", + (ins VecListTwoQWordIndexed:$list, addrmode6:$addr, pred:$p)>; defm VLD2LNdWB_register_Asm : NEONDT8AsmPseudoInst<"vld2${p}", "$list, $addr, $Rm", (ins VecListTwoDByteIndexed:$list, addrmode6:$addr, @@ -5754,6 +5782,14 @@ NEONDT32AsmPseudoInst<"vld2${p}", "$list, $addr, $Rm", (ins VecListTwoDWordIndexed:$list, addrmode6:$addr, rGPR:$Rm, pred:$p)>; +defm VLD2LNqWB_register_Asm : + NEONDT16AsmPseudoInst<"vld2${p}", "$list, $addr, $Rm", + (ins VecListTwoQHWordIndexed:$list, addrmode6:$addr, + rGPR:$Rm, pred:$p)>; +defm VLD2LNqWB_register_Asm : + NEONDT32AsmPseudoInst<"vld2${p}", "$list, $addr, $Rm", + (ins VecListTwoQWordIndexed:$list, addrmode6:$addr, + rGPR:$Rm, pred:$p)>; // VST2 single-lane pseudo-instructions. These need special handling for Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp?rev=146983&r1=146982&r2=146983&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp (original) +++ llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Tue Dec 20 13:21:26 2011 @@ -1128,33 +1128,49 @@ return VectorList.Count == 2; } + bool isSingleSpacedVectorIndexed() const { + return Kind == k_VectorListIndexed && !VectorList.isDoubleSpaced; + } + bool isDoubleSpacedVectorIndexed() const { + return Kind == k_VectorListIndexed && VectorList.isDoubleSpaced; + } bool isVecListOneDByteIndexed() const { - if (Kind != k_VectorListIndexed) return false; + if (!isSingleSpacedVectorIndexed()) return false; return VectorList.Count == 1 && VectorList.LaneIndex <= 7; } bool isVecListOneDHWordIndexed() const { - if (Kind != k_VectorListIndexed) return false; + if (!isSingleSpacedVectorIndexed()) return false; return VectorList.Count == 1 && VectorList.LaneIndex <= 3; } bool isVecListOneDWordIndexed() const { - if (Kind != k_VectorListIndexed) return false; + if (!isSingleSpacedVectorIndexed()) return false; return VectorList.Count == 1 && VectorList.LaneIndex <= 1; } bool isVecListTwoDByteIndexed() const { - if (Kind != k_VectorListIndexed) return false; + if (!isSingleSpacedVectorIndexed()) return false; return VectorList.Count == 2 && VectorList.LaneIndex <= 7; } bool isVecListTwoDHWordIndexed() const { - if (Kind != k_VectorListIndexed) return false; + if (!isSingleSpacedVectorIndexed()) return false; + return VectorList.Count == 2 && VectorList.LaneIndex <= 3; + } + + bool isVecListTwoQWordIndexed() const { + if (!isDoubleSpacedVectorIndexed()) return false; + return VectorList.Count == 2 && VectorList.LaneIndex <= 1; + } + + bool isVecListTwoQHWordIndexed() const { + if (!isDoubleSpacedVectorIndexed()) return false; return VectorList.Count == 2 && VectorList.LaneIndex <= 3; } bool isVecListTwoDWordIndexed() const { - if (Kind != k_VectorListIndexed) return false; + if (!isSingleSpacedVectorIndexed()) return false; return VectorList.Count == 2 && VectorList.LaneIndex <= 1; } @@ -2035,11 +2051,14 @@ } static ARMOperand *CreateVectorListIndexed(unsigned RegNum, unsigned Count, - unsigned Index, SMLoc S, SMLoc E) { + unsigned Index, + bool isDoubleSpaced, + SMLoc S, SMLoc E) { ARMOperand *Op = new ARMOperand(k_VectorListIndexed); Op->VectorList.RegNum = RegNum; Op->VectorList.Count = Count; Op->VectorList.LaneIndex = Index; + Op->VectorList.isDoubleSpaced = isDoubleSpaced; Op->StartLoc = S; Op->EndLoc = E; return Op; @@ -2849,7 +2868,8 @@ break; case IndexedLane: Operands.push_back(ARMOperand::CreateVectorListIndexed(Reg, 1, - LaneIndex, S,E)); + LaneIndex, + false, S, E)); break; } return MatchOperand_Success; @@ -2872,7 +2892,8 @@ break; case IndexedLane: Operands.push_back(ARMOperand::CreateVectorListIndexed(Reg, 2, - LaneIndex, S,E)); + LaneIndex, + false, S, E)); break; } return MatchOperand_Success; @@ -3020,11 +3041,6 @@ Error(EndLoc, "mismatched lane index in register list"); return MatchOperand_ParseFail; } - if (Spacing == 2 && LaneKind != NoLanes) { - Error(EndLoc, - "lane index specfier invalid in double spaced register list"); - return MatchOperand_ParseFail; - } } SMLoc E = Parser.getTok().getLoc(); @@ -3047,7 +3063,9 @@ break; case IndexedLane: Operands.push_back(ARMOperand::CreateVectorListIndexed(FirstReg, Count, - LaneIndex, S, E)); + LaneIndex, + (Spacing == 2), + S, E)); break; } return MatchOperand_Success; @@ -5181,84 +5199,132 @@ } } -static unsigned getRealVLDLNOpcode(unsigned Opc) { +static unsigned getRealVLDLNOpcode(unsigned Opc, unsigned &Spacing) { switch(Opc) { default: assert(0 && "unexpected opcode!"); // VLD1LN case ARM::VLD1LNdWB_fixed_Asm_8: case ARM::VLD1LNdWB_fixed_Asm_P8: case ARM::VLD1LNdWB_fixed_Asm_I8: case ARM::VLD1LNdWB_fixed_Asm_S8: case ARM::VLD1LNdWB_fixed_Asm_U8: + Spacing = 1; return ARM::VLD1LNd8_UPD; case ARM::VLD1LNdWB_fixed_Asm_16: case ARM::VLD1LNdWB_fixed_Asm_P16: case ARM::VLD1LNdWB_fixed_Asm_I16: case ARM::VLD1LNdWB_fixed_Asm_S16: case ARM::VLD1LNdWB_fixed_Asm_U16: + Spacing = 1; return ARM::VLD1LNd16_UPD; case ARM::VLD1LNdWB_fixed_Asm_32: case ARM::VLD1LNdWB_fixed_Asm_F: case ARM::VLD1LNdWB_fixed_Asm_F32: case ARM::VLD1LNdWB_fixed_Asm_I32: case ARM::VLD1LNdWB_fixed_Asm_S32: case ARM::VLD1LNdWB_fixed_Asm_U32: + Spacing = 1; return ARM::VLD1LNd32_UPD; case ARM::VLD1LNdWB_register_Asm_8: case ARM::VLD1LNdWB_register_Asm_P8: case ARM::VLD1LNdWB_register_Asm_I8: case ARM::VLD1LNdWB_register_Asm_S8: case ARM::VLD1LNdWB_register_Asm_U8: + Spacing = 1; return ARM::VLD1LNd8_UPD; case ARM::VLD1LNdWB_register_Asm_16: case ARM::VLD1LNdWB_register_Asm_P16: case ARM::VLD1LNdWB_register_Asm_I16: case ARM::VLD1LNdWB_register_Asm_S16: case ARM::VLD1LNdWB_register_Asm_U16: + Spacing = 1; return ARM::VLD1LNd16_UPD; case ARM::VLD1LNdWB_register_Asm_32: case ARM::VLD1LNdWB_register_Asm_F: case ARM::VLD1LNdWB_register_Asm_F32: case ARM::VLD1LNdWB_register_Asm_I32: case ARM::VLD1LNdWB_register_Asm_S32: case ARM::VLD1LNdWB_register_Asm_U32: + Spacing = 1; return ARM::VLD1LNd32_UPD; case ARM::VLD1LNdAsm_8: case ARM::VLD1LNdAsm_P8: case ARM::VLD1LNdAsm_I8: case ARM::VLD1LNdAsm_S8: case ARM::VLD1LNdAsm_U8: + Spacing = 1; return ARM::VLD1LNd8; case ARM::VLD1LNdAsm_16: case ARM::VLD1LNdAsm_P16: case ARM::VLD1LNdAsm_I16: case ARM::VLD1LNdAsm_S16: case ARM::VLD1LNdAsm_U16: + Spacing = 1; return ARM::VLD1LNd16; case ARM::VLD1LNdAsm_32: case ARM::VLD1LNdAsm_F: case ARM::VLD1LNdAsm_F32: case ARM::VLD1LNdAsm_I32: case ARM::VLD1LNdAsm_S32: case ARM::VLD1LNdAsm_U32: + Spacing = 1; return ARM::VLD1LNd32; // VLD2LN case ARM::VLD2LNdWB_fixed_Asm_8: case ARM::VLD2LNdWB_fixed_Asm_P8: case ARM::VLD2LNdWB_fixed_Asm_I8: case ARM::VLD2LNdWB_fixed_Asm_S8: case ARM::VLD2LNdWB_fixed_Asm_U8: + Spacing = 1; return ARM::VLD2LNd8_UPD; case ARM::VLD2LNdWB_fixed_Asm_16: case ARM::VLD2LNdWB_fixed_Asm_P16: case ARM::VLD2LNdWB_fixed_Asm_I16: case ARM::VLD2LNdWB_fixed_Asm_S16: case ARM::VLD2LNdWB_fixed_Asm_U16: + Spacing = 1; return ARM::VLD2LNd16_UPD; case ARM::VLD2LNdWB_fixed_Asm_32: case ARM::VLD2LNdWB_fixed_Asm_F: case ARM::VLD2LNdWB_fixed_Asm_F32: case ARM::VLD2LNdWB_fixed_Asm_I32: case ARM::VLD2LNdWB_fixed_Asm_S32: case ARM::VLD2LNdWB_fixed_Asm_U32: + Spacing = 1; return ARM::VLD2LNd32_UPD; + case ARM::VLD2LNqWB_fixed_Asm_16: case ARM::VLD2LNqWB_fixed_Asm_P16: + case ARM::VLD2LNqWB_fixed_Asm_I16: case ARM::VLD2LNqWB_fixed_Asm_S16: + case ARM::VLD2LNqWB_fixed_Asm_U16: + Spacing = 1; + return ARM::VLD2LNq16_UPD; + case ARM::VLD2LNqWB_fixed_Asm_32: case ARM::VLD2LNqWB_fixed_Asm_F: + case ARM::VLD2LNqWB_fixed_Asm_F32: case ARM::VLD2LNqWB_fixed_Asm_I32: + case ARM::VLD2LNqWB_fixed_Asm_S32: case ARM::VLD2LNqWB_fixed_Asm_U32: + Spacing = 2; + return ARM::VLD2LNq32_UPD; case ARM::VLD2LNdWB_register_Asm_8: case ARM::VLD2LNdWB_register_Asm_P8: case ARM::VLD2LNdWB_register_Asm_I8: case ARM::VLD2LNdWB_register_Asm_S8: case ARM::VLD2LNdWB_register_Asm_U8: + Spacing = 1; return ARM::VLD2LNd8_UPD; case ARM::VLD2LNdWB_register_Asm_16: case ARM::VLD2LNdWB_register_Asm_P16: case ARM::VLD2LNdWB_register_Asm_I16: case ARM::VLD2LNdWB_register_Asm_S16: case ARM::VLD2LNdWB_register_Asm_U16: + Spacing = 1; return ARM::VLD2LNd16_UPD; case ARM::VLD2LNdWB_register_Asm_32: case ARM::VLD2LNdWB_register_Asm_F: case ARM::VLD2LNdWB_register_Asm_F32: case ARM::VLD2LNdWB_register_Asm_I32: case ARM::VLD2LNdWB_register_Asm_S32: case ARM::VLD2LNdWB_register_Asm_U32: + Spacing = 1; return ARM::VLD2LNd32_UPD; + case ARM::VLD2LNqWB_register_Asm_16: case ARM::VLD2LNqWB_register_Asm_P16: + case ARM::VLD2LNqWB_register_Asm_I16: case ARM::VLD2LNqWB_register_Asm_S16: + case ARM::VLD2LNqWB_register_Asm_U16: + Spacing = 2; + return ARM::VLD2LNq16_UPD; + case ARM::VLD2LNqWB_register_Asm_32: case ARM::VLD2LNqWB_register_Asm_F: + case ARM::VLD2LNqWB_register_Asm_F32: case ARM::VLD2LNqWB_register_Asm_I32: + case ARM::VLD2LNqWB_register_Asm_S32: case ARM::VLD2LNqWB_register_Asm_U32: + Spacing = 2; + return ARM::VLD2LNq32_UPD; case ARM::VLD2LNdAsm_8: case ARM::VLD2LNdAsm_P8: case ARM::VLD2LNdAsm_I8: case ARM::VLD2LNdAsm_S8: case ARM::VLD2LNdAsm_U8: + Spacing = 1; return ARM::VLD2LNd8; case ARM::VLD2LNdAsm_16: case ARM::VLD2LNdAsm_P16: case ARM::VLD2LNdAsm_I16: case ARM::VLD2LNdAsm_S16: case ARM::VLD2LNdAsm_U16: + Spacing = 1; return ARM::VLD2LNd16; case ARM::VLD2LNdAsm_32: case ARM::VLD2LNdAsm_F: case ARM::VLD2LNdAsm_F32: case ARM::VLD2LNdAsm_I32: case ARM::VLD2LNdAsm_S32: case ARM::VLD2LNdAsm_U32: + Spacing = 1; return ARM::VLD2LNd32; + case ARM::VLD2LNqAsm_16: case ARM::VLD2LNqAsm_P16: + case ARM::VLD2LNqAsm_I16: case ARM::VLD2LNqAsm_S16: + case ARM::VLD2LNqAsm_U16: + Spacing = 2; + return ARM::VLD2LNq16; + case ARM::VLD2LNqAsm_32: case ARM::VLD2LNqAsm_F: + case ARM::VLD2LNqAsm_F32: case ARM::VLD2LNqAsm_I32: + case ARM::VLD2LNqAsm_S32: case ARM::VLD2LNqAsm_U32: + Spacing = 2; + return ARM::VLD2LNq32; } } @@ -5415,7 +5481,8 @@ MCInst TmpInst; // Shuffle the operands around so the lane index operand is in the // right place. - TmpInst.setOpcode(getRealVLDLNOpcode(Inst.getOpcode())); + unsigned Spacing; + TmpInst.setOpcode(getRealVLDLNOpcode(Inst.getOpcode(), Spacing)); TmpInst.addOperand(Inst.getOperand(0)); // Vd TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb TmpInst.addOperand(Inst.getOperand(2)); // Rn @@ -5429,26 +5496,34 @@ return true; } - case ARM::VLD2LNdWB_register_Asm_8: case ARM::VLD2LNdWB_register_Asm_P8: - case ARM::VLD2LNdWB_register_Asm_I8: case ARM::VLD2LNdWB_register_Asm_S8: - case ARM::VLD2LNdWB_register_Asm_U8: case ARM::VLD2LNdWB_register_Asm_16: + case ARM::VLD2LNdWB_register_Asm_8: case ARM::VLD2LNdWB_register_Asm_P8: + case ARM::VLD2LNdWB_register_Asm_I8: case ARM::VLD2LNdWB_register_Asm_S8: + case ARM::VLD2LNdWB_register_Asm_U8: case ARM::VLD2LNdWB_register_Asm_16: case ARM::VLD2LNdWB_register_Asm_P16: case ARM::VLD2LNdWB_register_Asm_I16: case ARM::VLD2LNdWB_register_Asm_S16: case ARM::VLD2LNdWB_register_Asm_U16: - case ARM::VLD2LNdWB_register_Asm_32: case ARM::VLD2LNdWB_register_Asm_F: + case ARM::VLD2LNdWB_register_Asm_32: case ARM::VLD2LNdWB_register_Asm_F: case ARM::VLD2LNdWB_register_Asm_F32: case ARM::VLD2LNdWB_register_Asm_I32: - case ARM::VLD2LNdWB_register_Asm_S32: case ARM::VLD2LNdWB_register_Asm_U32: { + case ARM::VLD2LNdWB_register_Asm_S32: case ARM::VLD2LNdWB_register_Asm_U32: + case ARM::VLD2LNqWB_register_Asm_P16: case ARM::VLD2LNqWB_register_Asm_I16: + case ARM::VLD2LNqWB_register_Asm_S16: case ARM::VLD2LNqWB_register_Asm_U16: + case ARM::VLD2LNqWB_register_Asm_32: case ARM::VLD2LNqWB_register_Asm_F: + case ARM::VLD2LNqWB_register_Asm_F32: case ARM::VLD2LNqWB_register_Asm_I32: + case ARM::VLD2LNqWB_register_Asm_S32: case ARM::VLD2LNqWB_register_Asm_U32: { MCInst TmpInst; // Shuffle the operands around so the lane index operand is in the // right place. - TmpInst.setOpcode(getRealVLDLNOpcode(Inst.getOpcode())); + unsigned Spacing; + TmpInst.setOpcode(getRealVLDLNOpcode(Inst.getOpcode(), Spacing)); TmpInst.addOperand(Inst.getOperand(0)); // Vd - TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg()+1)); + TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + + Spacing)); TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb TmpInst.addOperand(Inst.getOperand(2)); // Rn TmpInst.addOperand(Inst.getOperand(3)); // alignment TmpInst.addOperand(Inst.getOperand(4)); // Rm TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd) - TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg()+1)); + TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + + Spacing)); TmpInst.addOperand(Inst.getOperand(1)); // lane TmpInst.addOperand(Inst.getOperand(5)); // CondCode TmpInst.addOperand(Inst.getOperand(6)); @@ -5467,7 +5542,8 @@ MCInst TmpInst; // Shuffle the operands around so the lane index operand is in the // right place. - TmpInst.setOpcode(getRealVLDLNOpcode(Inst.getOpcode())); + unsigned Spacing; + TmpInst.setOpcode(getRealVLDLNOpcode(Inst.getOpcode(), Spacing)); TmpInst.addOperand(Inst.getOperand(0)); // Vd TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb TmpInst.addOperand(Inst.getOperand(2)); // Rn @@ -5481,26 +5557,34 @@ return true; } - case ARM::VLD2LNdWB_fixed_Asm_8: case ARM::VLD2LNdWB_fixed_Asm_P8: - case ARM::VLD2LNdWB_fixed_Asm_I8: case ARM::VLD2LNdWB_fixed_Asm_S8: - case ARM::VLD2LNdWB_fixed_Asm_U8: case ARM::VLD2LNdWB_fixed_Asm_16: + case ARM::VLD2LNdWB_fixed_Asm_8: case ARM::VLD2LNdWB_fixed_Asm_P8: + case ARM::VLD2LNdWB_fixed_Asm_I8: case ARM::VLD2LNdWB_fixed_Asm_S8: + case ARM::VLD2LNdWB_fixed_Asm_U8: case ARM::VLD2LNdWB_fixed_Asm_16: case ARM::VLD2LNdWB_fixed_Asm_P16: case ARM::VLD2LNdWB_fixed_Asm_I16: case ARM::VLD2LNdWB_fixed_Asm_S16: case ARM::VLD2LNdWB_fixed_Asm_U16: - case ARM::VLD2LNdWB_fixed_Asm_32: case ARM::VLD2LNdWB_fixed_Asm_F: + case ARM::VLD2LNdWB_fixed_Asm_32: case ARM::VLD2LNdWB_fixed_Asm_F: case ARM::VLD2LNdWB_fixed_Asm_F32: case ARM::VLD2LNdWB_fixed_Asm_I32: - case ARM::VLD2LNdWB_fixed_Asm_S32: case ARM::VLD2LNdWB_fixed_Asm_U32: { + case ARM::VLD2LNdWB_fixed_Asm_S32: case ARM::VLD2LNdWB_fixed_Asm_U32: + case ARM::VLD2LNqWB_fixed_Asm_P16: case ARM::VLD2LNqWB_fixed_Asm_I16: + case ARM::VLD2LNqWB_fixed_Asm_S16: case ARM::VLD2LNqWB_fixed_Asm_U16: + case ARM::VLD2LNqWB_fixed_Asm_32: case ARM::VLD2LNqWB_fixed_Asm_F: + case ARM::VLD2LNqWB_fixed_Asm_F32: case ARM::VLD2LNqWB_fixed_Asm_I32: + case ARM::VLD2LNqWB_fixed_Asm_S32: case ARM::VLD2LNqWB_fixed_Asm_U32: { MCInst TmpInst; // Shuffle the operands around so the lane index operand is in the // right place. - TmpInst.setOpcode(getRealVLDLNOpcode(Inst.getOpcode())); + unsigned Spacing; + TmpInst.setOpcode(getRealVLDLNOpcode(Inst.getOpcode(), Spacing)); TmpInst.addOperand(Inst.getOperand(0)); // Vd - TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg()+1)); + TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + + Spacing)); TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb TmpInst.addOperand(Inst.getOperand(2)); // Rn TmpInst.addOperand(Inst.getOperand(3)); // alignment TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd) - TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg()+1)); + TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + + Spacing)); TmpInst.addOperand(Inst.getOperand(1)); // lane TmpInst.addOperand(Inst.getOperand(4)); // CondCode TmpInst.addOperand(Inst.getOperand(5)); @@ -5517,7 +5601,8 @@ MCInst TmpInst; // Shuffle the operands around so the lane index operand is in the // right place. - TmpInst.setOpcode(getRealVLDLNOpcode(Inst.getOpcode())); + unsigned Spacing; + TmpInst.setOpcode(getRealVLDLNOpcode(Inst.getOpcode(), Spacing)); TmpInst.addOperand(Inst.getOperand(0)); // Vd TmpInst.addOperand(Inst.getOperand(2)); // Rn TmpInst.addOperand(Inst.getOperand(3)); // alignment @@ -5529,22 +5614,29 @@ return true; } - case ARM::VLD2LNdAsm_8: case ARM::VLD2LNdAsm_P8: case ARM::VLD2LNdAsm_I8: - case ARM::VLD2LNdAsm_S8: case ARM::VLD2LNdAsm_U8: case ARM::VLD2LNdAsm_16: + case ARM::VLD2LNdAsm_8: case ARM::VLD2LNdAsm_P8: case ARM::VLD2LNdAsm_I8: + case ARM::VLD2LNdAsm_S8: case ARM::VLD2LNdAsm_U8: case ARM::VLD2LNdAsm_16: case ARM::VLD2LNdAsm_P16: case ARM::VLD2LNdAsm_I16: case ARM::VLD2LNdAsm_S16: - case ARM::VLD2LNdAsm_U16: case ARM::VLD2LNdAsm_32: case ARM::VLD2LNdAsm_F: + case ARM::VLD2LNdAsm_U16: case ARM::VLD2LNdAsm_32: case ARM::VLD2LNdAsm_F: case ARM::VLD2LNdAsm_F32: case ARM::VLD2LNdAsm_I32: case ARM::VLD2LNdAsm_S32: - case ARM::VLD2LNdAsm_U32: { + case ARM::VLD2LNdAsm_U32: case ARM::VLD2LNqAsm_16: case ARM::VLD2LNqAsm_P16: + case ARM::VLD2LNqAsm_I16: case ARM::VLD2LNqAsm_S16: case ARM::VLD2LNqAsm_U16: + case ARM::VLD2LNqAsm_32: case ARM::VLD2LNqAsm_F: case ARM::VLD2LNqAsm_F32: + case ARM::VLD2LNqAsm_I32: case ARM::VLD2LNqAsm_S32: + case ARM::VLD2LNqAsm_U32: { MCInst TmpInst; // Shuffle the operands around so the lane index operand is in the // right place. - TmpInst.setOpcode(getRealVLDLNOpcode(Inst.getOpcode())); + unsigned Spacing; + TmpInst.setOpcode(getRealVLDLNOpcode(Inst.getOpcode(), Spacing)); TmpInst.addOperand(Inst.getOperand(0)); // Vd - TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg()+1)); + TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + + Spacing)); TmpInst.addOperand(Inst.getOperand(2)); // Rn TmpInst.addOperand(Inst.getOperand(3)); // alignment TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd) - TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg()+1)); + TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + + Spacing)); TmpInst.addOperand(Inst.getOperand(1)); // lane TmpInst.addOperand(Inst.getOperand(4)); // CondCode TmpInst.addOperand(Inst.getOperand(5)); Modified: llvm/trunk/test/MC/ARM/neon-vld-encoding.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/neon-vld-encoding.s?rev=146983&r1=146982&r2=146983&view=diff ============================================================================== --- llvm/trunk/test/MC/ARM/neon-vld-encoding.s (original) +++ llvm/trunk/test/MC/ARM/neon-vld-encoding.s Tue Dec 20 13:21:26 2011 @@ -230,8 +230,9 @@ vld2.8 {d16[1], d17[1]}, [r0, :16] vld2.16 {d16[1], d17[1]}, [r0, :32] vld2.32 {d16[1], d17[1]}, [r0] -@ vld2.16 {d17[1], d19[1]}, [r0] -@ vld2.32 {d17[0], d19[0]}, [r0, :64] + vld2.16 {d17[1], d19[1]}, [r0] + vld2.32 {d17[0], d19[0]}, [r0, :64] + vld2.32 {d17[0], d19[0]}, [r0, :64]! vld2.8 {d2[4], d3[4]}, [r2], r3 vld2.8 {d2[4], d3[4]}, [r2]! vld2.8 {d2[4], d3[4]}, [r2] @@ -239,8 +240,9 @@ @ CHECK: vld2.8 {d16[1], d17[1]}, [r0, :16] @ encoding: [0x3f,0x01,0xe0,0xf4] @ CHECK: vld2.16 {d16[1], d17[1]}, [r0, :32] @ encoding: [0x5f,0x05,0xe0,0xf4] @ CHECK: vld2.32 {d16[1], d17[1]}, [r0] @ encoding: [0x8f,0x09,0xe0,0xf4] -@ FIXME: vld2.16 {d17[1], d19[1]}, [r0] @ encoding: [0x6f,0x15,0xe0,0xf4] -@ FIXME: vld2.32 {d17[0], d19[0]}, [r0, :64] @ encoding: [0x5f,0x19,0xe0,0xf4] +@ CHECK: vld2.16 {d17[1], d19[1]}, [r0] @ encoding: [0x6f,0x15,0xe0,0xf4] +@ CHECK: vld2.32 {d17[0], d19[0]}, [r0, :64] @ encoding: [0x5f,0x19,0xe0,0xf4] +@ CHECK: vld2.32 {d17[0], d19[0]}, [r0, :64]! @ encoding: [0x5d,0x19,0xe0,0xf4] @ CHECK: vld2.8 {d2[4], d3[4]}, [r2], r3 @ encoding: [0x83,0x21,0xa2,0xf4] @ CHECK: vld2.8 {d2[4], d3[4]}, [r2]! @ encoding: [0x8d,0x21,0xa2,0xf4] @ CHECK: vld2.8 {d2[4], d3[4]}, [r2] @ encoding: [0x8f,0x21,0xa2,0xf4] From grosbach at apple.com Tue Dec 20 13:32:32 2011 From: grosbach at apple.com (Jim Grosbach) Date: Tue, 20 Dec 2011 11:32:32 -0800 Subject: [llvm-commits] [PATCH] MC ARM Thumb: fix incorrect relocation generation (PR11214) In-Reply-To: References: <000001ccbf1d$618f7490$24ae5db0$%beyls@arm.com> <57817466-3086-4652-85E2-4959AF23D81B@apple.com> Message-ID: <107270DB-89BE-4C71-9181-CF7FDD300E25@apple.com> Yeah, that's my guess. An assert(0 "unimplemented non-PLT call!") or something would have been better if that's the case exactly to prevent this sort of head-scratching. :) -Jim On Dec 20, 2011, at 11:21 AM, James Molloy wrote: > Yeah, I was confused about that too. > > I couldn't comprehend why that conditional was even there in the first place - an R_ARM_NONE relocation is *never* required for a call (it's a special no-op reloc). > > The only thing I could think of is that someone wanted to fix the relocation given to PLT entries and decided to keep the a broken behaviour for the default case, perhaps they had no knowledge about it. > ________________________________________ > From: llvm-commits-bounces at cs.uiuc.edu [llvm-commits-bounces at cs.uiuc.edu] On Behalf Of Jim Grosbach [grosbach at apple.com] > Sent: 20 December 2011 19:07 > To: Kristof Beyls > Cc: llvm-commits at cs.uiuc.edu > Subject: Re: [llvm-commits] [PATCH] MC ARM Thumb: fix incorrect relocation generation (PR11214) > > Someone with ELF knowledge should look at this. I'm a bit nervous about removing the conditional as it seems to imply that there's an different relocation that should be generated depending on the variant kind. > > -Jim > > On Dec 20, 2011, at 5:43 AM, Kristof Beyls wrote: > >> Hi, >> >> Please find a patch for fixing incorrect generation of relocation >> information on Thumb function calls. >> This should fix quite a few incorrect code generation problems in Thumb mode >> when using the integrated assembler. >> I believe this fixes PR11214 >> (http://www.llvm.org/bugs/show_bug.cgi?id=11214). >> >> Is this OK? >> >> Thanks, >> >> Kristof >> _______________________________________________ >> llvm-commits mailing list >> llvm-commits at cs.uiuc.edu >> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits > > > -- IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you. > From dpatel at apple.com Tue Dec 20 13:29:36 2011 From: dpatel at apple.com (Devang Patel) Date: Tue, 20 Dec 2011 19:29:36 -0000 Subject: [llvm-commits] [llvm] r146984 - in /llvm/trunk: include/llvm-c/Core.h lib/VMCore/Core.cpp Message-ID: <20111220192936.78B242A6C12C@llvm.org> Author: dpatel Date: Tue Dec 20 13:29:36 2011 New Revision: 146984 URL: http://llvm.org/viewvc/llvm-project?rev=146984&view=rev Log: Add support to add named metadata operand. Patch by Andrew Wilkins! Modified: llvm/trunk/include/llvm-c/Core.h llvm/trunk/lib/VMCore/Core.cpp Modified: llvm/trunk/include/llvm-c/Core.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm-c/Core.h?rev=146984&r1=146983&r2=146984&view=diff ============================================================================== --- llvm/trunk/include/llvm-c/Core.h (original) +++ llvm/trunk/include/llvm-c/Core.h Tue Dec 20 13:29:36 2011 @@ -567,6 +567,8 @@ const char *LLVMGetMDString(LLVMValueRef V, unsigned* Len); unsigned LLVMGetNamedMetadataNumOperands(LLVMModuleRef M, const char* name); void LLVMGetNamedMetadataOperands(LLVMModuleRef M, const char* name, LLVMValueRef *Dest); +void LLVMAddNamedMetadataOperand(LLVMModuleRef M, const char* name, + LLVMValueRef Val); /* Operations on scalar constants */ LLVMValueRef LLVMConstInt(LLVMTypeRef IntTy, unsigned long long N, Modified: llvm/trunk/lib/VMCore/Core.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/Core.cpp?rev=146984&r1=146983&r2=146984&view=diff ============================================================================== --- llvm/trunk/lib/VMCore/Core.cpp (original) +++ llvm/trunk/lib/VMCore/Core.cpp Tue Dec 20 13:29:36 2011 @@ -566,6 +566,17 @@ Dest[i] = wrap(N->getOperand(i)); } +void LLVMAddNamedMetadataOperand(LLVMModuleRef M, const char* name, + LLVMValueRef Val) +{ + NamedMDNode *N = unwrap(M)->getOrInsertNamedMetadata(name); + if (!N) + return; + MDNode *Op = Val ? unwrap(Val) : NULL; + if (Op) + N->addOperand(Op); +} + /*--.. Operations on scalar constants ......................................--*/ LLVMValueRef LLVMConstInt(LLVMTypeRef IntTy, unsigned long long N, From dpatel at apple.com Tue Dec 20 13:33:10 2011 From: dpatel at apple.com (Devang Patel) Date: Tue, 20 Dec 2011 11:33:10 -0800 Subject: [llvm-commits] [PATCH] Extend named metadata support in the LLVM C API In-Reply-To: References:

Message-ID: <4661010B-7543-441D-86F7-57E95C9A0E08@apple.com> On Dec 20, 2011, at 6:56 AM, Andrew Wilkins wrote: > On Tue, Dec 20, 2011 at 2:06 AM, Devang Patel wrote: > We want to preserve backward compatibility in C API as much as possible. So we don't want to remove LLVMGetNamedMetadataOperands or change signature of LLVMGetNamedMetadataNumOperands. > > Thanks for the feedback. Fair enough. Attached is a more conservative patch, just adding one new function LLVMAddNamedMetadataOperand. Looks good. I applied your patch r146984. - Devang > > Regards, > -- > Andrew Wilkins > http://awilkins.id.au > > -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20111220/7f5a9d2f/attachment.html From ahatanak at gmail.com Tue Dec 20 13:39:08 2011 From: ahatanak at gmail.com (Akira Hatanaka) Date: Tue, 20 Dec 2011 11:39:08 -0800 Subject: [llvm-commits] [llvm] r146604 - in /llvm/trunk: lib/CodeGen/MachineSink.cpp test/CodeGen/ARM/2011-12-14-machine-sink.ll In-Reply-To: <618FAA67-0A0A-4D20-9E58-491632F2BA7C@apple.com> References: <20111214232038.E9C9D2A6C12C@llvm.org> <5FF21D31-13D7-4EAA-99FC-EFC1AFA0C8F7@apple.com> <618FAA67-0A0A-4D20-9E58-491632F2BA7C@apple.com> Message-ID: After further investigation, I found a function that is possibly being mis-compiled. This is what I did: 1. Reverted this patch (machine sinking is less conservative now). 2. Turned off machine sinking just for the function. The generated executable segfaults when it is run. Additionally, I found that it produces the expected result and terminates normally if I add the option "-regalloc=basic" to llc to turn off greedy register allocation. Is there anything you can tell from this? Which part of the output should I pay attention to when I am reading llc's outputs when option -debug or -stats is provided? The function in question is fairly large and complicated, so it is difficult to tell which part is being mis-compiled just by looking at the machinefunction dumps or the CFGs viewCFG and viewCFGOnly show. On Fri, Dec 16, 2011 at 3:50 PM, Devang Patel wrote: > > On Dec 16, 2011, at 2:34 PM, Akira Hatanaka wrote: > >> The test still fails after I disable Machine Sink pass, but it passes >> if I revert the patch (just this one, the ones checked in after this >> remain applied). So it looks like MachineSinking is not causing the >> failure, but there is a bug in some other part of the backend that >> gets exposed if the pass doesn't sink instructions at all or is less >> aggresive. >> >> Do you have any idea which pass might be doing something wrong? > > > In the test case, which prompted this patch, machine sink pass was ?increasing distance between reg def and use resulting in unnecessary extra spill. > > However, in your particular case I have no idea what is going wrong. Finding out what exactly is miscompiled may be your best alternative. Do you see any significant (or noticeable) changes in stats for passes that follow machine sink ? >> >> Here are the stats: >> >> (before) >> 15 machine-sink ? ? ?- Number of copies coalesced >> 674 machine-sink ? ? ?- Number of critical edges split >> 3397 machine-sink ? ? ?- Number of machine instructions sunk >> >> (after) >> 15 machine-sink ? ? ?- Number of copies coalesced >> 674 machine-sink ? ? ?- Number of critical edges split >> 2881 machine-sink ? ? ?- Number of machine instructions sunk >> >> On Fri, Dec 16, 2011 at 9:21 AM, Devang Patel wrote: >>> >>> On Dec 15, 2011, at 7:55 PM, Akira Hatanaka wrote: >>> >>>> This commit is causing one the tests in llvm test-suite >>>> (MultiSource/Benchmarks/tramp3d-v4) to fail. >>>> It segfaults during execution. The target architecture is mips32r2. >>>> >>>> Would it be possible to revert this until we can figure out what is >>>> causing the failure? >>> >>> This patch makes machine sink more conservative. Please, >>> >>> 1) Disable Machine Sink pass completely locally and see if the segfaults reproduces or not. >>> 2) Enable stats and see if notice any change before and after the patch. >>> 3) Please file bugzilla with a reproducible test case before reverting the patch. >>> >>> Thanks, >>> - >>> Devang >>> >>> >>>> On Wed, Dec 14, 2011 at 3:20 PM, Devang Patel wrote: >>>>> Author: dpatel >>>>> Date: Wed Dec 14 17:20:38 2011 >>>>> New Revision: 146604 >>>>> >>>>> URL: http://llvm.org/viewvc/llvm-project?rev=146604&view=rev >>>>> Log: >>>>> Do not sink instruction, if it is not profitable. >>>>> >>>>> On ARM, peephole optimization for ABS creates a trivial cfg triangle which tempts machine sink to sink instructions in code which is really straight line code. Sometimes this sinking may alter register allocator input such that use and def of a reg is divided by a branch in between, which may result in extra spills. Now mahine sink avoids sinking if final sink destination is post dominator. >>>>> >>>>> Radar 10266272. >>>>> >>>>> Added: >>>>> ? ?llvm/trunk/test/CodeGen/ARM/2011-12-14-machine-sink.ll >>>>> Modified: >>>>> ? ?llvm/trunk/lib/CodeGen/MachineSink.cpp >>>>> >>>>> Modified: llvm/trunk/lib/CodeGen/MachineSink.cpp >>>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineSink.cpp?rev=146604&r1=146603&r2=146604&view=diff >>>>> ============================================================================== >>>>> --- llvm/trunk/lib/CodeGen/MachineSink.cpp (original) >>>>> +++ llvm/trunk/lib/CodeGen/MachineSink.cpp Wed Dec 14 17:20:38 2011 >>>>> @@ -90,7 +90,11 @@ >>>>> ? ? bool AllUsesDominatedByBlock(unsigned Reg, MachineBasicBlock *MBB, >>>>> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?MachineBasicBlock *DefMBB, >>>>> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?bool &BreakPHIEdge, bool &LocalUse) const; >>>>> - ? ?MachineBasicBlock *FindSuccToSinkTo(MachineInstr *MI, bool &BreakPHIEdge); >>>>> + ? ?MachineBasicBlock *FindSuccToSinkTo(MachineInstr *MI, MachineBasicBlock *MBB, >>>>> + ? ? ? ? ? ? ? bool &BreakPHIEdge); >>>>> + ? ?bool isProfitableToSinkTo(unsigned Reg, MachineInstr *MI, >>>>> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?MachineBasicBlock *MBB, >>>>> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?MachineBasicBlock *SuccToSinkTo); >>>>> >>>>> ? ? bool PerformTrivialForwardCoalescing(MachineInstr *MI, >>>>> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?MachineBasicBlock *MBB); >>>>> @@ -399,18 +403,76 @@ >>>>> ? } >>>>> ?} >>>>> >>>>> +/// isPostDominatedBy - Return true if A is post dominated by B. >>>>> +static bool isPostDominatedBy(MachineBasicBlock *A, MachineBasicBlock *B) { >>>>> + >>>>> + ?// FIXME - Use real post dominator. >>>>> + ?if (A->succ_size() != 2) >>>>> + ? ?return false; >>>>> + ?MachineBasicBlock::succ_iterator I = A->succ_begin(); >>>>> + ?if (B == *I) >>>>> + ? ?++I; >>>>> + ?MachineBasicBlock *OtherSuccBlock = *I; >>>>> + ?if (OtherSuccBlock->succ_size() != 1 || >>>>> + ? ? ?*(OtherSuccBlock->succ_begin()) != B) >>>>> + ? ?return false; >>>>> + >>>>> + ?return true; >>>>> +} >>>>> + >>>>> +/// isProfitableToSinkTo - Return true if it is profitable to sink MI. >>>>> +bool MachineSinking::isProfitableToSinkTo(unsigned Reg, MachineInstr *MI, >>>>> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?MachineBasicBlock *MBB, >>>>> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?MachineBasicBlock *SuccToSinkTo) { >>>>> + ?assert (MI && "Invalid MachineInstr!"); >>>>> + ?assert (SuccToSinkTo && "Invalid SinkTo Candidate BB"); >>>>> + >>>>> + ?if (MBB == SuccToSinkTo) >>>>> + ? ?return false; >>>>> + >>>>> + ?// It is profitable if SuccToSinkTo does not post dominate current block. >>>>> + ?if (!isPostDominatedBy(MBB, SuccToSinkTo)) >>>>> + ? ? ?return true; >>>>> + >>>>> + ?// Check if only use in post dominated block is PHI instruction. >>>>> + ?bool NonPHIUse = false; >>>>> + ?for (MachineRegisterInfo::use_nodbg_iterator >>>>> + ? ? ? ? I = MRI->use_nodbg_begin(Reg), E = MRI->use_nodbg_end(); >>>>> + ? ? ? I != E; ++I) { >>>>> + ? ?MachineInstr *UseInst = &*I; >>>>> + ? ?MachineBasicBlock *UseBlock = UseInst->getParent(); >>>>> + ? ?if (UseBlock == SuccToSinkTo && !UseInst->isPHI()) >>>>> + ? ? ?NonPHIUse = true; >>>>> + ?} >>>>> + ?if (!NonPHIUse) >>>>> + ? ?return true; >>>>> + >>>>> + ?// If SuccToSinkTo post dominates then also it may be profitable if MI >>>>> + ?// can further profitably sinked into another block in next round. >>>>> + ?bool BreakPHIEdge = false; >>>>> + ?// FIXME - If finding successor is compile time expensive then catch results. >>>>> + ?if (MachineBasicBlock *MBB2 = FindSuccToSinkTo(MI, SuccToSinkTo, BreakPHIEdge)) >>>>> + ? ?return isProfitableToSinkTo(Reg, MI, SuccToSinkTo, MBB2); >>>>> + >>>>> + ?// If SuccToSinkTo is final destination and it is a post dominator of current >>>>> + ?// block then it is not profitable to sink MI into SuccToSinkTo block. >>>>> + ?return false; >>>>> +} >>>>> + >>>>> ?/// FindSuccToSinkTo - Find a successor to sink this instruction to. >>>>> ?MachineBasicBlock *MachineSinking::FindSuccToSinkTo(MachineInstr *MI, >>>>> - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? bool &BreakPHIEdge) { >>>>> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? MachineBasicBlock *MBB, >>>>> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? bool &BreakPHIEdge) { >>>>> + >>>>> + ?assert (MI && "Invalid MachineInstr!"); >>>>> + ?assert (MBB && "Invalid MachineBasicBlock!"); >>>>> >>>>> ? // Loop over all the operands of the specified instruction. ?If there is >>>>> ? // anything we can't handle, bail out. >>>>> - ?MachineBasicBlock *ParentBlock = MI->getParent(); >>>>> >>>>> ? // SuccToSinkTo - This is the successor to sink this instruction to, once we >>>>> ? // decide. >>>>> ? MachineBasicBlock *SuccToSinkTo = 0; >>>>> - >>>>> ? for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { >>>>> ? ? const MachineOperand &MO = MI->getOperand(i); >>>>> ? ? if (!MO.isReg()) continue; ?// Ignore non-register operands. >>>>> @@ -469,7 +531,7 @@ >>>>> ? ? ? ? // If a previous operand picked a block to sink to, then this operand >>>>> ? ? ? ? // must be sinkable to the same block. >>>>> ? ? ? ? bool LocalUse = false; >>>>> - ? ? ? ?if (!AllUsesDominatedByBlock(Reg, SuccToSinkTo, ParentBlock, >>>>> + ? ? ? ?if (!AllUsesDominatedByBlock(Reg, SuccToSinkTo, MBB, >>>>> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?BreakPHIEdge, LocalUse)) >>>>> ? ? ? ? ? return NULL; >>>>> >>>>> @@ -478,11 +540,11 @@ >>>>> >>>>> ? ? ? // Otherwise, we should look at all the successors and decide which one >>>>> ? ? ? // we should sink to. >>>>> - ? ? ?for (MachineBasicBlock::succ_iterator SI = ParentBlock->succ_begin(), >>>>> - ? ? ? ? ? E = ParentBlock->succ_end(); SI != E; ++SI) { >>>>> - ? ? ? MachineBasicBlock *SuccBlock = *SI; >>>>> + ? ? ?for (MachineBasicBlock::succ_iterator SI = MBB->succ_begin(), >>>>> + ? ? ? ? ? E = MBB->succ_end(); SI != E; ++SI) { >>>>> + ? ? ? ?MachineBasicBlock *SuccBlock = *SI; >>>>> ? ? ? ? bool LocalUse = false; >>>>> - ? ? ? ?if (AllUsesDominatedByBlock(Reg, SuccBlock, ParentBlock, >>>>> + ? ? ? ?if (AllUsesDominatedByBlock(Reg, SuccBlock, MBB, >>>>> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? BreakPHIEdge, LocalUse)) { >>>>> ? ? ? ? ? SuccToSinkTo = SuccBlock; >>>>> ? ? ? ? ? break; >>>>> @@ -495,12 +557,14 @@ >>>>> ? ? ? // If we couldn't find a block to sink to, ignore this instruction. >>>>> ? ? ? if (SuccToSinkTo == 0) >>>>> ? ? ? ? return NULL; >>>>> + ? ? ?else if (!isProfitableToSinkTo(Reg, MI, MBB, SuccToSinkTo)) >>>>> + ? ? ? ?return NULL; >>>>> ? ? } >>>>> ? } >>>>> >>>>> ? // It is not possible to sink an instruction into its own block. ?This can >>>>> ? // happen with loops. >>>>> - ?if (ParentBlock == SuccToSinkTo) >>>>> + ?if (MBB == SuccToSinkTo) >>>>> ? ? return NULL; >>>>> >>>>> ? // It's not safe to sink instructions to EH landing pad. Control flow into >>>>> @@ -532,7 +596,8 @@ >>>>> ? // and z and only shrink the live range of x. >>>>> >>>>> ? bool BreakPHIEdge = false; >>>>> - ?MachineBasicBlock *SuccToSinkTo = FindSuccToSinkTo(MI, BreakPHIEdge); >>>>> + ?MachineBasicBlock *ParentBlock = MI->getParent(); >>>>> + ?MachineBasicBlock *SuccToSinkTo = FindSuccToSinkTo(MI, ParentBlock, BreakPHIEdge); >>>>> >>>>> ? // If there are no outputs, it must have side-effects. >>>>> ? if (SuccToSinkTo == 0) >>>>> @@ -553,8 +618,6 @@ >>>>> >>>>> ? DEBUG(dbgs() << "Sink instr " << *MI << "\tinto block " << *SuccToSinkTo); >>>>> >>>>> - ?MachineBasicBlock *ParentBlock = MI->getParent(); >>>>> - >>>>> ? // If the block has multiple predecessors, this would introduce computation on >>>>> ? // a path that it doesn't already exist. ?We could split the critical edge, >>>>> ? // but for now we just punt. >>>>> >>>>> Added: llvm/trunk/test/CodeGen/ARM/2011-12-14-machine-sink.ll >>>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/2011-12-14-machine-sink.ll?rev=146604&view=auto >>>>> ============================================================================== >>>>> --- llvm/trunk/test/CodeGen/ARM/2011-12-14-machine-sink.ll (added) >>>>> +++ llvm/trunk/test/CodeGen/ARM/2011-12-14-machine-sink.ll Wed Dec 14 17:20:38 2011 >>>>> @@ -0,0 +1,48 @@ >>>>> +; RUN: llc < %s -o /dev/null -stats |& FileCheck %s -check-prefix=STATS >>>>> +; Radar 10266272 >>>>> +target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:32:64-v128:32:128-a0:0:32-n32-S32" >>>>> +target triple = "thumbv7-apple-ios4.0.0" >>>>> +; STATS-NOT: machine-sink >>>>> + >>>>> +define i32 @foo(i32 %h) nounwind readonly ssp { >>>>> +entry: >>>>> + ?br label %for.cond >>>>> + >>>>> +for.cond: ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ; preds = %for.body, %entry >>>>> + ?%cmp = icmp slt i32 0, %h >>>>> + ?br i1 %cmp, label %for.body, label %if.end299 >>>>> + >>>>> +for.body: ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ; preds = %for.cond >>>>> + ?%v.5 = select i1 undef, i32 undef, i32 0 >>>>> + ?%0 = load i8* undef, align 1, !tbaa !0 >>>>> + ?%conv88 = zext i8 %0 to i32 >>>>> + ?%sub89 = sub nsw i32 0, %conv88 >>>>> + ?%v.8 = select i1 undef, i32 undef, i32 %sub89 >>>>> + ?%1 = load i8* null, align 1, !tbaa !0 >>>>> + ?%conv108 = zext i8 %1 to i32 >>>>> + ?%2 = load i8* undef, align 1, !tbaa !0 >>>>> + ?%conv110 = zext i8 %2 to i32 >>>>> + ?%sub111 = sub nsw i32 %conv108, %conv110 >>>>> + ?%cmp112 = icmp slt i32 %sub111, 0 >>>>> + ?%sub115 = sub nsw i32 0, %sub111 >>>>> + ?%v.10 = select i1 %cmp112, i32 %sub115, i32 %sub111 >>>>> + ?%add62 = add i32 0, %v.5 >>>>> + ?%add73 = add i32 %add62, 0 >>>>> + ?%add84 = add i32 %add73, 0 >>>>> + ?%add95 = add i32 %add84, %v.8 >>>>> + ?%add106 = add i32 %add95, 0 >>>>> + ?%add117 = add i32 %add106, %v.10 >>>>> + ?%add128 = add i32 %add117, 0 >>>>> + ?%add139 = add i32 %add128, 0 >>>>> + ?%add150 = add i32 %add139, 0 >>>>> + ?%add161 = add i32 %add150, 0 >>>>> + ?%add172 = add i32 %add161, 0 >>>>> + ?br i1 undef, label %for.cond, label %if.end299 >>>>> + >>>>> +if.end299: ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?; preds = %for.body, %for.cond >>>>> + ?%s.10 = phi i32 [ %add172, %for.body ], [ 0, %for.cond ] >>>>> + ?ret i32 %s.10 >>>>> +} >>>>> + >>>>> +!0 = metadata !{metadata !"omnipotent char", metadata !1} >>>>> +!1 = metadata !{metadata !"Simple C/C++ TBAA", null} >>>>> >>>>> >>>>> _______________________________________________ >>>>> llvm-commits mailing list >>>>> llvm-commits at cs.uiuc.edu >>>>> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits >>> > From spop at codeaurora.org Tue Dec 20 13:57:05 2011 From: spop at codeaurora.org (Sebastian Pop) Date: Tue, 20 Dec 2011 13:57:05 -0600 Subject: [llvm-commits] [LLVMdev] [PATCH] BasicBlock Autovectorization Pass In-Reply-To: <1323822351.590.1687.camel@sapling> References: <1319909412.23036.851.camel@sapling> <1319914924.23036.852.camel@sapling> <1319919418.23036.881.camel@sapling> <1319928991.23036.957.camel@sapling> <1320108633.23036.1266.camel@sapling> <1320172356.23036.1298.camel@sapling> <4EB0462C.5010209@grosser.es> <1320184739.23036.1334.camel@sapling> <1320191694.23036.1497.camel@sapling> <1320749109.19359.76.camel@sapling> <4EB90E98.4010805@grosser.es> <1320762963.19359.117.camel@sapling> <4EB98207.2070807@grosser.es> <1320791390.19359.262.camel@sapling> <4EBC4B0F.6010609@grosser.es> <1321050998.19359.539.camel@sapling> <4EBDA7F9.9080709@grosser.es> <1321053083.19359.550.camel@sapling> <4EBDB1BF.7090006@grosser.es> <1321400339.19359.782.camel@sapling> <1321486739.19359.1067.camel@sapling> <4EC504B5.2020408@grosser.es> <1321898108.2507.36.camel@sapling> <1321932161.2507.101.camel@sapling> <1322067157.2507.263.camel@sapling> <4ED8F7B0.8050309@grosser.es> <1323822351.590.1687.camel@sapling> Message-ID: Hi, I see that there are two functions in your code that are O(n^2) in number of instructions of the program: getCandidatePairs and buildDepMap. I think that you could make these two functions faster if you work on some form of factored def-use chains for memory, like the VUSE/VDEFs of GCC. I was trying to find a similar representation in LLVM: isn't there already a virtual SSA representation for memory references in LLVM? Thanks, Sebastian -- Qualcomm Innovation Center, Inc is a member of Code Aurora Forum From grosbach at apple.com Tue Dec 20 14:03:00 2011 From: grosbach at apple.com (Jim Grosbach) Date: Tue, 20 Dec 2011 20:03:00 -0000 Subject: [llvm-commits] [llvm] r146985 - /llvm/trunk/test/MC/ARM/neon-vst-encoding.s Message-ID: <20111220200300.9EBB92A6C12C@llvm.org> Author: grosbach Date: Tue Dec 20 14:03:00 2011 New Revision: 146985 URL: http://llvm.org/viewvc/llvm-project?rev=146985&view=rev Log: ARM enable a few more tests. Modified: llvm/trunk/test/MC/ARM/neon-vst-encoding.s Modified: llvm/trunk/test/MC/ARM/neon-vst-encoding.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/neon-vst-encoding.s?rev=146985&r1=146984&r2=146985&view=diff ============================================================================== --- llvm/trunk/test/MC/ARM/neon-vst-encoding.s (original) +++ llvm/trunk/test/MC/ARM/neon-vst-encoding.s Tue Dec 20 14:03:00 2011 @@ -98,8 +98,8 @@ @ FIXME: vst4.32 {d17, d19, d21, d23}, [r0]! @ encoding: [0x8d,0x11,0x40,0xf4] -@ vst2.8 {d16[1], d17[1]}, [r0, :16] -@ vst2.16 {d16[1], d17[1]}, [r0, :32] + vst2.8 {d16[1], d17[1]}, [r0, :16] + vst2.16 {d16[1], d17[1]}, [r0, :32] vst2.32 {d16[1], d17[1]}, [r0] @ vst2.16 {d17[1], d19[1]}, [r0] @ vst2.32 {d17[0], d19[0]}, [r0, :64] @@ -108,8 +108,8 @@ vst2.8 {d2[4], d3[4]}, [r2]! vst2.8 {d2[4], d3[4]}, [r2] -@ FIXME: vst2.8 {d16[1], d17[1]}, [r0, :16] @ encoding: [0x3f,0x01,0xc0,0xf4] -@ FIXME: vst2.16 {d16[1], d17[1]}, [r0, :32] @ encoding: [0x5f,0x05,0xc0,0xf4] +@ CHECK: vst2.8 {d16[1], d17[1]}, [r0, :16] @ encoding: [0x3f,0x01,0xc0,0xf4] +@ CHECK: vst2.16 {d16[1], d17[1]}, [r0, :32] @ encoding: [0x5f,0x05,0xc0,0xf4] @ CHECK: vst2.32 {d16[1], d17[1]}, [r0] @ encoding: [0x8f,0x09,0xc0,0xf4] @ FIXME: vst2.16 {d17[1], d19[1]}, [r0] @ encoding: [0x6f,0x15,0xc0,0xf4] @ FIXME: vst2.32 {d17[0], d19[0]}, [r0, :64] @ encoding: [0x5f,0x19,0xc0,0xf4] From Kristof.Beyls at arm.com Tue Dec 20 14:06:19 2011 From: Kristof.Beyls at arm.com (Kristof Beyls) Date: Tue, 20 Dec 2011 20:06:19 +0000 Subject: [llvm-commits] [PATCH] MC ARM Thumb: fix incorrect relocation generation (PR11214) In-Reply-To: <107270DB-89BE-4C71-9181-CF7FDD300E25@apple.com> References: <000001ccbf1d$618f7490$24ae5db0$%beyls@arm.com> <57817466-3086-4652-85E2-4959AF23D81B@apple.com> <107270DB-89BE-4C71-9181-CF7FDD300E25@apple.com> Message-ID: The reason why I thought the patch would be OK is that the patch only changes the behaviour for the thumb bl and blx instructions (i.e. only for the cases ARM::fixup_arm_thumb_bl and ARM::fixup_arm_thumb_blx. For these instructions, I can't see why R_ARM_NONE would ever be the correct relocation type. The definition of R_ARM_NONE from the AAELF ABI: """ R_ARM_NONE records that the section containing the place to be relocated depends on the section defining the symbol mentioned in the relocation directive in a way otherwise invisible to the static linker. The effect is to prevent removal of sections that might otherwise appear to be unused. """ Thanks, Kristof > -----Original Message----- > From: Jim Grosbach [mailto:grosbach at apple.com] > Sent: 20 December 2011 19:33 > To: James Molloy > Cc: Kristof Beyls; llvm-commits at cs.uiuc.edu > Subject: Re: [llvm-commits] [PATCH] MC ARM Thumb: fix incorrect > relocation generation (PR11214) > > Yeah, that's my guess. An assert(0 "unimplemented non-PLT call!") or > something would have been better if that's the case exactly to prevent > this sort of head-scratching. :) > > -Jim > > On Dec 20, 2011, at 11:21 AM, James Molloy wrote: > > > Yeah, I was confused about that too. > > > > I couldn't comprehend why that conditional was even there in the > first place - an R_ARM_NONE relocation is *never* required for a call > (it's a special no-op reloc). > > > > The only thing I could think of is that someone wanted to fix the > relocation given to PLT entries and decided to keep the a broken > behaviour for the default case, perhaps they had no knowledge about it. > > ________________________________________ > > From: llvm-commits-bounces at cs.uiuc.edu [llvm-commits- > bounces at cs.uiuc.edu] On Behalf Of Jim Grosbach [grosbach at apple.com] > > Sent: 20 December 2011 19:07 > > To: Kristof Beyls > > Cc: llvm-commits at cs.uiuc.edu > > Subject: Re: [llvm-commits] [PATCH] MC ARM Thumb: fix incorrect > relocation generation (PR11214) > > > > Someone with ELF knowledge should look at this. I'm a bit nervous > about removing the conditional as it seems to imply that there's an > different relocation that should be generated depending on the variant > kind. > > > > -Jim > > > > On Dec 20, 2011, at 5:43 AM, Kristof Beyls wrote: > > > >> Hi, > >> > >> Please find a patch for fixing incorrect generation of relocation > >> information on Thumb function calls. > >> This should fix quite a few incorrect code generation problems in > Thumb mode > >> when using the integrated assembler. > >> I believe this fixes PR11214 > >> (http://www.llvm.org/bugs/show_bug.cgi?id=11214). > >> > >> Is this OK? > >> > >> Thanks, > >> > >> Kristof > >> > ____________________________________________ > ___ > >> llvm-commits mailing list > >> llvm-commits at cs.uiuc.edu > >> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits > > > > _______________________________________________ > > llvm-commits mailing list > > llvm-commits at cs.uiuc.edu > > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits > > > > > > -- IMPORTANT NOTICE: The contents of this email and any attachments > are confidential and may also be privileged. If you are not the > intended recipient, please notify the sender immediately and do not > disclose the contents to any other person, use it for any purpose, or > store or copy the information in any medium. Thank you. > > > > -- IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you. From kubastaszak at gmail.com Tue Dec 20 14:03:11 2011 From: kubastaszak at gmail.com (Jakub Staszak) Date: Tue, 20 Dec 2011 20:03:11 -0000 Subject: [llvm-commits] [llvm] r146986 - in /llvm/trunk: include/llvm/Analysis/ include/llvm/CodeGen/ lib/Analysis/ lib/CodeGen/ lib/CodeGen/SelectionDAG/ Message-ID: <20111220200311.347CC2A6C12C@llvm.org> Author: kuba Date: Tue Dec 20 14:03:10 2011 New Revision: 146986 URL: http://llvm.org/viewvc/llvm-project?rev=146986&view=rev Log: Add some constantness to BranchProbabilityInfo and BlockFrequnencyInfo. Modified: llvm/trunk/include/llvm/Analysis/BlockFrequencyImpl.h llvm/trunk/include/llvm/Analysis/BlockFrequencyInfo.h llvm/trunk/include/llvm/CodeGen/MachineBasicBlock.h llvm/trunk/include/llvm/CodeGen/MachineBlockFrequencyInfo.h llvm/trunk/include/llvm/CodeGen/MachineBranchProbabilityInfo.h llvm/trunk/lib/Analysis/BlockFrequencyInfo.cpp llvm/trunk/lib/CodeGen/MachineBasicBlock.cpp llvm/trunk/lib/CodeGen/MachineBlockFrequencyInfo.cpp llvm/trunk/lib/CodeGen/MachineBranchProbabilityInfo.cpp llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.h Modified: llvm/trunk/include/llvm/Analysis/BlockFrequencyImpl.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Analysis/BlockFrequencyImpl.h?rev=146986&r1=146985&r2=146986&view=diff ============================================================================== --- llvm/trunk/include/llvm/Analysis/BlockFrequencyImpl.h (original) +++ llvm/trunk/include/llvm/Analysis/BlockFrequencyImpl.h Tue Dec 20 14:03:10 2011 @@ -40,7 +40,7 @@ template class BlockFrequencyImpl { - DenseMap Freqs; + DenseMap Freqs; BlockProbInfoT *BPI; @@ -308,8 +308,9 @@ public: /// getBlockFreq - Return block frequency. Return 0 if we don't have it. - BlockFrequency getBlockFreq(BlockT *BB) const { - typename DenseMap::const_iterator I = Freqs.find(BB); + BlockFrequency getBlockFreq(const BlockT *BB) const { + typename DenseMap::const_iterator + I = Freqs.find(BB); if (I != Freqs.end()) return I->second; return 0; Modified: llvm/trunk/include/llvm/Analysis/BlockFrequencyInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Analysis/BlockFrequencyInfo.h?rev=146986&r1=146985&r2=146986&view=diff ============================================================================== --- llvm/trunk/include/llvm/Analysis/BlockFrequencyInfo.h (original) +++ llvm/trunk/include/llvm/Analysis/BlockFrequencyInfo.h Tue Dec 20 14:03:10 2011 @@ -47,7 +47,7 @@ /// that we should not rely on the value itself, but only on the comparison to /// the other block frequencies. We do this to avoid using of floating points. /// - BlockFrequency getBlockFreq(BasicBlock *BB) const; + BlockFrequency getBlockFreq(const BasicBlock *BB) const; }; } Modified: llvm/trunk/include/llvm/CodeGen/MachineBasicBlock.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/MachineBasicBlock.h?rev=146986&r1=146985&r2=146986&view=diff ============================================================================== --- llvm/trunk/include/llvm/CodeGen/MachineBasicBlock.h (original) +++ llvm/trunk/include/llvm/CodeGen/MachineBasicBlock.h Tue Dec 20 14:03:10 2011 @@ -77,6 +77,7 @@ /// (disable optimization). std::vector Weights; typedef std::vector::iterator weight_iterator; + typedef std::vector::const_iterator const_weight_iterator; /// LiveIns - Keep track of the physical registers that are livein of /// the basicblock. @@ -589,13 +590,14 @@ /// getWeightIterator - Return weight iterator corresponding to the I /// successor iterator. weight_iterator getWeightIterator(succ_iterator I); + const_weight_iterator getWeightIterator(const_succ_iterator I) const; friend class MachineBranchProbabilityInfo; /// getSuccWeight - Return weight of the edge from this block to MBB. This /// method should NOT be called directly, but by using getEdgeWeight method /// from MachineBranchProbabilityInfo class. - uint32_t getSuccWeight(MachineBasicBlock *succ); + uint32_t getSuccWeight(const MachineBasicBlock *succ) const; // Methods used to maintain doubly linked list of blocks... Modified: llvm/trunk/include/llvm/CodeGen/MachineBlockFrequencyInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/MachineBlockFrequencyInfo.h?rev=146986&r1=146985&r2=146986&view=diff ============================================================================== --- llvm/trunk/include/llvm/CodeGen/MachineBlockFrequencyInfo.h (original) +++ llvm/trunk/include/llvm/CodeGen/MachineBlockFrequencyInfo.h Tue Dec 20 14:03:10 2011 @@ -48,7 +48,7 @@ /// that we should not rely on the value itself, but only on the comparison to /// the other block frequencies. We do this to avoid using of floating points. /// - BlockFrequency getBlockFreq(MachineBasicBlock *MBB) const; + BlockFrequency getBlockFreq(const MachineBasicBlock *MBB) const; }; } Modified: llvm/trunk/include/llvm/CodeGen/MachineBranchProbabilityInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/MachineBranchProbabilityInfo.h?rev=146986&r1=146985&r2=146986&view=diff ============================================================================== --- llvm/trunk/include/llvm/CodeGen/MachineBranchProbabilityInfo.h (original) +++ llvm/trunk/include/llvm/CodeGen/MachineBranchProbabilityInfo.h Tue Dec 20 14:03:10 2011 @@ -49,12 +49,13 @@ // Return edge weight. If we don't have any informations about it - return // DEFAULT_WEIGHT. - uint32_t getEdgeWeight(MachineBasicBlock *Src, MachineBasicBlock *Dst) const; + uint32_t getEdgeWeight(const MachineBasicBlock *Src, + const MachineBasicBlock *Dst) const; // Get sum of the block successors' weights, potentially scaling them to fit // within 32-bits. If scaling is required, sets Scale based on the necessary // adjustment. Any edge weights used with the sum should be divided by Scale. - uint32_t getSumForBlock(MachineBasicBlock *MBB, uint32_t &Scale) const; + uint32_t getSumForBlock(const MachineBasicBlock *MBB, uint32_t &Scale) const; // A 'Hot' edge is an edge which probability is >= 80%. bool isEdgeHot(MachineBasicBlock *Src, MachineBasicBlock *Dst) const; Modified: llvm/trunk/lib/Analysis/BlockFrequencyInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/BlockFrequencyInfo.cpp?rev=146986&r1=146985&r2=146986&view=diff ============================================================================== --- llvm/trunk/lib/Analysis/BlockFrequencyInfo.cpp (original) +++ llvm/trunk/lib/Analysis/BlockFrequencyInfo.cpp Tue Dec 20 14:03:10 2011 @@ -58,6 +58,6 @@ /// that we should not rely on the value itself, but only on the comparison to /// the other block frequencies. We do this to avoid using of floating points. /// -BlockFrequency BlockFrequencyInfo::getBlockFreq(BasicBlock *BB) const { +BlockFrequency BlockFrequencyInfo::getBlockFreq(const BasicBlock *BB) const { return BFI->getBlockFreq(BB); } Modified: llvm/trunk/lib/CodeGen/MachineBasicBlock.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineBasicBlock.cpp?rev=146986&r1=146985&r2=146986&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/MachineBasicBlock.cpp (original) +++ llvm/trunk/lib/CodeGen/MachineBasicBlock.cpp Tue Dec 20 14:03:10 2011 @@ -870,11 +870,11 @@ /// getSuccWeight - Return weight of the edge from this block to MBB. /// -uint32_t MachineBasicBlock::getSuccWeight(MachineBasicBlock *succ) { +uint32_t MachineBasicBlock::getSuccWeight(const MachineBasicBlock *succ) const { if (Weights.empty()) return 0; - succ_iterator I = std::find(Successors.begin(), Successors.end(), succ); + const_succ_iterator I = std::find(Successors.begin(), Successors.end(), succ); return *getWeightIterator(I); } @@ -888,6 +888,16 @@ return Weights.begin() + index; } +/// getWeightIterator - Return wight iterator corresonding to the I successor +/// iterator +MachineBasicBlock::const_weight_iterator MachineBasicBlock:: +getWeightIterator(MachineBasicBlock::const_succ_iterator I) const { + assert(Weights.size() == Successors.size() && "Async weight list!"); + const size_t index = std::distance(Successors.begin(), I); + assert(index < Weights.size() && "Not a current successor!"); + return Weights.begin() + index; +} + void llvm::WriteAsOperand(raw_ostream &OS, const MachineBasicBlock *MBB, bool t) { OS << "BB#" << MBB->getNumber(); Modified: llvm/trunk/lib/CodeGen/MachineBlockFrequencyInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineBlockFrequencyInfo.cpp?rev=146986&r1=146985&r2=146986&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/MachineBlockFrequencyInfo.cpp (original) +++ llvm/trunk/lib/CodeGen/MachineBlockFrequencyInfo.cpp Tue Dec 20 14:03:10 2011 @@ -56,6 +56,6 @@ /// the other block frequencies. We do this to avoid using of floating points. /// BlockFrequency MachineBlockFrequencyInfo:: -getBlockFreq(MachineBasicBlock *MBB) const { +getBlockFreq(const MachineBasicBlock *MBB) const { return MBFI->getBlockFreq(MBB); } Modified: llvm/trunk/lib/CodeGen/MachineBranchProbabilityInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineBranchProbabilityInfo.cpp?rev=146986&r1=146985&r2=146986&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/MachineBranchProbabilityInfo.cpp (original) +++ llvm/trunk/lib/CodeGen/MachineBranchProbabilityInfo.cpp Tue Dec 20 14:03:10 2011 @@ -29,7 +29,7 @@ void MachineBranchProbabilityInfo::anchor() { } uint32_t MachineBranchProbabilityInfo:: -getSumForBlock(MachineBasicBlock *MBB, uint32_t &Scale) const { +getSumForBlock(const MachineBasicBlock *MBB, uint32_t &Scale) const { // First we compute the sum with 64-bits of precision, ensuring that cannot // overflow by bounding the number of weights considered. Hopefully no one // actually needs 2^32 successors. @@ -61,8 +61,8 @@ } uint32_t -MachineBranchProbabilityInfo::getEdgeWeight(MachineBasicBlock *Src, - MachineBasicBlock *Dst) const { +MachineBranchProbabilityInfo::getEdgeWeight(const MachineBasicBlock *Src, + const MachineBasicBlock *Dst) const { uint32_t Weight = Src->getSuccWeight(Dst); if (!Weight) return DEFAULT_WEIGHT; Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp?rev=146986&r1=146985&r2=146986&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp Tue Dec 20 14:03:10 2011 @@ -1287,8 +1287,8 @@ } /// Return branch probability calculated by BranchProbabilityInfo for IR blocks. -uint32_t SelectionDAGBuilder::getEdgeWeight(MachineBasicBlock *Src, - MachineBasicBlock *Dst) { +uint32_t SelectionDAGBuilder::getEdgeWeight(const MachineBasicBlock *Src, + const MachineBasicBlock *Dst) const { BranchProbabilityInfo *BPI = FuncInfo.BPI; if (!BPI) return 0; Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.h?rev=146986&r1=146985&r2=146986&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.h (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.h Tue Dec 20 14:03:10 2011 @@ -454,7 +454,8 @@ MachineBasicBlock* Default, MachineBasicBlock *SwitchBB); - uint32_t getEdgeWeight(MachineBasicBlock *Src, MachineBasicBlock *Dst); + uint32_t getEdgeWeight(const MachineBasicBlock *Src, + const MachineBasicBlock *Dst) const; void addSuccessorWithWeight(MachineBasicBlock *Src, MachineBasicBlock *Dst, uint32_t Weight = 0); public: From hfinkel at anl.gov Tue Dec 20 14:08:56 2011 From: hfinkel at anl.gov (Hal Finkel) Date: Tue, 20 Dec 2011 14:08:56 -0600 Subject: [llvm-commits] [LLVMdev] [PATCH] BasicBlock Autovectorization Pass In-Reply-To: References: <1319909412.23036.851.camel@sapling> <1319914924.23036.852.camel@sapling> <1319919418.23036.881.camel@sapling> <1319928991.23036.957.camel@sapling> <1320108633.23036.1266.camel@sapling> <1320172356.23036.1298.camel@sapling> <4EB0462C.5010209@grosser.es> <1320184739.23036.1334.camel@sapling> <1320191694.23036.1497.camel@sapling> <1320749109.19359.76.camel@sapling> <4EB90E98.4010805@grosser.es> <1320762963.19359.117.camel@sapling> <4EB98207.2070807@grosser.es> <1320791390.19359.262.camel@sapling> <4EBC4B0F.6010609@grosser.es> <1321050998.19359.539.camel@sapling> <4EBDA7F9.9080709@grosser.es> <1321053083.19359.550.camel@sapling> <4EBDB1BF.7090006@grosser.es> <1321400339.19359.782.camel@sapling> <1321486739.19359.1067.camel@sapling> <4EC504B5.2020408@grosser.es> <1321898108.2507.36.camel@sapling> <1321932161.2507.101.camel@sapling> <1322067157.2507.263.camel@sapling> <4ED8F7B0.8050309@grosser.es> <1323822351.590.1687.camel@sapling> Message-ID: <1324411736.31367.485.camel@sapling> On Tue, 2011-12-20 at 13:57 -0600, Sebastian Pop wrote: > Hi, > > I see that there are two functions in your code that are O(n^2) in > number of instructions of the program: getCandidatePairs and > buildDepMap. I think that you could make these two functions faster > if you work on some form of factored def-use chains for memory, like > the VUSE/VDEFs of GCC. Thanks for the comment! I am not aware of anything along these lines, although it would be quite helpful. The pass spends a significant amount of time running the aliasing-analysis queries. -Hal > > I was trying to find a similar representation in LLVM: isn't there already > a virtual SSA representation for memory references in LLVM? > > Thanks, > Sebastian > -- > Qualcomm Innovation Center, Inc is a member of Code Aurora Forum -- Hal Finkel Postdoctoral Appointee Leadership Computing Facility Argonne National Laboratory From lhames at gmail.com Tue Dec 20 14:23:40 2011 From: lhames at gmail.com (Lang Hames) Date: Tue, 20 Dec 2011 20:23:40 -0000 Subject: [llvm-commits] [llvm] r146987 - /llvm/trunk/lib/CodeGen/LiveRangeCalc.cpp Message-ID: <20111220202340.5C4862A6C12C@llvm.org> Author: lhames Date: Tue Dec 20 14:23:40 2011 New Revision: 146987 URL: http://llvm.org/viewvc/llvm-project?rev=146987&view=rev Log: Fix assert condition. Modified: llvm/trunk/lib/CodeGen/LiveRangeCalc.cpp Modified: llvm/trunk/lib/CodeGen/LiveRangeCalc.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/LiveRangeCalc.cpp?rev=146987&r1=146986&r2=146987&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/LiveRangeCalc.cpp (original) +++ llvm/trunk/lib/CodeGen/LiveRangeCalc.cpp Tue Dec 20 14:23:40 2011 @@ -65,7 +65,7 @@ assert(DomTree && "Missing dominator tree"); MachineBasicBlock *KillMBB = Indexes->getMBBFromIndex(Kill.getPrevSlot()); - assert(Kill && "No MBB at Kill"); + assert(KillMBB && "No MBB at Kill"); // Is there a def in the same MBB we can extend? if (LI->extendInBlock(Indexes->getMBBStartIdx(KillMBB), Kill)) From grosbach at apple.com Tue Dec 20 14:46:29 2011 From: grosbach at apple.com (Jim Grosbach) Date: Tue, 20 Dec 2011 20:46:29 -0000 Subject: [llvm-commits] [llvm] r146990 - in /llvm/trunk: lib/Target/ARM/ARMInstrNEON.td lib/Target/ARM/AsmParser/ARMAsmParser.cpp test/MC/ARM/neon-vst-encoding.s Message-ID: <20111220204629.DE1E02A6C12C@llvm.org> Author: grosbach Date: Tue Dec 20 14:46:29 2011 New Revision: 146990 URL: http://llvm.org/viewvc/llvm-project?rev=146990&view=rev Log: ARM assembly parsing and encoding for VST2 single-element, double spaced. Modified: llvm/trunk/lib/Target/ARM/ARMInstrNEON.td llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp llvm/trunk/test/MC/ARM/neon-vst-encoding.s Modified: llvm/trunk/lib/Target/ARM/ARMInstrNEON.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrNEON.td?rev=146990&r1=146989&r2=146990&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrNEON.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrNEON.td Tue Dec 20 14:46:29 2011 @@ -5800,6 +5800,10 @@ (ins VecListTwoDHWordIndexed:$list, addrmode6:$addr, pred:$p)>; defm VST2LNdAsm : NEONDT32AsmPseudoInst<"vst2${p}", "$list, $addr", (ins VecListTwoDWordIndexed:$list, addrmode6:$addr, pred:$p)>; +defm VST2LNqAsm : NEONDT16AsmPseudoInst<"vst2${p}", "$list, $addr", + (ins VecListTwoQHWordIndexed:$list, addrmode6:$addr, pred:$p)>; +defm VST2LNqAsm : NEONDT32AsmPseudoInst<"vst2${p}", "$list, $addr", + (ins VecListTwoQWordIndexed:$list, addrmode6:$addr, pred:$p)>; defm VST2LNdWB_fixed_Asm : NEONDT8AsmPseudoInst<"vst2${p}", "$list, $addr!", (ins VecListTwoDByteIndexed:$list, addrmode6:$addr, pred:$p)>; @@ -5807,6 +5811,10 @@ (ins VecListTwoDHWordIndexed:$list, addrmode6:$addr, pred:$p)>; defm VST2LNdWB_fixed_Asm : NEONDT32AsmPseudoInst<"vst2${p}", "$list, $addr!", (ins VecListTwoDWordIndexed:$list, addrmode6:$addr, pred:$p)>; +defm VST2LNqWB_fixed_Asm : NEONDT16AsmPseudoInst<"vst2${p}", "$list, $addr!", + (ins VecListTwoQHWordIndexed:$list, addrmode6:$addr, pred:$p)>; +defm VST2LNqWB_fixed_Asm : NEONDT32AsmPseudoInst<"vst2${p}", "$list, $addr!", + (ins VecListTwoQWordIndexed:$list, addrmode6:$addr, pred:$p)>; defm VST2LNdWB_register_Asm : NEONDT8AsmPseudoInst<"vst2${p}", "$list, $addr, $Rm", (ins VecListTwoDByteIndexed:$list, addrmode6:$addr, @@ -5819,6 +5827,14 @@ NEONDT32AsmPseudoInst<"vst2${p}", "$list, $addr, $Rm", (ins VecListTwoDWordIndexed:$list, addrmode6:$addr, rGPR:$Rm, pred:$p)>; +defm VST2LNqWB_register_Asm : + NEONDT16AsmPseudoInst<"vst2${p}", "$list, $addr, $Rm", + (ins VecListTwoQHWordIndexed:$list, addrmode6:$addr, + rGPR:$Rm, pred:$p)>; +defm VST2LNqWB_register_Asm : + NEONDT32AsmPseudoInst<"vst2${p}", "$list, $addr, $Rm", + (ins VecListTwoQWordIndexed:$list, addrmode6:$addr, + rGPR:$Rm, pred:$p)>; // VMOV takes an optional datatype suffix defm : VFPDTAnyInstAlias<"vmov${p}", "$Vd, $Vm", Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp?rev=146990&r1=146989&r2=146990&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp (original) +++ llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Tue Dec 20 14:46:29 2011 @@ -5118,84 +5118,134 @@ return false; } -static unsigned getRealVSTLNOpcode(unsigned Opc) { +static unsigned getRealVSTLNOpcode(unsigned Opc, unsigned &Spacing) { switch(Opc) { default: assert(0 && "unexpected opcode!"); // VST1LN case ARM::VST1LNdWB_fixed_Asm_8: case ARM::VST1LNdWB_fixed_Asm_P8: case ARM::VST1LNdWB_fixed_Asm_I8: case ARM::VST1LNdWB_fixed_Asm_S8: case ARM::VST1LNdWB_fixed_Asm_U8: + Spacing = 1; return ARM::VST1LNd8_UPD; case ARM::VST1LNdWB_fixed_Asm_16: case ARM::VST1LNdWB_fixed_Asm_P16: case ARM::VST1LNdWB_fixed_Asm_I16: case ARM::VST1LNdWB_fixed_Asm_S16: case ARM::VST1LNdWB_fixed_Asm_U16: + Spacing = 1; return ARM::VST1LNd16_UPD; case ARM::VST1LNdWB_fixed_Asm_32: case ARM::VST1LNdWB_fixed_Asm_F: case ARM::VST1LNdWB_fixed_Asm_F32: case ARM::VST1LNdWB_fixed_Asm_I32: case ARM::VST1LNdWB_fixed_Asm_S32: case ARM::VST1LNdWB_fixed_Asm_U32: + Spacing = 1; return ARM::VST1LNd32_UPD; case ARM::VST1LNdWB_register_Asm_8: case ARM::VST1LNdWB_register_Asm_P8: case ARM::VST1LNdWB_register_Asm_I8: case ARM::VST1LNdWB_register_Asm_S8: case ARM::VST1LNdWB_register_Asm_U8: + Spacing = 1; return ARM::VST1LNd8_UPD; case ARM::VST1LNdWB_register_Asm_16: case ARM::VST1LNdWB_register_Asm_P16: case ARM::VST1LNdWB_register_Asm_I16: case ARM::VST1LNdWB_register_Asm_S16: case ARM::VST1LNdWB_register_Asm_U16: + Spacing = 1; return ARM::VST1LNd16_UPD; case ARM::VST1LNdWB_register_Asm_32: case ARM::VST1LNdWB_register_Asm_F: case ARM::VST1LNdWB_register_Asm_F32: case ARM::VST1LNdWB_register_Asm_I32: case ARM::VST1LNdWB_register_Asm_S32: case ARM::VST1LNdWB_register_Asm_U32: + Spacing = 1; return ARM::VST1LNd32_UPD; case ARM::VST1LNdAsm_8: case ARM::VST1LNdAsm_P8: case ARM::VST1LNdAsm_I8: case ARM::VST1LNdAsm_S8: case ARM::VST1LNdAsm_U8: + Spacing = 1; return ARM::VST1LNd8; case ARM::VST1LNdAsm_16: case ARM::VST1LNdAsm_P16: case ARM::VST1LNdAsm_I16: case ARM::VST1LNdAsm_S16: case ARM::VST1LNdAsm_U16: + Spacing = 1; return ARM::VST1LNd16; case ARM::VST1LNdAsm_32: case ARM::VST1LNdAsm_F: case ARM::VST1LNdAsm_F32: case ARM::VST1LNdAsm_I32: case ARM::VST1LNdAsm_S32: case ARM::VST1LNdAsm_U32: + Spacing = 1; return ARM::VST1LNd32; // VST2LN case ARM::VST2LNdWB_fixed_Asm_8: case ARM::VST2LNdWB_fixed_Asm_P8: case ARM::VST2LNdWB_fixed_Asm_I8: case ARM::VST2LNdWB_fixed_Asm_S8: case ARM::VST2LNdWB_fixed_Asm_U8: + Spacing = 1; return ARM::VST2LNd8_UPD; case ARM::VST2LNdWB_fixed_Asm_16: case ARM::VST2LNdWB_fixed_Asm_P16: case ARM::VST2LNdWB_fixed_Asm_I16: case ARM::VST2LNdWB_fixed_Asm_S16: case ARM::VST2LNdWB_fixed_Asm_U16: + Spacing = 1; return ARM::VST2LNd16_UPD; case ARM::VST2LNdWB_fixed_Asm_32: case ARM::VST2LNdWB_fixed_Asm_F: case ARM::VST2LNdWB_fixed_Asm_F32: case ARM::VST2LNdWB_fixed_Asm_I32: case ARM::VST2LNdWB_fixed_Asm_S32: case ARM::VST2LNdWB_fixed_Asm_U32: + Spacing = 1; return ARM::VST2LNd32_UPD; + case ARM::VST2LNqWB_fixed_Asm_16: case ARM::VST2LNqWB_fixed_Asm_P16: + case ARM::VST2LNqWB_fixed_Asm_I16: case ARM::VST2LNqWB_fixed_Asm_S16: + case ARM::VST2LNqWB_fixed_Asm_U16: + Spacing = 2; + return ARM::VST2LNq16_UPD; + case ARM::VST2LNqWB_fixed_Asm_32: case ARM::VST2LNqWB_fixed_Asm_F: + case ARM::VST2LNqWB_fixed_Asm_F32: case ARM::VST2LNqWB_fixed_Asm_I32: + case ARM::VST2LNqWB_fixed_Asm_S32: case ARM::VST2LNqWB_fixed_Asm_U32: + Spacing = 2; + return ARM::VST2LNq32_UPD; + case ARM::VST2LNdWB_register_Asm_8: case ARM::VST2LNdWB_register_Asm_P8: case ARM::VST2LNdWB_register_Asm_I8: case ARM::VST2LNdWB_register_Asm_S8: case ARM::VST2LNdWB_register_Asm_U8: + Spacing = 1; return ARM::VST2LNd8_UPD; case ARM::VST2LNdWB_register_Asm_16: case ARM::VST2LNdWB_register_Asm_P16: case ARM::VST2LNdWB_register_Asm_I16: case ARM::VST2LNdWB_register_Asm_S16: case ARM::VST2LNdWB_register_Asm_U16: + Spacing = 1; return ARM::VST2LNd16_UPD; case ARM::VST2LNdWB_register_Asm_32: case ARM::VST2LNdWB_register_Asm_F: case ARM::VST2LNdWB_register_Asm_F32: case ARM::VST2LNdWB_register_Asm_I32: case ARM::VST2LNdWB_register_Asm_S32: case ARM::VST2LNdWB_register_Asm_U32: + Spacing = 1; return ARM::VST2LNd32_UPD; + case ARM::VST2LNqWB_register_Asm_16: case ARM::VST2LNqWB_register_Asm_P16: + case ARM::VST2LNqWB_register_Asm_I16: case ARM::VST2LNqWB_register_Asm_S16: + case ARM::VST2LNqWB_register_Asm_U16: + Spacing = 2; + return ARM::VST2LNq16_UPD; + case ARM::VST2LNqWB_register_Asm_32: case ARM::VST2LNqWB_register_Asm_F: + case ARM::VST2LNqWB_register_Asm_F32: case ARM::VST2LNqWB_register_Asm_I32: + case ARM::VST2LNqWB_register_Asm_S32: case ARM::VST2LNqWB_register_Asm_U32: + Spacing = 2; + return ARM::VST2LNq32_UPD; + case ARM::VST2LNdAsm_8: case ARM::VST2LNdAsm_P8: case ARM::VST2LNdAsm_I8: case ARM::VST2LNdAsm_S8: case ARM::VST2LNdAsm_U8: + Spacing = 1; return ARM::VST2LNd8; case ARM::VST2LNdAsm_16: case ARM::VST2LNdAsm_P16: case ARM::VST2LNdAsm_I16: case ARM::VST2LNdAsm_S16: case ARM::VST2LNdAsm_U16: + Spacing = 1; return ARM::VST2LNd16; case ARM::VST2LNdAsm_32: case ARM::VST2LNdAsm_F: case ARM::VST2LNdAsm_F32: case ARM::VST2LNdAsm_I32: case ARM::VST2LNdAsm_S32: case ARM::VST2LNdAsm_U32: + Spacing = 1; return ARM::VST2LNd32; + case ARM::VST2LNqAsm_16: case ARM::VST2LNqAsm_P16: + case ARM::VST2LNqAsm_I16: case ARM::VST2LNqAsm_S16: + case ARM::VST2LNqAsm_U16: + Spacing = 2; + return ARM::VST2LNq16; + case ARM::VST2LNqAsm_32: case ARM::VST2LNqAsm_F: + case ARM::VST2LNqAsm_F32: case ARM::VST2LNqAsm_I32: + case ARM::VST2LNqAsm_S32: case ARM::VST2LNqAsm_U32: + Spacing = 2; + return ARM::VST2LNq32; } } @@ -5344,7 +5394,8 @@ MCInst TmpInst; // Shuffle the operands around so the lane index operand is in the // right place. - TmpInst.setOpcode(getRealVSTLNOpcode(Inst.getOpcode())); + unsigned Spacing; + TmpInst.setOpcode(getRealVSTLNOpcode(Inst.getOpcode(), Spacing)); TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb TmpInst.addOperand(Inst.getOperand(2)); // Rn TmpInst.addOperand(Inst.getOperand(3)); // alignment @@ -5357,24 +5408,32 @@ return true; } - case ARM::VST2LNdWB_register_Asm_8: case ARM::VST2LNdWB_register_Asm_P8: - case ARM::VST2LNdWB_register_Asm_I8: case ARM::VST2LNdWB_register_Asm_S8: - case ARM::VST2LNdWB_register_Asm_U8: case ARM::VST2LNdWB_register_Asm_16: + case ARM::VST2LNdWB_register_Asm_8: case ARM::VST2LNdWB_register_Asm_P8: + case ARM::VST2LNdWB_register_Asm_I8: case ARM::VST2LNdWB_register_Asm_S8: + case ARM::VST2LNdWB_register_Asm_U8: case ARM::VST2LNdWB_register_Asm_16: case ARM::VST2LNdWB_register_Asm_P16: case ARM::VST2LNdWB_register_Asm_I16: case ARM::VST2LNdWB_register_Asm_S16: case ARM::VST2LNdWB_register_Asm_U16: - case ARM::VST2LNdWB_register_Asm_32: case ARM::VST2LNdWB_register_Asm_F: + case ARM::VST2LNdWB_register_Asm_32: case ARM::VST2LNdWB_register_Asm_F: case ARM::VST2LNdWB_register_Asm_F32: case ARM::VST2LNdWB_register_Asm_I32: - case ARM::VST2LNdWB_register_Asm_S32: case ARM::VST2LNdWB_register_Asm_U32: { + case ARM::VST2LNdWB_register_Asm_S32: case ARM::VST2LNdWB_register_Asm_U32: + case ARM::VST2LNqWB_register_Asm_16: case ARM::VST2LNqWB_register_Asm_P16: + case ARM::VST2LNqWB_register_Asm_I16: case ARM::VST2LNqWB_register_Asm_S16: + case ARM::VST2LNqWB_register_Asm_U16: case ARM::VST2LNqWB_register_Asm_32: + case ARM::VST2LNqWB_register_Asm_F: case ARM::VST2LNqWB_register_Asm_F32: + case ARM::VST2LNqWB_register_Asm_I32: case ARM::VST2LNqWB_register_Asm_S32: + case ARM::VST2LNqWB_register_Asm_U32: { MCInst TmpInst; // Shuffle the operands around so the lane index operand is in the // right place. - TmpInst.setOpcode(getRealVSTLNOpcode(Inst.getOpcode())); + unsigned Spacing; + TmpInst.setOpcode(getRealVSTLNOpcode(Inst.getOpcode(), Spacing)); TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb TmpInst.addOperand(Inst.getOperand(2)); // Rn TmpInst.addOperand(Inst.getOperand(3)); // alignment TmpInst.addOperand(Inst.getOperand(4)); // Rm TmpInst.addOperand(Inst.getOperand(0)); // Vd - TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg()+1)); + TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + + Spacing)); TmpInst.addOperand(Inst.getOperand(1)); // lane TmpInst.addOperand(Inst.getOperand(5)); // CondCode TmpInst.addOperand(Inst.getOperand(6)); @@ -5392,7 +5451,8 @@ MCInst TmpInst; // Shuffle the operands around so the lane index operand is in the // right place. - TmpInst.setOpcode(getRealVSTLNOpcode(Inst.getOpcode())); + unsigned Spacing; + TmpInst.setOpcode(getRealVSTLNOpcode(Inst.getOpcode(), Spacing)); TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb TmpInst.addOperand(Inst.getOperand(2)); // Rn TmpInst.addOperand(Inst.getOperand(3)); // alignment @@ -5405,24 +5465,32 @@ return true; } - case ARM::VST2LNdWB_fixed_Asm_8: case ARM::VST2LNdWB_fixed_Asm_P8: - case ARM::VST2LNdWB_fixed_Asm_I8: case ARM::VST2LNdWB_fixed_Asm_S8: - case ARM::VST2LNdWB_fixed_Asm_U8: case ARM::VST2LNdWB_fixed_Asm_16: + case ARM::VST2LNdWB_fixed_Asm_8: case ARM::VST2LNdWB_fixed_Asm_P8: + case ARM::VST2LNdWB_fixed_Asm_I8: case ARM::VST2LNdWB_fixed_Asm_S8: + case ARM::VST2LNdWB_fixed_Asm_U8: case ARM::VST2LNdWB_fixed_Asm_16: case ARM::VST2LNdWB_fixed_Asm_P16: case ARM::VST2LNdWB_fixed_Asm_I16: case ARM::VST2LNdWB_fixed_Asm_S16: case ARM::VST2LNdWB_fixed_Asm_U16: - case ARM::VST2LNdWB_fixed_Asm_32: case ARM::VST2LNdWB_fixed_Asm_F: + case ARM::VST2LNdWB_fixed_Asm_32: case ARM::VST2LNdWB_fixed_Asm_F: case ARM::VST2LNdWB_fixed_Asm_F32: case ARM::VST2LNdWB_fixed_Asm_I32: - case ARM::VST2LNdWB_fixed_Asm_S32: case ARM::VST2LNdWB_fixed_Asm_U32: { + case ARM::VST2LNdWB_fixed_Asm_S32: case ARM::VST2LNdWB_fixed_Asm_U32: + case ARM::VST2LNqWB_fixed_Asm_16: case ARM::VST2LNqWB_fixed_Asm_P16: + case ARM::VST2LNqWB_fixed_Asm_I16: case ARM::VST2LNqWB_fixed_Asm_S16: + case ARM::VST2LNqWB_fixed_Asm_U16: case ARM::VST2LNqWB_fixed_Asm_32: + case ARM::VST2LNqWB_fixed_Asm_F: case ARM::VST2LNqWB_fixed_Asm_F32: + case ARM::VST2LNqWB_fixed_Asm_I32: case ARM::VST2LNqWB_fixed_Asm_S32: + case ARM::VST2LNqWB_fixed_Asm_U32: { MCInst TmpInst; // Shuffle the operands around so the lane index operand is in the // right place. - TmpInst.setOpcode(getRealVSTLNOpcode(Inst.getOpcode())); + unsigned Spacing; + TmpInst.setOpcode(getRealVSTLNOpcode(Inst.getOpcode(), Spacing)); TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb TmpInst.addOperand(Inst.getOperand(2)); // Rn TmpInst.addOperand(Inst.getOperand(3)); // alignment TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm TmpInst.addOperand(Inst.getOperand(0)); // Vd - TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg()+1)); + TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + + Spacing)); TmpInst.addOperand(Inst.getOperand(1)); // lane TmpInst.addOperand(Inst.getOperand(4)); // CondCode TmpInst.addOperand(Inst.getOperand(5)); @@ -5438,7 +5506,8 @@ MCInst TmpInst; // Shuffle the operands around so the lane index operand is in the // right place. - TmpInst.setOpcode(getRealVSTLNOpcode(Inst.getOpcode())); + unsigned Spacing; + TmpInst.setOpcode(getRealVSTLNOpcode(Inst.getOpcode(), Spacing)); TmpInst.addOperand(Inst.getOperand(2)); // Rn TmpInst.addOperand(Inst.getOperand(3)); // alignment TmpInst.addOperand(Inst.getOperand(0)); // Vd @@ -5449,20 +5518,25 @@ return true; } - case ARM::VST2LNdAsm_8: case ARM::VST2LNdAsm_P8: case ARM::VST2LNdAsm_I8: - case ARM::VST2LNdAsm_S8: case ARM::VST2LNdAsm_U8: case ARM::VST2LNdAsm_16: + case ARM::VST2LNdAsm_8: case ARM::VST2LNdAsm_P8: case ARM::VST2LNdAsm_I8: + case ARM::VST2LNdAsm_S8: case ARM::VST2LNdAsm_U8: case ARM::VST2LNdAsm_16: case ARM::VST2LNdAsm_P16: case ARM::VST2LNdAsm_I16: case ARM::VST2LNdAsm_S16: - case ARM::VST2LNdAsm_U16: case ARM::VST2LNdAsm_32: case ARM::VST2LNdAsm_F: + case ARM::VST2LNdAsm_U16: case ARM::VST2LNdAsm_32: case ARM::VST2LNdAsm_F: case ARM::VST2LNdAsm_F32: case ARM::VST2LNdAsm_I32: case ARM::VST2LNdAsm_S32: - case ARM::VST2LNdAsm_U32: { + case ARM::VST2LNdAsm_U32: case ARM::VST2LNqAsm_16: case ARM::VST2LNqAsm_P16: + case ARM::VST2LNqAsm_I16: case ARM::VST2LNqAsm_S16: case ARM::VST2LNqAsm_U16: + case ARM::VST2LNqAsm_32: case ARM::VST2LNqAsm_F: case ARM::VST2LNqAsm_F32: + case ARM::VST2LNqAsm_I32: case ARM::VST2LNqAsm_S32: case ARM::VST2LNqAsm_U32:{ MCInst TmpInst; // Shuffle the operands around so the lane index operand is in the // right place. - TmpInst.setOpcode(getRealVSTLNOpcode(Inst.getOpcode())); + unsigned Spacing; + TmpInst.setOpcode(getRealVSTLNOpcode(Inst.getOpcode(), Spacing)); TmpInst.addOperand(Inst.getOperand(2)); // Rn TmpInst.addOperand(Inst.getOperand(3)); // alignment TmpInst.addOperand(Inst.getOperand(0)); // Vd - TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg()+1)); + TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + + Spacing)); TmpInst.addOperand(Inst.getOperand(1)); // lane TmpInst.addOperand(Inst.getOperand(4)); // CondCode TmpInst.addOperand(Inst.getOperand(5)); @@ -5504,11 +5578,12 @@ case ARM::VLD2LNdWB_register_Asm_32: case ARM::VLD2LNdWB_register_Asm_F: case ARM::VLD2LNdWB_register_Asm_F32: case ARM::VLD2LNdWB_register_Asm_I32: case ARM::VLD2LNdWB_register_Asm_S32: case ARM::VLD2LNdWB_register_Asm_U32: - case ARM::VLD2LNqWB_register_Asm_P16: case ARM::VLD2LNqWB_register_Asm_I16: - case ARM::VLD2LNqWB_register_Asm_S16: case ARM::VLD2LNqWB_register_Asm_U16: - case ARM::VLD2LNqWB_register_Asm_32: case ARM::VLD2LNqWB_register_Asm_F: - case ARM::VLD2LNqWB_register_Asm_F32: case ARM::VLD2LNqWB_register_Asm_I32: - case ARM::VLD2LNqWB_register_Asm_S32: case ARM::VLD2LNqWB_register_Asm_U32: { + case ARM::VLD2LNqWB_register_Asm_16: case ARM::VLD2LNqWB_register_Asm_P16: + case ARM::VLD2LNqWB_register_Asm_I16: case ARM::VLD2LNqWB_register_Asm_S16: + case ARM::VLD2LNqWB_register_Asm_U16: case ARM::VLD2LNqWB_register_Asm_32: + case ARM::VLD2LNqWB_register_Asm_F: case ARM::VLD2LNqWB_register_Asm_F32: + case ARM::VLD2LNqWB_register_Asm_I32: case ARM::VLD2LNqWB_register_Asm_S32: + case ARM::VLD2LNqWB_register_Asm_U32: { MCInst TmpInst; // Shuffle the operands around so the lane index operand is in the // right place. @@ -5565,11 +5640,12 @@ case ARM::VLD2LNdWB_fixed_Asm_32: case ARM::VLD2LNdWB_fixed_Asm_F: case ARM::VLD2LNdWB_fixed_Asm_F32: case ARM::VLD2LNdWB_fixed_Asm_I32: case ARM::VLD2LNdWB_fixed_Asm_S32: case ARM::VLD2LNdWB_fixed_Asm_U32: - case ARM::VLD2LNqWB_fixed_Asm_P16: case ARM::VLD2LNqWB_fixed_Asm_I16: - case ARM::VLD2LNqWB_fixed_Asm_S16: case ARM::VLD2LNqWB_fixed_Asm_U16: - case ARM::VLD2LNqWB_fixed_Asm_32: case ARM::VLD2LNqWB_fixed_Asm_F: - case ARM::VLD2LNqWB_fixed_Asm_F32: case ARM::VLD2LNqWB_fixed_Asm_I32: - case ARM::VLD2LNqWB_fixed_Asm_S32: case ARM::VLD2LNqWB_fixed_Asm_U32: { + case ARM::VLD2LNqWB_fixed_Asm_16: case ARM::VLD2LNqWB_fixed_Asm_P16: + case ARM::VLD2LNqWB_fixed_Asm_I16: case ARM::VLD2LNqWB_fixed_Asm_S16: + case ARM::VLD2LNqWB_fixed_Asm_U16: case ARM::VLD2LNqWB_fixed_Asm_32: + case ARM::VLD2LNqWB_fixed_Asm_F: case ARM::VLD2LNqWB_fixed_Asm_F32: + case ARM::VLD2LNqWB_fixed_Asm_I32: case ARM::VLD2LNqWB_fixed_Asm_S32: + case ARM::VLD2LNqWB_fixed_Asm_U32: { MCInst TmpInst; // Shuffle the operands around so the lane index operand is in the // right place. @@ -5592,10 +5668,10 @@ return true; } - case ARM::VLD1LNdAsm_8: case ARM::VLD1LNdAsm_P8: case ARM::VLD1LNdAsm_I8: - case ARM::VLD1LNdAsm_S8: case ARM::VLD1LNdAsm_U8: case ARM::VLD1LNdAsm_16: + case ARM::VLD1LNdAsm_8: case ARM::VLD1LNdAsm_P8: case ARM::VLD1LNdAsm_I8: + case ARM::VLD1LNdAsm_S8: case ARM::VLD1LNdAsm_U8: case ARM::VLD1LNdAsm_16: case ARM::VLD1LNdAsm_P16: case ARM::VLD1LNdAsm_I16: case ARM::VLD1LNdAsm_S16: - case ARM::VLD1LNdAsm_U16: case ARM::VLD1LNdAsm_32: case ARM::VLD1LNdAsm_F: + case ARM::VLD1LNdAsm_U16: case ARM::VLD1LNdAsm_32: case ARM::VLD1LNdAsm_F: case ARM::VLD1LNdAsm_F32: case ARM::VLD1LNdAsm_I32: case ARM::VLD1LNdAsm_S32: case ARM::VLD1LNdAsm_U32: { MCInst TmpInst; Modified: llvm/trunk/test/MC/ARM/neon-vst-encoding.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/neon-vst-encoding.s?rev=146990&r1=146989&r2=146990&view=diff ============================================================================== --- llvm/trunk/test/MC/ARM/neon-vst-encoding.s (original) +++ llvm/trunk/test/MC/ARM/neon-vst-encoding.s Tue Dec 20 14:46:29 2011 @@ -101,23 +101,37 @@ vst2.8 {d16[1], d17[1]}, [r0, :16] vst2.16 {d16[1], d17[1]}, [r0, :32] vst2.32 {d16[1], d17[1]}, [r0] -@ vst2.16 {d17[1], d19[1]}, [r0] -@ vst2.32 {d17[0], d19[0]}, [r0, :64] + vst2.16 {d17[1], d19[1]}, [r0] + vst2.32 {d17[0], d19[0]}, [r0, :64] vst2.8 {d2[4], d3[4]}, [r2], r3 vst2.8 {d2[4], d3[4]}, [r2]! vst2.8 {d2[4], d3[4]}, [r2] + vst2.16 {d17[1], d19[1]}, [r0] + vst2.32 {d17[0], d19[0]}, [r0, :64] + vst2.16 {d7[1], d9[1]}, [r1]! + vst2.32 {d6[0], d8[0]}, [r2, :64]! + vst2.16 {d2[1], d4[1]}, [r3], r5 + vst2.32 {d5[0], d7[0]}, [r4, :64], r7 + @ CHECK: vst2.8 {d16[1], d17[1]}, [r0, :16] @ encoding: [0x3f,0x01,0xc0,0xf4] @ CHECK: vst2.16 {d16[1], d17[1]}, [r0, :32] @ encoding: [0x5f,0x05,0xc0,0xf4] @ CHECK: vst2.32 {d16[1], d17[1]}, [r0] @ encoding: [0x8f,0x09,0xc0,0xf4] -@ FIXME: vst2.16 {d17[1], d19[1]}, [r0] @ encoding: [0x6f,0x15,0xc0,0xf4] -@ FIXME: vst2.32 {d17[0], d19[0]}, [r0, :64] @ encoding: [0x5f,0x19,0xc0,0xf4] +@ CHECK: vst2.16 {d17[1], d19[1]}, [r0] @ encoding: [0x6f,0x15,0xc0,0xf4] +@ CHECK: vst2.32 {d17[0], d19[0]}, [r0, :64] @ encoding: [0x5f,0x19,0xc0,0xf4] @ CHECK: vst2.8 {d2[4], d3[4]}, [r2], r3 @ encoding: [0x83,0x21,0x82,0xf4] @ CHECK: vst2.8 {d2[4], d3[4]}, [r2]! @ encoding: [0x8d,0x21,0x82,0xf4] @ CHECK: vst2.8 {d2[4], d3[4]}, [r2] @ encoding: [0x8f,0x21,0x82,0xf4] +@ CHECK: vst2.16 {d17[1], d19[1]}, [r0] @ encoding: [0x6f,0x15,0xc0,0xf4] +@ CHECK: vst2.32 {d17[0], d19[0]}, [r0, :64] @ encoding: [0x5f,0x19,0xc0,0xf4] +@ CHECK: vst2.16 {d7[1], d9[1]}, [r1]! @ encoding: [0x6d,0x75,0x81,0xf4] +@ CHECK: vst2.32 {d6[0], d8[0]}, [r2, :64]! @ encoding: [0x5d,0x69,0x82,0xf4] +@ CHECK: vst2.16 {d2[1], d4[1]}, [r3], r5 @ encoding: [0x65,0x25,0x83,0xf4] +@ CHECK: vst2.32 {d5[0], d7[0]}, [r4, :64], r7 @ encoding: [0x57,0x59,0x84,0xf4] + @ vst3.8 {d16[1], d17[1], d18[1]}, [r0] @ vst3.16 {d16[1], d17[1], d18[1]}, [r0] From grosbach at apple.com Tue Dec 20 15:08:01 2011 From: grosbach at apple.com (Jim Grosbach) Date: Tue, 20 Dec 2011 13:08:01 -0800 Subject: [llvm-commits] [PATCH] MC ARM Thumb: fix incorrect relocation generation (PR11214) In-Reply-To: References: <000001ccbf1d$618f7490$24ae5db0$%beyls@arm.com> <57817466-3086-4652-85E2-4959AF23D81B@apple.com> <107270DB-89BE-4C71-9181-CF7FDD300E25@apple.com> Message-ID: <854417BF-9EFC-4743-A8F3-249712BC9ADD@apple.com> Right. I agree it's fairly clear that R_ARM_NONE is wrong. It's not clear, however, that R_ARM_THM_CALL is correct for non-PLT relocations. I suspect it's not else that conditional wouldn't have been there in the first place. I'm hoping that an ELF knowledgeable person will chime in and let us know for sure one way or the other. -Jim On Dec 20, 2011, at 12:06 PM, Kristof Beyls wrote: > The reason why I thought the patch would be OK is that the patch only > changes the behaviour for the thumb bl and blx instructions (i.e. only for > the cases ARM::fixup_arm_thumb_bl and ARM::fixup_arm_thumb_blx. > > For these instructions, I can't see why R_ARM_NONE would ever be the correct > relocation type. The definition of R_ARM_NONE from the AAELF ABI: > """ > R_ARM_NONE records that the section containing the place to be relocated depends on the section defining the symbol mentioned in the relocation directive in a way otherwise invisible to the static linker. The effect is to prevent removal of sections that might otherwise appear to be unused. > """ > > Thanks, > > Kristof > >> -----Original Message----- >> From: Jim Grosbach [mailto:grosbach at apple.com] >> Sent: 20 December 2011 19:33 >> To: James Molloy >> Cc: Kristof Beyls; llvm-commits at cs.uiuc.edu >> Subject: Re: [llvm-commits] [PATCH] MC ARM Thumb: fix incorrect >> relocation generation (PR11214) >> >> Yeah, that's my guess. An assert(0 "unimplemented non-PLT call!") or >> something would have been better if that's the case exactly to prevent >> this sort of head-scratching. :) >> >> -Jim >> >> On Dec 20, 2011, at 11:21 AM, James Molloy wrote: >> >>> Yeah, I was confused about that too. >>> >>> I couldn't comprehend why that conditional was even there in the >> first place - an R_ARM_NONE relocation is *never* required for a call >> (it's a special no-op reloc). >>> >>> The only thing I could think of is that someone wanted to fix the >> relocation given to PLT entries and decided to keep the a broken >> behaviour for the default case, perhaps they had no knowledge about it. >>> ________________________________________ >>> From: llvm-commits-bounces at cs.uiuc.edu [llvm-commits- >> bounces at cs.uiuc.edu] On Behalf Of Jim Grosbach [grosbach at apple.com] >>> Sent: 20 December 2011 19:07 >>> To: Kristof Beyls >>> Cc: llvm-commits at cs.uiuc.edu >>> Subject: Re: [llvm-commits] [PATCH] MC ARM Thumb: fix incorrect >> relocation generation (PR11214) >>> >>> Someone with ELF knowledge should look at this. I'm a bit nervous >> about removing the conditional as it seems to imply that there's an >> different relocation that should be generated depending on the variant >> kind. >>> >>> -Jim >>> >>> On Dec 20, 2011, at 5:43 AM, Kristof Beyls wrote: >>> >>>> Hi, >>>> >>>> Please find a patch for fixing incorrect generation of relocation >>>> information on Thumb function calls. >>>> This should fix quite a few incorrect code generation problems in >> Thumb mode >>>> when using the integrated assembler. >>>> I believe this fixes PR11214 >>>> (http://www.llvm.org/bugs/show_bug.cgi?id=11214). >>>> >>>> Is this OK? >>>> >>>> Thanks, >>>> >>>> Kristof >>>> >> ____________________________________________ >> ___ >>>> llvm-commits mailing list >>>> llvm-commits at cs.uiuc.edu >>>> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits >>> >>> _______________________________________________ >>> llvm-commits mailing list >>> llvm-commits at cs.uiuc.edu >>> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits >>> >>> >>> -- IMPORTANT NOTICE: The contents of this email and any attachments >> are confidential and may also be privileged. If you are not the >> intended recipient, please notify the sender immediately and do not >> disclose the contents to any other person, use it for any purpose, or >> store or copy the information in any medium. Thank you. >>> >> >> > > > -- IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you. > From ahatanaka at mips.com Tue Dec 20 15:50:50 2011 From: ahatanaka at mips.com (Akira Hatanaka) Date: Tue, 20 Dec 2011 21:50:50 -0000 Subject: [llvm-commits] [llvm] r146992 - /llvm/trunk/lib/Target/Mips/MipsInstrInfo.td Message-ID: <20111220215050.0BC072A6C12C@llvm.org> Author: ahatanak Date: Tue Dec 20 15:50:49 2011 New Revision: 146992 URL: http://llvm.org/viewvc/llvm-project?rev=146992&view=rev Log: Add a pattern for matching zero-store with 64-bit address. The pattern is enabled only when the target ABI is N64. Modified: llvm/trunk/lib/Target/Mips/MipsInstrInfo.td Modified: llvm/trunk/lib/Target/Mips/MipsInstrInfo.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsInstrInfo.td?rev=146992&r1=146991&r2=146992&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/MipsInstrInfo.td (original) +++ llvm/trunk/lib/Target/Mips/MipsInstrInfo.td Tue Dec 20 15:50:49 2011 @@ -1015,7 +1015,10 @@ def : Pat<(extloadi16_u addr:$src), (ULHu addr:$src)>; // peepholes -def : Pat<(store (i32 0), addr:$dst), (SW ZERO, addr:$dst)>; +def : Pat<(store (i32 0), addr:$dst), (SW ZERO, addr:$dst)>, + Requires<[NotN64]>; +def : Pat<(store (i32 0), addr:$dst), (SW_P8 ZERO, addr:$dst)>, + Requires<[IsN64]>; // brcond patterns multiclass BrcondPats Author: ahatanak Date: Tue Dec 20 16:06:20 2011 New Revision: 146995 URL: http://llvm.org/viewvc/llvm-project?rev=146995&view=rev Log: 32-to-64-bit sign extension pattern. Modified: llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td llvm/trunk/lib/Target/Mips/MipsISelDAGToDAG.cpp Modified: llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td?rev=146995&r1=146994&r2=146995&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td (original) +++ llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td Tue Dec 20 16:06:20 2011 @@ -299,3 +299,5 @@ // 32-to-64-bit extension def : Pat<(i64 (anyext CPURegs:$src)), (SLL64_32 CPURegs:$src)>; def : Pat<(i64 (zext CPURegs:$src)), (DSRL (DSLL64_32 CPURegs:$src), 32)>; +def : Pat<(i64 (sext CPURegs:$src)), (SLL64_32 CPURegs:$src)>; + Modified: llvm/trunk/lib/Target/Mips/MipsISelDAGToDAG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsISelDAGToDAG.cpp?rev=146995&r1=146994&r2=146995&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/MipsISelDAGToDAG.cpp (original) +++ llvm/trunk/lib/Target/Mips/MipsISelDAGToDAG.cpp Tue Dec 20 16:06:20 2011 @@ -293,6 +293,12 @@ case ISD::ConstantFP: { ConstantFPSDNode *CN = dyn_cast(Node); if (Node->getValueType(0) == MVT::f64 && CN->isExactlyValue(+0.0)) { + if (Subtarget.hasMips64()) { + SDValue Zero = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl, + Mips::ZERO_64, MVT::i64); + return CurDAG->getMachineNode(Mips::DMTC1, dl, MVT::f64, Zero); + } + SDValue Zero = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl, Mips::ZERO, MVT::i32); return CurDAG->getMachineNode(Mips::BuildPairF64, dl, MVT::f64, Zero, From ahatanaka at mips.com Tue Dec 20 16:09:36 2011 From: ahatanaka at mips.com (Akira Hatanaka) Date: Tue, 20 Dec 2011 22:09:36 -0000 Subject: [llvm-commits] [llvm] r146996 - /llvm/trunk/lib/Target/Mips/MipsISelDAGToDAG.cpp Message-ID: <20111220220936.8C9192A6C12C@llvm.org> Author: ahatanak Date: Tue Dec 20 16:09:36 2011 New Revision: 146996 URL: http://llvm.org/viewvc/llvm-project?rev=146996&view=rev Log: Revert part of r146995 that was accidentally commmitted. Modified: llvm/trunk/lib/Target/Mips/MipsISelDAGToDAG.cpp Modified: llvm/trunk/lib/Target/Mips/MipsISelDAGToDAG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsISelDAGToDAG.cpp?rev=146996&r1=146995&r2=146996&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/MipsISelDAGToDAG.cpp (original) +++ llvm/trunk/lib/Target/Mips/MipsISelDAGToDAG.cpp Tue Dec 20 16:09:36 2011 @@ -293,12 +293,6 @@ case ISD::ConstantFP: { ConstantFPSDNode *CN = dyn_cast(Node); if (Node->getValueType(0) == MVT::f64 && CN->isExactlyValue(+0.0)) { - if (Subtarget.hasMips64()) { - SDValue Zero = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl, - Mips::ZERO_64, MVT::i64); - return CurDAG->getMachineNode(Mips::DMTC1, dl, MVT::f64, Zero); - } - SDValue Zero = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl, Mips::ZERO, MVT::i32); return CurDAG->getMachineNode(Mips::BuildPairF64, dl, MVT::f64, Zero, From stoklund at 2pi.dk Tue Dec 20 16:15:04 2011 From: stoklund at 2pi.dk (Jakob Stoklund Olesen) Date: Tue, 20 Dec 2011 22:15:04 -0000 Subject: [llvm-commits] [llvm] r146997 - in /llvm/trunk: lib/Target/ARM/ARMBaseInstrInfo.cpp lib/Target/ARM/ARMBaseRegisterInfo.cpp test/CodeGen/ARM/fast-isel-deadcode.ll test/CodeGen/Thumb2/aligned-spill.ll Message-ID: <20111220221504.878B42A6C12C@llvm.org> Author: stoklund Date: Tue Dec 20 16:15:04 2011 New Revision: 146997 URL: http://llvm.org/viewvc/llvm-project?rev=146997&view=rev Log: Heed spill slot alignment on ARM. Use the spill slot alignment as well as the local variable alignment to determine when the stack needs to be realigned. This works now that the ARM target can always realign the stack by using a base pointer. Still respect the ARMBaseRegisterInfo::canRealignStack() function vetoing a realigned stack. Don't use aligned spill code in that case. Added: llvm/trunk/test/CodeGen/Thumb2/aligned-spill.ll Modified: llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp llvm/trunk/test/CodeGen/ARM/fast-isel-deadcode.ll Modified: llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp?rev=146997&r1=146996&r2=146997&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp Tue Dec 20 16:15:04 2011 @@ -765,7 +765,8 @@ break; case 16: if (ARM::QPRRegClass.hasSubClassEq(RC)) { - if (Align >= 16 && getRegisterInfo().needsStackRealignment(MF)) { + // Use aligned spills if the stack can be realigned. + if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) { AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VST1q64Pseudo)) .addFrameIndex(FI).addImm(16) .addReg(SrcReg, getKillRegState(isKill)) @@ -914,7 +915,7 @@ break; case 16: if (ARM::QPRRegClass.hasSubClassEq(RC)) { - if (Align >= 16 && getRegisterInfo().needsStackRealignment(MF)) { + if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) { AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLD1q64Pseudo), DestReg) .addFrameIndex(FI).addImm(16) .addMemOperand(MMO)); Modified: llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp?rev=146997&r1=146996&r2=146997&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp Tue Dec 20 16:15:04 2011 @@ -542,7 +542,7 @@ const MachineFrameInfo *MFI = MF.getFrameInfo(); const Function *F = MF.getFunction(); unsigned StackAlign = MF.getTarget().getFrameLowering()->getStackAlignment(); - bool requiresRealignment = ((MFI->getLocalFrameMaxAlign() > StackAlign) || + bool requiresRealignment = ((MFI->getMaxAlignment() > StackAlign) || F->hasFnAttr(Attribute::StackAlignment)); return requiresRealignment && canRealignStack(MF); Modified: llvm/trunk/test/CodeGen/ARM/fast-isel-deadcode.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/fast-isel-deadcode.ll?rev=146997&r1=146996&r2=146997&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/ARM/fast-isel-deadcode.ll (original) +++ llvm/trunk/test/CodeGen/ARM/fast-isel-deadcode.ll Tue Dec 20 16:15:04 2011 @@ -15,8 +15,7 @@ ; THUMB-NOT: sxtb ; THUMB: movs r0, #0 ; THUMB: movt r0, #0 -; THUMB: add sp, #32 -; THUMb: pop {r7, pc} +; THUMB: pop ret i32 0 } Added: llvm/trunk/test/CodeGen/Thumb2/aligned-spill.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb2/aligned-spill.ll?rev=146997&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/Thumb2/aligned-spill.ll (added) +++ llvm/trunk/test/CodeGen/Thumb2/aligned-spill.ll Tue Dec 20 16:15:04 2011 @@ -0,0 +1,22 @@ +; RUN: llc < %s -mcpu=cortex-a8 | FileCheck %s +target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:32:64-v128:32:128-a0:0:32-n32-S32" +target triple = "thumbv7-apple-ios" + +; CHECK: f +; This function is forced to spill a double. +; Verify that the spill slot is properly aligned. +; +; The caller-saved r4 is used as a scratch register for stack realignment. +; CHECK: push {r4, r7, lr} +; CHECK: bic r4, r4, #7 +; CHECK: mov sp, r4 +define void @f(double* nocapture %p) nounwind ssp { +entry: + %0 = load double* %p, align 4 + tail call void asm sideeffect "", "~{d8},~{d9},~{d10},~{d11},~{d12},~{d13},~{d14},~{d15}"() nounwind + tail call void @g() nounwind + store double %0, double* %p, align 4 + ret void +} + +declare void @g() From ahatanaka at mips.com Tue Dec 20 16:25:51 2011 From: ahatanaka at mips.com (Akira Hatanaka) Date: Tue, 20 Dec 2011 22:25:51 -0000 Subject: [llvm-commits] [llvm] r146999 - in /llvm/trunk: lib/Target/Mips/MipsISelDAGToDAG.cpp test/CodeGen/Mips/mips64fpimm0.ll Message-ID: <20111220222551.1FA342A6C12C@llvm.org> Author: ahatanak Date: Tue Dec 20 16:25:50 2011 New Revision: 146999 URL: http://llvm.org/viewvc/llvm-project?rev=146999&view=rev Log: Add code in MipsDAGToDAGISel for selecting constant +0.0. MIPS64 can generate constant +0.0 with a single DMTC1 instruction. Added: llvm/trunk/test/CodeGen/Mips/mips64fpimm0.ll Modified: llvm/trunk/lib/Target/Mips/MipsISelDAGToDAG.cpp Modified: llvm/trunk/lib/Target/Mips/MipsISelDAGToDAG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsISelDAGToDAG.cpp?rev=146999&r1=146998&r2=146999&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/MipsISelDAGToDAG.cpp (original) +++ llvm/trunk/lib/Target/Mips/MipsISelDAGToDAG.cpp Tue Dec 20 16:25:50 2011 @@ -293,6 +293,12 @@ case ISD::ConstantFP: { ConstantFPSDNode *CN = dyn_cast(Node); if (Node->getValueType(0) == MVT::f64 && CN->isExactlyValue(+0.0)) { + if (Subtarget.hasMips64()) { + SDValue Zero = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl, + Mips::ZERO_64, MVT::i64); + return CurDAG->getMachineNode(Mips::DMTC1, dl, MVT::f64, Zero); + } + SDValue Zero = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl, Mips::ZERO, MVT::i32); return CurDAG->getMachineNode(Mips::BuildPairF64, dl, MVT::f64, Zero, Added: llvm/trunk/test/CodeGen/Mips/mips64fpimm0.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/mips64fpimm0.ll?rev=146999&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/Mips/mips64fpimm0.ll (added) +++ llvm/trunk/test/CodeGen/Mips/mips64fpimm0.ll Tue Dec 20 16:25:50 2011 @@ -0,0 +1,7 @@ +; RUN: llc < %s -march=mips64el -mcpu=mips64 -mattr=n64 | FileCheck %s + +define double @foo1() nounwind readnone { +entry: +; CHECK: dmtc1 $zero + ret double 0.000000e+00 +} From grosbach at apple.com Tue Dec 20 16:26:38 2011 From: grosbach at apple.com (Jim Grosbach) Date: Tue, 20 Dec 2011 22:26:38 -0000 Subject: [llvm-commits] [llvm] r147000 - /llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Message-ID: <20111220222638.AD31A2A6C12C@llvm.org> Author: grosbach Date: Tue Dec 20 16:26:38 2011 New Revision: 147000 URL: http://llvm.org/viewvc/llvm-project?rev=147000&view=rev Log: Move comment to appropriate place. Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp?rev=147000&r1=146999&r2=147000&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp (original) +++ llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Tue Dec 20 16:26:38 2011 @@ -4297,7 +4297,6 @@ Error(Parser.getTok().getLoc(), "unexpected token in operand"); return true; case AsmToken::Identifier: { - // If this is VMRS, check for the apsr_nzcv operand. if (!tryParseRegisterWithWriteBack(Operands)) return false; int Res = tryParseShiftRegister(Operands); @@ -4305,6 +4304,7 @@ return false; else if (Res == -1) // irrecoverable error return true; + // If this is VMRS, check for the apsr_nzcv operand. if (Mnemonic == "vmrs" && Parser.getTok().getString() == "apsr_nzcv") { S = Parser.getTok().getLoc(); Parser.Lex(); From ahatanaka at mips.com Tue Dec 20 16:33:53 2011 From: ahatanaka at mips.com (Akira Hatanaka) Date: Tue, 20 Dec 2011 22:33:53 -0000 Subject: [llvm-commits] [llvm] r147001 - /llvm/trunk/lib/Target/Mips/MipsInstrInfo.td Message-ID: <20111220223353.6447C2A6C12C@llvm.org> Author: ahatanak Date: Tue Dec 20 16:33:53 2011 New Revision: 147001 URL: http://llvm.org/viewvc/llvm-project?rev=147001&view=rev Log: Add patterns for matching extloads with 64-bit address. The patterns are enabled only when the target ABI is N64. Modified: llvm/trunk/lib/Target/Mips/MipsInstrInfo.td Modified: llvm/trunk/lib/Target/Mips/MipsInstrInfo.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsInstrInfo.td?rev=147001&r1=147000&r2=147001&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/MipsInstrInfo.td (original) +++ llvm/trunk/lib/Target/Mips/MipsInstrInfo.td Tue Dec 20 16:33:53 2011 @@ -1008,11 +1008,19 @@ def : Pat<(not CPURegs:$in), (NOR CPURegs:$in, ZERO)>; -// extended load and stores -def : Pat<(extloadi1 addr:$src), (LBu addr:$src)>; -def : Pat<(extloadi8 addr:$src), (LBu addr:$src)>; -def : Pat<(extloadi16_a addr:$src), (LHu addr:$src)>; -def : Pat<(extloadi16_u addr:$src), (ULHu addr:$src)>; +// extended loads +let Predicates = [NotN64] in { + def : Pat<(i32 (extloadi1 addr:$src)), (LBu addr:$src)>; + def : Pat<(i32 (extloadi8 addr:$src)), (LBu addr:$src)>; + def : Pat<(i32 (extloadi16_a addr:$src)), (LHu addr:$src)>; + def : Pat<(i32 (extloadi16_u addr:$src)), (ULHu addr:$src)>; +} +let Predicates = [IsN64] in { + def : Pat<(i32 (extloadi1 addr:$src)), (LBu_P8 addr:$src)>; + def : Pat<(i32 (extloadi8 addr:$src)), (LBu_P8 addr:$src)>; + def : Pat<(i32 (extloadi16_a addr:$src)), (LHu_P8 addr:$src)>; + def : Pat<(i32 (extloadi16_u addr:$src)), (ULHu_P8 addr:$src)>; +} // peepholes def : Pat<(store (i32 0), addr:$dst), (SW ZERO, addr:$dst)>, From ahatanaka at mips.com Tue Dec 20 16:36:08 2011 From: ahatanaka at mips.com (Akira Hatanaka) Date: Tue, 20 Dec 2011 22:36:08 -0000 Subject: [llvm-commits] [llvm] r147003 - /llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td Message-ID: <20111220223609.070D62A6C12C@llvm.org> Author: ahatanak Date: Tue Dec 20 16:36:08 2011 New Revision: 147003 URL: http://llvm.org/viewvc/llvm-project?rev=147003&view=rev Log: Add 64-bit extload patterns. Modified: llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td Modified: llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td?rev=147003&r1=147002&r2=147003&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td (original) +++ llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td Tue Dec 20 16:36:08 2011 @@ -240,11 +240,21 @@ // extended loads let Predicates = [NotN64] in { - def : Pat<(extloadi32_a addr:$a), (DSRL (DSLL (LW64 addr:$a), 32), 32)>; + def : Pat<(i64 (extloadi1 addr:$src)), (LB64 addr:$src)>; + def : Pat<(i64 (extloadi8 addr:$src)), (LB64 addr:$src)>; + def : Pat<(i64 (extloadi16_a addr:$src)), (LH64 addr:$src)>; + def : Pat<(i64 (extloadi16_u addr:$src)), (ULH64 addr:$src)>; + def : Pat<(i64 (extloadi32_a addr:$src)), (LW64 addr:$src)>; + def : Pat<(i64 (extloadi32_u addr:$src)), (ULW64 addr:$src)>; def : Pat<(zextloadi32_u addr:$a), (DSRL (DSLL (ULW64 addr:$a), 32), 32)>; } let Predicates = [IsN64] in { - def : Pat<(extloadi32_a addr:$a), (DSRL (DSLL (LW64_P8 addr:$a), 32), 32)>; + def : Pat<(i64 (extloadi1 addr:$src)), (LB64_P8 addr:$src)>; + def : Pat<(i64 (extloadi8 addr:$src)), (LB64_P8 addr:$src)>; + def : Pat<(i64 (extloadi16_a addr:$src)), (LH64_P8 addr:$src)>; + def : Pat<(i64 (extloadi16_u addr:$src)), (ULH64_P8 addr:$src)>; + def : Pat<(i64 (extloadi32_a addr:$src)), (LW64_P8 addr:$src)>; + def : Pat<(i64 (extloadi32_u addr:$src)), (ULW64_P8 addr:$src)>; def : Pat<(zextloadi32_u addr:$a), (DSRL (DSLL (ULW64_P8 addr:$a), 32), 32)>; } From ahatanaka at mips.com Tue Dec 20 16:40:40 2011 From: ahatanaka at mips.com (Akira Hatanaka) Date: Tue, 20 Dec 2011 22:40:40 -0000 Subject: [llvm-commits] [llvm] r147004 - in /llvm/trunk: lib/Target/Mips/Mips64InstrInfo.td test/CodeGen/Mips/mips64ext.ll Message-ID: <20111220224040.B1A9F2A6C12C@llvm.org> Author: ahatanak Date: Tue Dec 20 16:40:40 2011 New Revision: 147004 URL: http://llvm.org/viewvc/llvm-project?rev=147004&view=rev Log: 32-to-64-bit sext_inreg pattern. Modified: llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td llvm/trunk/test/CodeGen/Mips/mips64ext.ll Modified: llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td?rev=147004&r1=147003&r2=147004&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td (original) +++ llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td Tue Dec 20 16:40:40 2011 @@ -215,6 +215,8 @@ def SLL64_32 : FR<0x0, 0x00, (outs CPU64Regs:$rd), (ins CPURegs:$rt), "sll\t$rd, $rt, 0", [], IIAlu>; +def SLL64_64 : FR<0x0, 0x00, (outs CPU64Regs:$rd), (ins CPU64Regs:$rt), + "sll\t$rd, $rt, 0", [], IIAlu>; //===----------------------------------------------------------------------===// // Arbitrary patterns that map to one or more instructions @@ -311,3 +313,6 @@ def : Pat<(i64 (zext CPURegs:$src)), (DSRL (DSLL64_32 CPURegs:$src), 32)>; def : Pat<(i64 (sext CPURegs:$src)), (SLL64_32 CPURegs:$src)>; +// Sign extend in register +def : Pat<(i64 (sext_inreg CPU64Regs:$src, i32)), (SLL64_64 CPU64Regs:$src)>; + Modified: llvm/trunk/test/CodeGen/Mips/mips64ext.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/mips64ext.ll?rev=147004&r1=147003&r2=147004&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/Mips/mips64ext.ll (original) +++ llvm/trunk/test/CodeGen/Mips/mips64ext.ll Tue Dec 20 16:40:40 2011 @@ -9,3 +9,11 @@ %conv = zext i32 %add to i64 ret i64 %conv } + +define i64 @sext64_32(i32 %a) nounwind readnone { +entry: +; CHECK: sll ${{[0-9]+}}, ${{[0-9]+}}, 0 + %conv = sext i32 %a to i64 + ret i64 %conv +} + From ahatanaka at mips.com Tue Dec 20 16:52:19 2011 From: ahatanaka at mips.com (Akira Hatanaka) Date: Tue, 20 Dec 2011 22:52:19 -0000 Subject: [llvm-commits] [llvm] r147005 - in /llvm/trunk: lib/Target/Mips/MCTargetDesc/MipsMCAsmInfo.cpp test/CodeGen/Mips/mips64directive.ll Message-ID: <20111220225219.83D572A6C12C@llvm.org> Author: ahatanak Date: Tue Dec 20 16:52:19 2011 New Revision: 147005 URL: http://llvm.org/viewvc/llvm-project?rev=147005&view=rev Log: 64-bit data directive. Added: llvm/trunk/test/CodeGen/Mips/mips64directive.ll Modified: llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsMCAsmInfo.cpp Modified: llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsMCAsmInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsMCAsmInfo.cpp?rev=147005&r1=147004&r2=147005&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsMCAsmInfo.cpp (original) +++ llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsMCAsmInfo.cpp Tue Dec 20 16:52:19 2011 @@ -27,7 +27,7 @@ AlignmentIsInBytes = false; Data16bitsDirective = "\t.2byte\t"; Data32bitsDirective = "\t.4byte\t"; - Data64bitsDirective = 0; + Data64bitsDirective = "\t.8byte\t"; PrivateGlobalPrefix = "$"; CommentString = "#"; ZeroDirective = "\t.space\t"; Added: llvm/trunk/test/CodeGen/Mips/mips64directive.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/mips64directive.ll?rev=147005&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/Mips/mips64directive.ll (added) +++ llvm/trunk/test/CodeGen/Mips/mips64directive.ll Tue Dec 20 16:52:19 2011 @@ -0,0 +1,11 @@ +; RUN: llc < %s -march=mips64el -mcpu=mips64 -mattr=n64 | FileCheck %s + + at gl = global i64 1250999896321, align 8 + +; CHECK: 8byte +define i64 @foo1() nounwind readonly { +entry: + %0 = load i64* @gl, align 8 + ret i64 %0 +} + From ahatanaka at mips.com Tue Dec 20 16:58:01 2011 From: ahatanaka at mips.com (Akira Hatanaka) Date: Tue, 20 Dec 2011 22:58:01 -0000 Subject: [llvm-commits] [llvm] r147007 - /llvm/trunk/lib/Target/Mips/MipsISelDAGToDAG.cpp Message-ID: <20111220225801.AF76E2A6C12C@llvm.org> Author: ahatanak Date: Tue Dec 20 16:58:01 2011 New Revision: 147007 URL: http://llvm.org/viewvc/llvm-project?rev=147007&view=rev Log: Fix indentation. Modified: llvm/trunk/lib/Target/Mips/MipsISelDAGToDAG.cpp Modified: llvm/trunk/lib/Target/Mips/MipsISelDAGToDAG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsISelDAGToDAG.cpp?rev=147007&r1=147006&r2=147007&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/MipsISelDAGToDAG.cpp (original) +++ llvm/trunk/lib/Target/Mips/MipsISelDAGToDAG.cpp Tue Dec 20 16:58:01 2011 @@ -196,141 +196,141 @@ // tablegen selection should be handled here. /// switch(Opcode) { - default: break; + default: break; - case ISD::SUBE: - case ISD::ADDE: { - SDValue InFlag = Node->getOperand(2), CmpLHS; - unsigned Opc = InFlag.getOpcode(); (void)Opc; - assert(((Opc == ISD::ADDC || Opc == ISD::ADDE) || - (Opc == ISD::SUBC || Opc == ISD::SUBE)) && - "(ADD|SUB)E flag operand must come from (ADD|SUB)C/E insn"); - - unsigned MOp; - if (Opcode == ISD::ADDE) { - CmpLHS = InFlag.getValue(0); - MOp = Mips::ADDu; - } else { - CmpLHS = InFlag.getOperand(0); - MOp = Mips::SUBu; - } + case ISD::SUBE: + case ISD::ADDE: { + SDValue InFlag = Node->getOperand(2), CmpLHS; + unsigned Opc = InFlag.getOpcode(); (void)Opc; + assert(((Opc == ISD::ADDC || Opc == ISD::ADDE) || + (Opc == ISD::SUBC || Opc == ISD::SUBE)) && + "(ADD|SUB)E flag operand must come from (ADD|SUB)C/E insn"); + + unsigned MOp; + if (Opcode == ISD::ADDE) { + CmpLHS = InFlag.getValue(0); + MOp = Mips::ADDu; + } else { + CmpLHS = InFlag.getOperand(0); + MOp = Mips::SUBu; + } - SDValue Ops[] = { CmpLHS, InFlag.getOperand(1) }; + SDValue Ops[] = { CmpLHS, InFlag.getOperand(1) }; - SDValue LHS = Node->getOperand(0); - SDValue RHS = Node->getOperand(1); + SDValue LHS = Node->getOperand(0); + SDValue RHS = Node->getOperand(1); - EVT VT = LHS.getValueType(); - SDNode *Carry = CurDAG->getMachineNode(Mips::SLTu, dl, VT, Ops, 2); - SDNode *AddCarry = CurDAG->getMachineNode(Mips::ADDu, dl, VT, - SDValue(Carry,0), RHS); + EVT VT = LHS.getValueType(); + SDNode *Carry = CurDAG->getMachineNode(Mips::SLTu, dl, VT, Ops, 2); + SDNode *AddCarry = CurDAG->getMachineNode(Mips::ADDu, dl, VT, + SDValue(Carry,0), RHS); - return CurDAG->SelectNodeTo(Node, MOp, VT, MVT::Glue, - LHS, SDValue(AddCarry,0)); - } + return CurDAG->SelectNodeTo(Node, MOp, VT, MVT::Glue, + LHS, SDValue(AddCarry,0)); + } - /// Mul with two results - case ISD::SMUL_LOHI: - case ISD::UMUL_LOHI: { - assert(Node->getValueType(0) != MVT::i64 && - "64-bit multiplication with two results not handled."); - SDValue Op1 = Node->getOperand(0); - SDValue Op2 = Node->getOperand(1); - - unsigned Op; - Op = (Opcode == ISD::UMUL_LOHI ? Mips::MULTu : Mips::MULT); - - SDNode *Mul = CurDAG->getMachineNode(Op, dl, MVT::Glue, Op1, Op2); - - SDValue InFlag = SDValue(Mul, 0); - SDNode *Lo = CurDAG->getMachineNode(Mips::MFLO, dl, MVT::i32, - MVT::Glue, InFlag); - InFlag = SDValue(Lo,1); - SDNode *Hi = CurDAG->getMachineNode(Mips::MFHI, dl, MVT::i32, InFlag); + /// Mul with two results + case ISD::SMUL_LOHI: + case ISD::UMUL_LOHI: { + assert(Node->getValueType(0) != MVT::i64 && + "64-bit multiplication with two results not handled."); + SDValue Op1 = Node->getOperand(0); + SDValue Op2 = Node->getOperand(1); + + unsigned Op; + Op = (Opcode == ISD::UMUL_LOHI ? Mips::MULTu : Mips::MULT); + + SDNode *Mul = CurDAG->getMachineNode(Op, dl, MVT::Glue, Op1, Op2); + + SDValue InFlag = SDValue(Mul, 0); + SDNode *Lo = CurDAG->getMachineNode(Mips::MFLO, dl, MVT::i32, + MVT::Glue, InFlag); + InFlag = SDValue(Lo,1); + SDNode *Hi = CurDAG->getMachineNode(Mips::MFHI, dl, MVT::i32, InFlag); - if (!SDValue(Node, 0).use_empty()) - ReplaceUses(SDValue(Node, 0), SDValue(Lo,0)); + if (!SDValue(Node, 0).use_empty()) + ReplaceUses(SDValue(Node, 0), SDValue(Lo,0)); - if (!SDValue(Node, 1).use_empty()) - ReplaceUses(SDValue(Node, 1), SDValue(Hi,0)); + if (!SDValue(Node, 1).use_empty()) + ReplaceUses(SDValue(Node, 1), SDValue(Hi,0)); - return NULL; - } + return NULL; + } - /// Special Muls - case ISD::MUL: - // Mips32 has a 32-bit three operand mul instruction. - if (Subtarget.hasMips32() && Node->getValueType(0) == MVT::i32) - break; - case ISD::MULHS: - case ISD::MULHU: { - assert((Opcode == ISD::MUL || Node->getValueType(0) != MVT::i64) && - "64-bit MULH* not handled."); - EVT Ty = Node->getValueType(0); - SDValue MulOp1 = Node->getOperand(0); - SDValue MulOp2 = Node->getOperand(1); - - unsigned MulOp = (Opcode == ISD::MULHU ? - Mips::MULTu : - (Ty == MVT::i32 ? Mips::MULT : Mips::DMULT)); - SDNode *MulNode = CurDAG->getMachineNode(MulOp, dl, - MVT::Glue, MulOp1, MulOp2); - - SDValue InFlag = SDValue(MulNode, 0); - - if (Opcode == ISD::MUL) { - unsigned Opc = (Ty == MVT::i32 ? Mips::MFLO : Mips::MFLO64); - return CurDAG->getMachineNode(Opc, dl, Ty, InFlag); - } - else - return CurDAG->getMachineNode(Mips::MFHI, dl, MVT::i32, InFlag); + /// Special Muls + case ISD::MUL: + // Mips32 has a 32-bit three operand mul instruction. + if (Subtarget.hasMips32() && Node->getValueType(0) == MVT::i32) + break; + case ISD::MULHS: + case ISD::MULHU: { + assert((Opcode == ISD::MUL || Node->getValueType(0) != MVT::i64) && + "64-bit MULH* not handled."); + EVT Ty = Node->getValueType(0); + SDValue MulOp1 = Node->getOperand(0); + SDValue MulOp2 = Node->getOperand(1); + + unsigned MulOp = (Opcode == ISD::MULHU ? + Mips::MULTu : + (Ty == MVT::i32 ? Mips::MULT : Mips::DMULT)); + SDNode *MulNode = CurDAG->getMachineNode(MulOp, dl, + MVT::Glue, MulOp1, MulOp2); + + SDValue InFlag = SDValue(MulNode, 0); + + if (Opcode == ISD::MUL) { + unsigned Opc = (Ty == MVT::i32 ? Mips::MFLO : Mips::MFLO64); + return CurDAG->getMachineNode(Opc, dl, Ty, InFlag); } + else + return CurDAG->getMachineNode(Mips::MFHI, dl, MVT::i32, InFlag); + } - // Get target GOT address. - case ISD::GLOBAL_OFFSET_TABLE: - return getGlobalBaseReg(); - - case ISD::ConstantFP: { - ConstantFPSDNode *CN = dyn_cast(Node); - if (Node->getValueType(0) == MVT::f64 && CN->isExactlyValue(+0.0)) { - if (Subtarget.hasMips64()) { - SDValue Zero = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl, - Mips::ZERO_64, MVT::i64); - return CurDAG->getMachineNode(Mips::DMTC1, dl, MVT::f64, Zero); - } - + // Get target GOT address. + case ISD::GLOBAL_OFFSET_TABLE: + return getGlobalBaseReg(); + + case ISD::ConstantFP: { + ConstantFPSDNode *CN = dyn_cast(Node); + if (Node->getValueType(0) == MVT::f64 && CN->isExactlyValue(+0.0)) { + if (Subtarget.hasMips64()) { SDValue Zero = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl, - Mips::ZERO, MVT::i32); - return CurDAG->getMachineNode(Mips::BuildPairF64, dl, MVT::f64, Zero, - Zero); + Mips::ZERO_64, MVT::i64); + return CurDAG->getMachineNode(Mips::DMTC1, dl, MVT::f64, Zero); } - break; + + SDValue Zero = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl, + Mips::ZERO, MVT::i32); + return CurDAG->getMachineNode(Mips::BuildPairF64, dl, MVT::f64, Zero, + Zero); } + break; + } - case MipsISD::ThreadPointer: { - EVT PtrVT = TLI.getPointerTy(); - unsigned RdhwrOpc, SrcReg, DestReg; - - if (PtrVT == MVT::i32) { - RdhwrOpc = Mips::RDHWR; - SrcReg = Mips::HWR29; - DestReg = Mips::V1; - } else { - RdhwrOpc = Mips::RDHWR64; - SrcReg = Mips::HWR29_64; - DestReg = Mips::V1_64; - } - - SDNode *Rdhwr = - CurDAG->getMachineNode(RdhwrOpc, Node->getDebugLoc(), - Node->getValueType(0), - CurDAG->getRegister(SrcReg, PtrVT)); - SDValue Chain = CurDAG->getCopyToReg(CurDAG->getEntryNode(), dl, DestReg, - SDValue(Rdhwr, 0)); - SDValue ResNode = CurDAG->getCopyFromReg(Chain, dl, DestReg, PtrVT); - ReplaceUses(SDValue(Node, 0), ResNode); - return ResNode.getNode(); + case MipsISD::ThreadPointer: { + EVT PtrVT = TLI.getPointerTy(); + unsigned RdhwrOpc, SrcReg, DestReg; + + if (PtrVT == MVT::i32) { + RdhwrOpc = Mips::RDHWR; + SrcReg = Mips::HWR29; + DestReg = Mips::V1; + } else { + RdhwrOpc = Mips::RDHWR64; + SrcReg = Mips::HWR29_64; + DestReg = Mips::V1_64; } + + SDNode *Rdhwr = + CurDAG->getMachineNode(RdhwrOpc, Node->getDebugLoc(), + Node->getValueType(0), + CurDAG->getRegister(SrcReg, PtrVT)); + SDValue Chain = CurDAG->getCopyToReg(CurDAG->getEntryNode(), dl, DestReg, + SDValue(Rdhwr, 0)); + SDValue ResNode = CurDAG->getCopyFromReg(Chain, dl, DestReg, PtrVT); + ReplaceUses(SDValue(Node, 0), ResNode); + return ResNode.getNode(); + } } // Select the default instruction From chandlerc at google.com Tue Dec 20 17:09:25 2011 From: chandlerc at google.com (Chandler Carruth) Date: Tue, 20 Dec 2011 15:09:25 -0800 Subject: [llvm-commits] [llvm] r146977 - /llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp In-Reply-To: <20111220173813.0BD732A6C12C@llvm.org> References: <20111220173813.0BD732A6C12C@llvm.org> Message-ID: Cool! On Tue, Dec 20, 2011 at 9:38 AM, Jason W Kim wrote: > First steps in ARM AsmParser support for .eabi_attribute and .arch > (Both used for Linux gnueabi) > No behavioral change yet (no tests need so far) > Why no tests needed? We should have tests that just exercise the parsing, no? If not, I think it would be good to wait on commit until enough functionality is there to at least have a sanity test. Essentially, you should have enough tests here to ensure you didn't commit an 'abort()' or a divide by zero. -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20111220/138d1670/attachment.html From ahatanaka at mips.com Tue Dec 20 17:10:57 2011 From: ahatanaka at mips.com (Akira Hatanaka) Date: Tue, 20 Dec 2011 23:10:57 -0000 Subject: [llvm-commits] [llvm] r147008 - in /llvm/trunk: lib/Target/Mips/MipsISelDAGToDAG.cpp test/CodeGen/Mips/mips64muldiv.ll Message-ID: <20111220231057.6CE0D2A6C12C@llvm.org> Author: ahatanak Date: Tue Dec 20 17:10:57 2011 New Revision: 147008 URL: http://llvm.org/viewvc/llvm-project?rev=147008&view=rev Log: Add function MipsDAGToDAGISel::SelectMULT and factor out code that generates nodes needed for multiplication. Add code for selecting 64-bit MULHS and MULHU nodes. Modified: llvm/trunk/lib/Target/Mips/MipsISelDAGToDAG.cpp llvm/trunk/test/CodeGen/Mips/mips64muldiv.ll Modified: llvm/trunk/lib/Target/Mips/MipsISelDAGToDAG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsISelDAGToDAG.cpp?rev=147008&r1=147007&r2=147008&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/MipsISelDAGToDAG.cpp (original) +++ llvm/trunk/lib/Target/Mips/MipsISelDAGToDAG.cpp Tue Dec 20 17:10:57 2011 @@ -81,6 +81,10 @@ } SDNode *getGlobalBaseReg(); + + std::pair SelectMULT(SDNode *N, unsigned Opc, DebugLoc dl, + EVT Ty, bool HasLo, bool HasHi); + SDNode *Select(SDNode *N); // Complex Pattern. @@ -176,6 +180,28 @@ return true; } +/// Select multiply instructions. +std::pair +MipsDAGToDAGISel::SelectMULT(SDNode *N, unsigned Opc, DebugLoc dl, EVT Ty, + bool HasLo, bool HasHi) { + SDNode *Lo, *Hi; + SDNode *Mul = CurDAG->getMachineNode(Opc, dl, MVT::Glue, N->getOperand(0), + N->getOperand(1)); + SDValue InFlag = SDValue(Mul, 0); + + if (HasLo) { + Lo = CurDAG->getMachineNode(Ty == MVT::i32 ? Mips::MFLO : Mips::MFLO64, dl, + Ty, MVT::Glue, InFlag); + InFlag = SDValue(Lo, 1); + } + if (HasHi) + Hi = CurDAG->getMachineNode(Ty == MVT::i32 ? Mips::MFHI : Mips::MFHI64, dl, + Ty, InFlag); + + return std::make_pair(Lo, Hi); +} + + /// Select instructions not customized! Used for /// expanded, promoted and normal instructions SDNode* MipsDAGToDAGISel::Select(SDNode *Node) { @@ -195,6 +221,9 @@ // Instruction Selection not handled by the auto-generated // tablegen selection should be handled here. /// + EVT NodeTy = Node->getValueType(0); + unsigned MultOpc; + switch(Opcode) { default: break; @@ -232,58 +261,39 @@ /// Mul with two results case ISD::SMUL_LOHI: case ISD::UMUL_LOHI: { - assert(Node->getValueType(0) != MVT::i64 && - "64-bit multiplication with two results not handled."); - SDValue Op1 = Node->getOperand(0); - SDValue Op2 = Node->getOperand(1); - - unsigned Op; - Op = (Opcode == ISD::UMUL_LOHI ? Mips::MULTu : Mips::MULT); - - SDNode *Mul = CurDAG->getMachineNode(Op, dl, MVT::Glue, Op1, Op2); - - SDValue InFlag = SDValue(Mul, 0); - SDNode *Lo = CurDAG->getMachineNode(Mips::MFLO, dl, MVT::i32, - MVT::Glue, InFlag); - InFlag = SDValue(Lo,1); - SDNode *Hi = CurDAG->getMachineNode(Mips::MFHI, dl, MVT::i32, InFlag); + if (NodeTy == MVT::i32) + MultOpc = (Opcode == ISD::UMUL_LOHI ? Mips::MULTu : Mips::MULT); + else + MultOpc = (Opcode == ISD::UMUL_LOHI ? Mips::DMULTu : Mips::DMULT); + + std::pair LoHi = SelectMULT(Node, MultOpc, dl, NodeTy, + true, true); if (!SDValue(Node, 0).use_empty()) - ReplaceUses(SDValue(Node, 0), SDValue(Lo,0)); + ReplaceUses(SDValue(Node, 0), SDValue(LoHi.first, 0)); if (!SDValue(Node, 1).use_empty()) - ReplaceUses(SDValue(Node, 1), SDValue(Hi,0)); + ReplaceUses(SDValue(Node, 1), SDValue(LoHi.second, 0)); return NULL; } /// Special Muls - case ISD::MUL: + case ISD::MUL: { // Mips32 has a 32-bit three operand mul instruction. - if (Subtarget.hasMips32() && Node->getValueType(0) == MVT::i32) + if (Subtarget.hasMips32() && NodeTy == MVT::i32) break; + return SelectMULT(Node, NodeTy == MVT::i32 ? Mips::MULT : Mips::DMULT, + dl, NodeTy, true, false).first; + } case ISD::MULHS: case ISD::MULHU: { - assert((Opcode == ISD::MUL || Node->getValueType(0) != MVT::i64) && - "64-bit MULH* not handled."); - EVT Ty = Node->getValueType(0); - SDValue MulOp1 = Node->getOperand(0); - SDValue MulOp2 = Node->getOperand(1); - - unsigned MulOp = (Opcode == ISD::MULHU ? - Mips::MULTu : - (Ty == MVT::i32 ? Mips::MULT : Mips::DMULT)); - SDNode *MulNode = CurDAG->getMachineNode(MulOp, dl, - MVT::Glue, MulOp1, MulOp2); - - SDValue InFlag = SDValue(MulNode, 0); - - if (Opcode == ISD::MUL) { - unsigned Opc = (Ty == MVT::i32 ? Mips::MFLO : Mips::MFLO64); - return CurDAG->getMachineNode(Opc, dl, Ty, InFlag); - } + if (NodeTy == MVT::i32) + MultOpc = (Opcode == ISD::MULHU ? Mips::MULTu : Mips::MULT); else - return CurDAG->getMachineNode(Mips::MFHI, dl, MVT::i32, InFlag); + MultOpc = (Opcode == ISD::MULHU ? Mips::DMULTu : Mips::DMULT); + + return SelectMULT(Node, MultOpc, dl, NodeTy, false, true).second; } // Get target GOT address. Modified: llvm/trunk/test/CodeGen/Mips/mips64muldiv.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/mips64muldiv.ll?rev=147008&r1=147007&r2=147008&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/Mips/mips64muldiv.ll (original) +++ llvm/trunk/test/CodeGen/Mips/mips64muldiv.ll Tue Dec 20 17:10:57 2011 @@ -8,6 +8,14 @@ ret i64 %mul } +define i64 @m1(i64 %a) nounwind readnone { +entry: +; CHECK: dmult +; CHECK: mfhi + %div = sdiv i64 %a, 3 + ret i64 %div +} + define i64 @d0(i64 %a0, i64 %a1) nounwind readnone { entry: ; CHECK: ddivu From grosbach at apple.com Tue Dec 20 17:11:01 2011 From: grosbach at apple.com (Jim Grosbach) Date: Tue, 20 Dec 2011 23:11:01 -0000 Subject: [llvm-commits] [llvm] r147009 - /llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Message-ID: <20111220231101.32FB52A6C12C@llvm.org> Author: grosbach Date: Tue Dec 20 17:11:00 2011 New Revision: 147009 URL: http://llvm.org/viewvc/llvm-project?rev=147009&view=rev Log: ARM .req register name aliases are case insensitive, just like regnames. Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp?rev=147009&r1=147008&r2=147009&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp (original) +++ llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Tue Dec 20 17:11:00 2011 @@ -2325,9 +2325,10 @@ .Default(0); } if (!RegNum) { - // Check for aliases registered via .req. - StringMap::const_iterator Entry = - RegisterReqs.find(Tok.getIdentifier()); + // Check for aliases registered via .req. Canonicalize to lower case. + // That's more consistent since register names are case insensitive, and + // it's how the original entry was passed in from MC/MCParser/AsmParser. + StringMap::const_iterator Entry = RegisterReqs.find(lowerCase); // If no match, return failure. if (Entry == RegisterReqs.end()) return -1; From chandlerc at google.com Tue Dec 20 17:16:35 2011 From: chandlerc at google.com (Chandler Carruth) Date: Tue, 20 Dec 2011 15:16:35 -0800 Subject: [llvm-commits] PATCH: remove unused variable TheError In-Reply-To: References: Message-ID: On Tue, Dec 20, 2011 at 6:54 AM, Manuel Klimek wrote: > While searching for an example to model my use of SourceMgr after, I > stumbled over LLLexer.h and found what looks like an unused variable - > this patch would remove it, if there's not some hidden use of TheError > that I'm missing. > Looks good. As long as this kind of change doesn't break the build in some way, always feel free to commit as "obvious". > > diff --git a/lib/AsmParser/LLLexer.h b/lib/AsmParser/LLLexer.h > index 33b9135..09aea5b 100644 > --- a/lib/AsmParser/LLLexer.h > +++ b/lib/AsmParser/LLLexer.h > @@ -42,7 +42,6 @@ namespace llvm { > APFloat APFloatVal; > APSInt APSIntVal; > > - std::string TheError; > public: > explicit LLLexer(MemoryBuffer *StartBuf, SourceMgr &SM, SMDiagnostic &, > LLVMContext &C); > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits > -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20111220/503fabca/attachment.html From sabre at nondot.org Tue Dec 20 17:14:57 2011 From: sabre at nondot.org (Chris Lattner) Date: Tue, 20 Dec 2011 23:14:57 -0000 Subject: [llvm-commits] [llvm] r147010 - /llvm/trunk/lib/Linker/LinkModules.cpp Message-ID: <20111220231457.AE3482A6C12C@llvm.org> Author: lattner Date: Tue Dec 20 17:14:57 2011 New Revision: 147010 URL: http://llvm.org/viewvc/llvm-project?rev=147010&view=rev Log: Fix a nasty bug in the type remapping stuff that I added that is breaking kc++ on the build bot in some cases. The basic issue happens when a source module contains both a "%foo" type and a "%foo.42" type. It will see the later one, check to see if the destination module contains a "%foo" type, and it will return true... because both the source and destination modules are in the same LLVMContext. We don't want to map source types to other source types, so don't do the remapping if the mapped type came from the source module. Unfortunately, I've been unable to reduce a decent testcase for this, kc++ is pretty great that way. Modified: llvm/trunk/lib/Linker/LinkModules.cpp Modified: llvm/trunk/lib/Linker/LinkModules.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Linker/LinkModules.cpp?rev=147010&r1=147009&r2=147010&view=diff ============================================================================== --- llvm/trunk/lib/Linker/LinkModules.cpp (original) +++ llvm/trunk/lib/Linker/LinkModules.cpp Tue Dec 20 17:14:57 2011 @@ -148,6 +148,7 @@ if (PointerType *PT = dyn_cast(DstTy)) { if (PT->getAddressSpace() != cast(SrcTy)->getAddressSpace()) return false; + } else if (FunctionType *FT = dyn_cast(DstTy)) { if (FT->isVarArg() != cast(SrcTy)->isVarArg()) return false; @@ -567,6 +568,9 @@ std::vector SrcStructTypes; SrcM->findUsedStructTypes(SrcStructTypes); + SmallPtrSet SrcStructTypesSet(SrcStructTypes.begin(), + SrcStructTypes.end()); + for (unsigned i = 0, e = SrcStructTypes.size(); i != e; ++i) { StructType *ST = SrcStructTypes[i]; if (!ST->hasName()) continue; @@ -579,7 +583,10 @@ // Check to see if the destination module has a struct with the prefix name. if (StructType *DST = DstM->getTypeByName(ST->getName().substr(0, DotPos))) - TypeMap.addTypeMapping(DST, ST); + // Don't use it if this actually came from the source module. They're in + // the same LLVMContext after all. + if (!SrcStructTypesSet.count(DST)) + TypeMap.addTypeMapping(DST, ST); } From grosbach at apple.com Tue Dec 20 17:20:00 2011 From: grosbach at apple.com (Jim Grosbach) Date: Tue, 20 Dec 2011 23:20:00 -0000 Subject: [llvm-commits] [llvm] r147011 - /llvm/trunk/test/MC/ARM/neont2-mul-encoding.s Message-ID: <20111220232000.9ADDF2A6C12C@llvm.org> Author: grosbach Date: Tue Dec 20 17:20:00 2011 New Revision: 147011 URL: http://llvm.org/viewvc/llvm-project?rev=147011&view=rev Log: Enable and fix a test. Modified: llvm/trunk/test/MC/ARM/neont2-mul-encoding.s Modified: llvm/trunk/test/MC/ARM/neont2-mul-encoding.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/neont2-mul-encoding.s?rev=147011&r1=147010&r2=147011&view=diff ============================================================================== --- llvm/trunk/test/MC/ARM/neont2-mul-encoding.s (original) +++ llvm/trunk/test/MC/ARM/neont2-mul-encoding.s Tue Dec 20 17:20:00 2011 @@ -70,9 +70,9 @@ vqdmull.s16 q8, d16, d17 vqdmull.s32 q8, d16, d17 -@ vqdmull.s16 q1, d7, d1[1] + vqdmull.s16 q1, d7, d1[1] @ CHECK: vqdmull.s16 q8, d16, d17 @ encoding: [0xd0,0xef,0xa1,0x0d] @ CHECK: vqdmull.s32 q8, d16, d17 @ encoding: [0xe0,0xef,0xa1,0x0d] -@ FIXME: vqdmull.s16 q1, d7, d1[1] @ encoding: [0x97,0xef,0x49,0x3b] +@ CHECK: vqdmull.s16 q1, d7, d1[1] @ encoding: [0x97,0xef,0x49,0x2b] From James.Molloy at arm.com Tue Dec 20 17:30:07 2011 From: James.Molloy at arm.com (James Molloy) Date: Tue, 20 Dec 2011 23:30:07 +0000 Subject: [llvm-commits] PATCH: remove unused variable TheError In-Reply-To: References: , Message-ID: Manuel, Do you have commit access? If not, I can commit for you. James ________________________________________ From: llvm-commits-bounces at cs.uiuc.edu [llvm-commits-bounces at cs.uiuc.edu] On Behalf Of Chandler Carruth [chandlerc at google.com] Sent: 20 December 2011 23:16 To: Manuel Klimek Cc: llvm-commits at cs.uiuc.edu Subject: Re: [llvm-commits] PATCH: remove unused variable TheError On Tue, Dec 20, 2011 at 6:54 AM, Manuel Klimek > wrote: While searching for an example to model my use of SourceMgr after, I stumbled over LLLexer.h and found what looks like an unused variable - this patch would remove it, if there's not some hidden use of TheError that I'm missing. Looks good. As long as this kind of change doesn't break the build in some way, always feel free to commit as "obvious". diff --git a/lib/AsmParser/LLLexer.h b/lib/AsmParser/LLLexer.h index 33b9135..09aea5b 100644 --- a/lib/AsmParser/LLLexer.h +++ b/lib/AsmParser/LLLexer.h @@ -42,7 +42,6 @@ namespace llvm { APFloat APFloatVal; APSInt APSIntVal; - std::string TheError; public: explicit LLLexer(MemoryBuffer *StartBuf, SourceMgr &SM, SMDiagnostic &, LLVMContext &C); _______________________________________________ llvm-commits mailing list llvm-commits at cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits -- IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you. From ahatanaka at mips.com Tue Dec 20 17:28:36 2011 From: ahatanaka at mips.com (Akira Hatanaka) Date: Tue, 20 Dec 2011 23:28:36 -0000 Subject: [llvm-commits] [llvm] r147012 - /llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp Message-ID: <20111220232836.6AE2C2A6C12C@llvm.org> Author: ahatanak Date: Tue Dec 20 17:28:36 2011 New Revision: 147012 URL: http://llvm.org/viewvc/llvm-project?rev=147012&view=rev Log: Set the correct stack pointer register that should be saved or restored. Modified: llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp Modified: llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp?rev=147012&r1=147011&r2=147012&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp (original) +++ llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp Tue Dec 20 17:28:36 2011 @@ -231,7 +231,7 @@ setMinFunctionAlignment(2); - setStackPointerRegisterToSaveRestore(Mips::SP); + setStackPointerRegisterToSaveRestore(HasMips64 ? Mips::SP_64 : Mips::SP); computeRegisterProperties(); setExceptionPointerRegister(Mips::A0); From jvoung at google.com Tue Dec 20 17:35:10 2011 From: jvoung at google.com (Jan Voung) Date: Tue, 20 Dec 2011 15:35:10 -0800 Subject: [llvm-commits] patch for "puzzle" in llvm-test suite -- use of rand (PR11629) Message-ID: For http://llvm.org/bugs/show_bug.cgi?id=11629 See attached patch. -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20111220/191e388e/attachment.html -------------- next part -------------- A non-text attachment was scrubbed... Name: puzzle_test.patch Type: text/x-patch Size: 1535 bytes Desc: not available Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20111220/191e388e/attachment.bin From ahatanaka at mips.com Tue Dec 20 17:35:46 2011 From: ahatanaka at mips.com (Akira Hatanaka) Date: Tue, 20 Dec 2011 23:35:46 -0000 Subject: [llvm-commits] [llvm] r147013 - /llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp Message-ID: <20111220233547.01D8F2A6C12C@llvm.org> Author: ahatanak Date: Tue Dec 20 17:35:46 2011 New Revision: 147013 URL: http://llvm.org/viewvc/llvm-project?rev=147013&view=rev Log: Enable custom lowering DYNAMIC_STACKALLOC nodes. Modified: llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp Modified: llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp?rev=147013&r1=147012&r2=147013&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp (original) +++ llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp Tue Dec 20 17:35:46 2011 @@ -136,6 +136,7 @@ setOperationAction(ISD::SELECT, MVT::i32, Custom); setOperationAction(ISD::BRCOND, MVT::Other, Custom); setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Custom); + setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Custom); setOperationAction(ISD::VASTART, MVT::Other, Custom); setOperationAction(ISD::SDIV, MVT::i32, Expand); From ahatanaka at mips.com Tue Dec 20 17:40:56 2011 From: ahatanaka at mips.com (Akira Hatanaka) Date: Tue, 20 Dec 2011 23:40:56 -0000 Subject: [llvm-commits] [llvm] r147014 - /llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp Message-ID: <20111220234056.69D132A6C12C@llvm.org> Author: ahatanak Date: Tue Dec 20 17:40:56 2011 New Revision: 147014 URL: http://llvm.org/viewvc/llvm-project?rev=147014&view=rev Log: 64-bit uint-fp conversion nodes are expanded. Modified: llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp Modified: llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp?rev=147014&r1=147013&r2=147014&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp (original) +++ llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp Tue Dec 20 17:40:56 2011 @@ -153,7 +153,9 @@ setOperationAction(ISD::BR_CC, MVT::Other, Expand); setOperationAction(ISD::SELECT_CC, MVT::Other, Expand); setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand); + setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand); setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand); + setOperationAction(ISD::FP_TO_UINT, MVT::i64, Expand); setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand); setOperationAction(ISD::CTPOP, MVT::i32, Expand); setOperationAction(ISD::CTTZ, MVT::i32, Expand); From ahatanaka at mips.com Tue Dec 20 17:47:45 2011 From: ahatanaka at mips.com (Akira Hatanaka) Date: Tue, 20 Dec 2011 23:47:45 -0000 Subject: [llvm-commits] [llvm] r147015 - in /llvm/trunk/lib/Target/Mips: Mips.td MipsInstrInfo.td Message-ID: <20111220234745.1A5E72A6C12C@llvm.org> Author: ahatanak Date: Tue Dec 20 17:47:44 2011 New Revision: 147015 URL: http://llvm.org/viewvc/llvm-project?rev=147015&view=rev Log: Add definition of WSBH (Word Swap Bytes within Halfwords), which is an instruction supported by mips32r2, and add a pattern which replaces bswap with a ROTR and WSBH pair. WSBW is removed since it is not an instruction the current architectures support. Modified: llvm/trunk/lib/Target/Mips/Mips.td llvm/trunk/lib/Target/Mips/MipsInstrInfo.td Modified: llvm/trunk/lib/Target/Mips/Mips.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/Mips.td?rev=147015&r1=147014&r2=147015&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/Mips.td (original) +++ llvm/trunk/lib/Target/Mips/Mips.td Tue Dec 20 17:47:44 2011 @@ -63,7 +63,7 @@ [FeatureCondMov, FeatureBitCount]>; def FeatureMips32r2 : SubtargetFeature<"mips32r2", "MipsArchVersion", "Mips32r2", "Mips32r2 ISA Support", - [FeatureMips32, FeatureSEInReg]>; + [FeatureMips32, FeatureSEInReg, FeatureSwap]>; def FeatureMips64 : SubtargetFeature<"mips64", "MipsArchVersion", "Mips64", "Mips64 ISA Support", [FeatureGP64Bit, FeatureFP64Bit, Modified: llvm/trunk/lib/Target/Mips/MipsInstrInfo.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsInstrInfo.td?rev=147015&r1=147014&r2=147015&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/MipsInstrInfo.td (original) +++ llvm/trunk/lib/Target/Mips/MipsInstrInfo.td Tue Dec 20 17:47:44 2011 @@ -625,11 +625,10 @@ let Predicates = [HasSEInReg]; } -// Byte Swap -class ByteSwap func, bits<5> sa, string instr_asm>: - FR<0x1f, func, (outs CPURegs:$rd), (ins CPURegs:$rt), - !strconcat(instr_asm, "\t$rd, $rt"), - [(set CPURegs:$rd, (bswap CPURegs:$rt))], NoItinerary> { +// Subword Swap +class SubwordSwap func, bits<5> sa, string instr_asm, RegisterClass RC>: + FR<0x1f, func, (outs RC:$rd), (ins RC:$rt), + !strconcat(instr_asm, "\t$rd, $rt"), [], NoItinerary> { let rs = 0; let shamt = sa; let Predicates = [HasSwap]; @@ -895,8 +894,8 @@ def CLZ : CountLeading0<0x20, "clz", CPURegs>; def CLO : CountLeading1<0x21, "clo", CPURegs>; -/// Byte Swap -def WSBW : ByteSwap<0x20, 0x2, "wsbw">; +/// Word Swap Bytes Within Halfwords +def WSBH : SubwordSwap<0x20, 0x2, "wsbh", CPURegs>; /// No operation let addr=0 in @@ -1104,6 +1103,9 @@ // select MipsDynAlloc def : Pat<(MipsDynAlloc addr:$f), (DynAlloc addr:$f)>; +// bswap pattern +def : Pat<(bswap CPURegs:$rt), (ROTR (WSBH CPURegs:$rt), 16)>; + //===----------------------------------------------------------------------===// // Floating Point Support //===----------------------------------------------------------------------===// From dpatel at apple.com Tue Dec 20 17:52:41 2011 From: dpatel at apple.com (Devang Patel) Date: Tue, 20 Dec 2011 15:52:41 -0800 Subject: [llvm-commits] [llvm] r146604 - in /llvm/trunk: lib/CodeGen/MachineSink.cpp test/CodeGen/ARM/2011-12-14-machine-sink.ll In-Reply-To: References: <20111214232038.E9C9D2A6C12C@llvm.org> <5FF21D31-13D7-4EAA-99FC-EFC1AFA0C8F7@apple.com> <618FAA67-0A0A-4D20-9E58-491632F2BA7C@apple.com> Message-ID: <91FF2423-D67D-4E80-985B-532E27DF3799@apple.com> Akira, On Dec 20, 2011, at 11:39 AM, Akira Hatanaka wrote: > After further investigation, I found a function that is possibly being > mis-compiled. This is what I did: > > 1. Reverted this patch (machine sinking is less conservative now). > 2. Turned off machine sinking just for the function. > > The generated executable segfaults when it is run. > > Additionally, I found that it produces the expected result and > terminates normally if I add the option "-regalloc=basic" to llc to > turn off greedy register allocation. > > Is there anything you can tell from this? Which part of the output > should I pay attention to when I am reading llc's outputs when option > -debug or -stats is provided? The function in question is fairly large > and complicated, so it is difficult to tell which part is being > mis-compiled just by looking at the machinefunction dumps or the CFGs > viewCFG and viewCFGOnly show. One alternative for you is to reproduce segfault in debugger and investigate what is being compiled. Other alternative is to narrow down the particular MI sink that is difference maker. You can do this by disabling this patch and adding a artificial threshold in Machine Sink pass to control how many instructions are sinked. One you know the critical MI sink, you can investigate how it impacts other passes, including register allocator, down the road. I am afraid, there is not any easy answer. - Devang > > On Fri, Dec 16, 2011 at 3:50 PM, Devang Patel wrote: >> >> On Dec 16, 2011, at 2:34 PM, Akira Hatanaka wrote: >> >>> The test still fails after I disable Machine Sink pass, but it passes >>> if I revert the patch (just this one, the ones checked in after this >>> remain applied). So it looks like MachineSinking is not causing the >>> failure, but there is a bug in some other part of the backend that >>> gets exposed if the pass doesn't sink instructions at all or is less >>> aggresive. >>> >>> Do you have any idea which pass might be doing something wrong? >> >> >> In the test case, which prompted this patch, machine sink pass was increasing distance between reg def and use resulting in unnecessary extra spill. >> >> However, in your particular case I have no idea what is going wrong. Finding out what exactly is miscompiled may be your best alternative. Do you see any significant (or noticeable) changes in stats for passes that follow machine sink ? >>> >>> Here are the stats: >>> >>> (before) >>> 15 machine-sink - Number of copies coalesced >>> 674 machine-sink - Number of critical edges split >>> 3397 machine-sink - Number of machine instructions sunk >>> >>> (after) >>> 15 machine-sink - Number of copies coalesced >>> 674 machine-sink - Number of critical edges split >>> 2881 machine-sink - Number of machine instructions sunk >>> >>> On Fri, Dec 16, 2011 at 9:21 AM, Devang Patel wrote: >>>> >>>> On Dec 15, 2011, at 7:55 PM, Akira Hatanaka wrote: >>>> >>>>> This commit is causing one the tests in llvm test-suite >>>>> (MultiSource/Benchmarks/tramp3d-v4) to fail. >>>>> It segfaults during execution. The target architecture is mips32r2. >>>>> >>>>> Would it be possible to revert this until we can figure out what is >>>>> causing the failure? >>>> >>>> This patch makes machine sink more conservative. Please, >>>> >>>> 1) Disable Machine Sink pass completely locally and see if the segfaults reproduces or not. >>>> 2) Enable stats and see if notice any change before and after the patch. >>>> 3) Please file bugzilla with a reproducible test case before reverting the patch. >>>> >>>> Thanks, >>>> - >>>> Devang >>>> >>>> >>>>> On Wed, Dec 14, 2011 at 3:20 PM, Devang Patel wrote: >>>>>> Author: dpatel >>>>>> Date: Wed Dec 14 17:20:38 2011 >>>>>> New Revision: 146604 >>>>>> >>>>>> URL: http://llvm.org/viewvc/llvm-project?rev=146604&view=rev >>>>>> Log: >>>>>> Do not sink instruction, if it is not profitable. >>>>>> >>>>>> On ARM, peephole optimization for ABS creates a trivial cfg triangle which tempts machine sink to sink instructions in code which is really straight line code. Sometimes this sinking may alter register allocator input such that use and def of a reg is divided by a branch in between, which may result in extra spills. Now mahine sink avoids sinking if final sink destination is post dominator. >>>>>> >>>>>> Radar 10266272. >>>>>> >>>>>> Added: >>>>>> llvm/trunk/test/CodeGen/ARM/2011-12-14-machine-sink.ll >>>>>> Modified: >>>>>> llvm/trunk/lib/CodeGen/MachineSink.cpp >>>>>> >>>>>> Modified: llvm/trunk/lib/CodeGen/MachineSink.cpp >>>>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineSink.cpp?rev=146604&r1=146603&r2=146604&view=diff >>>>>> ============================================================================== >>>>>> --- llvm/trunk/lib/CodeGen/MachineSink.cpp (original) >>>>>> +++ llvm/trunk/lib/CodeGen/MachineSink.cpp Wed Dec 14 17:20:38 2011 >>>>>> @@ -90,7 +90,11 @@ >>>>>> bool AllUsesDominatedByBlock(unsigned Reg, MachineBasicBlock *MBB, >>>>>> MachineBasicBlock *DefMBB, >>>>>> bool &BreakPHIEdge, bool &LocalUse) const; >>>>>> - MachineBasicBlock *FindSuccToSinkTo(MachineInstr *MI, bool &BreakPHIEdge); >>>>>> + MachineBasicBlock *FindSuccToSinkTo(MachineInstr *MI, MachineBasicBlock *MBB, >>>>>> + bool &BreakPHIEdge); >>>>>> + bool isProfitableToSinkTo(unsigned Reg, MachineInstr *MI, >>>>>> + MachineBasicBlock *MBB, >>>>>> + MachineBasicBlock *SuccToSinkTo); >>>>>> >>>>>> bool PerformTrivialForwardCoalescing(MachineInstr *MI, >>>>>> MachineBasicBlock *MBB); >>>>>> @@ -399,18 +403,76 @@ >>>>>> } >>>>>> } >>>>>> >>>>>> +/// isPostDominatedBy - Return true if A is post dominated by B. >>>>>> +static bool isPostDominatedBy(MachineBasicBlock *A, MachineBasicBlock *B) { >>>>>> + >>>>>> + // FIXME - Use real post dominator. >>>>>> + if (A->succ_size() != 2) >>>>>> + return false; >>>>>> + MachineBasicBlock::succ_iterator I = A->succ_begin(); >>>>>> + if (B == *I) >>>>>> + ++I; >>>>>> + MachineBasicBlock *OtherSuccBlock = *I; >>>>>> + if (OtherSuccBlock->succ_size() != 1 || >>>>>> + *(OtherSuccBlock->succ_begin()) != B) >>>>>> + return false; >>>>>> + >>>>>> + return true; >>>>>> +} >>>>>> + >>>>>> +/// isProfitableToSinkTo - Return true if it is profitable to sink MI. >>>>>> +bool MachineSinking::isProfitableToSinkTo(unsigned Reg, MachineInstr *MI, >>>>>> + MachineBasicBlock *MBB, >>>>>> + MachineBasicBlock *SuccToSinkTo) { >>>>>> + assert (MI && "Invalid MachineInstr!"); >>>>>> + assert (SuccToSinkTo && "Invalid SinkTo Candidate BB"); >>>>>> + >>>>>> + if (MBB == SuccToSinkTo) >>>>>> + return false; >>>>>> + >>>>>> + // It is profitable if SuccToSinkTo does not post dominate current block. >>>>>> + if (!isPostDominatedBy(MBB, SuccToSinkTo)) >>>>>> + return true; >>>>>> + >>>>>> + // Check if only use in post dominated block is PHI instruction. >>>>>> + bool NonPHIUse = false; >>>>>> + for (MachineRegisterInfo::use_nodbg_iterator >>>>>> + I = MRI->use_nodbg_begin(Reg), E = MRI->use_nodbg_end(); >>>>>> + I != E; ++I) { >>>>>> + MachineInstr *UseInst = &*I; >>>>>> + MachineBasicBlock *UseBlock = UseInst->getParent(); >>>>>> + if (UseBlock == SuccToSinkTo && !UseInst->isPHI()) >>>>>> + NonPHIUse = true; >>>>>> + } >>>>>> + if (!NonPHIUse) >>>>>> + return true; >>>>>> + >>>>>> + // If SuccToSinkTo post dominates then also it may be profitable if MI >>>>>> + // can further profitably sinked into another block in next round. >>>>>> + bool BreakPHIEdge = false; >>>>>> + // FIXME - If finding successor is compile time expensive then catch results. >>>>>> + if (MachineBasicBlock *MBB2 = FindSuccToSinkTo(MI, SuccToSinkTo, BreakPHIEdge)) >>>>>> + return isProfitableToSinkTo(Reg, MI, SuccToSinkTo, MBB2); >>>>>> + >>>>>> + // If SuccToSinkTo is final destination and it is a post dominator of current >>>>>> + // block then it is not profitable to sink MI into SuccToSinkTo block. >>>>>> + return false; >>>>>> +} >>>>>> + >>>>>> /// FindSuccToSinkTo - Find a successor to sink this instruction to. >>>>>> MachineBasicBlock *MachineSinking::FindSuccToSinkTo(MachineInstr *MI, >>>>>> - bool &BreakPHIEdge) { >>>>>> + MachineBasicBlock *MBB, >>>>>> + bool &BreakPHIEdge) { >>>>>> + >>>>>> + assert (MI && "Invalid MachineInstr!"); >>>>>> + assert (MBB && "Invalid MachineBasicBlock!"); >>>>>> >>>>>> // Loop over all the operands of the specified instruction. If there is >>>>>> // anything we can't handle, bail out. >>>>>> - MachineBasicBlock *ParentBlock = MI->getParent(); >>>>>> >>>>>> // SuccToSinkTo - This is the successor to sink this instruction to, once we >>>>>> // decide. >>>>>> MachineBasicBlock *SuccToSinkTo = 0; >>>>>> - >>>>>> for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { >>>>>> const MachineOperand &MO = MI->getOperand(i); >>>>>> if (!MO.isReg()) continue; // Ignore non-register operands. >>>>>> @@ -469,7 +531,7 @@ >>>>>> // If a previous operand picked a block to sink to, then this operand >>>>>> // must be sinkable to the same block. >>>>>> bool LocalUse = false; >>>>>> - if (!AllUsesDominatedByBlock(Reg, SuccToSinkTo, ParentBlock, >>>>>> + if (!AllUsesDominatedByBlock(Reg, SuccToSinkTo, MBB, >>>>>> BreakPHIEdge, LocalUse)) >>>>>> return NULL; >>>>>> >>>>>> @@ -478,11 +540,11 @@ >>>>>> >>>>>> // Otherwise, we should look at all the successors and decide which one >>>>>> // we should sink to. >>>>>> - for (MachineBasicBlock::succ_iterator SI = ParentBlock->succ_begin(), >>>>>> - E = ParentBlock->succ_end(); SI != E; ++SI) { >>>>>> - MachineBasicBlock *SuccBlock = *SI; >>>>>> + for (MachineBasicBlock::succ_iterator SI = MBB->succ_begin(), >>>>>> + E = MBB->succ_end(); SI != E; ++SI) { >>>>>> + MachineBasicBlock *SuccBlock = *SI; >>>>>> bool LocalUse = false; >>>>>> - if (AllUsesDominatedByBlock(Reg, SuccBlock, ParentBlock, >>>>>> + if (AllUsesDominatedByBlock(Reg, SuccBlock, MBB, >>>>>> BreakPHIEdge, LocalUse)) { >>>>>> SuccToSinkTo = SuccBlock; >>>>>> break; >>>>>> @@ -495,12 +557,14 @@ >>>>>> // If we couldn't find a block to sink to, ignore this instruction. >>>>>> if (SuccToSinkTo == 0) >>>>>> return NULL; >>>>>> + else if (!isProfitableToSinkTo(Reg, MI, MBB, SuccToSinkTo)) >>>>>> + return NULL; >>>>>> } >>>>>> } >>>>>> >>>>>> // It is not possible to sink an instruction into its own block. This can >>>>>> // happen with loops. >>>>>> - if (ParentBlock == SuccToSinkTo) >>>>>> + if (MBB == SuccToSinkTo) >>>>>> return NULL; >>>>>> >>>>>> // It's not safe to sink instructions to EH landing pad. Control flow into >>>>>> @@ -532,7 +596,8 @@ >>>>>> // and z and only shrink the live range of x. >>>>>> >>>>>> bool BreakPHIEdge = false; >>>>>> - MachineBasicBlock *SuccToSinkTo = FindSuccToSinkTo(MI, BreakPHIEdge); >>>>>> + MachineBasicBlock *ParentBlock = MI->getParent(); >>>>>> + MachineBasicBlock *SuccToSinkTo = FindSuccToSinkTo(MI, ParentBlock, BreakPHIEdge); >>>>>> >>>>>> // If there are no outputs, it must have side-effects. >>>>>> if (SuccToSinkTo == 0) >>>>>> @@ -553,8 +618,6 @@ >>>>>> >>>>>> DEBUG(dbgs() << "Sink instr " << *MI << "\tinto block " << *SuccToSinkTo); >>>>>> >>>>>> - MachineBasicBlock *ParentBlock = MI->getParent(); >>>>>> - >>>>>> // If the block has multiple predecessors, this would introduce computation on >>>>>> // a path that it doesn't already exist. We could split the critical edge, >>>>>> // but for now we just punt. >>>>>> >>>>>> Added: llvm/trunk/test/CodeGen/ARM/2011-12-14-machine-sink.ll >>>>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/2011-12-14-machine-sink.ll?rev=146604&view=auto >>>>>> ============================================================================== >>>>>> --- llvm/trunk/test/CodeGen/ARM/2011-12-14-machine-sink.ll (added) >>>>>> +++ llvm/trunk/test/CodeGen/ARM/2011-12-14-machine-sink.ll Wed Dec 14 17:20:38 2011 >>>>>> @@ -0,0 +1,48 @@ >>>>>> +; RUN: llc < %s -o /dev/null -stats |& FileCheck %s -check-prefix=STATS >>>>>> +; Radar 10266272 >>>>>> +target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:32:64-v128:32:128-a0:0:32-n32-S32" >>>>>> +target triple = "thumbv7-apple-ios4.0.0" >>>>>> +; STATS-NOT: machine-sink >>>>>> + >>>>>> +define i32 @foo(i32 %h) nounwind readonly ssp { >>>>>> +entry: >>>>>> + br label %for.cond >>>>>> + >>>>>> +for.cond: ; preds = %for.body, %entry >>>>>> + %cmp = icmp slt i32 0, %h >>>>>> + br i1 %cmp, label %for.body, label %if.end299 >>>>>> + >>>>>> +for.body: ; preds = %for.cond >>>>>> + %v.5 = select i1 undef, i32 undef, i32 0 >>>>>> + %0 = load i8* undef, align 1, !tbaa !0 >>>>>> + %conv88 = zext i8 %0 to i32 >>>>>> + %sub89 = sub nsw i32 0, %conv88 >>>>>> + %v.8 = select i1 undef, i32 undef, i32 %sub89 >>>>>> + %1 = load i8* null, align 1, !tbaa !0 >>>>>> + %conv108 = zext i8 %1 to i32 >>>>>> + %2 = load i8* undef, align 1, !tbaa !0 >>>>>> + %conv110 = zext i8 %2 to i32 >>>>>> + %sub111 = sub nsw i32 %conv108, %conv110 >>>>>> + %cmp112 = icmp slt i32 %sub111, 0 >>>>>> + %sub115 = sub nsw i32 0, %sub111 >>>>>> + %v.10 = select i1 %cmp112, i32 %sub115, i32 %sub111 >>>>>> + %add62 = add i32 0, %v.5 >>>>>> + %add73 = add i32 %add62, 0 >>>>>> + %add84 = add i32 %add73, 0 >>>>>> + %add95 = add i32 %add84, %v.8 >>>>>> + %add106 = add i32 %add95, 0 >>>>>> + %add117 = add i32 %add106, %v.10 >>>>>> + %add128 = add i32 %add117, 0 >>>>>> + %add139 = add i32 %add128, 0 >>>>>> + %add150 = add i32 %add139, 0 >>>>>> + %add161 = add i32 %add150, 0 >>>>>> + %add172 = add i32 %add161, 0 >>>>>> + br i1 undef, label %for.cond, label %if.end299 >>>>>> + >>>>>> +if.end299: ; preds = %for.body, %for.cond >>>>>> + %s.10 = phi i32 [ %add172, %for.body ], [ 0, %for.cond ] >>>>>> + ret i32 %s.10 >>>>>> +} >>>>>> + >>>>>> +!0 = metadata !{metadata !"omnipotent char", metadata !1} >>>>>> +!1 = metadata !{metadata !"Simple C/C++ TBAA", null} >>>>>> >>>>>> >>>>>> _______________________________________________ >>>>>> llvm-commits mailing list >>>>>> llvm-commits at cs.uiuc.edu >>>>>> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits >>>> >> From rafael.espindola at gmail.com Tue Dec 20 17:58:09 2011 From: rafael.espindola at gmail.com (=?UTF-8?B?UmFmYWVsIMOBdmlsYSBkZSBFc3DDrW5kb2xh?=) Date: Tue, 20 Dec 2011 18:58:09 -0500 Subject: [llvm-commits] [llvm] r146801 - in /llvm/trunk: include/llvm/MC/MCStreamer.h lib/CodeGen/AsmPrinter/AsmPrinterDwarf.cpp lib/MC/MCAsmStreamer.cpp lib/MC/MCLoggingStreamer.cpp lib/MC/MCNullStreamer.cpp lib/MC/MCParser/COFFAsmParser.cpp lib/MC/MCStr In-Reply-To: References: Message-ID: <4EF12111.2000806@gmail.com> > + > +#include "../Target/X86/MCTargetDesc/X86FixupKinds.h" > + > > > This is a pretty egregious layering violation. Please fix or revert, > this causes all kinds of problems with improper dependencies between > various components. This is not making library dependencies any worse: grep -r X86FixupKinds.h lib/MC/ lib/MC/ELFObjectWriter.cpp:#include "../Target/X86/MCTargetDesc/X86FixupKinds.h" lib/MC/WinCOFFStreamer.cpp:#include "../Target/X86/MCTargetDesc/X86FixupKinds.h" lib/MC/WinCOFFObjectWriter.cpp:#include "../Target/X86/MCTargetDesc/X86FixupKinds.h" I will take a look at this this week, but reverting this will break codegen of an empty main on windows with -g, so it seems like bit harsh for what it is. Cheers, Rafael From ahatanaka at mips.com Tue Dec 20 17:56:43 2011 From: ahatanaka at mips.com (Akira Hatanaka) Date: Tue, 20 Dec 2011 23:56:43 -0000 Subject: [llvm-commits] [llvm] r147017 - in /llvm/trunk/lib/Target/Mips: Mips64InstrInfo.td MipsISelLowering.cpp Message-ID: <20111220235643.BB0D52A6C12C@llvm.org> Author: ahatanak Date: Tue Dec 20 17:56:43 2011 New Revision: 147017 URL: http://llvm.org/viewvc/llvm-project?rev=147017&view=rev Log: Add definition of DSBH (Double Swap Bytes within Halfwords) and DSHD (Double Swap Halfwords within Doublewords). Add a pattern which replaces 64-bit bswap with a DSBH and DSHD pair. Modified: llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp Modified: llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td?rev=147017&r1=147016&r2=147017&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td (original) +++ llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td Tue Dec 20 17:56:43 2011 @@ -199,6 +199,10 @@ def DCLZ : CountLeading0<0x24, "dclz", CPU64Regs>; def DCLO : CountLeading1<0x25, "dclo", CPU64Regs>; +/// Double Word Swap Bytes/HalfWords +def DSBH : SubwordSwap<0x24, 0x2, "dsbh", CPU64Regs>; +def DSHD : SubwordSwap<0x24, 0x5, "dshd", CPU64Regs>; + def LEA_ADDiu64 : EffectiveAddress<"addiu\t$rt, $addr", CPU64Regs, mem_ea_64>; let Uses = [SP_64] in @@ -316,3 +320,5 @@ // Sign extend in register def : Pat<(i64 (sext_inreg CPU64Regs:$src, i32)), (SLL64_64 CPU64Regs:$src)>; +// bswap pattern +def : Pat<(bswap CPU64Regs:$rt), (DSHD (DSBH CPU64Regs:$rt))>; Modified: llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp?rev=147017&r1=147016&r2=147017&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp (original) +++ llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp Tue Dec 20 17:56:43 2011 @@ -221,8 +221,10 @@ if (!Subtarget->hasBitCount()) setOperationAction(ISD::CTLZ, MVT::i32, Expand); - if (!Subtarget->hasSwap()) + if (!Subtarget->hasSwap()) { setOperationAction(ISD::BSWAP, MVT::i32, Expand); + setOperationAction(ISD::BSWAP, MVT::i64, Expand); + } setTargetDAGCombine(ISD::ADDE); setTargetDAGCombine(ISD::SUBE); From ahatanaka at mips.com Tue Dec 20 17:58:37 2011 From: ahatanaka at mips.com (Akira Hatanaka) Date: Tue, 20 Dec 2011 23:58:37 -0000 Subject: [llvm-commits] [llvm] r147018 - /llvm/trunk/test/CodeGen/Mips/bswap.ll Message-ID: <20111220235837.0C02D2A6C12C@llvm.org> Author: ahatanak Date: Tue Dec 20 17:58:36 2011 New Revision: 147018 URL: http://llvm.org/viewvc/llvm-project?rev=147018&view=rev Log: Test case for r147017. Added: llvm/trunk/test/CodeGen/Mips/bswap.ll Added: llvm/trunk/test/CodeGen/Mips/bswap.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/bswap.ll?rev=147018&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/Mips/bswap.ll (added) +++ llvm/trunk/test/CodeGen/Mips/bswap.ll Tue Dec 20 17:58:36 2011 @@ -0,0 +1,25 @@ +; RUN: llc < %s -march=mipsel -mcpu=mips32r2 | FileCheck %s -check-prefix=MIPS32 +; RUN: llc < %s -march=mips64el -mcpu=mips64r2 | FileCheck %s -check-prefix=MIPS64 + +define i32 @bswap32(i32 %x) nounwind readnone { +entry: +; MIPS32: bswap32: +; MIPS32: wsbh $[[R0:[0-9]+]] +; MIPS32: rotr ${{[0-9]+}}, $[[R0]], 16 + %or.3 = call i32 @llvm.bswap.i32(i32 %x) + ret i32 %or.3 +} + +define i64 @bswap64(i64 %x) nounwind readnone { +entry: +; MIPS64: bswap64: +; MIPS64: dsbh $[[R0:[0-9]+]] +; MIPS64: dshd ${{[0-9]+}}, $[[R0]] + %or.7 = call i64 @llvm.bswap.i64(i64 %x) + ret i64 %or.7 +} + +declare i32 @llvm.bswap.i32(i32) nounwind readnone + +declare i64 @llvm.bswap.i64(i64) nounwind readnone + From ahatanaka at mips.com Tue Dec 20 18:02:58 2011 From: ahatanaka at mips.com (Akira Hatanaka) Date: Wed, 21 Dec 2011 00:02:58 -0000 Subject: [llvm-commits] [llvm] r147019 - /llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp Message-ID: <20111221000258.9C5342A6C12C@llvm.org> Author: ahatanak Date: Tue Dec 20 18:02:58 2011 New Revision: 147019 URL: http://llvm.org/viewvc/llvm-project?rev=147019&view=rev Log: Expand 64-bit atomic load and store. Modified: llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp Modified: llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp?rev=147019&r1=147018&r2=147019&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp (original) +++ llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp Tue Dec 20 18:02:58 2011 @@ -206,7 +206,9 @@ setOperationAction(ISD::ATOMIC_FENCE, MVT::Other, Custom); setOperationAction(ISD::ATOMIC_LOAD, MVT::i32, Expand); + setOperationAction(ISD::ATOMIC_LOAD, MVT::i64, Expand); setOperationAction(ISD::ATOMIC_STORE, MVT::i32, Expand); + setOperationAction(ISD::ATOMIC_STORE, MVT::i64, Expand); setInsertFencesForAtomic(true); From ahatanaka at mips.com Tue Dec 20 18:14:05 2011 From: ahatanaka at mips.com (Akira Hatanaka) Date: Wed, 21 Dec 2011 00:14:05 -0000 Subject: [llvm-commits] [llvm] r147021 - /llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp Message-ID: <20111221001405.6679D2A6C12C@llvm.org> Author: ahatanak Date: Tue Dec 20 18:14:05 2011 New Revision: 147021 URL: http://llvm.org/viewvc/llvm-project?rev=147021&view=rev Log: Expand 64-bit CTPOP and CTTZ. Modified: llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp Modified: llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp?rev=147021&r1=147020&r2=147021&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp (original) +++ llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp Tue Dec 20 18:14:05 2011 @@ -158,7 +158,9 @@ setOperationAction(ISD::FP_TO_UINT, MVT::i64, Expand); setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand); setOperationAction(ISD::CTPOP, MVT::i32, Expand); + setOperationAction(ISD::CTPOP, MVT::i64, Expand); setOperationAction(ISD::CTTZ, MVT::i32, Expand); + setOperationAction(ISD::CTTZ, MVT::i64, Expand); setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32, Expand); setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand); setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32, Expand); From ahatanaka at mips.com Tue Dec 20 18:20:28 2011 From: ahatanaka at mips.com (Akira Hatanaka) Date: Wed, 21 Dec 2011 00:20:28 -0000 Subject: [llvm-commits] [llvm] r147022 - in /llvm/trunk: lib/Target/Mips/MipsISelLowering.cpp test/CodeGen/Mips/mips64countleading.ll Message-ID: <20111221002028.1D5B12A6C12C@llvm.org> Author: ahatanak Date: Tue Dec 20 18:20:27 2011 New Revision: 147022 URL: http://llvm.org/viewvc/llvm-project?rev=147022&view=rev Log: Expand 64-bit CTLZ nodes if target architecture does not support it. Add test case for DCLO and DCLZ. Added: llvm/trunk/test/CodeGen/Mips/mips64countleading.ll Modified: llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp Modified: llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp?rev=147022&r1=147021&r2=147022&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp (original) +++ llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp Tue Dec 20 18:20:27 2011 @@ -222,8 +222,10 @@ setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand); } - if (!Subtarget->hasBitCount()) + if (!Subtarget->hasBitCount()) { setOperationAction(ISD::CTLZ, MVT::i32, Expand); + setOperationAction(ISD::CTLZ, MVT::i64, Expand); + } if (!Subtarget->hasSwap()) { setOperationAction(ISD::BSWAP, MVT::i32, Expand); Added: llvm/trunk/test/CodeGen/Mips/mips64countleading.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/mips64countleading.ll?rev=147022&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/Mips/mips64countleading.ll (added) +++ llvm/trunk/test/CodeGen/Mips/mips64countleading.ll Tue Dec 20 18:20:27 2011 @@ -0,0 +1,19 @@ +; RUN: llc -march=mips64el -mcpu=mips64 < %s | FileCheck %s + +define i64 @t1(i64 %X) nounwind readnone { +entry: +; CHECK: dclz + %tmp1 = tail call i64 @llvm.ctlz.i64(i64 %X, i1 true) + ret i64 %tmp1 +} + +declare i64 @llvm.ctlz.i64(i64, i1) nounwind readnone + +define i64 @t3(i64 %X) nounwind readnone { +entry: +; CHECK: dclo + %neg = xor i64 %X, -1 + %tmp1 = tail call i64 @llvm.ctlz.i64(i64 %neg, i1 true) + ret i64 %tmp1 +} + From ahatanaka at mips.com Tue Dec 20 18:31:10 2011 From: ahatanaka at mips.com (Akira Hatanaka) Date: Wed, 21 Dec 2011 00:31:10 -0000 Subject: [llvm-commits] [llvm] r147024 - in /llvm/trunk: lib/Target/Mips/MipsInstrInfo.td test/CodeGen/Mips/swzero.ll Message-ID: <20111221003110.C8BE92A6C12C@llvm.org> Author: ahatanak Date: Tue Dec 20 18:31:10 2011 New Revision: 147024 URL: http://llvm.org/viewvc/llvm-project?rev=147024&view=rev Log: Fix bug in zero-store peephole pattern reported in pr11615. The patch and test case were originally written by Mans Rullgard. Added: llvm/trunk/test/CodeGen/Mips/swzero.ll Modified: llvm/trunk/lib/Target/Mips/MipsInstrInfo.td Modified: llvm/trunk/lib/Target/Mips/MipsInstrInfo.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsInstrInfo.td?rev=147024&r1=147023&r2=147024&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/MipsInstrInfo.td (original) +++ llvm/trunk/lib/Target/Mips/MipsInstrInfo.td Tue Dec 20 18:31:10 2011 @@ -1022,10 +1022,14 @@ } // peepholes -def : Pat<(store (i32 0), addr:$dst), (SW ZERO, addr:$dst)>, - Requires<[NotN64]>; -def : Pat<(store (i32 0), addr:$dst), (SW_P8 ZERO, addr:$dst)>, - Requires<[IsN64]>; +let Predicates = [NotN64] in { + def : Pat<(store_a (i32 0), addr:$dst), (SW ZERO, addr:$dst)>; + def : Pat<(store_u (i32 0), addr:$dst), (USW ZERO, addr:$dst)>; +} +let Predicates = [IsN64] in { + def : Pat<(store_a (i32 0), addr:$dst), (SW_P8 ZERO, addr:$dst)>; + def : Pat<(store_u (i32 0), addr:$dst), (USW_P8 ZERO, addr:$dst)>; +} // brcond patterns multiclass BrcondPats + +define void @zero_u(%struct.unaligned* nocapture %p) nounwind { +entry: +; CHECK: usw $zero + %x = getelementptr inbounds %struct.unaligned* %p, i32 0, i32 0 + store i32 0, i32* %x, align 1 + ret void +} + +define void @zero_a(i32* nocapture %p) nounwind { +entry: +; CHECK: sw $zero + store i32 0, i32* %p, align 4 + ret void +} + From grosbach at apple.com Tue Dec 20 18:38:54 2011 From: grosbach at apple.com (Jim Grosbach) Date: Wed, 21 Dec 2011 00:38:54 -0000 Subject: [llvm-commits] [llvm] r147025 - in /llvm/trunk: lib/Target/ARM/ARMExpandPseudoInsts.cpp lib/Target/ARM/ARMInstrNEON.td lib/Target/ARM/AsmParser/ARMAsmParser.cpp lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp lib/Target/ARM/InstPrinter/ARMInstPrinter.h test/MC/ARM/neon-vld-encoding.s utils/TableGen/EDEmitter.cpp Message-ID: <20111221003854.DCFA32A6C12C@llvm.org> Author: grosbach Date: Tue Dec 20 18:38:54 2011 New Revision: 147025 URL: http://llvm.org/viewvc/llvm-project?rev=147025&view=rev Log: ARM NEON VLD2 assembly parsing for structure to all lanes, non-writeback. Modified: llvm/trunk/lib/Target/ARM/ARMExpandPseudoInsts.cpp llvm/trunk/lib/Target/ARM/ARMInstrNEON.td llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.h llvm/trunk/test/MC/ARM/neon-vld-encoding.s llvm/trunk/utils/TableGen/EDEmitter.cpp Modified: llvm/trunk/lib/Target/ARM/ARMExpandPseudoInsts.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMExpandPseudoInsts.cpp?rev=147025&r1=147024&r2=147025&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMExpandPseudoInsts.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMExpandPseudoInsts.cpp Tue Dec 20 18:38:54 2011 @@ -161,11 +161,11 @@ { ARM::VLD1q8PseudoWB_fixed, ARM::VLD1q8wb_fixed,true,false, false, SingleSpc, 2, 8 ,false}, { ARM::VLD1q8PseudoWB_register, ARM::VLD1q8wb_register,true,true, true,SingleSpc,2,8,false}, -{ ARM::VLD2DUPd16Pseudo, ARM::VLD2DUPd16, true, false, false, SingleSpc, 2, 4,true}, +{ ARM::VLD2DUPd16Pseudo, ARM::VLD2DUPd16, true, false, false, SingleSpc, 2, 4,false}, { ARM::VLD2DUPd16Pseudo_UPD, ARM::VLD2DUPd16_UPD, true, true, true, SingleSpc, 2, 4,true}, -{ ARM::VLD2DUPd32Pseudo, ARM::VLD2DUPd32, true, false, false, SingleSpc, 2, 2,true}, +{ ARM::VLD2DUPd32Pseudo, ARM::VLD2DUPd32, true, false, false, SingleSpc, 2, 2,false}, { ARM::VLD2DUPd32Pseudo_UPD, ARM::VLD2DUPd32_UPD, true, true, true, SingleSpc, 2, 2,true}, -{ ARM::VLD2DUPd8Pseudo, ARM::VLD2DUPd8, true, false, false, SingleSpc, 2, 8,true}, +{ ARM::VLD2DUPd8Pseudo, ARM::VLD2DUPd8, true, false, false, SingleSpc, 2, 8,false}, { ARM::VLD2DUPd8Pseudo_UPD, ARM::VLD2DUPd8_UPD, true, true, true, SingleSpc, 2, 8,true}, { ARM::VLD2LNd16Pseudo, ARM::VLD2LNd16, true, false, false, SingleSpc, 2, 4 ,true}, Modified: llvm/trunk/lib/Target/ARM/ARMInstrNEON.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrNEON.td?rev=147025&r1=147024&r2=147025&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrNEON.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrNEON.td Tue Dec 20 18:38:54 2011 @@ -143,6 +143,16 @@ def VecListTwoDAllLanes : RegisterOperand { let ParserMatchClass = VecListTwoDAllLanesAsmOperand; } +// Register list of two D registers spaced by 2 (two sequential Q registers). +def VecListTwoQAllLanesAsmOperand : AsmOperandClass { + let Name = "VecListTwoQAllLanes"; + let ParserMethod = "parseVectorList"; + let RenderMethod = "addVecListOperands"; +} +def VecListTwoQAllLanes : RegisterOperand { + let ParserMatchClass = VecListTwoQAllLanesAsmOperand; +} // Register list of one D register, with byte lane subscripting. def VecListOneDByteIndexAsmOperand : AsmOperandClass { @@ -1221,27 +1231,27 @@ def VLD1DUPq32PseudoWB_register : VLDQWBregisterPseudo; // VLD2DUP : Vector Load (single 2-element structure to all lanes) -class VLD2DUP op7_4, string Dt> - : NLdSt<1, 0b10, 0b1101, op7_4, (outs DPR:$Vd, DPR:$dst2), +class VLD2DUP op7_4, string Dt, RegisterOperand VdTy> + : NLdSt<1, 0b10, 0b1101, op7_4, (outs VdTy:$Vd), (ins addrmode6dup:$Rn), IIC_VLD2dup, - "vld2", Dt, "\\{$Vd[], $dst2[]\\}, $Rn", "", []> { + "vld2", Dt, "$Vd, $Rn", "", []> { let Rm = 0b1111; let Inst{4} = Rn{4}; let DecoderMethod = "DecodeVLD2DupInstruction"; } -def VLD2DUPd8 : VLD2DUP<{0,0,0,?}, "8">; -def VLD2DUPd16 : VLD2DUP<{0,1,0,?}, "16">; -def VLD2DUPd32 : VLD2DUP<{1,0,0,?}, "32">; +def VLD2DUPd8 : VLD2DUP<{0,0,0,?}, "8", VecListTwoDAllLanes>; +def VLD2DUPd16 : VLD2DUP<{0,1,0,?}, "16", VecListTwoDAllLanes>; +def VLD2DUPd32 : VLD2DUP<{1,0,0,?}, "32", VecListTwoDAllLanes>; def VLD2DUPd8Pseudo : VLDQPseudo; def VLD2DUPd16Pseudo : VLDQPseudo; def VLD2DUPd32Pseudo : VLDQPseudo; // ...with double-spaced registers (not used for codegen): -def VLD2DUPd8x2 : VLD2DUP<{0,0,1,?}, "8">; -def VLD2DUPd16x2 : VLD2DUP<{0,1,1,?}, "16">; -def VLD2DUPd32x2 : VLD2DUP<{1,0,1,?}, "32">; +def VLD2DUPd8x2 : VLD2DUP<{0,0,1,?}, "8", VecListTwoQAllLanes>; +def VLD2DUPd16x2 : VLD2DUP<{0,1,1,?}, "16", VecListTwoQAllLanes>; +def VLD2DUPd32x2 : VLD2DUP<{1,0,1,?}, "32", VecListTwoQAllLanes>; // ...with address register writeback: class VLD2DUPWB op7_4, string Dt> Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp?rev=147025&r1=147024&r2=147025&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp (original) +++ llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Tue Dec 20 18:38:54 2011 @@ -1118,13 +1118,24 @@ return VectorList.Count == 2; } + bool isSingleSpacedVectorAllLanes() const { + return Kind == k_VectorListAllLanes && !VectorList.isDoubleSpaced; + } + bool isDoubleSpacedVectorAllLanes() const { + return Kind == k_VectorListAllLanes && VectorList.isDoubleSpaced; + } bool isVecListOneDAllLanes() const { - if (Kind != k_VectorListAllLanes) return false; + if (!isSingleSpacedVectorAllLanes()) return false; return VectorList.Count == 1; } bool isVecListTwoDAllLanes() const { - if (Kind != k_VectorListAllLanes) return false; + if (!isSingleSpacedVectorAllLanes()) return false; + return VectorList.Count == 2; + } + + bool isVecListTwoQAllLanes() const { + if (!isDoubleSpacedVectorAllLanes()) return false; return VectorList.Count == 2; } @@ -2041,10 +2052,12 @@ } static ARMOperand *CreateVectorListAllLanes(unsigned RegNum, unsigned Count, + bool isDoubleSpaced, SMLoc S, SMLoc E) { ARMOperand *Op = new ARMOperand(k_VectorListAllLanes); Op->VectorList.RegNum = RegNum; Op->VectorList.Count = Count; + Op->VectorList.isDoubleSpaced = isDoubleSpaced; Op->StartLoc = S; Op->EndLoc = E; return Op; @@ -2865,7 +2878,8 @@ break; case AllLanes: E = Parser.getTok().getLoc(); - Operands.push_back(ARMOperand::CreateVectorListAllLanes(Reg, 1, S, E)); + Operands.push_back(ARMOperand::CreateVectorListAllLanes(Reg, 1, false, + S, E)); break; case IndexedLane: Operands.push_back(ARMOperand::CreateVectorListIndexed(Reg, 1, @@ -2889,7 +2903,8 @@ break; case AllLanes: E = Parser.getTok().getLoc(); - Operands.push_back(ARMOperand::CreateVectorListAllLanes(Reg, 2, S, E)); + Operands.push_back(ARMOperand::CreateVectorListAllLanes(Reg, 2, false, + S, E)); break; case IndexedLane: Operands.push_back(ARMOperand::CreateVectorListIndexed(Reg, 2, @@ -3060,6 +3075,7 @@ break; case AllLanes: Operands.push_back(ARMOperand::CreateVectorListAllLanes(FirstReg, Count, + (Spacing == 2), S, E)); break; case IndexedLane: Modified: llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp?rev=147025&r1=147024&r2=147025&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp (original) +++ llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp Tue Dec 20 18:38:54 2011 @@ -1066,3 +1066,13 @@ << getRegisterName(MI->getOperand(OpNum).getReg() + 2) << "}"; } +void ARMInstPrinter::printVectorListTwoSpacedAllLanes(const MCInst *MI, + unsigned OpNum, + raw_ostream &O) { + // Normally, it's not safe to use register enum values directly with + // addition to get the next register, but for VFP registers, the + // sort order is guaranteed because they're all of the form D. + O << "{" << getRegisterName(MI->getOperand(OpNum).getReg()) << "[], " + << getRegisterName(MI->getOperand(OpNum).getReg() + 2) << "[]}"; +} + Modified: llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.h?rev=147025&r1=147024&r2=147025&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.h (original) +++ llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.h Tue Dec 20 18:38:54 2011 @@ -139,6 +139,8 @@ raw_ostream &O); void printVectorListTwoSpaced(const MCInst *MI, unsigned OpNum, raw_ostream &O); + void printVectorListTwoSpacedAllLanes(const MCInst *MI, unsigned OpNum, + raw_ostream &O); }; } // end namespace llvm Modified: llvm/trunk/test/MC/ARM/neon-vld-encoding.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/neon-vld-encoding.s?rev=147025&r1=147024&r2=147025&view=diff ============================================================================== --- llvm/trunk/test/MC/ARM/neon-vld-encoding.s (original) +++ llvm/trunk/test/MC/ARM/neon-vld-encoding.s Tue Dec 20 18:38:54 2011 @@ -236,6 +236,8 @@ vld2.8 {d2[4], d3[4]}, [r2], r3 vld2.8 {d2[4], d3[4]}, [r2]! vld2.8 {d2[4], d3[4]}, [r2] + vld2.32 {d22[], d23[]}, [r1] + vld2.32 {d22[], d24[]}, [r1] @ CHECK: vld2.8 {d16[1], d17[1]}, [r0, :16] @ encoding: [0x3f,0x01,0xe0,0xf4] @ CHECK: vld2.16 {d16[1], d17[1]}, [r0, :32] @ encoding: [0x5f,0x05,0xe0,0xf4] @@ -246,7 +248,8 @@ @ CHECK: vld2.8 {d2[4], d3[4]}, [r2], r3 @ encoding: [0x83,0x21,0xa2,0xf4] @ CHECK: vld2.8 {d2[4], d3[4]}, [r2]! @ encoding: [0x8d,0x21,0xa2,0xf4] @ CHECK: vld2.8 {d2[4], d3[4]}, [r2] @ encoding: [0x8f,0x21,0xa2,0xf4] - +@ CHECK: vld2.32 {d22[], d23[]}, [r1] @ encoding: [0x8f,0x6d,0xe1,0xf4] +@ CHECK: vld2.32 {d22[], d24[]}, [r1] @ encoding: [0xaf,0x6d,0xe1,0xf4] @ vld3.8 {d16[1], d17[1], d18[1]}, [r0] Modified: llvm/trunk/utils/TableGen/EDEmitter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/EDEmitter.cpp?rev=147025&r1=147024&r2=147025&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/EDEmitter.cpp (original) +++ llvm/trunk/utils/TableGen/EDEmitter.cpp Tue Dec 20 18:38:54 2011 @@ -578,6 +578,7 @@ REG("VecListTwoQ"); REG("VecListOneDAllLanes"); REG("VecListTwoDAllLanes"); + REG("VecListTwoQAllLanes"); IMM("i32imm"); IMM("i32imm_hilo16"); From echristo at apple.com Tue Dec 20 18:52:44 2011 From: echristo at apple.com (Eric Christopher) Date: Wed, 21 Dec 2011 00:52:44 -0000 Subject: [llvm-commits] [llvm] r147027 - /llvm/trunk/configure Message-ID: <20111221005244.BFF4A2A6C12C@llvm.org> Author: echristo Date: Tue Dec 20 18:52:44 2011 New Revision: 147027 URL: http://llvm.org/viewvc/llvm-project?rev=147027&view=rev Log: Regenerate. Modified: llvm/trunk/configure Modified: llvm/trunk/configure URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/configure?rev=147027&r1=147026&r2=147027&view=diff ============================================================================== --- llvm/trunk/configure (original) +++ llvm/trunk/configure Tue Dec 20 18:52:44 2011 @@ -1,8 +1,8 @@ #! /bin/sh # Guess values for system-dependent variables and create Makefiles. -# Generated by GNU Autoconf 2.60 for llvm 3.1svn. +# Generated by GNU Autoconf 2.60 for LLVM 3.1svn. # -# Report bugs to . +# Report bugs to . # # Copyright (C) 1992, 1993, 1994, 1995, 1996, 1998, 1999, 2000, 2001, # 2002, 2003, 2004, 2005, 2006 Free Software Foundation, Inc. @@ -559,11 +559,11 @@ SHELL=${CONFIG_SHELL-/bin/sh} # Identity of this package. -PACKAGE_NAME='llvm' -PACKAGE_TARNAME='-llvm-' +PACKAGE_NAME='LLVM' +PACKAGE_TARNAME='llvm' PACKAGE_VERSION='3.1svn' -PACKAGE_STRING='llvm 3.1svn' -PACKAGE_BUGREPORT='llvmbugs at cs.uiuc.edu' +PACKAGE_STRING='LLVM 3.1svn' +PACKAGE_BUGREPORT='http://llvm.org/bugs/' ac_unique_file="lib/VMCore/Module.cpp" # Factoring default headers for most tests. @@ -1317,7 +1317,7 @@ # Omit some internal or obsolete options to make the list less imposing. # This message is too long to be a string in the A/UX 3.1 sh. cat <<_ACEOF -\`configure' configures llvm 3.1svn to adapt to many kinds of systems. +\`configure' configures LLVM 3.1svn to adapt to many kinds of systems. Usage: $0 [OPTION]... [VAR=VALUE]... @@ -1365,7 +1365,7 @@ --infodir=DIR info documentation [DATAROOTDIR/info] --localedir=DIR locale-dependent data [DATAROOTDIR/locale] --mandir=DIR man documentation [DATAROOTDIR/man] - --docdir=DIR documentation root [DATAROOTDIR/doc/-llvm-] + --docdir=DIR documentation root [DATAROOTDIR/doc/llvm] --htmldir=DIR html documentation [DOCDIR] --dvidir=DIR dvi documentation [DOCDIR] --pdfdir=DIR pdf documentation [DOCDIR] @@ -1383,7 +1383,7 @@ if test -n "$ac_init_help"; then case $ac_init_help in - short | recursive ) echo "Configuration of llvm 3.1svn:";; + short | recursive ) echo "Configuration of LLVM 3.1svn:";; esac cat <<\_ACEOF @@ -1418,8 +1418,8 @@ (default is YES) --enable-targets Build specific host targets: all or target1,target2,... Valid targets are: host, x86, - x86_64, sparc, powerpc, arm, mips, spu, xcore, - hexagon, msp430, ptx, cbe, and cpp (default=all) + x86_64, sparc, powerpc, arm, mips, spu, hexagon, + xcore, msp430, ptx, cbe, and cpp (default=all) --enable-cbe-printf-a Enable C Backend output with hex floating point via %a (default is YES) --enable-bindings Build specific language bindings: @@ -1472,7 +1472,7 @@ Use these variables to override the choices made by `configure' or to help it to find libraries and programs with nonstandard names/locations. -Report bugs to . +Report bugs to . _ACEOF ac_status=$? fi @@ -1533,7 +1533,7 @@ test -n "$ac_init_help" && exit $ac_status if $ac_init_version; then cat <<\_ACEOF -llvm configure 3.1svn +LLVM configure 3.1svn generated by GNU Autoconf 2.60 Copyright (C) 1992, 1993, 1994, 1995, 1996, 1998, 1999, 2000, 2001, @@ -1549,7 +1549,7 @@ This file contains any messages produced by compilers while running configure, to aid debugging if configure makes a mistake. -It was created by llvm $as_me 3.1svn, which was +It was created by LLVM $as_me 3.1svn, which was generated by GNU Autoconf 2.60. Invocation command line was $ $0 $@ @@ -8682,9 +8682,9 @@ { echo "$as_me:$LINENO: WARNING: $ac_header: in the future, the compiler will take precedence" >&5 echo "$as_me: WARNING: $ac_header: in the future, the compiler will take precedence" >&2;} ( cat <<\_ASBOX -## ----------------------------------- ## -## Report this to llvmbugs at cs.uiuc.edu ## -## ----------------------------------- ## +## ------------------------------------ ## +## Report this to http://llvm.org/bugs/ ## +## ------------------------------------ ## _ASBOX ) | sed "s/^/$as_me: WARNING: /" >&2 ;; @@ -10495,7 +10495,7 @@ lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2 lt_status=$lt_dlunknown cat > conftest.$ac_ext <&5 echo "$as_me: WARNING: $ac_header: in the future, the compiler will take precedence" >&2;} ( cat <<\_ASBOX -## ----------------------------------- ## -## Report this to llvmbugs at cs.uiuc.edu ## -## ----------------------------------- ## +## ------------------------------------ ## +## Report this to http://llvm.org/bugs/ ## +## ------------------------------------ ## _ASBOX ) | sed "s/^/$as_me: WARNING: /" >&2 ;; @@ -11226,9 +11226,9 @@ { echo "$as_me:$LINENO: WARNING: $ac_header: in the future, the compiler will take precedence" >&5 echo "$as_me: WARNING: $ac_header: in the future, the compiler will take precedence" >&2;} ( cat <<\_ASBOX -## ----------------------------------- ## -## Report this to llvmbugs at cs.uiuc.edu ## -## ----------------------------------- ## +## ------------------------------------ ## +## Report this to http://llvm.org/bugs/ ## +## ------------------------------------ ## _ASBOX ) | sed "s/^/$as_me: WARNING: /" >&2 ;; @@ -11398,9 +11398,9 @@ { echo "$as_me:$LINENO: WARNING: $ac_header: in the future, the compiler will take precedence" >&5 echo "$as_me: WARNING: $ac_header: in the future, the compiler will take precedence" >&2;} ( cat <<\_ASBOX -## ----------------------------------- ## -## Report this to llvmbugs at cs.uiuc.edu ## -## ----------------------------------- ## +## ------------------------------------ ## +## Report this to http://llvm.org/bugs/ ## +## ------------------------------------ ## _ASBOX ) | sed "s/^/$as_me: WARNING: /" >&2 ;; @@ -11568,9 +11568,9 @@ { echo "$as_me:$LINENO: WARNING: $ac_header: in the future, the compiler will take precedence" >&5 echo "$as_me: WARNING: $ac_header: in the future, the compiler will take precedence" >&2;} ( cat <<\_ASBOX -## ----------------------------------- ## -## Report this to llvmbugs at cs.uiuc.edu ## -## ----------------------------------- ## +## ------------------------------------ ## +## Report this to http://llvm.org/bugs/ ## +## ------------------------------------ ## _ASBOX ) | sed "s/^/$as_me: WARNING: /" >&2 ;; @@ -13699,9 +13699,9 @@ { echo "$as_me:$LINENO: WARNING: opagent.h: in the future, the compiler will take precedence" >&5 echo "$as_me: WARNING: opagent.h: in the future, the compiler will take precedence" >&2;} ( cat <<\_ASBOX -## ----------------------------------- ## -## Report this to llvmbugs at cs.uiuc.edu ## -## ----------------------------------- ## +## ------------------------------------ ## +## Report this to http://llvm.org/bugs/ ## +## ------------------------------------ ## _ASBOX ) | sed "s/^/$as_me: WARNING: /" >&2 ;; @@ -14489,9 +14489,9 @@ { echo "$as_me:$LINENO: WARNING: $ac_header: in the future, the compiler will take precedence" >&5 echo "$as_me: WARNING: $ac_header: in the future, the compiler will take precedence" >&2;} ( cat <<\_ASBOX -## ----------------------------------- ## -## Report this to llvmbugs at cs.uiuc.edu ## -## ----------------------------------- ## +## ------------------------------------ ## +## Report this to http://llvm.org/bugs/ ## +## ------------------------------------ ## _ASBOX ) | sed "s/^/$as_me: WARNING: /" >&2 ;; @@ -14663,9 +14663,9 @@ { echo "$as_me:$LINENO: WARNING: $ac_header: in the future, the compiler will take precedence" >&5 echo "$as_me: WARNING: $ac_header: in the future, the compiler will take precedence" >&2;} ( cat <<\_ASBOX -## ----------------------------------- ## -## Report this to llvmbugs at cs.uiuc.edu ## -## ----------------------------------- ## +## ------------------------------------ ## +## Report this to http://llvm.org/bugs/ ## +## ------------------------------------ ## _ASBOX ) | sed "s/^/$as_me: WARNING: /" >&2 ;; @@ -14833,9 +14833,9 @@ { echo "$as_me:$LINENO: WARNING: $ac_header: in the future, the compiler will take precedence" >&5 echo "$as_me: WARNING: $ac_header: in the future, the compiler will take precedence" >&2;} ( cat <<\_ASBOX -## ----------------------------------- ## -## Report this to llvmbugs at cs.uiuc.edu ## -## ----------------------------------- ## +## ------------------------------------ ## +## Report this to http://llvm.org/bugs/ ## +## ------------------------------------ ## _ASBOX ) | sed "s/^/$as_me: WARNING: /" >&2 ;; @@ -15006,9 +15006,9 @@ { echo "$as_me:$LINENO: WARNING: $ac_header: in the future, the compiler will take precedence" >&5 echo "$as_me: WARNING: $ac_header: in the future, the compiler will take precedence" >&2;} ( cat <<\_ASBOX -## ----------------------------------- ## -## Report this to llvmbugs at cs.uiuc.edu ## -## ----------------------------------- ## +## ------------------------------------ ## +## Report this to http://llvm.org/bugs/ ## +## ------------------------------------ ## _ASBOX ) | sed "s/^/$as_me: WARNING: /" >&2 ;; @@ -15178,9 +15178,9 @@ { echo "$as_me:$LINENO: WARNING: $ac_header: in the future, the compiler will take precedence" >&5 echo "$as_me: WARNING: $ac_header: in the future, the compiler will take precedence" >&2;} ( cat <<\_ASBOX -## ----------------------------------- ## -## Report this to llvmbugs at cs.uiuc.edu ## -## ----------------------------------- ## +## ------------------------------------ ## +## Report this to http://llvm.org/bugs/ ## +## ------------------------------------ ## _ASBOX ) | sed "s/^/$as_me: WARNING: /" >&2 ;; @@ -15347,9 +15347,9 @@ { echo "$as_me:$LINENO: WARNING: $ac_header: in the future, the compiler will take precedence" >&5 echo "$as_me: WARNING: $ac_header: in the future, the compiler will take precedence" >&2;} ( cat <<\_ASBOX -## ----------------------------------- ## -## Report this to llvmbugs at cs.uiuc.edu ## -## ----------------------------------- ## +## ------------------------------------ ## +## Report this to http://llvm.org/bugs/ ## +## ------------------------------------ ## _ASBOX ) | sed "s/^/$as_me: WARNING: /" >&2 ;; @@ -15516,9 +15516,9 @@ { echo "$as_me:$LINENO: WARNING: $ac_header: in the future, the compiler will take precedence" >&5 echo "$as_me: WARNING: $ac_header: in the future, the compiler will take precedence" >&2;} ( cat <<\_ASBOX -## ----------------------------------- ## -## Report this to llvmbugs at cs.uiuc.edu ## -## ----------------------------------- ## +## ------------------------------------ ## +## Report this to http://llvm.org/bugs/ ## +## ------------------------------------ ## _ASBOX ) | sed "s/^/$as_me: WARNING: /" >&2 ;; @@ -15686,9 +15686,9 @@ { echo "$as_me:$LINENO: WARNING: $ac_header: in the future, the compiler will take precedence" >&5 echo "$as_me: WARNING: $ac_header: in the future, the compiler will take precedence" >&2;} ( cat <<\_ASBOX -## ----------------------------------- ## -## Report this to llvmbugs at cs.uiuc.edu ## -## ----------------------------------- ## +## ------------------------------------ ## +## Report this to http://llvm.org/bugs/ ## +## ------------------------------------ ## _ASBOX ) | sed "s/^/$as_me: WARNING: /" >&2 ;; @@ -15866,9 +15866,9 @@ { echo "$as_me:$LINENO: WARNING: $ac_header: in the future, the compiler will take precedence" >&5 echo "$as_me: WARNING: $ac_header: in the future, the compiler will take precedence" >&2;} ( cat <<\_ASBOX -## ----------------------------------- ## -## Report this to llvmbugs at cs.uiuc.edu ## -## ----------------------------------- ## +## ------------------------------------ ## +## Report this to http://llvm.org/bugs/ ## +## ------------------------------------ ## _ASBOX ) | sed "s/^/$as_me: WARNING: /" >&2 ;; @@ -16037,9 +16037,9 @@ { echo "$as_me:$LINENO: WARNING: $ac_header: in the future, the compiler will take precedence" >&5 echo "$as_me: WARNING: $ac_header: in the future, the compiler will take precedence" >&2;} ( cat <<\_ASBOX -## ----------------------------------- ## -## Report this to llvmbugs at cs.uiuc.edu ## -## ----------------------------------- ## +## ------------------------------------ ## +## Report this to http://llvm.org/bugs/ ## +## ------------------------------------ ## _ASBOX ) | sed "s/^/$as_me: WARNING: /" >&2 ;; @@ -20078,9 +20078,9 @@ { echo "$as_me:$LINENO: WARNING: $ac_header: in the future, the compiler will take precedence" >&5 echo "$as_me: WARNING: $ac_header: in the future, the compiler will take precedence" >&2;} ( cat <<\_ASBOX -## ----------------------------------- ## -## Report this to llvmbugs at cs.uiuc.edu ## -## ----------------------------------- ## +## ------------------------------------ ## +## Report this to http://llvm.org/bugs/ ## +## ------------------------------------ ## _ASBOX ) | sed "s/^/$as_me: WARNING: /" >&2 ;; @@ -21548,7 +21548,7 @@ # report actual input values of CONFIG_FILES etc. instead of their # values after options handling. ac_log=" -This file was extended by llvm $as_me 3.1svn, which was +This file was extended by LLVM $as_me 3.1svn, which was generated by GNU Autoconf 2.60. Invocation command line was CONFIG_FILES = $CONFIG_FILES @@ -21601,7 +21601,7 @@ _ACEOF cat >>$CONFIG_STATUS <<_ACEOF ac_cs_version="\\ -llvm config.status 3.1svn +LLVM config.status 3.1svn configured by $0, generated by GNU Autoconf 2.60, with options \\"`echo "$ac_configure_args" | sed 's/^ //; s/[\\""\`\$]/\\\\&/g'`\\" From wendling at apple.com Tue Dec 20 19:07:32 2011 From: wendling at apple.com (Bill Wendling) Date: Tue, 20 Dec 2011 17:07:32 -0800 Subject: [llvm-commits] [llvm] r147010 - /llvm/trunk/lib/Linker/LinkModules.cpp In-Reply-To: <20111220231457.AE3482A6C12C@llvm.org> References: <20111220231457.AE3482A6C12C@llvm.org> Message-ID: <111A2708-481E-4117-8FD8-983DA49FCE34@apple.com> Yay! This was also making LTO fail. -bw On Dec 20, 2011, at 3:14 PM, Chris Lattner wrote: > Author: lattner > Date: Tue Dec 20 17:14:57 2011 > New Revision: 147010 > > URL: http://llvm.org/viewvc/llvm-project?rev=147010&view=rev > Log: > Fix a nasty bug in the type remapping stuff that I added that is breaking kc++ on > the build bot in some cases. The basic issue happens when a source module contains > both a "%foo" type and a "%foo.42" type. It will see the later one, check to see if > the destination module contains a "%foo" type, and it will return true... because > both the source and destination modules are in the same LLVMContext. We don't want > to map source types to other source types, so don't do the remapping if the mapped > type came from the source module. > > Unfortunately, I've been unable to reduce a decent testcase for this, kc++ is > pretty great that way. > > Modified: > llvm/trunk/lib/Linker/LinkModules.cpp > > Modified: llvm/trunk/lib/Linker/LinkModules.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Linker/LinkModules.cpp?rev=147010&r1=147009&r2=147010&view=diff > ============================================================================== > --- llvm/trunk/lib/Linker/LinkModules.cpp (original) > +++ llvm/trunk/lib/Linker/LinkModules.cpp Tue Dec 20 17:14:57 2011 > @@ -148,6 +148,7 @@ > if (PointerType *PT = dyn_cast(DstTy)) { > if (PT->getAddressSpace() != cast(SrcTy)->getAddressSpace()) > return false; > + > } else if (FunctionType *FT = dyn_cast(DstTy)) { > if (FT->isVarArg() != cast(SrcTy)->isVarArg()) > return false; > @@ -567,6 +568,9 @@ > std::vector SrcStructTypes; > SrcM->findUsedStructTypes(SrcStructTypes); > > + SmallPtrSet SrcStructTypesSet(SrcStructTypes.begin(), > + SrcStructTypes.end()); > + > for (unsigned i = 0, e = SrcStructTypes.size(); i != e; ++i) { > StructType *ST = SrcStructTypes[i]; > if (!ST->hasName()) continue; > @@ -579,7 +583,10 @@ > > // Check to see if the destination module has a struct with the prefix name. > if (StructType *DST = DstM->getTypeByName(ST->getName().substr(0, DotPos))) > - TypeMap.addTypeMapping(DST, ST); > + // Don't use it if this actually came from the source module. They're in > + // the same LLVMContext after all. > + if (!SrcStructTypesSet.count(DST)) > + TypeMap.addTypeMapping(DST, ST); > } > > > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From grosbach at apple.com Tue Dec 20 19:19:23 2011 From: grosbach at apple.com (Jim Grosbach) Date: Wed, 21 Dec 2011 01:19:23 -0000 Subject: [llvm-commits] [llvm] r147028 - /llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Message-ID: <20111221011923.E2F7C2A6C12C@llvm.org> Author: grosbach Date: Tue Dec 20 19:19:23 2011 New Revision: 147028 URL: http://llvm.org/viewvc/llvm-project?rev=147028&view=rev Log: ARM assembly parsing allows constant expressions for lane indices. Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp?rev=147028&r1=147027&r2=147028&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp (original) +++ llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Tue Dec 20 19:19:23 2011 @@ -2831,21 +2831,32 @@ Parser.Lex(); // Eat the ']'. return MatchOperand_Success; } - if (Parser.getTok().is(AsmToken::Integer)) { - int64_t Val = Parser.getTok().getIntVal(); - // Make this range check context sensitive for .8, .16, .32. - if (Val < 0 && Val > 7) - Error(Parser.getTok().getLoc(), "lane index out of range"); - Index = Val; - LaneKind = IndexedLane; - Parser.Lex(); // Eat the token; - if (Parser.getTok().isNot(AsmToken::RBrac)) - Error(Parser.getTok().getLoc(), "']' expected"); - Parser.Lex(); // Eat the ']'. - return MatchOperand_Success; + const MCExpr *LaneIndex; + SMLoc Loc = Parser.getTok().getLoc(); + if (getParser().ParseExpression(LaneIndex)) { + Error(Loc, "illegal expression"); + return MatchOperand_ParseFail; } - Error(Parser.getTok().getLoc(), "lane index must be empty or an integer"); - return MatchOperand_ParseFail; + const MCConstantExpr *CE = dyn_cast(LaneIndex); + if (!CE) { + Error(Loc, "lane index must be empty or an integer"); + return MatchOperand_ParseFail; + } + if (Parser.getTok().isNot(AsmToken::RBrac)) { + Error(Parser.getTok().getLoc(), "']' expected"); + return MatchOperand_ParseFail; + } + Parser.Lex(); // Eat the ']'. + int64_t Val = CE->getValue(); + + // FIXME: Make this range check context sensitive for .8, .16, .32. + if (Val < 0 || Val > 7) { + Error(Parser.getTok().getLoc(), "lane index out of range"); + return MatchOperand_ParseFail; + } + Index = Val; + LaneKind = IndexedLane; + return MatchOperand_Success; } LaneKind = NoLanes; return MatchOperand_Success; From evan.cheng at apple.com Tue Dec 20 19:38:48 2011 From: evan.cheng at apple.com (Evan Cheng) Date: Tue, 20 Dec 2011 17:38:48 -0800 Subject: [llvm-commits] [llvm] r146801 - in /llvm/trunk: include/llvm/MC/MCStreamer.h lib/CodeGen/AsmPrinter/AsmPrinterDwarf.cpp lib/MC/MCAsmStreamer.cpp lib/MC/MCLoggingStreamer.cpp lib/MC/MCNullStreamer.cpp lib/MC/MCParser/COFFAsmParser.cpp lib/MC/MCStr In-Reply-To: <4EF12111.2000806@gmail.com> References: <4EF12111.2000806@gmail.com> Message-ID: On Dec 20, 2011, at 3:58 PM, Rafael ?vila de Esp?ndola wrote: >> + >> +#include "../Target/X86/MCTargetDesc/X86FixupKinds.h" >> + >> >> >> This is a pretty egregious layering violation. Please fix or revert, >> this causes all kinds of problems with improper dependencies between >> various components. > > This is not making library dependencies any worse: > > grep -r X86FixupKinds.h lib/MC/ > lib/MC/ELFObjectWriter.cpp:#include > "../Target/X86/MCTargetDesc/X86FixupKinds.h" > lib/MC/WinCOFFStreamer.cpp:#include > "../Target/X86/MCTargetDesc/X86FixupKinds.h" > lib/MC/WinCOFFObjectWriter.cpp:#include > "../Target/X86/MCTargetDesc/X86FixupKinds.h" > > I will take a look at this this week, but reverting this will break > codegen of an empty main on windows with -g, so it seems like bit harsh > for what it is. Yuck. You're right. Evan > > Cheers, > Rafael > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From evan.cheng at apple.com Tue Dec 20 21:04:10 2011 From: evan.cheng at apple.com (Evan Cheng) Date: Wed, 21 Dec 2011 03:04:10 -0000 Subject: [llvm-commits] [llvm] r147032 - in /llvm/trunk: lib/Target/ARM/ARMInstrInfo.td test/CodeGen/ARM/atomic-op.ll Message-ID: <20111221030410.E8DBE2A6C12C@llvm.org> Author: evancheng Date: Tue Dec 20 21:04:10 2011 New Revision: 147032 URL: http://llvm.org/viewvc/llvm-project?rev=147032&view=rev Log: Fix a couple of copy-n-paste bugs. Noticed by George Russell. Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td llvm/trunk/test/CodeGen/ARM/atomic-op.ll Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.td?rev=147032&r1=147031&r2=147032&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrInfo.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Tue Dec 20 21:04:10 2011 @@ -4212,10 +4212,10 @@ [(set GPR:$dst, (atomic_load_max_32 GPR:$ptr, GPR:$val))]>; def ATOMIC_LOAD_UMIN_I32 : PseudoInst< (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary, - [(set GPR:$dst, (atomic_load_min_32 GPR:$ptr, GPR:$val))]>; + [(set GPR:$dst, (atomic_load_umin_32 GPR:$ptr, GPR:$val))]>; def ATOMIC_LOAD_UMAX_I32 : PseudoInst< (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary, - [(set GPR:$dst, (atomic_load_max_32 GPR:$ptr, GPR:$val))]>; + [(set GPR:$dst, (atomic_load_umax_32 GPR:$ptr, GPR:$val))]>; def ATOMIC_SWAP_I8 : PseudoInst< (outs GPR:$dst), (ins GPR:$ptr, GPR:$new), NoItinerary, Modified: llvm/trunk/test/CodeGen/ARM/atomic-op.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/atomic-op.ll?rev=147032&r1=147031&r2=147032&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/ARM/atomic-op.ll (original) +++ llvm/trunk/test/CodeGen/ARM/atomic-op.ll Tue Dec 20 21:04:10 2011 @@ -1,5 +1,5 @@ -; RUN: llc < %s -mtriple=armv7-apple-darwin10 -verify-machineinstrs | FileCheck %s -; RUN: llc < %s -mtriple=thumbv7-apple-darwin10 -verify-machineinstrs | FileCheck %s +; RUN: llc < %s -mtriple=armv7-apple-ios -verify-machineinstrs | FileCheck %s +; RUN: llc < %s -mtriple=thumbv7-apple-ios -verify-machineinstrs | FileCheck %s define void @func(i32 %argc, i8** %argv) nounwind { entry: @@ -61,7 +61,7 @@ ; CHECK: strex %7 = atomicrmw min i32* %val2, i32 16 monotonic store i32 %7, i32* %old - %neg = sub i32 0, 1 ; [#uses=1] + %neg = sub i32 0, 1 ; CHECK: ldrex ; CHECK: cmp ; CHECK: strex @@ -77,5 +77,27 @@ ; CHECK: strex %10 = atomicrmw max i32* %val2, i32 0 monotonic store i32 %10, i32* %old - ret void + ; CHECK: ldrex + ; CHECK: cmp + ; CHECK: strex + %11 = atomicrmw umin i32* %val2, i32 16 monotonic + store i32 %11, i32* %old + %uneg = sub i32 0, 1 + ; CHECK: ldrex + ; CHECK: cmp + ; CHECK: strex + %12 = atomicrmw umin i32* %val2, i32 %uneg monotonic + store i32 %12, i32* %old + ; CHECK: ldrex + ; CHECK: cmp + ; CHECK: strex + %13 = atomicrmw umax i32* %val2, i32 1 monotonic + store i32 %13, i32* %old + ; CHECK: ldrex + ; CHECK: cmp + ; CHECK: strex + %14 = atomicrmw umax i32* %val2, i32 0 monotonic + store i32 %14, i32* %old + + ret void } From nicholas at mxc.ca Tue Dec 20 23:52:02 2011 From: nicholas at mxc.ca (Nick Lewycky) Date: Wed, 21 Dec 2011 05:52:02 -0000 Subject: [llvm-commits] [llvm] r147036 - in /llvm/trunk: lib/Analysis/ValueTracking.cpp lib/Transforms/Utils/SimplifyCFG.cpp test/Transforms/SimplifyCFG/SpeculativeExec.ll Message-ID: <20111221055202.885DE2A6C12C@llvm.org> Author: nicholas Date: Tue Dec 20 23:52:02 2011 New Revision: 147036 URL: http://llvm.org/viewvc/llvm-project?rev=147036&view=rev Log: Make some intrinsics safe to speculatively execute. Modified: llvm/trunk/lib/Analysis/ValueTracking.cpp llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp llvm/trunk/test/Transforms/SimplifyCFG/SpeculativeExec.ll Modified: llvm/trunk/lib/Analysis/ValueTracking.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/ValueTracking.cpp?rev=147036&r1=147035&r2=147036&view=diff ============================================================================== --- llvm/trunk/lib/Analysis/ValueTracking.cpp (original) +++ llvm/trunk/lib/Analysis/ValueTracking.cpp Tue Dec 20 23:52:02 2011 @@ -1912,11 +1912,31 @@ return false; return LI->getPointerOperand()->isDereferenceablePointer(); } - case Instruction::Call: + case Instruction::Call: { + if (const IntrinsicInst *II = dyn_cast(Inst)) { + switch (II->getIntrinsicID()) { + case Intrinsic::bswap: + case Intrinsic::ctlz: + case Intrinsic::ctpop: + case Intrinsic::cttz: + case Intrinsic::objectsize: + case Intrinsic::sadd_with_overflow: + case Intrinsic::smul_with_overflow: + case Intrinsic::ssub_with_overflow: + case Intrinsic::uadd_with_overflow: + case Intrinsic::umul_with_overflow: + case Intrinsic::usub_with_overflow: + return true; + // TODO: some fp intrinsics are marked as having the same error handling + // as libm. They're safe to speculate when they won't error. + // TODO: are convert_{from,to}_fp16 safe? + // TODO: can we list target-specific intrinsics here? + default: break; + } + } return false; // The called function could have undefined behavior or - // side-effects. - // FIXME: We should special-case some intrinsics (bswap, - // overflow-checking arithmetic, etc.) + // side-effects, even if marked readnone nounwind. + } case Instruction::VAArg: case Instruction::Alloca: case Instruction::Invoke: Modified: llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp?rev=147036&r1=147035&r2=147036&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp (original) +++ llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp Tue Dec 20 23:52:02 2011 @@ -293,6 +293,7 @@ Cost = 1; break; // These are all cheap and non-trapping instructions. + case Instruction::Call: case Instruction::Select: Cost = 2; break; Modified: llvm/trunk/test/Transforms/SimplifyCFG/SpeculativeExec.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/SimplifyCFG/SpeculativeExec.ll?rev=147036&r1=147035&r2=147036&view=diff ============================================================================== --- llvm/trunk/test/Transforms/SimplifyCFG/SpeculativeExec.ll (original) +++ llvm/trunk/test/Transforms/SimplifyCFG/SpeculativeExec.ll Tue Dec 20 23:52:02 2011 @@ -1,7 +1,10 @@ -; RUN: opt < %s -simplifycfg -S | grep select -; RUN: opt < %s -simplifycfg -S | grep br | count 2 +; RUN: opt < %s -simplifycfg -phi-node-folding-threshold=2 -S | FileCheck %s -define i32 @t2(i32 %a, i32 %b, i32 %c) nounwind { +target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128" +target triple = "x86_64-unknown-linux-gnu" + +define i32 @test1(i32 %a, i32 %b, i32 %c) nounwind { +; CHECK: @test1 entry: %tmp1 = icmp eq i32 %b, 0 br i1 %tmp1, label %bb1, label %bb3 @@ -9,6 +12,11 @@ bb1: ; preds = %entry %tmp2 = icmp sgt i32 %c, 1 br i1 %tmp2, label %bb2, label %bb3 +; CHECK: bb1: +; CHECK-NEXT: add i32 %a, 1 +; CHECK-NEXT: icmp sgt i32 %c, 1 +; CHECK-NEXT: select i1 %tmp2, i32 %tmp3, i32 %a +; CHECK-NEXT: br label %bb3 bb2: ; preds = bb1 %tmp3 = add i32 %a, 1 @@ -19,3 +27,20 @@ %tmp5 = sub i32 %tmp4, 1 ret i32 %tmp5 } + +declare i8 @llvm.cttz.i8(i8, i1) + +define i8 @test2(i8 %a) { +; CHECK: @test2 + br i1 undef, label %bb_true, label %bb_false +bb_true: + %b = tail call i8 @llvm.cttz.i8(i8 %a, i1 false) + br label %join +bb_false: + br label %join +join: + %c = phi i8 [%b, %bb_true], [%a, %bb_false] +; CHECK: select + ret i8 %c +} + From nicholas at mxc.ca Wed Dec 21 00:06:30 2011 From: nicholas at mxc.ca (Nick Lewycky) Date: Wed, 21 Dec 2011 06:06:30 -0000 Subject: [llvm-commits] [llvm] r147037 - /llvm/trunk/lib/Analysis/InlineCost.cpp Message-ID: <20111221060630.8F5FD2A6C12C@llvm.org> Author: nicholas Date: Wed Dec 21 00:06:30 2011 New Revision: 147037 URL: http://llvm.org/viewvc/llvm-project?rev=147037&view=rev Log: A call to a function marked 'noinline' is not an inline candidate. The sole call site of an intrinsic is also not an inline candidate. While here, make it more obvious that this code ignores all intrinsics. Noticed by inspection! Modified: llvm/trunk/lib/Analysis/InlineCost.cpp Modified: llvm/trunk/lib/Analysis/InlineCost.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/InlineCost.cpp?rev=147037&r1=147036&r2=147037&view=diff ============================================================================== --- llvm/trunk/lib/Analysis/InlineCost.cpp (original) +++ llvm/trunk/lib/Analysis/InlineCost.cpp Wed Dec 21 00:06:30 2011 @@ -63,8 +63,8 @@ // Special handling for calls. if (isa(II) || isa(II)) { - if (isa(II)) - continue; // Debug intrinsics don't count as size. + if (isa(II)) + continue; // Intrinsics have no argument setup and can't be inlined. ImmutableCallSite CS(cast(II)); @@ -72,7 +72,7 @@ // If a function is both internal and has a single use, then it is // extremely likely to get inlined in the future (it was probably // exposed by an interleaved devirtualization pass). - if (F->hasInternalLinkage() && F->hasOneUse()) + if (!CS.isNoInline() && F->hasInternalLinkage() && F->hasOneUse()) ++NumInlineCandidates; // If this call is to function itself, then the function is recursive. @@ -83,7 +83,7 @@ isRecursive = true; } - if (!isa(II) && !callIsSmall(CS.getCalledFunction())) { + if (!callIsSmall(CS.getCalledFunction())) { // Each argument to a call takes on average one instruction to set up. NumInsts += CS.arg_size(); From daniel at zuster.org Wed Dec 21 00:21:56 2011 From: daniel at zuster.org (Daniel Dunbar) Date: Wed, 21 Dec 2011 06:21:56 -0000 Subject: [llvm-commits] [zorg] r147038 - /zorg/trunk/lnt/lnt/lnttool/create.py Message-ID: <20111221062156.4BBF52A6C12C@llvm.org> Author: ddunbar Date: Wed Dec 21 00:21:56 2011 New Revision: 147038 URL: http://llvm.org/viewvc/llvm-project?rev=147038&view=rev Log: [lnt/v0.4] lnt create: Fix up some errors in the default NT test suite definition. Modified: zorg/trunk/lnt/lnt/lnttool/create.py Modified: zorg/trunk/lnt/lnt/lnttool/create.py URL: http://llvm.org/viewvc/llvm-project/zorg/trunk/lnt/lnt/lnttool/create.py?rev=147038&r1=147037&r2=147038&view=diff ============================================================================== --- zorg/trunk/lnt/lnt/lnttool/create.py (original) +++ zorg/trunk/lnt/lnt/lnttool/create.py Wed Dec 21 00:21:56 2011 @@ -107,11 +107,11 @@ # We are only interested in simple runs, so we expect exactly four fields # per test. ts.sample_fields.append(testsuite.SampleField( - "compile_time", real_sample_type, ".compile.time")) + "compile_time", real_sample_type, ".compile")) ts.sample_fields.append(testsuite.SampleField( "compile_status", status_sample_type, ".compile.status")) ts.sample_fields.append(testsuite.SampleField( - "execution_time", real_sample_type, ".exec.time")) + "execution_time", real_sample_type, ".exec")) ts.sample_fields.append(testsuite.SampleField( "execution_status", status_sample_type, ".exec.status")) From daniel at zuster.org Wed Dec 21 00:21:59 2011 From: daniel at zuster.org (Daniel Dunbar) Date: Wed, 21 Dec 2011 06:21:59 -0000 Subject: [llvm-commits] [zorg] r147039 - /zorg/trunk/lnt/lnt/server/db/testsuitedb.py Message-ID: <20111221062159.714B12A6C12C@llvm.org> Author: ddunbar Date: Wed Dec 21 00:21:59 2011 New Revision: 147039 URL: http://llvm.org/viewvc/llvm-project?rev=147039&view=rev Log: [lnt/v0.4] lnt.server.db.testsuitedb: Finish first draft of import implementation. - Probably not very fast, but I believe it is functionally complete. Modified: zorg/trunk/lnt/lnt/server/db/testsuitedb.py Modified: zorg/trunk/lnt/lnt/server/db/testsuitedb.py URL: http://llvm.org/viewvc/llvm-project/zorg/trunk/lnt/lnt/server/db/testsuitedb.py?rev=147039&r1=147038&r2=147039&view=diff ============================================================================== --- zorg/trunk/lnt/lnt/server/db/testsuitedb.py (original) +++ zorg/trunk/lnt/lnt/server/db/testsuitedb.py Wed Dec 21 00:21:59 2011 @@ -60,7 +60,7 @@ def __repr__(self): return '%s_%s%r' % (db_key_name, self.__class__.__name__, (self.name,)) - + class Order(self.base): __tablename__ = db_key_name + '_Order' @@ -144,7 +144,7 @@ def __repr__(self): return '%s_%s%r' % (db_key_name, self.__class__.__name__, - (self.name)) + (self.name,)) class Sample(self.base): __tablename__ = db_key_name + '_Sample' @@ -183,13 +183,21 @@ class_dict[item.name] = item.column - def __init__(self, run, test): + def __init__(self, run, test, **kwargs): self.run = run self.test = test + # Initialize sample fields (defaulting to 0, for now). + for item in test_suite.sample_fields: + setattr(self, item.name, kwargs.get(item.name, 0)) + def __repr__(self): - return '%s_%s%r' % (db_key_name, self.__class__.__name__, - (self.run, self.test, self.value)) + fields = dict((item.name, getattr(self, item.name)) + for item in test_suite.sample_fields) + + return '%s_%s(%r, %r, **%r)' % ( + db_key_name, self.__class__.__name__, + self.run, self.test, fields) self.Machine = Machine self.Run = Run @@ -370,6 +378,62 @@ return run,True + def _importSampleValues(self, tests_data, run): + # We now need to transform the old schema data (composite samples split + # into multiple tests) into the V4DB format where each sample is a + # complete record. + + # Load a map of all the tests, which we will extend when we find tests + # that need to be added. + test_cache = dict((test.name, test) + for test in self.query(self.Test)) + + # We build a map of test name to sample values, by scanning all the + # tests. This is complicated by the interchange's support of multiple + # values, which we cannot properly aggregate. We handle this by keying + # off of the test name and the sample index. + # + # Note that the above strategy only works if reports don't report the + # same test name multiple times. That was possible in the schema, but I + # believe never used. + sample_records = {} + for test_data in tests_data: + if test_data['Info']: + raise ValueError,"""\ +test parameter sets are not supported by V4DB databases""" + + name = test_data['Name'] + + # Map this reported test name into a test name and a sample field. + # + # FIXME: This is really slow. + for item in self.test_suite.sample_fields: + if name.endswith(item.info_key): + test_name = name[:-len(item.info_key)] + sample_field = item + break + else: + # Disallow tests which do not map to a sample field. + raise ValueError,"""\ +test %r does not map to a sample field in the reported suite""" % ( + name) + + # Get or create the test. + test = test_cache.get(test_name) + if test is None: + test_cache[test_name] = test = self.Test(test_name) + self.add(test) + + for i,value in enumerate(test_data['Data']): + record_key = (test_name, i) + record = sample_records.get(record_key) + if record is None: + sample_records[record_key] = sample = self.Sample(run, test) + self.add(sample) + + # FIXME: Avoid setattr. + setattr(sample, sample_field.name, value) + def importDataFromDict(self, data): """ importDataFromDict(data) -> Run, bool @@ -392,7 +456,6 @@ if not inserted: return False, run - # FIXME: Insert tests and samples. - raise NotImplementedError + self._importSampleValues(data['Tests'], run) return True, run From daniel at zuster.org Wed Dec 21 00:22:04 2011 From: daniel at zuster.org (Daniel Dunbar) Date: Wed, 21 Dec 2011 06:22:04 -0000 Subject: [llvm-commits] [zorg] r147040 - in /zorg/trunk/lnt/lnt: db/perfdb.py server/db/v4db.py server/ui/app.py server/ui/templates/index.html server/ui/views.py Message-ID: <20111221062204.535BF2A6C12C@llvm.org> Author: ddunbar Date: Wed Dec 21 00:22:04 2011 New Revision: 147040 URL: http://llvm.org/viewvc/llvm-project?rev=147040&view=rev Log: [lnt/v0.4] lnt.server.ui/index: Start work on UI for V4 databases. Modified: zorg/trunk/lnt/lnt/db/perfdb.py zorg/trunk/lnt/lnt/server/db/v4db.py zorg/trunk/lnt/lnt/server/ui/app.py zorg/trunk/lnt/lnt/server/ui/templates/index.html zorg/trunk/lnt/lnt/server/ui/views.py Modified: zorg/trunk/lnt/lnt/db/perfdb.py URL: http://llvm.org/viewvc/llvm-project/zorg/trunk/lnt/lnt/db/perfdb.py?rev=147040&r1=147039&r2=147040&view=diff ============================================================================== --- zorg/trunk/lnt/lnt/db/perfdb.py (original) +++ zorg/trunk/lnt/lnt/db/perfdb.py Wed Dec 21 00:22:04 2011 @@ -344,6 +344,10 @@ def importDataFromDict(self, data): return importDataFromDict(self, data) + def get_db_summary(self): + import perfdbsummary + return perfdbsummary.PerfDBSummary.fromdb(self) + def importDataFromDict(db, data): # FIXME: Validate data machineData = data['Machine'] Modified: zorg/trunk/lnt/lnt/server/db/v4db.py URL: http://llvm.org/viewvc/llvm-project/zorg/trunk/lnt/lnt/server/db/v4db.py?rev=147040&r1=147039&r2=147040&view=diff ============================================================================== --- zorg/trunk/lnt/lnt/server/db/v4db.py (original) +++ zorg/trunk/lnt/lnt/server/db/v4db.py Wed Dec 21 00:22:04 2011 @@ -113,3 +113,23 @@ db = self.testsuite.get(db_name) return db.importDataFromDict(data) + + def get_db_summary(self): + return V4DBSummary(self) + +class V4DBSummary(object): + class SuiteSummary(object): + def __init__(self, name, path): + self.name = name + self.path = path + + def __init__(self, db): + self.db = db + + @property + def suites(self): + for name in self.db.testsuite: + yield V4DBSummary.SuiteSummary(name, ("v4", name)) + + def is_up_to_date(self, db): + return True Modified: zorg/trunk/lnt/lnt/server/ui/app.py URL: http://llvm.org/viewvc/llvm-project/zorg/trunk/lnt/lnt/server/ui/app.py?rev=147040&r1=147039&r2=147040&view=diff ============================================================================== --- zorg/trunk/lnt/lnt/server/ui/app.py (original) +++ zorg/trunk/lnt/lnt/server/ui/app.py Wed Dec 21 00:22:04 2011 @@ -12,6 +12,7 @@ import lnt.server.config import lnt.server.ui.filters import lnt.server.ui.views +import lnt.server.db.v4db from lnt.db import perfdbsummary from lnt.db import perfdb @@ -41,7 +42,10 @@ def get_db(self): if self.db is None: - self.db = perfdb.PerfDB(g.db_info.path) + if g.db_info.db_version == '0.3': + self.db = perfdb.PerfDB(g.db_info.path) + else: + self.db = lnt.server.db.v4db.V4DB(g.db_info.path) # Enable SQL logging with db_log. # @@ -110,9 +114,10 @@ old_config=self.old_config) def get_db_summary(self, db_name, db): + # FIXME/v3removal: Eliminate this, V4DB style has no need for summary + # abstraction. db_summary = self.db_summaries.get(db_name) if db_summary is None or not db_summary.is_up_to_date(db): - self.db_summaries[db_name] = db_summary = \ - perfdbsummary.PerfDBSummary.fromdb(db) + self.db_summaries[db_name] = db_summary = db.get_db_summary() return db_summary Modified: zorg/trunk/lnt/lnt/server/ui/templates/index.html URL: http://llvm.org/viewvc/llvm-project/zorg/trunk/lnt/lnt/server/ui/templates/index.html?rev=147040&r1=147039&r2=147040&view=diff ============================================================================== --- zorg/trunk/lnt/lnt/server/ui/templates/index.html (original) +++ zorg/trunk/lnt/lnt/server/ui/templates/index.html Wed Dec 21 00:22:04 2011 @@ -5,12 +5,12 @@ {# Display available test result suites. #} {% set summary = request.get_db_summary() %} -

Test Results

Test Suites

{% for suite in summary.suites %} {{suite.name}}
{% endfor %} -{% if g.db_info.showGeneral %} +{% if g.db_info.db_version == '0.3' and g.db_info.showGeneral %}

General Database Access

Modified: zorg/trunk/lnt/lnt/server/ui/views.py URL: http://llvm.org/viewvc/llvm-project/zorg/trunk/lnt/lnt/server/ui/views.py?rev=147040&r1=147039&r2=147040&view=diff ============================================================================== --- zorg/trunk/lnt/lnt/server/ui/views.py (original) +++ zorg/trunk/lnt/lnt/server/ui/views.py Wed Dec 21 00:22:04 2011 @@ -46,7 +46,7 @@ # Per-Database Routes # Decorator for implementing per-database routes. -def db_route(rule, **options): +def db_route(rule, only_v3 = True, **options): """ LNT specific route for endpoints which always refer to some database object. @@ -62,12 +62,13 @@ if g.db_info is None: abort(404) - # Currently the UI has absolutely no support for non-v0.3 databases. - if g.db_info.db_version != '0.3': + # Disable non-v0.3 database support, if requested. + if only_v3 and g.db_info.db_version != '0.3': return render_template("error.html", message="""\ UI support for database with version %r is not yet implemented.""" % ( g.db_info.db_version)) + return f(**args) frontend.add_url_rule(rule, f.__name__, wrap, **options) @@ -77,7 +78,7 @@ return wrap return decorator - at db_route('/') + at db_route('/', only_v3 = False) def index(): return render_template("index.html") From daniel at zuster.org Wed Dec 21 00:22:14 2011 From: daniel at zuster.org (Daniel Dunbar) Date: Wed, 21 Dec 2011 06:22:14 -0000 Subject: [llvm-commits] [zorg] r147043 - /zorg/trunk/lnt/lnt/server/db/testsuitedb.py Message-ID: <20111221062214.345782A6C12E@llvm.org> Author: ddunbar Date: Wed Dec 21 00:22:13 2011 New Revision: 147043 URL: http://llvm.org/viewvc/llvm-project?rev=147043&view=rev Log: [lnt/v0.4] lnt.server.db.testsuitedb: Add helper methods for TestSuiteDB model classes to support easier access to parameterized fields. Modified: zorg/trunk/lnt/lnt/server/db/testsuitedb.py Modified: zorg/trunk/lnt/lnt/server/db/testsuitedb.py URL: http://llvm.org/viewvc/llvm-project/zorg/trunk/lnt/lnt/server/db/testsuitedb.py?rev=147043&r1=147042&r2=147043&view=diff ============================================================================== --- zorg/trunk/lnt/lnt/server/db/testsuitedb.py (original) +++ zorg/trunk/lnt/lnt/server/db/testsuitedb.py Wed Dec 21 00:22:13 2011 @@ -42,6 +42,7 @@ class Machine(self.base): __tablename__ = db_key_name + '_Machine' + fields = self.machine_fields id = Column("ID", Integer, primary_key=True) name = Column("Name", String(256), index=True) @@ -53,7 +54,7 @@ # Dynamically create fields for all of the test suite defined # machine fields. class_dict = locals() - for item in self.machine_fields: + for item in fields: if item.name in class_dict: raise ValueError,"test suite defines reserved key %r" % ( name,) @@ -68,9 +69,19 @@ return '%s_%s%r' % (db_key_name, self.__class__.__name__, (self.name,)) + def get_field(self, field): + return getattr(self, field.name) + + def set_field(self, field, value): + return setattr(self, field.name, value) + + def get_parameters(self): + return json.loads(self.parameters) + class Order(self.base): __tablename__ = db_key_name + '_Order' + fields = self.order_fields id = Column("ID", Integer, primary_key=True) # Dynamically create fields for all of the test suite defined order @@ -87,16 +98,31 @@ class_dict[item.name] = item.column = Column( item.name, String(256)) - def __init__(self): - pass + def __init__(self, **kwargs): + for item in self.fields: + self.set_field(item, kwargs[item.name]) def __repr__(self): return '%s_%s%r' % (db_key_name, self.__class__.__name__, ()) + def __repr__(self): + fields = dict((item.name, self.get_field(item)) + for item in self.fields) + + return '%s_%s(**%r)' % ( + db_key_name, self.__class__.__name__, fields) + + def get_field(self, field): + return getattr(self, field.name) + + def set_field(self, field, value): + return setattr(self, field.name, value) + class Run(self.base): __tablename__ = db_key_name + '_Run' + fields = self.run_fields id = Column("ID", Integer, primary_key=True) machine_id = Column("MachineID", Integer, ForeignKey(Machine.id), index=True) @@ -120,7 +146,7 @@ # FIXME: We are probably going to want to index on some of these, # but need a bit for that in the test suite definition. class_dict = locals() - for item in self.run_fields: + for item in fields: if item.name in class_dict: raise ValueError,"test suite defines reserved key %r" % ( name,) @@ -140,6 +166,15 @@ (self.machine, self.order, self.start_time, self.end_time)) + def get_field(self, field): + return getattr(self, field.name) + + def set_field(self, field, value): + return setattr(self, field.name, value) + + def get_parameters(self): + return json.loads(self.parameters) + class Test(self.base): __tablename__ = db_key_name + '_Test' @@ -153,9 +188,16 @@ return '%s_%s%r' % (db_key_name, self.__class__.__name__, (self.name,)) + def get_field(self, field): + return getattr(self, field.name) + + def set_field(self, field, value): + return setattr(self, field.name, value) + class Sample(self.base): __tablename__ = db_key_name + '_Sample' + fields = self.sample_fields id = Column("ID", Integer, primary_key=True) # We do not need an index on run_id, this is covered by the compound # (Run(ID),Test(ID)) index we create below. @@ -195,17 +237,23 @@ self.test = test # Initialize sample fields (defaulting to 0, for now). - for item in testsuitedb.sample_fields: - setattr(self, item.name, kwargs.get(item.name, 0)) + for item in self.fields: + self.set_field(item, kwargs.get(item.name, 0)) def __repr__(self): - fields = dict((item.name, getattr(self, item.name)) - for item in self.sample_fields) + fields = dict((item.name, self.get_field(item)) + for item in self.fields) return '%s_%s(%r, %r, **%r)' % ( db_key_name, self.__class__.__name__, self.run, self.test, fields) + def get_field(self, field): + return getattr(self, field.name) + + def set_field(self, field, value): + return setattr(self, field.name, value) + self.Machine = Machine self.Run = Run self.Test = Test @@ -263,9 +311,8 @@ # suite to define defaults. value = '' - # FIXME: Avoid setattr. query = query.filter(item.column == value) - setattr(machine, item.name, value) + machine.set_field(item.name, value) # Convert any remaining machine_parameters into a JSON encoded blob. We # encode this as an array to avoid a potential ambiguity on the key @@ -309,9 +356,8 @@ supplied run is missing required run parameter: %r""" % ( item.info_key) - # FIXME: Avoid setattr. query = query.filter(item.column == value) - setattr(order, item.name, value) + order.set_field(item, value) # Execute the query to see if we already have this order. try: @@ -368,9 +414,8 @@ # suite to define defaults. value = '' - # FIXME: Avoid setattr. query = query.filter(item.column == value) - setattr(run, item.name, value) + run.set_field(item, value) # Any remaining parameters are saved as a JSON encoded array. run.parameters = json.dumps(sorted(run_parameters.items())) @@ -438,8 +483,7 @@ sample_records[record_key] = sample = self.Sample(run, test) self.add(sample) - # FIXME: Avoid setattr. - setattr(sample, sample_field.name, value) + sample.set_field(sample_field, value) def importDataFromDict(self, data): """ @@ -466,3 +510,14 @@ self._importSampleValues(data['Tests'], run) return True, run + + # Simple query support (mostly used by templates) + + def machines(self, name=None): + q = self.query(self.Machine) + if name: + q = q.filter_by(name=name) + return q + + def getMachine(self, id): + return self.query(self.Machine).filter_by(id=id).one() From daniel at zuster.org Wed Dec 21 00:22:07 2011 From: daniel at zuster.org (Daniel Dunbar) Date: Wed, 21 Dec 2011 06:22:07 -0000 Subject: [llvm-commits] [zorg] r147041 - /zorg/trunk/lnt/lnt/server/db/testsuitedb.py Message-ID: <20111221062207.7781A2A6C12C@llvm.org> Author: ddunbar Date: Wed Dec 21 00:22:07 2011 New Revision: 147041 URL: http://llvm.org/viewvc/llvm-project?rev=147041&view=rev Log: [lnt/v0.4] lnt.server.db.testsuitedb: Cache the assorted fields lists, important particularly because we save the column in the particular model instance during initialization. Modified: zorg/trunk/lnt/lnt/server/db/testsuitedb.py Modified: zorg/trunk/lnt/lnt/server/db/testsuitedb.py URL: http://llvm.org/viewvc/llvm-project/zorg/trunk/lnt/lnt/server/db/testsuitedb.py?rev=147041&r1=147040&r2=147041&view=diff ============================================================================== --- zorg/trunk/lnt/lnt/server/db/testsuitedb.py (original) +++ zorg/trunk/lnt/lnt/server/db/testsuitedb.py Wed Dec 21 00:22:07 2011 @@ -25,9 +25,16 @@ """ def __init__(self, v4db, test_suite): + testsuitedb = self self.v4db = v4db self.test_suite = test_suite + # Save caches of the various fields. + self.machine_fields = list(self.test_suite.machine_fields) + self.order_fields = list(self.test_suite.order_fields) + self.run_fields = list(self.test_suite.run_fields) + self.sample_fields = list(self.test_suite.sample_fields) + self.base = sqlalchemy.ext.declarative.declarative_base() # Create parameterized model classes for this test suite. @@ -46,7 +53,7 @@ # Dynamically create fields for all of the test suite defined # machine fields. class_dict = locals() - for item in test_suite.machine_fields: + for item in self.machine_fields: if item.name in class_dict: raise ValueError,"test suite defines reserved key %r" % ( name,) @@ -72,7 +79,7 @@ # FIXME: We are probably going to want to index on some of these, # but need a bit for that in the test suite definition. class_dict = locals() - for item in test_suite.order_fields: + for item in self.order_fields: if item.name in class_dict: raise ValueError,"test suite defines reserved key %r" % ( name,) @@ -113,7 +120,7 @@ # FIXME: We are probably going to want to index on some of these, # but need a bit for that in the test suite definition. class_dict = locals() - for item in test_suite.run_fields: + for item in self.run_fields: if item.name in class_dict: raise ValueError,"test suite defines reserved key %r" % ( name,) @@ -166,7 +173,7 @@ # index below into a covering index. We should evaluate this once # the new UI is up. class_dict = locals() - for item in test_suite.sample_fields: + for item in self.sample_fields: if item.name in class_dict: raise ValueError,"test suite defines reserved key %r" % ( name,) @@ -188,12 +195,12 @@ self.test = test # Initialize sample fields (defaulting to 0, for now). - for item in test_suite.sample_fields: + for item in testsuitedb.sample_fields: setattr(self, item.name, kwargs.get(item.name, 0)) def __repr__(self): fields = dict((item.name, getattr(self, item.name)) - for item in test_suite.sample_fields) + for item in self.sample_fields) return '%s_%s(%r, %r, **%r)' % ( db_key_name, self.__class__.__name__, @@ -211,7 +218,7 @@ # Create the index we use to ensure machine uniqueness. args = [Machine.name, Machine.parameters] - for item in self.test_suite.machine_fields: + for item in self.machine_fields: args.append(item.column) sqlalchemy.schema.Index("ix_%s_Machine_Unique" % db_key_name, *args, unique = True) @@ -247,7 +254,7 @@ machine_parameters = machine_data['Info'].copy() # First, extract all of the specified machine fields. - for item in self.test_suite.machine_fields: + for item in self.machine_fields: if item.info_key in machine_parameters: value = machine_parameters.pop(item.info_key) else: @@ -293,7 +300,7 @@ order = self.Order() # First, extract all of the specified order fields. - for item in self.test_suite.order_fields: + for item in self.order_fields: if item.info_key in run_parameters: value = run_parameters.pop(item.info_key) else: @@ -352,7 +359,7 @@ run = self.Run(machine, order, start_time, end_time) # First, extract all of the specified run fields. - for item in self.test_suite.run_fields: + for item in self.run_fields: if item.info_key in run_parameters: value = run_parameters.pop(item.info_key) else: @@ -407,7 +414,7 @@ # Map this reported test name into a test name and a sample field. # # FIXME: This is really slow. - for item in self.test_suite.sample_fields: + for item in self.sample_fields: if name.endswith(item.info_key): test_name = name[:-len(item.info_key)] sample_field = item From daniel at zuster.org Wed Dec 21 00:22:11 2011 From: daniel at zuster.org (Daniel Dunbar) Date: Wed, 21 Dec 2011 06:22:11 -0000 Subject: [llvm-commits] [zorg] r147042 - in /zorg/trunk/lnt/lnt/server/ui: app.py templates/v4_overview.html views.py Message-ID: <20111221062211.351772A6C12D@llvm.org> Author: ddunbar Date: Wed Dec 21 00:22:10 2011 New Revision: 147042 URL: http://llvm.org/viewvc/llvm-project?rev=147042&view=rev Log: [lnt/v0.4] lnt.server.ui/v4/: Implement V4 overview page. Added: zorg/trunk/lnt/lnt/server/ui/templates/v4_overview.html Modified: zorg/trunk/lnt/lnt/server/ui/app.py zorg/trunk/lnt/lnt/server/ui/views.py Modified: zorg/trunk/lnt/lnt/server/ui/app.py URL: http://llvm.org/viewvc/llvm-project/zorg/trunk/lnt/lnt/server/ui/app.py?rev=147042&r1=147041&r2=147042&view=diff ============================================================================== --- zorg/trunk/lnt/lnt/server/ui/app.py (original) +++ zorg/trunk/lnt/lnt/server/ui/app.py Wed Dec 21 00:22:10 2011 @@ -34,6 +34,7 @@ self.request_time = time.time() self.db = None self.db_summary = None + self.testsuite = None def elapsed_time(self): return time.time() - self.request_time @@ -59,6 +60,12 @@ return self.db + def get_testsuite(self): + if self.testsuite is None: + self.testsuite = self.get_db().testsuite[g.testsuite_name] + + return self.testsuite + def get_db_summary(self): return current_app.get_db_summary(g.db_name, self.get_db()) @@ -68,6 +75,14 @@ """ return url_for(*args, db_name=g.db_name, **kwargs) +def v4_url_for(*args, **kwargs): + """ + Like url_for, but handles automatically providing the db_name and + testsuite_name arguments. + """ + return url_for(*args, db_name=g.db_name, testsuite_name=g.testsuite_name, + **kwargs) + class App(flask.Flask): @staticmethod def create_standalone(config_path): @@ -110,6 +125,7 @@ self.jinja_env.globals.update( app=current_app, db_url_for=db_url_for, + v4_url_for=v4_url_for, perfdb=perfdb, old_config=self.old_config) Added: zorg/trunk/lnt/lnt/server/ui/templates/v4_overview.html URL: http://llvm.org/viewvc/llvm-project/zorg/trunk/lnt/lnt/server/ui/templates/v4_overview.html?rev=147042&view=auto ============================================================================== --- zorg/trunk/lnt/lnt/server/ui/templates/v4_overview.html (added) +++ zorg/trunk/lnt/lnt/server/ui/templates/v4_overview.html Wed Dec 21 00:22:10 2011 @@ -0,0 +1,71 @@ +{% set db = request.get_db() %} + +{% extends "layout.html" %} +{% set components = [(testsuite_name, v4_url_for("v4_overview"))] %} +{% block title %}Overview{% endblock %} +{% block body %} + +{# Find recent runs. #} +

Submission Overview

+ + + + + +

+ +

Active Machines

+ + + + + + + + + +{# Show the most active machines. #} +{% for machine_name,r in active_machines|dictsort %} + + + + + +{% endfor %} + +

Latest Submission	Machine	Results
{{r.start_time}}	{{ + r.machine.name}}:{{r.machine.id}}	+ View Results

+ +

Recent Submissions

+ + + + + + + + + + + +{# Show the active submissions. #} +{% for r,run_order in active_submissions %} +{% set m = r.machine %} + + + + + + + +{% endfor %} +

Run Order	Start Time	End Time	Machine	Results
{{run_order}}	{{r.start_time}}	{{r.end_time}}	{{ + m.name}}:{{m.id}}	+ View Results

+ +

+ +{% endblock %} Modified: zorg/trunk/lnt/lnt/server/ui/views.py URL: http://llvm.org/viewvc/llvm-project/zorg/trunk/lnt/lnt/server/ui/views.py?rev=147042&r1=147041&r2=147042&view=diff ============================================================================== --- zorg/trunk/lnt/lnt/server/ui/views.py (original) +++ zorg/trunk/lnt/lnt/server/ui/views.py Wed Dec 21 00:22:10 2011 @@ -170,7 +170,7 @@ filter(RunInfo.key == "tag").\ filter(RunInfo.value == tag).limit(100) recent_runs = list(recent_runs) - + # Compute the active machine list. active_machines = dict((run.machine.name, run) for run in recent_runs[::-1]) @@ -558,3 +558,67 @@ for m in available_machines] return render_template("simple_order_aggregate_report.html", **locals()) + +### +# V4 Schema Viewer + +# Decorator for implementing per-testsuite routes. +def v4_route(rule, **options): + """ + LNT V4 specific route for endpoints which always refer to some testsuite + object. + """ + + # FIXME: This is manually composed with db_route. + def decorator(f): + def wrap(testsuite_name, db_name = None, **args): + # Initialize the test suite parameters on the app globals object. + g.testsuite_name = testsuite_name + + # Initialize the database parameters on the app globals object. + g.db_name = db_name or "default" + g.db_info = current_app.old_config.databases.get(g.db_name) + if g.db_info is None: + abort(404) + + return f(**args) + + frontend.add_url_rule("/v4/" + rule, + f.__name__, wrap, **options) + frontend.add_url_rule("/db_/v4/" + rule, + f.__name__, wrap, **options) + + return wrap + return decorator + + at v4_route("/") +def v4_overview(): + ts = request.get_testsuite() + + # Get the most recent runs in this tag, we just arbitrarily limit to looking + # at the last 100 submission. + recent_runs = ts.query(ts.Run).\ + order_by(ts.Run.start_time.desc()).limit(100) + recent_runs = list(recent_runs) + + # Compute the active machine list. + active_machines = dict((run.machine.name, run) + for run in recent_runs[::-1]) + + # Compute the active submission list. + N = 30 + active_submissions = [(r, r.order.llvm_project_revision) + for r in recent_runs[:N]] + + return render_template("v4_overview.html", + testsuite_name=g.testsuite_name, + active_machines=active_machines, + active_submissions=active_submissions) + + at v4_route("/machine/") +def v4_machine(id): + return "machine %d" % int(id) + + at v4_route("/run/") +def v4_run(id): + return "run %d" % int(id) From daniel at zuster.org Wed Dec 21 00:22:17 2011 From: daniel at zuster.org (Daniel Dunbar) Date: Wed, 21 Dec 2011 06:22:17 -0000 Subject: [llvm-commits] [zorg] r147044 - in /zorg/trunk/lnt/lnt/server/ui: templates/v4_machine.html views.py Message-ID: <20111221062217.E40C82A6C12C@llvm.org> Author: ddunbar Date: Wed Dec 21 00:22:17 2011 New Revision: 147044 URL: http://llvm.org/viewvc/llvm-project?rev=147044&view=rev Log: [lnt/v0.4] lnt.server.ui: Implement V4 machine page. Added: zorg/trunk/lnt/lnt/server/ui/templates/v4_machine.html Modified: zorg/trunk/lnt/lnt/server/ui/views.py Added: zorg/trunk/lnt/lnt/server/ui/templates/v4_machine.html URL: http://llvm.org/viewvc/llvm-project/zorg/trunk/lnt/lnt/server/ui/templates/v4_machine.html?rev=147044&view=auto ============================================================================== --- zorg/trunk/lnt/lnt/server/ui/templates/v4_machine.html (added) +++ zorg/trunk/lnt/lnt/server/ui/templates/v4_machine.html Wed Dec 21 00:22:17 2011 @@ -0,0 +1,92 @@ +{% import "utils.html" as utils %} + +{% set ts = request.get_testsuite() %} +{% set machine = ts.getMachine(id) %} + +{% extends "layout.html" %}{ +% set components = [(testsuite_name, v4_url_for("v4_overview"))] %} +{% block head %} + +{% endblock %} +{% block title %}Machine: {{machine.name}}:{{machine.id}}{% endblock %} +{% block body %} + + + + + + +

+ Homepage +

Relatives:

{{ + m.name}}:{{m.id}}

+ + + + + + + + + +

Nickname	{{machine.name}}
Machine ID	{{machine.id}}

+ + +{{ utils.render_popup_begin('machine_info', 'Machine Info', true, 1) }} +

Fields

+ +{% for item in ts.machine_fields %} + + + + +{% endfor %} +

{{item.name}}

Parameters

+ +{% for key,value in machine.get_parameters() %} + + + + +{% endfor %} +

{{key}}

+{{ utils.render_popup_end() }} + +

+ + + + + + + + + +{% for order,runs in associated_runs|sort|reverse %} +{% for run in runs %} + +{% if loop.first %} + +{% endif %} + + + + +{% endfor %} +{% endfor %} +
Run Order Start Time End Time
{{order}} {{ run.start_time }} {{ run.end_time }}s + View Results
+ + +

+ +{% endblock %} Modified: zorg/trunk/lnt/lnt/server/ui/views.py URL: http://llvm.org/viewvc/llvm-project/zorg/trunk/lnt/lnt/server/ui/views.py?rev=147044&r1=147043&r2=147044&view=diff ============================================================================== --- zorg/trunk/lnt/lnt/server/ui/views.py (original) +++ zorg/trunk/lnt/lnt/server/ui/views.py Wed Dec 21 00:22:17 2011 @@ -606,6 +606,8 @@ for run in recent_runs[::-1]) # Compute the active submission list. + # + # FIXME: Remove hard coded field use here. N = 30 active_submissions = [(r, r.order.llvm_project_revision) for r in recent_runs[:N]] @@ -615,9 +617,25 @@ active_machines=active_machines, active_submissions=active_submissions) - at v4_route("/machine/") + at v4_route("/machine/") def v4_machine(id): - return "machine %d" % int(id) + # Compute the list of associated runs, grouped by order. + from lnt.server.ui import util + + # Gather all the runs on this machine. + ts = request.get_testsuite() + + # FIXME: Remove hard coded field use here. + associated_runs = util.multidict( + (run_order, r) + for r,run_order in ts.query(ts.Run, ts.Order.llvm_project_revision).\ + join(ts.Order).\ + filter(ts.Run.machine_id == id)) + associated_runs = associated_runs.items() + + return render_template("v4_machine.html", + testsuite_name=g.testsuite_name, id=id, + associated_runs=associated_runs) @v4_route("/run/") def v4_run(id): From craig.topper at gmail.com Wed Dec 21 00:30:53 2011 From: craig.topper at gmail.com (Craig Topper) Date: Wed, 21 Dec 2011 06:30:53 -0000 Subject: [llvm-commits] [llvm] r147045 - /llvm/trunk/lib/Target/X86/Disassembler/X86Disassembler.h Message-ID: <20111221063053.46F562A6C12C@llvm.org> Author: ctopper Date: Wed Dec 21 00:30:53 2011 New Revision: 147045 URL: http://llvm.org/viewvc/llvm-project?rev=147045&view=rev Log: Fix typo in a couple comments Modified: llvm/trunk/lib/Target/X86/Disassembler/X86Disassembler.h Modified: llvm/trunk/lib/Target/X86/Disassembler/X86Disassembler.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/Disassembler/X86Disassembler.h?rev=147045&r1=147044&r2=147045&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/Disassembler/X86Disassembler.h (original) +++ llvm/trunk/lib/Target/X86/Disassembler/X86Disassembler.h Wed Dec 21 00:30:53 2011 @@ -133,9 +133,9 @@ X86_16Disassembler(const MCSubtargetInfo &STI) : X86GenericDisassembler(STI, MODE_16BIT) { } -}; +}; -/// X86_16Disassembler - 32-bit X86 disassembler. +/// X86_32Disassembler - 32-bit X86 disassembler. class X86_32Disassembler : public X86GenericDisassembler { virtual void anchor(); public: @@ -144,7 +144,7 @@ } }; -/// X86_16Disassembler - 64-bit X86 disassembler. +/// X86_64Disassembler - 64-bit X86 disassembler. class X86_64Disassembler : public X86GenericDisassembler { virtual void anchor(); public: From anton at korobeynikov.info Wed Dec 21 01:57:59 2011 From: anton at korobeynikov.info (Anton Korobeynikov) Date: Wed, 21 Dec 2011 11:57:59 +0400 Subject: [llvm-commits] [llvm] r146604 - in /llvm/trunk: lib/CodeGen/MachineSink.cpp test/CodeGen/ARM/2011-12-14-machine-sink.ll In-Reply-To: <91FF2423-D67D-4E80-985B-532E27DF3799@apple.com> References: <20111214232038.E9C9D2A6C12C@llvm.org> <5FF21D31-13D7-4EAA-99FC-EFC1AFA0C8F7@apple.com> <618FAA67-0A0A-4D20-9E58-491632F2BA7C@apple.com> <91FF2423-D67D-4E80-985B-532E27DF3799@apple.com> Message-ID: > One alternative for you is to reproduce segfault in debugger and investigate what is being compiled. > > Other alternative is to narrow down the particular MI sink that is difference maker. You can do this by disabling this patch and adding a artificial threshold in Machine Sink pass to control how many instructions are sinked. One you know the critical MI sink, you can investigate how it impacts other passes, including register allocator, down the road. > > I am afraid, there is not any easy answer. Previously one could use bugpoint to reduce such problems automatically via splitting the code into two parts, compiling one part with gcc and another - via llvm. Though, I doubt this will work right now since cbe is broken now. That said, you do not have any automatic reduction in such cases and should do everything by hands. -- With best regards, Anton Korobeynikov Faculty of Mathematics and Mechanics, Saint Petersburg State University From craig.topper at gmail.com Wed Dec 21 02:06:52 2011 From: craig.topper at gmail.com (Craig Topper) Date: Wed, 21 Dec 2011 08:06:52 -0000 Subject: [llvm-commits] [llvm] r147046 - in /llvm/trunk/lib/Target: MBlaze/Disassembler/MBlazeDisassembler.h X86/Disassembler/X86Disassembler.cpp X86/Disassembler/X86Disassembler.h Message-ID: <20111221080652.BEF9B2A6C12C@llvm.org> Author: ctopper Date: Wed Dec 21 02:06:52 2011 New Revision: 147046 URL: http://llvm.org/viewvc/llvm-project?rev=147046&view=rev Log: Remove mode specific disassembler classes and just call X86GenericDisassembler constructor with appropriate argument in the creation functions. This removes a few tables that needed to be anchored. Modified: llvm/trunk/lib/Target/MBlaze/Disassembler/MBlazeDisassembler.h llvm/trunk/lib/Target/X86/Disassembler/X86Disassembler.cpp llvm/trunk/lib/Target/X86/Disassembler/X86Disassembler.h Modified: llvm/trunk/lib/Target/MBlaze/Disassembler/MBlazeDisassembler.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MBlaze/Disassembler/MBlazeDisassembler.h?rev=147046&r1=147045&r2=147046&view=diff ============================================================================== --- llvm/trunk/lib/Target/MBlaze/Disassembler/MBlazeDisassembler.h (original) +++ llvm/trunk/lib/Target/MBlaze/Disassembler/MBlazeDisassembler.h Wed Dec 21 02:06:52 2011 @@ -17,8 +17,6 @@ #include "llvm/MC/MCDisassembler.h" -struct InternalInstruction; - namespace llvm { class MCInst; Modified: llvm/trunk/lib/Target/X86/Disassembler/X86Disassembler.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/Disassembler/X86Disassembler.cpp?rev=147046&r1=147045&r2=147046&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/Disassembler/X86Disassembler.cpp (original) +++ llvm/trunk/lib/Target/X86/Disassembler/X86Disassembler.cpp Wed Dec 21 02:06:52 2011 @@ -79,12 +79,6 @@ return instInfoX86; } -void X86_16Disassembler::anchor() { } - -void X86_32Disassembler::anchor() { } - -void X86_64Disassembler::anchor() { } - /// regionReader - a callback function that wraps the readByte method from /// MemoryObject. /// @@ -597,11 +591,11 @@ } static MCDisassembler *createX86_32Disassembler(const Target &T, const MCSubtargetInfo &STI) { - return new X86Disassembler::X86_32Disassembler(STI); + return new X86Disassembler::X86GenericDisassembler(STI, MODE_32BIT); } static MCDisassembler *createX86_64Disassembler(const Target &T, const MCSubtargetInfo &STI) { - return new X86Disassembler::X86_64Disassembler(STI); + return new X86Disassembler::X86GenericDisassembler(STI, MODE_64BIT); } extern "C" void LLVMInitializeX86Disassembler() { Modified: llvm/trunk/lib/Target/X86/Disassembler/X86Disassembler.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/Disassembler/X86Disassembler.h?rev=147046&r1=147045&r2=147046&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/Disassembler/X86Disassembler.h (original) +++ llvm/trunk/lib/Target/X86/Disassembler/X86Disassembler.h Wed Dec 21 02:06:52 2011 @@ -87,8 +87,6 @@ #include "llvm/MC/MCDisassembler.h" -struct InternalInstruction; - namespace llvm { class MCInst; @@ -104,13 +102,14 @@ /// All each platform class should have to do is subclass the constructor, and /// provide a different disassemblerMode value. class X86GenericDisassembler : public MCDisassembler { -protected: +public: /// Constructor - Initializes the disassembler. /// /// @param mode - The X86 architecture mode to decode for. X86GenericDisassembler(const MCSubtargetInfo &STI, DisassemblerMode mode); -public: +private: ~X86GenericDisassembler(); +public: /// getInstruction - See MCDisassembler. DecodeStatus getInstruction(MCInst &instr, @@ -126,35 +125,8 @@ DisassemblerMode fMode; }; -/// X86_16Disassembler - 16-bit X86 disassembler. -class X86_16Disassembler : public X86GenericDisassembler { - virtual void anchor(); -public: - X86_16Disassembler(const MCSubtargetInfo &STI) : - X86GenericDisassembler(STI, MODE_16BIT) { - } -}; - -/// X86_32Disassembler - 32-bit X86 disassembler. -class X86_32Disassembler : public X86GenericDisassembler { - virtual void anchor(); -public: - X86_32Disassembler(const MCSubtargetInfo &STI) : - X86GenericDisassembler(STI, MODE_32BIT) { - } -}; - -/// X86_64Disassembler - 64-bit X86 disassembler. -class X86_64Disassembler : public X86GenericDisassembler { - virtual void anchor(); -public: - X86_64Disassembler(const MCSubtargetInfo &STI) : - X86GenericDisassembler(STI, MODE_64BIT) { - } -}; - } // namespace X86Disassembler - + } // namespace llvm - + #endif From victor.umansky at intel.com Wed Dec 21 03:00:30 2011 From: victor.umansky at intel.com (Umansky, Victor) Date: Wed, 21 Dec 2011 09:00:30 +0000 Subject: [llvm-commits] x86 branch sequence optimization in LLVM code gen: please review In-Reply-To: <021AD592C708E24FA11FD214489EC9BE01269D1FA3@hasmsx501.ger.corp.intel.com> References: <021AD592C708E24FA11FD214489EC9BE0123F25260@hasmsx501.ger.corp.intel.com> <021AD592C708E24FA11FD214489EC9BE0123F95DDF@hasmsx501.ger.corp.intel.com> <90F01864-DEB5-4DEA-B8E2-625EF4449126@apple.com> <021AD592C708E24FA11FD214489EC9BE0123FE98C8@hasmsx501.ger.corp.intel.com> <021AD592C708E24FA11FD214489EC9BE01269D1FA3@hasmsx501.ger.corp.intel.com> Message-ID: Hi Bruno, I've updated the patch with additional peephole-optimization patterns and with additional AVX-specific LIT test. Can you please review, so that I'll proceed to commit the fixes? Best Regards, Victor -----Original Message----- From: llvm-commits-bounces at cs.uiuc.edu [mailto:llvm-commits-bounces at cs.uiuc.edu] On Behalf Of Umansky, Victor Sent: Thursday, December 15, 2011 20:09 To: Bruno Cardoso Lopes Cc: llvm-commits at cs.uiuc.edu Subject: Re: [llvm-commits] x86 branch sequence optimization in LLVM code gen: please review Hi Bruno, Please see attached the patch. It incorporates the feedback, and I yet extended it with coverage for more LLVM IR patterns related to usage of ptestz/ptestc LLVM built-ins (tests are also extended). Best Regards, Victor -----Original Message----- From: Bruno Cardoso Lopes [mailto:bruno.cardoso at gmail.com] Sent: Friday, December 09, 2011 04:25 To: Umansky, Victor Cc: Chad Rosier; Anton Korobeynikov; bruno.cardoso at gmail.com; llvm-commits at cs.uiuc.edu Subject: Re: [llvm-commits] x86 branch sequence optimization in LLVM code gen: please review On Wed, Dec 7, 2011 at 1:03 PM, Umansky, Victor wrote: > > Hi Chad, Anton, Bruno, > > > > Thank you for the suggestion. > > > > Unfortunately, it won't work in the case of brcond.ll file. > > > > Indeed I can introduce different "check-prefix" values in order to separate checks for "core2" case from those for "penryn" case. > > However, the compilation of all functions in a file will be done unconditionally for both "RUN" cases. And this will inevitably lead to the test failure (in instruction selection) when a function using "ptest" LLVM intrinsic will be processed with "-mcpu=core2" option. > > That's why I was not able to include the test cases for "ptest" intrinsic sequence to a file which will be compiled for a pre-Penryn target. > > > > A solution which does work is to have legacy brcond.ll LIT tests running under "-mcpu=penryn". > > I'm attaching the file. > > Are you OK with such solution? LGTM, please resend the orignal patch with the testcase (both in the same patch file)! Also remove the trailing CRs and generate the diff with "svn diff" under the project root. If you have any question, the docs may help: http://llvm.org/docs/DeveloperPolicy.html#patches -- Bruno Cardoso Lopes http://www.brunocardoso.cc --------------------------------------------------------------------- Intel Israel (74) Limited This e-mail and any attachments may contain confidential material for the sole use of the intended recipient(s). Any review or distribution by others is strictly prohibited. If you are not the intended recipient, please contact the sender and delete all copies. --------------------------------------------------------------------- Intel Israel (74) Limited This e-mail and any attachments may contain confidential material for the sole use of the intended recipient(s). Any review or distribution by others is strictly prohibited. If you are not the intended recipient, please contact the sender and delete all copies. -------------- next part -------------- A non-text attachment was scrubbed... Name: brcond_combine.patch Type: application/octet-stream Size: 22585 bytes Desc: brcond_combine.patch Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20111221/1bfb489d/attachment-0001.obj From klimek at google.com Wed Dec 21 04:02:45 2011 From: klimek at google.com (Manuel Klimek) Date: Wed, 21 Dec 2011 10:02:45 -0000 Subject: [llvm-commits] [llvm] r147049 - /llvm/trunk/lib/AsmParser/LLLexer.h Message-ID: <20111221100245.EC8302A6C12C@llvm.org> Author: klimek Date: Wed Dec 21 04:02:45 2011 New Revision: 147049 URL: http://llvm.org/viewvc/llvm-project?rev=147049&view=rev Log: Removes unused field TheError from LLLexer. Modified: llvm/trunk/lib/AsmParser/LLLexer.h Modified: llvm/trunk/lib/AsmParser/LLLexer.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/AsmParser/LLLexer.h?rev=147049&r1=147048&r2=147049&view=diff ============================================================================== --- llvm/trunk/lib/AsmParser/LLLexer.h (original) +++ llvm/trunk/lib/AsmParser/LLLexer.h Wed Dec 21 04:02:45 2011 @@ -42,7 +42,6 @@ APFloat APFloatVal; APSInt APSIntVal; - std::string TheError; public: explicit LLLexer(MemoryBuffer *StartBuf, SourceMgr &SM, SMDiagnostic &, LLVMContext &C); From klimek at google.com Wed Dec 21 04:06:47 2011 From: klimek at google.com (Manuel Klimek) Date: Wed, 21 Dec 2011 11:06:47 +0100 Subject: [llvm-commits] PATCH: remove unused variable TheError In-Reply-To: References:

Message-ID: On Wed, Dec 21, 2011 at 12:30 AM, James Molloy wrote: > Manuel, > > Do you have commit access? If not, I can commit for you. Commited. Yes, I have access, I just wasn't sure where the line is for "obvious" changes and was rather erring on the side of asking :) Thanks, /Manuel > > James > ________________________________________ > From: llvm-commits-bounces at cs.uiuc.edu [llvm-commits-bounces at cs.uiuc.edu] On Behalf Of Chandler Carruth [chandlerc at google.com] > Sent: 20 December 2011 23:16 > To: Manuel Klimek > Cc: llvm-commits at cs.uiuc.edu > Subject: Re: [llvm-commits] PATCH: remove unused variable TheError > > On Tue, Dec 20, 2011 at 6:54 AM, Manuel Klimek > wrote: > While searching for an example to model my use of SourceMgr after, I > stumbled over LLLexer.h and found what looks like an unused variable - > this patch would remove it, if there's not some hidden use of TheError > that I'm missing. > > Looks good. As long as this kind of change doesn't break the build in some way, always feel free to commit as "obvious". > > > diff --git a/lib/AsmParser/LLLexer.h b/lib/AsmParser/LLLexer.h > index 33b9135..09aea5b 100644 > --- a/lib/AsmParser/LLLexer.h > +++ b/lib/AsmParser/LLLexer.h > @@ -42,7 +42,6 @@ namespace llvm { > ? ?APFloat APFloatVal; > ? ?APSInt ?APSIntVal; > > - ? ?std::string TheError; > ?public: > ? ?explicit LLLexer(MemoryBuffer *StartBuf, SourceMgr &SM, SMDiagnostic &, > ? ? ? ? ? ? ? ? ? ? LLVMContext &C); > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits > > > -- IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. ?Thank you. > From eugeni.stepanov at gmail.com Wed Dec 21 05:52:32 2011 From: eugeni.stepanov at gmail.com (Evgeniy Stepanov) Date: Wed, 21 Dec 2011 15:52:32 +0400 Subject: [llvm-commits] [PATCH] asan-rt: fix signal wrapper on Android Message-ID: Hi, this patch wraps bsd_signal instead of signal on Android. Signal is a macro there. -------------- next part -------------- A non-text attachment was scrubbed... Name: bsd_signal.patch Type: text/x-patch Size: 1775 bytes Desc: not available Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20111221/98613d48/attachment.bin From eugeni.stepanov at gmail.com Wed Dec 21 05:57:23 2011 From: eugeni.stepanov at gmail.com (Evgeniy Stepanov) Date: Wed, 21 Dec 2011 15:57:23 +0400 Subject: [llvm-commits] [PATCH] asan-rt: getenv() from .preinit_array Message-ID: Hi, this patch brings in the implementation of GetenvBeforeMain() from google-perftools and uses it in place of getenv(). This is required to call __asan_init from .preinit_array. -------------- next part -------------- A non-text attachment was scrubbed... Name: getenv.patch Type: text/x-patch Size: 3690 bytes Desc: not available Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20111221/c625756a/attachment.bin From eugeni.stepanov at gmail.com Wed Dec 21 05:59:57 2011 From: eugeni.stepanov at gmail.com (Evgeniy Stepanov) Date: Wed, 21 Dec 2011 15:59:57 +0400 Subject: [llvm-commits] [PATCH] asan-rt: wrappers for new() on Android Message-ID: Hi, new() has slightly different signature on Android. This patch adds the required wrappers. -------------- next part -------------- A non-text attachment was scrubbed... Name: new_nothrow.patch Type: text/x-patch Size: 809 bytes Desc: not available Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20111221/f41e4fc8/attachment.bin From eugeni.stepanov at gmail.com Wed Dec 21 06:08:51 2011 From: eugeni.stepanov at gmail.com (Evgeniy Stepanov) Date: Wed, 21 Dec 2011 16:08:51 +0400 Subject: [llvm-commits] [PATCH] asan-rt: add definitions for ucontext_t and friends on Android Message-ID: Hi, libc headers on Android miss ucontext_t and friends. This patch adds some compatible definitions. -------------- next part -------------- A non-text attachment was scrubbed... Name: ucontext.patch Type: text/x-patch Size: 3275 bytes Desc: not available Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20111221/d57ea47d/attachment.bin From eugeni.stepanov at gmail.com Wed Dec 21 06:10:22 2011 From: eugeni.stepanov at gmail.com (Evgeniy Stepanov) Date: Wed, 21 Dec 2011 16:10:22 +0400 Subject: [llvm-commits] [PATCH] asan-rt: no cfree() on Android Message-ID: Hi, this patch disables the cfree() test on Android. -------------- next part -------------- A non-text attachment was scrubbed... Name: cfree.patch Type: text/x-patch Size: 325 bytes Desc: not available Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20111221/26c3c929/attachment.bin From eugeni.stepanov at gmail.com Wed Dec 21 06:14:26 2011 From: eugeni.stepanov at gmail.com (Evgeniy Stepanov) Date: Wed, 21 Dec 2011 16:14:26 +0400 Subject: [llvm-commits] [PATCH] asan-rt: use .preinit_array when not building a shared runtime library Message-ID: Hi, this is an N-th attempt to use .preinit_array for asan initialization. This time we only do it when the shared runtime library is not being built. This patch should go in after the stacksize and getenv patch I've sent earlier today. -------------- next part -------------- A non-text attachment was scrubbed... Name: preinit_array.patch Type: text/x-patch Size: 2583 bytes Desc: not available Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20111221/bc906f55/attachment.bin From eugeni.stepanov at gmail.com Wed Dec 21 06:26:18 2011 From: eugeni.stepanov at gmail.com (Evgeniy Stepanov) Date: Wed, 21 Dec 2011 16:26:18 +0400 Subject: [llvm-commits] [PATCH] Add -androideabi to llvm::Triple Message-ID: Hi, recent Android toolchains use arm-linux-androideabi as triple. Having androideabi in llvm::Triple::EnvironmentType will simplify cross-compilation and let Clang pick saner defaults for -mfloat-abi, among other things. Please review. -------------- next part -------------- A non-text attachment was scrubbed... Name: androideabi.patch Type: text/x-patch Size: 907 bytes Desc: not available Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20111221/8cb9fc33/attachment.bin -------------- next part -------------- A non-text attachment was scrubbed... Name: androideabi-cfe.patch Type: text/x-patch Size: 2310 bytes Desc: not available Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20111221/8cb9fc33/attachment-0001.bin From chandlerc at google.com Wed Dec 21 06:31:01 2011 From: chandlerc at google.com (Chandler Carruth) Date: Wed, 21 Dec 2011 04:31:01 -0800 Subject: [llvm-commits] [PATCH] Add -androideabi to llvm::Triple In-Reply-To: References: Message-ID: FYI, I'll try to look at these tomorrow, but one quick note, whenever you have patches to both LLVM and Clang, please send them to both llvm-commits and cfe-commits. Not all of the Clang developers read llvm-commits or vice-versa. On Wed, Dec 21, 2011 at 4:26 AM, Evgeniy Stepanov wrote: > Hi, > > recent Android toolchains use arm-linux-androideabi as triple. Having > androideabi in llvm::Triple::EnvironmentType will simplify > cross-compilation and let Clang pick saner defaults for -mfloat-abi, > among other things. > > Please review. > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits > > -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20111221/cbbb9f1d/attachment.html From eugeni.stepanov at gmail.com Wed Dec 21 06:04:09 2011 From: eugeni.stepanov at gmail.com (Evgeniy Stepanov) Date: Wed, 21 Dec 2011 16:04:09 +0400 Subject: [llvm-commits] [PATCH] asan-rt: discover main thread stack limits without pthread Message-ID: Hi, if __asan_init is called from .preinit_array, pthread_getattr_np may become unsafe. This patch adds a different way of locating the stack of the main thread with a combination of getlrimit() and /proc/self/maps. -------------- next part -------------- A non-text attachment was scrubbed... Name: stacksize.patch Type: text/x-patch Size: 2846 bytes Desc: not available Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20111221/61818618/attachment.bin From hfinkel at anl.gov Wed Dec 21 07:49:57 2011 From: hfinkel at anl.gov (Hal Finkel) Date: Wed, 21 Dec 2011 07:49:57 -0600 Subject: [llvm-commits] [PATCH] Allow SelectionDAGBuilder to reorder loads past stores In-Reply-To: <1324407129.31367.481.camel@sapling> References: <1324316529.31367.96.camel@sapling> <945273C4-D0AA-4CAF-B0ED-C6D96A52FE02@apple.com> <1324325951.31367.178.camel@sapling> <1324355462.31367.287.camel@sapling> <2264DB7F-F14F-4D93-B6C1-79D69B5F2DBF@apple.com> <1324401740.31367.437.camel@sapling> <4B06FCD2-5607-4F5A-989E-C961B6DD6FE4@2pi.dk> <1324407129.31367.481.camel@sapling> Message-ID: <1324475397.31367.527.camel@sapling> It turns out that a significant cause of the performance regressions caused by this patch are related to this issue: with the patch applied the scheduler is now free to schedule many more things, especially stores, after calls (especially intrinsics that are expanded to lib calls). This tendency is bad because of the spilling necessary to cross the call boundary. I am working on a proposed solution, and I'll post an updated patch soon. Thanks again, Hal On Tue, 2011-12-20 at 12:52 -0600, Hal Finkel wrote: > On Tue, 2011-12-20 at 10:44 -0800, Jakob Stoklund Olesen wrote: > > On Dec 20, 2011, at 9:22 AM, Hal Finkel wrote: > > > > > when I later look at the register map, only XMM0 and XMM1 are ever > > > assigned to vregs, everything else is spilled. This is wrong. Do you > > > have any ideas on what could be going wrong or other things I should > > > examine? Could the register allocator not be accounting correctly for > > > callee-saved registers when computing live-interval interference > > > information? > > > > There are no callee-saved xmm registers. > > Thanks! I was mixing up the Win64 calling convention with the regular > one. That explains things, so, I suppose the right thing to do is to > make sure all stores are flushed before any call (which I think it > already does), and any intrinsic that will be expanded (which it will > not currently do). > > -Hal > > > > > /jakob > > > -- Hal Finkel Postdoctoral Appointee Leadership Computing Facility Argonne National Laboratory From rafael.espindola at gmail.com Wed Dec 21 08:26:30 2011 From: rafael.espindola at gmail.com (Rafael Espindola) Date: Wed, 21 Dec 2011 14:26:30 -0000 Subject: [llvm-commits] [llvm] r147053 - in /llvm/trunk/lib/MC: ELFObjectWriter.cpp ELFObjectWriter.h Message-ID: <20111221142630.313F52A6C12C@llvm.org> Author: rafael Date: Wed Dec 21 08:26:29 2011 New Revision: 147053 URL: http://llvm.org/viewvc/llvm-project?rev=147053&view=rev Log: Small refactoring so that RelocNeedsGOT can stay in the target independent side when the target specific bits are moved to the Target directory. Modified: llvm/trunk/lib/MC/ELFObjectWriter.cpp llvm/trunk/lib/MC/ELFObjectWriter.h Modified: llvm/trunk/lib/MC/ELFObjectWriter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/ELFObjectWriter.cpp?rev=147053&r1=147052&r2=147053&view=diff ============================================================================== --- llvm/trunk/lib/MC/ELFObjectWriter.cpp (original) +++ llvm/trunk/lib/MC/ELFObjectWriter.cpp Wed Dec 21 08:26:29 2011 @@ -447,6 +447,10 @@ FixedValue = Value; unsigned Type = GetRelocType(Target, Fixup, IsPCRel, (RelocSymbol != 0), Addend); + MCSymbolRefExpr::VariantKind Modifier = Target.isAbsolute() ? + MCSymbolRefExpr::VK_None : Target.getSymA()->getKind(); + if (RelocNeedsGOT(Modifier)) + NeedsGOT = true; uint64_t RelocOffset = Layout.getFragmentOffset(Fragment) + Fixup.getOffset(); @@ -1385,16 +1389,8 @@ const MCFixup &Fixup, bool IsPCRel, bool IsRelocWithSymbol, - int64_t Addend) { - MCSymbolRefExpr::VariantKind Modifier = Target.isAbsolute() ? - MCSymbolRefExpr::VK_None : Target.getSymA()->getKind(); - - unsigned Type = GetRelocTypeInner(Target, Fixup, IsPCRel); - - if (RelocNeedsGOT(Modifier)) - NeedsGOT = true; - - return Type; + int64_t Addend) const { + return GetRelocTypeInner(Target, Fixup, IsPCRel); } unsigned ARMELFObjectWriter::GetRelocTypeInner(const MCValue &Target, @@ -1536,7 +1532,7 @@ const MCFixup &Fixup, bool IsPCRel, bool IsRelocWithSymbol, - int64_t Addend) { + int64_t Addend) const { // determine the type of the relocation unsigned Type; if (IsPCRel) { @@ -1606,7 +1602,7 @@ const MCFixup &Fixup, bool IsPCRel, bool IsRelocWithSymbol, - int64_t Addend) { + int64_t Addend) const { // determine the type of the relocation unsigned Type; if (IsPCRel) { @@ -1652,7 +1648,7 @@ const MCFixup &Fixup, bool IsPCRel, bool IsRelocWithSymbol, - int64_t Addend) { + int64_t Addend) const { // determine the type of the relocation MCSymbolRefExpr::VariantKind Modifier = Target.isAbsolute() ? @@ -1822,9 +1818,6 @@ } } - if (RelocNeedsGOT(Modifier)) - NeedsGOT = true; - return Type; } @@ -1862,7 +1855,7 @@ const MCFixup &Fixup, bool IsPCRel, bool IsRelocWithSymbol, - int64_t Addend) { + int64_t Addend) const { // determine the type of the relocation unsigned Type = (unsigned)ELF::R_MIPS_NONE; unsigned Kind = (unsigned)Fixup.getKind(); Modified: llvm/trunk/lib/MC/ELFObjectWriter.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/ELFObjectWriter.h?rev=147053&r1=147052&r2=147053&view=diff ============================================================================== --- llvm/trunk/lib/MC/ELFObjectWriter.h (original) +++ llvm/trunk/lib/MC/ELFObjectWriter.h Wed Dec 21 08:26:29 2011 @@ -351,7 +351,7 @@ protected: virtual unsigned GetRelocType(const MCValue &Target, const MCFixup &Fixup, bool IsPCRel, bool IsRelocWithSymbol, - int64_t Addend) = 0; + int64_t Addend) const = 0; virtual void adjustFixupOffset(const MCFixup &Fixup, uint64_t &RelocOffset) {} }; @@ -368,7 +368,7 @@ protected: virtual unsigned GetRelocType(const MCValue &Target, const MCFixup &Fixup, bool IsPCRel, bool IsRelocWithSymbol, - int64_t Addend); + int64_t Addend) const; }; @@ -395,11 +395,10 @@ virtual unsigned GetRelocType(const MCValue &Target, const MCFixup &Fixup, bool IsPCRel, bool IsRelocWithSymbol, - int64_t Addend); + int64_t Addend) const; private: unsigned GetRelocTypeInner(const MCValue &Target, const MCFixup &Fixup, bool IsPCRel) const; - }; //===- PPCELFObjectWriter -------------------------------------------===// @@ -414,7 +413,7 @@ protected: virtual unsigned GetRelocType(const MCValue &Target, const MCFixup &Fixup, bool IsPCRel, bool IsRelocWithSymbol, - int64_t Addend); + int64_t Addend) const; virtual void adjustFixupOffset(const MCFixup &Fixup, uint64_t &RelocOffset); }; @@ -430,7 +429,7 @@ protected: virtual unsigned GetRelocType(const MCValue &Target, const MCFixup &Fixup, bool IsPCRel, bool IsRelocWithSymbol, - int64_t Addend); + int64_t Addend) const; }; //===- MipsELFObjectWriter -------------------------------------------===// @@ -453,7 +452,7 @@ virtual unsigned GetRelocType(const MCValue &Target, const MCFixup &Fixup, bool IsPCRel, bool IsRelocWithSymbol, - int64_t Addend); + int64_t Addend) const; }; } From rafael.espindola at gmail.com Wed Dec 21 08:48:04 2011 From: rafael.espindola at gmail.com (Rafael Espindola) Date: Wed, 21 Dec 2011 14:48:04 -0000 Subject: [llvm-commits] [llvm] r147054 - /llvm/trunk/include/llvm/MC/MCELFObjectWriter.h Message-ID: <20111221144804.419122A6C12C@llvm.org> Author: rafael Date: Wed Dec 21 08:48:04 2011 New Revision: 147054 URL: http://llvm.org/viewvc/llvm-project?rev=147054&view=rev Log: Add const. Modified: llvm/trunk/include/llvm/MC/MCELFObjectWriter.h Modified: llvm/trunk/include/llvm/MC/MCELFObjectWriter.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/MC/MCELFObjectWriter.h?rev=147054&r1=147053&r2=147054&view=diff ============================================================================== --- llvm/trunk/include/llvm/MC/MCELFObjectWriter.h (original) +++ llvm/trunk/include/llvm/MC/MCELFObjectWriter.h Wed Dec 21 08:48:04 2011 @@ -31,7 +31,7 @@ Triple::OSType getOSType() { return OSType; } uint16_t getEMachine() { return EMachine; } bool hasRelocationAddend() { return HasRelocationAddend; } - bool is64Bit() { return Is64Bit; } + bool is64Bit() const { return Is64Bit; } /// @} }; From kristof.beyls at arm.com Wed Dec 21 09:01:01 2011 From: kristof.beyls at arm.com (Kristof Beyls) Date: Wed, 21 Dec 2011 15:01:01 -0000 Subject: [llvm-commits] [PATCH] MC ARM Thumb: fix incorrect relocation generation (PR11214) In-Reply-To: <854417BF-9EFC-4743-A8F3-249712BC9ADD@apple.com> References: <000001ccbf1d$618f7490$24ae5db0$%beyls@arm.com> <57817466-3086-4652-85E2-4959AF23D81B@apple.com> <107270DB-89BE-4C71-9181-CF7FDD300E25@apple.com> <854417BF-9EFC-4743-A8F3-249712BC9ADD@apple.com> Message-ID: <000001ccbff1$5afc4ed0$10f4ec70$@beyls@arm.com> Hi Jim, (I included Rafael and Koan-sin in cc since they committed the code that this proposed patch changes) Thanks for your answer. I'm not an ELF expert, but I do think that R_ARM_THM_CALL is always the correct relocation for Thumb BL and BLX instructions, for the following reasons: * I checked with 2 ELF experts in the office, and they agree that Thumb BL and BLX instructions always need to have relocation R_ARM_THM_CALL, no matter whether it's a PLT or a non-PLT reference. This is in line with what the ARM AAELF ABI states, section 4.7.1.6. "Static Thumb32 relocations": "R_ARM_THM_CALL is used to relocate Thumb BL (and ARMv5 Thumb BLX) instructions." There's no distinction between PLT or non-PLT references. * I ran the assembler code in the regression test in the patch through both GNU as and armasm (the assembler from ARM Compiler 5, a.k.a. 'armcc'). They both produce the R_ARM_THUMB relocation, as expected. * We found this issue because we were trying to compile and run a bare metal version of dhrystone. Without the patch, the final image is not linked correctly, resulting in an infinite loop. With this patch, it compiles and links correctly. The code in the case statement that will be changed, came from a single commit, r131748, and was discussed in the following mail thread: http://lists.cs.uiuc.edu/pipermail/llvmdev/2011-May/040088.html. Rafael or Koan-sin, do you happen to know or remember why patch r131748 special cases MCSymbolRefExpr::VK_ARM_PLT? $ svn log -c 131748 ------------------------------------------------------------------------ r131748 | rafael | 2011-05-20 21:01:01 +0100 (Fri, 20 May 2011) | 4 lines fixes target address tBL and tBLX and sets relocation type of tBL/tBLX to R_ARM_THM_CALL (ARM ELF 4.7.1.6) Patch by koan-sin tan. ------------------------------------------------------------------------ $ svn diff -c 131748 ... Index: lib/MC/ELFObjectWriter.cpp =================================================================== --- lib/MC/ELFObjectWriter.cpp (revision 131747) +++ lib/MC/ELFObjectWriter.cpp (revision 131748) @@ -1441,6 +1441,17 @@ case ARM::fixup_t2_movw_lo16_pcrel: Type = ELF::R_ARM_THM_MOVW_PREL_NC; break; + case ARM::fixup_arm_thumb_bl: + case ARM::fixup_arm_thumb_blx: + switch (Modifier) { + case MCSymbolRefExpr::VK_ARM_PLT: + Type = ELF::R_ARM_THM_CALL; + break; + default: + Type = ELF::R_ARM_NONE; + break; + } + break; } ... Thanks, Kristof > -----Original Message----- > From: Jim Grosbach [mailto:grosbach at apple.com] > Sent: 20 December 2011 21:08 > To: Kristof Beyls > Cc: James Molloy; llvm-commits at cs.uiuc.edu > Subject: Re: [llvm-commits] [PATCH] MC ARM Thumb: fix incorrect > relocation generation (PR11214) > > Right. I agree it's fairly clear that R_ARM_NONE is wrong. It's not > clear, however, that R_ARM_THM_CALL is correct for non-PLT relocations. > I suspect it's not else that conditional wouldn't have been there in > the first place. I'm hoping that an ELF knowledgeable person will chime > in and let us know for sure one way or the other. > > -Jim > > > On Dec 20, 2011, at 12:06 PM, Kristof Beyls wrote: > > > The reason why I thought the patch would be OK is that the patch only > > changes the behaviour for the thumb bl and blx instructions (i.e. > only for > > the cases ARM::fixup_arm_thumb_bl and ARM::fixup_arm_thumb_blx. > > > > For these instructions, I can't see why R_ARM_NONE would ever be the > correct > > relocation type. The definition of R_ARM_NONE from the AAELF ABI: > > """ > > R_ARM_NONE records that the section containing the place to be > relocated depends on the section defining the symbol mentioned in the > relocation directive in a way otherwise invisible to the static linker. > The effect is to prevent removal of sections that might otherwise > appear to be unused. > > """ > > > > Thanks, > > > > Kristof > > > >> -----Original Message----- > >> From: Jim Grosbach [mailto:grosbach at apple.com] > >> Sent: 20 December 2011 19:33 > >> To: James Molloy > >> Cc: Kristof Beyls; llvm-commits at cs.uiuc.edu > >> Subject: Re: [llvm-commits] [PATCH] MC ARM Thumb: fix incorrect > >> relocation generation (PR11214) > >> > >> Yeah, that's my guess. An assert(0 "unimplemented non-PLT call!") or > >> something would have been better if that's the case exactly to > prevent > >> this sort of head-scratching. :) > >> > >> -Jim > >> > >> On Dec 20, 2011, at 11:21 AM, James Molloy wrote: > >> > >>> Yeah, I was confused about that too. > >>> > >>> I couldn't comprehend why that conditional was even there in the > >> first place - an R_ARM_NONE relocation is *never* required for a > call > >> (it's a special no-op reloc). > >>> > >>> The only thing I could think of is that someone wanted to fix the > >> relocation given to PLT entries and decided to keep the a broken > >> behaviour for the default case, perhaps they had no knowledge about > it. > >>> ________________________________________ > >>> From: llvm-commits-bounces at cs.uiuc.edu [llvm-commits- > >> bounces at cs.uiuc.edu] On Behalf Of Jim Grosbach [grosbach at apple.com] > >>> Sent: 20 December 2011 19:07 > >>> To: Kristof Beyls > >>> Cc: llvm-commits at cs.uiuc.edu > >>> Subject: Re: [llvm-commits] [PATCH] MC ARM Thumb: fix incorrect > >> relocation generation (PR11214) > >>> > >>> Someone with ELF knowledge should look at this. I'm a bit nervous > >> about removing the conditional as it seems to imply that there's an > >> different relocation that should be generated depending on the > variant > >> kind. > >>> > >>> -Jim > >>> > >>> On Dec 20, 2011, at 5:43 AM, Kristof Beyls wrote: > >>> > >>>> Hi, > >>>> > >>>> Please find a patch for fixing incorrect generation of relocation > >>>> information on Thumb function calls. > >>>> This should fix quite a few incorrect code generation problems in > >> Thumb mode > >>>> when using the integrated assembler. > >>>> I believe this fixes PR11214 > >>>> (http://www.llvm.org/bugs/show_bug.cgi?id=11214). > >>>> > >>>> Is this OK? > >>>> > >>>> Thanks, > >>>> > >>>> Kristof > >>>> > >> > ____________________________________________ > >> ___ > >>>> llvm-commits mailing list > >>>> llvm-commits at cs.uiuc.edu > >>>> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits > >>> > >>> _______________________________________________ > >>> llvm-commits mailing list > >>> llvm-commits at cs.uiuc.edu > >>> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits > >>> > >>> > >>> -- IMPORTANT NOTICE: The contents of this email and any attachments > >> are confidential and may also be privileged. If you are not the > >> intended recipient, please notify the sender immediately and do not > >> disclose the contents to any other person, use it for any purpose, > or > >> store or copy the information in any medium. Thank you. > >>> > >> > >> > > > > > > -- IMPORTANT NOTICE: The contents of this email and any attachments > are confidential and may also be privileged. If you are not the > intended recipient, please notify the sender immediately and do not > disclose the contents to any other person, use it for any purpose, or > store or copy the information in any medium. Thank you. > > > > From james.molloy at arm.com Wed Dec 21 09:12:18 2011 From: james.molloy at arm.com (James Molloy) Date: Wed, 21 Dec 2011 15:12:18 -0000 Subject: [llvm-commits] PATCH: ARM_TARGET1 relocation for C++ global constructors Message-ID: <000c01ccbff2$ee95d750$cbc185f0$@molloy@arm.com> Hi, Attached is a patch to cause the relocations for C++ global/static constructor thunks to be outputted properly on ARM. The ABI states that these thunks should have an R_ARM_TARGET1 relocation type applied to them for portability reasons. Currently they're emitted as normal global variables so get an R_ARM_ABS32. I've implemented this by creating a new overridable hook, "EmitXXStructor()", in the AsmPrinter. For all targets this defaults to EmitGlobalConstant as usual, but ARM overrides it to emit a constant with this specific relocation type. Am I OK to commit? Cheers, James -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20111221/e5e8c230/attachment.html -------------- next part -------------- A non-text attachment was scrubbed... Name: reloc_arm_target1.patch Type: application/octet-stream Size: 3556 bytes Desc: not available Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20111221/e5e8c230/attachment.obj From victor.umansky at intel.com Wed Dec 21 10:10:56 2011 From: victor.umansky at intel.com (Umansky, Victor) Date: Wed, 21 Dec 2011 16:10:56 +0000 Subject: [llvm-commits] x86 branch sequence optimization in LLVM code gen: please review In-Reply-To: References: <021AD592C708E24FA11FD214489EC9BE0123F25260@hasmsx501.ger.corp.intel.com> <021AD592C708E24FA11FD214489EC9BE0123F95DDF@hasmsx501.ger.corp.intel.com> <90F01864-DEB5-4DEA-B8E2-625EF4449126@apple.com> <021AD592C708E24FA11FD214489EC9BE0123FE98C8@hasmsx501.ger.corp.intel.com> <021AD592C708E24FA11FD214489EC9BE01269D1FA3@hasmsx501.ger.corp.intel.com> Message-ID: Replacing patch with a newer one. Changes: aligned naming policy with that of LLVM. Victor -----Original Message----- From: llvm-commits-bounces at cs.uiuc.edu [mailto:llvm-commits-bounces at cs.uiuc.edu] On Behalf Of Umansky, Victor Sent: Wednesday, December 21, 2011 11:01 To: Bruno Cardoso Lopes Cc: llvm-commits at cs.uiuc.edu Subject: Re: [llvm-commits] x86 branch sequence optimization in LLVM code gen: please review Hi Bruno, I've updated the patch with additional peephole-optimization patterns and with additional AVX-specific LIT test. Can you please review, so that I'll proceed to commit the fixes? Best Regards, Victor -----Original Message----- From: llvm-commits-bounces at cs.uiuc.edu [mailto:llvm-commits-bounces at cs.uiuc.edu] On Behalf Of Umansky, Victor Sent: Thursday, December 15, 2011 20:09 To: Bruno Cardoso Lopes Cc: llvm-commits at cs.uiuc.edu Subject: Re: [llvm-commits] x86 branch sequence optimization in LLVM code gen: please review Hi Bruno, Please see attached the patch. It incorporates the feedback, and I yet extended it with coverage for more LLVM IR patterns related to usage of ptestz/ptestc LLVM built-ins (tests are also extended). Best Regards, Victor -----Original Message----- From: Bruno Cardoso Lopes [mailto:bruno.cardoso at gmail.com] Sent: Friday, December 09, 2011 04:25 To: Umansky, Victor Cc: Chad Rosier; Anton Korobeynikov; bruno.cardoso at gmail.com; llvm-commits at cs.uiuc.edu Subject: Re: [llvm-commits] x86 branch sequence optimization in LLVM code gen: please review On Wed, Dec 7, 2011 at 1:03 PM, Umansky, Victor wrote: > > Hi Chad, Anton, Bruno, > > > > Thank you for the suggestion. > > > > Unfortunately, it won't work in the case of brcond.ll file. > > > > Indeed I can introduce different "check-prefix" values in order to separate checks for "core2" case from those for "penryn" case. > > However, the compilation of all functions in a file will be done unconditionally for both "RUN" cases. And this will inevitably lead to the test failure (in instruction selection) when a function using "ptest" LLVM intrinsic will be processed with "-mcpu=core2" option. > > That's why I was not able to include the test cases for "ptest" intrinsic sequence to a file which will be compiled for a pre-Penryn target. > > > > A solution which does work is to have legacy brcond.ll LIT tests running under "-mcpu=penryn". > > I'm attaching the file. > > Are you OK with such solution? LGTM, please resend the orignal patch with the testcase (both in the same patch file)! Also remove the trailing CRs and generate the diff with "svn diff" under the project root. If you have any question, the docs may help: http://llvm.org/docs/DeveloperPolicy.html#patches -- Bruno Cardoso Lopes http://www.brunocardoso.cc --------------------------------------------------------------------- Intel Israel (74) Limited This e-mail and any attachments may contain confidential material for the sole use of the intended recipient(s). Any review or distribution by others is strictly prohibited. If you are not the intended recipient, please contact the sender and delete all copies. --------------------------------------------------------------------- Intel Israel (74) Limited This e-mail and any attachments may contain confidential material for the sole use of the intended recipient(s). Any review or distribution by others is strictly prohibited. If you are not the intended recipient, please contact the sender and delete all copies. --------------------------------------------------------------------- Intel Israel (74) Limited This e-mail and any attachments may contain confidential material for the sole use of the intended recipient(s). Any review or distribution by others is strictly prohibited. If you are not the intended recipient, please contact the sender and delete all copies. -------------- next part -------------- A non-text attachment was scrubbed... Name: brcond_combine.patch Type: application/octet-stream Size: 21527 bytes Desc: brcond_combine.patch Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20111221/06bf5a7d/attachment-0001.obj From slarin at codeaurora.org Wed Dec 21 10:44:22 2011 From: slarin at codeaurora.org (Sergei Larin) Date: Wed, 21 Dec 2011 10:44:22 -0600 Subject: [llvm-commits] [PATCH] Allow SelectionDAGBuilder to reorder loads past stores In-Reply-To: <1324475397.31367.527.camel@sapling> References: <1324316529.31367.96.camel@sapling> <945273C4-D0AA-4CAF-B0ED-C6D96A52FE02@apple.com> <1324325951.31367.178.camel@sapling> <1324355462.31367.287.camel@sapling> <2264DB7F-F14F-4D93-B6C1-79D69B5F2DBF@apple.com> <1324401740.31367.437.camel@sapling> <4B06FCD2-5607-4F5A-989E-C961B6DD6FE4@2pi.dk> <1324407129.31367.481.camel@sapling> <1324475397.31367.527.camel@sapling> Message-ID: <069a01ccbfff$cacf7120$606e5360$@org> Hal, I have actually done the same fix internally (couple months ago) which also resulted in severe performance degradation. To solve it for our back end (Hexagon) I ended up modifying the scheduler. In fact I have introduced our own (calling it VLIW) scheduler to handle newly available parallelism and resulting reg pressure. Result was significant overall performance gain on a wide (internal) test suite, with some kernels gaining 40-60%. I tried to accomplish the same with existing infrastructure, but failed. Now you are seeing similar issue with another architecture. I really wonder what your next move shell be. I have not checked my changes in for a simple reason that we are not caught with the LLVM tip in our internal repository (we are several months behind), and Evan has changed the game rules enough (I mean the removal of top-down schedulers) ...for my design to be incompatible with the tip (my scheduler is top-down). I still plan to submit my work, but it needs to be changed it first, and that takes time. Finally, what I am trying to say - if you are interested in what I have been doing, or you know a better solution for the problem within existing infrastructure, I would be very interested in talking about it. Thanks. Sergei Larin -- Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum. > -----Original Message----- > From: llvm-commits-bounces at cs.uiuc.edu [mailto:llvm-commits- > bounces at cs.uiuc.edu] On Behalf Of Hal Finkel > Sent: Wednesday, December 21, 2011 7:50 AM > To: Jakob Stoklund Olesen > Cc: llvm-commits at cs.uiuc.edu > Subject: Re: [llvm-commits] [PATCH] Allow SelectionDAGBuilder to > reorder loads past stores > > It turns out that a significant cause of the performance regressions > caused by this patch are related to this issue: with the patch applied > the scheduler is now free to schedule many more things, especially > stores, after calls (especially intrinsics that are expanded to lib > calls). This tendency is bad because of the spilling necessary to cross > the call boundary. I am working on a proposed solution, and I'll post > an > updated patch soon. > > Thanks again, > Hal > > On Tue, 2011-12-20 at 12:52 -0600, Hal Finkel wrote: > > On Tue, 2011-12-20 at 10:44 -0800, Jakob Stoklund Olesen wrote: > > > On Dec 20, 2011, at 9:22 AM, Hal Finkel wrote: > > > > > > > when I later look at the register map, only XMM0 and XMM1 are > ever > > > > assigned to vregs, everything else is spilled. This is wrong. Do > you > > > > have any ideas on what could be going wrong or other things I > should > > > > examine? Could the register allocator not be accounting correctly > for > > > > callee-saved registers when computing live-interval interference > > > > information? > > > > > > There are no callee-saved xmm registers. > > > > Thanks! I was mixing up the Win64 calling convention with the regular > > one. That explains things, so, I suppose the right thing to do is to > > make sure all stores are flushed before any call (which I think it > > already does), and any intrinsic that will be expanded (which it will > > not currently do). > > > > -Hal > > > > > > > > /jakob > > > > > > > -- > Hal Finkel > Postdoctoral Appointee > Leadership Computing Facility > Argonne National Laboratory > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From rafael.espindola at gmail.com Wed Dec 21 11:00:36 2011 From: rafael.espindola at gmail.com (Rafael Espindola) Date: Wed, 21 Dec 2011 17:00:36 -0000 Subject: [llvm-commits] [llvm] r147059 - in /llvm/trunk: include/llvm/MC/MCELFObjectWriter.h lib/MC/ELFObjectWriter.cpp lib/MC/MCELFObjectTargetWriter.cpp lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp lib/Target/MBlaze/MCTargetDesc/MBlazeAsmBackend.cpp lib/Target/Mips/MCTargetDesc/MipsAsmBackend.cpp lib/Target/PowerPC/MCTargetDesc/PPCAsmBackend.cpp lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp Message-ID: <20111221170036.B59BC2A6C12C@llvm.org> Author: rafael Date: Wed Dec 21 11:00:36 2011 New Revision: 147059 URL: http://llvm.org/viewvc/llvm-project?rev=147059&view=rev Log: Reduce the exposure of Triple::OSType in the ELF object writer. This will avoid including ADT/Triple.h in many places when the target specific bits are moved. Modified: llvm/trunk/include/llvm/MC/MCELFObjectWriter.h llvm/trunk/lib/MC/ELFObjectWriter.cpp llvm/trunk/lib/MC/MCELFObjectTargetWriter.cpp llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp llvm/trunk/lib/Target/MBlaze/MCTargetDesc/MBlazeAsmBackend.cpp llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsAsmBackend.cpp llvm/trunk/lib/Target/PowerPC/MCTargetDesc/PPCAsmBackend.cpp llvm/trunk/lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp Modified: llvm/trunk/include/llvm/MC/MCELFObjectWriter.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/MC/MCELFObjectWriter.h?rev=147059&r1=147058&r2=147059&view=diff ============================================================================== --- llvm/trunk/include/llvm/MC/MCELFObjectWriter.h (original) +++ llvm/trunk/include/llvm/MC/MCELFObjectWriter.h Wed Dec 21 11:00:36 2011 @@ -12,23 +12,37 @@ #include "llvm/MC/MCObjectWriter.h" #include "llvm/Support/DataTypes.h" +#include "llvm/Support/ELF.h" namespace llvm { class MCELFObjectTargetWriter { - const Triple::OSType OSType; + const uint8_t OSABI; const uint16_t EMachine; const unsigned HasRelocationAddend : 1; const unsigned Is64Bit : 1; + protected: - MCELFObjectTargetWriter(bool Is64Bit_, Triple::OSType OSType_, + + MCELFObjectTargetWriter(bool Is64Bit_, uint8_t OSABI_, uint16_t EMachine_, bool HasRelocationAddend_); public: + static uint8_t getOSABI(Triple::OSType OSType) { + switch (OSType) { + case Triple::FreeBSD: + return ELF::ELFOSABI_FREEBSD; + case Triple::Linux: + return ELF::ELFOSABI_LINUX; + default: + return ELF::ELFOSABI_NONE; + } + } + virtual ~MCELFObjectTargetWriter(); /// @name Accessors /// @{ - Triple::OSType getOSType() { return OSType; } + uint8_t getOSABI() { return OSABI; } uint16_t getEMachine() { return EMachine; } bool hasRelocationAddend() { return HasRelocationAddend; } bool is64Bit() const { return Is64Bit; } Modified: llvm/trunk/lib/MC/ELFObjectWriter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/ELFObjectWriter.cpp?rev=147059&r1=147058&r2=147059&view=diff ============================================================================== --- llvm/trunk/lib/MC/ELFObjectWriter.cpp (original) +++ llvm/trunk/lib/MC/ELFObjectWriter.cpp Wed Dec 21 11:00:36 2011 @@ -93,11 +93,7 @@ Write8(ELF::EV_CURRENT); // e_ident[EI_VERSION] // e_ident[EI_OSABI] - switch (TargetObjectWriter->getOSType()) { - case Triple::FreeBSD: Write8(ELF::ELFOSABI_FREEBSD); break; - case Triple::Linux: Write8(ELF::ELFOSABI_LINUX); break; - default: Write8(ELF::ELFOSABI_NONE); break; - } + Write8(TargetObjectWriter->getOSABI()); Write8(0); // e_ident[EI_ABIVERSION] WriteZeros(ELF::EI_NIDENT - ELF::EI_PAD); Modified: llvm/trunk/lib/MC/MCELFObjectTargetWriter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCELFObjectTargetWriter.cpp?rev=147059&r1=147058&r2=147059&view=diff ============================================================================== --- llvm/trunk/lib/MC/MCELFObjectTargetWriter.cpp (original) +++ llvm/trunk/lib/MC/MCELFObjectTargetWriter.cpp Wed Dec 21 11:00:36 2011 @@ -12,10 +12,10 @@ using namespace llvm; MCELFObjectTargetWriter::MCELFObjectTargetWriter(bool Is64Bit_, - Triple::OSType OSType_, + uint8_t OSABI_, uint16_t EMachine_, bool HasRelocationAddend_) - : OSType(OSType_), EMachine(EMachine_), + : OSABI(OSABI_), EMachine(EMachine_), HasRelocationAddend(HasRelocationAddend_), Is64Bit(Is64Bit_) { } Modified: llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp?rev=147059&r1=147058&r2=147059&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp (original) +++ llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp Wed Dec 21 11:00:36 2011 @@ -31,8 +31,8 @@ namespace { class ARMELFObjectWriter : public MCELFObjectTargetWriter { public: - ARMELFObjectWriter(Triple::OSType OSType) - : MCELFObjectTargetWriter(/*Is64Bit*/ false, OSType, ELF::EM_ARM, + ARMELFObjectWriter(uint8_t OSABI) + : MCELFObjectTargetWriter(/*Is64Bit*/ false, OSABI, ELF::EM_ARM, /*HasRelocationAddend*/ false) {} }; @@ -447,16 +447,16 @@ // ELF is an ELF of course... class ELFARMAsmBackend : public ARMAsmBackend { public: - Triple::OSType OSType; + uint8_t OSABI; ELFARMAsmBackend(const Target &T, const StringRef TT, - Triple::OSType _OSType) - : ARMAsmBackend(T, TT), OSType(_OSType) { } + uint8_t _OSABI) + : ARMAsmBackend(T, TT), OSABI(_OSABI) { } void ApplyFixup(const MCFixup &Fixup, char *Data, unsigned DataSize, uint64_t Value) const; MCObjectWriter *createObjectWriter(raw_ostream &OS) const { - return createELFObjectWriter(new ARMELFObjectWriter(OSType), OS, + return createELFObjectWriter(new ARMELFObjectWriter(OSABI), OS, /*IsLittleEndian*/ true); } }; @@ -580,5 +580,6 @@ if (TheTriple.isOSWindows()) assert(0 && "Windows not supported on ARM"); - return new ELFARMAsmBackend(T, TT, Triple(TT).getOS()); + uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(Triple(TT).getOS()); + return new ELFARMAsmBackend(T, TT, OSABI); } Modified: llvm/trunk/lib/Target/MBlaze/MCTargetDesc/MBlazeAsmBackend.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MBlaze/MCTargetDesc/MBlazeAsmBackend.cpp?rev=147059&r1=147058&r2=147059&view=diff ============================================================================== --- llvm/trunk/lib/Target/MBlaze/MCTargetDesc/MBlazeAsmBackend.cpp (original) +++ llvm/trunk/lib/Target/MBlaze/MCTargetDesc/MBlazeAsmBackend.cpp Wed Dec 21 11:00:36 2011 @@ -41,8 +41,8 @@ namespace { class MBlazeELFObjectWriter : public MCELFObjectTargetWriter { public: - MBlazeELFObjectWriter(Triple::OSType OSType) - : MCELFObjectTargetWriter(/*is64Bit*/ false, OSType, ELF::EM_MBLAZE, + MBlazeELFObjectWriter(uint8_t OSABI) + : MCELFObjectTargetWriter(/*is64Bit*/ false, OSABI, ELF::EM_MBLAZE, /*HasRelocationAddend*/ true) {} }; @@ -123,15 +123,15 @@ namespace { class ELFMBlazeAsmBackend : public MBlazeAsmBackend { public: - Triple::OSType OSType; - ELFMBlazeAsmBackend(const Target &T, Triple::OSType _OSType) - : MBlazeAsmBackend(T), OSType(_OSType) { } + uint8_t OSABI; + ELFMBlazeAsmBackend(const Target &T, uint8_t _OSABI) + : MBlazeAsmBackend(T), OSABI(_OSABI) { } void ApplyFixup(const MCFixup &Fixup, char *Data, unsigned DataSize, uint64_t Value) const; MCObjectWriter *createObjectWriter(raw_ostream &OS) const { - return createELFObjectWriter(new MBlazeELFObjectWriter(OSType), OS, + return createELFObjectWriter(new MBlazeELFObjectWriter(OSABI), OS, /*IsLittleEndian*/ false); } }; @@ -172,5 +172,6 @@ if (TheTriple.isOSWindows()) assert(0 && "Windows not supported on MBlaze"); - return new ELFMBlazeAsmBackend(T, TheTriple.getOS()); + uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(TheTriple.getOS()); + return new ELFMBlazeAsmBackend(T, OSABI); } Modified: llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsAsmBackend.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsAsmBackend.cpp?rev=147059&r1=147058&r2=147059&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsAsmBackend.cpp (original) +++ llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsAsmBackend.cpp Wed Dec 21 11:00:36 2011 @@ -72,9 +72,9 @@ class MipsELFObjectWriter : public MCELFObjectTargetWriter { public: - MipsELFObjectWriter(bool is64Bit, Triple::OSType OSType, uint16_t EMachine, + MipsELFObjectWriter(bool is64Bit, uint8_t OSABI, uint16_t EMachine, bool HasRelocationAddend) - : MCELFObjectTargetWriter(is64Bit, OSType, EMachine, + : MCELFObjectTargetWriter(is64Bit, OSABI, EMachine, HasRelocationAddend) {} }; @@ -197,10 +197,10 @@ class MipsEB_AsmBackend : public MipsAsmBackend { public: - Triple::OSType OSType; + uint8_t OSABI; - MipsEB_AsmBackend(const Target &T, Triple::OSType _OSType) - : MipsAsmBackend(T), OSType(_OSType) {} + MipsEB_AsmBackend(const Target &T, uint8_t _OSABI) + : MipsAsmBackend(T), OSABI(_OSABI) {} MCObjectWriter *createObjectWriter(raw_ostream &OS) const { return createELFObjectWriter(createELFObjectTargetWriter(), @@ -208,16 +208,16 @@ } MCELFObjectTargetWriter *createELFObjectTargetWriter() const { - return new MipsELFObjectWriter(false, OSType, ELF::EM_MIPS, false); + return new MipsELFObjectWriter(false, OSABI, ELF::EM_MIPS, false); } }; class MipsEL_AsmBackend : public MipsAsmBackend { public: - Triple::OSType OSType; + uint8_t OSABI; - MipsEL_AsmBackend(const Target &T, Triple::OSType _OSType) - : MipsAsmBackend(T), OSType(_OSType) {} + MipsEL_AsmBackend(const Target &T, uint8_t _OSABI) + : MipsAsmBackend(T), OSABI(_OSABI) {} MCObjectWriter *createObjectWriter(raw_ostream &OS) const { return createELFObjectWriter(createELFObjectTargetWriter(), @@ -225,7 +225,7 @@ } MCELFObjectTargetWriter *createELFObjectTargetWriter() const { - return new MipsELFObjectWriter(false, OSType, ELF::EM_MIPS, false); + return new MipsELFObjectWriter(false, OSABI, ELF::EM_MIPS, false); } }; } // namespace @@ -235,5 +235,6 @@ // just return little endian for now // - return new MipsEL_AsmBackend(T, Triple(TT).getOS()); + uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(Triple(TT).getOS()); + return new MipsEL_AsmBackend(T, OSABI); } Modified: llvm/trunk/lib/Target/PowerPC/MCTargetDesc/PPCAsmBackend.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/MCTargetDesc/PPCAsmBackend.cpp?rev=147059&r1=147058&r2=147059&view=diff ============================================================================== --- llvm/trunk/lib/Target/PowerPC/MCTargetDesc/PPCAsmBackend.cpp (original) +++ llvm/trunk/lib/Target/PowerPC/MCTargetDesc/PPCAsmBackend.cpp Wed Dec 21 11:00:36 2011 @@ -59,9 +59,9 @@ class PPCELFObjectWriter : public MCELFObjectTargetWriter { public: - PPCELFObjectWriter(bool Is64Bit, Triple::OSType OSType, uint16_t EMachine, + PPCELFObjectWriter(bool Is64Bit, uint8_t OSABI, uint16_t EMachine, bool HasRelocationAddend, bool isLittleEndian) - : MCELFObjectTargetWriter(Is64Bit, OSType, EMachine, HasRelocationAddend) {} + : MCELFObjectTargetWriter(Is64Bit, OSABI, EMachine, HasRelocationAddend) {} }; class PPCAsmBackend : public MCAsmBackend { @@ -154,10 +154,10 @@ }; class ELFPPCAsmBackend : public PPCAsmBackend { - Triple::OSType OSType; + uint8_t OSABI; public: - ELFPPCAsmBackend(const Target &T, Triple::OSType OSType) : - PPCAsmBackend(T), OSType(OSType) { } + ELFPPCAsmBackend(const Target &T, uint8_t OSABI) : + PPCAsmBackend(T), OSABI(OSABI) { } void ApplyFixup(const MCFixup &Fixup, char *Data, unsigned DataSize, uint64_t Value) const { @@ -177,7 +177,7 @@ bool is64 = getPointerSize() == 8; return createELFObjectWriter(new PPCELFObjectWriter( /*Is64Bit=*/is64, - OSType, + OSABI, is64 ? ELF::EM_PPC64 : ELF::EM_PPC, /*addend*/ true, /*isLittleEndian*/ false), OS, /*IsLittleEndian=*/false); @@ -197,5 +197,6 @@ if (Triple(TT).isOSDarwin()) return new DarwinPPCAsmBackend(T); - return new ELFPPCAsmBackend(T, Triple(TT).getOS()); + uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(Triple(TT).getOS()); + return new ELFPPCAsmBackend(T, OSABI); } Modified: llvm/trunk/lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp?rev=147059&r1=147058&r2=147059&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp (original) +++ llvm/trunk/lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp Wed Dec 21 11:00:36 2011 @@ -58,9 +58,9 @@ class X86ELFObjectWriter : public MCELFObjectTargetWriter { public: - X86ELFObjectWriter(bool is64Bit, Triple::OSType OSType, uint16_t EMachine, - bool HasRelocationAddend) - : MCELFObjectTargetWriter(is64Bit, OSType, EMachine, HasRelocationAddend) {} + X86ELFObjectWriter(bool is64Bit, uint8_t OSABI, uint16_t EMachine, + bool HasRelocationAddend, bool foobar) + : MCELFObjectTargetWriter(is64Bit, OSABI, EMachine, HasRelocationAddend) {} }; class X86AsmBackend : public MCAsmBackend { @@ -325,9 +325,9 @@ namespace { class ELFX86AsmBackend : public X86AsmBackend { public: - Triple::OSType OSType; - ELFX86AsmBackend(const Target &T, Triple::OSType _OSType) - : X86AsmBackend(T), OSType(_OSType) { + uint8_t OSABI; + ELFX86AsmBackend(const Target &T, uint8_t _OSABI) + : X86AsmBackend(T), OSABI(_OSABI) { HasReliableSymbolDifference = true; } @@ -339,8 +339,8 @@ class ELFX86_32AsmBackend : public ELFX86AsmBackend { public: - ELFX86_32AsmBackend(const Target &T, Triple::OSType OSType) - : ELFX86AsmBackend(T, OSType) {} + ELFX86_32AsmBackend(const Target &T, uint8_t OSABI) + : ELFX86AsmBackend(T, OSABI) {} MCObjectWriter *createObjectWriter(raw_ostream &OS) const { return createELFObjectWriter(createELFObjectTargetWriter(), @@ -348,14 +348,14 @@ } MCELFObjectTargetWriter *createELFObjectTargetWriter() const { - return new X86ELFObjectWriter(false, OSType, ELF::EM_386, false); + return new X86ELFObjectWriter(false, OSABI, ELF::EM_386, false, false); } }; class ELFX86_64AsmBackend : public ELFX86AsmBackend { public: - ELFX86_64AsmBackend(const Target &T, Triple::OSType OSType) - : ELFX86AsmBackend(T, OSType) {} + ELFX86_64AsmBackend(const Target &T, uint8_t OSABI) + : ELFX86AsmBackend(T, OSABI) {} MCObjectWriter *createObjectWriter(raw_ostream &OS) const { return createELFObjectWriter(createELFObjectTargetWriter(), @@ -363,7 +363,7 @@ } MCELFObjectTargetWriter *createELFObjectTargetWriter() const { - return new X86ELFObjectWriter(true, OSType, ELF::EM_X86_64, true); + return new X86ELFObjectWriter(true, OSABI, ELF::EM_X86_64, true, false); } }; @@ -457,7 +457,8 @@ if (TheTriple.isOSWindows()) return new WindowsX86AsmBackend(T, false); - return new ELFX86_32AsmBackend(T, TheTriple.getOS()); + uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(TheTriple.getOS()); + return new ELFX86_32AsmBackend(T, OSABI); } MCAsmBackend *llvm::createX86_64AsmBackend(const Target &T, StringRef TT) { @@ -469,5 +470,6 @@ if (TheTriple.isOSWindows()) return new WindowsX86AsmBackend(T, true); - return new ELFX86_64AsmBackend(T, TheTriple.getOS()); + uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(TheTriple.getOS()); + return new ELFX86_64AsmBackend(T, OSABI); } From rafael.espindola at gmail.com Wed Dec 21 11:30:17 2011 From: rafael.espindola at gmail.com (Rafael Espindola) Date: Wed, 21 Dec 2011 17:30:17 -0000 Subject: [llvm-commits] [llvm] r147060 - in /llvm/trunk: include/llvm/MC/MCELFObjectWriter.h lib/MC/ELFObjectWriter.cpp lib/MC/ELFObjectWriter.h lib/MC/MCELFObjectTargetWriter.cpp lib/Target/X86/MCTargetDesc/CMakeLists.txt lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp lib/Target/X86/MCTargetDesc/X86ELFObjectWriter.cpp lib/Target/X86/MCTargetDesc/X86MCTargetDesc.h Message-ID: <20111221173017.8EE1D2A6C12C@llvm.org> Author: rafael Date: Wed Dec 21 11:30:17 2011 New Revision: 147060 URL: http://llvm.org/viewvc/llvm-project?rev=147060&view=rev Log: Move the X86 specific bits of the ELF writer to the Target/X86 directory. Other targets will follow shortly. Added: llvm/trunk/lib/Target/X86/MCTargetDesc/X86ELFObjectWriter.cpp Modified: llvm/trunk/include/llvm/MC/MCELFObjectWriter.h llvm/trunk/lib/MC/ELFObjectWriter.cpp llvm/trunk/lib/MC/ELFObjectWriter.h llvm/trunk/lib/MC/MCELFObjectTargetWriter.cpp llvm/trunk/lib/Target/X86/MCTargetDesc/CMakeLists.txt llvm/trunk/lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.h Modified: llvm/trunk/include/llvm/MC/MCELFObjectWriter.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/MC/MCELFObjectWriter.h?rev=147060&r1=147059&r2=147060&view=diff ============================================================================== --- llvm/trunk/include/llvm/MC/MCELFObjectWriter.h (original) +++ llvm/trunk/include/llvm/MC/MCELFObjectWriter.h Wed Dec 21 11:30:17 2011 @@ -40,6 +40,10 @@ virtual ~MCELFObjectTargetWriter(); + virtual unsigned GetRelocType(const MCValue &Target, const MCFixup &Fixup, + bool IsPCRel, bool IsRelocWithSymbol, + int64_t Addend) const; // FIXME: add = 0 + /// @name Accessors /// @{ uint8_t getOSABI() { return OSABI; } Modified: llvm/trunk/lib/MC/ELFObjectWriter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/ELFObjectWriter.cpp?rev=147060&r1=147059&r2=147060&view=diff ============================================================================== --- llvm/trunk/lib/MC/ELFObjectWriter.cpp (original) +++ llvm/trunk/lib/MC/ELFObjectWriter.cpp Wed Dec 21 11:30:17 2011 @@ -29,7 +29,6 @@ #include "llvm/ADT/StringSwitch.h" #include "../Target/Mips/MCTargetDesc/MipsFixupKinds.h" -#include "../Target/X86/MCTargetDesc/X86FixupKinds.h" #include "../Target/ARM/MCTargetDesc/ARMFixupKinds.h" #include "../Target/PowerPC/MCTargetDesc/PPCFixupKinds.h" @@ -1261,7 +1260,7 @@ switch (MOTW->getEMachine()) { case ELF::EM_386: case ELF::EM_X86_64: - return new X86ELFObjectWriter(MOTW, OS, IsLittleEndian); break; + return new ELFObjectWriter(MOTW, OS, IsLittleEndian); break; case ELF::EM_ARM: return new ARMELFObjectWriter(MOTW, OS, IsLittleEndian); break; case ELF::EM_MBLAZE: @@ -1275,6 +1274,15 @@ } } +unsigned ELFObjectWriter::GetRelocType(const MCValue &Target, + const MCFixup &Fixup, + bool IsPCRel, + bool IsRelocWithSymbol, + int64_t Addend) const { + return TargetObjectWriter->GetRelocType(Target, Fixup, IsPCRel, + IsRelocWithSymbol, Addend); +} + /// START OF SUBCLASSES for ELFObjectWriter //===- ARMELFObjectWriter -------------------------------------------===// @@ -1628,195 +1636,6 @@ return Type; } -//===- X86ELFObjectWriter -------------------------------------------===// - - -X86ELFObjectWriter::X86ELFObjectWriter(MCELFObjectTargetWriter *MOTW, - raw_ostream &_OS, - bool IsLittleEndian) - : ELFObjectWriter(MOTW, _OS, IsLittleEndian) -{} - -X86ELFObjectWriter::~X86ELFObjectWriter() -{} - -unsigned X86ELFObjectWriter::GetRelocType(const MCValue &Target, - const MCFixup &Fixup, - bool IsPCRel, - bool IsRelocWithSymbol, - int64_t Addend) const { - // determine the type of the relocation - - MCSymbolRefExpr::VariantKind Modifier = Target.isAbsolute() ? - MCSymbolRefExpr::VK_None : Target.getSymA()->getKind(); - unsigned Type; - if (is64Bit()) { - if (IsPCRel) { - switch ((unsigned)Fixup.getKind()) { - default: llvm_unreachable("invalid fixup kind!"); - - case FK_Data_8: Type = ELF::R_X86_64_PC64; break; - case FK_Data_4: Type = ELF::R_X86_64_PC32; break; - case FK_Data_2: Type = ELF::R_X86_64_PC16; break; - - case FK_PCRel_8: - assert(Modifier == MCSymbolRefExpr::VK_None); - Type = ELF::R_X86_64_PC64; - break; - case X86::reloc_signed_4byte: - case X86::reloc_riprel_4byte_movq_load: - case X86::reloc_riprel_4byte: - case FK_PCRel_4: - switch (Modifier) { - default: - llvm_unreachable("Unimplemented"); - case MCSymbolRefExpr::VK_None: - Type = ELF::R_X86_64_PC32; - break; - case MCSymbolRefExpr::VK_PLT: - Type = ELF::R_X86_64_PLT32; - break; - case MCSymbolRefExpr::VK_GOTPCREL: - Type = ELF::R_X86_64_GOTPCREL; - break; - case MCSymbolRefExpr::VK_GOTTPOFF: - Type = ELF::R_X86_64_GOTTPOFF; - break; - case MCSymbolRefExpr::VK_TLSGD: - Type = ELF::R_X86_64_TLSGD; - break; - case MCSymbolRefExpr::VK_TLSLD: - Type = ELF::R_X86_64_TLSLD; - break; - } - break; - case FK_PCRel_2: - assert(Modifier == MCSymbolRefExpr::VK_None); - Type = ELF::R_X86_64_PC16; - break; - case FK_PCRel_1: - assert(Modifier == MCSymbolRefExpr::VK_None); - Type = ELF::R_X86_64_PC8; - break; - } - } else { - switch ((unsigned)Fixup.getKind()) { - default: llvm_unreachable("invalid fixup kind!"); - case FK_Data_8: Type = ELF::R_X86_64_64; break; - case X86::reloc_signed_4byte: - switch (Modifier) { - default: - llvm_unreachable("Unimplemented"); - case MCSymbolRefExpr::VK_None: - Type = ELF::R_X86_64_32S; - break; - case MCSymbolRefExpr::VK_GOT: - Type = ELF::R_X86_64_GOT32; - break; - case MCSymbolRefExpr::VK_GOTPCREL: - Type = ELF::R_X86_64_GOTPCREL; - break; - case MCSymbolRefExpr::VK_TPOFF: - Type = ELF::R_X86_64_TPOFF32; - break; - case MCSymbolRefExpr::VK_DTPOFF: - Type = ELF::R_X86_64_DTPOFF32; - break; - } - break; - case FK_Data_4: - Type = ELF::R_X86_64_32; - break; - case FK_Data_2: Type = ELF::R_X86_64_16; break; - case FK_PCRel_1: - case FK_Data_1: Type = ELF::R_X86_64_8; break; - } - } - } else { - if (IsPCRel) { - switch ((unsigned)Fixup.getKind()) { - default: llvm_unreachable("invalid fixup kind!"); - - case X86::reloc_global_offset_table: - Type = ELF::R_386_GOTPC; - break; - - case X86::reloc_signed_4byte: - case FK_PCRel_4: - case FK_Data_4: - switch (Modifier) { - default: - llvm_unreachable("Unimplemented"); - case MCSymbolRefExpr::VK_None: - Type = ELF::R_386_PC32; - break; - case MCSymbolRefExpr::VK_PLT: - Type = ELF::R_386_PLT32; - break; - } - break; - } - } else { - switch ((unsigned)Fixup.getKind()) { - default: llvm_unreachable("invalid fixup kind!"); - - case X86::reloc_global_offset_table: - Type = ELF::R_386_GOTPC; - break; - - // FIXME: Should we avoid selecting reloc_signed_4byte in 32 bit mode - // instead? - case X86::reloc_signed_4byte: - case FK_PCRel_4: - case FK_Data_4: - switch (Modifier) { - default: - llvm_unreachable("Unimplemented"); - case MCSymbolRefExpr::VK_None: - Type = ELF::R_386_32; - break; - case MCSymbolRefExpr::VK_GOT: - Type = ELF::R_386_GOT32; - break; - case MCSymbolRefExpr::VK_GOTOFF: - Type = ELF::R_386_GOTOFF; - break; - case MCSymbolRefExpr::VK_TLSGD: - Type = ELF::R_386_TLS_GD; - break; - case MCSymbolRefExpr::VK_TPOFF: - Type = ELF::R_386_TLS_LE_32; - break; - case MCSymbolRefExpr::VK_INDNTPOFF: - Type = ELF::R_386_TLS_IE; - break; - case MCSymbolRefExpr::VK_NTPOFF: - Type = ELF::R_386_TLS_LE; - break; - case MCSymbolRefExpr::VK_GOTNTPOFF: - Type = ELF::R_386_TLS_GOTIE; - break; - case MCSymbolRefExpr::VK_TLSLDM: - Type = ELF::R_386_TLS_LDM; - break; - case MCSymbolRefExpr::VK_DTPOFF: - Type = ELF::R_386_TLS_LDO_32; - break; - case MCSymbolRefExpr::VK_GOTTPOFF: - Type = ELF::R_386_TLS_IE_32; - break; - } - break; - case FK_Data_2: Type = ELF::R_386_16; break; - case FK_PCRel_1: - case FK_Data_1: Type = ELF::R_386_8; break; - } - } - } - - return Type; -} - //===- MipsELFObjectWriter -------------------------------------------===// MipsELFObjectWriter::MipsELFObjectWriter(MCELFObjectTargetWriter *MOTW, Modified: llvm/trunk/lib/MC/ELFObjectWriter.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/ELFObjectWriter.h?rev=147060&r1=147059&r2=147060&view=diff ============================================================================== --- llvm/trunk/lib/MC/ELFObjectWriter.h (original) +++ llvm/trunk/lib/MC/ELFObjectWriter.h Wed Dec 21 11:30:17 2011 @@ -351,27 +351,11 @@ protected: virtual unsigned GetRelocType(const MCValue &Target, const MCFixup &Fixup, bool IsPCRel, bool IsRelocWithSymbol, - int64_t Addend) const = 0; + int64_t Addend) const; virtual void adjustFixupOffset(const MCFixup &Fixup, uint64_t &RelocOffset) {} }; - //===- X86ELFObjectWriter -------------------------------------------===// - - class X86ELFObjectWriter : public ELFObjectWriter { - public: - X86ELFObjectWriter(MCELFObjectTargetWriter *MOTW, - raw_ostream &_OS, - bool IsLittleEndian); - - virtual ~X86ELFObjectWriter(); - protected: - virtual unsigned GetRelocType(const MCValue &Target, const MCFixup &Fixup, - bool IsPCRel, bool IsRelocWithSymbol, - int64_t Addend) const; - }; - - //===- ARMELFObjectWriter -------------------------------------------===// class ARMELFObjectWriter : public ELFObjectWriter { Modified: llvm/trunk/lib/MC/MCELFObjectTargetWriter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCELFObjectTargetWriter.cpp?rev=147060&r1=147059&r2=147060&view=diff ============================================================================== --- llvm/trunk/lib/MC/MCELFObjectTargetWriter.cpp (original) +++ llvm/trunk/lib/MC/MCELFObjectTargetWriter.cpp Wed Dec 21 11:30:17 2011 @@ -19,5 +19,13 @@ HasRelocationAddend(HasRelocationAddend_), Is64Bit(Is64Bit_) { } +unsigned MCELFObjectTargetWriter::GetRelocType(const MCValue &Target, + const MCFixup &Fixup, + bool IsPCRel, + bool IsRelocWithSymbol, + int64_t Addend) const { + return 0; +} + MCELFObjectTargetWriter::~MCELFObjectTargetWriter() { } Modified: llvm/trunk/lib/Target/X86/MCTargetDesc/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/MCTargetDesc/CMakeLists.txt?rev=147060&r1=147059&r2=147060&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/MCTargetDesc/CMakeLists.txt (original) +++ llvm/trunk/lib/Target/X86/MCTargetDesc/CMakeLists.txt Wed Dec 21 11:30:17 2011 @@ -2,8 +2,9 @@ X86AsmBackend.cpp X86MCTargetDesc.cpp X86MCAsmInfo.cpp - X86MCCodeEmitter.cpp + X86MCCodeEmitter.cpp X86MachObjectWriter.cpp + X86ELFObjectWriter.cpp ) add_dependencies(LLVMX86Desc X86CommonTableGen) Modified: llvm/trunk/lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp?rev=147060&r1=147059&r2=147060&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp (original) +++ llvm/trunk/lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp Wed Dec 21 11:30:17 2011 @@ -343,12 +343,7 @@ : ELFX86AsmBackend(T, OSABI) {} MCObjectWriter *createObjectWriter(raw_ostream &OS) const { - return createELFObjectWriter(createELFObjectTargetWriter(), - OS, /*IsLittleEndian*/ true); - } - - MCELFObjectTargetWriter *createELFObjectTargetWriter() const { - return new X86ELFObjectWriter(false, OSABI, ELF::EM_386, false, false); + return createX86ELFObjectWriter(OS, /*Is64Bit*/ false, OSABI); } }; @@ -358,12 +353,7 @@ : ELFX86AsmBackend(T, OSABI) {} MCObjectWriter *createObjectWriter(raw_ostream &OS) const { - return createELFObjectWriter(createELFObjectTargetWriter(), - OS, /*IsLittleEndian*/ true); - } - - MCELFObjectTargetWriter *createELFObjectTargetWriter() const { - return new X86ELFObjectWriter(true, OSABI, ELF::EM_X86_64, true, false); + return createX86ELFObjectWriter(OS, /*Is64Bit*/ true, OSABI); } }; Added: llvm/trunk/lib/Target/X86/MCTargetDesc/X86ELFObjectWriter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/MCTargetDesc/X86ELFObjectWriter.cpp?rev=147060&view=auto ============================================================================== --- llvm/trunk/lib/Target/X86/MCTargetDesc/X86ELFObjectWriter.cpp (added) +++ llvm/trunk/lib/Target/X86/MCTargetDesc/X86ELFObjectWriter.cpp Wed Dec 21 11:30:17 2011 @@ -0,0 +1,224 @@ +//===-- X86ELFObjectWriter.cpp - X86 ELF Writer ---------------------------===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// + +#include "MCTargetDesc/X86FixupKinds.h" +#include "MCTargetDesc/X86MCTargetDesc.h" +#include "llvm/MC/MCELFObjectWriter.h" +#include "llvm/MC/MCExpr.h" +#include "llvm/MC/MCValue.h" +#include "llvm/Support/ELF.h" +#include "llvm/Support/ErrorHandling.h" + +using namespace llvm; + +namespace { + class X86ELFObjectWriter : public MCELFObjectTargetWriter { + public: + X86ELFObjectWriter(bool is64Bit, uint8_t OSABI); + + virtual ~X86ELFObjectWriter(); + protected: + virtual unsigned GetRelocType(const MCValue &Target, const MCFixup &Fixup, + bool IsPCRel, bool IsRelocWithSymbol, + int64_t Addend) const; + }; +} + +X86ELFObjectWriter::X86ELFObjectWriter(bool Is64Bit, uint8_t OSABI) + : MCELFObjectTargetWriter(Is64Bit, OSABI, + Is64Bit ? ELF::EM_X86_64 : ELF::EM_386, + /*HasRelocationAddend*/ Is64Bit) {} + +X86ELFObjectWriter::~X86ELFObjectWriter() +{} + +unsigned X86ELFObjectWriter::GetRelocType(const MCValue &Target, + const MCFixup &Fixup, + bool IsPCRel, + bool IsRelocWithSymbol, + int64_t Addend) const { + // determine the type of the relocation + + MCSymbolRefExpr::VariantKind Modifier = Target.isAbsolute() ? + MCSymbolRefExpr::VK_None : Target.getSymA()->getKind(); + unsigned Type; + if (is64Bit()) { + if (IsPCRel) { + switch ((unsigned)Fixup.getKind()) { + default: llvm_unreachable("invalid fixup kind!"); + + case FK_Data_8: Type = ELF::R_X86_64_PC64; break; + case FK_Data_4: Type = ELF::R_X86_64_PC32; break; + case FK_Data_2: Type = ELF::R_X86_64_PC16; break; + + case FK_PCRel_8: + assert(Modifier == MCSymbolRefExpr::VK_None); + Type = ELF::R_X86_64_PC64; + break; + case X86::reloc_signed_4byte: + case X86::reloc_riprel_4byte_movq_load: + case X86::reloc_riprel_4byte: + case FK_PCRel_4: + switch (Modifier) { + default: + llvm_unreachable("Unimplemented"); + case MCSymbolRefExpr::VK_None: + Type = ELF::R_X86_64_PC32; + break; + case MCSymbolRefExpr::VK_PLT: + Type = ELF::R_X86_64_PLT32; + break; + case MCSymbolRefExpr::VK_GOTPCREL: + Type = ELF::R_X86_64_GOTPCREL; + break; + case MCSymbolRefExpr::VK_GOTTPOFF: + Type = ELF::R_X86_64_GOTTPOFF; + break; + case MCSymbolRefExpr::VK_TLSGD: + Type = ELF::R_X86_64_TLSGD; + break; + case MCSymbolRefExpr::VK_TLSLD: + Type = ELF::R_X86_64_TLSLD; + break; + } + break; + case FK_PCRel_2: + assert(Modifier == MCSymbolRefExpr::VK_None); + Type = ELF::R_X86_64_PC16; + break; + case FK_PCRel_1: + assert(Modifier == MCSymbolRefExpr::VK_None); + Type = ELF::R_X86_64_PC8; + break; + } + } else { + switch ((unsigned)Fixup.getKind()) { + default: llvm_unreachable("invalid fixup kind!"); + case FK_Data_8: Type = ELF::R_X86_64_64; break; + case X86::reloc_signed_4byte: + switch (Modifier) { + default: + llvm_unreachable("Unimplemented"); + case MCSymbolRefExpr::VK_None: + Type = ELF::R_X86_64_32S; + break; + case MCSymbolRefExpr::VK_GOT: + Type = ELF::R_X86_64_GOT32; + break; + case MCSymbolRefExpr::VK_GOTPCREL: + Type = ELF::R_X86_64_GOTPCREL; + break; + case MCSymbolRefExpr::VK_TPOFF: + Type = ELF::R_X86_64_TPOFF32; + break; + case MCSymbolRefExpr::VK_DTPOFF: + Type = ELF::R_X86_64_DTPOFF32; + break; + } + break; + case FK_Data_4: + Type = ELF::R_X86_64_32; + break; + case FK_Data_2: Type = ELF::R_X86_64_16; break; + case FK_PCRel_1: + case FK_Data_1: Type = ELF::R_X86_64_8; break; + } + } + } else { + if (IsPCRel) { + switch ((unsigned)Fixup.getKind()) { + default: llvm_unreachable("invalid fixup kind!"); + + case X86::reloc_global_offset_table: + Type = ELF::R_386_GOTPC; + break; + + case X86::reloc_signed_4byte: + case FK_PCRel_4: + case FK_Data_4: + switch (Modifier) { + default: + llvm_unreachable("Unimplemented"); + case MCSymbolRefExpr::VK_None: + Type = ELF::R_386_PC32; + break; + case MCSymbolRefExpr::VK_PLT: + Type = ELF::R_386_PLT32; + break; + } + break; + } + } else { + switch ((unsigned)Fixup.getKind()) { + default: llvm_unreachable("invalid fixup kind!"); + + case X86::reloc_global_offset_table: + Type = ELF::R_386_GOTPC; + break; + + // FIXME: Should we avoid selecting reloc_signed_4byte in 32 bit mode + // instead? + case X86::reloc_signed_4byte: + case FK_PCRel_4: + case FK_Data_4: + switch (Modifier) { + default: + llvm_unreachable("Unimplemented"); + case MCSymbolRefExpr::VK_None: + Type = ELF::R_386_32; + break; + case MCSymbolRefExpr::VK_GOT: + Type = ELF::R_386_GOT32; + break; + case MCSymbolRefExpr::VK_GOTOFF: + Type = ELF::R_386_GOTOFF; + break; + case MCSymbolRefExpr::VK_TLSGD: + Type = ELF::R_386_TLS_GD; + break; + case MCSymbolRefExpr::VK_TPOFF: + Type = ELF::R_386_TLS_LE_32; + break; + case MCSymbolRefExpr::VK_INDNTPOFF: + Type = ELF::R_386_TLS_IE; + break; + case MCSymbolRefExpr::VK_NTPOFF: + Type = ELF::R_386_TLS_LE; + break; + case MCSymbolRefExpr::VK_GOTNTPOFF: + Type = ELF::R_386_TLS_GOTIE; + break; + case MCSymbolRefExpr::VK_TLSLDM: + Type = ELF::R_386_TLS_LDM; + break; + case MCSymbolRefExpr::VK_DTPOFF: + Type = ELF::R_386_TLS_LDO_32; + break; + case MCSymbolRefExpr::VK_GOTTPOFF: + Type = ELF::R_386_TLS_IE_32; + break; + } + break; + case FK_Data_2: Type = ELF::R_386_16; break; + case FK_PCRel_1: + case FK_Data_1: Type = ELF::R_386_8; break; + } + } + } + + return Type; +} + +MCObjectWriter *llvm::createX86ELFObjectWriter(raw_ostream &OS, + bool Is64Bit, + uint8_t OSABI) { + MCELFObjectTargetWriter *MOTW = + new X86ELFObjectWriter(Is64Bit, OSABI); + return createELFObjectWriter(MOTW, OS, /*IsLittleEndian=*/true); +} Modified: llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.h?rev=147060&r1=147059&r2=147060&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.h (original) +++ llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.h Wed Dec 21 11:30:17 2011 @@ -88,6 +88,10 @@ uint32_t CPUType, uint32_t CPUSubtype); +/// createX86ELFObjectWriter - Construct an X86 ELF object writer. +MCObjectWriter *createX86ELFObjectWriter(raw_ostream &OS, + bool Is64Bit, + uint8_t OSABI); } // End llvm namespace From stoklund at 2pi.dk Wed Dec 21 12:04:35 2011 From: stoklund at 2pi.dk (Jakob Stoklund Olesen) Date: Wed, 21 Dec 2011 10:04:35 -0800 Subject: [llvm-commits] [llvm] r147037 - /llvm/trunk/lib/Analysis/InlineCost.cpp In-Reply-To: <20111221060630.8F5FD2A6C12C@llvm.org> References: <20111221060630.8F5FD2A6C12C@llvm.org> Message-ID: On Dec 20, 2011, at 10:06 PM, Nick Lewycky wrote: > Author: nicholas > Date: Wed Dec 21 00:06:30 2011 > New Revision: 147037 > > URL: http://llvm.org/viewvc/llvm-project?rev=147037&view=rev > Log: > A call to a function marked 'noinline' is not an inline candidate. The sole > call site of an intrinsic is also not an inline candidate. While here, make it > more obvious that this code ignores all intrinsics. Noticed by inspection! > > Modified: > llvm/trunk/lib/Analysis/InlineCost.cpp > > Modified: llvm/trunk/lib/Analysis/InlineCost.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/InlineCost.cpp?rev=147037&r1=147036&r2=147037&view=diff > ============================================================================== > --- llvm/trunk/lib/Analysis/InlineCost.cpp (original) > +++ llvm/trunk/lib/Analysis/InlineCost.cpp Wed Dec 21 00:06:30 2011 > @@ -63,8 +63,8 @@ > > // Special handling for calls. > if (isa(II) || isa(II)) { > - if (isa(II)) > - continue; // Debug intrinsics don't count as size. > + if (isa(II)) > + continue; // Intrinsics have no argument setup and can't be inlined. This change doesn't make sense. You are skipping a lot more loop below this continue, effectively ignoring all intrinsics. The code did /not/ ignore intrinsics before. /jakob From klimek at google.com Wed Dec 21 12:16:40 2011 From: klimek at google.com (Manuel Klimek) Date: Wed, 21 Dec 2011 18:16:40 -0000 Subject: [llvm-commits] [llvm] r147063 - in /llvm/trunk: include/llvm/Support/JSONParser.h lib/Support/JSONParser.cpp unittests/Support/JSONParserTest.cpp utils/json-bench/JSONBench.cpp Message-ID: <20111221181640.67B2E2A6C12C@llvm.org> Author: klimek Date: Wed Dec 21 12:16:39 2011 New Revision: 147063 URL: http://llvm.org/viewvc/llvm-project?rev=147063&view=rev Log: Changes the JSON parser to use the SourceMgr. Diagnostics are now emitted via the SourceMgr and we use MemoryBuffer for buffer management. Switched the code to make use of the trailing '0' that MemoryBuffer guarantees where it makes sense. Modified: llvm/trunk/include/llvm/Support/JSONParser.h llvm/trunk/lib/Support/JSONParser.cpp llvm/trunk/unittests/Support/JSONParserTest.cpp llvm/trunk/utils/json-bench/JSONBench.cpp Modified: llvm/trunk/include/llvm/Support/JSONParser.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Support/JSONParser.h?rev=147063&r1=147062&r2=147063&view=diff ============================================================================== --- llvm/trunk/include/llvm/Support/JSONParser.h (original) +++ llvm/trunk/include/llvm/Support/JSONParser.h Wed Dec 21 12:16:39 2011 @@ -23,6 +23,7 @@ #include "llvm/ADT/StringRef.h" #include "llvm/Support/Allocator.h" #include "llvm/Support/ErrorHandling.h" +#include "llvm/Support/SourceMgr.h" namespace llvm { @@ -67,7 +68,7 @@ /// /// Parsing is started via parseRoot(). Access to the object returned from /// parseRoot() will parse the input lazily. - JSONParser(StringRef Input); + JSONParser(StringRef Input, SourceMgr *SM); /// \brief Returns the outermost JSON value (either an array or an object). /// @@ -90,9 +91,6 @@ /// iterating over the result of 'parseRoot', 'failed' will return true. bool failed() const; - /// \brief Returns an error message when 'failed' returns true. - std::string getErrorMessage() const; - private: /// \brief These methods manage the implementation details of parsing new JSON /// atoms. @@ -147,13 +145,20 @@ BumpPtrAllocator ValueAllocator; /// \brief The original input to the parser. - const StringRef Input; + MemoryBuffer *InputBuffer; + + /// \brief The source manager used for diagnostics and buffer management. + SourceMgr *SM; /// \brief The current position in the parse stream. StringRef::iterator Position; - /// \brief If non-empty, an error has occurred. - std::string ErrorMessage; + /// \brief The end position for fast EOF checks without introducing + /// unnecessary dereferences. + StringRef::iterator End; + + /// \brief If true, an error has occurred. + bool Failed; template Modified: llvm/trunk/lib/Support/JSONParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Support/JSONParser.cpp?rev=147063&r1=147062&r2=147063&view=diff ============================================================================== --- llvm/trunk/lib/Support/JSONParser.cpp (original) +++ llvm/trunk/lib/Support/JSONParser.cpp Wed Dec 21 12:16:39 2011 @@ -15,14 +15,20 @@ #include "llvm/ADT/Twine.h" #include "llvm/Support/Casting.h" +#include "llvm/Support/MemoryBuffer.h" using namespace llvm; -JSONParser::JSONParser(StringRef Input) - : Input(Input), Position(Input.begin()) {} +JSONParser::JSONParser(StringRef Input, SourceMgr *SM) + : SM(SM), Failed(false) { + InputBuffer = MemoryBuffer::getMemBuffer(Input, "JSON"); + SM->AddNewSourceBuffer(InputBuffer, SMLoc()); + End = InputBuffer->getBuffer().end(); + Position = InputBuffer->getBuffer().begin(); +} JSONValue *JSONParser::parseRoot() { - if (Position != Input.begin()) + if (Position != InputBuffer->getBuffer().begin()) report_fatal_error("Cannot resuse JSONParser."); if (isWhitespace()) nextNonWhitespace(); @@ -40,7 +46,11 @@ } bool JSONParser::validate() { - return skip(*parseRoot()); + JSONValue *Root = parseRoot(); + if (Root == NULL) { + return false; + } + return skip(*Root); } bool JSONParser::skip(const JSONAtom &Atom) { @@ -55,22 +65,23 @@ } // Sets the current error to: -// "Error while parsing JSON: expected , but found ". +// "expected , but found ". void JSONParser::setExpectedError(StringRef Expected, StringRef Found) { - ErrorMessage = ("Error while parsing JSON: expected " + - Expected + ", but found " + Found + ".").str(); + SM->PrintMessage(SMLoc::getFromPointer(Position), SourceMgr::DK_Error, + "expected " + Expected + ", but found " + Found + ".", ArrayRef()); + Failed = true; } // Sets the current error to: -// "Error while parsing JSON: expected , but found ". +// "expected , but found ". void JSONParser::setExpectedError(StringRef Expected, char Found) { - setExpectedError(Expected, StringRef(&Found, 1)); + setExpectedError(Expected, ("'" + StringRef(&Found, 1) + "'").str()); } // If there is no character available, returns true and sets the current error -// to: "Error while parsing JSON: expected , but found EOF.". +// to: "expected , but found EOF.". bool JSONParser::errorIfAtEndOfFile(StringRef Expected) { - if (Position == Input.end()) { + if (Position == End) { setExpectedError(Expected, "EOF"); return true; } @@ -78,12 +89,12 @@ } // Sets the current error if the current character is not C to: -// "Error while parsing JSON: expected 'C', but got ". +// "expected 'C', but got ". bool JSONParser::errorIfNotAt(char C, StringRef Message) { - if (Position == Input.end() || *Position != C) { + if (*Position != C) { std::string Expected = ("'" + StringRef(&C, 1) + "' " + Message).str(); - if (Position == Input.end()) + if (Position == End) setExpectedError(Expected, "EOF"); else setExpectedError(Expected, *Position); @@ -113,7 +124,7 @@ // Parses a JSONString, assuming that the current position is on a quote. JSONString *JSONParser::parseString() { - assert(Position != Input.end()); + assert(Position != End); assert(!isWhitespace()); if (errorIfNotAt('"', "at start of string")) return 0; @@ -136,9 +147,9 @@ // Step over the current quote. ++Position; // Find the next quote. - while (Position != Input.end() && *Position != '"') + while (Position != End && *Position != '"') ++Position; - if (errorIfAtEndOfFile("\" at end of string")) + if (errorIfAtEndOfFile("'\"' at end of string")) return 0; // Repeat until the previous character was not a '\' or was an escaped // backslash. @@ -158,22 +169,18 @@ // Checks if there is a whitespace character at the current position. bool JSONParser::isWhitespace() { - return Position != Input.end() && (*Position == ' ' || *Position == '\t' || - *Position == '\n' || *Position == '\r'); + return *Position == ' ' || *Position == '\t' || + *Position == '\n' || *Position == '\r'; } bool JSONParser::failed() const { - return !ErrorMessage.empty(); -} - -std::string JSONParser::getErrorMessage() const { - return ErrorMessage; + return Failed; } // Parses a JSONValue, assuming that the current position is at the first // character of the value. JSONValue *JSONParser::parseValue() { - assert(Position != Input.end()); + assert(Position != End); assert(!isWhitespace()); switch (*Position) { case '[': @@ -191,7 +198,7 @@ // Parses a JSONKeyValuePair, assuming that the current position is at the first // character of the key, value pair. JSONKeyValuePair *JSONParser::parseKeyValuePair() { - assert(Position != Input.end()); + assert(Position != End); assert(!isWhitespace()); JSONString *Key = parseString(); Modified: llvm/trunk/unittests/Support/JSONParserTest.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/unittests/Support/JSONParserTest.cpp?rev=147063&r1=147062&r2=147063&view=diff ============================================================================== --- llvm/trunk/unittests/Support/JSONParserTest.cpp (original) +++ llvm/trunk/unittests/Support/JSONParserTest.cpp Wed Dec 21 12:16:39 2011 @@ -14,57 +14,28 @@ namespace llvm { -// Returns a buffer that contains the content of the given string without -// the trailing zero, in order to get valgrind to catch out-of-bound reads. -static std::vector CutTrailingZero(StringRef String) { - std::vector InputWithoutZero(String.size()); - memcpy(&InputWithoutZero[0], String.data(), String.size()); - return InputWithoutZero; -} - // Checks that the given input gives a parse error. Makes sure that an error // text is available and the parse fails. -static void ExpectParseError(StringRef Message, - const std::vector &InputWithoutZero) { - StringRef Input = StringRef(&InputWithoutZero[0], InputWithoutZero.size()); - JSONParser Parser(Input); +static void ExpectParseError(StringRef Message, StringRef Input) { + SourceMgr SM; + JSONParser Parser(Input, &SM); EXPECT_FALSE(Parser.validate()) << Message << ": " << Input; EXPECT_TRUE(Parser.failed()) << Message << ": " << Input; - EXPECT_FALSE(Parser.getErrorMessage().empty()) << Message << ": " << Input; -} - -// Overloads the above to allow using const char * as Input. -static void ExpectParseError(StringRef Message, StringRef Input) { - return ExpectParseError(Message, CutTrailingZero(Input)); } // Checks that the given input can be parsed without error. -static void ExpectParseSuccess(StringRef Message, - const std::vector &InputWithoutZero) { - StringRef Input = StringRef(&InputWithoutZero[0], InputWithoutZero.size()); - JSONParser Parser(Input); - EXPECT_TRUE(Parser.validate()) - << Message << ": " << Input << " - " << Parser.getErrorMessage(); -} - -// Overloads the above to allow using const char * as Input. static void ExpectParseSuccess(StringRef Message, StringRef Input) { - return ExpectParseSuccess(Message, CutTrailingZero(Input)); + SourceMgr SM; + JSONParser Parser(Input, &SM); + EXPECT_TRUE(Parser.validate()) << Message << ": " << Input; } TEST(JSONParser, FailsOnEmptyString) { - JSONParser Parser(""); - EXPECT_EQ(NULL, Parser.parseRoot()); + ExpectParseError("Empty JSON text", ""); } - -TEST(JSONParser, DoesNotReadAfterInput) { - JSONParser Parser(llvm::StringRef(NULL, 0)); - EXPECT_EQ(NULL, Parser.parseRoot()); -} - + TEST(JSONParser, FailsIfStartsWithString) { - JSONParser Character("\"x\""); - EXPECT_EQ(NULL, Character.parseRoot()); + ExpectParseError("Top-level string", "\"x\""); } TEST(JSONParser, ParsesEmptyArray) { @@ -177,11 +148,12 @@ // of an array. static void ExpectCanParseString(StringRef String) { std::string StringInArray = (llvm::Twine("[\"") + String + "\"]").str(); - JSONParser Parser(StringInArray); + SourceMgr SM; + JSONParser Parser(StringInArray, &SM); const JSONArray *ParsedArray = dyn_cast(Parser.parseRoot()); StringRef ParsedString = dyn_cast(*ParsedArray->begin())->getRawText(); - EXPECT_EQ(String, ParsedString.str()) << Parser.getErrorMessage(); + EXPECT_EQ(String, ParsedString.str()); } // Checks that parsing the given string inside an array fails. @@ -210,7 +182,8 @@ } TEST(JSONParser, WorksWithIteratorAlgorithms) { - JSONParser Parser("[\"1\", \"2\", \"3\", \"4\", \"5\", \"6\"]"); + SourceMgr SM; + JSONParser Parser("[\"1\", \"2\", \"3\", \"4\", \"5\", \"6\"]", &SM); const JSONArray *Array = dyn_cast(Parser.parseRoot()); EXPECT_EQ(6, std::distance(Array->begin(), Array->end())); } Modified: llvm/trunk/utils/json-bench/JSONBench.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/json-bench/JSONBench.cpp?rev=147063&r1=147062&r2=147063&view=diff ============================================================================== --- llvm/trunk/utils/json-bench/JSONBench.cpp (original) +++ llvm/trunk/utils/json-bench/JSONBench.cpp Wed Dec 21 12:16:39 2011 @@ -41,7 +41,8 @@ llvm::Timer Parsing((Name + ": Parsing").str(), Group); Parsing.startTimer(); - llvm::JSONParser Parser(JSONText); + llvm::SourceMgr SM; + llvm::JSONParser Parser(JSONText, &SM); if (!Parser.validate()) { llvm::errs() << "Parsing error in JSON parser benchmark.\n"; exit(1); From mcrosier at apple.com Wed Dec 21 12:56:22 2011 From: mcrosier at apple.com (Chad Rosier) Date: Wed, 21 Dec 2011 18:56:22 -0000 Subject: [llvm-commits] [llvm] r147064 - in /llvm/trunk: lib/Target/ARM/ARMInstrInfo.td test/CodeGen/ARM/atomic-op.ll Message-ID: <20111221185622.9FA892A6C12C@llvm.org> Author: mcrosier Date: Wed Dec 21 12:56:22 2011 New Revision: 147064 URL: http://llvm.org/viewvc/llvm-project?rev=147064&view=rev Log: Fix a couple of copy-n-paste bugs. Noticed by George Russell! Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td llvm/trunk/test/CodeGen/ARM/atomic-op.ll Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.td?rev=147064&r1=147063&r2=147064&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrInfo.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Wed Dec 21 12:56:22 2011 @@ -4152,10 +4152,10 @@ [(set GPR:$dst, (atomic_load_max_8 GPR:$ptr, GPR:$val))]>; def ATOMIC_LOAD_UMIN_I8 : PseudoInst< (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary, - [(set GPR:$dst, (atomic_load_min_8 GPR:$ptr, GPR:$val))]>; + [(set GPR:$dst, (atomic_load_umin_8 GPR:$ptr, GPR:$val))]>; def ATOMIC_LOAD_UMAX_I8 : PseudoInst< (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary, - [(set GPR:$dst, (atomic_load_max_8 GPR:$ptr, GPR:$val))]>; + [(set GPR:$dst, (atomic_load_umax_8 GPR:$ptr, GPR:$val))]>; def ATOMIC_LOAD_ADD_I16 : PseudoInst< (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary, [(set GPR:$dst, (atomic_load_add_16 GPR:$ptr, GPR:$incr))]>; @@ -4182,10 +4182,10 @@ [(set GPR:$dst, (atomic_load_max_16 GPR:$ptr, GPR:$val))]>; def ATOMIC_LOAD_UMIN_I16 : PseudoInst< (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary, - [(set GPR:$dst, (atomic_load_min_16 GPR:$ptr, GPR:$val))]>; + [(set GPR:$dst, (atomic_load_umin_16 GPR:$ptr, GPR:$val))]>; def ATOMIC_LOAD_UMAX_I16 : PseudoInst< (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary, - [(set GPR:$dst, (atomic_load_max_16 GPR:$ptr, GPR:$val))]>; + [(set GPR:$dst, (atomic_load_umax_16 GPR:$ptr, GPR:$val))]>; def ATOMIC_LOAD_ADD_I32 : PseudoInst< (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary, [(set GPR:$dst, (atomic_load_add_32 GPR:$ptr, GPR:$incr))]>; Modified: llvm/trunk/test/CodeGen/ARM/atomic-op.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/atomic-op.ll?rev=147064&r1=147063&r2=147064&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/ARM/atomic-op.ll (original) +++ llvm/trunk/test/CodeGen/ARM/atomic-op.ll Wed Dec 21 12:56:22 2011 @@ -101,3 +101,61 @@ ret void } + +define void @func2() nounwind { +entry: + %val = alloca i16 + %old = alloca i16 + store i16 31, i16* %val + ; CHECK: ldrex + ; CHECK: cmp + ; CHECK: strex + %0 = atomicrmw umin i16* %val, i16 16 monotonic + store i16 %0, i16* %old + %uneg = sub i16 0, 1 + ; CHECK: ldrex + ; CHECK: cmp + ; CHECK: strex + %1 = atomicrmw umin i16* %val, i16 %uneg monotonic + store i16 %1, i16* %old + ; CHECK: ldrex + ; CHECK: cmp + ; CHECK: strex + %2 = atomicrmw umax i16* %val, i16 1 monotonic + store i16 %2, i16* %old + ; CHECK: ldrex + ; CHECK: cmp + ; CHECK: strex + %3 = atomicrmw umax i16* %val, i16 0 monotonic + store i16 %3, i16* %old + ret void +} + +define void @func3() nounwind { +entry: + %val = alloca i8 + %old = alloca i8 + store i8 31, i8* %val + ; CHECK: ldrex + ; CHECK: cmp + ; CHECK: strex + %0 = atomicrmw umin i8* %val, i8 16 monotonic + store i8 %0, i8* %old + ; CHECK: ldrex + ; CHECK: cmp + ; CHECK: strex + %uneg = sub i8 0, 1 + %1 = atomicrmw umin i8* %val, i8 %uneg monotonic + store i8 %1, i8* %old + ; CHECK: ldrex + ; CHECK: cmp + ; CHECK: strex + %2 = atomicrmw umax i8* %val, i8 1 monotonic + store i8 %2, i8* %old + ; CHECK: ldrex + ; CHECK: cmp + ; CHECK: strex + %3 = atomicrmw umax i8* %val, i8 0 monotonic + store i8 %3, i8* %old + ret void +} From gohman at apple.com Wed Dec 21 13:02:32 2011 From: gohman at apple.com (Dan Gohman) Date: Wed, 21 Dec 2011 11:02:32 -0800 Subject: [llvm-commits] [llvm] r147036 - in /llvm/trunk: lib/Analysis/ValueTracking.cpp lib/Transforms/Utils/SimplifyCFG.cpp test/Transforms/SimplifyCFG/SpeculativeExec.ll In-Reply-To: <20111221055202.885DE2A6C12C@llvm.org> References: <20111221055202.885DE2A6C12C@llvm.org> Message-ID: <05C067F7-5491-4FF6-AA1F-CDCB18D419BB@apple.com> On Dec 20, 2011, at 9:52 PM, Nick Lewycky wrote: > Author: nicholas > Date: Tue Dec 20 23:52:02 2011 > New Revision: 147036 > > URL: http://llvm.org/viewvc/llvm-project?rev=147036&view=rev > Log: > Make some intrinsics safe to speculatively execute. > > Modified: > llvm/trunk/lib/Analysis/ValueTracking.cpp > llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp > llvm/trunk/test/Transforms/SimplifyCFG/SpeculativeExec.ll > > Modified: llvm/trunk/lib/Analysis/ValueTracking.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/ValueTracking.cpp?rev=147036&r1=147035&r2=147036&view=diff > ============================================================================== > --- llvm/trunk/lib/Analysis/ValueTracking.cpp (original) > +++ llvm/trunk/lib/Analysis/ValueTracking.cpp Tue Dec 20 23:52:02 2011 > @@ -1912,11 +1912,31 @@ > return false; > return LI->getPointerOperand()->isDereferenceablePointer(); > } > - case Instruction::Call: > + case Instruction::Call: { > + if (const IntrinsicInst *II = dyn_cast(Inst)) { > + switch (II->getIntrinsicID()) { > + case Intrinsic::bswap: > + case Intrinsic::ctlz: > + case Intrinsic::ctpop: > + case Intrinsic::cttz: > + case Intrinsic::objectsize: > + case Intrinsic::sadd_with_overflow: > + case Intrinsic::smul_with_overflow: > + case Intrinsic::ssub_with_overflow: > + case Intrinsic::uadd_with_overflow: > + case Intrinsic::umul_with_overflow: > + case Intrinsic::usub_with_overflow: > + return true; > + // TODO: some fp intrinsics are marked as having the same error handling > + // as libm. They're safe to speculate when they won't error. > + // TODO: are convert_{from,to}_fp16 safe? > + // TODO: can we list target-specific intrinsics here? Just checking mayHaveSideEffects() should cover almost everything here. > + default: break; > + } > + } > return false; // The called function could have undefined behavior or > - // side-effects. > - // FIXME: We should special-case some intrinsics (bswap, > - // overflow-checking arithmetic, etc.) > + // side-effects, even if marked readnone nounwind. > + } > case Instruction::VAArg: > case Instruction::Alloca: > case Instruction::Invoke: > > Modified: llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp?rev=147036&r1=147035&r2=147036&view=diff > ============================================================================== > --- llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp (original) > +++ llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp Tue Dec 20 23:52:02 2011 > @@ -293,6 +293,7 @@ > Cost = 1; > break; // These are all cheap and non-trapping instructions. > > + case Instruction::Call: cttz, ctlz, etc. are very expensive on many targets. Having SimplifyCFG speculate them here could cause substantial pessimizations. Dan From mcrosier at apple.com Wed Dec 21 13:14:53 2011 From: mcrosier at apple.com (Chad Rosier) Date: Wed, 21 Dec 2011 19:14:53 -0000 Subject: [llvm-commits] [llvm] r147065 - /llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Message-ID: <20111221191453.28D0B2A6C12C@llvm.org> Author: mcrosier Date: Wed Dec 21 13:14:52 2011 New Revision: 147065 URL: http://llvm.org/viewvc/llvm-project?rev=147065&view=rev Log: No case stmt for BUILD_VECTOR in PerformDAGCombine(), so I assume this isn't necessary. Please chime in if I'm mistaken. Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=147065&r1=147064&r2=147065&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original) +++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Wed Dec 21 13:14:52 2011 @@ -1190,7 +1190,6 @@ // We have target-specific dag combine patterns for the following nodes: setTargetDAGCombine(ISD::VECTOR_SHUFFLE); setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT); - setTargetDAGCombine(ISD::BUILD_VECTOR); setTargetDAGCombine(ISD::VSELECT); setTargetDAGCombine(ISD::SELECT); setTargetDAGCombine(ISD::SHL); From dpatel at apple.com Wed Dec 21 13:20:13 2011 From: dpatel at apple.com (Devang Patel) Date: Wed, 21 Dec 2011 11:20:13 -0800 Subject: [llvm-commits] [llvm] r147037 - /llvm/trunk/lib/Analysis/InlineCost.cpp In-Reply-To: <20111221060630.8F5FD2A6C12C@llvm.org> References: <20111221060630.8F5FD2A6C12C@llvm.org> Message-ID: <4675B739-ACBC-4DB2-A4B0-EE020FE4FDE9@apple.com> On Dec 20, 2011, at 10:06 PM, Nick Lewycky wrote: > Author: nicholas > Date: Wed Dec 21 00:06:30 2011 > New Revision: 147037 > > URL: http://llvm.org/viewvc/llvm-project?rev=147037&view=rev > Log: > A call to a function marked 'noinline' is not an inline candidate. > The sole call site of an intrinsic is also not an inline candidate. Really ? - Devang > While here, make it > more obvious that this code ignores all intrinsics. Noticed by inspection! > > Modified: > llvm/trunk/lib/Analysis/InlineCost.cpp > > Modified: llvm/trunk/lib/Analysis/InlineCost.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/InlineCost.cpp?rev=147037&r1=147036&r2=147037&view=diff > ============================================================================== > --- llvm/trunk/lib/Analysis/InlineCost.cpp (original) > +++ llvm/trunk/lib/Analysis/InlineCost.cpp Wed Dec 21 00:06:30 2011 > @@ -63,8 +63,8 @@ > > // Special handling for calls. > if (isa(II) || isa(II)) { > - if (isa(II)) > - continue; // Debug intrinsics don't count as size. > + if (isa(II)) > + continue; // Intrinsics have no argument setup and can't be inlined. > > ImmutableCallSite CS(cast(II)); > > @@ -72,7 +72,7 @@ > // If a function is both internal and has a single use, then it is > // extremely likely to get inlined in the future (it was probably > // exposed by an interleaved devirtualization pass). > - if (F->hasInternalLinkage() && F->hasOneUse()) > + if (!CS.isNoInline() && F->hasInternalLinkage() && F->hasOneUse()) > ++NumInlineCandidates; > > // If this call is to function itself, then the function is recursive. > @@ -83,7 +83,7 @@ > isRecursive = true; > } > > - if (!isa(II) && !callIsSmall(CS.getCalledFunction())) { > + if (!callIsSmall(CS.getCalledFunction())) { > // Each argument to a call takes on average one instruction to set up. > NumInsts += CS.arg_size(); > > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From grosbach at apple.com Wed Dec 21 13:40:55 2011 From: grosbach at apple.com (Jim Grosbach) Date: Wed, 21 Dec 2011 19:40:55 -0000 Subject: [llvm-commits] [llvm] r147069 - in /llvm/trunk: lib/Target/ARM/ARMBaseInstrInfo.cpp lib/Target/ARM/ARMExpandPseudoInsts.cpp lib/Target/ARM/ARMISelDAGToDAG.cpp lib/Target/ARM/ARMInstrNEON.td test/MC/ARM/neon-vld-encoding.s Message-ID: <20111221194055.84F052A6C12C@llvm.org> Author: grosbach Date: Wed Dec 21 13:40:55 2011 New Revision: 147069 URL: http://llvm.org/viewvc/llvm-project?rev=147069&view=rev Log: ARM NEON assmebly parsing for VLD2 to all lanes instructions. Modified: llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp llvm/trunk/lib/Target/ARM/ARMExpandPseudoInsts.cpp llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp llvm/trunk/lib/Target/ARM/ARMInstrNEON.td llvm/trunk/test/MC/ARM/neon-vld-encoding.s Modified: llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp?rev=147069&r1=147068&r2=147069&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp Wed Dec 21 13:40:55 2011 @@ -2584,9 +2584,12 @@ case ARM::VLD2DUPd8: case ARM::VLD2DUPd16: case ARM::VLD2DUPd32: - case ARM::VLD2DUPd8_UPD: - case ARM::VLD2DUPd16_UPD: - case ARM::VLD2DUPd32_UPD: + case ARM::VLD2DUPd8wb_fixed: + case ARM::VLD2DUPd16wb_fixed: + case ARM::VLD2DUPd32wb_fixed: + case ARM::VLD2DUPd8wb_register: + case ARM::VLD2DUPd16wb_register: + case ARM::VLD2DUPd32wb_register: case ARM::VLD4DUPd8: case ARM::VLD4DUPd16: case ARM::VLD4DUPd32: @@ -2768,9 +2771,12 @@ case ARM::VLD2DUPd8Pseudo: case ARM::VLD2DUPd16Pseudo: case ARM::VLD2DUPd32Pseudo: - case ARM::VLD2DUPd8Pseudo_UPD: - case ARM::VLD2DUPd16Pseudo_UPD: - case ARM::VLD2DUPd32Pseudo_UPD: + case ARM::VLD2DUPd8PseudoWB_fixed: + case ARM::VLD2DUPd16PseudoWB_fixed: + case ARM::VLD2DUPd32PseudoWB_fixed: + case ARM::VLD2DUPd8PseudoWB_register: + case ARM::VLD2DUPd16PseudoWB_register: + case ARM::VLD2DUPd32PseudoWB_register: case ARM::VLD4DUPd8Pseudo: case ARM::VLD4DUPd16Pseudo: case ARM::VLD4DUPd32Pseudo: Modified: llvm/trunk/lib/Target/ARM/ARMExpandPseudoInsts.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMExpandPseudoInsts.cpp?rev=147069&r1=147068&r2=147069&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMExpandPseudoInsts.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMExpandPseudoInsts.cpp Wed Dec 21 13:40:55 2011 @@ -162,11 +162,14 @@ { ARM::VLD1q8PseudoWB_register, ARM::VLD1q8wb_register,true,true, true,SingleSpc,2,8,false}, { ARM::VLD2DUPd16Pseudo, ARM::VLD2DUPd16, true, false, false, SingleSpc, 2, 4,false}, -{ ARM::VLD2DUPd16Pseudo_UPD, ARM::VLD2DUPd16_UPD, true, true, true, SingleSpc, 2, 4,true}, +{ ARM::VLD2DUPd16PseudoWB_fixed, ARM::VLD2DUPd16wb_fixed, true, true, false, SingleSpc, 2, 4,false}, +{ ARM::VLD2DUPd16PseudoWB_register, ARM::VLD2DUPd16wb_register, true, true, true, SingleSpc, 2, 4,false}, { ARM::VLD2DUPd32Pseudo, ARM::VLD2DUPd32, true, false, false, SingleSpc, 2, 2,false}, -{ ARM::VLD2DUPd32Pseudo_UPD, ARM::VLD2DUPd32_UPD, true, true, true, SingleSpc, 2, 2,true}, +{ ARM::VLD2DUPd32PseudoWB_fixed, ARM::VLD2DUPd32wb_fixed, true, true, false, SingleSpc, 2, 2,false}, +{ ARM::VLD2DUPd32PseudoWB_register, ARM::VLD2DUPd32wb_register, true, true, true, SingleSpc, 2, 2,false}, { ARM::VLD2DUPd8Pseudo, ARM::VLD2DUPd8, true, false, false, SingleSpc, 2, 8,false}, -{ ARM::VLD2DUPd8Pseudo_UPD, ARM::VLD2DUPd8_UPD, true, true, true, SingleSpc, 2, 8,true}, +{ ARM::VLD2DUPd8PseudoWB_fixed, ARM::VLD2DUPd8wb_fixed, true, true, false, SingleSpc, 2, 8,false}, +{ ARM::VLD2DUPd8PseudoWB_register, ARM::VLD2DUPd8wb_register, true, true, true, SingleSpc, 2, 8,false}, { ARM::VLD2LNd16Pseudo, ARM::VLD2LNd16, true, false, false, SingleSpc, 2, 4 ,true}, { ARM::VLD2LNd16Pseudo_UPD, ARM::VLD2LNd16_UPD, true, true, true, SingleSpc, 2, 4 ,true}, @@ -1163,9 +1166,12 @@ case ARM::VLD2DUPd8Pseudo: case ARM::VLD2DUPd16Pseudo: case ARM::VLD2DUPd32Pseudo: - case ARM::VLD2DUPd8Pseudo_UPD: - case ARM::VLD2DUPd16Pseudo_UPD: - case ARM::VLD2DUPd32Pseudo_UPD: + case ARM::VLD2DUPd8PseudoWB_fixed: + case ARM::VLD2DUPd16PseudoWB_fixed: + case ARM::VLD2DUPd32PseudoWB_fixed: + case ARM::VLD2DUPd8PseudoWB_register: + case ARM::VLD2DUPd16PseudoWB_register: + case ARM::VLD2DUPd32PseudoWB_register: case ARM::VLD3DUPd8Pseudo: case ARM::VLD3DUPd16Pseudo: case ARM::VLD3DUPd32Pseudo: Modified: llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp?rev=147069&r1=147068&r2=147069&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp Wed Dec 21 13:40:55 2011 @@ -1595,6 +1595,10 @@ case ARM::VST2q8PseudoWB_fixed: return ARM::VST2q8PseudoWB_register; case ARM::VST2q16PseudoWB_fixed: return ARM::VST2q16PseudoWB_register; case ARM::VST2q32PseudoWB_fixed: return ARM::VST2q32PseudoWB_register; + + case ARM::VLD2DUPd8PseudoWB_fixed: return ARM::VLD2DUPd8PseudoWB_register; + case ARM::VLD2DUPd16PseudoWB_fixed: return ARM::VLD2DUPd16PseudoWB_register; + case ARM::VLD2DUPd32PseudoWB_fixed: return ARM::VLD2DUPd32PseudoWB_register; } return Opc; // If not one we handle, return it unchanged. } @@ -2043,8 +2047,14 @@ Ops.push_back(MemAddr); Ops.push_back(Align); if (isUpdating) { + // fixed-stride update instructions don't have an explicit writeback + // operand. It's implicit in the opcode itself. SDValue Inc = N->getOperand(2); - Ops.push_back(isa(Inc.getNode()) ? Reg0 : Inc); + if (!isa(Inc.getNode())) + Ops.push_back(Inc); + // FIXME: VLD3 and VLD4 haven't been updated to that form yet. + else if (NumVecs > 2) + Ops.push_back(Reg0); } Ops.push_back(Pred); Ops.push_back(Reg0); @@ -2798,8 +2808,9 @@ } case ARMISD::VLD2DUP_UPD: { - unsigned Opcodes[] = { ARM::VLD2DUPd8Pseudo_UPD, ARM::VLD2DUPd16Pseudo_UPD, - ARM::VLD2DUPd32Pseudo_UPD }; + unsigned Opcodes[] = { ARM::VLD2DUPd8PseudoWB_fixed, + ARM::VLD2DUPd16PseudoWB_fixed, + ARM::VLD2DUPd32PseudoWB_fixed }; return SelectVLDDup(N, true, 2, Opcodes); } Modified: llvm/trunk/lib/Target/ARM/ARMInstrNEON.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrNEON.td?rev=147069&r1=147068&r2=147069&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrNEON.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrNEON.td Wed Dec 21 13:40:55 2011 @@ -1254,25 +1254,42 @@ def VLD2DUPd32x2 : VLD2DUP<{1,0,1,?}, "32", VecListTwoQAllLanes>; // ...with address register writeback: -class VLD2DUPWB op7_4, string Dt> - : NLdSt<1, 0b10, 0b1101, op7_4, (outs DPR:$Vd, DPR:$dst2, GPR:$wb), - (ins addrmode6dup:$Rn, am6offset:$Rm), IIC_VLD2dupu, - "vld2", Dt, "\\{$Vd[], $dst2[]\\}, $Rn$Rm", "$Rn.addr = $wb", []> { - let Inst{4} = Rn{4}; - let DecoderMethod = "DecodeVLD2DupInstruction"; +multiclass VLD2DUPWB op7_4, string Dt, RegisterOperand VdTy> { + def _fixed : NLdSt<1, 0b10, 0b1101, op7_4, + (outs VdTy:$Vd, GPR:$wb), + (ins addrmode6dup:$Rn), IIC_VLD2dupu, + "vld2", Dt, "$Vd, $Rn!", + "$Rn.addr = $wb", []> { + let Rm = 0b1101; // NLdSt will assign to the right encoding bits. + let Inst{4} = Rn{4}; + let DecoderMethod = "DecodeVLD2DupInstruction"; + let AsmMatchConverter = "cvtVLDwbFixed"; + } + def _register : NLdSt<1, 0b10, 0b1101, op7_4, + (outs VdTy:$Vd, GPR:$wb), + (ins addrmode6dup:$Rn, rGPR:$Rm), IIC_VLD2dupu, + "vld2", Dt, "$Vd, $Rn, $Rm", + "$Rn.addr = $wb", []> { + let Inst{4} = Rn{4}; + let DecoderMethod = "DecodeVLD2DupInstruction"; + let AsmMatchConverter = "cvtVLDwbRegister"; + } } -def VLD2DUPd8_UPD : VLD2DUPWB<{0,0,0,0}, "8">; -def VLD2DUPd16_UPD : VLD2DUPWB<{0,1,0,?}, "16">; -def VLD2DUPd32_UPD : VLD2DUPWB<{1,0,0,?}, "32">; +defm VLD2DUPd8wb : VLD2DUPWB<{0,0,0,0}, "8", VecListTwoDAllLanes>; +defm VLD2DUPd16wb : VLD2DUPWB<{0,1,0,?}, "16", VecListTwoDAllLanes>; +defm VLD2DUPd32wb : VLD2DUPWB<{1,0,0,?}, "32", VecListTwoDAllLanes>; -def VLD2DUPd8x2_UPD : VLD2DUPWB<{0,0,1,0}, "8">; -def VLD2DUPd16x2_UPD : VLD2DUPWB<{0,1,1,?}, "16">; -def VLD2DUPd32x2_UPD : VLD2DUPWB<{1,0,1,?}, "32">; +defm VLD2DUPd8x2wb : VLD2DUPWB<{0,0,1,0}, "8", VecListTwoQAllLanes>; +defm VLD2DUPd16x2wb : VLD2DUPWB<{0,1,1,?}, "16", VecListTwoQAllLanes>; +defm VLD2DUPd32x2wb : VLD2DUPWB<{1,0,1,?}, "32", VecListTwoQAllLanes>; -def VLD2DUPd8Pseudo_UPD : VLDQWBPseudo; -def VLD2DUPd16Pseudo_UPD : VLDQWBPseudo; -def VLD2DUPd32Pseudo_UPD : VLDQWBPseudo; +def VLD2DUPd8PseudoWB_fixed : VLDQWBfixedPseudo ; +def VLD2DUPd8PseudoWB_register : VLDQWBregisterPseudo; +def VLD2DUPd16PseudoWB_fixed : VLDQWBfixedPseudo ; +def VLD2DUPd16PseudoWB_register : VLDQWBregisterPseudo; +def VLD2DUPd32PseudoWB_fixed : VLDQWBfixedPseudo ; +def VLD2DUPd32PseudoWB_register : VLDQWBregisterPseudo; // VLD3DUP : Vector Load (single 3-element structure to all lanes) class VLD3DUP op7_4, string Dt> Modified: llvm/trunk/test/MC/ARM/neon-vld-encoding.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/neon-vld-encoding.s?rev=147069&r1=147068&r2=147069&view=diff ============================================================================== --- llvm/trunk/test/MC/ARM/neon-vld-encoding.s (original) +++ llvm/trunk/test/MC/ARM/neon-vld-encoding.s Wed Dec 21 13:40:55 2011 @@ -238,6 +238,10 @@ vld2.8 {d2[4], d3[4]}, [r2] vld2.32 {d22[], d23[]}, [r1] vld2.32 {d22[], d24[]}, [r1] + vld2.32 {d10[ ],d11[ ]}, [r3]! + vld2.32 {d14[ ],d16[ ]}, [r4]! + vld2.32 {d22[ ],d23[ ]}, [r5], r4 + vld2.32 {d22[ ],d24[ ]}, [r6], r4 @ CHECK: vld2.8 {d16[1], d17[1]}, [r0, :16] @ encoding: [0x3f,0x01,0xe0,0xf4] @ CHECK: vld2.16 {d16[1], d17[1]}, [r0, :32] @ encoding: [0x5f,0x05,0xe0,0xf4] @@ -250,6 +254,10 @@ @ CHECK: vld2.8 {d2[4], d3[4]}, [r2] @ encoding: [0x8f,0x21,0xa2,0xf4] @ CHECK: vld2.32 {d22[], d23[]}, [r1] @ encoding: [0x8f,0x6d,0xe1,0xf4] @ CHECK: vld2.32 {d22[], d24[]}, [r1] @ encoding: [0xaf,0x6d,0xe1,0xf4] +@ CHECK: vld2.32 {d10[], d11[]}, [r3]! @ encoding: [0x8d,0xad,0xa3,0xf4] +@ CHECK: vld2.32 {d14[], d16[]}, [r4]! @ encoding: [0xad,0xed,0xa4,0xf4] +@ CHECK: vld2.32 {d22[], d23[]}, [r5], r4 @ encoding: [0x84,0x6d,0xe5,0xf4] +@ CHECK: vld2.32 {d22[], d24[]}, [r6], r4 @ encoding: [0xa4,0x6d,0xe6,0xf4] @ vld3.8 {d16[1], d17[1], d18[1]}, [r0] From stoklund at 2pi.dk Wed Dec 21 13:50:05 2011 From: stoklund at 2pi.dk (Jakob Stoklund Olesen) Date: Wed, 21 Dec 2011 19:50:05 -0000 Subject: [llvm-commits] [llvm] r147071 - in /llvm/trunk: include/llvm/CodeGen/MachineRegisterInfo.h lib/CodeGen/ExecutionDepsFix.cpp lib/CodeGen/PrologEpilogInserter.cpp lib/Target/ARM/ARMFrameLowering.cpp Message-ID: <20111221195005.B85162A6C12C@llvm.org> Author: stoklund Date: Wed Dec 21 13:50:05 2011 New Revision: 147071 URL: http://llvm.org/viewvc/llvm-project?rev=147071&view=rev Log: Move common code into an MRI function. Modified: llvm/trunk/include/llvm/CodeGen/MachineRegisterInfo.h llvm/trunk/lib/CodeGen/ExecutionDepsFix.cpp llvm/trunk/lib/CodeGen/PrologEpilogInserter.cpp llvm/trunk/lib/Target/ARM/ARMFrameLowering.cpp Modified: llvm/trunk/include/llvm/CodeGen/MachineRegisterInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/MachineRegisterInfo.h?rev=147071&r1=147070&r2=147071&view=diff ============================================================================== --- llvm/trunk/include/llvm/CodeGen/MachineRegisterInfo.h (original) +++ llvm/trunk/include/llvm/CodeGen/MachineRegisterInfo.h Wed Dec 21 13:50:05 2011 @@ -283,7 +283,16 @@ /// isPhysRegUsed - Return true if the specified register is used in this /// function. This only works after register allocation. bool isPhysRegUsed(unsigned Reg) const { return UsedPhysRegs[Reg]; } - + + /// isPhysRegOrOverlapUsed - Return true if Reg or any overlapping register + /// is used in this function. + bool isPhysRegOrOverlapUsed(unsigned Reg) const { + for (const unsigned *AI = TRI->getOverlaps(Reg); *AI; ++AI) + if (isPhysRegUsed(*AI)) + return true; + return false; + } + /// setPhysRegUsed - Mark the specified register used in this function. /// This should only be called during and after register allocation. void setPhysRegUsed(unsigned Reg) { UsedPhysRegs[Reg] = true; } Modified: llvm/trunk/lib/CodeGen/ExecutionDepsFix.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/ExecutionDepsFix.cpp?rev=147071&r1=147070&r2=147071&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/ExecutionDepsFix.cpp (original) +++ llvm/trunk/lib/CodeGen/ExecutionDepsFix.cpp Wed Dec 21 13:50:05 2011 @@ -654,11 +654,10 @@ bool anyregs = false; for (TargetRegisterClass::const_iterator I = RC->begin(), E = RC->end(); I != E; ++I) - for (const unsigned *AI = TRI->getOverlaps(*I); *AI; ++AI) - if (MF->getRegInfo().isPhysRegUsed(*AI)) { - anyregs = true; - break; - } + if (MF->getRegInfo().isPhysRegOrOverlapUsed(*I)) { + anyregs = true; + break; + } if (!anyregs) return false; // Initialize the AliasMap on the first use. Modified: llvm/trunk/lib/CodeGen/PrologEpilogInserter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/PrologEpilogInserter.cpp?rev=147071&r1=147070&r2=147071&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/PrologEpilogInserter.cpp (original) +++ llvm/trunk/lib/CodeGen/PrologEpilogInserter.cpp Wed Dec 21 13:50:05 2011 @@ -224,17 +224,9 @@ std::vector CSI; for (unsigned i = 0; CSRegs[i]; ++i) { unsigned Reg = CSRegs[i]; - if (Fn.getRegInfo().isPhysRegUsed(Reg)) { + if (Fn.getRegInfo().isPhysRegOrOverlapUsed(Reg)) { // If the reg is modified, save it! CSI.push_back(CalleeSavedInfo(Reg)); - } else { - for (const unsigned *AliasSet = RegInfo->getAliasSet(Reg); - *AliasSet; ++AliasSet) { // Check alias registers too. - if (Fn.getRegInfo().isPhysRegUsed(*AliasSet)) { - CSI.push_back(CalleeSavedInfo(Reg)); - break; - } - } } } Modified: llvm/trunk/lib/Target/ARM/ARMFrameLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMFrameLowering.cpp?rev=147071&r1=147070&r2=147071&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMFrameLowering.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMFrameLowering.cpp Wed Dec 21 13:50:05 2011 @@ -898,18 +898,9 @@ for (unsigned i = 0; CSRegs[i]; ++i) { unsigned Reg = CSRegs[i]; bool Spilled = false; - if (MF.getRegInfo().isPhysRegUsed(Reg)) { + if (MF.getRegInfo().isPhysRegOrOverlapUsed(Reg)) { Spilled = true; CanEliminateFrame = false; - } else { - // Check alias registers too. - for (const unsigned *Aliases = - RegInfo->getAliasSet(Reg); *Aliases; ++Aliases) { - if (MF.getRegInfo().isPhysRegUsed(*Aliases)) { - Spilled = true; - CanEliminateFrame = false; - } - } } if (!ARM::GPRRegisterClass->contains(Reg)) From daniel at zuster.org Wed Dec 21 13:59:55 2011 From: daniel at zuster.org (Daniel Dunbar) Date: Wed, 21 Dec 2011 19:59:55 -0000 Subject: [llvm-commits] [zorg] r147073 - /zorg/trunk/lnt/lnt/lnttool/import_data.py Message-ID: <20111221195955.D68D12A6C12C@llvm.org> Author: ddunbar Date: Wed Dec 21 13:59:55 2011 New Revision: 147073 URL: http://llvm.org/viewvc/llvm-project?rev=147073&view=rev Log: [lnt/v0.4] lnt import: Change command to fail on import failures. Modified: zorg/trunk/lnt/lnt/lnttool/import_data.py Modified: zorg/trunk/lnt/lnt/lnttool/import_data.py URL: http://llvm.org/viewvc/llvm-project/zorg/trunk/lnt/lnt/lnttool/import_data.py?rev=147073&r1=147072&r2=147073&view=diff ============================================================================== --- zorg/trunk/lnt/lnt/lnttool/import_data.py (original) +++ zorg/trunk/lnt/lnt/lnttool/import_data.py Wed Dec 21 13:59:55 2011 @@ -63,15 +63,20 @@ db_entry.db_version,) # Load the database. + success = True for file in args: result = lnt.util.ImportData.import_and_report( config, opts.database, db, file, opts.format, opts.commit, opts.show_sample_count, opts.noEmail) + success &= result.get('success', False) if opts.show_raw_result: pprint.pprint(result) else: lnt.util.ImportData.print_report_result(result, sys.stdout, opts.verbose) + if not success: + raise SystemExit, 1 + From daniel at zuster.org Wed Dec 21 13:59:59 2011 From: daniel at zuster.org (Daniel Dunbar) Date: Wed, 21 Dec 2011 19:59:59 -0000 Subject: [llvm-commits] [zorg] r147074 - in /zorg/trunk/lnt/lnt: lnttool/import_data.py util/ImportData.py util/ServerUtil.py Message-ID: <20111221195959.5B8F72A6C12C@llvm.org> Author: ddunbar Date: Wed Dec 21 13:59:59 2011 New Revision: 147074 URL: http://llvm.org/viewvc/llvm-project?rev=147074&view=rev Log: [lnt/v0.4] lnt.util.ImportData: Change status report to print unexpected failures to stderr. Modified: zorg/trunk/lnt/lnt/lnttool/import_data.py zorg/trunk/lnt/lnt/util/ImportData.py zorg/trunk/lnt/lnt/util/ServerUtil.py Modified: zorg/trunk/lnt/lnt/lnttool/import_data.py URL: http://llvm.org/viewvc/llvm-project/zorg/trunk/lnt/lnt/lnttool/import_data.py?rev=147074&r1=147073&r2=147074&view=diff ============================================================================== --- zorg/trunk/lnt/lnt/lnttool/import_data.py (original) +++ zorg/trunk/lnt/lnt/lnttool/import_data.py Wed Dec 21 13:59:59 2011 @@ -75,6 +75,7 @@ pprint.pprint(result) else: lnt.util.ImportData.print_report_result(result, sys.stdout, + sys.stderr, opts.verbose) if not success: Modified: zorg/trunk/lnt/lnt/util/ImportData.py URL: http://llvm.org/viewvc/llvm-project/zorg/trunk/lnt/lnt/util/ImportData.py?rev=147074&r1=147073&r2=147074&view=diff ============================================================================== --- zorg/trunk/lnt/lnt/util/ImportData.py (original) +++ zorg/trunk/lnt/lnt/util/ImportData.py Wed Dec 21 13:59:59 2011 @@ -100,7 +100,7 @@ result['success'] = True return result -def print_report_result(result, out, verbose = True): +def print_report_result(result, out, err, verbose = True): """ import_and_report(result, out) -> None @@ -114,8 +114,10 @@ print >>out, "Import succeeded." print >>out else: - print >>out, "Import Failed:" - print >>out, "--\n%s--\n" % result['error'] + out.flush() + print >>err, "Import Failed:" + print >>err, "--\n%s--\n" % result['error'] + err.flush() return if 'original_run' in result: Modified: zorg/trunk/lnt/lnt/util/ServerUtil.py URL: http://llvm.org/viewvc/llvm-project/zorg/trunk/lnt/lnt/util/ServerUtil.py?rev=147074&r1=147073&r2=147074&view=diff ============================================================================== --- zorg/trunk/lnt/lnt/util/ServerUtil.py (original) +++ zorg/trunk/lnt/lnt/util/ServerUtil.py Wed Dec 21 13:59:59 2011 @@ -38,7 +38,7 @@ return # Print the test report. - ImportData.print_report_result(result, sys.stdout, verbose) + ImportData.print_report_result(result, sys.stdout, sys.stderr, verbose) def submitFiles(url, files, commit, verbose): for file in files: From daniel at zuster.org Wed Dec 21 14:00:03 2011 From: daniel at zuster.org (Daniel Dunbar) Date: Wed, 21 Dec 2011 20:00:03 -0000 Subject: [llvm-commits] [zorg] r147075 - in /zorg/trunk/lnt/lnt/server: db/testsuitedb.py ui/templates/v4_machine.html Message-ID: <20111221200003.22A312A6C12C@llvm.org> Author: ddunbar Date: Wed Dec 21 14:00:02 2011 New Revision: 147075 URL: http://llvm.org/viewvc/llvm-project?rev=147075&view=rev Log: [lnt/v0.4] lnt.server.db.testsuitedb: Refine model classes. - Change .parameters methods to be properties. - Factor out methods based on parameterized table access. Modified: zorg/trunk/lnt/lnt/server/db/testsuitedb.py zorg/trunk/lnt/lnt/server/ui/templates/v4_machine.html Modified: zorg/trunk/lnt/lnt/server/db/testsuitedb.py URL: http://llvm.org/viewvc/llvm-project/zorg/trunk/lnt/lnt/server/db/testsuitedb.py?rev=147075&r1=147074&r2=147075&view=diff ============================================================================== --- zorg/trunk/lnt/lnt/server/db/testsuitedb.py (original) +++ zorg/trunk/lnt/lnt/server/db/testsuitedb.py Wed Dec 21 14:00:02 2011 @@ -38,8 +38,15 @@ self.base = sqlalchemy.ext.declarative.declarative_base() # Create parameterized model classes for this test suite. + class ParameterizedMixin(object): + def get_field(self, field): + return getattr(self, field.name) + + def set_field(self, field, value): + return setattr(self, field.name, value) + db_key_name = self.test_suite.db_key_name - class Machine(self.base): + class Machine(self.base, ParameterizedMixin): __tablename__ = db_key_name + '_Machine' fields = self.machine_fields @@ -49,7 +56,7 @@ # The parameters blob is used to store any additional information # reported by the run but not promoted into the machine record. Such # data is stored as a JSON encoded blob. - parameters = Column("Parameters", Binary) + parameters_data = Column("Parameters", Binary) # Dynamically create fields for all of the test suite defined # machine fields. @@ -69,16 +76,16 @@ return '%s_%s%r' % (db_key_name, self.__class__.__name__, (self.name,)) - def get_field(self, field): - return getattr(self, field.name) + @property + def parameters(self): + """dictionary access to the BLOB encoded parameters data""" + return dict(json.loads(self.parameters_data)) + + @parameters.setter + def parameters(self, data): + self.parameters_data = json.dumps(sorted(data.items())) - def set_field(self, field, value): - return setattr(self, field.name, value) - - def get_parameters(self): - return json.loads(self.parameters) - - class Order(self.base): + class Order(self.base, ParameterizedMixin): __tablename__ = db_key_name + '_Order' fields = self.order_fields @@ -102,9 +109,6 @@ for item in self.fields: self.set_field(item, kwargs[item.name]) - def __repr__(self): - return '%s_%s%r' % (db_key_name, self.__class__.__name__, - ()) def __repr__(self): fields = dict((item.name, self.get_field(item)) @@ -113,13 +117,7 @@ return '%s_%s(**%r)' % ( db_key_name, self.__class__.__name__, fields) - def get_field(self, field): - return getattr(self, field.name) - - def set_field(self, field, value): - return setattr(self, field.name, value) - - class Run(self.base): + class Run(self.base, ParameterizedMixin): __tablename__ = db_key_name + '_Run' fields = self.run_fields @@ -135,7 +133,7 @@ # The parameters blob is used to store any additional information # reported by the run but not promoted into the machine record. Such # data is stored as a JSON encoded blob. - parameters = Column("Parameters", Binary) + parameters_data = Column("Parameters", Binary) machine = sqlalchemy.orm.relation(Machine) order = sqlalchemy.orm.relation(Order) @@ -166,16 +164,16 @@ (self.machine, self.order, self.start_time, self.end_time)) - def get_field(self, field): - return getattr(self, field.name) - - def set_field(self, field, value): - return setattr(self, field.name, value) - - def get_parameters(self): - return json.loads(self.parameters) + @property + def parameters(self): + """dictionary access to the BLOB encoded parameters data""" + return dict(json.loads(self.parameters_data)) + + @parameters.setter + def parameters(self, data): + self.parameters_data = json.dumps(sorted(data.items())) - class Test(self.base): + class Test(self.base, ParameterizedMixin): __tablename__ = db_key_name + '_Test' id = Column("ID", Integer, primary_key=True) @@ -188,13 +186,7 @@ return '%s_%s%r' % (db_key_name, self.__class__.__name__, (self.name,)) - def get_field(self, field): - return getattr(self, field.name) - - def set_field(self, field, value): - return setattr(self, field.name, value) - - class Sample(self.base): + class Sample(self.base, ParameterizedMixin): __tablename__ = db_key_name + '_Sample' fields = self.sample_fields @@ -248,12 +240,6 @@ db_key_name, self.__class__.__name__, self.run, self.test, fields) - def get_field(self, field): - return getattr(self, field.name) - - def set_field(self, field, value): - return setattr(self, field.name, value) - self.Machine = Machine self.Run = Run self.Test = Test @@ -265,7 +251,7 @@ Sample.run_id, Sample.test_id) # Create the index we use to ensure machine uniqueness. - args = [Machine.name, Machine.parameters] + args = [Machine.name, Machine.parameters_data] for item in self.machine_fields: args.append(item.column) sqlalchemy.schema.Index("ix_%s_Machine_Unique" % db_key_name, @@ -312,13 +298,14 @@ value = '' query = query.filter(item.column == value) - machine.set_field(item.name, value) + machine.set_field(item, value) # Convert any remaining machine_parameters into a JSON encoded blob. We # encode this as an array to avoid a potential ambiguity on the key # ordering. - machine.parameters = json.dumps(sorted(machine_parameters.items())) - query = query.filter(self.Machine.parameters == machine.parameters) + machine.parameters = machine_parameters + query = query.filter(self.Machine.parameters_data == + machine.parameters_data) # Execute the query to see if we already have this machine. try: @@ -418,8 +405,8 @@ run.set_field(item, value) # Any remaining parameters are saved as a JSON encoded array. - run.parameters = json.dumps(sorted(run_parameters.items())) - query = query.filter(self.Run.parameters == run.parameters) + run.parameters = run_parameters + query = query.filter(self.Run.parameters_data == run.parameters_data) # Execute the query to see if we already have this run. try: Modified: zorg/trunk/lnt/lnt/server/ui/templates/v4_machine.html URL: http://llvm.org/viewvc/llvm-project/zorg/trunk/lnt/lnt/server/ui/templates/v4_machine.html?rev=147075&r1=147074&r2=147075&view=diff ============================================================================== --- zorg/trunk/lnt/lnt/server/ui/templates/v4_machine.html (original) +++ zorg/trunk/lnt/lnt/server/ui/templates/v4_machine.html Wed Dec 21 14:00:02 2011 @@ -50,7 +50,7 @@

Parameters

-{% for key,value in machine.get_parameters() %} +{% for key,value in machine.parameters|dictsort %} From daniel at zuster.org Wed Dec 21 14:00:06 2011 From: daniel at zuster.org (Daniel Dunbar) Date: Wed, 21 Dec 2011 20:00:06 -0000 Subject: [llvm-commits] [zorg] r147076 - /zorg/trunk/lnt/lnt/server/db/testsuitedb.py Message-ID: <20111221200006.304CD2A6C12C@llvm.org> Author: ddunbar Date: Wed Dec 21 14:00:05 2011 New Revision: 147076 URL: http://llvm.org/viewvc/llvm-project?rev=147076&view=rev Log: [lnt/v0.4] lnt.server.db.testsuitedb: Add an ordinal field to Order class. - Defines the index in the total ordering of Orders. - We are probably going to have to refine this abstraction eventually, but this will work for now and allows for tidy queries. Modified: zorg/trunk/lnt/lnt/server/db/testsuitedb.py Modified: zorg/trunk/lnt/lnt/server/db/testsuitedb.py URL: http://llvm.org/viewvc/llvm-project/zorg/trunk/lnt/lnt/server/db/testsuitedb.py?rev=147076&r1=147075&r2=147076&view=diff ============================================================================== --- zorg/trunk/lnt/lnt/server/db/testsuitedb.py (original) +++ zorg/trunk/lnt/lnt/server/db/testsuitedb.py Wed Dec 21 14:00:05 2011 @@ -88,14 +88,29 @@ class Order(self.base, ParameterizedMixin): __tablename__ = db_key_name + '_Order' - fields = self.order_fields + # We guarantee that our fields are stored in the order they are + # supposed to be lexicographically compared, the __cmp__ method + # relies on this. + fields = sorted(self.order_fields, + key = lambda of: of.ordinal) + + id = Column("ID", Integer, primary_key=True) + # The ordinal defines the placement of the Order record within the + # total ordering. The ordinals are always [0, count(Order)) and are + # maintained by the insertion code. + # + # FIXME: There are many other ways we could deal with this + # information. Obviously we could always manage it outside the + # database, but we could also store things like previous and next + # links in the orders (which would be easier to update, but harder + # to query, but also supports more complicated ordering schemes). + ordinal = Column("Ordinal", Integer, nullable=False, unique=True, + index=True) + # Dynamically create fields for all of the test suite defined order # fields. - # - # FIXME: We are probably going to want to index on some of these, - # but need a bit for that in the test suite definition. class_dict = locals() for item in self.order_fields: if item.name in class_dict: @@ -105,17 +120,25 @@ class_dict[item.name] = item.column = Column( item.name, String(256)) - def __init__(self, **kwargs): - for item in self.fields: - self.set_field(item, kwargs[item.name]) + def __init__(self, ordinal, **kwargs): + self.ordinal = ordinal + # Initialize fields (defaulting to None, for now). + for item in self.fields: + self.set_field(item, kwargs.get(item.name)) def __repr__(self): fields = dict((item.name, self.get_field(item)) for item in self.fields) - return '%s_%s(**%r)' % ( - db_key_name, self.__class__.__name__, fields) + return '%s_%s(%r, **%r)' % ( + db_key_name, self.__class__.__name__, self.ordinal, fields) + + def __cmp__(self, b): + return cmp(tuple(self.get_field(item) + for item in self.fields), + tuple(b.get_field(item) + for item in self.fields)) class Run(self.base, ParameterizedMixin): __tablename__ = db_key_name + '_Run' @@ -331,7 +354,7 @@ """ query = self.query(self.Order) - order = self.Order() + order = self.Order(ordinal = None) # First, extract all of the specified order fields. for item in self.order_fields: @@ -350,7 +373,31 @@ try: return query.one(),False except sqlalchemy.orm.exc.NoResultFound: - # If not, add the run. + # If not, then we need to assign an ordinal to this run. + # + # For now, we do this in the simple, slow, and stupid fashion in + # which we just recompute the total ordering and reassign the + # ordinals. + # + # FIXME: Optimize this for the common case, in which the new ordinal + # will almost always be very close to the top value, and will + # require shifting only a few (or no) other order ordinals. + + # Load all the orders. + orders = list(self.query(self.Order)) + orders.append(order) + + # Sort the objects to form the total ordering. + orders.sort() + + # Assign ordinals. + for i,o in enumerate(orders): + # FIXME: Figure out whether or not SA checks modified status on + # write or on value change. + if o.ordinal != i: + o.ordinal = i + + # Finally, add the new order. self.add(order) return order,True @@ -508,3 +555,6 @@ def getMachine(self, id): return self.query(self.Machine).filter_by(id=id).one() + + def getRun(self, id): + return self.query(self.Run).filter_by(id=id).one() From daniel at zuster.org Wed Dec 21 14:00:11 2011 From: daniel at zuster.org (Daniel Dunbar) Date: Wed, 21 Dec 2011 20:00:11 -0000 Subject: [llvm-commits] [zorg] r147077 - in /zorg/trunk/lnt: lnt/lnttool/create.py lnt/server/db/testsuite.py lnt/server/db/v4db.py tests/server/db/CreateV4TestSuiteInstance.py Message-ID: <20111221200011.2E7502A6C12C@llvm.org> Author: ddunbar Date: Wed Dec 21 14:00:10 2011 New Revision: 147077 URL: http://llvm.org/viewvc/llvm-project?rev=147077&view=rev Log: [lnt/v0.4] lnt create: Fix create to properly initialize StatusKind table. - Also, fix up some problems in the CreateV4TestSuiteInstance test. Modified: zorg/trunk/lnt/lnt/lnttool/create.py zorg/trunk/lnt/lnt/server/db/testsuite.py zorg/trunk/lnt/lnt/server/db/v4db.py zorg/trunk/lnt/tests/server/db/CreateV4TestSuiteInstance.py Modified: zorg/trunk/lnt/lnt/lnttool/create.py URL: http://llvm.org/viewvc/llvm-project/zorg/trunk/lnt/lnt/lnttool/create.py?rev=147077&r1=147076&r2=147077&view=diff ============================================================================== --- zorg/trunk/lnt/lnt/lnttool/create.py (original) +++ zorg/trunk/lnt/lnt/lnttool/create.py Wed Dec 21 14:00:10 2011 @@ -78,6 +78,7 @@ ### import lnt.db.perfdb +import lnt.testing def _create_v4_nt_database(db_path): from lnt.server.db import v4db, testsuite @@ -89,6 +90,13 @@ # Create an NT compatible test suite, automatically. ts = testsuite.TestSuite("nt", "NT") + # Define the default status kinds. + # + # FIXME: This should probably be done by V4DB. + db.add(testsuite.StatusKind(lnt.testing.PASS, "PASS")) + db.add(testsuite.StatusKind(lnt.testing.FAIL, "FAIL")) + db.add(testsuite.StatusKind(lnt.testing.XFAIL, "XFAIL")) + # Define the default sample types. # # FIXME: This should probably be done by V4DB. Modified: zorg/trunk/lnt/lnt/server/db/testsuite.py URL: http://llvm.org/viewvc/llvm-project/zorg/trunk/lnt/lnt/server/db/testsuite.py?rev=147077&r1=147076&r2=147077&view=diff ============================================================================== --- zorg/trunk/lnt/lnt/server/db/testsuite.py (original) +++ zorg/trunk/lnt/lnt/server/db/testsuite.py Wed Dec 21 14:00:10 2011 @@ -46,7 +46,8 @@ id = Column("ID", Integer, primary_key=True) name = Column("Name", String(256), unique=True) - def __init__(self, name): + def __init__(self, id, name): + self.id = id self.name = name def __repr__(self): Modified: zorg/trunk/lnt/lnt/server/db/v4db.py URL: http://llvm.org/viewvc/llvm-project/zorg/trunk/lnt/lnt/server/db/v4db.py?rev=147077&r1=147076&r2=147077&view=diff ============================================================================== --- zorg/trunk/lnt/lnt/server/db/v4db.py (original) +++ zorg/trunk/lnt/lnt/server/db/v4db.py Wed Dec 21 14:00:10 2011 @@ -74,6 +74,12 @@ self.query = self.session.query self.rollback = self.session.rollback + # For parity with the usage of TestSuiteDB, we make our primary model + # classes available as instance variables. + self.SampleType = testsuite.SampleType + self.StatusKind = testsuite.StatusKind + self.TestSuite = testsuite.TestSuite + @property def testsuite(self): # This is the start of "magic" part of V4DB, which allows us to get Modified: zorg/trunk/lnt/tests/server/db/CreateV4TestSuiteInstance.py URL: http://llvm.org/viewvc/llvm-project/zorg/trunk/lnt/tests/server/db/CreateV4TestSuiteInstance.py?rev=147077&r1=147076&r2=147077&view=diff ============================================================================== --- zorg/trunk/lnt/tests/server/db/CreateV4TestSuiteInstance.py (original) +++ zorg/trunk/lnt/tests/server/db/CreateV4TestSuiteInstance.py Wed Dec 21 14:00:10 2011 @@ -41,9 +41,9 @@ start_time = datetime.datetime.utcnow() end_time = datetime.datetime.utcnow() -machine = ts_db.Machine("test-machine", 1) +machine = ts_db.Machine("test-machine") machine.uname = "test-uname" -order = ts_db.Order() +order = ts_db.Order(ordinal = 0) order.llvm_revision = "test-revision" run = ts_db.Run(machine, order, start_time, end_time) run.arch = "test-arch" @@ -83,9 +83,9 @@ # Audit the various fields. assert machine.name == "test-machine" -assert machine.number == 1 assert machine.uname == "test-uname" +assert order.ordinal == 0 assert order.llvm_revision == "test-revision" assert run.machine is machine From daniel at zuster.org Wed Dec 21 14:00:15 2011 From: daniel at zuster.org (Daniel Dunbar) Date: Wed, 21 Dec 2011 20:00:15 -0000 Subject: [llvm-commits] [zorg] r147078 - in /zorg/trunk/lnt/tests/server/db: ImportV4TestSuiteInstance.py Inputs/sample-a-small.plist Inputs/sample-b-small.plist Message-ID: <20111221200015.1D65D2A6C12C@llvm.org> Author: ddunbar Date: Wed Dec 21 14:00:14 2011 New Revision: 147078 URL: http://llvm.org/viewvc/llvm-project?rev=147078&view=rev Log: [lnt/v0.4] tests: Finish out the ImportV4? test. Modified: zorg/trunk/lnt/tests/server/db/ImportV4TestSuiteInstance.py zorg/trunk/lnt/tests/server/db/Inputs/sample-a-small.plist zorg/trunk/lnt/tests/server/db/Inputs/sample-b-small.plist Modified: zorg/trunk/lnt/tests/server/db/ImportV4TestSuiteInstance.py URL: http://llvm.org/viewvc/llvm-project/zorg/trunk/lnt/tests/server/db/ImportV4TestSuiteInstance.py?rev=147078&r1=147077&r2=147078&view=diff ============================================================================== --- zorg/trunk/lnt/tests/server/db/ImportV4TestSuiteInstance.py (original) +++ zorg/trunk/lnt/tests/server/db/ImportV4TestSuiteInstance.py Wed Dec 21 14:00:14 2011 @@ -5,40 +5,111 @@ # RUN: lnt create --use-v4 %t.install # Import the first test set. -# RUNX: lnt import %t.install %S/Inputs/sample-a-small.plist \ -# RUNX: --commit=1 --show-sample-count | \ -# RUNX: FileCheck -check-prefix=IMPORT-A-1 %s +# RUN: lnt import %t.install %S/Inputs/sample-a-small.plist \ +# RUN: --commit=1 --show-sample-count > %t1.log +# RUN: FileCheck -check-prefix=IMPORT-A-1 %s < %t1.log # # IMPORT-A-1: Added Machines: 1 # IMPORT-A-1: Added Runs : 1 -# IMPORT-A-1: Added Tests : 8 -# IMPORT-A-1: Added Samples : 8 +# IMPORT-A-1: Added Tests : 1 +# IMPORT-A-1: Added Samples : 1 # Import the second test set. -# RUNX: lnt import %t.install %S/Inputs/sample-b-small.plist \ -# RUNX: --commit=1 --show-sample-count |\ -# RUNX: FileCheck -check-prefix=IMPORT-B %s +# RUN: lnt import %t.install %S/Inputs/sample-b-small.plist \ +# RUN: --commit=1 --show-sample-count --show-sql > %t2.log +# RUN: FileCheck -check-prefix=IMPORT-B %s < %t2.log # # IMPORT-B: Added Runs : 1 -# IMPORT-B: Added Samples : 8 +# IMPORT-B: Added Samples : 1 # Check that reimporting the first test set properly reports as a duplicate. -# RUNX: lnt import %t.install %S/Inputs/sample-a-small.plist \ -# RUNX: --commit=1 --show-sample-count | \ -# RUNX: FileCheck -check-prefix=IMPORT-A-2 %s +# RUN: lnt import %t.install %S/Inputs/sample-a-small.plist \ +# RUN: --commit=1 --show-sample-count > %t3.log +# RUN: FileCheck -check-prefix=IMPORT-A-2 %s < %t3.log # # IMPORT-A-2: This submission is a duplicate of run 1 +# Dump a copy of the database, so it will show up in logs. +# RUN: sqlite3 %t.install/data/lnt.db .dump + # Run consistency checks on the final database, to validate the import. # RUN: python %s %t.install/data/lnt.db import datetime, sys +import lnt.testing from lnt.server.db import testsuite from lnt.server.db import v4db # Load the test database. db = v4db.V4DB("sqlite:///%s" % sys.argv[1], echo=True) +# Get the status kinds, and validate the IDs align with the testing IDs. +pass_kind = db.query(db.StatusKind).filter_by(id = lnt.testing.PASS).one() +assert pass_kind.name == "PASS" +fail_kind = db.query(db.StatusKind).filter_by(id = lnt.testing.FAIL).one() +assert fail_kind.name == "FAIL" +xfail_kind = db.query(db.StatusKind).filter_by(id = lnt.testing.XFAIL).one() +assert xfail_kind.name == "XFAIL" + # Load the imported test suite. ts = db.testsuite['nt'] + +# Validate the machine. +machines = list(ts.query(ts.Machine)) +assert len(machines) == 1 +machine = machines[0] +assert machine.name == 'LNT SAMPLE MACHINE' +assert machine.hardware == "x86_64" +assert machine.os == "SAMPLE OS" +parameters = machine.parameters +assert len(parameters) == 1 +assert parameters['extrakey'] == u'extravalue' + +# Validate the tests. +tests = list(ts.query(ts.Test)) +assert len(tests) == 1 +test = tests[0] +assert tests[0].name == 'sampletest' + +# Validate the orders. +orders = list(ts.query(ts.Order).order_by(ts.Order.ordinal)) +assert len(orders) == 2 +order_a,order_b = orders +assert order_a.ordinal == 0 +assert order_a.llvm_project_revision == u'% 7d' % 1 +assert order_b.ordinal == 1 +assert order_b.llvm_project_revision == u'% 7d' % 2 + +# Validate the runs. +runs = list(ts.query(ts.Run)) +assert len(runs) == 2 +run_a,run_b = runs +assert run_a.machine is machine +assert run_b.machine is machine +assert run_a.order is order_a +assert run_b.order is order_b +# FIXME: Set imported_from correctly. +assert run_a.imported_from is None +assert run_b.imported_from is None +assert run_a.start_time == datetime.datetime(2009, 11, 17, 2, 12, 25) +assert run_a.end_time == datetime.datetime(2009, 11, 17, 3, 44, 48) +assert not run_a.parameters +assert not run_b.parameters + +# Validate the samples. +samples = list(ts.query(ts.Sample)) +assert len(samples) == 2 +sample_a,sample_b = samples +assert sample_a.run is run_a +assert sample_b.run is run_b +assert sample_a.test is test +assert sample_b.test is test +assert sample_a.compile_time == 0.019 +assert sample_a.compile_status == lnt.testing.PASS +assert sample_a.execution_time == 0.3 +assert sample_a.execution_status == lnt.testing.PASS +assert sample_b.compile_time == 0.022 +assert sample_b.compile_status == lnt.testing.PASS +assert sample_b.execution_time == 0.32 +assert sample_b.execution_status == lnt.testing.PASS Modified: zorg/trunk/lnt/tests/server/db/Inputs/sample-a-small.plist URL: http://llvm.org/viewvc/llvm-project/zorg/trunk/lnt/tests/server/db/Inputs/sample-a-small.plist?rev=147078&r1=147077&r2=147078&view=diff ============================================================================== --- zorg/trunk/lnt/tests/server/db/Inputs/sample-a-small.plist (original) +++ zorg/trunk/lnt/tests/server/db/Inputs/sample-a-small.plist Wed Dec 21 14:00:14 2011 @@ -6,14 +6,12 @@ Info - gcc_version - i686-apple-darwin10-gcc-4.2.1 (GCC) 4.2.1 (Apple Inc. build 5646) - name - smoosh-01 + extrakey + extravalue os - Darwin 10.2.0 - uname - Darwin smoosh-01 10.2.0 Darwin Kernel Version 10.2.0: Tue Nov 3 10:37:10 PST 2009; root:xnu-1486.2.11~1/RELEASE_I386 i386hardware: i386 + SAMPLE OS + hardware + x86_64 Name LNT SAMPLE MACHINE @@ -43,7 +41,7 @@ Name - nightlytest.SingleSource/Benchmarks/BenchmarkGame/fannkuch.compile.status + sampletest.compile.status Data @@ -54,7 +52,7 @@ Name - nightlytest.SingleSource/Benchmarks/BenchmarkGame/fannkuch.compile.time + sampletest.compile Data @@ -65,7 +63,7 @@ Name - nightlytest.SingleSource/Benchmarks/BenchmarkGame/fannkuch.exec.status + sampletest.exec.status Data @@ -76,7 +74,7 @@ Name - nightlytest.SingleSource/Benchmarks/BenchmarkGame/fannkuch.exec.time + sampletest.exec Modified: zorg/trunk/lnt/tests/server/db/Inputs/sample-b-small.plist URL: http://llvm.org/viewvc/llvm-project/zorg/trunk/lnt/tests/server/db/Inputs/sample-b-small.plist?rev=147078&r1=147077&r2=147078&view=diff ============================================================================== --- zorg/trunk/lnt/tests/server/db/Inputs/sample-b-small.plist (original) +++ zorg/trunk/lnt/tests/server/db/Inputs/sample-b-small.plist Wed Dec 21 14:00:14 2011 @@ -6,14 +6,12 @@ Info - gcc_version - i686-apple-darwin10-gcc-4.2.1 (GCC) 4.2.1 (Apple Inc. build 5646) - name - smoosh-01 + extrakey + extravalue os - Darwin 10.2.0 - uname - Darwin smoosh-01 10.2.0 Darwin Kernel Version 10.2.0: Tue Nov 3 10:37:10 PST 2009; root:xnu-1486.2.11~1/RELEASE_I386 i386hardware: i386 + SAMPLE OS + hardware + x86_64 Name LNT SAMPLE MACHINE @@ -43,7 +41,7 @@ Name - nightlytest.SingleSource/Benchmarks/BenchmarkGame/fannkuch.compile.status + sampletest.compile.status Data @@ -54,7 +52,7 @@ Name - nightlytest.SingleSource/Benchmarks/BenchmarkGame/fannkuch.compile.time + sampletest.compile Data @@ -65,7 +63,7 @@ Name - nightlytest.SingleSource/Benchmarks/BenchmarkGame/fannkuch.exec.status + sampletest.exec.status Data @@ -76,7 +74,7 @@ Name - nightlytest.SingleSource/Benchmarks/BenchmarkGame/fannkuch.exec.time + sampletest.exec From daniel at zuster.org Wed Dec 21 14:00:17 2011 From: daniel at zuster.org (Daniel Dunbar) Date: Wed, 21 Dec 2011 20:00:17 -0000 Subject: [llvm-commits] [zorg] r147079 - /zorg/trunk/lnt/docs/todo.rst Message-ID: <20111221200017.801C62A6C12C@llvm.org> Author: ddunbar Date: Wed Dec 21 14:00:17 2011 New Revision: 147079 URL: http://llvm.org/viewvc/llvm-project?rev=147079&view=rev Log: lnt/docs: Add some todo notes on better SQLite database management. Modified: zorg/trunk/lnt/docs/todo.rst Modified: zorg/trunk/lnt/docs/todo.rst URL: http://llvm.org/viewvc/llvm-project/zorg/trunk/lnt/docs/todo.rst?rev=147079&r1=147078&r2=147079&view=diff ============================================================================== --- zorg/trunk/lnt/docs/todo.rst (original) +++ zorg/trunk/lnt/docs/todo.rst Wed Dec 21 14:00:17 2011 @@ -30,6 +30,17 @@ These changes would significantly compact the archive format, which improves performance across the board. +Other stuff: + + 1. We should find ways to manage the SQLite databases better. Currently we: + + o Could benefit from having LNT manage when to run ANALYZE. + + o Could benefit from making LNT handle setting some of the page size + pragmas, at some point. + + o Could benefit from finding a way to have LNT VACUUM, although this can be + very expensive. v0.4 Redesign ------------- From daniel at zuster.org Wed Dec 21 14:00:20 2011 From: daniel at zuster.org (Daniel Dunbar) Date: Wed, 21 Dec 2011 20:00:20 -0000 Subject: [llvm-commits] [zorg] r147080 - in /zorg/trunk/lnt/lnt/server/db: testsuitedb.py v4db.py Message-ID: <20111221200020.C90652A6C12C@llvm.org> Author: ddunbar Date: Wed Dec 21 14:00:20 2011 New Revision: 147080 URL: http://llvm.org/viewvc/llvm-project?rev=147080&view=rev Log: [lnt/v0.4] lnt.server.db.testsuitedb: Store the suite name in the DB wrapper. Modified: zorg/trunk/lnt/lnt/server/db/testsuitedb.py zorg/trunk/lnt/lnt/server/db/v4db.py Modified: zorg/trunk/lnt/lnt/server/db/testsuitedb.py URL: http://llvm.org/viewvc/llvm-project/zorg/trunk/lnt/lnt/server/db/testsuitedb.py?rev=147080&r1=147079&r2=147080&view=diff ============================================================================== --- zorg/trunk/lnt/lnt/server/db/testsuitedb.py (original) +++ zorg/trunk/lnt/lnt/server/db/testsuitedb.py Wed Dec 21 14:00:20 2011 @@ -24,9 +24,10 @@ through the model classes constructed by this wrapper object. """ - def __init__(self, v4db, test_suite): + def __init__(self, v4db, name, test_suite): testsuitedb = self self.v4db = v4db + self.name = name self.test_suite = test_suite # Save caches of the various fields. Modified: zorg/trunk/lnt/lnt/server/db/v4db.py URL: http://llvm.org/viewvc/llvm-project/zorg/trunk/lnt/lnt/server/db/v4db.py?rev=147080&r1=147079&r2=147080&view=diff ============================================================================== --- zorg/trunk/lnt/lnt/server/db/v4db.py (original) +++ zorg/trunk/lnt/lnt/server/db/v4db.py Wed Dec 21 14:00:20 2011 @@ -30,7 +30,8 @@ raise IndexError,name # Instantiate the per-test suite wrapper object for this test suite. - self._cache[name] = ts = testsuitedb.TestSuiteDB(self.v4db, ts) + self._cache[name] = ts = testsuitedb.TestSuiteDB( + self.v4db, name, ts) return ts def get(self, name, default = None): From daniel at zuster.org Wed Dec 21 14:00:24 2011 From: daniel at zuster.org (Daniel Dunbar) Date: Wed, 21 Dec 2011 20:00:24 -0000 Subject: [llvm-commits] [zorg] r147081 - in /zorg/trunk/lnt/lnt/server/ui: templates/v4_order.html templates/v4_overview.html views.py Message-ID: <20111221200024.AA94A2A6C12C@llvm.org> Author: ddunbar Date: Wed Dec 21 14:00:24 2011 New Revision: 147081 URL: http://llvm.org/viewvc/llvm-project?rev=147081&view=rev Log: [lnt/v0.4] lnt.server.ui/v4: Add a primitive UI for browing runs by order, which is now trivial to implement. Added: zorg/trunk/lnt/lnt/server/ui/templates/v4_order.html Modified: zorg/trunk/lnt/lnt/server/ui/templates/v4_overview.html zorg/trunk/lnt/lnt/server/ui/views.py Added: zorg/trunk/lnt/lnt/server/ui/templates/v4_order.html URL: http://llvm.org/viewvc/llvm-project/zorg/trunk/lnt/lnt/server/ui/templates/v4_order.html?rev=147081&view=auto ============================================================================== --- zorg/trunk/lnt/lnt/server/ui/templates/v4_order.html (added) +++ zorg/trunk/lnt/lnt/server/ui/templates/v4_order.html Wed Dec 21 14:00:24 2011 @@ -0,0 +1,65 @@ +{% import "utils.html" as utils %} + +{% extends "layout.html" %}{ +{% set components = [(ts.name, v4_url_for("v4_overview"))] %} +{% block head %} + +{% endblock %} +{% block title %}Order: {{order.id}}{% endblock %} +{% block body %} + +

Order Fields

{{key}}

+ + + + + + + + + + +{% for field in order.fields %} + + + + +{% endfor %} +

Name	Value
Ordinal	{{order.ordinal}}
{{field.name}}	{{order.get_field(field)}}

+ +{# Provide links to the previous and next orders. #} +{% if order.ordinal != 0 %} +Previous +{% endif %} +Next + +{# List all submissions which reported for this order. #} +

Submissions

+ + + + + + + + + + +{# Show the active submissions. #} +{% for r in ts.query(ts.Run).filter_by(order_id = order.id) %} +{% set m = r.machine %} + + + + + + +{% endfor %} +

Start Time	End Time	Machine	Results
{{r.start_time}}	{{r.end_time}}	{{ + m.name}}:{{m.id}}	+ View Results

Num. Submissions: {{ + ts.query(ts.Run).filter_by(order_id = order.id).count()}}

Fields

+ + + {% for item in ts.machine_fields %} @@ -50,6 +53,9 @@

Name	Value
{{item.name}}

Parameters

+ + + {% for key,value in machine.parameters|dictsort %} Added: zorg/trunk/lnt/lnt/server/ui/templates/v4_run.html URL: http://llvm.org/viewvc/llvm-project/zorg/trunk/lnt/lnt/server/ui/templates/v4_run.html?rev=147082&view=auto ============================================================================== --- zorg/trunk/lnt/lnt/server/ui/templates/v4_run.html (added) +++ zorg/trunk/lnt/lnt/server/ui/templates/v4_run.html Wed Dec 21 14:00:28 2011 @@ -0,0 +1,86 @@ +{% import "v4_utils.html" as v4_utils %} +{% import "utils.html" as utils %} + +{% set machine = run.machine %} + +{% extends "layout.html" %} +{% set components = [(ts.name, v4_url_for("v4_overview")), + ('machine', v4_url_for("v4_machine", id=machine.id))] %} +{% block head %} + + + +{% endblock %} + +{% block title %}Run Results{% endblock %} + +{% block body %} + +{% call v4_utils.v4_run_page(ts, machine, run, compare_to, neighboring_runs) %} + +{{ utils.render_popup_begin('view_options', 'View Options', true) }} + +Show Delta: +
+ +Show Previous Value: +
+ +Show Standard Deviation: +
+ +Show Median Absolute Deviation: +
+ +Show All Values: +
+ +Show All Samples: +
+ +Show Sample Counts: +
+ +Number of Comparison Runs: +
+ +Show Report Graphs: +
+ +Show Data Table: +
+ +Hide Report By Default: +
+ +Test Filter (regexp): +
+ + + +{{ utils.render_popup_end() }} + +{{ utils.render_popup_begin('text_report', 'Report (Text)', true) }} +

{{ text_report }}

+{{ utils.render_popup_end() }} + +{{ utils.render_popup_begin('html_report', 'Report (HTML)', + options.hide_report_by_default) }} +{{html_report|safe}} +{{ utils.render_popup_end() }} + +{% endcall %} + +{% endblock %} Added: zorg/trunk/lnt/lnt/server/ui/templates/v4_utils.html URL: http://llvm.org/viewvc/llvm-project/zorg/trunk/lnt/lnt/server/ui/templates/v4_utils.html?rev=147082&view=auto ============================================================================== --- zorg/trunk/lnt/lnt/server/ui/templates/v4_utils.html (added) +++ zorg/trunk/lnt/lnt/server/ui/templates/v4_utils.html Wed Dec 21 14:00:28 2011 @@ -0,0 +1,113 @@ +{% import "utils.html" as utils %} + +{% macro v4_run_page(ts, machine, run, compare_to, neighboring_runs) %} + + +

Name	Value
{{key}}

+ + + + + + +{# FIXME: Don't hard code field name. #} + + +{% if compare_to %} + + +{# FIXME: Don't hard code field name. #} + + +{% endif %} +

Machine:	{{machine.name}}:{{machine.id}}
Run:	{{run.start_time}} ({{ + run.order.llvm_project_revision}})
Compare To:	{{compare_to.start_time}} ({{ + compare_to.order.llvm_project_revision}})

+ +

+ + + + + + +
+ Homepage +
Machine:
+ {{ + machine.name}}:{{machine.id}} +
Runs:
+
+ +{# Show a small number of neighboring runs. #} +{% for r in neighboring_runs %} +
{{ "
"|safe if r.id == run.id }} + {{ + r.start_time}}{{ + "
"|safe if r.id == run.id }} +{% endfor %} +
+ + + + + + + + + + +
Nickname {{machine.name}}
Machine ID {{machine.id}}
+{{ utils.render_popup_begin('machine_info', 'Machine Info', true) }} +
Fields
+ +{% for item in machine.fields %} + + + + +{% endfor %} +
{{item.name}} {{machine.get_field(item)}}
+
Parameters
+ +{% for key,value in machine.parameters|dictsort %} + + + + +{% endfor %} +
{{key}} {{value}}
+{{ utils.render_popup_end() }} + +{{ utils.render_popup_begin('run_info', 'Run Info', true) }} +
Fields
+ + + + +{% for item in run.fields %} + + + + +{% endfor %} +
Name Value
{{item.name}} {{run.get_field(item)}}
+ +
Parameters
+ + + + +{% for key,value in run.parameters|dictsort %} + + + + +{% endfor %} +
Name Value
{{key}} {{value}}
+{{ utils.render_popup_end() }} +{{ caller() }} + +
+ +{% endmacro %} Modified: zorg/trunk/lnt/lnt/server/ui/views.py URL: http://llvm.org/viewvc/llvm-project/zorg/trunk/lnt/lnt/server/ui/views.py?rev=147082&r1=147081&r2=147082&view=diff ============================================================================== --- zorg/trunk/lnt/lnt/server/ui/views.py (original) +++ zorg/trunk/lnt/lnt/server/ui/views.py Wed Dec 21 14:00:28 2011 @@ -637,9 +637,72 @@ testsuite_name=g.testsuite_name, id=id, associated_runs=associated_runs) +def get_adjacent_runs_on_machine(ts, run, N): + prev_runs = [] + ordinal = run.order.ordinal - 1 + while ordinal >= 0 and (len(prev_runs) < N or + run.order.ordinal - ordinal < N): + # Find all the runs on this machine from the previous order. + prev_runs.extend(ts.query(ts.Run).\ + join(ts.Order).\ + filter(ts.Order.ordinal == ordinal).\ + filter(ts.Run.machine == run.machine)) + ordinal = ordinal - 1 + + next_runs = [] + ordinal = run.order.ordinal + 1 + # FIXME: This probably isn't a great way to limit our search, at least for + # SQLite which can't answer this quickly. + last_ordinal = ts.query(ts.Order).count() + while ordinal != last_ordinal and (len(next_runs) < N or + ordinal - run.order.ordinal < N): + # Find all the runs on this machine from the next order. + next_runs.extend(ts.query(ts.Run).\ + join(ts.Order).\ + filter(ts.Order.ordinal == ordinal).\ + filter(ts.Run.machine == run.machine)) + ordinal = ordinal + 1 + + return next_runs[::-1] + [run] + prev_runs + @v4_route("/") def v4_run(id): - return "run %d" % id + ts = request.get_testsuite() + run = ts.getRun(id) + + # Find the neighboring runs, by order. + neighboring_runs = get_adjacent_runs_on_machine(ts, run, N = 3) + + # Parse the view options. + options = {} + options['show_delta'] = bool(request.args.get('show_delta')) + options['show_previous'] = bool(request.args.get('show_previous')) + options['show_stddev'] = bool(request.args.get('show_stddev')) + options['show_mad'] = bool(request.args.get('show_mad')) + options['show_all'] = bool(request.args.get('show_all')) + options['show_all_samples'] = bool(request.args.get('show_all_samples')) + options['show_sample_counts'] = bool(request.args.get('show_sample_counts')) + options['show_graphs'] = show_graphs = bool(request.args.get('show_graphs')) + options['show_data_table'] = bool(request.args.get('show_data_table')) + options['hide_report_by_default'] = bool( + request.args.get('hide_report_by_default')) + try: + num_comparison_runs = int(request.args.get('num_comparison_runs')) + except: + num_comparison_runs = 10 + options['num_comparison_runs'] = num_comparison_runs + options['test_filter'] = test_filter_str = request.args.get( + 'test_filter', '') + if test_filter_str: + test_filter_re = re.compile(test_filter_str) + else: + test_filter_re = None + + # FIXME: Include when we have report functionality. + _, text_report, html_report = None, "", "" + + return render_template("v4_run.html", ts=ts, run=run, + options=options, neighboring_runs=neighboring_runs) @v4_route("/order/") def v4_order(ordinal): From daniel at zuster.org Wed Dec 21 14:00:32 2011 From: daniel at zuster.org (Daniel Dunbar) Date: Wed, 21 Dec 2011 20:00:32 -0000 Subject: [llvm-commits] [zorg] r147083 - in /zorg/trunk/lnt: lnt/util/ImportData.py tests/server/db/ImportV4TestSuiteInstance.py Message-ID: <20111221200033.07E6F2A6C12C@llvm.org> Author: ddunbar Date: Wed Dec 21 14:00:32 2011 New Revision: 147083 URL: http://llvm.org/viewvc/llvm-project?rev=147083&view=rev Log: [lnt/v0.4] lnt import: Update to maintain imported_from field. Modified: zorg/trunk/lnt/lnt/util/ImportData.py zorg/trunk/lnt/tests/server/db/ImportV4TestSuiteInstance.py Modified: zorg/trunk/lnt/lnt/util/ImportData.py URL: http://llvm.org/viewvc/llvm-project/zorg/trunk/lnt/lnt/util/ImportData.py?rev=147083&r1=147082&r2=147083&view=diff ============================================================================== --- zorg/trunk/lnt/lnt/util/ImportData.py (original) +++ zorg/trunk/lnt/lnt/util/ImportData.py Wed Dec 21 14:00:32 2011 @@ -68,6 +68,9 @@ result['error'] = "import failure: %s" % traceback.format_exc() return result + # If the import succeeded, save the import path. + run.imported_from = file + result['import_time'] = time.time() - importStartTime if not success: # Record the original run this is a duplicate of. Modified: zorg/trunk/lnt/tests/server/db/ImportV4TestSuiteInstance.py URL: http://llvm.org/viewvc/llvm-project/zorg/trunk/lnt/tests/server/db/ImportV4TestSuiteInstance.py?rev=147083&r1=147082&r2=147083&view=diff ============================================================================== --- zorg/trunk/lnt/tests/server/db/ImportV4TestSuiteInstance.py (original) +++ zorg/trunk/lnt/tests/server/db/ImportV4TestSuiteInstance.py Wed Dec 21 14:00:32 2011 @@ -89,9 +89,8 @@ assert run_b.machine is machine assert run_a.order is order_a assert run_b.order is order_b -# FIXME: Set imported_from correctly. -assert run_a.imported_from is None -assert run_b.imported_from is None +assert run_a.imported_from.endswith("sample-a-small.plist") +assert run_b.imported_from.endswith("sample-b-small.plist") assert run_a.start_time == datetime.datetime(2009, 11, 17, 2, 12, 25) assert run_a.end_time == datetime.datetime(2009, 11, 17, 3, 44, 48) assert not run_a.parameters From nicholas at mxc.ca Wed Dec 21 14:03:50 2011 From: nicholas at mxc.ca (Nick Lewycky) Date: Wed, 21 Dec 2011 12:03:50 -0800 Subject: [llvm-commits] [llvm] r147037 - /llvm/trunk/lib/Analysis/InlineCost.cpp In-Reply-To: References: <20111221060630.8F5FD2A6C12C@llvm.org> Message-ID: <4EF23BA6.4090009@mxc.ca> On 12/21/2011 10:04 AM, Jakob Stoklund Olesen wrote: > > On Dec 20, 2011, at 10:06 PM, Nick Lewycky wrote: > >> Author: nicholas >> Date: Wed Dec 21 00:06:30 2011 >> New Revision: 147037 >> >> URL: http://llvm.org/viewvc/llvm-project?rev=147037&view=rev >> Log: >> A call to a function marked 'noinline' is not an inline candidate. The sole >> call site of an intrinsic is also not an inline candidate. While here, make it >> more obvious that this code ignores all intrinsics. Noticed by inspection! >> >> Modified: >> llvm/trunk/lib/Analysis/InlineCost.cpp >> >> Modified: llvm/trunk/lib/Analysis/InlineCost.cpp >> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/InlineCost.cpp?rev=147037&r1=147036&r2=147037&view=diff >> ============================================================================== >> --- llvm/trunk/lib/Analysis/InlineCost.cpp (original) >> +++ llvm/trunk/lib/Analysis/InlineCost.cpp Wed Dec 21 00:06:30 2011 >> @@ -63,8 +63,8 @@ >> >> // Special handling for calls. >> if (isa(II) || isa(II)) { >> - if (isa(II)) >> - continue; // Debug intrinsics don't count as size. >> + if (isa(II)) >> + continue; // Intrinsics have no argument setup and can't be inlined. > > This change doesn't make sense. You are skipping a lot more loop below this continue, effectively ignoring all intrinsics. > > The code did /not/ ignore intrinsics before. You are correct! Sorry, I'll go back and fix this properly, thanks for the review! Nick From daniel at zuster.org Wed Dec 21 14:00:35 2011 From: daniel at zuster.org (Daniel Dunbar) Date: Wed, 21 Dec 2011 20:00:35 -0000 Subject: [llvm-commits] [zorg] r147084 - /zorg/trunk/lnt/docs/todo.rst Message-ID: <20111221200035.789152A6C12C@llvm.org> Author: ddunbar Date: Wed Dec 21 14:00:35 2011 New Revision: 147084 URL: http://llvm.org/viewvc/llvm-project?rev=147084&view=rev Log: lnt/docs: Minor TODO notes on testing of LNT itself. Modified: zorg/trunk/lnt/docs/todo.rst Modified: zorg/trunk/lnt/docs/todo.rst URL: http://llvm.org/viewvc/llvm-project/zorg/trunk/lnt/docs/todo.rst?rev=147084&r1=147083&r2=147084&view=diff ============================================================================== --- zorg/trunk/lnt/docs/todo.rst (original) +++ zorg/trunk/lnt/docs/todo.rst Wed Dec 21 14:00:35 2011 @@ -42,6 +42,11 @@ o Could benefit from finding a way to have LNT VACUUM, although this can be very expensive. + 2. We should get an LNT buildbot up somewhere. + + 3. We should start defining performance tests for LNT itself, and have LNT + monitor them (of course). Probably best integrated into the LNT buildbot. + v0.4 Redesign ------------- From daniel at zuster.org Wed Dec 21 14:00:43 2011 From: daniel at zuster.org (Daniel Dunbar) Date: Wed, 21 Dec 2011 20:00:43 -0000 Subject: [llvm-commits] [zorg] r147086 - in /zorg/trunk/lnt/lnt: server/ui/templates/v4_order.html server/ui/templates/v4_run.html server/ui/views.py util/NTEmailReport.py Message-ID: <20111221200043.698502A6C12E@llvm.org> Author: ddunbar Date: Wed Dec 21 14:00:42 2011 New Revision: 147086 URL: http://llvm.org/viewvc/llvm-project?rev=147086&view=rev Log: [lnt/v0.4]: lnt.server.ui/v4: Implement UI access to reports (which themselves still aren't implemented). Modified: zorg/trunk/lnt/lnt/server/ui/templates/v4_order.html zorg/trunk/lnt/lnt/server/ui/templates/v4_run.html zorg/trunk/lnt/lnt/server/ui/views.py zorg/trunk/lnt/lnt/util/NTEmailReport.py Modified: zorg/trunk/lnt/lnt/server/ui/templates/v4_order.html URL: http://llvm.org/viewvc/llvm-project/zorg/trunk/lnt/lnt/server/ui/templates/v4_order.html?rev=147086&r1=147085&r2=147086&view=diff ============================================================================== --- zorg/trunk/lnt/lnt/server/ui/templates/v4_order.html (original) +++ zorg/trunk/lnt/lnt/server/ui/templates/v4_order.html Wed Dec 21 14:00:42 2011 @@ -17,6 +17,10 @@ + ID + {{order.id}} + + Ordinal {{order.ordinal}} Modified: zorg/trunk/lnt/lnt/server/ui/templates/v4_run.html URL: http://llvm.org/viewvc/llvm-project/zorg/trunk/lnt/lnt/server/ui/templates/v4_run.html?rev=147086&r1=147085&r2=147086&view=diff ============================================================================== --- zorg/trunk/lnt/lnt/server/ui/templates/v4_run.html (original) +++ zorg/trunk/lnt/lnt/server/ui/templates/v4_run.html Wed Dec 21 14:00:42 2011 @@ -9,7 +9,6 @@ {% block head %} - {% endblock %} {% block title %}Run Results{% endblock %} Modified: zorg/trunk/lnt/lnt/server/ui/views.py URL: http://llvm.org/viewvc/llvm-project/zorg/trunk/lnt/lnt/server/ui/views.py?rev=147086&r1=147085&r2=147086&view=diff ============================================================================== --- zorg/trunk/lnt/lnt/server/ui/views.py (original) +++ zorg/trunk/lnt/lnt/server/ui/views.py Wed Dec 21 14:00:42 2011 @@ -14,6 +14,7 @@ from flask import url_for from lnt.db import perfdb +from lnt.server.ui.globals import v4_url_for frontend = flask.Module(__name__) @@ -665,8 +666,35 @@ return next_runs[::-1] + [run] + prev_runs + at v4_route("//report") +def v4_report(id): + db = request.get_db() + ts = request.get_testsuite() + run = ts.getRun(id) + + _, _, html_report = NTEmailReport.getReport( + result=None, db=db, run=run, baseurl=v4_url_for('index'), + was_added=True, will_commit=True, only_html_body=False) + + return make_response(html_report) + + at v4_route("//text_report") +def v4_text_report(id): + db = request.get_db() + ts = request.get_testsuite() + run = ts.getRun(id) + + _, text_report, _ = NTEmailReport.getReport( + result=None, db=db, run=run, baseurl=v4_url_for('index'), + was_added=True, will_commit=True, only_html_body=True) + + response = make_response(text_report) + response.mimetype = "text/plain" + return response + @v4_route("/") def v4_run(id): + db = request.get_db() ts = request.get_testsuite() run = ts.getRun(id) @@ -698,11 +726,17 @@ else: test_filter_re = None - # FIXME: Include when we have report functionality. - _, text_report, html_report = None, "", "" + # Generate the report for inclusion in the run page. + # + # FIXME: This is a crummy implementation of the concept that we want the + # webapp UI to be easy to correlate with the email reports. + _, text_report, html_report = NTEmailReport.getReport( + result=None, db=db, run=run, baseurl=v4_url_for('index'), + was_added=True, will_commit=True, only_html_body=True) return render_template("v4_run.html", ts=ts, run=run, - options=options, neighboring_runs=neighboring_runs) + options=options, neighboring_runs=neighboring_runs, + text_report=text_report, html_report=html_report) @v4_route("/order/") def v4_order(ordinal): Modified: zorg/trunk/lnt/lnt/util/NTEmailReport.py URL: http://llvm.org/viewvc/llvm-project/zorg/trunk/lnt/lnt/util/NTEmailReport.py?rev=147086&r1=147085&r2=147086&view=diff ============================================================================== --- zorg/trunk/lnt/lnt/util/NTEmailReport.py (original) +++ zorg/trunk/lnt/lnt/util/NTEmailReport.py Wed Dec 21 14:00:42 2011 @@ -462,7 +462,8 @@ return subject, report.getvalue(), html_report -def getReport(result, db, run, baseurl, was_added, will_commit): +def getReport(result, db, run, baseurl, was_added, will_commit, + only_html_body = False): report = StringIO.StringIO() # We haven't implemented V4DB support yet in reports. @@ -472,7 +473,8 @@ # Use a simple report unless the tag indicates this is an old style nightly # test run. if 'tag' in run.info and run.info['tag'].value != 'nightlytest': - return getSimpleReport(result, db, run, baseurl, was_added, will_commit) + return getSimpleReport(result, db, run, baseurl, was_added, will_commit, + only_html_body) machine = run.machine compareTo = None From daniel at zuster.org Wed Dec 21 14:00:39 2011 From: daniel at zuster.org (Daniel Dunbar) Date: Wed, 21 Dec 2011 20:00:39 -0000 Subject: [llvm-commits] [zorg] r147085 - in /zorg/trunk/lnt/lnt/server/ui: app.py globals.py Message-ID: <20111221200039.10DC72A6C12D@llvm.org> Author: ddunbar Date: Wed Dec 21 14:00:38 2011 New Revision: 147085 URL: http://llvm.org/viewvc/llvm-project?rev=147085&view=rev Log: [lnt/v0.4]: Factor Jinja global extensions out into a separate module. Added: zorg/trunk/lnt/lnt/server/ui/globals.py Modified: zorg/trunk/lnt/lnt/server/ui/app.py Modified: zorg/trunk/lnt/lnt/server/ui/app.py URL: http://llvm.org/viewvc/llvm-project/zorg/trunk/lnt/lnt/server/ui/app.py?rev=147085&r1=147084&r2=147085&view=diff ============================================================================== --- zorg/trunk/lnt/lnt/server/ui/app.py (original) +++ zorg/trunk/lnt/lnt/server/ui/app.py Wed Dec 21 14:00:38 2011 @@ -11,6 +11,7 @@ import lnt import lnt.server.config import lnt.server.ui.filters +import lnt.server.ui.globals import lnt.server.ui.views import lnt.server.db.v4db @@ -69,20 +70,6 @@ def get_db_summary(self): return current_app.get_db_summary(g.db_name, self.get_db()) -def db_url_for(*args, **kwargs): - """ - Like url_for, but handles automatically providing the db_name argument. - """ - return url_for(*args, db_name=g.db_name, **kwargs) - -def v4_url_for(*args, **kwargs): - """ - Like url_for, but handles automatically providing the db_name and - testsuite_name arguments. - """ - return url_for(*args, db_name=g.db_name, testsuite_name=g.testsuite_name, - **kwargs) - class App(flask.Flask): @staticmethod def create_standalone(config_path): @@ -124,11 +111,11 @@ self.jinja_env.globals.update( app=current_app, - db_url_for=db_url_for, - v4_url_for=v4_url_for, perfdb=perfdb, old_config=self.old_config) + lnt.server.ui.globals.register(self) + def get_db_summary(self, db_name, db): # FIXME/v3removal: Eliminate this, V4DB style has no need for summary # abstraction. Added: zorg/trunk/lnt/lnt/server/ui/globals.py URL: http://llvm.org/viewvc/llvm-project/zorg/trunk/lnt/lnt/server/ui/globals.py?rev=147085&view=auto ============================================================================== --- zorg/trunk/lnt/lnt/server/ui/globals.py (added) +++ zorg/trunk/lnt/lnt/server/ui/globals.py Wed Dec 21 14:00:38 2011 @@ -0,0 +1,24 @@ +""" +Module for defining additional Jinja global functions. +""" + +import flask + +def db_url_for(*args, **kwargs): + """ + Like url_for, but handles automatically providing the db_name argument. + """ + return flask.url_for(*args, db_name=flask.g.db_name, **kwargs) + +def v4_url_for(*args, **kwargs): + """ + Like url_for, but handles automatically providing the db_name and + testsuite_name arguments. + """ + return flask.url_for(*args, db_name=flask.g.db_name, + testsuite_name=flask.g.testsuite_name, **kwargs) + +def register(app): + app.jinja_env.globals.update( + db_url_for=db_url_for, + v4_url_for=v4_url_for) From rafael.espindola at gmail.com Wed Dec 21 14:09:46 2011 From: rafael.espindola at gmail.com (Rafael Espindola) Date: Wed, 21 Dec 2011 20:09:46 -0000 Subject: [llvm-commits] [llvm] r147087 - in /llvm/trunk/lib/MC: ELFObjectWriter.cpp ELFObjectWriter.h Message-ID: <20111221200946.6DBBA2A6C12C@llvm.org> Author: rafael Date: Wed Dec 21 14:09:46 2011 New Revision: 147087 URL: http://llvm.org/viewvc/llvm-project?rev=147087&view=rev Log: Switch from WriteEFlags to getEFlags in preparation for moving it to Target/. Modified: llvm/trunk/lib/MC/ELFObjectWriter.cpp llvm/trunk/lib/MC/ELFObjectWriter.h Modified: llvm/trunk/lib/MC/ELFObjectWriter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/ELFObjectWriter.cpp?rev=147087&r1=147086&r2=147087&view=diff ============================================================================== --- llvm/trunk/lib/MC/ELFObjectWriter.cpp (original) +++ llvm/trunk/lib/MC/ELFObjectWriter.cpp Wed Dec 21 14:09:46 2011 @@ -108,7 +108,7 @@ sizeof(ELF::Elf32_Ehdr))); // e_shoff = sec hdr table off in bytes // e_flags = whatever the target wants - WriteEFlags(); + Write32(getEFlags()); // e_ehsize = ELF header size Write16(is64Bit() ? sizeof(ELF::Elf64_Ehdr) : sizeof(ELF::Elf32_Ehdr)); @@ -1296,8 +1296,8 @@ {} // FIXME: get the real EABI Version from the Triple. -void ARMELFObjectWriter::WriteEFlags() { - Write32(ELF::EF_ARM_EABIMASK & DefaultEABIVersion); +unsigned ARMELFObjectWriter::getEFlags() { + return ELF::EF_ARM_EABIMASK & DefaultEABIVersion; } // In ARM, _MergedGlobals and other most symbols get emitted directly. @@ -1646,9 +1646,8 @@ MipsELFObjectWriter::~MipsELFObjectWriter() {} // FIXME: get the real EABI Version from the Triple. -void MipsELFObjectWriter::WriteEFlags() { - Write32(ELF::EF_MIPS_NOREORDER | - ELF::EF_MIPS_ARCH_32R2); +unsigned MipsELFObjectWriter::getEFlags() { + return ELF::EF_MIPS_NOREORDER | ELF::EF_MIPS_ARCH_32R2; } const MCSymbol *MipsELFObjectWriter::ExplicitRelSym(const MCAssembler &Asm, Modified: llvm/trunk/lib/MC/ELFObjectWriter.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/ELFObjectWriter.h?rev=147087&r1=147086&r2=147087&view=diff ============================================================================== --- llvm/trunk/lib/MC/ELFObjectWriter.h (original) +++ llvm/trunk/lib/MC/ELFObjectWriter.h Wed Dec 21 14:09:46 2011 @@ -244,7 +244,7 @@ unsigned NumberOfSections); /// Default e_flags = 0 - virtual void WriteEFlags() { Write32(0); } + virtual unsigned getEFlags() { return 0; } virtual void WriteSymbolEntry(MCDataFragment *SymtabF, MCDataFragment *ShndxF, @@ -369,7 +369,7 @@ virtual ~ARMELFObjectWriter(); - virtual void WriteEFlags(); + virtual unsigned getEFlags(); protected: virtual const MCSymbol *ExplicitRelSym(const MCAssembler &Asm, const MCValue &Target, @@ -425,7 +425,7 @@ bool IsLittleEndian); virtual ~MipsELFObjectWriter(); - virtual void WriteEFlags(); + virtual unsigned getEFlags(); protected: virtual const MCSymbol *ExplicitRelSym(const MCAssembler &Asm, From lhames at gmail.com Wed Dec 21 14:12:55 2011 From: lhames at gmail.com (Lang Hames) Date: Wed, 21 Dec 2011 20:12:55 -0000 Subject: [llvm-commits] [llvm] r147088 - /llvm/trunk/lib/CodeGen/LiveIntervalUnion.h Message-ID: <20111221201255.0EB092A6C12C@llvm.org> Author: lhames Date: Wed Dec 21 14:12:54 2011 New Revision: 147088 URL: http://llvm.org/viewvc/llvm-project?rev=147088&view=rev Log: Remove disused STL header include. Modified: llvm/trunk/lib/CodeGen/LiveIntervalUnion.h Modified: llvm/trunk/lib/CodeGen/LiveIntervalUnion.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/LiveIntervalUnion.h?rev=147088&r1=147087&r2=147088&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/LiveIntervalUnion.h (original) +++ llvm/trunk/lib/CodeGen/LiveIntervalUnion.h Wed Dec 21 14:12:54 2011 @@ -20,8 +20,6 @@ #include "llvm/ADT/IntervalMap.h" #include "llvm/CodeGen/LiveInterval.h" -#include - namespace llvm { class MachineLoopRange; From lhames at gmail.com Wed Dec 21 14:16:11 2011 From: lhames at gmail.com (Lang Hames) Date: Wed, 21 Dec 2011 20:16:11 -0000 Subject: [llvm-commits] [llvm] r147089 - /llvm/trunk/lib/CodeGen/LiveIntervalUnion.cpp Message-ID: <20111221201611.ACFC92A6C12C@llvm.org> Author: lhames Date: Wed Dec 21 14:16:11 2011 New Revision: 147089 URL: http://llvm.org/viewvc/llvm-project?rev=147089&view=rev Log: Oops - LiveIntervalUnion.cpp file does use std::find. Moving STL header include to LiveIntervalUnion.cpp file. Modified: llvm/trunk/lib/CodeGen/LiveIntervalUnion.cpp Modified: llvm/trunk/lib/CodeGen/LiveIntervalUnion.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/LiveIntervalUnion.cpp?rev=147089&r1=147088&r2=147089&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/LiveIntervalUnion.cpp (original) +++ llvm/trunk/lib/CodeGen/LiveIntervalUnion.cpp Wed Dec 21 14:16:11 2011 @@ -21,6 +21,8 @@ #include "llvm/Support/raw_ostream.h" #include "llvm/Target/TargetRegisterInfo.h" +#include + using namespace llvm; From kubastaszak at gmail.com Wed Dec 21 14:18:54 2011 From: kubastaszak at gmail.com (Jakub Staszak) Date: Wed, 21 Dec 2011 20:18:54 -0000 Subject: [llvm-commits] [llvm] r147090 - /llvm/trunk/lib/CodeGen/MachineBlockPlacement.cpp Message-ID: <20111221201854.521D02A6C12C@llvm.org> Author: kuba Date: Wed Dec 21 14:18:54 2011 New Revision: 147090 URL: http://llvm.org/viewvc/llvm-project?rev=147090&view=rev Log: - Change a few operator[] to lookup which is cheaper. - Add some constantness. Modified: llvm/trunk/lib/CodeGen/MachineBlockPlacement.cpp Modified: llvm/trunk/lib/CodeGen/MachineBlockPlacement.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineBlockPlacement.cpp?rev=147090&r1=147089&r2=147090&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/MachineBlockPlacement.cpp (original) +++ llvm/trunk/lib/CodeGen/MachineBlockPlacement.cpp Wed Dec 21 14:18:54 2011 @@ -116,7 +116,7 @@ /// a contiguous sequence of basic blocks, updating the edge list, and /// updating the block -> chain mapping. It does not free or tear down the /// old chain, but the old chain's block list is no longer valid. - void merge(MachineBasicBlock *BB, BlockChain *Chain) { + void merge(MachineBasicBlock *BB, const BlockChain *Chain) { assert(BB); assert(!Blocks.empty()); @@ -185,28 +185,27 @@ /// between basic blocks. DenseMap BlockToChain; - void markChainSuccessors(BlockChain &Chain, - MachineBasicBlock *LoopHeaderBB, + void markChainSuccessors(const BlockChain &Chain, + const MachineBasicBlock *LoopHeaderBB, SmallVectorImpl &BlockWorkList, - const BlockFilterSet *BlockFilter = 0); - MachineBasicBlock *selectBestSuccessor(MachineBasicBlock *BB, - BlockChain &Chain, - const BlockFilterSet *BlockFilter); + const BlockFilterSet *BlockFilter = 0) const; + MachineBasicBlock *selectBestSuccessor(const MachineBasicBlock *BB, + const BlockChain &Chain, const BlockFilterSet *BlockFilter) const; MachineBasicBlock *selectBestCandidateBlock( - BlockChain &Chain, SmallVectorImpl &WorkList, - const BlockFilterSet *BlockFilter); + const BlockChain &Chain, SmallVectorImpl &WorkList, + const BlockFilterSet *BlockFilter) const; MachineBasicBlock *getFirstUnplacedBlock( MachineFunction &F, const BlockChain &PlacedChain, MachineFunction::iterator &PrevUnplacedBlockIt, - const BlockFilterSet *BlockFilter); + const BlockFilterSet *BlockFilter) const; void buildChain(MachineBasicBlock *BB, BlockChain &Chain, SmallVectorImpl &BlockWorkList, - const BlockFilterSet *BlockFilter = 0); + const BlockFilterSet *BlockFilter = 0) const; MachineBasicBlock *findBestLoopTop(MachineFunction &F, MachineLoop &L, - const BlockFilterSet &LoopBlockSet); - void buildLoopChains(MachineFunction &F, MachineLoop &L); + const BlockFilterSet &LoopBlockSet) const; + void buildLoopChains(MachineFunction &F, MachineLoop &L) const; void buildCFGChains(MachineFunction &F); void AlignLoops(MachineFunction &F); @@ -246,7 +245,7 @@ /// \brief Helper to print the name of a MBB. /// /// Only used by debug logging. -static std::string getBlockName(MachineBasicBlock *BB) { +static std::string getBlockName(const MachineBasicBlock *BB) { std::string Result; raw_string_ostream OS(Result); OS << "BB#" << BB->getNumber() @@ -258,7 +257,7 @@ /// \brief Helper to print the number of a MBB. /// /// Only used by debug logging. -static std::string getBlockNum(MachineBasicBlock *BB) { +static std::string getBlockNum(const MachineBasicBlock *BB) { std::string Result; raw_string_ostream OS(Result); OS << "BB#" << BB->getNumber(); @@ -274,10 +273,10 @@ /// having one fewer active predecessor. It also adds any successors of this /// chain which reach the zero-predecessor state to the worklist passed in. void MachineBlockPlacement::markChainSuccessors( - BlockChain &Chain, - MachineBasicBlock *LoopHeaderBB, + const BlockChain &Chain, + const MachineBasicBlock *LoopHeaderBB, SmallVectorImpl &BlockWorkList, - const BlockFilterSet *BlockFilter) { + const BlockFilterSet *BlockFilter) const { // Walk all the blocks in this chain, marking their successors as having // a predecessor placed. for (BlockChain::iterator CBI = Chain.begin(), CBE = Chain.end(); @@ -291,7 +290,7 @@ SI != SE; ++SI) { if (BlockFilter && !BlockFilter->count(*SI)) continue; - BlockChain &SuccChain = *BlockToChain[*SI]; + BlockChain &SuccChain = *BlockToChain.lookup(*SI); // Disregard edges within a fixed chain, or edges to the loop header. if (&Chain == &SuccChain || *SI == LoopHeaderBB) continue; @@ -314,8 +313,8 @@ /// /// \returns The best successor block found, or null if none are viable. MachineBasicBlock *MachineBlockPlacement::selectBestSuccessor( - MachineBasicBlock *BB, BlockChain &Chain, - const BlockFilterSet *BlockFilter) { + const MachineBasicBlock *BB, const BlockChain &Chain, + const BlockFilterSet *BlockFilter) const { const BranchProbability HotProb(4, 5); // 80% MachineBasicBlock *BestSucc = 0; @@ -329,12 +328,11 @@ uint32_t WeightScale = 0; uint32_t SumWeight = MBPI->getSumForBlock(BB, WeightScale); DEBUG(dbgs() << "Attempting merge from: " << getBlockName(BB) << "\n"); - for (MachineBasicBlock::succ_iterator SI = BB->succ_begin(), - SE = BB->succ_end(); - SI != SE; ++SI) { + for (MachineBasicBlock::const_succ_iterator SI = BB->succ_begin(), + SE = BB->succ_end(); SI != SE; ++SI) { if (BlockFilter && !BlockFilter->count(*SI)) continue; - BlockChain &SuccChain = *BlockToChain[*SI]; + const BlockChain &SuccChain = *BlockToChain.lookup(*SI); if (&SuccChain == &Chain) { DEBUG(dbgs() << " " << getBlockName(*SI) << " -> Already merged!\n"); continue; @@ -364,7 +362,7 @@ PE = (*SI)->pred_end(); PI != PE; ++PI) { if (*PI == *SI || (BlockFilter && !BlockFilter->count(*PI)) || - BlockToChain[*PI] == &Chain) + BlockToChain.lookup(*PI) == &Chain) continue; BlockFrequency PredEdgeFreq = MBFI->getBlockFreq(*PI) * MBPI->getEdgeProbability(*PI, *SI); @@ -420,8 +418,8 @@ /// /// \returns The best block found, or null if none are viable. MachineBasicBlock *MachineBlockPlacement::selectBestCandidateBlock( - BlockChain &Chain, SmallVectorImpl &WorkList, - const BlockFilterSet *BlockFilter) { + const BlockChain &Chain, SmallVectorImpl &WorkList, + const BlockFilterSet *BlockFilter) const { // Once we need to walk the worklist looking for a candidate, cleanup the // worklist of already placed entries. // FIXME: If this shows up on profiles, it could be folded (at the cost of @@ -436,7 +434,7 @@ WBE = WorkList.end(); WBI != WBE; ++WBI) { assert(!BlockFilter || BlockFilter->count(*WBI)); - BlockChain &SuccChain = *BlockToChain[*WBI]; + const BlockChain &SuccChain = *BlockToChain.lookup(*WBI); if (&SuccChain == &Chain) { DEBUG(dbgs() << " " << getBlockName(*WBI) << " -> Already merged!\n"); @@ -465,17 +463,17 @@ MachineBasicBlock *MachineBlockPlacement::getFirstUnplacedBlock( MachineFunction &F, const BlockChain &PlacedChain, MachineFunction::iterator &PrevUnplacedBlockIt, - const BlockFilterSet *BlockFilter) { + const BlockFilterSet *BlockFilter) const { for (MachineFunction::iterator I = PrevUnplacedBlockIt, E = F.end(); I != E; ++I) { if (BlockFilter && !BlockFilter->count(I)) continue; - if (BlockToChain[I] != &PlacedChain) { + if (BlockToChain.lookup(I) != &PlacedChain) { PrevUnplacedBlockIt = I; // Now select the head of the chain to which the unplaced block belongs // as the block to place. This will force the entire chain to be placed, // and satisfies the requirements of merging chains. - return *BlockToChain[I]->begin(); + return *BlockToChain.lookup(I)->begin(); } } return 0; @@ -485,9 +483,9 @@ MachineBasicBlock *BB, BlockChain &Chain, SmallVectorImpl &BlockWorkList, - const BlockFilterSet *BlockFilter) { + const BlockFilterSet *BlockFilter) const { assert(BB); - assert(BlockToChain[BB] == &Chain); + assert(BlockToChain.lookup(BB) == &Chain); MachineFunction &F = *BB->getParent(); MachineFunction::iterator PrevUnplacedBlockIt = F.begin(); @@ -496,7 +494,7 @@ BB = *llvm::prior(Chain.end()); for (;;) { assert(BB); - assert(BlockToChain[BB] == &Chain); + assert(BlockToChain.lookup(BB) == &Chain); assert(*llvm::prior(Chain.end()) == BB); MachineBasicBlock *BestSucc = 0; @@ -521,7 +519,7 @@ } // Place this block, updating the datastructures to reflect its placement. - BlockChain &SuccChain = *BlockToChain[BestSucc]; + BlockChain &SuccChain = *BlockToChain.lookup(BestSucc); // Zero out LoopPredecessors for the successor we're about to merge in case // we selected a successor that didn't fit naturally into the CFG. SuccChain.LoopPredecessors = 0; @@ -544,7 +542,7 @@ MachineBasicBlock * MachineBlockPlacement::findBestLoopTop(MachineFunction &F, MachineLoop &L, - const BlockFilterSet &LoopBlockSet) { + const BlockFilterSet &LoopBlockSet) const { BlockFrequency BestExitEdgeFreq; MachineBasicBlock *ExitingBB = 0; MachineBasicBlock *LoopingBB = 0; @@ -558,7 +556,7 @@ for (MachineLoop::block_iterator I = L.block_begin(), E = L.block_end(); I != E; ++I) { - BlockChain &Chain = *BlockToChain[*I]; + const BlockChain &Chain = *BlockToChain.lookup(*I); // Ensure that this block is at the end of a chain; otherwise it could be // mid-way through an inner loop or a successor of an analyzable branch. if (*I != *llvm::prior(Chain.end())) @@ -588,7 +586,7 @@ continue; if (*SI == *I) continue; - BlockChain &SuccChain = *BlockToChain[*SI]; + const BlockChain &SuccChain = *BlockToChain.lookup(*SI); // Don't split chains, either this chain or the successor's chain. if (&Chain == &SuccChain || *SI != *SuccChain.begin()) { DEBUG(dbgs() << " " << (LoopBlockSet.count(*SI) ? "looping: " @@ -665,7 +663,7 @@ /// both preserves the topological structure and minimizes taken conditional /// branches. void MachineBlockPlacement::buildLoopChains(MachineFunction &F, - MachineLoop &L) { + MachineLoop &L) const { // First recurse through any nested loops, building chains for those inner // loops. for (MachineLoop::iterator LI = L.begin(), LE = L.end(); LI != LE; ++LI) @@ -675,29 +673,29 @@ BlockFilterSet LoopBlockSet(L.block_begin(), L.block_end()); MachineBasicBlock *LayoutTop = findBestLoopTop(F, L, LoopBlockSet); - BlockChain &LoopChain = *BlockToChain[LayoutTop]; + BlockChain &LoopChain = *BlockToChain.lookup(LayoutTop); // FIXME: This is a really lame way of walking the chains in the loop: we // walk the blocks, and use a set to prevent visiting a particular chain // twice. - SmallPtrSet UpdatedPreds; + SmallPtrSet UpdatedPreds; assert(LoopChain.LoopPredecessors == 0); UpdatedPreds.insert(&LoopChain); for (MachineLoop::block_iterator BI = L.block_begin(), BE = L.block_end(); BI != BE; ++BI) { - BlockChain &Chain = *BlockToChain[*BI]; + BlockChain &Chain = *BlockToChain.lookup(*BI); if (!UpdatedPreds.insert(&Chain)) continue; assert(Chain.LoopPredecessors == 0); for (BlockChain::iterator BCI = Chain.begin(), BCE = Chain.end(); BCI != BCE; ++BCI) { - assert(BlockToChain[*BCI] == &Chain); + assert(BlockToChain.lookup(*BCI) == &Chain); for (MachineBasicBlock::pred_iterator PI = (*BCI)->pred_begin(), PE = (*BCI)->pred_end(); PI != PE; ++PI) { - if (BlockToChain[*PI] == &Chain || !LoopBlockSet.count(*PI)) + if (BlockToChain.lookup(*PI) == &Chain || !LoopBlockSet.count(*PI)) continue; ++Chain.LoopPredecessors; } From nicholas at mxc.ca Wed Dec 21 14:21:55 2011 From: nicholas at mxc.ca (Nick Lewycky) Date: Wed, 21 Dec 2011 20:21:55 -0000 Subject: [llvm-commits] [llvm] r147092 - /llvm/trunk/lib/Analysis/InlineCost.cpp Message-ID: <20111221202155.C24E52A6C12C@llvm.org> Author: nicholas Date: Wed Dec 21 14:21:55 2011 New Revision: 147092 URL: http://llvm.org/viewvc/llvm-project?rev=147092&view=rev Log: Fix typo and spacing, no functionality change. Modified: llvm/trunk/lib/Analysis/InlineCost.cpp Modified: llvm/trunk/lib/Analysis/InlineCost.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/InlineCost.cpp?rev=147092&r1=147091&r2=147092&view=diff ============================================================================== --- llvm/trunk/lib/Analysis/InlineCost.cpp (original) +++ llvm/trunk/lib/Analysis/InlineCost.cpp Wed Dec 21 14:21:55 2011 @@ -138,7 +138,7 @@ // FIXME: This logic isn't really right; we can safely inline functions // with indirectbr's as long as no other function or global references the // blockaddress of a block within the current function. And as a QOI issue, - // if someone is using a blockaddress wihtout an indirectbr, and that + // if someone is using a blockaddress without an indirectbr, and that // reference somehow ends up in another function or global, we probably // don't want to inline this function. if (isa(BB->getTerminator())) @@ -422,7 +422,7 @@ InlineCost += CalleeFI->Metrics.NumCalls * InlineConstants::CallPenalty; // Look at the size of the callee. Each instruction counts as 5. - InlineCost += CalleeFI->Metrics.NumInsts*InlineConstants::InstrCost; + InlineCost += CalleeFI->Metrics.NumInsts * InlineConstants::InstrCost; return InlineCost; } From nicholas at mxc.ca Wed Dec 21 14:26:04 2011 From: nicholas at mxc.ca (Nick Lewycky) Date: Wed, 21 Dec 2011 20:26:04 -0000 Subject: [llvm-commits] [llvm] r147093 - /llvm/trunk/lib/Analysis/InlineCost.cpp Message-ID: <20111221202604.24C7F2A6C12C@llvm.org> Author: nicholas Date: Wed Dec 21 14:26:03 2011 New Revision: 147093 URL: http://llvm.org/viewvc/llvm-project?rev=147093&view=rev Log: Continue counting intrinsics as instructions (except when they aren't, such as debug info) and for being vector operations. Fixes regression from r147037. Modified: llvm/trunk/lib/Analysis/InlineCost.cpp Modified: llvm/trunk/lib/Analysis/InlineCost.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/InlineCost.cpp?rev=147093&r1=147092&r2=147093&view=diff ============================================================================== --- llvm/trunk/lib/Analysis/InlineCost.cpp (original) +++ llvm/trunk/lib/Analysis/InlineCost.cpp Wed Dec 21 14:26:03 2011 @@ -63,8 +63,22 @@ // Special handling for calls. if (isa(II) || isa(II)) { - if (isa(II)) - continue; // Intrinsics have no argument setup and can't be inlined. + if (const IntrinsicInst *IntrinsicI = dyn_cast(II)) { + switch (IntrinsicI->getIntrinsicID()) { + default: break; + case Intrinsic::dbg_declare: + case Intrinsic::dbg_value: + case Intrinsic::invariant_start: + case Intrinsic::invariant_end: + case Intrinsic::lifetime_start: + case Intrinsic::lifetime_end: + case Intrinsic::objectsize: + case Intrinsic::ptr_annotation: + case Intrinsic::var_annotation: + // These intrinsics don't count as size. + continue; + } + } ImmutableCallSite CS(cast(II)); @@ -83,7 +97,7 @@ isRecursive = true; } - if (!callIsSmall(CS.getCalledFunction())) { + if (!isa(II) && !callIsSmall(CS.getCalledFunction())) { // Each argument to a call takes on average one instruction to set up. NumInsts += CS.arg_size(); From hfinkel at anl.gov Wed Dec 21 14:36:14 2011 From: hfinkel at anl.gov (Hal Finkel) Date: Wed, 21 Dec 2011 14:36:14 -0600 Subject: [llvm-commits] [PATCH] Allow SelectionDAGBuilder to reorder loads past stores In-Reply-To: <1324475397.31367.527.camel@sapling> References: <1324316529.31367.96.camel@sapling> <945273C4-D0AA-4CAF-B0ED-C6D96A52FE02@apple.com> <1324325951.31367.178.camel@sapling> <1324355462.31367.287.camel@sapling> <2264DB7F-F14F-4D93-B6C1-79D69B5F2DBF@apple.com> <1324401740.31367.437.camel@sapling> <4B06FCD2-5607-4F5A-989E-C961B6DD6FE4@2pi.dk> <1324407129.31367.481.camel@sapling> <1324475397.31367.527.camel@sapling> Message-ID: <1324499774.31367.806.camel@sapling> For the purpose of discussion, I have attached an updated version of my patch. This version has partially resolved the scheduling-after-call (excess-spilling) problem by introducing an overriding heuristic into BURRSort which prioritizes all non-loads over calls. Roughly, this causes stuff that can be done before a call (except for loads) to be done prior to the call. In practice, this still does not always happen b/c of the local nature of the scheduling decisions. Surprisingly (to me at least), this relatively simple change seems to have eliminated all of the major performance regressions while leaving a substantial aggregate speedup [for some code it seems better to even prioritize the loads, and I don't understand that at all]. Nevertheless, this change has its downsides, and I would like to discuss various alternatives to mitigating the scheduling problems caused by call-induced spilling. I consider this patch to be for discussion only b/c I have not included any regression-test updates, and there still is a test-suite failure on x86_64 (and likely on other platforms as well) that need to be resolved. Please let me know what you think. Thanks again, Hal On Wed, 2011-12-21 at 07:49 -0600, Hal Finkel wrote: > It turns out that a significant cause of the performance regressions > caused by this patch are related to this issue: with the patch applied > the scheduler is now free to schedule many more things, especially > stores, after calls (especially intrinsics that are expanded to lib > calls). This tendency is bad because of the spilling necessary to cross > the call boundary. I am working on a proposed solution, and I'll post an > updated patch soon. > > Thanks again, > Hal > > On Tue, 2011-12-20 at 12:52 -0600, Hal Finkel wrote: > > On Tue, 2011-12-20 at 10:44 -0800, Jakob Stoklund Olesen wrote: > > > On Dec 20, 2011, at 9:22 AM, Hal Finkel wrote: > > > > > > > when I later look at the register map, only XMM0 and XMM1 are ever > > > > assigned to vregs, everything else is spilled. This is wrong. Do you > > > > have any ideas on what could be going wrong or other things I should > > > > examine? Could the register allocator not be accounting correctly for > > > > callee-saved registers when computing live-interval interference > > > > information? > > > > > > There are no callee-saved xmm registers. > > > > Thanks! I was mixing up the Win64 calling convention with the regular > > one. That explains things, so, I suppose the right thing to do is to > > make sure all stores are flushed before any call (which I think it > > already does), and any intrinsic that will be expanded (which it will > > not currently do). > > > > -Hal > > > > > > > > /jakob > > > > > > -- Hal Finkel Postdoctoral Appointee Leadership Computing Facility Argonne National Laboratory -------------- next part -------------- A non-text attachment was scrubbed... Name: llvm_lsro-20111221.diff Type: text/x-patch Size: 23163 bytes Desc: not available Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20111221/e5c5a307/attachment-0001.bin From nicholas at mxc.ca Wed Dec 21 14:54:13 2011 From: nicholas at mxc.ca (Nick Lewycky) Date: Wed, 21 Dec 2011 12:54:13 -0800 Subject: [llvm-commits] [llvm] r147037 - /llvm/trunk/lib/Analysis/InlineCost.cpp In-Reply-To: <4675B739-ACBC-4DB2-A4B0-EE020FE4FDE9@apple.com> References: <20111221060630.8F5FD2A6C12C@llvm.org> <4675B739-ACBC-4DB2-A4B0-EE020FE4FDE9@apple.com> Message-ID: <4EF24775.8020203@mxc.ca> On 12/21/2011 11:20 AM, Devang Patel wrote: > > On Dec 20, 2011, at 10:06 PM, Nick Lewycky wrote: > >> Author: nicholas >> Date: Wed Dec 21 00:06:30 2011 >> New Revision: 147037 >> >> URL: http://llvm.org/viewvc/llvm-project?rev=147037&view=rev >> Log: >> A call to a function marked 'noinline' is not an inline candidate. > > >> The sole call site of an intrinsic is also not an inline candidate. > > Really ? Yes because an intrinsic has no body to inline? I didn't find any description of "inline candidate" but it appears from the places it's used (not the inliner, only the loop unroller) to refer to call-sites that might be inlined, as it wants to avoid duplicating those. If you know otherwise, please fill me in! Nick > - > Devang > >> While here, make it >> more obvious that this code ignores all intrinsics. Noticed by inspection! >> >> Modified: >> llvm/trunk/lib/Analysis/InlineCost.cpp >> >> Modified: llvm/trunk/lib/Analysis/InlineCost.cpp >> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/InlineCost.cpp?rev=147037&r1=147036&r2=147037&view=diff >> ============================================================================== >> --- llvm/trunk/lib/Analysis/InlineCost.cpp (original) >> +++ llvm/trunk/lib/Analysis/InlineCost.cpp Wed Dec 21 00:06:30 2011 >> @@ -63,8 +63,8 @@ >> >> // Special handling for calls. >> if (isa(II) || isa(II)) { >> - if (isa(II)) >> - continue; // Debug intrinsics don't count as size. >> + if (isa(II)) >> + continue; // Intrinsics have no argument setup and can't be inlined. >> >> ImmutableCallSite CS(cast(II)); >> >> @@ -72,7 +72,7 @@ >> // If a function is both internal and has a single use, then it is >> // extremely likely to get inlined in the future (it was probably >> // exposed by an interleaved devirtualization pass). >> - if (F->hasInternalLinkage()&& F->hasOneUse()) >> + if (!CS.isNoInline()&& F->hasInternalLinkage()&& F->hasOneUse()) >> ++NumInlineCandidates; >> >> // If this call is to function itself, then the function is recursive. >> @@ -83,7 +83,7 @@ >> isRecursive = true; >> } >> >> - if (!isa(II)&& !callIsSmall(CS.getCalledFunction())) { >> + if (!callIsSmall(CS.getCalledFunction())) { >> // Each argument to a call takes on average one instruction to set up. >> NumInsts += CS.arg_size(); >> >> >> >> _______________________________________________ >> llvm-commits mailing list >> llvm-commits at cs.uiuc.edu >> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits > > From grosbach at apple.com Wed Dec 21 14:54:00 2011 From: grosbach at apple.com (Jim Grosbach) Date: Wed, 21 Dec 2011 20:54:00 -0000 Subject: [llvm-commits] [llvm] r147094 - in /llvm/trunk: lib/Target/ARM/ARMInstrThumb2.td lib/Target/ARM/AsmParser/ARMAsmParser.cpp test/MC/ARM/basic-thumb2-instructions.s Message-ID: <20111221205400.7E0C92A6C12C@llvm.org> Author: grosbach Date: Wed Dec 21 14:54:00 2011 New Revision: 147094 URL: http://llvm.org/viewvc/llvm-project?rev=147094&view=rev Log: Thumb2 assembly parsing of 'mov(register shifted register)' aliases. These map to the ASR, LSR, LSL, ROR instruction definitions. rdar://10615373 Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td?rev=147094&r1=147093&r2=147094&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td Wed Dec 21 14:54:00 2011 @@ -4141,6 +4141,11 @@ def t2MOVSsi: t2AsmPseudo<"movs${p} $Rd, $shift", (ins rGPR:$Rd, t2_so_reg:$shift, pred:$p)>; +def t2MOVsr: t2AsmPseudo<"mov${p} $Rd, $shift", + (ins rGPR:$Rd, so_reg_reg:$shift, pred:$p)>; +def t2MOVSsr: t2AsmPseudo<"movs${p} $Rd, $shift", + (ins rGPR:$Rd, so_reg_reg:$shift, pred:$p)>; + // ADR w/o the .w suffix def : t2InstAlias<"adr${p} $Rd, $addr", (t2ADR rGPR:$Rd, t2adrlabel:$addr, pred:$p)>; Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp?rev=147094&r1=147093&r2=147094&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp (original) +++ llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Wed Dec 21 14:54:00 2011 @@ -5748,6 +5748,42 @@ return true; } // Handle the Thumb2 mode MOV complex aliases. + case ARM::t2MOVsr: + case ARM::t2MOVSsr: { + // Which instruction to expand to depends on the CCOut operand and + // whether we're in an IT block if the register operands are low + // registers. + bool isNarrow = false; + if (isARMLowRegister(Inst.getOperand(0).getReg()) && + isARMLowRegister(Inst.getOperand(1).getReg()) && + isARMLowRegister(Inst.getOperand(2).getReg()) && + Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() && + inITBlock() == (Inst.getOpcode() == ARM::t2MOVsr)) + isNarrow = true; + MCInst TmpInst; + unsigned newOpc; + switch(ARM_AM::getSORegShOp(Inst.getOperand(3).getImm())) { + default: llvm_unreachable("unexpected opcode!"); + case ARM_AM::asr: newOpc = isNarrow ? ARM::tASRrr : ARM::t2ASRrr; break; + case ARM_AM::lsr: newOpc = isNarrow ? ARM::tLSRrr : ARM::t2LSRrr; break; + case ARM_AM::lsl: newOpc = isNarrow ? ARM::tLSLrr : ARM::t2LSLrr; break; + case ARM_AM::ror: newOpc = isNarrow ? ARM::tROR : ARM::t2RORrr; break; + } + TmpInst.setOpcode(newOpc); + TmpInst.addOperand(Inst.getOperand(0)); // Rd + if (isNarrow) + TmpInst.addOperand(MCOperand::CreateReg( + Inst.getOpcode() == ARM::t2MOVSsr ? ARM::CPSR : 0)); + TmpInst.addOperand(Inst.getOperand(1)); // Rn + TmpInst.addOperand(Inst.getOperand(2)); // Rm + TmpInst.addOperand(Inst.getOperand(4)); // CondCode + TmpInst.addOperand(Inst.getOperand(5)); + if (!isNarrow) + TmpInst.addOperand(MCOperand::CreateReg( + Inst.getOpcode() == ARM::t2MOVSsr ? ARM::CPSR : 0)); + Inst = TmpInst; + return true; + } case ARM::t2MOVsi: case ARM::t2MOVSsi: { // Which instruction to expand to depends on the CCOut operand and Modified: llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s?rev=147094&r1=147093&r2=147094&view=diff ============================================================================== --- llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s (original) +++ llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s Wed Dec 21 14:54:00 2011 @@ -1155,11 +1155,36 @@ mov r6, r2, lsr #16 movs r6, r2, asr #32 movs r6, r2, ror #5 + movs r4, r4, lsl r5 + movs r4, r4, lsr r5 + movs r4, r4, asr r5 + movs r4, r4, ror r5 + mov r4, r4, lsl r5 + movs r4, r4, ror r8 + movs r4, r5, lsr r6 + itttt eq + moveq r4, r4, lsl r5 + moveq r4, r4, lsr r5 + moveq r4, r4, asr r5 + moveq r4, r4, ror r5 @ CHECK: lsl.w r6, r2, #16 @ encoding: [0x4f,0xea,0x02,0x46] @ CHECK: lsr.w r6, r2, #16 @ encoding: [0x4f,0xea,0x12,0x46] @ CHECK: asrs r6, r2, #32 @ encoding: [0x16,0x10] @ CHECK: rors.w r6, r2, #5 @ encoding: [0x5f,0xea,0x72,0x16] +@ CHECK: lsls r4, r5 @ encoding: [0xac,0x40] +@ CHECK: lsrs r4, r5 @ encoding: [0xec,0x40] +@ CHECK: asrs r4, r5 @ encoding: [0x2c,0x41] +@ CHECK: rors r4, r5 @ encoding: [0xec,0x41] +@ CHECK: lsl.w r4, r4, r5 @ encoding: [0x04,0xfa,0x05,0xf4] +@ CHECK: rors.w r4, r4, r8 @ encoding: [0x74,0xfa,0x08,0xf4] +@ CHECK: lsrs.w r4, r5, r6 @ encoding: [0x35,0xfa,0x06,0xf4] +@ CHECK: itttt eq @ encoding: [0x01,0xbf] +@ CHECK: lsleq r4, r5 @ encoding: [0xac,0x40] +@ CHECK: lsreq r4, r5 @ encoding: [0xec,0x40] +@ CHECK: asreq r4, r5 @ encoding: [0x2c,0x41] +@ CHECK: roreq r4, r5 @ encoding: [0xec,0x41] + @------------------------------------------------------------------------------ From hfinkel at anl.gov Wed Dec 21 15:01:22 2011 From: hfinkel at anl.gov (Hal Finkel) Date: Wed, 21 Dec 2011 15:01:22 -0600 Subject: [llvm-commits] [PATCH] Allow SelectionDAGBuilder to reorder loads past stores In-Reply-To: <1324499774.31367.806.camel@sapling> References: <1324316529.31367.96.camel@sapling> <945273C4-D0AA-4CAF-B0ED-C6D96A52FE02@apple.com> <1324325951.31367.178.camel@sapling> <1324355462.31367.287.camel@sapling> <2264DB7F-F14F-4D93-B6C1-79D69B5F2DBF@apple.com> <1324401740.31367.437.camel@sapling> <4B06FCD2-5607-4F5A-989E-C961B6DD6FE4@2pi.dk> <1324407129.31367.481.camel@sapling> <1324475397.31367.527.camel@sapling> <1324499774.31367.806.camel@sapling> Message-ID: <1324501282.31367.812.camel@sapling> On Wed, 2011-12-21 at 14:36 -0600, Hal Finkel wrote: > For the purpose of discussion, I have attached an updated version of my > patch. This version has partially resolved the scheduling-after-call > (excess-spilling) problem by introducing an overriding heuristic into > BURRSort which prioritizes all non-loads over calls. Roughly, this > causes stuff that can be done before a call (except for loads) to be > done prior to the call. In practice, this still does not always happen > b/c of the local nature of the scheduling decisions. Surprisingly (to me > at least), this relatively simple change seems to have eliminated all of > the major performance regressions while leaving a substantial aggregate > speedup [for some code it seems better to even prioritize the loads, and > I don't understand that at all]. Nevertheless, this change has its > downsides, and I would like to discuss various alternatives to > mitigating the scheduling problems caused by call-induced spilling. For example, instead of trying to adjust the scheduling algorithms, it might be better to have the register allocator move instructions across call-induced spill points to eliminate spills when all of an instruction's inputs are defined before the call (or if all of its uses are after the call). -Hal > > I consider this patch to be for discussion only b/c I have not included > any regression-test updates, and there still is a test-suite failure on > x86_64 (and likely on other platforms as well) that need to be resolved. > > Please let me know what you think. > > Thanks again, > Hal > > On Wed, 2011-12-21 at 07:49 -0600, Hal Finkel wrote: > > It turns out that a significant cause of the performance regressions > > caused by this patch are related to this issue: with the patch applied > > the scheduler is now free to schedule many more things, especially > > stores, after calls (especially intrinsics that are expanded to lib > > calls). This tendency is bad because of the spilling necessary to cross > > the call boundary. I am working on a proposed solution, and I'll post an > > updated patch soon. > > > > Thanks again, > > Hal > > > > On Tue, 2011-12-20 at 12:52 -0600, Hal Finkel wrote: > > > On Tue, 2011-12-20 at 10:44 -0800, Jakob Stoklund Olesen wrote: > > > > On Dec 20, 2011, at 9:22 AM, Hal Finkel wrote: > > > > > > > > > when I later look at the register map, only XMM0 and XMM1 are ever > > > > > assigned to vregs, everything else is spilled. This is wrong. Do you > > > > > have any ideas on what could be going wrong or other things I should > > > > > examine? Could the register allocator not be accounting correctly for > > > > > callee-saved registers when computing live-interval interference > > > > > information? > > > > > > > > There are no callee-saved xmm registers. > > > > > > Thanks! I was mixing up the Win64 calling convention with the regular > > > one. That explains things, so, I suppose the right thing to do is to > > > make sure all stores are flushed before any call (which I think it > > > already does), and any intrinsic that will be expanded (which it will > > > not currently do). > > > > > > -Hal > > > > > > > > > > > /jakob > > > > > > > > > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits -- Hal Finkel Postdoctoral Appointee Leadership Computing Facility Argonne National Laboratory From mcrosier at apple.com Wed Dec 21 14:59:09 2011 From: mcrosier at apple.com (Chad Rosier) Date: Wed, 21 Dec 2011 20:59:09 -0000 Subject: [llvm-commits] [llvm] r147095 - /llvm/trunk/lib/Target/X86/X86InstrSSE.td Message-ID: <20111221205909.CA7422A6C12C@llvm.org> Author: mcrosier Date: Wed Dec 21 14:59:09 2011 New Revision: 147095 URL: http://llvm.org/viewvc/llvm-project?rev=147095&view=rev Log: Fix 80-column violations. Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrSSE.td?rev=147095&r1=147094&r2=147095&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86InstrSSE.td (original) +++ llvm/trunk/lib/Target/X86/X86InstrSSE.td Wed Dec 21 14:59:09 2011 @@ -1222,9 +1222,9 @@ (VMOVHPSrm VR128:$src1, addr:$src2)>; // FIXME: Instead of X86Unpckl, there should be a X86Movlhpd here, the problem - // is during lowering, where it's not possible to recognize the load fold cause - // it has two uses through a bitcast. One use disappears at isel time and the - // fold opportunity reappears. + // is during lowering, where it's not possible to recognize the load fold + // cause it has two uses through a bitcast. One use disappears at isel time + // and the fold opportunity reappears. def : Pat<(v2f64 (X86Unpckl VR128:$src1, (scalar_to_vector (loadf64 addr:$src2)))), (VMOVHPDrm VR128:$src1, addr:$src2)>; @@ -1265,9 +1265,9 @@ let Predicates = [HasSSE2] in { // FIXME: Instead of X86Unpckl, there should be a X86Movlhpd here, the problem - // is during lowering, where it's not possible to recognize the load fold cause - // it has two uses through a bitcast. One use disappears at isel time and the - // fold opportunity reappears. + // is during lowering, where it's not possible to recognize the load fold + // cause it has two uses through a bitcast. One use disappears at isel time + // and the fold opportunity reappears. def : Pat<(v2f64 (X86Unpckl VR128:$src1, (scalar_to_vector (loadf64 addr:$src2)))), (MOVHPDrm VR128:$src1, addr:$src2)>; From nicholas at mxc.ca Wed Dec 21 15:04:10 2011 From: nicholas at mxc.ca (Nick Lewycky) Date: Wed, 21 Dec 2011 13:04:10 -0800 Subject: [llvm-commits] [llvm] r147036 - in /llvm/trunk: lib/Analysis/ValueTracking.cpp lib/Transforms/Utils/SimplifyCFG.cpp test/Transforms/SimplifyCFG/SpeculativeExec.ll In-Reply-To: <05C067F7-5491-4FF6-AA1F-CDCB18D419BB@apple.com> References: <20111221055202.885DE2A6C12C@llvm.org> <05C067F7-5491-4FF6-AA1F-CDCB18D419BB@apple.com> Message-ID: <4EF249CA.9010808@mxc.ca> On 12/21/2011 11:02 AM, Dan Gohman wrote: > > On Dec 20, 2011, at 9:52 PM, Nick Lewycky wrote: > >> Author: nicholas >> Date: Tue Dec 20 23:52:02 2011 >> New Revision: 147036 >> >> URL: http://llvm.org/viewvc/llvm-project?rev=147036&view=rev >> Log: >> Make some intrinsics safe to speculatively execute. >> >> Modified: >> llvm/trunk/lib/Analysis/ValueTracking.cpp >> llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp >> llvm/trunk/test/Transforms/SimplifyCFG/SpeculativeExec.ll >> >> Modified: llvm/trunk/lib/Analysis/ValueTracking.cpp >> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/ValueTracking.cpp?rev=147036&r1=147035&r2=147036&view=diff >> ============================================================================== >> --- llvm/trunk/lib/Analysis/ValueTracking.cpp (original) >> +++ llvm/trunk/lib/Analysis/ValueTracking.cpp Tue Dec 20 23:52:02 2011 >> @@ -1912,11 +1912,31 @@ >> return false; >> return LI->getPointerOperand()->isDereferenceablePointer(); >> } >> - case Instruction::Call: >> + case Instruction::Call: { >> + if (const IntrinsicInst *II = dyn_cast(Inst)) { >> + switch (II->getIntrinsicID()) { >> + case Intrinsic::bswap: >> + case Intrinsic::ctlz: >> + case Intrinsic::ctpop: >> + case Intrinsic::cttz: >> + case Intrinsic::objectsize: >> + case Intrinsic::sadd_with_overflow: >> + case Intrinsic::smul_with_overflow: >> + case Intrinsic::ssub_with_overflow: >> + case Intrinsic::uadd_with_overflow: >> + case Intrinsic::umul_with_overflow: >> + case Intrinsic::usub_with_overflow: >> + return true; >> + // TODO: some fp intrinsics are marked as having the same error handling >> + // as libm. They're safe to speculate when they won't error. >> + // TODO: are convert_{from,to}_fp16 safe? >> + // TODO: can we list target-specific intrinsics here? > > Just checking mayHaveSideEffects() should cover almost everything here. Good point! Is there anything that mayHaveSideEffects() would return true on that wouldn't be safe to speculate? The comment on mayHaveSideEffects claims that a call to malloc would return false, but that's a lie, suggesting that an audit of users of these two functions is due... > >> + default: break; >> + } >> + } >> return false; // The called function could have undefined behavior or >> - // side-effects. >> - // FIXME: We should special-case some intrinsics (bswap, >> - // overflow-checking arithmetic, etc.) >> + // side-effects, even if marked readnone nounwind. >> + } >> case Instruction::VAArg: >> case Instruction::Alloca: >> case Instruction::Invoke: >> >> Modified: llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp >> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp?rev=147036&r1=147035&r2=147036&view=diff >> ============================================================================== >> --- llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp (original) >> +++ llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp Tue Dec 20 23:52:02 2011 >> @@ -293,6 +293,7 @@ >> Cost = 1; >> break; // These are all cheap and non-trapping instructions. >> >> + case Instruction::Call: > > cttz, ctlz, etc. are very expensive on many targets. Having SimplifyCFG > speculate them here could cause substantial pessimizations. Yes, and indeed it won't because the cost of these is 2 and the threshold is 1. That's why the test needs -phi-node-folding-threshold=2 to work. Ultimately the IR-level optimizers will always do better with a select instead of branch+phi, and I'd like to instead teach codegen to turn selects into branches (sinking the computations on each side) when profitable. Nick From stoklund at 2pi.dk Wed Dec 21 15:05:23 2011 From: stoklund at 2pi.dk (Jakob Stoklund Olesen) Date: Wed, 21 Dec 2011 13:05:23 -0800 Subject: [llvm-commits] [llvm] r147093 - /llvm/trunk/lib/Analysis/InlineCost.cpp In-Reply-To: <20111221202604.24C7F2A6C12C@llvm.org> References: <20111221202604.24C7F2A6C12C@llvm.org> Message-ID: <90FF8717-402C-4218-AB8C-5AFFA7997C25@2pi.dk> On Dec 21, 2011, at 12:26 PM, Nick Lewycky wrote: > Author: nicholas > Date: Wed Dec 21 14:26:03 2011 > New Revision: 147093 > > URL: http://llvm.org/viewvc/llvm-project?rev=147093&view=rev > Log: > Continue counting intrinsics as instructions (except when they aren't, such as > debug info) and for being vector operations. Fixes regression from r147037. Looks good. Thanks! /jakob > > Modified: > llvm/trunk/lib/Analysis/InlineCost.cpp > > Modified: llvm/trunk/lib/Analysis/InlineCost.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/InlineCost.cpp?rev=147093&r1=147092&r2=147093&view=diff > ============================================================================== > --- llvm/trunk/lib/Analysis/InlineCost.cpp (original) > +++ llvm/trunk/lib/Analysis/InlineCost.cpp Wed Dec 21 14:26:03 2011 > @@ -63,8 +63,22 @@ > > // Special handling for calls. > if (isa(II) || isa(II)) { > - if (isa(II)) > - continue; // Intrinsics have no argument setup and can't be inlined. > + if (const IntrinsicInst *IntrinsicI = dyn_cast(II)) { > + switch (IntrinsicI->getIntrinsicID()) { > + default: break; > + case Intrinsic::dbg_declare: > + case Intrinsic::dbg_value: > + case Intrinsic::invariant_start: > + case Intrinsic::invariant_end: > + case Intrinsic::lifetime_start: > + case Intrinsic::lifetime_end: > + case Intrinsic::objectsize: > + case Intrinsic::ptr_annotation: > + case Intrinsic::var_annotation: > + // These intrinsics don't count as size. > + continue; > + } > + } > > ImmutableCallSite CS(cast(II)); > > @@ -83,7 +97,7 @@ > isRecursive = true; > } > > - if (!callIsSmall(CS.getCalledFunction())) { > + if (!isa(II) && !callIsSmall(CS.getCalledFunction())) { > // Each argument to a call takes on average one instruction to set up. > NumInsts += CS.arg_size(); > > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From grosbach at apple.com Wed Dec 21 15:04:19 2011 From: grosbach at apple.com (Jim Grosbach) Date: Wed, 21 Dec 2011 21:04:19 -0000 Subject: [llvm-commits] [llvm] r147096 - in /llvm/trunk: lib/Target/ARM/AsmParser/ARMAsmParser.cpp test/MC/ARM/basic-thumb2-instructions.s Message-ID: <20111221210419.ED2FC2A6C12C@llvm.org> Author: grosbach Date: Wed Dec 21 15:04:19 2011 New Revision: 147096 URL: http://llvm.org/viewvc/llvm-project?rev=147096&view=rev Log: Thumb2 assembly parsing of 'mov rd, rn, rrx'. Maps to the RRX instruction. Missed this case earlier. rdar://10615373 Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp?rev=147096&r1=147095&r2=147096&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp (original) +++ llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Wed Dec 21 15:04:19 2011 @@ -5802,6 +5802,7 @@ case ARM_AM::lsr: newOpc = isNarrow ? ARM::tLSRri : ARM::t2LSRri; break; case ARM_AM::lsl: newOpc = isNarrow ? ARM::tLSLri : ARM::t2LSLri; break; case ARM_AM::ror: newOpc = ARM::t2RORri; isNarrow = false; break; + case ARM_AM::rrx: isNarrow = false; newOpc = ARM::t2RRX; break; } unsigned Ammount = ARM_AM::getSORegOffset(Inst.getOperand(2).getImm()); if (Ammount == 32) Ammount = 0; @@ -5811,7 +5812,8 @@ TmpInst.addOperand(MCOperand::CreateReg( Inst.getOpcode() == ARM::t2MOVSsi ? ARM::CPSR : 0)); TmpInst.addOperand(Inst.getOperand(1)); // Rn - TmpInst.addOperand(MCOperand::CreateImm(Ammount)); + if (newOpc != ARM::t2RRX) + TmpInst.addOperand(MCOperand::CreateImm(Ammount)); TmpInst.addOperand(Inst.getOperand(3)); // CondCode TmpInst.addOperand(Inst.getOperand(4)); if (!isNarrow) Modified: llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s?rev=147096&r1=147095&r2=147096&view=diff ============================================================================== --- llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s (original) +++ llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s Wed Dec 21 15:04:19 2011 @@ -1167,6 +1167,7 @@ moveq r4, r4, lsr r5 moveq r4, r4, asr r5 moveq r4, r4, ror r5 + mov r4, r4, rrx @ CHECK: lsl.w r6, r2, #16 @ encoding: [0x4f,0xea,0x02,0x46] @ CHECK: lsr.w r6, r2, #16 @ encoding: [0x4f,0xea,0x12,0x46] @@ -1184,7 +1185,7 @@ @ CHECK: lsreq r4, r5 @ encoding: [0xec,0x40] @ CHECK: asreq r4, r5 @ encoding: [0x2c,0x41] @ CHECK: roreq r4, r5 @ encoding: [0xec,0x41] - +@ CHECK: rrx r4, r4 @ encoding: [0x4f,0xea,0x34,0x04] @------------------------------------------------------------------------------ From chandlerc at google.com Wed Dec 21 15:19:18 2011 From: chandlerc at google.com (Chandler Carruth) Date: Wed, 21 Dec 2011 13:19:18 -0800 Subject: [llvm-commits] [llvm] r147090 - /llvm/trunk/lib/CodeGen/MachineBlockPlacement.cpp In-Reply-To: <20111221201854.521D02A6C12C@llvm.org> References: <20111221201854.521D02A6C12C@llvm.org> Message-ID: On Wed, Dec 21, 2011 at 12:18 PM, Jakub Staszak wrote: > - Change a few operator[] to lookup which is cheaper. > Cool, but... > - Add some constantness. > I really don't like this. There are a lot of methods on MachineBasicBlock that are non-const, and I don't want to have to undo this patch when I discover I need to call one. I don't think this is protecting us from any bugs or enabling any interesting optimizations. -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20111221/2a5d2a15/attachment.html From eli.friedman at gmail.com Wed Dec 21 15:26:06 2011 From: eli.friedman at gmail.com (Eli Friedman) Date: Wed, 21 Dec 2011 13:26:06 -0800 Subject: [llvm-commits] [llvm] r147036 - in /llvm/trunk: lib/Analysis/ValueTracking.cpp lib/Transforms/Utils/SimplifyCFG.cpp test/Transforms/SimplifyCFG/SpeculativeExec.ll In-Reply-To: <4EF249CA.9010808@mxc.ca> References: <20111221055202.885DE2A6C12C@llvm.org> <05C067F7-5491-4FF6-AA1F-CDCB18D419BB@apple.com> <4EF249CA.9010808@mxc.ca> Message-ID: On Wed, Dec 21, 2011 at 1:04 PM, Nick Lewycky wrote: > On 12/21/2011 11:02 AM, Dan Gohman wrote: >> >> On Dec 20, 2011, at 9:52 PM, Nick Lewycky wrote: >> >>> Author: nicholas >>> Date: Tue Dec 20 23:52:02 2011 >>> New Revision: 147036 >>> >>> URL: http://llvm.org/viewvc/llvm-project?rev=147036&view=rev >>> Log: >>> Make some intrinsics safe to speculatively execute. >>> >>> Modified: >>> ? ? llvm/trunk/lib/Analysis/ValueTracking.cpp >>> ? ? llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp >>> ? ? llvm/trunk/test/Transforms/SimplifyCFG/SpeculativeExec.ll >>> >>> Modified: llvm/trunk/lib/Analysis/ValueTracking.cpp >>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/ValueTracking.cpp?rev=147036&r1=147035&r2=147036&view=diff >>> ============================================================================== >>> --- llvm/trunk/lib/Analysis/ValueTracking.cpp (original) >>> +++ llvm/trunk/lib/Analysis/ValueTracking.cpp Tue Dec 20 23:52:02 2011 >>> @@ -1912,11 +1912,31 @@ >>> ? ? ? ?return false; >>> ? ? ?return LI->getPointerOperand()->isDereferenceablePointer(); >>> ? ?} >>> - ?case Instruction::Call: >>> + ?case Instruction::Call: { >>> + ? if (const IntrinsicInst *II = dyn_cast(Inst)) { >>> + ? ? switch (II->getIntrinsicID()) { >>> + ? ? ? case Intrinsic::bswap: >>> + ? ? ? case Intrinsic::ctlz: >>> + ? ? ? case Intrinsic::ctpop: >>> + ? ? ? case Intrinsic::cttz: >>> + ? ? ? case Intrinsic::objectsize: >>> + ? ? ? case Intrinsic::sadd_with_overflow: >>> + ? ? ? case Intrinsic::smul_with_overflow: >>> + ? ? ? case Intrinsic::ssub_with_overflow: >>> + ? ? ? case Intrinsic::uadd_with_overflow: >>> + ? ? ? case Intrinsic::umul_with_overflow: >>> + ? ? ? case Intrinsic::usub_with_overflow: >>> + ? ? ? ? return true; >>> + ? ? ? // TODO: some fp intrinsics are marked as having the same error handling >>> + ? ? ? // as libm. They're safe to speculate when they won't error. >>> + ? ? ? // TODO: are convert_{from,to}_fp16 safe? >>> + ? ? ? // TODO: can we list target-specific intrinsics here? >> >> Just checking mayHaveSideEffects() should cover almost everything here. > > Good point! Is there anything that mayHaveSideEffects() would return > true on that wouldn't be safe to speculate? The comment on > mayHaveSideEffects claims that a call to malloc would return false, but > that's a lie, suggesting that an audit of users of these two functions > is due... mayHaveSideEffects is essentially equivalent to mayWriteToMemory, and that is clearly not the same thing as being safe to speculate. -Eli From kubastaszak at gmail.com Wed Dec 21 15:39:45 2011 From: kubastaszak at gmail.com (Jakub Staszak) Date: Wed, 21 Dec 2011 22:39:45 +0100 Subject: [llvm-commits] [llvm] r147090 - /llvm/trunk/lib/CodeGen/MachineBlockPlacement.cpp In-Reply-To: References: <20111221201854.521D02A6C12C@llvm.org> Message-ID: You are right. Now I realize that I was a little bit too "aggressive" here. I will be more careful in the future. - Kuba On Dec 21, 2011, at 10:19 PM, Chandler Carruth wrote: > On Wed, Dec 21, 2011 at 12:18 PM, Jakub Staszak wrote: > - Change a few operator[] to lookup which is cheaper. > > Cool, but... > > - Add some constantness. > > I really don't like this. There are a lot of methods on MachineBasicBlock that are non-const, and I don't want to have to undo this patch when I discover I need to call one. I don't think this is protecting us from any bugs or enabling any interesting optimizations. -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20111221/e90fbc3b/attachment.html From gohman at apple.com Wed Dec 21 15:43:51 2011 From: gohman at apple.com (Dan Gohman) Date: Wed, 21 Dec 2011 21:43:51 -0000 Subject: [llvm-commits] [llvm] r147098 - /llvm/trunk/lib/Transforms/Scalar/ObjCARC.cpp Message-ID: <20111221214351.0BB472A6C12C@llvm.org> Author: djg Date: Wed Dec 21 15:43:50 2011 New Revision: 147098 URL: http://llvm.org/viewvc/llvm-project?rev=147098&view=rev Log: Fix a copy+pasto. No testcase, because the symptoms of dereferencing an invalid iterator aren't reproducible. rdar://10614085. Modified: llvm/trunk/lib/Transforms/Scalar/ObjCARC.cpp Modified: llvm/trunk/lib/Transforms/Scalar/ObjCARC.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/ObjCARC.cpp?rev=147098&r1=147097&r2=147098&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Scalar/ObjCARC.cpp (original) +++ llvm/trunk/lib/Transforms/Scalar/ObjCARC.cpp Wed Dec 21 15:43:50 2011 @@ -2504,7 +2504,7 @@ Pred = *PI++; if (Pred != BB) { I = BBStates.find(Pred); - if (I == BBStates.end() || I->second.isVisitedTopDown()) + if (I != BBStates.end() && I->second.isVisitedTopDown()) MyStates.MergePred(I->second); } } From dmalyshev at accesssoftek.com Wed Dec 21 15:47:46 2011 From: dmalyshev at accesssoftek.com (Danil Malyshev) Date: Wed, 21 Dec 2011 13:47:46 -0800 Subject: [llvm-commits] JIT/MCJIT::getPointerToNamedFunction() Message-ID: <6AE1604EE3EC5F4296C096518C6B77EE1AA4D191F3@mail.accesssoftek.com> ping ________________________________ From: Danil Malyshev Sent: Friday, December 16, 2011 1:02 AM To: 'llvm-commits at cs.uiuc.edu' Subject: JIT/MCJIT::getPointerToNamedFunction() Hello everyone, Please find attached the patch for review. It's a small re-factored JIT/MCJIT::getPointerToNamedFunction(), so it could be called with the base class. Regards, Danil -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20111221/30a1300d/attachment.html From dblaikie at gmail.com Wed Dec 21 15:53:13 2011 From: dblaikie at gmail.com (David Blaikie) Date: Wed, 21 Dec 2011 13:53:13 -0800 Subject: [llvm-commits] [llvm] r147090 - /llvm/trunk/lib/CodeGen/MachineBlockPlacement.cpp Message-ID: <-5322339473606123382@unknownmsgid> Is there any reason lookup should be cheaper than []? Should we just be fixing the container? From: Jakub Staszak Sent: 12/21/2011 10:24 AM To: llvm-commits at cs.uiuc.edu Subject: [llvm-commits] [llvm] r147090 - /llvm/trunk/lib/CodeGen/MachineBlockPlacement.cpp Author: kuba Date: Wed Dec 21 14:18:54 2011 New Revision: 147090 URL: http://llvm.org/viewvc/llvm-project?rev=147090&view=rev Log: - Change a few operator[] to lookup which is cheaper. - Add some constantness. Modified: llvm/trunk/lib/CodeGen/MachineBlockPlacement.cpp Modified: llvm/trunk/lib/CodeGen/MachineBlockPlacement.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineBlockPlacement.cpp?rev=147090&r1=147089&r2=147090&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/MachineBlockPlacement.cpp (original) +++ llvm/trunk/lib/CodeGen/MachineBlockPlacement.cpp Wed Dec 21 14:18:54 2011 @@ -116,7 +116,7 @@ /// a contiguous sequence of basic blocks, updating the edge list, and /// updating the block -> chain mapping. It does not free or tear down the /// old chain, but the old chain's block list is no longer valid. - void merge(MachineBasicBlock *BB, BlockChain *Chain) { + void merge(MachineBasicBlock *BB, const BlockChain *Chain) { assert(BB); assert(!Blocks.empty()); @@ -185,28 +185,27 @@ /// between basic blocks. DenseMap BlockToChain; - void markChainSuccessors(BlockChain &Chain, - MachineBasicBlock *LoopHeaderBB, + void markChainSuccessors(const BlockChain &Chain, + const MachineBasicBlock *LoopHeaderBB, SmallVectorImpl &BlockWorkList, - const BlockFilterSet *BlockFilter = 0); - MachineBasicBlock *selectBestSuccessor(MachineBasicBlock *BB, - BlockChain &Chain, - const BlockFilterSet *BlockFilter); + const BlockFilterSet *BlockFilter = 0) const; + MachineBasicBlock *selectBestSuccessor(const MachineBasicBlock *BB, + const BlockChain &Chain, const BlockFilterSet *BlockFilter) const; MachineBasicBlock *selectBestCandidateBlock( - BlockChain &Chain, SmallVectorImpl &WorkList, - const BlockFilterSet *BlockFilter); + const BlockChain &Chain, SmallVectorImpl &WorkList, + const BlockFilterSet *BlockFilter) const; MachineBasicBlock *getFirstUnplacedBlock( MachineFunction &F, const BlockChain &PlacedChain, MachineFunction::iterator &PrevUnplacedBlockIt, - const BlockFilterSet *BlockFilter); + const BlockFilterSet *BlockFilter) const; void buildChain(MachineBasicBlock *BB, BlockChain &Chain, SmallVectorImpl &BlockWorkList, - const BlockFilterSet *BlockFilter = 0); + const BlockFilterSet *BlockFilter = 0) const; MachineBasicBlock *findBestLoopTop(MachineFunction &F, MachineLoop &L, - const BlockFilterSet &LoopBlockSet); - void buildLoopChains(MachineFunction &F, MachineLoop &L); + const BlockFilterSet &LoopBlockSet) const; + void buildLoopChains(MachineFunction &F, MachineLoop &L) const; void buildCFGChains(MachineFunction &F); void AlignLoops(MachineFunction &F); @@ -246,7 +245,7 @@ /// \brief Helper to print the name of a MBB. /// /// Only used by debug logging. -static std::string getBlockName(MachineBasicBlock *BB) { +static std::string getBlockName(const MachineBasicBlock *BB) { std::string Result; raw_string_ostream OS(Result); OS << "BB#" << BB->getNumber() @@ -258,7 +257,7 @@ /// \brief Helper to print the number of a MBB. /// /// Only used by debug logging. -static std::string getBlockNum(MachineBasicBlock *BB) { +static std::string getBlockNum(const MachineBasicBlock *BB) { std::string Result; raw_string_ostream OS(Result); OS << "BB#" << BB->getNumber(); @@ -274,10 +273,10 @@ /// having one fewer active predecessor. It also adds any successors of this /// chain which reach the zero-predecessor state to the worklist passed in. void MachineBlockPlacement::markChainSuccessors( - BlockChain &Chain, - MachineBasicBlock *LoopHeaderBB, + const BlockChain &Chain, + const MachineBasicBlock *LoopHeaderBB, SmallVectorImpl &BlockWorkList, - const BlockFilterSet *BlockFilter) { + const BlockFilterSet *BlockFilter) const { // Walk all the blocks in this chain, marking their successors as having // a predecessor placed. for (BlockChain::iterator CBI = Chain.begin(), CBE = Chain.end(); @@ -291,7 +290,7 @@ SI != SE; ++SI) { if (BlockFilter && !BlockFilter->count(*SI)) continue; - BlockChain &SuccChain = *BlockToChain[*SI]; + BlockChain &SuccChain = *BlockToChain.lookup(*SI); // Disregard edges within a fixed chain, or edges to the loop header. if (&Chain == &SuccChain || *SI == LoopHeaderBB) continue; @@ -314,8 +313,8 @@ /// /// \returns The best successor block found, or null if none are viable. MachineBasicBlock *MachineBlockPlacement::selectBestSuccessor( - MachineBasicBlock *BB, BlockChain &Chain, - const BlockFilterSet *BlockFilter) { + const MachineBasicBlock *BB, const BlockChain &Chain, + const BlockFilterSet *BlockFilter) const { const BranchProbability HotProb(4, 5); // 80% MachineBasicBlock *BestSucc = 0; @@ -329,12 +328,11 @@ uint32_t WeightScale = 0; uint32_t SumWeight = MBPI->getSumForBlock(BB, WeightScale); DEBUG(dbgs() << "Attempting merge from: " << getBlockName(BB) << "\n"); - for (MachineBasicBlock::succ_iterator SI = BB->succ_begin(), - SE = BB->succ_end(); - SI != SE; ++SI) { + for (MachineBasicBlock::const_succ_iterator SI = BB->succ_begin(), + SE = BB->succ_end(); SI != SE; ++SI) { if (BlockFilter && !BlockFilter->count(*SI)) continue; - BlockChain &SuccChain = *BlockToChain[*SI]; + const BlockChain &SuccChain = *BlockToChain.lookup(*SI); if (&SuccChain == &Chain) { DEBUG(dbgs() << " " << getBlockName(*SI) << " -> Already merged!\n"); continue; @@ -364,7 +362,7 @@ PE = (*SI)->pred_end(); PI != PE; ++PI) { if (*PI == *SI || (BlockFilter && !BlockFilter->count(*PI)) || - BlockToChain[*PI] == &Chain) + BlockToChain.lookup(*PI) == &Chain) continue; BlockFrequency PredEdgeFreq = MBFI->getBlockFreq(*PI) * MBPI->getEdgeProbability(*PI, *SI); @@ -420,8 +418,8 @@ /// /// \returns The best block found, or null if none are viable. MachineBasicBlock *MachineBlockPlacement::selectBestCandidateBlock( - BlockChain &Chain, SmallVectorImpl &WorkList, - const BlockFilterSet *BlockFilter) { + const BlockChain &Chain, SmallVectorImpl &WorkList, + const BlockFilterSet *BlockFilter) const { // Once we need to walk the worklist looking for a candidate, cleanup the // worklist of already placed entries. // FIXME: If this shows up on profiles, it could be folded (at the cost of @@ -436,7 +434,7 @@ WBE = WorkList.end(); WBI != WBE; ++WBI) { assert(!BlockFilter || BlockFilter->count(*WBI)); - BlockChain &SuccChain = *BlockToChain[*WBI]; + const BlockChain &SuccChain = *BlockToChain.lookup(*WBI); if (&SuccChain == &Chain) { DEBUG(dbgs() << " " << getBlockName(*WBI) << " -> Already merged!\n"); @@ -465,17 +463,17 @@ MachineBasicBlock *MachineBlockPlacement::getFirstUnplacedBlock( MachineFunction &F, const BlockChain &PlacedChain, MachineFunction::iterator &PrevUnplacedBlockIt, - const BlockFilterSet *BlockFilter) { + const BlockFilterSet *BlockFilter) const { for (MachineFunction::iterator I = PrevUnplacedBlockIt, E = F.end(); I != E; ++I) { if (BlockFilter && !BlockFilter->count(I)) continue; - if (BlockToChain[I] != &PlacedChain) { + if (BlockToChain.lookup(I) != &PlacedChain) { PrevUnplacedBlockIt = I; // Now select the head of the chain to which the unplaced block belongs // as the block to place. This will force the entire chain to be placed, // and satisfies the requirements of merging chains. - return *BlockToChain[I]->begin(); + return *BlockToChain.lookup(I)->begin(); } } return 0; @@ -485,9 +483,9 @@ MachineBasicBlock *BB, BlockChain &Chain, SmallVectorImpl &BlockWorkList, - const BlockFilterSet *BlockFilter) { + const BlockFilterSet *BlockFilter) const { assert(BB); - assert(BlockToChain[BB] == &Chain); + assert(BlockToChain.lookup(BB) == &Chain); MachineFunction &F = *BB->getParent(); MachineFunction::iterator PrevUnplacedBlockIt = F.begin(); @@ -496,7 +494,7 @@ BB = *llvm::prior(Chain.end()); for (;;) { assert(BB); - assert(BlockToChain[BB] == &Chain); + assert(BlockToChain.lookup(BB) == &Chain); assert(*llvm::prior(Chain.end()) == BB); MachineBasicBlock *BestSucc = 0; @@ -521,7 +519,7 @@ } // Place this block, updating the datastructures to reflect its placement. - BlockChain &SuccChain = *BlockToChain[BestSucc]; + BlockChain &SuccChain = *BlockToChain.lookup(BestSucc); // Zero out LoopPredecessors for the successor we're about to merge in case // we selected a successor that didn't fit naturally into the CFG. SuccChain.LoopPredecessors = 0; @@ -544,7 +542,7 @@ MachineBasicBlock * MachineBlockPlacement::findBestLoopTop(MachineFunction &F, MachineLoop &L, - const BlockFilterSet &LoopBlockSet) { + const BlockFilterSet &LoopBlockSet) const { BlockFrequency BestExitEdgeFreq; MachineBasicBlock *ExitingBB = 0; MachineBasicBlock *LoopingBB = 0; @@ -558,7 +556,7 @@ for (MachineLoop::block_iterator I = L.block_begin(), E = L.block_end(); I != E; ++I) { - BlockChain &Chain = *BlockToChain[*I]; + const BlockChain &Chain = *BlockToChain.lookup(*I); // Ensure that this block is at the end of a chain; otherwise it could be // mid-way through an inner loop or a successor of an analyzable branch. if (*I != *llvm::prior(Chain.end())) @@ -588,7 +586,7 @@ continue; if (*SI == *I) continue; - BlockChain &SuccChain = *BlockToChain[*SI]; + const BlockChain &SuccChain = *BlockToChain.lookup(*SI); // Don't split chains, either this chain or the successor's chain. if (&Chain == &SuccChain || *SI != *SuccChain.begin()) { DEBUG(dbgs() << " " << (LoopBlockSet.count(*SI) ? "looping: " @@ -665,7 +663,7 @@ /// both preserves the topological structure and minimizes taken conditional /// branches. void MachineBlockPlacement::buildLoopChains(MachineFunction &F, - MachineLoop &L) { + MachineLoop &L) const { // First recurse through any nested loops, building chains for those inner // loops. for (MachineLoop::iterator LI = L.begin(), LE = L.end(); LI != LE; ++LI) @@ -675,29 +673,29 @@ BlockFilterSet LoopBlockSet(L.block_begin(), L.block_end()); MachineBasicBlock *LayoutTop = findBestLoopTop(F, L, LoopBlockSet); - BlockChain &LoopChain = *BlockToChain[LayoutTop]; + BlockChain &LoopChain = *BlockToChain.lookup(LayoutTop); // FIXME: This is a really lame way of walking the chains in the loop: we // walk the blocks, and use a set to prevent visiting a particular chain // twice. - SmallPtrSet UpdatedPreds; + SmallPtrSet UpdatedPreds; assert(LoopChain.LoopPredecessors == 0); UpdatedPreds.insert(&LoopChain); for (MachineLoop::block_iterator BI = L.block_begin(), BE = L.block_end(); BI != BE; ++BI) { - BlockChain &Chain = *BlockToChain[*BI]; + BlockChain &Chain = *BlockToChain.lookup(*BI); if (!UpdatedPreds.insert(&Chain)) continue; assert(Chain.LoopPredecessors == 0); for (BlockChain::iterator BCI = Chain.begin(), BCE = Chain.end(); BCI != BCE; ++BCI) { - assert(BlockToChain[*BCI] == &Chain); + assert(BlockToChain.lookup(*BCI) == &Chain); for (MachineBasicBlock::pred_iterator PI = (*BCI)->pred_begin(), PE = (*BCI)->pred_end(); PI != PE; ++PI) { - if (BlockToChain[*PI] == &Chain || !LoopBlockSet.count(*PI)) + if (BlockToChain.lookup(*PI) == &Chain || !LoopBlockSet.count(*PI)) continue; ++Chain.LoopPredecessors; } _______________________________________________ llvm-commits mailing list llvm-commits at cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From kubastaszak at gmail.com Wed Dec 21 16:00:57 2011 From: kubastaszak at gmail.com (Jakub Staszak) Date: Wed, 21 Dec 2011 23:00:57 +0100 Subject: [llvm-commits] [llvm] r147090 - /llvm/trunk/lib/CodeGen/MachineBlockPlacement.cpp In-Reply-To: <-5322339473606123382@unknownmsgid> References: <-5322339473606123382@unknownmsgid> Message-ID: <1F4292AB-5A70-48AB-9AE2-A4D6DFFD196B@gmail.com> operator[] inserts an object for key if it doesn't exist. // X is empty if (X[0] == a) { } if (X[1] == b) { } if (X[2] == c) { } // X.size() = 3 This is the way that std::map works. I believe we want to be quite compatible here. - Kuba On Dec 21, 2011, at 10:53 PM, David Blaikie wrote: > Is there any reason lookup should be cheaper than []? Should we just be > fixing the container? > From: Jakub Staszak > Sent: 12/21/2011 10:24 AM > To: llvm-commits at cs.uiuc.edu > Subject: [llvm-commits] [llvm] r147090 > - /llvm/trunk/lib/CodeGen/MachineBlockPlacement.cpp > Author: kuba > Date: Wed Dec 21 14:18:54 2011 > New Revision: 147090 > > URL: http://llvm.org/viewvc/llvm-project?rev=147090&view=rev > Log: > - Change a few operator[] to lookup which is cheaper. > - Add some constantness. > > Modified: > llvm/trunk/lib/CodeGen/MachineBlockPlacement.cpp > > Modified: llvm/trunk/lib/CodeGen/MachineBlockPlacement.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineBlockPlacement.cpp?rev=147090&r1=147089&r2=147090&view=diff > ============================================================================== > --- llvm/trunk/lib/CodeGen/MachineBlockPlacement.cpp (original) > +++ llvm/trunk/lib/CodeGen/MachineBlockPlacement.cpp Wed Dec 21 14:18:54 2011 > @@ -116,7 +116,7 @@ > /// a contiguous sequence of basic blocks, updating the edge list, and > /// updating the block -> chain mapping. It does not free or tear down the > /// old chain, but the old chain's block list is no longer valid. > - void merge(MachineBasicBlock *BB, BlockChain *Chain) { > + void merge(MachineBasicBlock *BB, const BlockChain *Chain) { > assert(BB); > assert(!Blocks.empty()); > > @@ -185,28 +185,27 @@ > /// between basic blocks. > DenseMap BlockToChain; > > - void markChainSuccessors(BlockChain &Chain, > - MachineBasicBlock *LoopHeaderBB, > + void markChainSuccessors(const BlockChain &Chain, > + const MachineBasicBlock *LoopHeaderBB, > SmallVectorImpl &BlockWorkList, > - const BlockFilterSet *BlockFilter = 0); > - MachineBasicBlock *selectBestSuccessor(MachineBasicBlock *BB, > - BlockChain &Chain, > - const BlockFilterSet *BlockFilter); > + const BlockFilterSet *BlockFilter = 0) const; > + MachineBasicBlock *selectBestSuccessor(const MachineBasicBlock *BB, > + const BlockChain &Chain, const BlockFilterSet *BlockFilter) const; > MachineBasicBlock *selectBestCandidateBlock( > - BlockChain &Chain, SmallVectorImpl &WorkList, > - const BlockFilterSet *BlockFilter); > + const BlockChain &Chain, SmallVectorImpl &WorkList, > + const BlockFilterSet *BlockFilter) const; > MachineBasicBlock *getFirstUnplacedBlock( > MachineFunction &F, > const BlockChain &PlacedChain, > MachineFunction::iterator &PrevUnplacedBlockIt, > - const BlockFilterSet *BlockFilter); > + const BlockFilterSet *BlockFilter) const; > void buildChain(MachineBasicBlock *BB, BlockChain &Chain, > SmallVectorImpl &BlockWorkList, > - const BlockFilterSet *BlockFilter = 0); > + const BlockFilterSet *BlockFilter = 0) const; > MachineBasicBlock *findBestLoopTop(MachineFunction &F, > MachineLoop &L, > - const BlockFilterSet &LoopBlockSet); > - void buildLoopChains(MachineFunction &F, MachineLoop &L); > + const BlockFilterSet &LoopBlockSet) const; > + void buildLoopChains(MachineFunction &F, MachineLoop &L) const; > void buildCFGChains(MachineFunction &F); > void AlignLoops(MachineFunction &F); > > @@ -246,7 +245,7 @@ > /// \brief Helper to print the name of a MBB. > /// > /// Only used by debug logging. > -static std::string getBlockName(MachineBasicBlock *BB) { > +static std::string getBlockName(const MachineBasicBlock *BB) { > std::string Result; > raw_string_ostream OS(Result); > OS << "BB#" << BB->getNumber() > @@ -258,7 +257,7 @@ > /// \brief Helper to print the number of a MBB. > /// > /// Only used by debug logging. > -static std::string getBlockNum(MachineBasicBlock *BB) { > +static std::string getBlockNum(const MachineBasicBlock *BB) { > std::string Result; > raw_string_ostream OS(Result); > OS << "BB#" << BB->getNumber(); > @@ -274,10 +273,10 @@ > /// having one fewer active predecessor. It also adds any successors of this > /// chain which reach the zero-predecessor state to the worklist passed in. > void MachineBlockPlacement::markChainSuccessors( > - BlockChain &Chain, > - MachineBasicBlock *LoopHeaderBB, > + const BlockChain &Chain, > + const MachineBasicBlock *LoopHeaderBB, > SmallVectorImpl &BlockWorkList, > - const BlockFilterSet *BlockFilter) { > + const BlockFilterSet *BlockFilter) const { > // Walk all the blocks in this chain, marking their successors as having > // a predecessor placed. > for (BlockChain::iterator CBI = Chain.begin(), CBE = Chain.end(); > @@ -291,7 +290,7 @@ > SI != SE; ++SI) { > if (BlockFilter && !BlockFilter->count(*SI)) > continue; > - BlockChain &SuccChain = *BlockToChain[*SI]; > + BlockChain &SuccChain = *BlockToChain.lookup(*SI); > // Disregard edges within a fixed chain, or edges to the loop header. > if (&Chain == &SuccChain || *SI == LoopHeaderBB) > continue; > @@ -314,8 +313,8 @@ > /// > /// \returns The best successor block found, or null if none are viable. > MachineBasicBlock *MachineBlockPlacement::selectBestSuccessor( > - MachineBasicBlock *BB, BlockChain &Chain, > - const BlockFilterSet *BlockFilter) { > + const MachineBasicBlock *BB, const BlockChain &Chain, > + const BlockFilterSet *BlockFilter) const { > const BranchProbability HotProb(4, 5); // 80% > > MachineBasicBlock *BestSucc = 0; > @@ -329,12 +328,11 @@ > uint32_t WeightScale = 0; > uint32_t SumWeight = MBPI->getSumForBlock(BB, WeightScale); > DEBUG(dbgs() << "Attempting merge from: " << getBlockName(BB) << "\n"); > - for (MachineBasicBlock::succ_iterator SI = BB->succ_begin(), > - SE = BB->succ_end(); > - SI != SE; ++SI) { > + for (MachineBasicBlock::const_succ_iterator SI = BB->succ_begin(), > + SE = BB->succ_end(); SI != SE; ++SI) { > if (BlockFilter && !BlockFilter->count(*SI)) > continue; > - BlockChain &SuccChain = *BlockToChain[*SI]; > + const BlockChain &SuccChain = *BlockToChain.lookup(*SI); > if (&SuccChain == &Chain) { > DEBUG(dbgs() << " " << getBlockName(*SI) << " -> Already merged!\n"); > continue; > @@ -364,7 +362,7 @@ > PE = (*SI)->pred_end(); > PI != PE; ++PI) { > if (*PI == *SI || (BlockFilter && !BlockFilter->count(*PI)) || > - BlockToChain[*PI] == &Chain) > + BlockToChain.lookup(*PI) == &Chain) > continue; > BlockFrequency PredEdgeFreq > = MBFI->getBlockFreq(*PI) * MBPI->getEdgeProbability(*PI, *SI); > @@ -420,8 +418,8 @@ > /// > /// \returns The best block found, or null if none are viable. > MachineBasicBlock *MachineBlockPlacement::selectBestCandidateBlock( > - BlockChain &Chain, SmallVectorImpl &WorkList, > - const BlockFilterSet *BlockFilter) { > + const BlockChain &Chain, SmallVectorImpl &WorkList, > + const BlockFilterSet *BlockFilter) const { > // Once we need to walk the worklist looking for a candidate, cleanup the > // worklist of already placed entries. > // FIXME: If this shows up on profiles, it could be folded (at the cost of > @@ -436,7 +434,7 @@ > WBE = WorkList.end(); > WBI != WBE; ++WBI) { > assert(!BlockFilter || BlockFilter->count(*WBI)); > - BlockChain &SuccChain = *BlockToChain[*WBI]; > + const BlockChain &SuccChain = *BlockToChain.lookup(*WBI); > if (&SuccChain == &Chain) { > DEBUG(dbgs() << " " << getBlockName(*WBI) > << " -> Already merged!\n"); > @@ -465,17 +463,17 @@ > MachineBasicBlock *MachineBlockPlacement::getFirstUnplacedBlock( > MachineFunction &F, const BlockChain &PlacedChain, > MachineFunction::iterator &PrevUnplacedBlockIt, > - const BlockFilterSet *BlockFilter) { > + const BlockFilterSet *BlockFilter) const { > for (MachineFunction::iterator I = PrevUnplacedBlockIt, E = F.end(); I != E; > ++I) { > if (BlockFilter && !BlockFilter->count(I)) > continue; > - if (BlockToChain[I] != &PlacedChain) { > + if (BlockToChain.lookup(I) != &PlacedChain) { > PrevUnplacedBlockIt = I; > // Now select the head of the chain to which the unplaced block belongs > // as the block to place. This will force the entire chain to be placed, > // and satisfies the requirements of merging chains. > - return *BlockToChain[I]->begin(); > + return *BlockToChain.lookup(I)->begin(); > } > } > return 0; > @@ -485,9 +483,9 @@ > MachineBasicBlock *BB, > BlockChain &Chain, > SmallVectorImpl &BlockWorkList, > - const BlockFilterSet *BlockFilter) { > + const BlockFilterSet *BlockFilter) const { > assert(BB); > - assert(BlockToChain[BB] == &Chain); > + assert(BlockToChain.lookup(BB) == &Chain); > MachineFunction &F = *BB->getParent(); > MachineFunction::iterator PrevUnplacedBlockIt = F.begin(); > > @@ -496,7 +494,7 @@ > BB = *llvm::prior(Chain.end()); > for (;;) { > assert(BB); > - assert(BlockToChain[BB] == &Chain); > + assert(BlockToChain.lookup(BB) == &Chain); > assert(*llvm::prior(Chain.end()) == BB); > MachineBasicBlock *BestSucc = 0; > > @@ -521,7 +519,7 @@ > } > > // Place this block, updating the datastructures to reflect its placement. > - BlockChain &SuccChain = *BlockToChain[BestSucc]; > + BlockChain &SuccChain = *BlockToChain.lookup(BestSucc); > // Zero out LoopPredecessors for the successor we're about to merge in case > // we selected a successor that didn't fit naturally into the CFG. > SuccChain.LoopPredecessors = 0; > @@ -544,7 +542,7 @@ > MachineBasicBlock * > MachineBlockPlacement::findBestLoopTop(MachineFunction &F, > MachineLoop &L, > - const BlockFilterSet &LoopBlockSet) { > + const BlockFilterSet > &LoopBlockSet) const { > BlockFrequency BestExitEdgeFreq; > MachineBasicBlock *ExitingBB = 0; > MachineBasicBlock *LoopingBB = 0; > @@ -558,7 +556,7 @@ > for (MachineLoop::block_iterator I = L.block_begin(), > E = L.block_end(); > I != E; ++I) { > - BlockChain &Chain = *BlockToChain[*I]; > + const BlockChain &Chain = *BlockToChain.lookup(*I); > // Ensure that this block is at the end of a chain; otherwise it could be > // mid-way through an inner loop or a successor of an analyzable branch. > if (*I != *llvm::prior(Chain.end())) > @@ -588,7 +586,7 @@ > continue; > if (*SI == *I) > continue; > - BlockChain &SuccChain = *BlockToChain[*SI]; > + const BlockChain &SuccChain = *BlockToChain.lookup(*SI); > // Don't split chains, either this chain or the successor's chain. > if (&Chain == &SuccChain || *SI != *SuccChain.begin()) { > DEBUG(dbgs() << " " << (LoopBlockSet.count(*SI) ? "looping: " > @@ -665,7 +663,7 @@ > /// both preserves the topological structure and minimizes taken conditional > /// branches. > void MachineBlockPlacement::buildLoopChains(MachineFunction &F, > - MachineLoop &L) { > + MachineLoop &L) const { > // First recurse through any nested loops, building chains for those inner > // loops. > for (MachineLoop::iterator LI = L.begin(), LE = L.end(); LI != LE; ++LI) > @@ -675,29 +673,29 @@ > BlockFilterSet LoopBlockSet(L.block_begin(), L.block_end()); > > MachineBasicBlock *LayoutTop = findBestLoopTop(F, L, LoopBlockSet); > - BlockChain &LoopChain = *BlockToChain[LayoutTop]; > + BlockChain &LoopChain = *BlockToChain.lookup(LayoutTop); > > // FIXME: This is a really lame way of walking the chains in the loop: we > // walk the blocks, and use a set to prevent visiting a particular chain > // twice. > - SmallPtrSet UpdatedPreds; > + SmallPtrSet UpdatedPreds; > assert(LoopChain.LoopPredecessors == 0); > UpdatedPreds.insert(&LoopChain); > for (MachineLoop::block_iterator BI = L.block_begin(), > BE = L.block_end(); > BI != BE; ++BI) { > - BlockChain &Chain = *BlockToChain[*BI]; > + BlockChain &Chain = *BlockToChain.lookup(*BI); > if (!UpdatedPreds.insert(&Chain)) > continue; > > assert(Chain.LoopPredecessors == 0); > for (BlockChain::iterator BCI = Chain.begin(), BCE = Chain.end(); > BCI != BCE; ++BCI) { > - assert(BlockToChain[*BCI] == &Chain); > + assert(BlockToChain.lookup(*BCI) == &Chain); > for (MachineBasicBlock::pred_iterator PI = (*BCI)->pred_begin(), > PE = (*BCI)->pred_end(); > PI != PE; ++PI) { > - if (BlockToChain[*PI] == &Chain || !LoopBlockSet.count(*PI)) > + if (BlockToChain.lookup(*PI) == &Chain || !LoopBlockSet.count(*PI)) > continue; > ++Chain.LoopPredecessors; > } > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From chandlerc at google.com Wed Dec 21 16:11:16 2011 From: chandlerc at google.com (Chandler Carruth) Date: Wed, 21 Dec 2011 14:11:16 -0800 Subject: [llvm-commits] [llvm] r147090 - /llvm/trunk/lib/CodeGen/MachineBlockPlacement.cpp In-Reply-To: <1F4292AB-5A70-48AB-9AE2-A4D6DFFD196B@gmail.com> References: <-5322339473606123382@unknownmsgid> <1F4292AB-5A70-48AB-9AE2-A4D6DFFD196B@gmail.com> Message-ID: On Wed, Dec 21, 2011 at 2:00 PM, Jakub Staszak wrote: > operator[] inserts an object for key if it doesn't exist. > > // X is empty > if (X[0] == a) { } > if (X[1] == b) { } > if (X[2] == c) { } > // X.size() = 3 > > This is the way that std::map works. I believe we want to be quite > compatible here. Certainly, but is it actually cheaper if you know ahead of time that no such insertion will occur? I would expect the lookup path to a hot path through the [] operators. To be honest, I'm beginning to question the entire patch. No insertion ever happens with these [] uses, and they seem more readable to me than lookup... I don't feel strongly about the lookup, but I do feel strongly about the const thing. I'd really rather you strip back out all the const here. -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20111221/38759749/attachment.html From dblaikie at gmail.com Wed Dec 21 16:25:35 2011 From: dblaikie at gmail.com (David Blaikie) Date: Wed, 21 Dec 2011 14:25:35 -0800 Subject: [llvm-commits] [llvm] r147090 - /llvm/trunk/lib/CodeGen/MachineBlockPlacement.cpp Message-ID: <4516045828442472123@unknownmsgid> Ah, fair, sorry (chandler has a reasonable point that [] shouldn't be much more costly than lookup for already existing elements, too though - but at least I can see that there could be some benefit) (I think I just jumped/was reminded of another lookup perf quirk in one of llvms containers that should be fixed (I think it was count being being observably faster than find != end)) From: Jakub Staszak Sent: 12/21/2011 12:00 PM To: llvm-commits at cs.uiuc.edu Cc: David Blaikie Subject: Re: [llvm-commits] [llvm] r147090 - /llvm/trunk/lib/CodeGen/MachineBlockPlacement.cpp operator[] inserts an object for key if it doesn't exist. // X is empty if (X[0] == a) { } if (X[1] == b) { } if (X[2] == c) { } // X.size() = 3 This is the way that std::map works. I believe we want to be quite compatible here. - Kuba On Dec 21, 2011, at 10:53 PM, David Blaikie wrote: > Is there any reason lookup should be cheaper than []? Should we just be > fixing the container? > From: Jakub Staszak > Sent: 12/21/2011 10:24 AM > To: llvm-commits at cs.uiuc.edu > Subject: [llvm-commits] [llvm] r147090 > - /llvm/trunk/lib/CodeGen/MachineBlockPlacement.cpp > Author: kuba > Date: Wed Dec 21 14:18:54 2011 > New Revision: 147090 > > URL: http://llvm.org/viewvc/llvm-project?rev=147090&view=rev > Log: > - Change a few operator[] to lookup which is cheaper. > - Add some constantness. > > Modified: > llvm/trunk/lib/CodeGen/MachineBlockPlacement.cpp > > Modified: llvm/trunk/lib/CodeGen/MachineBlockPlacement.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineBlockPlacement.cpp?rev=147090&r1=147089&r2=147090&view=diff > ============================================================================== > --- llvm/trunk/lib/CodeGen/MachineBlockPlacement.cpp (original) > +++ llvm/trunk/lib/CodeGen/MachineBlockPlacement.cpp Wed Dec 21 14:18:54 2011 > @@ -116,7 +116,7 @@ > /// a contiguous sequence of basic blocks, updating the edge list, and > /// updating the block -> chain mapping. It does not free or tear down the > /// old chain, but the old chain's block list is no longer valid. > - void merge(MachineBasicBlock *BB, BlockChain *Chain) { > + void merge(MachineBasicBlock *BB, const BlockChain *Chain) { > assert(BB); > assert(!Blocks.empty()); > > @@ -185,28 +185,27 @@ > /// between basic blocks. > DenseMap BlockToChain; > > - void markChainSuccessors(BlockChain &Chain, > - MachineBasicBlock *LoopHeaderBB, > + void markChainSuccessors(const BlockChain &Chain, > + const MachineBasicBlock *LoopHeaderBB, > SmallVectorImpl &BlockWorkList, > - const BlockFilterSet *BlockFilter = 0); > - MachineBasicBlock *selectBestSuccessor(MachineBasicBlock *BB, > - BlockChain &Chain, > - const BlockFilterSet *BlockFilter); > + const BlockFilterSet *BlockFilter = 0) const; > + MachineBasicBlock *selectBestSuccessor(const MachineBasicBlock *BB, > + const BlockChain &Chain, const BlockFilterSet *BlockFilter) const; > MachineBasicBlock *selectBestCandidateBlock( > - BlockChain &Chain, SmallVectorImpl &WorkList, > - const BlockFilterSet *BlockFilter); > + const BlockChain &Chain, SmallVectorImpl &WorkList, > + const BlockFilterSet *BlockFilter) const; > MachineBasicBlock *getFirstUnplacedBlock( > MachineFunction &F, > const BlockChain &PlacedChain, > MachineFunction::iterator &PrevUnplacedBlockIt, > - const BlockFilterSet *BlockFilter); > + const BlockFilterSet *BlockFilter) const; > void buildChain(MachineBasicBlock *BB, BlockChain &Chain, > SmallVectorImpl &BlockWorkList, > - const BlockFilterSet *BlockFilter = 0); > + const BlockFilterSet *BlockFilter = 0) const; > MachineBasicBlock *findBestLoopTop(MachineFunction &F, > MachineLoop &L, > - const BlockFilterSet &LoopBlockSet); > - void buildLoopChains(MachineFunction &F, MachineLoop &L); > + const BlockFilterSet &LoopBlockSet) const; > + void buildLoopChains(MachineFunction &F, MachineLoop &L) const; > void buildCFGChains(MachineFunction &F); > void AlignLoops(MachineFunction &F); > > @@ -246,7 +245,7 @@ > /// \brief Helper to print the name of a MBB. > /// > /// Only used by debug logging. > -static std::string getBlockName(MachineBasicBlock *BB) { > +static std::string getBlockName(const MachineBasicBlock *BB) { > std::string Result; > raw_string_ostream OS(Result); > OS << "BB#" << BB->getNumber() > @@ -258,7 +257,7 @@ > /// \brief Helper to print the number of a MBB. > /// > /// Only used by debug logging. > -static std::string getBlockNum(MachineBasicBlock *BB) { > +static std::string getBlockNum(const MachineBasicBlock *BB) { > std::string Result; > raw_string_ostream OS(Result); > OS << "BB#" << BB->getNumber(); > @@ -274,10 +273,10 @@ > /// having one fewer active predecessor. It also adds any successors of this > /// chain which reach the zero-predecessor state to the worklist passed in. > void MachineBlockPlacement::markChainSuccessors( > - BlockChain &Chain, > - MachineBasicBlock *LoopHeaderBB, > + const BlockChain &Chain, > + const MachineBasicBlock *LoopHeaderBB, > SmallVectorImpl &BlockWorkList, > - const BlockFilterSet *BlockFilter) { > + const BlockFilterSet *BlockFilter) const { > // Walk all the blocks in this chain, marking their successors as having > // a predecessor placed. > for (BlockChain::iterator CBI = Chain.begin(), CBE = Chain.end(); > @@ -291,7 +290,7 @@ > SI != SE; ++SI) { > if (BlockFilter && !BlockFilter->count(*SI)) > continue; > - BlockChain &SuccChain = *BlockToChain[*SI]; > + BlockChain &SuccChain = *BlockToChain.lookup(*SI); > // Disregard edges within a fixed chain, or edges to the loop header. > if (&Chain == &SuccChain || *SI == LoopHeaderBB) > continue; > @@ -314,8 +313,8 @@ > /// > /// \returns The best successor block found, or null if none are viable. > MachineBasicBlock *MachineBlockPlacement::selectBestSuccessor( > - MachineBasicBlock *BB, BlockChain &Chain, > - const BlockFilterSet *BlockFilter) { > + const MachineBasicBlock *BB, const BlockChain &Chain, > + const BlockFilterSet *BlockFilter) const { > const BranchProbability HotProb(4, 5); // 80% > > MachineBasicBlock *BestSucc = 0; > @@ -329,12 +328,11 @@ > uint32_t WeightScale = 0; > uint32_t SumWeight = MBPI->getSumForBlock(BB, WeightScale); > DEBUG(dbgs() << "Attempting merge from: " << getBlockName(BB) << "\n"); > - for (MachineBasicBlock::succ_iterator SI = BB->succ_begin(), > - SE = BB->succ_end(); > - SI != SE; ++SI) { > + for (MachineBasicBlock::const_succ_iterator SI = BB->succ_begin(), > + SE = BB->succ_end(); SI != SE; ++SI) { > if (BlockFilter && !BlockFilter->count(*SI)) > continue; > - BlockChain &SuccChain = *BlockToChain[*SI]; > + const BlockChain &SuccChain = *BlockToChain.lookup(*SI); > if (&SuccChain == &Chain) { > DEBUG(dbgs() << " " << getBlockName(*SI) << " -> Already merged!\n"); > continue; > @@ -364,7 +362,7 @@ > PE = (*SI)->pred_end(); > PI != PE; ++PI) { > if (*PI == *SI || (BlockFilter && !BlockFilter->count(*PI)) || > - BlockToChain[*PI] == &Chain) > + BlockToChain.lookup(*PI) == &Chain) > continue; > BlockFrequency PredEdgeFreq > = MBFI->getBlockFreq(*PI) * MBPI->getEdgeProbability(*PI, *SI); > @@ -420,8 +418,8 @@ > /// > /// \returns The best block found, or null if none are viable. > MachineBasicBlock *MachineBlockPlacement::selectBestCandidateBlock( > - BlockChain &Chain, SmallVectorImpl &WorkList, > - const BlockFilterSet *BlockFilter) { > + const BlockChain &Chain, SmallVectorImpl &WorkList, > + const BlockFilterSet *BlockFilter) const { > // Once we need to walk the worklist looking for a candidate, cleanup the > // worklist of already placed entries. > // FIXME: If this shows up on profiles, it could be folded (at the cost of > @@ -436,7 +434,7 @@ > WBE = WorkList.end(); > WBI != WBE; ++WBI) { > assert(!BlockFilter || BlockFilter->count(*WBI)); > - BlockChain &SuccChain = *BlockToChain[*WBI]; > + const BlockChain &SuccChain = *BlockToChain.lookup(*WBI); > if (&SuccChain == &Chain) { > DEBUG(dbgs() << " " << getBlockName(*WBI) > << " -> Already merged!\n"); > @@ -465,17 +463,17 @@ > MachineBasicBlock *MachineBlockPlacement::getFirstUnplacedBlock( > MachineFunction &F, const BlockChain &PlacedChain, > MachineFunction::iterator &PrevUnplacedBlockIt, > - const BlockFilterSet *BlockFilter) { > + const BlockFilterSet *BlockFilter) const { > for (MachineFunction::iterator I = PrevUnplacedBlockIt, E = F.end(); I != E; > ++I) { > if (BlockFilter && !BlockFilter->count(I)) > continue; > - if (BlockToChain[I] != &PlacedChain) { > + if (BlockToChain.lookup(I) != &PlacedChain) { > PrevUnplacedBlockIt = I; > // Now select the head of the chain to which the unplaced block belongs > // as the block to place. This will force the entire chain to be placed, > // and satisfies the requirements of merging chains. > - return *BlockToChain[I]->begin(); > + return *BlockToChain.lookup(I)->begin(); > } > } > return 0; > @@ -485,9 +483,9 @@ > MachineBasicBlock *BB, > BlockChain &Chain, > SmallVectorImpl &BlockWorkList, > - const BlockFilterSet *BlockFilter) { > + const BlockFilterSet *BlockFilter) const { > assert(BB); > - assert(BlockToChain[BB] == &Chain); > + assert(BlockToChain.lookup(BB) == &Chain); > MachineFunction &F = *BB->getParent(); > MachineFunction::iterator PrevUnplacedBlockIt = F.begin(); > > @@ -496,7 +494,7 @@ > BB = *llvm::prior(Chain.end()); > for (;;) { > assert(BB); > - assert(BlockToChain[BB] == &Chain); > + assert(BlockToChain.lookup(BB) == &Chain); > assert(*llvm::prior(Chain.end()) == BB); > MachineBasicBlock *BestSucc = 0; > > @@ -521,7 +519,7 @@ > } > > // Place this block, updating the datastructures to reflect its placement. > - BlockChain &SuccChain = *BlockToChain[BestSucc]; > + BlockChain &SuccChain = *BlockToChain.lookup(BestSucc); > // Zero out LoopPredecessors for the successor we're about to merge in case > // we selected a successor that didn't fit naturally into the CFG. > SuccChain.LoopPredecessors = 0; > @@ -544,7 +542,7 @@ > MachineBasicBlock * > MachineBlockPlacement::findBestLoopTop(MachineFunction &F, > MachineLoop &L, > - const BlockFilterSet &LoopBlockSet) { > + const BlockFilterSet > &LoopBlockSet) const { > BlockFrequency BestExitEdgeFreq; > MachineBasicBlock *ExitingBB = 0; > MachineBasicBlock *LoopingBB = 0; > @@ -558,7 +556,7 @@ > for (MachineLoop::block_iterator I = L.block_begin(), > E = L.block_end(); > I != E; ++I) { > - BlockChain &Chain = *BlockToChain[*I]; > + const BlockChain &Chain = *BlockToChain.lookup(*I); > // Ensure that this block is at the end of a chain; otherwise it could be > // mid-way through an inner loop or a successor of an analyzable branch. > if (*I != *llvm::prior(Chain.end())) > @@ -588,7 +586,7 @@ > continue; > if (*SI == *I) > continue; > - BlockChain &SuccChain = *BlockToChain[*SI]; > + const BlockChain &SuccChain = *BlockToChain.lookup(*SI); > // Don't split chains, either this chain or the successor's chain. > if (&Chain == &SuccChain || *SI != *SuccChain.begin()) { > DEBUG(dbgs() << " " << (LoopBlockSet.count(*SI) ? "looping: " > @@ -665,7 +663,7 @@ > /// both preserves the topological structure and minimizes taken conditional > /// branches. > void MachineBlockPlacement::buildLoopChains(MachineFunction &F, > - MachineLoop &L) { > + MachineLoop &L) const { > // First recurse through any nested loops, building chains for those inner > // loops. > for (MachineLoop::iterator LI = L.begin(), LE = L.end(); LI != LE; ++LI) > @@ -675,29 +673,29 @@ > BlockFilterSet LoopBlockSet(L.block_begin(), L.block_end()); > > MachineBasicBlock *LayoutTop = findBestLoopTop(F, L, LoopBlockSet); > - BlockChain &LoopChain = *BlockToChain[LayoutTop]; > + BlockChain &LoopChain = *BlockToChain.lookup(LayoutTop); > > // FIXME: This is a really lame way of walking the chains in the loop: we > // walk the blocks, and use a set to prevent visiting a particular chain > // twice. > - SmallPtrSet UpdatedPreds; > + SmallPtrSet UpdatedPreds; > assert(LoopChain.LoopPredecessors == 0); > UpdatedPreds.insert(&LoopChain); > for (MachineLoop::block_iterator BI = L.block_begin(), > BE = L.block_end(); > BI != BE; ++BI) { > - BlockChain &Chain = *BlockToChain[*BI]; > + BlockChain &Chain = *BlockToChain.lookup(*BI); > if (!UpdatedPreds.insert(&Chain)) > continue; > > assert(Chain.LoopPredecessors == 0); > for (BlockChain::iterator BCI = Chain.begin(), BCE = Chain.end(); > BCI != BCE; ++BCI) { > - assert(BlockToChain[*BCI] == &Chain); > + assert(BlockToChain.lookup(*BCI) == &Chain); > for (MachineBasicBlock::pred_iterator PI = (*BCI)->pred_begin(), > PE = (*BCI)->pred_end(); > PI != PE; ++PI) { > - if (BlockToChain[*PI] == &Chain || !LoopBlockSet.count(*PI)) > + if (BlockToChain.lookup(*PI) == &Chain || !LoopBlockSet.count(*PI)) > continue; > ++Chain.LoopPredecessors; > } > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From andy.zhang at intel.com Wed Dec 21 16:28:29 2011 From: andy.zhang at intel.com (Zhang, Andy) Date: Wed, 21 Dec 2011 15:28:29 -0700 Subject: [llvm-commits] Intel Atom optimization - use LEA to adjust stack pointer Message-ID: <9A83F73AEA08BB46A2799C5D4C16BFED011A38BC09@rrsmsx509.amr.corp.intel.com> Hi all, Please find attached a patch that implements an optimization for the Intel Atom processor. We can avoid an ALU to AGU dependency by using the LEA instruction to update the stack pointer so as to prevent a stall, as recommended by the Intel Optimization Reference Manual (coding rule 5, specifically). Commit message: Use LEA instruction to adjust stack pointer when generating code for Atom to avoid an ALU to AGU dependency (and subsequent stall). - Modified stack pointer adjustment in X86FrameLowering to emit LEA instructions instead of SUB/ADD when Atom is specified or detected. - Created lit tests for allocating on the stack (array and scalars), and calling a function with many arguments. - Modified TableGen to use 'const uint64_t' instead of an anonymous enum when there are more than 32 subtarget features. When compiling with Visual C++, enums are always 'int's, so "1 << 32" overflows. I'd like to commit this to LLVM trunk; your feedback would be most appreciated. Thanks, Andy -------------- next part -------------- A non-text attachment was scrubbed... Name: lea_sp.diff Type: application/octet-stream Size: 11139 bytes Desc: lea_sp.diff Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20111221/215e9e21/attachment.obj From grosbach at apple.com Wed Dec 21 16:30:16 2011 From: grosbach at apple.com (Jim Grosbach) Date: Wed, 21 Dec 2011 22:30:16 -0000 Subject: [llvm-commits] [llvm] r147100 - /llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Message-ID: <20111221223017.03F902A6C12C@llvm.org> Author: grosbach Date: Wed Dec 21 16:30:16 2011 New Revision: 147100 URL: http://llvm.org/viewvc/llvm-project?rev=147100&view=rev Log: ARM asm parser should be more lenient w/ .thumb_func directive. Rather than require the symbol to be explicitly an argument of the directive, allow it to look ahead and grab the symbol from the next non-whitespace line. rdar://10611140 Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp?rev=147100&r1=147099&r2=147100&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp (original) +++ llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Wed Dec 21 16:30:16 2011 @@ -6421,23 +6421,32 @@ const MCAsmInfo &MAI = getParser().getStreamer().getContext().getAsmInfo(); bool isMachO = MAI.hasSubsectionsViaSymbols(); StringRef Name; + bool needFuncName = true; - // Darwin asm has function name after .thumb_func direction + // Darwin asm has (optionally) function name after .thumb_func direction // ELF doesn't if (isMachO) { const AsmToken &Tok = Parser.getTok(); - if (Tok.isNot(AsmToken::Identifier) && Tok.isNot(AsmToken::String)) - return Error(L, "unexpected token in .thumb_func directive"); - Name = Tok.getIdentifier(); - Parser.Lex(); // Consume the identifier token. + if (Tok.isNot(AsmToken::EndOfStatement)) { + if (Tok.isNot(AsmToken::Identifier) && Tok.isNot(AsmToken::String)) + return Error(L, "unexpected token in .thumb_func directive"); + Name = Tok.getIdentifier(); + Parser.Lex(); // Consume the identifier token. + needFuncName = false; + } } - if (getLexer().isNot(AsmToken::EndOfStatement)) + if (getLexer().isNot(AsmToken::EndOfStatement)) return Error(L, "unexpected token in directive"); - Parser.Lex(); + + // Eat the end of statement and any blank lines that follow. + while (getLexer().is(AsmToken::EndOfStatement)) + Parser.Lex(); // FIXME: assuming function name will be the line following .thumb_func - if (!isMachO) { + // We really should be checking the next symbol definition even if there's + // stuff in between. + if (needFuncName) { Name = Parser.getTok().getIdentifier(); } From kubastaszak at gmail.com Wed Dec 21 16:34:29 2011 From: kubastaszak at gmail.com (Jakub Staszak) Date: Wed, 21 Dec 2011 23:34:29 +0100 Subject: [llvm-commits] [llvm] r147090 - /llvm/trunk/lib/CodeGen/MachineBlockPlacement.cpp In-Reply-To: References: <-5322339473606123382@unknownmsgid> <1F4292AB-5A70-48AB-9AE2-A4D6DFFD196B@gmail.com> Message-ID: <0E3456C5-17C8-490D-A5D2-AC9B332F5D29@gmail.com> I have to agree with operator[] vs lookup(). We don't get any benefit here, so there is no point to make code less readable. In this case I'd have to revert the whole patch, because most of these operator[] won't work because of its lack of constantness. - Kuba On Dec 21, 2011, at 11:11 PM, Chandler Carruth wrote: > On Wed, Dec 21, 2011 at 2:00 PM, Jakub Staszak wrote: > operator[] inserts an object for key if it doesn't exist. > > // X is empty > if (X[0] == a) { } > if (X[1] == b) { } > if (X[2] == c) { } > // X.size() = 3 > > This is the way that std::map works. I believe we want to be quite compatible here. > > Certainly, but is it actually cheaper if you know ahead of time that no such insertion will occur? I would expect the lookup path to a hot path through the [] operators. > > To be honest, I'm beginning to question the entire patch. No insertion ever happens with these [] uses, and they seem more readable to me than lookup... I don't feel strongly about the lookup, but I do feel strongly about the const thing. I'd really rather you strip back out all the const here. -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20111221/9d3c2c6f/attachment.html From chandlerc at google.com Wed Dec 21 16:36:06 2011 From: chandlerc at google.com (Chandler Carruth) Date: Wed, 21 Dec 2011 14:36:06 -0800 Subject: [llvm-commits] [llvm] r147090 - /llvm/trunk/lib/CodeGen/MachineBlockPlacement.cpp In-Reply-To: <0E3456C5-17C8-490D-A5D2-AC9B332F5D29@gmail.com> References: <-5322339473606123382@unknownmsgid> <1F4292AB-5A70-48AB-9AE2-A4D6DFFD196B@gmail.com> <0E3456C5-17C8-490D-A5D2-AC9B332F5D29@gmail.com> Message-ID: On Wed, Dec 21, 2011 at 2:34 PM, Jakub Staszak wrote: > I have to agree with operator[] vs lookup(). We don't get any benefit > here, so there is no point to make code less readable. In this case I'd > have to revert the whole patch, because most of these operator[] won't work > because of its lack of constantness. > For reference, I'm fine with that. I don't think constantness is helping this code. > > - Kuba > > On Dec 21, 2011, at 11:11 PM, Chandler Carruth wrote: > > On Wed, Dec 21, 2011 at 2:00 PM, Jakub Staszak wrote: > >> operator[] inserts an object for key if it doesn't exist. >> >> // X is empty >> if (X[0] == a) { } >> if (X[1] == b) { } >> if (X[2] == c) { } >> // X.size() = 3 >> >> This is the way that std::map works. I believe we want to be quite >> compatible here. > > > Certainly, but is it actually cheaper if you know ahead of time that no > such insertion will occur? I would expect the lookup path to a hot path > through the [] operators. > > To be honest, I'm beginning to question the entire patch. No insertion > ever happens with these [] uses, and they seem more readable to me than > lookup... I don't feel strongly about the lookup, but I do feel strongly > about the const thing. I'd really rather you strip back out all the const > here. > > > -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20111221/2c20775a/attachment.html From dblaikie at gmail.com Wed Dec 21 16:54:04 2011 From: dblaikie at gmail.com (David Blaikie) Date: Wed, 21 Dec 2011 14:54:04 -0800 Subject: [llvm-commits] [llvm] r147090 - /llvm/trunk/lib/CodeGen/MachineBlockPlacement.cpp Message-ID: <1142948289857282882@unknownmsgid> (I rather like strict const but it is apparently a deliberate non goal of the code base so I'd say it's probably idiomatic to just revert) ------------------------------ From: Chandler Carruth Sent: 12/21/2011 12:36 PM To: Jakub Staszak Cc: llvm-commits at cs.uiuc.edu; David Blaikie Subject: Re: [llvm-commits] [llvm] r147090 - /llvm/trunk/lib/CodeGen/MachineBlockPlacement.cpp On Wed, Dec 21, 2011 at 2:34 PM, Jakub Staszak wrote: > I have to agree with operator[] vs lookup(). We don't get any benefit > here, so there is no point to make code less readable. In this case I'd > have to revert the whole patch, because most of these operator[] won't work > because of its lack of constantness. > For reference, I'm fine with that. I don't think constantness is helping this code. > > - Kuba > > On Dec 21, 2011, at 11:11 PM, Chandler Carruth wrote: > > On Wed, Dec 21, 2011 at 2:00 PM, Jakub Staszak wrote: > >> operator[] inserts an object for key if it doesn't exist. >> >> // X is empty >> if (X[0] == a) { } >> if (X[1] == b) { } >> if (X[2] == c) { } >> // X.size() = 3 >> >> This is the way that std::map works. I believe we want to be quite >> compatible here. > > > Certainly, but is it actually cheaper if you know ahead of time that no > such insertion will occur? I would expect the lookup path to a hot path > through the [] operators. > > To be honest, I'm beginning to question the entire patch. No insertion > ever happens with these [] uses, and they seem more readable to me than > lookup... I don't feel strongly about the lookup, but I do feel strongly > about the const thing. I'd really rather you strip back out all the const > here. > > > -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20111221/0420715c/attachment.html From kubastaszak at gmail.com Wed Dec 21 17:02:08 2011 From: kubastaszak at gmail.com (Jakub Staszak) Date: Wed, 21 Dec 2011 23:02:08 -0000 Subject: [llvm-commits] [llvm] r147101 - /llvm/trunk/lib/CodeGen/MachineBlockPlacement.cpp Message-ID: <20111221230208.DFE362A6C12C@llvm.org> Author: kuba Date: Wed Dec 21 17:02:08 2011 New Revision: 147101 URL: http://llvm.org/viewvc/llvm-project?rev=147101&view=rev Log: Revert patch from 147090. There is not point to make code less readable if we don't get any serious benefit there. Modified: llvm/trunk/lib/CodeGen/MachineBlockPlacement.cpp Modified: llvm/trunk/lib/CodeGen/MachineBlockPlacement.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineBlockPlacement.cpp?rev=147101&r1=147100&r2=147101&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/MachineBlockPlacement.cpp (original) +++ llvm/trunk/lib/CodeGen/MachineBlockPlacement.cpp Wed Dec 21 17:02:08 2011 @@ -116,7 +116,7 @@ /// a contiguous sequence of basic blocks, updating the edge list, and /// updating the block -> chain mapping. It does not free or tear down the /// old chain, but the old chain's block list is no longer valid. - void merge(MachineBasicBlock *BB, const BlockChain *Chain) { + void merge(MachineBasicBlock *BB, BlockChain *Chain) { assert(BB); assert(!Blocks.empty()); @@ -185,27 +185,28 @@ /// between basic blocks. DenseMap BlockToChain; - void markChainSuccessors(const BlockChain &Chain, - const MachineBasicBlock *LoopHeaderBB, + void markChainSuccessors(BlockChain &Chain, + MachineBasicBlock *LoopHeaderBB, SmallVectorImpl &BlockWorkList, - const BlockFilterSet *BlockFilter = 0) const; - MachineBasicBlock *selectBestSuccessor(const MachineBasicBlock *BB, - const BlockChain &Chain, const BlockFilterSet *BlockFilter) const; + const BlockFilterSet *BlockFilter = 0); + MachineBasicBlock *selectBestSuccessor(MachineBasicBlock *BB, + BlockChain &Chain, + const BlockFilterSet *BlockFilter); MachineBasicBlock *selectBestCandidateBlock( - const BlockChain &Chain, SmallVectorImpl &WorkList, - const BlockFilterSet *BlockFilter) const; + BlockChain &Chain, SmallVectorImpl &WorkList, + const BlockFilterSet *BlockFilter); MachineBasicBlock *getFirstUnplacedBlock( MachineFunction &F, const BlockChain &PlacedChain, MachineFunction::iterator &PrevUnplacedBlockIt, - const BlockFilterSet *BlockFilter) const; + const BlockFilterSet *BlockFilter); void buildChain(MachineBasicBlock *BB, BlockChain &Chain, SmallVectorImpl &BlockWorkList, - const BlockFilterSet *BlockFilter = 0) const; + const BlockFilterSet *BlockFilter = 0); MachineBasicBlock *findBestLoopTop(MachineFunction &F, MachineLoop &L, - const BlockFilterSet &LoopBlockSet) const; - void buildLoopChains(MachineFunction &F, MachineLoop &L) const; + const BlockFilterSet &LoopBlockSet); + void buildLoopChains(MachineFunction &F, MachineLoop &L); void buildCFGChains(MachineFunction &F); void AlignLoops(MachineFunction &F); @@ -245,7 +246,7 @@ /// \brief Helper to print the name of a MBB. /// /// Only used by debug logging. -static std::string getBlockName(const MachineBasicBlock *BB) { +static std::string getBlockName(MachineBasicBlock *BB) { std::string Result; raw_string_ostream OS(Result); OS << "BB#" << BB->getNumber() @@ -257,7 +258,7 @@ /// \brief Helper to print the number of a MBB. /// /// Only used by debug logging. -static std::string getBlockNum(const MachineBasicBlock *BB) { +static std::string getBlockNum(MachineBasicBlock *BB) { std::string Result; raw_string_ostream OS(Result); OS << "BB#" << BB->getNumber(); @@ -273,10 +274,10 @@ /// having one fewer active predecessor. It also adds any successors of this /// chain which reach the zero-predecessor state to the worklist passed in. void MachineBlockPlacement::markChainSuccessors( - const BlockChain &Chain, - const MachineBasicBlock *LoopHeaderBB, + BlockChain &Chain, + MachineBasicBlock *LoopHeaderBB, SmallVectorImpl &BlockWorkList, - const BlockFilterSet *BlockFilter) const { + const BlockFilterSet *BlockFilter) { // Walk all the blocks in this chain, marking their successors as having // a predecessor placed. for (BlockChain::iterator CBI = Chain.begin(), CBE = Chain.end(); @@ -290,7 +291,7 @@ SI != SE; ++SI) { if (BlockFilter && !BlockFilter->count(*SI)) continue; - BlockChain &SuccChain = *BlockToChain.lookup(*SI); + BlockChain &SuccChain = *BlockToChain[*SI]; // Disregard edges within a fixed chain, or edges to the loop header. if (&Chain == &SuccChain || *SI == LoopHeaderBB) continue; @@ -313,8 +314,8 @@ /// /// \returns The best successor block found, or null if none are viable. MachineBasicBlock *MachineBlockPlacement::selectBestSuccessor( - const MachineBasicBlock *BB, const BlockChain &Chain, - const BlockFilterSet *BlockFilter) const { + MachineBasicBlock *BB, BlockChain &Chain, + const BlockFilterSet *BlockFilter) { const BranchProbability HotProb(4, 5); // 80% MachineBasicBlock *BestSucc = 0; @@ -328,11 +329,12 @@ uint32_t WeightScale = 0; uint32_t SumWeight = MBPI->getSumForBlock(BB, WeightScale); DEBUG(dbgs() << "Attempting merge from: " << getBlockName(BB) << "\n"); - for (MachineBasicBlock::const_succ_iterator SI = BB->succ_begin(), - SE = BB->succ_end(); SI != SE; ++SI) { + for (MachineBasicBlock::succ_iterator SI = BB->succ_begin(), + SE = BB->succ_end(); + SI != SE; ++SI) { if (BlockFilter && !BlockFilter->count(*SI)) continue; - const BlockChain &SuccChain = *BlockToChain.lookup(*SI); + BlockChain &SuccChain = *BlockToChain[*SI]; if (&SuccChain == &Chain) { DEBUG(dbgs() << " " << getBlockName(*SI) << " -> Already merged!\n"); continue; @@ -362,7 +364,7 @@ PE = (*SI)->pred_end(); PI != PE; ++PI) { if (*PI == *SI || (BlockFilter && !BlockFilter->count(*PI)) || - BlockToChain.lookup(*PI) == &Chain) + BlockToChain[*PI] == &Chain) continue; BlockFrequency PredEdgeFreq = MBFI->getBlockFreq(*PI) * MBPI->getEdgeProbability(*PI, *SI); @@ -418,8 +420,8 @@ /// /// \returns The best block found, or null if none are viable. MachineBasicBlock *MachineBlockPlacement::selectBestCandidateBlock( - const BlockChain &Chain, SmallVectorImpl &WorkList, - const BlockFilterSet *BlockFilter) const { + BlockChain &Chain, SmallVectorImpl &WorkList, + const BlockFilterSet *BlockFilter) { // Once we need to walk the worklist looking for a candidate, cleanup the // worklist of already placed entries. // FIXME: If this shows up on profiles, it could be folded (at the cost of @@ -434,7 +436,7 @@ WBE = WorkList.end(); WBI != WBE; ++WBI) { assert(!BlockFilter || BlockFilter->count(*WBI)); - const BlockChain &SuccChain = *BlockToChain.lookup(*WBI); + BlockChain &SuccChain = *BlockToChain[*WBI]; if (&SuccChain == &Chain) { DEBUG(dbgs() << " " << getBlockName(*WBI) << " -> Already merged!\n"); @@ -463,17 +465,17 @@ MachineBasicBlock *MachineBlockPlacement::getFirstUnplacedBlock( MachineFunction &F, const BlockChain &PlacedChain, MachineFunction::iterator &PrevUnplacedBlockIt, - const BlockFilterSet *BlockFilter) const { + const BlockFilterSet *BlockFilter) { for (MachineFunction::iterator I = PrevUnplacedBlockIt, E = F.end(); I != E; ++I) { if (BlockFilter && !BlockFilter->count(I)) continue; - if (BlockToChain.lookup(I) != &PlacedChain) { + if (BlockToChain[I] != &PlacedChain) { PrevUnplacedBlockIt = I; // Now select the head of the chain to which the unplaced block belongs // as the block to place. This will force the entire chain to be placed, // and satisfies the requirements of merging chains. - return *BlockToChain.lookup(I)->begin(); + return *BlockToChain[I]->begin(); } } return 0; @@ -483,9 +485,9 @@ MachineBasicBlock *BB, BlockChain &Chain, SmallVectorImpl &BlockWorkList, - const BlockFilterSet *BlockFilter) const { + const BlockFilterSet *BlockFilter) { assert(BB); - assert(BlockToChain.lookup(BB) == &Chain); + assert(BlockToChain[BB] == &Chain); MachineFunction &F = *BB->getParent(); MachineFunction::iterator PrevUnplacedBlockIt = F.begin(); @@ -494,7 +496,7 @@ BB = *llvm::prior(Chain.end()); for (;;) { assert(BB); - assert(BlockToChain.lookup(BB) == &Chain); + assert(BlockToChain[BB] == &Chain); assert(*llvm::prior(Chain.end()) == BB); MachineBasicBlock *BestSucc = 0; @@ -519,7 +521,7 @@ } // Place this block, updating the datastructures to reflect its placement. - BlockChain &SuccChain = *BlockToChain.lookup(BestSucc); + BlockChain &SuccChain = *BlockToChain[BestSucc]; // Zero out LoopPredecessors for the successor we're about to merge in case // we selected a successor that didn't fit naturally into the CFG. SuccChain.LoopPredecessors = 0; @@ -542,7 +544,7 @@ MachineBasicBlock * MachineBlockPlacement::findBestLoopTop(MachineFunction &F, MachineLoop &L, - const BlockFilterSet &LoopBlockSet) const { + const BlockFilterSet &LoopBlockSet) { BlockFrequency BestExitEdgeFreq; MachineBasicBlock *ExitingBB = 0; MachineBasicBlock *LoopingBB = 0; @@ -556,7 +558,7 @@ for (MachineLoop::block_iterator I = L.block_begin(), E = L.block_end(); I != E; ++I) { - const BlockChain &Chain = *BlockToChain.lookup(*I); + BlockChain &Chain = *BlockToChain[*I]; // Ensure that this block is at the end of a chain; otherwise it could be // mid-way through an inner loop or a successor of an analyzable branch. if (*I != *llvm::prior(Chain.end())) @@ -586,7 +588,7 @@ continue; if (*SI == *I) continue; - const BlockChain &SuccChain = *BlockToChain.lookup(*SI); + BlockChain &SuccChain = *BlockToChain[*SI]; // Don't split chains, either this chain or the successor's chain. if (&Chain == &SuccChain || *SI != *SuccChain.begin()) { DEBUG(dbgs() << " " << (LoopBlockSet.count(*SI) ? "looping: " @@ -663,7 +665,7 @@ /// both preserves the topological structure and minimizes taken conditional /// branches. void MachineBlockPlacement::buildLoopChains(MachineFunction &F, - MachineLoop &L) const { + MachineLoop &L) { // First recurse through any nested loops, building chains for those inner // loops. for (MachineLoop::iterator LI = L.begin(), LE = L.end(); LI != LE; ++LI) @@ -673,29 +675,29 @@ BlockFilterSet LoopBlockSet(L.block_begin(), L.block_end()); MachineBasicBlock *LayoutTop = findBestLoopTop(F, L, LoopBlockSet); - BlockChain &LoopChain = *BlockToChain.lookup(LayoutTop); + BlockChain &LoopChain = *BlockToChain[LayoutTop]; // FIXME: This is a really lame way of walking the chains in the loop: we // walk the blocks, and use a set to prevent visiting a particular chain // twice. - SmallPtrSet UpdatedPreds; + SmallPtrSet UpdatedPreds; assert(LoopChain.LoopPredecessors == 0); UpdatedPreds.insert(&LoopChain); for (MachineLoop::block_iterator BI = L.block_begin(), BE = L.block_end(); BI != BE; ++BI) { - BlockChain &Chain = *BlockToChain.lookup(*BI); + BlockChain &Chain = *BlockToChain[*BI]; if (!UpdatedPreds.insert(&Chain)) continue; assert(Chain.LoopPredecessors == 0); for (BlockChain::iterator BCI = Chain.begin(), BCE = Chain.end(); BCI != BCE; ++BCI) { - assert(BlockToChain.lookup(*BCI) == &Chain); + assert(BlockToChain[*BCI] == &Chain); for (MachineBasicBlock::pred_iterator PI = (*BCI)->pred_begin(), PE = (*BCI)->pred_end(); PI != PE; ++PI) { - if (BlockToChain.lookup(*PI) == &Chain || !LoopBlockSet.count(*PI)) + if (BlockToChain[*PI] == &Chain || !LoopBlockSet.count(*PI)) continue; ++Chain.LoopPredecessors; } From kubastaszak at gmail.com Wed Dec 21 17:07:22 2011 From: kubastaszak at gmail.com (Jakub Staszak) Date: Thu, 22 Dec 2011 00:07:22 +0100 Subject: [llvm-commits] [llvm] r147090 - /llvm/trunk/lib/CodeGen/MachineBlockPlacement.cpp In-Reply-To: <1142948289857282882@unknownmsgid> References: <1142948289857282882@unknownmsgid> Message-ID: <8A338110-0136-47C8-AFEC-851E8C3138D5@gmail.com> Reverted in 147101. As you said, there was no point to make code less readable. Thanks! - Kuba On Dec 21, 2011, at 11:54 PM, David Blaikie wrote: > (I rather like strict const but it is apparently a deliberate non goal of the code base so I'd say it's probably idiomatic to just revert) > From: Chandler Carruth > Sent: 12/21/2011 12:36 PM > To: Jakub Staszak > Cc: llvm-commits at cs.uiuc.edu; David Blaikie > Subject: Re: [llvm-commits] [llvm] r147090 - /llvm/trunk/lib/CodeGen/MachineBlockPlacement.cpp > > On Wed, Dec 21, 2011 at 2:34 PM, Jakub Staszak wrote: > I have to agree with operator[] vs lookup(). We don't get any benefit here, so there is no point to make code less readable. In this case I'd have to revert the whole patch, because most of these operator[] won't work because of its lack of constantness. > > For reference, I'm fine with that. I don't think constantness is helping this code. > > > - Kuba > > On Dec 21, 2011, at 11:11 PM, Chandler Carruth wrote: > >> On Wed, Dec 21, 2011 at 2:00 PM, Jakub Staszak wrote: >> operator[] inserts an object for key if it doesn't exist. >> >> // X is empty >> if (X[0] == a) { } >> if (X[1] == b) { } >> if (X[2] == c) { } >> // X.size() = 3 >> >> This is the way that std::map works. I believe we want to be quite compatible here. >> >> Certainly, but is it actually cheaper if you know ahead of time that no such insertion will occur? I would expect the lookup path to a hot path through the [] operators. >> >> To be honest, I'm beginning to question the entire patch. No insertion ever happens with these [] uses, and they seem more readable to me than lookup... I don't feel strongly about the lookup, but I do feel strongly about the const thing. I'd really rather you strip back out all the const here. > > -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20111222/1ec1ce7b/attachment.html From grosbach at apple.com Wed Dec 21 17:04:33 2011 From: grosbach at apple.com (Jim Grosbach) Date: Wed, 21 Dec 2011 23:04:33 -0000 Subject: [llvm-commits] [llvm] r147102 - /llvm/trunk/lib/Target/ARM/ARMInstrNEON.td Message-ID: <20111221230433.5798E2A6C12C@llvm.org> Author: grosbach Date: Wed Dec 21 17:04:33 2011 New Revision: 147102 URL: http://llvm.org/viewvc/llvm-project?rev=147102&view=rev Log: ARM NEON mnemonic aliases for vzipq and vswpq. Modified: llvm/trunk/lib/Target/ARM/ARMInstrNEON.td Modified: llvm/trunk/lib/Target/ARM/ARMInstrNEON.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrNEON.td?rev=147102&r1=147101&r2=147102&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrNEON.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrNEON.td Wed Dec 21 17:04:33 2011 @@ -6076,3 +6076,6 @@ def : NEONMnemonicAlias<"vcleq", "vcle">; def : NEONMnemonicAlias<"vceqq", "vceq">; + +def : NEONMnemonicAlias<"vzipq", "vzip">; +def : NEONMnemonicAlias<"vswpq", "vswp">; From grosbach at apple.com Wed Dec 21 17:09:29 2011 From: grosbach at apple.com (Jim Grosbach) Date: Wed, 21 Dec 2011 23:09:29 -0000 Subject: [llvm-commits] [llvm] r147103 - /llvm/trunk/lib/Target/ARM/ARMInstrNEON.td Message-ID: <20111221230929.3070B2A6C12C@llvm.org> Author: grosbach Date: Wed Dec 21 17:09:28 2011 New Revision: 147103 URL: http://llvm.org/viewvc/llvm-project?rev=147103&view=rev Log: ARM NEON optional data type on VSWP instructions. Modified: llvm/trunk/lib/Target/ARM/ARMInstrNEON.td Modified: llvm/trunk/lib/Target/ARM/ARMInstrNEON.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrNEON.td?rev=147103&r1=147102&r2=147103&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrNEON.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrNEON.td Wed Dec 21 17:09:28 2011 @@ -6033,6 +6033,12 @@ def : NEONInstAlias<"vpadd${p}.f32 $Vdn, $Vm", (VPADDf DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>; +// VSWP allows, but does not require, a type suffix. +defm : VFPDTAnyInstAlias<"vswp${p}", "$Vd, $Vm", + (VSWPd DPR:$Vd, DPR:$Vm, pred:$p)>; +defm : VFPDTAnyInstAlias<"vswp${p}", "$Vd, $Vm", + (VSWPq QPR:$Vd, QPR:$Vm, pred:$p)>; + // "vmov Rd, #-imm" can be handled via "vmvn". def : NEONInstAlias<"vmov${p}.i32 $Vd, $imm", (VMVNv2i32 DPR:$Vd, nImmVMOVI32Neg:$imm, pred:$p)>; From grosbach at apple.com Wed Dec 21 17:24:15 2011 From: grosbach at apple.com (Jim Grosbach) Date: Wed, 21 Dec 2011 23:24:15 -0000 Subject: [llvm-commits] [llvm] r147104 - in /llvm/trunk: lib/Target/ARM/ARMInstrVFP.td test/MC/ARM/simple-fp-encoding.s Message-ID: <20111221232415.C59222A6C12C@llvm.org> Author: grosbach Date: Wed Dec 21 17:24:15 2011 New Revision: 147104 URL: http://llvm.org/viewvc/llvm-project?rev=147104&view=rev Log: ARM VFP optional data type on VMOV GPR<-->SPR. Modified: llvm/trunk/lib/Target/ARM/ARMInstrVFP.td llvm/trunk/test/MC/ARM/simple-fp-encoding.s Modified: llvm/trunk/lib/Target/ARM/ARMInstrVFP.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrVFP.td?rev=147104&r1=147103&r2=147104&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrVFP.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrVFP.td Wed Dec 21 17:24:15 2011 @@ -1240,10 +1240,18 @@ def : VFP2InstAlias<"vsub${p}.f32 $Sn, $Sm", (VSUBS SPR:$Sn, SPR:$Sn, SPR:$Sm, pred:$p)>; -// VMOV can accept optional .f32/.f64 suffix. -def : VFP2InstAlias<"vmov${p}.f32 $Rt, $Sn", +// VMOV can accept optional 32-bit or less data type suffix suffix. +def : VFP2InstAlias<"vmov${p}.8 $Rt, $Sn", (VMOVRS GPR:$Rt, SPR:$Sn, pred:$p)>; -def : VFP2InstAlias<"vmov${p}.f32 $Sn, $Rt", +def : VFP2InstAlias<"vmov${p}.16 $Rt, $Sn", + (VMOVRS GPR:$Rt, SPR:$Sn, pred:$p)>; +def : VFP2InstAlias<"vmov${p}.32 $Rt, $Sn", + (VMOVRS GPR:$Rt, SPR:$Sn, pred:$p)>; +def : VFP2InstAlias<"vmov${p}.8 $Sn, $Rt", + (VMOVSR SPR:$Sn, GPR:$Rt, pred:$p)>; +def : VFP2InstAlias<"vmov${p}.16 $Sn, $Rt", + (VMOVSR SPR:$Sn, GPR:$Rt, pred:$p)>; +def : VFP2InstAlias<"vmov${p}.32 $Sn, $Rt", (VMOVSR SPR:$Sn, GPR:$Rt, pred:$p)>; def : VFP2InstAlias<"vmov${p}.f64 $Rt, $Rt2, $Dn", Modified: llvm/trunk/test/MC/ARM/simple-fp-encoding.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/simple-fp-encoding.s?rev=147104&r1=147103&r2=147104&view=diff ============================================================================== --- llvm/trunk/test/MC/ARM/simple-fp-encoding.s (original) +++ llvm/trunk/test/MC/ARM/simple-fp-encoding.s Wed Dec 21 17:24:15 2011 @@ -271,3 +271,31 @@ @ CHECK: vmovne s25, s26, r2, r5 vmovne s25, s26, r2, r5 @ encoding: [0x39,0x2a,0x45,0x1c] + +@ VMOV w/ optional data type suffix. + vmov.32 s1, r8 + vmov.s16 s2, r4 + vmov.16 s3, r6 + vmov.u32 s4, r1 + vmov.p8 s5, r2 + vmov.8 s6, r3 + + vmov.32 r1, s8 + vmov.s16 r2, s4 + vmov.16 r3, s6 + vmov.u32 r4, s1 + vmov.p8 r5, s2 + vmov.8 r6, s3 + +@ CHECK: vmov s1, r8 @ encoding: [0x90,0x8a,0x00,0xee] +@ CHECK: vmov s2, r4 @ encoding: [0x10,0x4a,0x01,0xee] +@ CHECK: vmov s3, r6 @ encoding: [0x90,0x6a,0x01,0xee] +@ CHECK: vmov s4, r1 @ encoding: [0x10,0x1a,0x02,0xee] +@ CHECK: vmov s5, r2 @ encoding: [0x90,0x2a,0x02,0xee] +@ CHECK: vmov s6, r3 @ encoding: [0x10,0x3a,0x03,0xee] +@ CHECK: vmov r1, s8 @ encoding: [0x10,0x1a,0x14,0xee] +@ CHECK: vmov r2, s4 @ encoding: [0x10,0x2a,0x12,0xee] +@ CHECK: vmov r3, s6 @ encoding: [0x10,0x3a,0x13,0xee] +@ CHECK: vmov r4, s1 @ encoding: [0x90,0x4a,0x10,0xee] +@ CHECK: vmov r5, s2 @ encoding: [0x10,0x5a,0x11,0xee] +@ CHECK: vmov r6, s3 @ encoding: [0x90,0x6a,0x11,0xee] From grosbach at apple.com Wed Dec 21 17:52:37 2011 From: grosbach at apple.com (Jim Grosbach) Date: Wed, 21 Dec 2011 23:52:37 -0000 Subject: [llvm-commits] [llvm] r147109 - /llvm/trunk/lib/Target/ARM/ARMInstrNEON.td Message-ID: <20111221235237.9352C2A6C12C@llvm.org> Author: grosbach Date: Wed Dec 21 17:52:37 2011 New Revision: 147109 URL: http://llvm.org/viewvc/llvm-project?rev=147109&view=rev Log: ARM NEON mnemonic aliase for vrecpeq. Modified: llvm/trunk/lib/Target/ARM/ARMInstrNEON.td Modified: llvm/trunk/lib/Target/ARM/ARMInstrNEON.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrNEON.td?rev=147109&r1=147108&r2=147109&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrNEON.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrNEON.td Wed Dec 21 17:52:37 2011 @@ -6085,3 +6085,6 @@ def : NEONMnemonicAlias<"vzipq", "vzip">; def : NEONMnemonicAlias<"vswpq", "vswp">; + +def : NEONMnemonicAlias<"vrecpeq.f32", "vrecpe.f32">; +def : NEONMnemonicAlias<"vrecpeq.u32", "vrecpe.u32">; From lhames at gmail.com Wed Dec 21 18:12:51 2011 From: lhames at gmail.com (Lang Hames) Date: Thu, 22 Dec 2011 00:12:51 -0000 Subject: [llvm-commits] [llvm] r147113 - /llvm/trunk/include/llvm/ADT/IntervalMap.h Message-ID: <20111222001251.5C1CE2A6C12C@llvm.org> Author: lhames Date: Wed Dec 21 18:12:51 2011 New Revision: 147113 URL: http://llvm.org/viewvc/llvm-project?rev=147113&view=rev Log: Fixed typo. Modified: llvm/trunk/include/llvm/ADT/IntervalMap.h Modified: llvm/trunk/include/llvm/ADT/IntervalMap.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/ADT/IntervalMap.h?rev=147113&r1=147112&r2=147113&view=diff ============================================================================== --- llvm/trunk/include/llvm/ADT/IntervalMap.h (original) +++ llvm/trunk/include/llvm/ADT/IntervalMap.h Wed Dec 21 18:12:51 2011 @@ -739,7 +739,7 @@ // A Path is used by iterators to represent a position in a B+-tree, and the // path to get there from the root. // -// The Path class also constains the tree navigation code that doesn't have to +// The Path class also contains the tree navigation code that doesn't have to // be templatized. // //===----------------------------------------------------------------------===// From rafael.espindola at gmail.com Wed Dec 21 18:21:50 2011 From: rafael.espindola at gmail.com (Rafael Espindola) Date: Thu, 22 Dec 2011 00:21:50 -0000 Subject: [llvm-commits] [llvm] r147114 - in /llvm/trunk/lib/MC: ELFObjectWriter.cpp ELFObjectWriter.h Message-ID: <20111222002151.02CBE2A6C12C@llvm.org> Author: rafael Date: Wed Dec 21 18:21:50 2011 New Revision: 147114 URL: http://llvm.org/viewvc/llvm-project?rev=147114&view=rev Log: getEFlags is const. Modified: llvm/trunk/lib/MC/ELFObjectWriter.cpp llvm/trunk/lib/MC/ELFObjectWriter.h Modified: llvm/trunk/lib/MC/ELFObjectWriter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/ELFObjectWriter.cpp?rev=147114&r1=147113&r2=147114&view=diff ============================================================================== --- llvm/trunk/lib/MC/ELFObjectWriter.cpp (original) +++ llvm/trunk/lib/MC/ELFObjectWriter.cpp Wed Dec 21 18:21:50 2011 @@ -1296,7 +1296,7 @@ {} // FIXME: get the real EABI Version from the Triple. -unsigned ARMELFObjectWriter::getEFlags() { +unsigned ARMELFObjectWriter::getEFlags() const { return ELF::EF_ARM_EABIMASK & DefaultEABIVersion; } @@ -1646,7 +1646,7 @@ MipsELFObjectWriter::~MipsELFObjectWriter() {} // FIXME: get the real EABI Version from the Triple. -unsigned MipsELFObjectWriter::getEFlags() { +unsigned MipsELFObjectWriter::getEFlags() const { return ELF::EF_MIPS_NOREORDER | ELF::EF_MIPS_ARCH_32R2; } Modified: llvm/trunk/lib/MC/ELFObjectWriter.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/ELFObjectWriter.h?rev=147114&r1=147113&r2=147114&view=diff ============================================================================== --- llvm/trunk/lib/MC/ELFObjectWriter.h (original) +++ llvm/trunk/lib/MC/ELFObjectWriter.h Wed Dec 21 18:21:50 2011 @@ -244,7 +244,7 @@ unsigned NumberOfSections); /// Default e_flags = 0 - virtual unsigned getEFlags() { return 0; } + virtual unsigned getEFlags() const { return 0; } virtual void WriteSymbolEntry(MCDataFragment *SymtabF, MCDataFragment *ShndxF, @@ -369,7 +369,7 @@ virtual ~ARMELFObjectWriter(); - virtual unsigned getEFlags(); + virtual unsigned getEFlags() const; protected: virtual const MCSymbol *ExplicitRelSym(const MCAssembler &Asm, const MCValue &Target, @@ -425,7 +425,7 @@ bool IsLittleEndian); virtual ~MipsELFObjectWriter(); - virtual unsigned getEFlags(); + virtual unsigned getEFlags() const; protected: virtual const MCSymbol *ExplicitRelSym(const MCAssembler &Asm, From rafael.espindola at gmail.com Wed Dec 21 18:37:50 2011 From: rafael.espindola at gmail.com (Rafael Espindola) Date: Thu, 22 Dec 2011 00:37:50 -0000 Subject: [llvm-commits] [llvm] r147115 - in /llvm/trunk: include/llvm/MC/MCELFObjectWriter.h lib/MC/ELFObjectWriter.cpp lib/MC/ELFObjectWriter.h lib/MC/MCELFObjectTargetWriter.cpp lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp lib/Target/ARM/MCTargetDesc/ARMELFObjectWriter.cpp lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.h Message-ID: <20111222003751.0BD9E2A6C12C@llvm.org> Author: rafael Date: Wed Dec 21 18:37:50 2011 New Revision: 147115 URL: http://llvm.org/viewvc/llvm-project?rev=147115&view=rev Log: Move the ARM specific parts of the ELF writer to Target/ARM. Added: llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMELFObjectWriter.cpp Modified: llvm/trunk/include/llvm/MC/MCELFObjectWriter.h llvm/trunk/lib/MC/ELFObjectWriter.cpp llvm/trunk/lib/MC/ELFObjectWriter.h llvm/trunk/lib/MC/MCELFObjectTargetWriter.cpp llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.h Modified: llvm/trunk/include/llvm/MC/MCELFObjectWriter.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/MC/MCELFObjectWriter.h?rev=147115&r1=147114&r2=147115&view=diff ============================================================================== --- llvm/trunk/include/llvm/MC/MCELFObjectWriter.h (original) +++ llvm/trunk/include/llvm/MC/MCELFObjectWriter.h Wed Dec 21 18:37:50 2011 @@ -43,6 +43,12 @@ virtual unsigned GetRelocType(const MCValue &Target, const MCFixup &Fixup, bool IsPCRel, bool IsRelocWithSymbol, int64_t Addend) const; // FIXME: add = 0 + virtual unsigned getEFlags() const; + virtual const MCSymbol *ExplicitRelSym(const MCAssembler &Asm, + const MCValue &Target, + const MCFragment &F, + const MCFixup &Fixup, + bool IsPCRel) const; /// @name Accessors /// @{ Modified: llvm/trunk/lib/MC/ELFObjectWriter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/ELFObjectWriter.cpp?rev=147115&r1=147114&r2=147115&view=diff ============================================================================== --- llvm/trunk/lib/MC/ELFObjectWriter.cpp (original) +++ llvm/trunk/lib/MC/ELFObjectWriter.cpp Wed Dec 21 18:37:50 2011 @@ -25,11 +25,9 @@ #include "llvm/Support/ErrorHandling.h" #include "llvm/Support/ELF.h" #include "llvm/Support/CommandLine.h" -#include "llvm/ADT/Statistic.h" #include "llvm/ADT/StringSwitch.h" #include "../Target/Mips/MCTargetDesc/MipsFixupKinds.h" -#include "../Target/ARM/MCTargetDesc/ARMFixupKinds.h" #include "../Target/PowerPC/MCTargetDesc/PPCFixupKinds.h" #include @@ -1260,9 +1258,8 @@ switch (MOTW->getEMachine()) { case ELF::EM_386: case ELF::EM_X86_64: - return new ELFObjectWriter(MOTW, OS, IsLittleEndian); break; case ELF::EM_ARM: - return new ARMELFObjectWriter(MOTW, OS, IsLittleEndian); break; + return new ELFObjectWriter(MOTW, OS, IsLittleEndian); break; case ELF::EM_MBLAZE: return new MBlazeELFObjectWriter(MOTW, OS, IsLittleEndian); break; case ELF::EM_PPC: @@ -1284,243 +1281,6 @@ } /// START OF SUBCLASSES for ELFObjectWriter -//===- ARMELFObjectWriter -------------------------------------------===// - -ARMELFObjectWriter::ARMELFObjectWriter(MCELFObjectTargetWriter *MOTW, - raw_ostream &_OS, - bool IsLittleEndian) - : ELFObjectWriter(MOTW, _OS, IsLittleEndian) -{} - -ARMELFObjectWriter::~ARMELFObjectWriter() -{} - -// FIXME: get the real EABI Version from the Triple. -unsigned ARMELFObjectWriter::getEFlags() const { - return ELF::EF_ARM_EABIMASK & DefaultEABIVersion; -} - -// In ARM, _MergedGlobals and other most symbols get emitted directly. -// I.e. not as an offset to a section symbol. -// This code is an approximation of what ARM/gcc does. - -STATISTIC(PCRelCount, "Total number of PIC Relocations"); -STATISTIC(NonPCRelCount, "Total number of non-PIC relocations"); - -const MCSymbol *ARMELFObjectWriter::ExplicitRelSym(const MCAssembler &Asm, - const MCValue &Target, - const MCFragment &F, - const MCFixup &Fixup, - bool IsPCRel) const { - const MCSymbol &Symbol = Target.getSymA()->getSymbol(); - bool EmitThisSym = false; - - const MCSectionELF &Section = - static_cast(Symbol.getSection()); - bool InNormalSection = true; - unsigned RelocType = 0; - RelocType = GetRelocTypeInner(Target, Fixup, IsPCRel); - - DEBUG( - const MCSymbolRefExpr::VariantKind Kind = Target.getSymA()->getKind(); - MCSymbolRefExpr::VariantKind Kind2; - Kind2 = Target.getSymB() ? Target.getSymB()->getKind() : - MCSymbolRefExpr::VK_None; - dbgs() << "considering symbol " - << Section.getSectionName() << "/" - << Symbol.getName() << "/" - << " Rel:" << (unsigned)RelocType - << " Kind: " << (int)Kind << "/" << (int)Kind2 - << " Tmp:" - << Symbol.isAbsolute() << "/" << Symbol.isDefined() << "/" - << Symbol.isVariable() << "/" << Symbol.isTemporary() - << " Counts:" << PCRelCount << "/" << NonPCRelCount << "\n"); - - if (IsPCRel) { ++PCRelCount; - switch (RelocType) { - default: - // Most relocation types are emitted as explicit symbols - InNormalSection = - StringSwitch(Section.getSectionName()) - .Case(".data.rel.ro.local", false) - .Case(".data.rel", false) - .Case(".bss", false) - .Default(true); - EmitThisSym = true; - break; - case ELF::R_ARM_ABS32: - // But things get strange with R_ARM_ABS32 - // In this case, most things that go in .rodata show up - // as section relative relocations - InNormalSection = - StringSwitch(Section.getSectionName()) - .Case(".data.rel.ro.local", false) - .Case(".data.rel", false) - .Case(".rodata", false) - .Case(".bss", false) - .Default(true); - EmitThisSym = false; - break; - } - } else { - NonPCRelCount++; - InNormalSection = - StringSwitch(Section.getSectionName()) - .Case(".data.rel.ro.local", false) - .Case(".rodata", false) - .Case(".data.rel", false) - .Case(".bss", false) - .Default(true); - - switch (RelocType) { - default: EmitThisSym = true; break; - case ELF::R_ARM_ABS32: EmitThisSym = false; break; - } - } - - if (EmitThisSym) - return &Symbol; - if (! Symbol.isTemporary() && InNormalSection) { - return &Symbol; - } - return NULL; -} - -// Need to examine the Fixup when determining whether to -// emit the relocation as an explicit symbol or as a section relative -// offset -unsigned ARMELFObjectWriter::GetRelocType(const MCValue &Target, - const MCFixup &Fixup, - bool IsPCRel, - bool IsRelocWithSymbol, - int64_t Addend) const { - return GetRelocTypeInner(Target, Fixup, IsPCRel); -} - -unsigned ARMELFObjectWriter::GetRelocTypeInner(const MCValue &Target, - const MCFixup &Fixup, - bool IsPCRel) const { - MCSymbolRefExpr::VariantKind Modifier = Target.isAbsolute() ? - MCSymbolRefExpr::VK_None : Target.getSymA()->getKind(); - - unsigned Type = 0; - if (IsPCRel) { - switch ((unsigned)Fixup.getKind()) { - default: assert(0 && "Unimplemented"); - case FK_Data_4: - switch (Modifier) { - default: llvm_unreachable("Unsupported Modifier"); - case MCSymbolRefExpr::VK_None: - Type = ELF::R_ARM_REL32; - break; - case MCSymbolRefExpr::VK_ARM_TLSGD: - assert(0 && "unimplemented"); - break; - case MCSymbolRefExpr::VK_ARM_GOTTPOFF: - Type = ELF::R_ARM_TLS_IE32; - break; - } - break; - case ARM::fixup_arm_uncondbranch: - switch (Modifier) { - case MCSymbolRefExpr::VK_ARM_PLT: - Type = ELF::R_ARM_PLT32; - break; - default: - Type = ELF::R_ARM_CALL; - break; - } - break; - case ARM::fixup_arm_condbranch: - Type = ELF::R_ARM_JUMP24; - break; - case ARM::fixup_arm_movt_hi16: - case ARM::fixup_arm_movt_hi16_pcrel: - Type = ELF::R_ARM_MOVT_PREL; - break; - case ARM::fixup_arm_movw_lo16: - case ARM::fixup_arm_movw_lo16_pcrel: - Type = ELF::R_ARM_MOVW_PREL_NC; - break; - case ARM::fixup_t2_movt_hi16: - case ARM::fixup_t2_movt_hi16_pcrel: - Type = ELF::R_ARM_THM_MOVT_PREL; - break; - case ARM::fixup_t2_movw_lo16: - case ARM::fixup_t2_movw_lo16_pcrel: - Type = ELF::R_ARM_THM_MOVW_PREL_NC; - break; - case ARM::fixup_arm_thumb_bl: - case ARM::fixup_arm_thumb_blx: - switch (Modifier) { - case MCSymbolRefExpr::VK_ARM_PLT: - Type = ELF::R_ARM_THM_CALL; - break; - default: - Type = ELF::R_ARM_NONE; - break; - } - break; - } - } else { - switch ((unsigned)Fixup.getKind()) { - default: llvm_unreachable("invalid fixup kind!"); - case FK_Data_4: - switch (Modifier) { - default: llvm_unreachable("Unsupported Modifier"); break; - case MCSymbolRefExpr::VK_ARM_GOT: - Type = ELF::R_ARM_GOT_BREL; - break; - case MCSymbolRefExpr::VK_ARM_TLSGD: - Type = ELF::R_ARM_TLS_GD32; - break; - case MCSymbolRefExpr::VK_ARM_TPOFF: - Type = ELF::R_ARM_TLS_LE32; - break; - case MCSymbolRefExpr::VK_ARM_GOTTPOFF: - Type = ELF::R_ARM_TLS_IE32; - break; - case MCSymbolRefExpr::VK_None: - Type = ELF::R_ARM_ABS32; - break; - case MCSymbolRefExpr::VK_ARM_GOTOFF: - Type = ELF::R_ARM_GOTOFF32; - break; - } - break; - case ARM::fixup_arm_ldst_pcrel_12: - case ARM::fixup_arm_pcrel_10: - case ARM::fixup_arm_adr_pcrel_12: - case ARM::fixup_arm_thumb_bl: - case ARM::fixup_arm_thumb_cb: - case ARM::fixup_arm_thumb_cp: - case ARM::fixup_arm_thumb_br: - assert(0 && "Unimplemented"); - break; - case ARM::fixup_arm_uncondbranch: - Type = ELF::R_ARM_CALL; - break; - case ARM::fixup_arm_condbranch: - Type = ELF::R_ARM_JUMP24; - break; - case ARM::fixup_arm_movt_hi16: - Type = ELF::R_ARM_MOVT_ABS; - break; - case ARM::fixup_arm_movw_lo16: - Type = ELF::R_ARM_MOVW_ABS_NC; - break; - case ARM::fixup_t2_movt_hi16: - Type = ELF::R_ARM_THM_MOVT_ABS; - break; - case ARM::fixup_t2_movw_lo16: - Type = ELF::R_ARM_THM_MOVW_ABS_NC; - break; - } - } - - return Type; -} - //===- PPCELFObjectWriter -------------------------------------------===// PPCELFObjectWriter::PPCELFObjectWriter(MCELFObjectTargetWriter *MOTW, Modified: llvm/trunk/lib/MC/ELFObjectWriter.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/ELFObjectWriter.h?rev=147115&r1=147114&r2=147115&view=diff ============================================================================== --- llvm/trunk/lib/MC/ELFObjectWriter.h (original) +++ llvm/trunk/lib/MC/ELFObjectWriter.h Wed Dec 21 18:37:50 2011 @@ -152,7 +152,7 @@ const MCFragment &F, const MCFixup &Fixup, bool IsPCRel) const { - return NULL; + return TargetObjectWriter->ExplicitRelSym(Asm, Target, F, Fixup, IsPCRel); } bool is64Bit() const { return TargetObjectWriter->is64Bit(); } @@ -243,8 +243,9 @@ virtual void WriteHeader(uint64_t SectionDataSize, unsigned NumberOfSections); - /// Default e_flags = 0 - virtual unsigned getEFlags() const { return 0; } + virtual unsigned getEFlags() const { + return TargetObjectWriter->getEFlags(); + } virtual void WriteSymbolEntry(MCDataFragment *SymtabF, MCDataFragment *ShndxF, @@ -356,35 +357,6 @@ uint64_t &RelocOffset) {} }; - //===- ARMELFObjectWriter -------------------------------------------===// - - class ARMELFObjectWriter : public ELFObjectWriter { - public: - // FIXME: MCAssembler can't yet return the Subtarget, - enum { DefaultEABIVersion = 0x05000000U }; - - ARMELFObjectWriter(MCELFObjectTargetWriter *MOTW, - raw_ostream &_OS, - bool IsLittleEndian); - - virtual ~ARMELFObjectWriter(); - - virtual unsigned getEFlags() const; - protected: - virtual const MCSymbol *ExplicitRelSym(const MCAssembler &Asm, - const MCValue &Target, - const MCFragment &F, - const MCFixup &Fixup, - bool IsPCRel) const; - - virtual unsigned GetRelocType(const MCValue &Target, const MCFixup &Fixup, - bool IsPCRel, bool IsRelocWithSymbol, - int64_t Addend) const; - private: - unsigned GetRelocTypeInner(const MCValue &Target, - const MCFixup &Fixup, bool IsPCRel) const; - }; - //===- PPCELFObjectWriter -------------------------------------------===// class PPCELFObjectWriter : public ELFObjectWriter { Modified: llvm/trunk/lib/MC/MCELFObjectTargetWriter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCELFObjectTargetWriter.cpp?rev=147115&r1=147114&r2=147115&view=diff ============================================================================== --- llvm/trunk/lib/MC/MCELFObjectTargetWriter.cpp (original) +++ llvm/trunk/lib/MC/MCELFObjectTargetWriter.cpp Wed Dec 21 18:37:50 2011 @@ -19,6 +19,20 @@ HasRelocationAddend(HasRelocationAddend_), Is64Bit(Is64Bit_) { } +/// Default e_flags = 0 +unsigned MCELFObjectTargetWriter::getEFlags() const { + return 0; +} + +const MCSymbol *MCELFObjectTargetWriter::ExplicitRelSym(const MCAssembler &Asm, + const MCValue &Target, + const MCFragment &F, + const MCFixup &Fixup, + bool IsPCRel) const { + return NULL; +} + + unsigned MCELFObjectTargetWriter::GetRelocType(const MCValue &Target, const MCFixup &Fixup, bool IsPCRel, Modified: llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp?rev=147115&r1=147114&r2=147115&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp (original) +++ llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp Wed Dec 21 18:37:50 2011 @@ -456,8 +456,7 @@ uint64_t Value) const; MCObjectWriter *createObjectWriter(raw_ostream &OS) const { - return createELFObjectWriter(new ARMELFObjectWriter(OSABI), OS, - /*IsLittleEndian*/ true); + return createARMELFObjectWriter(OS, OSABI); } }; Added: llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMELFObjectWriter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMELFObjectWriter.cpp?rev=147115&view=auto ============================================================================== --- llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMELFObjectWriter.cpp (added) +++ llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMELFObjectWriter.cpp Wed Dec 21 18:37:50 2011 @@ -0,0 +1,286 @@ +//===-- X86ELFObjectWriter.cpp - X86 ELF Writer ---------------------------===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// + +#include "MCTargetDesc/ARMFixupKinds.h" +#include "MCTargetDesc/ARMMCTargetDesc.h" +#include "llvm/Support/Debug.h" +#include "llvm/Support/ErrorHandling.h" +#include "llvm/ADT/Statistic.h" +#include "llvm/ADT/StringSwitch.h" +#include "llvm/MC/MCELFObjectWriter.h" +#include "llvm/MC/MCExpr.h" +#include "llvm/MC/MCSectionELF.h" +#include "llvm/MC/MCValue.h" + +using namespace llvm; + +namespace { + class ARMELFObjectWriter : public MCELFObjectTargetWriter { + enum { DefaultEABIVersion = 0x05000000U }; + + const MCSymbol *ExplicitRelSym(const MCAssembler &Asm, + const MCValue &Target, + const MCFragment &F, + const MCFixup &Fixup, + bool IsPCRel) const; + unsigned GetRelocTypeInner(const MCValue &Target, + const MCFixup &Fixup, + bool IsPCRel) const; + + + public: + ARMELFObjectWriter(uint8_t OSABI); + + virtual ~ARMELFObjectWriter(); + protected: + virtual unsigned GetRelocType(const MCValue &Target, const MCFixup &Fixup, + bool IsPCRel, bool IsRelocWithSymbol, + int64_t Addend) const; + virtual unsigned getEFlags() const; + }; +} + +ARMELFObjectWriter::ARMELFObjectWriter(uint8_t OSABI) + : MCELFObjectTargetWriter(/*Is64Bit*/ false, OSABI, + ELF::EM_ARM, + /*HasRelocationAddend*/ false) {} + +ARMELFObjectWriter::~ARMELFObjectWriter() {} + +// FIXME: get the real EABI Version from the Triple. +unsigned ARMELFObjectWriter::getEFlags() const { + return ELF::EF_ARM_EABIMASK & DefaultEABIVersion; +} + +// In ARM, _MergedGlobals and other most symbols get emitted directly. +// I.e. not as an offset to a section symbol. +// This code is an approximation of what ARM/gcc does. + +STATISTIC(PCRelCount, "Total number of PIC Relocations"); +STATISTIC(NonPCRelCount, "Total number of non-PIC relocations"); + +const MCSymbol *ARMELFObjectWriter::ExplicitRelSym(const MCAssembler &Asm, + const MCValue &Target, + const MCFragment &F, + const MCFixup &Fixup, + bool IsPCRel) const { + const MCSymbol &Symbol = Target.getSymA()->getSymbol(); + bool EmitThisSym = false; + + const MCSectionELF &Section = + static_cast(Symbol.getSection()); + bool InNormalSection = true; + unsigned RelocType = 0; + RelocType = GetRelocTypeInner(Target, Fixup, IsPCRel); + + DEBUG( + const MCSymbolRefExpr::VariantKind Kind = Target.getSymA()->getKind(); + MCSymbolRefExpr::VariantKind Kind2; + Kind2 = Target.getSymB() ? Target.getSymB()->getKind() : + MCSymbolRefExpr::VK_None; + dbgs() << "considering symbol " + << Section.getSectionName() << "/" + << Symbol.getName() << "/" + << " Rel:" << (unsigned)RelocType + << " Kind: " << (int)Kind << "/" << (int)Kind2 + << " Tmp:" + << Symbol.isAbsolute() << "/" << Symbol.isDefined() << "/" + << Symbol.isVariable() << "/" << Symbol.isTemporary() + << " Counts:" << PCRelCount << "/" << NonPCRelCount << "\n"); + + if (IsPCRel) { ++PCRelCount; + switch (RelocType) { + default: + // Most relocation types are emitted as explicit symbols + InNormalSection = + StringSwitch(Section.getSectionName()) + .Case(".data.rel.ro.local", false) + .Case(".data.rel", false) + .Case(".bss", false) + .Default(true); + EmitThisSym = true; + break; + case ELF::R_ARM_ABS32: + // But things get strange with R_ARM_ABS32 + // In this case, most things that go in .rodata show up + // as section relative relocations + InNormalSection = + StringSwitch(Section.getSectionName()) + .Case(".data.rel.ro.local", false) + .Case(".data.rel", false) + .Case(".rodata", false) + .Case(".bss", false) + .Default(true); + EmitThisSym = false; + break; + } + } else { + NonPCRelCount++; + InNormalSection = + StringSwitch(Section.getSectionName()) + .Case(".data.rel.ro.local", false) + .Case(".rodata", false) + .Case(".data.rel", false) + .Case(".bss", false) + .Default(true); + + switch (RelocType) { + default: EmitThisSym = true; break; + case ELF::R_ARM_ABS32: EmitThisSym = false; break; + } + } + + if (EmitThisSym) + return &Symbol; + if (! Symbol.isTemporary() && InNormalSection) { + return &Symbol; + } + return NULL; +} + +// Need to examine the Fixup when determining whether to +// emit the relocation as an explicit symbol or as a section relative +// offset +unsigned ARMELFObjectWriter::GetRelocType(const MCValue &Target, + const MCFixup &Fixup, + bool IsPCRel, + bool IsRelocWithSymbol, + int64_t Addend) const { + return GetRelocTypeInner(Target, Fixup, IsPCRel); +} + +unsigned ARMELFObjectWriter::GetRelocTypeInner(const MCValue &Target, + const MCFixup &Fixup, + bool IsPCRel) const { + MCSymbolRefExpr::VariantKind Modifier = Target.isAbsolute() ? + MCSymbolRefExpr::VK_None : Target.getSymA()->getKind(); + + unsigned Type = 0; + if (IsPCRel) { + switch ((unsigned)Fixup.getKind()) { + default: assert(0 && "Unimplemented"); + case FK_Data_4: + switch (Modifier) { + default: llvm_unreachable("Unsupported Modifier"); + case MCSymbolRefExpr::VK_None: + Type = ELF::R_ARM_REL32; + break; + case MCSymbolRefExpr::VK_ARM_TLSGD: + assert(0 && "unimplemented"); + break; + case MCSymbolRefExpr::VK_ARM_GOTTPOFF: + Type = ELF::R_ARM_TLS_IE32; + break; + } + break; + case ARM::fixup_arm_uncondbranch: + switch (Modifier) { + case MCSymbolRefExpr::VK_ARM_PLT: + Type = ELF::R_ARM_PLT32; + break; + default: + Type = ELF::R_ARM_CALL; + break; + } + break; + case ARM::fixup_arm_condbranch: + Type = ELF::R_ARM_JUMP24; + break; + case ARM::fixup_arm_movt_hi16: + case ARM::fixup_arm_movt_hi16_pcrel: + Type = ELF::R_ARM_MOVT_PREL; + break; + case ARM::fixup_arm_movw_lo16: + case ARM::fixup_arm_movw_lo16_pcrel: + Type = ELF::R_ARM_MOVW_PREL_NC; + break; + case ARM::fixup_t2_movt_hi16: + case ARM::fixup_t2_movt_hi16_pcrel: + Type = ELF::R_ARM_THM_MOVT_PREL; + break; + case ARM::fixup_t2_movw_lo16: + case ARM::fixup_t2_movw_lo16_pcrel: + Type = ELF::R_ARM_THM_MOVW_PREL_NC; + break; + case ARM::fixup_arm_thumb_bl: + case ARM::fixup_arm_thumb_blx: + switch (Modifier) { + case MCSymbolRefExpr::VK_ARM_PLT: + Type = ELF::R_ARM_THM_CALL; + break; + default: + Type = ELF::R_ARM_NONE; + break; + } + break; + } + } else { + switch ((unsigned)Fixup.getKind()) { + default: llvm_unreachable("invalid fixup kind!"); + case FK_Data_4: + switch (Modifier) { + default: llvm_unreachable("Unsupported Modifier"); break; + case MCSymbolRefExpr::VK_ARM_GOT: + Type = ELF::R_ARM_GOT_BREL; + break; + case MCSymbolRefExpr::VK_ARM_TLSGD: + Type = ELF::R_ARM_TLS_GD32; + break; + case MCSymbolRefExpr::VK_ARM_TPOFF: + Type = ELF::R_ARM_TLS_LE32; + break; + case MCSymbolRefExpr::VK_ARM_GOTTPOFF: + Type = ELF::R_ARM_TLS_IE32; + break; + case MCSymbolRefExpr::VK_None: + Type = ELF::R_ARM_ABS32; + break; + case MCSymbolRefExpr::VK_ARM_GOTOFF: + Type = ELF::R_ARM_GOTOFF32; + break; + } + break; + case ARM::fixup_arm_ldst_pcrel_12: + case ARM::fixup_arm_pcrel_10: + case ARM::fixup_arm_adr_pcrel_12: + case ARM::fixup_arm_thumb_bl: + case ARM::fixup_arm_thumb_cb: + case ARM::fixup_arm_thumb_cp: + case ARM::fixup_arm_thumb_br: + assert(0 && "Unimplemented"); + break; + case ARM::fixup_arm_uncondbranch: + Type = ELF::R_ARM_CALL; + break; + case ARM::fixup_arm_condbranch: + Type = ELF::R_ARM_JUMP24; + break; + case ARM::fixup_arm_movt_hi16: + Type = ELF::R_ARM_MOVT_ABS; + break; + case ARM::fixup_arm_movw_lo16: + Type = ELF::R_ARM_MOVW_ABS_NC; + break; + case ARM::fixup_t2_movt_hi16: + Type = ELF::R_ARM_THM_MOVT_ABS; + break; + case ARM::fixup_t2_movw_lo16: + Type = ELF::R_ARM_THM_MOVW_ABS_NC; + break; + } + } + + return Type; +} + +MCObjectWriter *llvm::createARMELFObjectWriter(raw_ostream &OS, + uint8_t OSABI) { + MCELFObjectTargetWriter *MOTW = new ARMELFObjectWriter(OSABI); + return createELFObjectWriter(MOTW, OS, /*IsLittleEndian=*/true); +} Modified: llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.h?rev=147115&r1=147114&r2=147115&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.h (original) +++ llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.h Wed Dec 21 18:37:50 2011 @@ -46,6 +46,10 @@ MCAsmBackend *createARMAsmBackend(const Target &T, StringRef TT); +/// createARMELFObjectWriter - Construct an ELF Mach-O object writer. +MCObjectWriter *createARMELFObjectWriter(raw_ostream &OS, + uint8_t OSABI); + /// createARMMachObjectWriter - Construct an ARM Mach-O object writer. MCObjectWriter *createARMMachObjectWriter(raw_ostream &OS, bool Is64Bit, From richard-llvm at metafoo.co.uk Wed Dec 21 19:03:36 2011 From: richard-llvm at metafoo.co.uk (Richard Smith) Date: Thu, 22 Dec 2011 01:03:36 -0000 Subject: [llvm-commits] [llvm] r147117 - /llvm/trunk/lib/Target/ARM/MCTargetDesc/CMakeLists.txt Message-ID: <20111222010336.2E3AA2A6C12C@llvm.org> Author: rsmith Date: Wed Dec 21 19:03:35 2011 New Revision: 147117 URL: http://llvm.org/viewvc/llvm-project?rev=147117&view=rev Log: Unbreak cmake build after r147115. Modified: llvm/trunk/lib/Target/ARM/MCTargetDesc/CMakeLists.txt Modified: llvm/trunk/lib/Target/ARM/MCTargetDesc/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/MCTargetDesc/CMakeLists.txt?rev=147117&r1=147116&r2=147117&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/MCTargetDesc/CMakeLists.txt (original) +++ llvm/trunk/lib/Target/ARM/MCTargetDesc/CMakeLists.txt Wed Dec 21 19:03:35 2011 @@ -1,5 +1,6 @@ add_llvm_library(LLVMARMDesc ARMAsmBackend.cpp + ARMELFObjectWriter.cpp ARMMCAsmInfo.cpp ARMMCCodeEmitter.cpp ARMMCExpr.cpp From ahatanaka at mips.com Wed Dec 21 19:05:17 2011 From: ahatanaka at mips.com (Akira Hatanaka) Date: Thu, 22 Dec 2011 01:05:17 -0000 Subject: [llvm-commits] [llvm] r147118 - in /llvm/trunk: include/llvm/MC/MCExpr.h lib/MC/ELFObjectWriter.cpp lib/MC/MCExpr.cpp lib/Target/Mips/MCTargetDesc/MipsAsmBackend.cpp lib/Target/Mips/MCTargetDesc/MipsFixupKinds.h lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp test/MC/Mips/elf-tls.ll Message-ID: <20111222010517.592D32A6C12C@llvm.org> Author: ahatanak Date: Wed Dec 21 19:05:17 2011 New Revision: 147118 URL: http://llvm.org/viewvc/llvm-project?rev=147118&view=rev Log: Local dynamic TLS model for direct object output. Create the correct TLS MIPS ELF relocations. Patch by Jack Carter. Added: llvm/trunk/test/MC/Mips/elf-tls.ll Modified: llvm/trunk/include/llvm/MC/MCExpr.h llvm/trunk/lib/MC/ELFObjectWriter.cpp llvm/trunk/lib/MC/MCExpr.cpp llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsAsmBackend.cpp llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsFixupKinds.h llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp Modified: llvm/trunk/include/llvm/MC/MCExpr.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/MC/MCExpr.h?rev=147118&r1=147117&r2=147118&view=diff ============================================================================== --- llvm/trunk/include/llvm/MC/MCExpr.h (original) +++ llvm/trunk/include/llvm/MC/MCExpr.h Wed Dec 21 19:05:17 2011 @@ -176,7 +176,6 @@ VK_PPC_GAS_HA16, // symbol at ha VK_PPC_GAS_LO16, // symbol at l - VK_Mips_None, VK_Mips_GPREL, VK_Mips_GOT_CALL, VK_Mips_GOT16, Modified: llvm/trunk/lib/MC/ELFObjectWriter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/ELFObjectWriter.cpp?rev=147118&r1=147117&r2=147118&view=diff ============================================================================== --- llvm/trunk/lib/MC/ELFObjectWriter.cpp (original) +++ llvm/trunk/lib/MC/ELFObjectWriter.cpp Wed Dec 21 19:05:17 2011 @@ -1474,6 +1474,15 @@ case Mips::fixup_Mips_TPREL_LO: Type = ELF::R_MIPS_TLS_TPREL_LO16; break; + case Mips::fixup_Mips_TLSLDM: + Type = ELF::R_MIPS_TLS_LDM; + break; + case Mips::fixup_Mips_DTPREL_HI: + Type = ELF::R_MIPS_TLS_DTPREL_HI16; + break; + case Mips::fixup_Mips_DTPREL_LO: + Type = ELF::R_MIPS_TLS_DTPREL_LO16; + break; case Mips::fixup_Mips_Branch_PCRel: case Mips::fixup_Mips_PC16: Type = ELF::R_MIPS_PC16; Modified: llvm/trunk/lib/MC/MCExpr.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCExpr.cpp?rev=147118&r1=147117&r2=147118&view=diff ============================================================================== --- llvm/trunk/lib/MC/MCExpr.cpp (original) +++ llvm/trunk/lib/MC/MCExpr.cpp Wed Dec 21 19:05:17 2011 @@ -200,6 +200,24 @@ case VK_PPC_DARWIN_LO16: return "lo16"; case VK_PPC_GAS_HA16: return "ha"; case VK_PPC_GAS_LO16: return "l"; + case VK_Mips_GPREL: return "GPREL"; + case VK_Mips_GOT_CALL: return "GOT_CALL"; + case VK_Mips_GOT16: return "GOT16"; + case VK_Mips_GOT: return "GOT"; + case VK_Mips_ABS_HI: return "ABS_HI"; + case VK_Mips_ABS_LO: return "ABS_LO"; + case VK_Mips_TLSGD: return "TLSGD"; + case VK_Mips_TLSLDM: return "TLSLDM"; + case VK_Mips_DTPREL_HI: return "DTPREL_HI"; + case VK_Mips_DTPREL_LO: return "DTPREL_LO"; + case VK_Mips_GOTTPREL: return "GOTTPREL"; + case VK_Mips_TPREL_HI: return "TPREL_HI"; + case VK_Mips_TPREL_LO: return "TPREL_LO"; + case VK_Mips_GPOFF_HI: return "GPOFF_HI"; + case VK_Mips_GPOFF_LO: return "GPOFF_LO"; + case VK_Mips_GOT_DISP: return "GOT_DISP"; + case VK_Mips_GOT_PAGE: return "GOT_PAGE"; + case VK_Mips_GOT_OFST: return "GOT_OFST"; } } Modified: llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsAsmBackend.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsAsmBackend.cpp?rev=147118&r1=147117&r2=147118&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsAsmBackend.cpp (original) +++ llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsAsmBackend.cpp Wed Dec 21 19:05:17 2011 @@ -141,6 +141,9 @@ { "fixup_Mips_GOTTPREL", 0, 16, 0 }, { "fixup_Mips_TPREL_HI", 0, 16, 0 }, { "fixup_Mips_TPREL_LO", 0, 16, 0 }, + { "fixup_Mips_TLSLDM", 0, 16, 0 }, + { "fixup_Mips_DTPREL_HI", 0, 16, 0 }, + { "fixup_Mips_DTPREL_LO", 0, 16, 0 }, { "fixup_Mips_Branch_PCRel", 0, 16, MCFixupKindInfo::FKF_IsPCRel } }; Modified: llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsFixupKinds.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsFixupKinds.h?rev=147118&r1=147117&r2=147118&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsFixupKinds.h (original) +++ llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsFixupKinds.h Wed Dec 21 19:05:17 2011 @@ -83,6 +83,15 @@ // resulting in - R_MIPS_TLS_TPREL_LO16. fixup_Mips_TPREL_LO, + // resulting in - R_MIPS_TLS_LDM. + fixup_Mips_TLSLDM, + + // resulting in - R_MIPS_TLS_DTPREL_HI16. + fixup_Mips_DTPREL_HI, + + // resulting in - R_MIPS_TLS_DTPREL_LO16. + fixup_Mips_DTPREL_LO, + // PC relative branch fixup resulting in - R_MIPS_PC16 fixup_Mips_Branch_PCRel, Modified: llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp?rev=147118&r1=147117&r2=147118&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp (original) +++ llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp Wed Dec 21 19:05:17 2011 @@ -187,6 +187,7 @@ if (Kind == MCExpr::SymbolRef) { Mips::Fixups FixupKind; + switch(cast(Expr)->getKind()) { case MCSymbolRefExpr::VK_Mips_GPREL: FixupKind = Mips::fixup_Mips_GPREL16; @@ -209,6 +210,15 @@ case MCSymbolRefExpr::VK_Mips_TLSGD: FixupKind = Mips::fixup_Mips_TLSGD; break; + case MCSymbolRefExpr::VK_Mips_TLSLDM: + FixupKind = Mips::fixup_Mips_TLSLDM; + break; + case MCSymbolRefExpr::VK_Mips_DTPREL_HI: + FixupKind = Mips::fixup_Mips_DTPREL_HI; + break; + case MCSymbolRefExpr::VK_Mips_DTPREL_LO: + FixupKind = Mips::fixup_Mips_DTPREL_LO; + break; case MCSymbolRefExpr::VK_Mips_GOTTPREL: FixupKind = Mips::fixup_Mips_GOTTPREL; break; Added: llvm/trunk/test/MC/Mips/elf-tls.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/elf-tls.ll?rev=147118&view=auto ============================================================================== --- llvm/trunk/test/MC/Mips/elf-tls.ll (added) +++ llvm/trunk/test/MC/Mips/elf-tls.ll Wed Dec 21 19:05:17 2011 @@ -0,0 +1,36 @@ +; RUN: llc -filetype=obj -mtriple mipsel-unknown-linux %s -o - | elf-dump --dump-section-data | FileCheck %s + +; Check that the appropriate relocations were created. + +; CHECK: ('r_type', 0x2b) +; CHECK: ('r_type', 0x2c) +; CHECK: ('r_type', 0x2d) + + at t1 = thread_local global i32 0, align 4 + +define i32 @f1() nounwind { +entry: + %tmp = load i32* @t1, align 4 + ret i32 %tmp + +} + + + at t2 = external thread_local global i32 + +define i32 @f2() nounwind { +entry: + %tmp = load i32* @t2, align 4 + ret i32 %tmp + +} + + at f3.i = internal thread_local unnamed_addr global i32 1, align 4 + +define i32 @f3() nounwind { +entry: + %0 = load i32* @f3.i, align 4 + %inc = add nsw i32 %0, 1 + store i32 %inc, i32* @f3.i, align 4 + ret i32 %inc +} From rafael.espindola at gmail.com Wed Dec 21 19:06:53 2011 From: rafael.espindola at gmail.com (Rafael Espindola) Date: Thu, 22 Dec 2011 01:06:53 -0000 Subject: [llvm-commits] [llvm] r147119 - /llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMELFObjectWriter.cpp Message-ID: <20111222010653.678DD2A6C12C@llvm.org> Author: rafael Date: Wed Dec 21 19:06:53 2011 New Revision: 147119 URL: http://llvm.org/viewvc/llvm-project?rev=147119&view=rev Log: Fix name in comments. Modified: llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMELFObjectWriter.cpp Modified: llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMELFObjectWriter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMELFObjectWriter.cpp?rev=147119&r1=147118&r2=147119&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMELFObjectWriter.cpp (original) +++ llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMELFObjectWriter.cpp Wed Dec 21 19:06:53 2011 @@ -1,4 +1,4 @@ -//===-- X86ELFObjectWriter.cpp - X86 ELF Writer ---------------------------===// +//===-- ARMELFObjectWriter.cpp - ARM ELF Writer ---------------------------===// // // The LLVM Compiler Infrastructure // From rafael.espindola at gmail.com Wed Dec 21 19:11:02 2011 From: rafael.espindola at gmail.com (Rafael Espindola) Date: Thu, 22 Dec 2011 01:11:02 -0000 Subject: [llvm-commits] [llvm] r147121 - /llvm/trunk/lib/Target/ARM/MCTargetDesc/CMakeLists.txt Message-ID: <20111222011102.3792A2A6C12C@llvm.org> Author: rafael Date: Wed Dec 21 19:11:01 2011 New Revision: 147121 URL: http://llvm.org/viewvc/llvm-project?rev=147121&view=rev Log: Hopefully fix the cmake build. Modified: llvm/trunk/lib/Target/ARM/MCTargetDesc/CMakeLists.txt Modified: llvm/trunk/lib/Target/ARM/MCTargetDesc/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/MCTargetDesc/CMakeLists.txt?rev=147121&r1=147120&r2=147121&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/MCTargetDesc/CMakeLists.txt (original) +++ llvm/trunk/lib/Target/ARM/MCTargetDesc/CMakeLists.txt Wed Dec 21 19:11:01 2011 @@ -6,6 +6,7 @@ ARMMCExpr.cpp ARMMCTargetDesc.cpp ARMMachObjectWriter.cpp + ARMELFObjectWriter.cpp ) add_dependencies(LLVMARMDesc ARMCommonTableGen) From rafael.espindola at gmail.com Wed Dec 21 19:49:12 2011 From: rafael.espindola at gmail.com (=?ISO-8859-1?Q?Rafael_=C1vila_de_Esp=EDndola?=) Date: Wed, 21 Dec 2011 20:49:12 -0500 Subject: [llvm-commits] Anyone using the PPC ELF object writer? Message-ID: <4EF28C98.1080705@gmail.com> I am refactoring the object writers and noticed that no test depends on adjustFixupOffset. Is it dead code and should be removed or are we missing tests? Cheers, Rafael From rafael.espindola at gmail.com Wed Dec 21 19:57:09 2011 From: rafael.espindola at gmail.com (Rafael Espindola) Date: Thu, 22 Dec 2011 01:57:09 -0000 Subject: [llvm-commits] [llvm] r147124 - in /llvm/trunk: include/llvm/MC/MCELFObjectWriter.h lib/MC/ELFObjectWriter.cpp lib/MC/ELFObjectWriter.h lib/MC/MCELFObjectTargetWriter.cpp lib/Target/PowerPC/MCTargetDesc/PPCELFObjectWriter.cpp lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.h Message-ID: <20111222015709.DA0782A6C12C@llvm.org> Author: rafael Date: Wed Dec 21 19:57:09 2011 New Revision: 147124 URL: http://llvm.org/viewvc/llvm-project?rev=147124&view=rev Log: Move PPC bits to lib/Target/PowerPC. Added: llvm/trunk/lib/Target/PowerPC/MCTargetDesc/PPCELFObjectWriter.cpp Modified: llvm/trunk/include/llvm/MC/MCELFObjectWriter.h llvm/trunk/lib/MC/ELFObjectWriter.cpp llvm/trunk/lib/MC/ELFObjectWriter.h llvm/trunk/lib/MC/MCELFObjectTargetWriter.cpp llvm/trunk/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.h Modified: llvm/trunk/include/llvm/MC/MCELFObjectWriter.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/MC/MCELFObjectWriter.h?rev=147124&r1=147123&r2=147124&view=diff ============================================================================== --- llvm/trunk/include/llvm/MC/MCELFObjectWriter.h (original) +++ llvm/trunk/include/llvm/MC/MCELFObjectWriter.h Wed Dec 21 19:57:09 2011 @@ -49,6 +49,9 @@ const MCFragment &F, const MCFixup &Fixup, bool IsPCRel) const; + virtual void adjustFixupOffset(const MCFixup &Fixup, + uint64_t &RelocOffset); + /// @name Accessors /// @{ Modified: llvm/trunk/lib/MC/ELFObjectWriter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/ELFObjectWriter.cpp?rev=147124&r1=147123&r2=147124&view=diff ============================================================================== --- llvm/trunk/lib/MC/ELFObjectWriter.cpp (original) +++ llvm/trunk/lib/MC/ELFObjectWriter.cpp Wed Dec 21 19:57:09 2011 @@ -28,7 +28,6 @@ #include "llvm/ADT/StringSwitch.h" #include "../Target/Mips/MCTargetDesc/MipsFixupKinds.h" -#include "../Target/PowerPC/MCTargetDesc/PPCFixupKinds.h" #include using namespace llvm; @@ -448,7 +447,8 @@ uint64_t RelocOffset = Layout.getFragmentOffset(Fragment) + Fixup.getOffset(); - adjustFixupOffset(Fixup, RelocOffset); + // FIXME: no tests cover this. Is adjustFixupOffset dead code? + TargetObjectWriter->adjustFixupOffset(Fixup, RelocOffset); if (!hasRelocationAddend()) Addend = 0; @@ -1259,12 +1259,11 @@ case ELF::EM_386: case ELF::EM_X86_64: case ELF::EM_ARM: + case ELF::EM_PPC: + case ELF::EM_PPC64: return new ELFObjectWriter(MOTW, OS, IsLittleEndian); break; case ELF::EM_MBLAZE: return new MBlazeELFObjectWriter(MOTW, OS, IsLittleEndian); break; - case ELF::EM_PPC: - case ELF::EM_PPC64: - return new PPCELFObjectWriter(MOTW, OS, IsLittleEndian); break; case ELF::EM_MIPS: return new MipsELFObjectWriter(MOTW, OS, IsLittleEndian); break; default: llvm_unreachable("Unsupported architecture"); break; @@ -1281,76 +1280,6 @@ } /// START OF SUBCLASSES for ELFObjectWriter -//===- PPCELFObjectWriter -------------------------------------------===// - -PPCELFObjectWriter::PPCELFObjectWriter(MCELFObjectTargetWriter *MOTW, - raw_ostream &_OS, - bool IsLittleEndian) - : ELFObjectWriter(MOTW, _OS, IsLittleEndian) { -} - -PPCELFObjectWriter::~PPCELFObjectWriter() { -} - -unsigned PPCELFObjectWriter::GetRelocType(const MCValue &Target, - const MCFixup &Fixup, - bool IsPCRel, - bool IsRelocWithSymbol, - int64_t Addend) const { - // determine the type of the relocation - unsigned Type; - if (IsPCRel) { - switch ((unsigned)Fixup.getKind()) { - default: - llvm_unreachable("Unimplemented"); - case PPC::fixup_ppc_br24: - Type = ELF::R_PPC_REL24; - break; - case FK_PCRel_4: - Type = ELF::R_PPC_REL32; - break; - } - } else { - switch ((unsigned)Fixup.getKind()) { - default: llvm_unreachable("invalid fixup kind!"); - case PPC::fixup_ppc_br24: - Type = ELF::R_PPC_ADDR24; - break; - case PPC::fixup_ppc_brcond14: - Type = ELF::R_PPC_ADDR14_BRTAKEN; // XXX: or BRNTAKEN?_ - break; - case PPC::fixup_ppc_ha16: - Type = ELF::R_PPC_ADDR16_HA; - break; - case PPC::fixup_ppc_lo16: - Type = ELF::R_PPC_ADDR16_LO; - break; - case PPC::fixup_ppc_lo14: - Type = ELF::R_PPC_ADDR14; - break; - case FK_Data_4: - Type = ELF::R_PPC_ADDR32; - break; - case FK_Data_2: - Type = ELF::R_PPC_ADDR16; - break; - } - } - return Type; -} - -void PPCELFObjectWriter:: -adjustFixupOffset(const MCFixup &Fixup, uint64_t &RelocOffset) { - switch ((unsigned)Fixup.getKind()) { - case PPC::fixup_ppc_ha16: - case PPC::fixup_ppc_lo16: - RelocOffset += 2; - break; - default: - break; - } -} - //===- MBlazeELFObjectWriter -------------------------------------------===// MBlazeELFObjectWriter::MBlazeELFObjectWriter(MCELFObjectTargetWriter *MOTW, Modified: llvm/trunk/lib/MC/ELFObjectWriter.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/ELFObjectWriter.h?rev=147124&r1=147123&r2=147124&view=diff ============================================================================== --- llvm/trunk/lib/MC/ELFObjectWriter.h (original) +++ llvm/trunk/lib/MC/ELFObjectWriter.h Wed Dec 21 19:57:09 2011 @@ -353,24 +353,6 @@ virtual unsigned GetRelocType(const MCValue &Target, const MCFixup &Fixup, bool IsPCRel, bool IsRelocWithSymbol, int64_t Addend) const; - virtual void adjustFixupOffset(const MCFixup &Fixup, - uint64_t &RelocOffset) {} - }; - - //===- PPCELFObjectWriter -------------------------------------------===// - - class PPCELFObjectWriter : public ELFObjectWriter { - public: - PPCELFObjectWriter(MCELFObjectTargetWriter *MOTW, - raw_ostream &_OS, - bool IsLittleEndian); - - virtual ~PPCELFObjectWriter(); - protected: - virtual unsigned GetRelocType(const MCValue &Target, const MCFixup &Fixup, - bool IsPCRel, bool IsRelocWithSymbol, - int64_t Addend) const; - virtual void adjustFixupOffset(const MCFixup &Fixup, uint64_t &RelocOffset); }; //===- MBlazeELFObjectWriter -------------------------------------------===// Modified: llvm/trunk/lib/MC/MCELFObjectTargetWriter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCELFObjectTargetWriter.cpp?rev=147124&r1=147123&r2=147124&view=diff ============================================================================== --- llvm/trunk/lib/MC/MCELFObjectTargetWriter.cpp (original) +++ llvm/trunk/lib/MC/MCELFObjectTargetWriter.cpp Wed Dec 21 19:57:09 2011 @@ -33,6 +33,10 @@ } +void MCELFObjectTargetWriter::adjustFixupOffset(const MCFixup &Fixup, + uint64_t &RelocOffset) { +} + unsigned MCELFObjectTargetWriter::GetRelocType(const MCValue &Target, const MCFixup &Fixup, bool IsPCRel, Added: llvm/trunk/lib/Target/PowerPC/MCTargetDesc/PPCELFObjectWriter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/MCTargetDesc/PPCELFObjectWriter.cpp?rev=147124&view=auto ============================================================================== --- llvm/trunk/lib/Target/PowerPC/MCTargetDesc/PPCELFObjectWriter.cpp (added) +++ llvm/trunk/lib/Target/PowerPC/MCTargetDesc/PPCELFObjectWriter.cpp Wed Dec 21 19:57:09 2011 @@ -0,0 +1,103 @@ +//===-- PPCELFObjectWriter.cpp - PPC ELF Writer ---------------------------===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// + +#include "MCTargetDesc/PPCFixupKinds.h" +#include "MCTargetDesc/PPCMCTargetDesc.h" +#include "llvm/MC/MCELFObjectWriter.h" +#include "llvm/Support/ErrorHandling.h" + +using namespace llvm; + +namespace { + class PPCELFObjectWriter : public MCELFObjectTargetWriter { + public: + PPCELFObjectWriter(bool Is64Bit, uint8_t OSABI); + + virtual ~PPCELFObjectWriter(); + protected: + virtual unsigned GetRelocType(const MCValue &Target, const MCFixup &Fixup, + bool IsPCRel, bool IsRelocWithSymbol, + int64_t Addend) const; + virtual void adjustFixupOffset(const MCFixup &Fixup, uint64_t &RelocOffset); + }; +} + +PPCELFObjectWriter::PPCELFObjectWriter(bool Is64Bit, uint8_t OSABI) + : MCELFObjectTargetWriter(Is64Bit, OSABI, + Is64Bit ? ELF::EM_PPC64 : ELF::EM_PPC, + /*HasRelocationAddend*/ false) {} + +PPCELFObjectWriter::~PPCELFObjectWriter() { +} + +unsigned PPCELFObjectWriter::GetRelocType(const MCValue &Target, + const MCFixup &Fixup, + bool IsPCRel, + bool IsRelocWithSymbol, + int64_t Addend) const { + // determine the type of the relocation + unsigned Type; + if (IsPCRel) { + switch ((unsigned)Fixup.getKind()) { + default: + llvm_unreachable("Unimplemented"); + case PPC::fixup_ppc_br24: + Type = ELF::R_PPC_REL24; + break; + case FK_PCRel_4: + Type = ELF::R_PPC_REL32; + break; + } + } else { + switch ((unsigned)Fixup.getKind()) { + default: llvm_unreachable("invalid fixup kind!"); + case PPC::fixup_ppc_br24: + Type = ELF::R_PPC_ADDR24; + break; + case PPC::fixup_ppc_brcond14: + Type = ELF::R_PPC_ADDR14_BRTAKEN; // XXX: or BRNTAKEN?_ + break; + case PPC::fixup_ppc_ha16: + Type = ELF::R_PPC_ADDR16_HA; + break; + case PPC::fixup_ppc_lo16: + Type = ELF::R_PPC_ADDR16_LO; + break; + case PPC::fixup_ppc_lo14: + Type = ELF::R_PPC_ADDR14; + break; + case FK_Data_4: + Type = ELF::R_PPC_ADDR32; + break; + case FK_Data_2: + Type = ELF::R_PPC_ADDR16; + break; + } + } + return Type; +} + +void PPCELFObjectWriter:: +adjustFixupOffset(const MCFixup &Fixup, uint64_t &RelocOffset) { + switch ((unsigned)Fixup.getKind()) { + case PPC::fixup_ppc_ha16: + case PPC::fixup_ppc_lo16: + RelocOffset += 2; + break; + default: + break; + } +} + +MCObjectWriter *llvm::createPPCELFObjectWriter(raw_ostream &OS, + bool Is64Bit, + uint8_t OSABI) { + MCELFObjectTargetWriter *MOTW = new PPCELFObjectWriter(Is64Bit, OSABI); + return createELFObjectWriter(MOTW, OS, /*IsLittleEndian=*/true); +} Modified: llvm/trunk/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.h?rev=147124&r1=147123&r2=147124&view=diff ============================================================================== --- llvm/trunk/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.h (original) +++ llvm/trunk/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.h Wed Dec 21 19:57:09 2011 @@ -14,14 +14,18 @@ #ifndef PPCMCTARGETDESC_H #define PPCMCTARGETDESC_H +#include "llvm/Support/DataTypes.h" + namespace llvm { class MCAsmBackend; class MCCodeEmitter; class MCContext; class MCInstrInfo; +class MCObjectWriter; class MCSubtargetInfo; class Target; class StringRef; +class raw_ostream; extern Target ThePPC32Target; extern Target ThePPC64Target; @@ -31,7 +35,11 @@ MCContext &Ctx); MCAsmBackend *createPPCAsmBackend(const Target &T, StringRef TT); - + +/// createPPCELFObjectWriter - Construct an PPC ELF object writer. +MCObjectWriter *createPPCELFObjectWriter(raw_ostream &OS, + bool Is64Bit, + uint8_t OSABI); } // End llvm namespace // Defines symbolic names for PowerPC registers. This defines a mapping from From peter_cooper at apple.com Wed Dec 21 20:05:40 2011 From: peter_cooper at apple.com (Pete Cooper) Date: Thu, 22 Dec 2011 02:05:40 -0000 Subject: [llvm-commits] [llvm] r147125 - /llvm/trunk/lib/CodeGen/MachineLICM.cpp Message-ID: <20111222020540.E4E8F2A6C12C@llvm.org> Author: pete Date: Wed Dec 21 20:05:40 2011 New Revision: 147125 URL: http://llvm.org/viewvc/llvm-project?rev=147125&view=rev Log: Changed MachineLICM to use a worklist list MachineCSE instead of recursion. Fixes Modified: llvm/trunk/lib/CodeGen/MachineLICM.cpp Modified: llvm/trunk/lib/CodeGen/MachineLICM.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineLICM.cpp?rev=147125&r1=147124&r2=147125&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/MachineLICM.cpp (original) +++ llvm/trunk/lib/CodeGen/MachineLICM.cpp Wed Dec 21 20:05:40 2011 @@ -215,13 +215,25 @@ /// If not then a load from this mbb may not be safe to hoist. bool IsGuaranteedToExecute(MachineBasicBlock *BB); - /// HoistRegion - Walk the specified region of the CFG (defined by all - /// blocks dominated by the specified block, and that are in the current - /// loop) in depth first order w.r.t the DominatorTree. This allows us to - /// visit definitions before uses, allowing us to hoist a loop body in one - /// pass without iteration. + void EnterScope(MachineBasicBlock *MBB); + + void ExitScope(MachineBasicBlock *MBB); + + /// ExitScopeIfDone - Destroy scope for the MBB that corresponds to given + /// dominator tree node if its a leaf or all of its children are done. Walk + /// up the dominator tree to destroy ancestors which are now done. + void ExitScopeIfDone(MachineDomTreeNode *Node, + DenseMap &OpenChildren, + DenseMap &ParentMap); + + /// HoistOutOfLoop - Walk the specified loop in the CFG (defined by all + /// blocks dominated by the specified header block, and that are in the + /// current loop) in depth first order w.r.t the DominatorTree. This allows + /// us to visit definitions before uses, allowing us to hoist a loop body in + /// one pass without iteration. /// - void HoistRegion(MachineDomTreeNode *N, bool IsHeader = false); + void HoistOutOfLoop(MachineDomTreeNode *LoopHeaderNode); + void HoistRegion(MachineDomTreeNode *N, bool IsHeader); /// getRegisterClassIDAndCost - For a given MI, register, and the operand /// index, return the ID and cost of its representative register class by @@ -356,7 +368,7 @@ // being hoisted. MachineDomTreeNode *N = DT->getNode(CurLoop->getHeader()); FirstInLoop = true; - HoistRegion(N, true); + HoistOutOfLoop(N); CSEMap.clear(); } } @@ -605,57 +617,126 @@ return true; } -/// HoistRegion - Walk the specified region of the CFG (defined by all blocks -/// dominated by the specified block, and that are in the current loop) in depth -/// first order w.r.t the DominatorTree. This allows us to visit definitions -/// before uses, allowing us to hoist a loop body in one pass without iteration. -/// -void MachineLICM::HoistRegion(MachineDomTreeNode *N, bool IsHeader) { - assert(N != 0 && "Null dominator tree node?"); - MachineBasicBlock *BB = N->getBlock(); - - // If the header of the loop containing this basic block is a landing pad, - // then don't try to hoist instructions out of this loop. - const MachineLoop *ML = MLI->getLoopFor(BB); - if (ML && ML->getHeader()->isLandingPad()) return; +void MachineLICM::EnterScope(MachineBasicBlock *MBB) { + DEBUG(dbgs() << "Entering: " << MBB->getName() << '\n'); + + // Remember livein register pressure. + BackTrace.push_back(RegPressure); +} - // If this subregion is not in the top level loop at all, exit. - if (!CurLoop->contains(BB)) return; +void MachineLICM::ExitScope(MachineBasicBlock *MBB) { + DEBUG(dbgs() << "Exiting: " << MBB->getName() << '\n'); + BackTrace.pop_back(); +} - MachineBasicBlock *Preheader = getCurPreheader(); - if (!Preheader) +/// ExitScopeIfDone - Destroy scope for the MBB that corresponds to the given +/// dominator tree node if its a leaf or all of its children are done. Walk +/// up the dominator tree to destroy ancestors which are now done. +void MachineLICM::ExitScopeIfDone(MachineDomTreeNode *Node, + DenseMap &OpenChildren, + DenseMap &ParentMap) { + if (OpenChildren[Node]) return; - if (IsHeader) { + // Pop scope. + ExitScope(Node->getBlock()); + + // Now traverse upwards to pop ancestors whose offsprings are all done. + while (MachineDomTreeNode *Parent = ParentMap[Node]) { + unsigned Left = --OpenChildren[Parent]; + if (Left != 0) + break; + ExitScope(Parent->getBlock()); + Node = Parent; + } +} + +/// HoistOutOfLoop - Walk the specified loop in the CFG (defined by all +/// blocks dominated by the specified header block, and that are in the +/// current loop) in depth first order w.r.t the DominatorTree. This allows +/// us to visit definitions before uses, allowing us to hoist a loop body in +/// one pass without iteration. +/// +void MachineLICM::HoistOutOfLoop(MachineDomTreeNode *HeaderN) { + SmallVector Scopes; + SmallVector WorkList; + DenseMap ParentMap; + DenseMap OpenChildren; + + // Perform a DFS walk to determine the order of visit. + WorkList.push_back(HeaderN); + do { + MachineDomTreeNode *Node = WorkList.pop_back_val(); + assert(Node != 0 && "Null dominator tree node?"); + MachineBasicBlock *BB = Node->getBlock(); + + // If the header of the loop containing this basic block is a landing pad, + // then don't try to hoist instructions out of this loop. + const MachineLoop *ML = MLI->getLoopFor(BB); + if (ML && ML->getHeader()->isLandingPad()) + continue; + + // If this subregion is not in the top level loop at all, exit. + if (!CurLoop->contains(BB)) + continue; + + Scopes.push_back(Node); + const std::vector &Children = Node->getChildren(); + unsigned NumChildren = Children.size(); + + // Don't hoist things out of a large switch statement. This often causes + // code to be hoisted that wasn't going to be executed, and increases + // register pressure in a situation where it's likely to matter. + if (BB->succ_size() >= 25) + NumChildren = 0; + + OpenChildren[Node] = NumChildren; + // Add children in reverse order as then the next popped worklist node is + // the first child of this node. This means we ultimately traverse the + // DOM tree in exactly the same order as if we'd recursed. + for (int i = (int)NumChildren-1; i >= 0; --i) { + MachineDomTreeNode *Child = Children[i]; + ParentMap[Child] = Node; + WorkList.push_back(Child); + } + } while (!WorkList.empty()); + + if (Scopes.size() != 0) { + MachineBasicBlock *Preheader = getCurPreheader(); + if (!Preheader) + return; + // Compute registers which are livein into the loop headers. RegSeen.clear(); BackTrace.clear(); InitRegPressure(Preheader); } - // Remember livein register pressure. - BackTrace.push_back(RegPressure); + // Now perform LICM. + for (unsigned i = 0, e = Scopes.size(); i != e; ++i) { + MachineDomTreeNode *Node = Scopes[i]; + MachineBasicBlock *MBB = Node->getBlock(); - SpeculationState = SpeculateUnknown; - for (MachineBasicBlock::iterator - MII = BB->begin(), E = BB->end(); MII != E; ) { - MachineBasicBlock::iterator NextMII = MII; ++NextMII; - MachineInstr *MI = &*MII; - if (!Hoist(MI, Preheader)) - UpdateRegPressure(MI); - MII = NextMII; - } + MachineBasicBlock *Preheader = getCurPreheader(); + if (!Preheader) + continue; - // Don't hoist things out of a large switch statement. This often causes - // code to be hoisted that wasn't going to be executed, and increases - // register pressure in a situation where it's likely to matter. - if (BB->succ_size() < 25) { - const std::vector &Children = N->getChildren(); - for (unsigned I = 0, E = Children.size(); I != E; ++I) - HoistRegion(Children[I]); - } + EnterScope(MBB); - BackTrace.pop_back(); + // Process the block + SpeculationState = SpeculateUnknown; + for (MachineBasicBlock::iterator + MII = MBB->begin(), E = MBB->end(); MII != E; ) { + MachineBasicBlock::iterator NextMII = MII; ++NextMII; + MachineInstr *MI = &*MII; + if (!Hoist(MI, Preheader)) + UpdateRegPressure(MI); + MII = NextMII; + } + + // If it's a leaf node, it's done. Traverse upwards to pop ancestors. + ExitScopeIfDone(Node, OpenChildren, ParentMap); + } } static bool isOperandKill(const MachineOperand &MO, MachineRegisterInfo *MRI) { From rafael.espindola at gmail.com Wed Dec 21 20:06:17 2011 From: rafael.espindola at gmail.com (Rafael Espindola) Date: Thu, 22 Dec 2011 02:06:17 -0000 Subject: [llvm-commits] [llvm] r147126 - /llvm/trunk/lib/Target/PowerPC/MCTargetDesc/CMakeLists.txt Message-ID: <20111222020617.B5D362A6C12C@llvm.org> Author: rafael Date: Wed Dec 21 20:06:17 2011 New Revision: 147126 URL: http://llvm.org/viewvc/llvm-project?rev=147126&view=rev Log: Fix cmake. Modified: llvm/trunk/lib/Target/PowerPC/MCTargetDesc/CMakeLists.txt Modified: llvm/trunk/lib/Target/PowerPC/MCTargetDesc/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/MCTargetDesc/CMakeLists.txt?rev=147126&r1=147125&r2=147126&view=diff ============================================================================== --- llvm/trunk/lib/Target/PowerPC/MCTargetDesc/CMakeLists.txt (original) +++ llvm/trunk/lib/Target/PowerPC/MCTargetDesc/CMakeLists.txt Wed Dec 21 20:06:17 2011 @@ -4,6 +4,7 @@ PPCMCAsmInfo.cpp PPCMCCodeEmitter.cpp PPCPredicates.cpp + PPCELFObjectWriter.cpp ) add_dependencies(LLVMPowerPCDesc PowerPCCommonTableGen) From mcrosier at apple.com Wed Dec 21 20:12:38 2011 From: mcrosier at apple.com (Chad Rosier) Date: Wed, 21 Dec 2011 18:12:38 -0800 Subject: [llvm-commits] [PATCH] AVX vmovaps +vxoprs + vinsertf128 DAG combine to vmovaps Message-ID: <9B9D99A1-48D5-4E4A-A32B-C97F167EFB51@apple.com> This patch is for an AVX specific DAGcombine optimization. The following code: __m256 foo(float *f) { return _mm256_castps128_ps256 (_mm_load_ps(f)); } generates this assembly: vmovaps (%rdi), %xmm0 vxorps %ymm1, %ymm1, %ymm1 vinsertf128 $0, %xmm0, %ymm1, %ymm0 On AVX enabled processors, the vmovaps will zero the upper bits (255:128) of the corresponding YMM register. Therefore, the vxorps and vinsertf128 instructions are not necessary. This patch implements a DAG combine that removes the unnecessary vxorps and vinsertf128 instructions. Currently, this is only working as an enhancement to one of Bruno's DAGcombines (r135727), but I do plan on making this more general in the future. Chad -------------- next part -------------- A non-text attachment was scrubbed... Name: vzext_load128.patch Type: application/octet-stream Size: 4552 bytes Desc: not available Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20111221/da6900e8/attachment.obj From peter_cooper at apple.com Wed Dec 21 20:13:25 2011 From: peter_cooper at apple.com (Pete Cooper) Date: Thu, 22 Dec 2011 02:13:25 -0000 Subject: [llvm-commits] [llvm] r147127 - /llvm/trunk/lib/CodeGen/MachineLICM.cpp Message-ID: <20111222021325.C07C72A6C12C@llvm.org> Author: pete Date: Wed Dec 21 20:13:25 2011 New Revision: 147127 URL: http://llvm.org/viewvc/llvm-project?rev=147127&view=rev Log: Hoisted some loop invariant smallvector lookups out of a MachineLICM loop Modified: llvm/trunk/lib/CodeGen/MachineLICM.cpp Modified: llvm/trunk/lib/CodeGen/MachineLICM.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineLICM.cpp?rev=147127&r1=147126&r2=147127&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/MachineLICM.cpp (original) +++ llvm/trunk/lib/CodeGen/MachineLICM.cpp Wed Dec 21 20:13:25 2011 @@ -1036,9 +1036,11 @@ continue; unsigned RCId = CI->first; + unsigned Limit = RegLimit[RCId]; + int Cost = CI->second; for (unsigned i = BackTrace.size(); i != 0; --i) { SmallVector &RP = BackTrace[i-1]; - if (RP[RCId] + CI->second >= RegLimit[RCId]) + if (RP[RCId] + Cost >= Limit) return true; } } From rafael.espindola at gmail.com Wed Dec 21 20:28:25 2011 From: rafael.espindola at gmail.com (Rafael Espindola) Date: Thu, 22 Dec 2011 02:28:25 -0000 Subject: [llvm-commits] [llvm] r147129 - in /llvm/trunk/lib: MC/ELFObjectWriter.cpp MC/ELFObjectWriter.h Target/MBlaze/MCTargetDesc/CMakeLists.txt Target/MBlaze/MCTargetDesc/MBlazeAsmBackend.cpp Target/MBlaze/MCTargetDesc/MBlazeELFObjectWriter.cpp Target/MBlaze/MCTargetDesc/MBlazeMCTargetDesc.h Message-ID: <20111222022825.60C372A6C12C@llvm.org> Author: rafael Date: Wed Dec 21 20:28:24 2011 New Revision: 147129 URL: http://llvm.org/viewvc/llvm-project?rev=147129&view=rev Log: Move the MBlaze ELF writer bits to lib/Target/MBlaze. Added: llvm/trunk/lib/Target/MBlaze/MCTargetDesc/MBlazeELFObjectWriter.cpp Modified: llvm/trunk/lib/MC/ELFObjectWriter.cpp llvm/trunk/lib/MC/ELFObjectWriter.h llvm/trunk/lib/Target/MBlaze/MCTargetDesc/CMakeLists.txt llvm/trunk/lib/Target/MBlaze/MCTargetDesc/MBlazeAsmBackend.cpp llvm/trunk/lib/Target/MBlaze/MCTargetDesc/MBlazeMCTargetDesc.h Modified: llvm/trunk/lib/MC/ELFObjectWriter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/ELFObjectWriter.cpp?rev=147129&r1=147128&r2=147129&view=diff ============================================================================== --- llvm/trunk/lib/MC/ELFObjectWriter.cpp (original) +++ llvm/trunk/lib/MC/ELFObjectWriter.cpp Wed Dec 21 20:28:24 2011 @@ -1261,9 +1261,8 @@ case ELF::EM_ARM: case ELF::EM_PPC: case ELF::EM_PPC64: - return new ELFObjectWriter(MOTW, OS, IsLittleEndian); break; case ELF::EM_MBLAZE: - return new MBlazeELFObjectWriter(MOTW, OS, IsLittleEndian); break; + return new ELFObjectWriter(MOTW, OS, IsLittleEndian); break; case ELF::EM_MIPS: return new MipsELFObjectWriter(MOTW, OS, IsLittleEndian); break; default: llvm_unreachable("Unsupported architecture"); break; @@ -1280,51 +1279,6 @@ } /// START OF SUBCLASSES for ELFObjectWriter -//===- MBlazeELFObjectWriter -------------------------------------------===// - -MBlazeELFObjectWriter::MBlazeELFObjectWriter(MCELFObjectTargetWriter *MOTW, - raw_ostream &_OS, - bool IsLittleEndian) - : ELFObjectWriter(MOTW, _OS, IsLittleEndian) { -} - -MBlazeELFObjectWriter::~MBlazeELFObjectWriter() { -} - -unsigned MBlazeELFObjectWriter::GetRelocType(const MCValue &Target, - const MCFixup &Fixup, - bool IsPCRel, - bool IsRelocWithSymbol, - int64_t Addend) const { - // determine the type of the relocation - unsigned Type; - if (IsPCRel) { - switch ((unsigned)Fixup.getKind()) { - default: - llvm_unreachable("Unimplemented"); - case FK_PCRel_4: - Type = ELF::R_MICROBLAZE_64_PCREL; - break; - case FK_PCRel_2: - Type = ELF::R_MICROBLAZE_32_PCREL; - break; - } - } else { - switch ((unsigned)Fixup.getKind()) { - default: llvm_unreachable("invalid fixup kind!"); - case FK_Data_4: - Type = ((IsRelocWithSymbol || Addend !=0) - ? ELF::R_MICROBLAZE_32 - : ELF::R_MICROBLAZE_64); - break; - case FK_Data_2: - Type = ELF::R_MICROBLAZE_32; - break; - } - } - return Type; -} - //===- MipsELFObjectWriter -------------------------------------------===// MipsELFObjectWriter::MipsELFObjectWriter(MCELFObjectTargetWriter *MOTW, Modified: llvm/trunk/lib/MC/ELFObjectWriter.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/ELFObjectWriter.h?rev=147129&r1=147128&r2=147129&view=diff ============================================================================== --- llvm/trunk/lib/MC/ELFObjectWriter.h (original) +++ llvm/trunk/lib/MC/ELFObjectWriter.h Wed Dec 21 20:28:24 2011 @@ -355,21 +355,6 @@ int64_t Addend) const; }; - //===- MBlazeELFObjectWriter -------------------------------------------===// - - class MBlazeELFObjectWriter : public ELFObjectWriter { - public: - MBlazeELFObjectWriter(MCELFObjectTargetWriter *MOTW, - raw_ostream &_OS, - bool IsLittleEndian); - - virtual ~MBlazeELFObjectWriter(); - protected: - virtual unsigned GetRelocType(const MCValue &Target, const MCFixup &Fixup, - bool IsPCRel, bool IsRelocWithSymbol, - int64_t Addend) const; - }; - //===- MipsELFObjectWriter -------------------------------------------===// class MipsELFObjectWriter : public ELFObjectWriter { Modified: llvm/trunk/lib/Target/MBlaze/MCTargetDesc/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MBlaze/MCTargetDesc/CMakeLists.txt?rev=147129&r1=147128&r2=147129&view=diff ============================================================================== --- llvm/trunk/lib/Target/MBlaze/MCTargetDesc/CMakeLists.txt (original) +++ llvm/trunk/lib/Target/MBlaze/MCTargetDesc/CMakeLists.txt Wed Dec 21 20:28:24 2011 @@ -3,6 +3,7 @@ MBlazeMCAsmInfo.cpp MBlazeMCCodeEmitter.cpp MBlazeMCTargetDesc.cpp + MBlazeELFObjectWriter.cpp ) add_dependencies(LLVMMBlazeDesc MBlazeCommonTableGen) Modified: llvm/trunk/lib/Target/MBlaze/MCTargetDesc/MBlazeAsmBackend.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MBlaze/MCTargetDesc/MBlazeAsmBackend.cpp?rev=147129&r1=147128&r2=147129&view=diff ============================================================================== --- llvm/trunk/lib/Target/MBlaze/MCTargetDesc/MBlazeAsmBackend.cpp (original) +++ llvm/trunk/lib/Target/MBlaze/MCTargetDesc/MBlazeAsmBackend.cpp Wed Dec 21 20:28:24 2011 @@ -39,12 +39,6 @@ namespace { -class MBlazeELFObjectWriter : public MCELFObjectTargetWriter { -public: - MBlazeELFObjectWriter(uint8_t OSABI) - : MCELFObjectTargetWriter(/*is64Bit*/ false, OSABI, ELF::EM_MBLAZE, - /*HasRelocationAddend*/ true) {} -}; class MBlazeAsmBackend : public MCAsmBackend { public: @@ -131,8 +125,7 @@ uint64_t Value) const; MCObjectWriter *createObjectWriter(raw_ostream &OS) const { - return createELFObjectWriter(new MBlazeELFObjectWriter(OSABI), OS, - /*IsLittleEndian*/ false); + return createMBlazeELFObjectWriter(OS, OSABI); } }; Added: llvm/trunk/lib/Target/MBlaze/MCTargetDesc/MBlazeELFObjectWriter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MBlaze/MCTargetDesc/MBlazeELFObjectWriter.cpp?rev=147129&view=auto ============================================================================== --- llvm/trunk/lib/Target/MBlaze/MCTargetDesc/MBlazeELFObjectWriter.cpp (added) +++ llvm/trunk/lib/Target/MBlaze/MCTargetDesc/MBlazeELFObjectWriter.cpp Wed Dec 21 20:28:24 2011 @@ -0,0 +1,77 @@ +//===-- MBlazeELFObjectWriter.cpp - MBlaze ELF Writer ---------------------===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// + +#include "MCTargetDesc/MBlazeMCTargetDesc.h" +#include "llvm/MC/MCELFObjectWriter.h" +#include "llvm/MC/MCFixup.h" +#include "llvm/Support/ErrorHandling.h" + +using namespace llvm; + +namespace { + class MBlazeELFObjectWriter : public MCELFObjectTargetWriter { + public: + MBlazeELFObjectWriter(uint8_t OSABI); + + virtual ~MBlazeELFObjectWriter(); + protected: + virtual unsigned GetRelocType(const MCValue &Target, const MCFixup &Fixup, + bool IsPCRel, bool IsRelocWithSymbol, + int64_t Addend) const; + }; +} + +MBlazeELFObjectWriter::MBlazeELFObjectWriter(uint8_t OSABI) + : MCELFObjectTargetWriter(/*Is64Bit*/ false, OSABI, ELF::EM_MBLAZE, + /*HasRelocationAddend*/ false) {} + +MBlazeELFObjectWriter::~MBlazeELFObjectWriter() { +} + +unsigned MBlazeELFObjectWriter::GetRelocType(const MCValue &Target, + const MCFixup &Fixup, + bool IsPCRel, + bool IsRelocWithSymbol, + int64_t Addend) const { + // determine the type of the relocation + unsigned Type; + if (IsPCRel) { + switch ((unsigned)Fixup.getKind()) { + default: + llvm_unreachable("Unimplemented"); + case FK_PCRel_4: + Type = ELF::R_MICROBLAZE_64_PCREL; + break; + case FK_PCRel_2: + Type = ELF::R_MICROBLAZE_32_PCREL; + break; + } + } else { + switch ((unsigned)Fixup.getKind()) { + default: llvm_unreachable("invalid fixup kind!"); + case FK_Data_4: + Type = ((IsRelocWithSymbol || Addend !=0) + ? ELF::R_MICROBLAZE_32 + : ELF::R_MICROBLAZE_64); + break; + case FK_Data_2: + Type = ELF::R_MICROBLAZE_32; + break; + } + } + return Type; +} + + + +MCObjectWriter *llvm::createMBlazeELFObjectWriter(raw_ostream &OS, + uint8_t OSABI) { + MCELFObjectTargetWriter *MOTW = new MBlazeELFObjectWriter(OSABI); + return createELFObjectWriter(MOTW, OS, /*IsLittleEndian=*/ false); +} Modified: llvm/trunk/lib/Target/MBlaze/MCTargetDesc/MBlazeMCTargetDesc.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MBlaze/MCTargetDesc/MBlazeMCTargetDesc.h?rev=147129&r1=147128&r2=147129&view=diff ============================================================================== --- llvm/trunk/lib/Target/MBlaze/MCTargetDesc/MBlazeMCTargetDesc.h (original) +++ llvm/trunk/lib/Target/MBlaze/MCTargetDesc/MBlazeMCTargetDesc.h Wed Dec 21 20:28:24 2011 @@ -14,24 +14,29 @@ #ifndef MBLAZEMCTARGETDESC_H #define MBLAZEMCTARGETDESC_H +#include "llvm/Support/DataTypes.h" + namespace llvm { class MCAsmBackend; class MCContext; class MCCodeEmitter; class MCInstrInfo; +class MCObjectWriter; class MCSubtargetInfo; class Target; class StringRef; class formatted_raw_ostream; +class raw_ostream; extern Target TheMBlazeTarget; MCCodeEmitter *createMBlazeMCCodeEmitter(const MCInstrInfo &MCII, const MCSubtargetInfo &STI, MCContext &Ctx); - + MCAsmBackend *createMBlazeAsmBackend(const Target &T, StringRef TT); +MCObjectWriter *createMBlazeELFObjectWriter(raw_ostream &OS, uint8_t OSABI); } // End llvm namespace // Defines symbolic names for MBlaze registers. This defines a mapping from From mcrosier at apple.com Wed Dec 21 20:40:57 2011 From: mcrosier at apple.com (Chad Rosier) Date: Thu, 22 Dec 2011 02:40:57 -0000 Subject: [llvm-commits] [llvm] r147131 - in /llvm/trunk: lib/Transforms/Scalar/LoopUnswitch.cpp test/Transforms/LoopUnswitch/2011-11-18-SimpleSwitch.ll test/Transforms/LoopUnswitch/2011-11-18-TwoSwitches-Threshold.ll test/Transforms/LoopUnswitch/2011-11-18-TwoSwitches.ll Message-ID: <20111222024057.A02C82A6C12C@llvm.org> Author: mcrosier Date: Wed Dec 21 20:40:57 2011 New Revision: 147131 URL: http://llvm.org/viewvc/llvm-project?rev=147131&view=rev Log: Speculatively revert r146578 to determine if it is the cause of a number of performance regressions (both execution-time and compile-time) on our nightly testers. Original commit message: Fix for bug #11429: Wrong behaviour for switches. Small improvement for code size heuristics. Removed: llvm/trunk/test/Transforms/LoopUnswitch/2011-11-18-SimpleSwitch.ll llvm/trunk/test/Transforms/LoopUnswitch/2011-11-18-TwoSwitches-Threshold.ll llvm/trunk/test/Transforms/LoopUnswitch/2011-11-18-TwoSwitches.ll Modified: llvm/trunk/lib/Transforms/Scalar/LoopUnswitch.cpp Modified: llvm/trunk/lib/Transforms/Scalar/LoopUnswitch.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/LoopUnswitch.cpp?rev=147131&r1=147130&r2=147131&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Scalar/LoopUnswitch.cpp (original) +++ llvm/trunk/lib/Transforms/Scalar/LoopUnswitch.cpp Wed Dec 21 20:40:57 2011 @@ -71,9 +71,7 @@ // LoopProcessWorklist - Used to check if second loop needs processing // after RewriteLoopBodyWithConditionConstant rewrites first loop. std::vector LoopProcessWorklist; - - // FIXME: Consider custom class for this. - std::map > UnswitchedVals; + SmallPtrSet UnswitchedVals; bool OptimizeForSize; bool redoLoop; @@ -119,15 +117,7 @@ private: virtual void releaseMemory() { - // We need to forget about all switches in the current loop. - // FIXME: Do it better than enumerating all blocks of code - // and see if it is a switch instruction. - for (Loop::block_iterator I = currentLoop->block_begin(), - E = currentLoop->block_end(); I != E; ++I) { - SwitchInst* SI = dyn_cast((*I)->getTerminator()); - if (SI) - UnswitchedVals.erase(SI); - } + UnswitchedVals.clear(); } /// RemoveLoopFromWorklist - If the specified loop is on the loop worklist, @@ -138,12 +128,6 @@ if (I != LoopProcessWorklist.end()) LoopProcessWorklist.erase(I); } - - /// For new loop switches we clone info about values that was - /// already unswitched and has redundant successors. - /// Note, that new loop data is stored inside the VMap. - void CloneUnswitchedVals(const ValueToValueMapTy& VMap, - const BasicBlock* SrcBB); void initLoopData() { loopHeader = currentLoop->getHeader(); @@ -271,25 +255,13 @@ } else if (SwitchInst *SI = dyn_cast(TI)) { Value *LoopCond = FindLIVLoopCondition(SI->getCondition(), currentLoop, Changed); - unsigned NumCases = SI->getNumCases(); - if (LoopCond && NumCases > 1) { + if (LoopCond && SI->getNumCases() > 1) { // Find a value to unswitch on: // FIXME: this should chose the most expensive case! // FIXME: scan for a case with a non-critical edge? - Constant *UnswitchVal = NULL; - + Constant *UnswitchVal = SI->getCaseValue(1); // Do not process same value again and again. - // At this point we have some cases already unswitched and - // some not yet unswitched. Let's find the first not yet unswitched one. - for (unsigned i = 1; i < NumCases; ++i) { - Constant* UnswitchValCandidate = SI->getCaseValue(i); - if (!UnswitchedVals[SI].count(UnswitchValCandidate)) { - UnswitchVal = UnswitchValCandidate; - break; - } - } - - if (!UnswitchVal) + if (!UnswitchedVals.insert(UnswitchVal)) continue; if (UnswitchIfProfitable(LoopCond, UnswitchVal)) { @@ -315,23 +287,6 @@ return Changed; } -/// For new loop switches we clone info about values that was -/// already unswitched and has redundant successors. -/// Not that new loop data is stored inside the VMap. -void LoopUnswitch::CloneUnswitchedVals(const ValueToValueMapTy& VMap, - const BasicBlock* SrcBB) { - - const SwitchInst* SI = dyn_cast(SrcBB->getTerminator()); - if (SI && UnswitchedVals.count(SI)) { - // Don't clone a totally simplified switch. - if (isa(SI->getCondition())) - return; - Value* I = VMap.lookup(SI); - assert(I && "All instructions that are in SrcBB must be in VMap."); - UnswitchedVals[cast(I)] = UnswitchedVals[SI]; - } -} - /// isTrivialLoopExitBlock - Check to see if all paths from BB exit the /// loop with no side effects (including infinite loops). /// @@ -423,25 +378,14 @@ // Check to see if a successor of the switch is guaranteed to go to the // latch block or exit through a one exit block without having any // side-effects. If so, determine the value of Cond that causes it to do - // this. - // Note that we can't trivially unswitch on the default case or - // on already unswitched cases. - for (unsigned i = 1, e = SI->getNumSuccessors(); i != e; ++i) { - BasicBlock* LoopExitCandidate; - if ((LoopExitCandidate = isTrivialLoopExitBlock(currentLoop, + // this. Note that we can't trivially unswitch on the default case. + for (unsigned i = 1, e = SI->getNumSuccessors(); i != e; ++i) + if ((LoopExitBB = isTrivialLoopExitBlock(currentLoop, SI->getSuccessor(i)))) { // Okay, we found a trivial case, remember the value that is trivial. - ConstantInt* CaseVal = SI->getCaseValue(i); - - // Check that it was not unswitched before, since already unswitched - // trivial vals are looks trivial too. - if (UnswitchedVals[SI].count(CaseVal)) - continue; - LoopExitBB = LoopExitCandidate; - if (Val) *Val = CaseVal; + if (Val) *Val = SI->getCaseValue(i); break; } - } } // If we didn't find a single unique LoopExit block, or if the loop exit block @@ -503,14 +447,8 @@ // expansion, and the number of basic blocks, to avoid loops with // large numbers of branches which cause loop unswitching to go crazy. // This is a very ad-hoc heuristic. - - unsigned NumUnswitched = - (NumSwitches + NumBranches) + 1 /*take in account current iteration*/; - - unsigned NumInsts = Metrics.NumInsts * NumUnswitched; - unsigned NumBlocks = Metrics.NumBlocks * NumUnswitched; - - if (NumInsts > Threshold || NumBlocks * 5 > Threshold || + if (Metrics.NumInsts > Threshold || + Metrics.NumBlocks * 5 > Threshold || Metrics.containsIndirectBr || Metrics.isRecursive) { DEBUG(dbgs() << "NOT unswitching loop %" << currentLoop->getHeader()->getName() << ", cost too high: " @@ -682,12 +620,6 @@ ValueToValueMapTy VMap; for (unsigned i = 0, e = LoopBlocks.size(); i != e; ++i) { BasicBlock *NewBB = CloneBasicBlock(LoopBlocks[i], VMap, ".us", F); - - // Inherit simplified switches info for NewBB - // We needn't pass NewBB since its instructions are already contained - // inside the VMap. - CloneUnswitchedVals(VMap, LoopBlocks[i]); - NewBlocks.push_back(NewBB); VMap[LoopBlocks[i]] = NewBB; // Keep the BB mapping. LPM->cloneBasicBlockSimpleAnalysis(LoopBlocks[i], NewBB, L); @@ -1013,9 +945,6 @@ BasicBlock *Switch = SI->getParent(); BasicBlock *SISucc = SI->getSuccessor(DeadCase); BasicBlock *Latch = L->getLoopLatch(); - - UnswitchedVals[SI].insert(Val); - if (!SI->findCaseDest(SISucc)) continue; // Edge is critical. // If the DeadCase successor dominates the loop latch, then the // transformation isn't safe since it will delete the sole predecessor edge Removed: llvm/trunk/test/Transforms/LoopUnswitch/2011-11-18-SimpleSwitch.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/LoopUnswitch/2011-11-18-SimpleSwitch.ll?rev=147130&view=auto ============================================================================== --- llvm/trunk/test/Transforms/LoopUnswitch/2011-11-18-SimpleSwitch.ll (original) +++ llvm/trunk/test/Transforms/LoopUnswitch/2011-11-18-SimpleSwitch.ll (removed) @@ -1,91 +0,0 @@ -; RUN: opt -loop-unswitch -disable-output -stats -info-output-file - < %s | FileCheck --check-prefix=STATS %s -; RUN: opt -S -loop-unswitch -verify-loop-info -verify-dom-info %s | FileCheck %s - -; STATS: 1 loop-simplify - Number of pre-header or exit blocks inserted -; STATS: 2 loop-unswitch - Number of switches unswitched - -; CHECK: %1 = icmp eq i32 %c, 1 -; CHECK-NEXT: br i1 %1, label %.split.us, label %..split_crit_edge - -; CHECK: ..split_crit_edge: ; preds = %0 -; CHECK-NEXT: br label %.split - -; CHECK: .split.us: ; preds = %0 -; CHECK-NEXT: br label %loop_begin.us - -; CHECK: loop_begin.us: ; preds = %loop_begin.backedge.us, %.split.us -; CHECK-NEXT: %var_val.us = load i32* %var -; CHECK-NEXT: switch i32 1, label %default.us-lcssa.us [ -; CHECK-NEXT: i32 1, label %inc.us - -; CHECK: inc.us: ; preds = %loop_begin.us -; CHECK-NEXT: call void @incf() noreturn nounwind -; CHECK-NEXT: br label %loop_begin.backedge.us - -; CHECK: .split: ; preds = %..split_crit_edge -; CHECK-NEXT: %2 = icmp eq i32 %c, 2 -; CHECK-NEXT: br i1 %2, label %.split.split.us, label %.split..split.split_crit_edge - -; CHECK: .split..split.split_crit_edge: ; preds = %.split -; CHECK-NEXT: br label %.split.split - -; CHECK: .split.split.us: ; preds = %.split -; CHECK-NEXT: br label %loop_begin.us1 - -; CHECK: loop_begin.us1: ; preds = %loop_begin.backedge.us5, %.split.split.us -; CHECK-NEXT: %var_val.us2 = load i32* %var -; CHECK-NEXT: switch i32 2, label %default.us-lcssa.us-lcssa.us [ -; CHECK-NEXT: i32 1, label %inc.us3 -; CHECK-NEXT: i32 2, label %dec.us4 -; CHECK-NEXT: ] - -; CHECK: dec.us4: ; preds = %loop_begin.us1 -; CHECK-NEXT: call void @decf() noreturn nounwind -; CHECK-NEXT: br label %loop_begin.backedge.us5 - -; CHECK: .split.split: ; preds = %.split..split.split_crit_edge -; CHECK-NEXT: br label %loop_begin - -; CHECK: loop_begin: ; preds = %loop_begin.backedge, %.split.split -; CHECK-NEXT: %var_val = load i32* %var -; CHECK-NEXT: switch i32 %c, label %default.us-lcssa.us-lcssa [ -; CHECK-NEXT: i32 1, label %inc -; CHECK-NEXT: i32 2, label %dec -; CHECK-NEXT: ] - -; CHECK: inc: ; preds = %loop_begin -; CHECK-NEXT: br i1 true, label %us-unreachable.us-lcssa, label %inc.split - -; CHECK: dec: ; preds = %loop_begin -; CHECK-NEXT: br i1 true, label %us-unreachable6, label %dec.split - -define i32 @test(i32* %var) { - %mem = alloca i32 - store i32 2, i32* %mem - %c = load i32* %mem - - br label %loop_begin - -loop_begin: - - %var_val = load i32* %var - - switch i32 %c, label %default [ - i32 1, label %inc - i32 2, label %dec - ] - -inc: - call void @incf() noreturn nounwind - br label %loop_begin -dec: - call void @decf() noreturn nounwind - br label %loop_begin -default: - br label %loop_exit -loop_exit: - ret i32 0 -} - -declare void @incf() noreturn -declare void @decf() noreturn Removed: llvm/trunk/test/Transforms/LoopUnswitch/2011-11-18-TwoSwitches-Threshold.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/LoopUnswitch/2011-11-18-TwoSwitches-Threshold.ll?rev=147130&view=auto ============================================================================== --- llvm/trunk/test/Transforms/LoopUnswitch/2011-11-18-TwoSwitches-Threshold.ll (original) +++ llvm/trunk/test/Transforms/LoopUnswitch/2011-11-18-TwoSwitches-Threshold.ll (removed) @@ -1,84 +0,0 @@ -; RUN: opt -loop-unswitch -loop-unswitch-threshold 30 -disable-output -stats -info-output-file - < %s | FileCheck --check-prefix=STATS %s -; RUN: opt -S -loop-unswitch -loop-unswitch-threshold 30 -verify-loop-info -verify-dom-info %s | FileCheck %s - -; STATS: 1 loop-simplify - Number of pre-header or exit blocks inserted -; STATS: 1 loop-unswitch - Number of switches unswitched - -; ModuleID = '../llvm/test/Transforms/LoopUnswitch/2011-11-18-TwoSwitches.ll' - -; CHECK: %1 = icmp eq i32 %c, 1 -; CHECK-NEXT: br i1 %1, label %.split.us, label %..split_crit_edge - -; CHECK: ..split_crit_edge: ; preds = %0 -; CHECK-NEXT: br label %.split - -; CHECK: .split.us: ; preds = %0 -; CHECK-NEXT: br label %loop_begin.us - -; CHECK: loop_begin.us: ; preds = %loop_begin.backedge.us, %.split.us -; CHECK: switch i32 1, label %second_switch.us [ -; CHECK-NEXT: i32 1, label %inc.us - -; CHECK: inc.us: ; preds = %second_switch.us, %loop_begin.us -; CHECK-NEXT: call void @incf() noreturn nounwind -; CHECK-NEXT: br label %loop_begin.backedge.us - -; CHECK: second_switch.us: ; preds = %loop_begin.us -; CHECK-NEXT: switch i32 %d, label %default.us [ -; CHECK-NEXT: i32 1, label %inc.us -; CHECK-NEXT: ] - -; CHECK: .split: ; preds = %..split_crit_edge -; CHECK-NEXT: br label %loop_begin - -; CHECK: loop_begin: ; preds = %loop_begin.backedge, %.split -; CHECK: switch i32 %c, label %second_switch [ -; CHECK-NEXT: i32 1, label %loop_begin.inc_crit_edge -; CHECK-NEXT: ] - -; CHECK: loop_begin.inc_crit_edge: ; preds = %loop_begin -; CHECK-NEXT: br i1 true, label %us-unreachable, label %inc - -; CHECK: second_switch: ; preds = %loop_begin -; CHECK-NEXT: switch i32 %d, label %default [ -; CHECK-NEXT: i32 1, label %inc -; CHECK-NEXT: ] - -; CHECK: inc: ; preds = %loop_begin.inc_crit_edge, %second_switch -; CHECK-NEXT: call void @incf() noreturn nounwind -; CHECK-NEXT: br label %loop_begin.backedge - -define i32 @test(i32* %var) { - %mem = alloca i32 - store i32 2, i32* %mem - %c = load i32* %mem - %d = load i32* %mem - - br label %loop_begin - -loop_begin: - - %var_val = load i32* %var - - switch i32 %c, label %second_switch [ - i32 1, label %inc - ] - -second_switch: - switch i32 %d, label %default [ - i32 1, label %inc - ] - -inc: - call void @incf() noreturn nounwind - br label %loop_begin - -default: - br label %loop_begin - -loop_exit: - ret i32 0 -} - -declare void @incf() noreturn -declare void @decf() noreturn Removed: llvm/trunk/test/Transforms/LoopUnswitch/2011-11-18-TwoSwitches.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/LoopUnswitch/2011-11-18-TwoSwitches.ll?rev=147130&view=auto ============================================================================== --- llvm/trunk/test/Transforms/LoopUnswitch/2011-11-18-TwoSwitches.ll (original) +++ llvm/trunk/test/Transforms/LoopUnswitch/2011-11-18-TwoSwitches.ll (removed) @@ -1,138 +0,0 @@ -; RUN: opt -loop-unswitch -loop-unswitch-threshold 1000 -disable-output -stats -info-output-file - < %s | FileCheck --check-prefix=STATS %s -; RUN: opt -S -loop-unswitch -loop-unswitch-threshold 1000 -verify-loop-info -verify-dom-info %s | FileCheck %s - -; STATS: 1 loop-simplify - Number of pre-header or exit blocks inserted -; STATS: 3 loop-unswitch - Number of switches unswitched - -; CHECK: %1 = icmp eq i32 %c, 1 -; CHECK-NEXT: br i1 %1, label %.split.us, label %..split_crit_edge - -; CHECK: ..split_crit_edge: ; preds = %0 -; CHECK-NEXT: br label %.split - -; CHECK: .split.us: ; preds = %0 -; CHECK-NEXT: %2 = icmp eq i32 %d, 1 -; CHECK-NEXT: br i1 %2, label %.split.us.split.us, label %.split.us..split.us.split_crit_edge - -; CHECK: .split.us..split.us.split_crit_edge: ; preds = %.split.us -; CHECK-NEXT: br label %.split.us.split - -; CHECK: .split.us.split.us: ; preds = %.split.us -; CHECK-NEXT: br label %loop_begin.us.us - -; CHECK: loop_begin.us.us: ; preds = %loop_begin.backedge.us.us, %.split.us.split.us -; CHECK-NEXT: %var_val.us.us = load i32* %var -; CHECK-NEXT: switch i32 1, label %second_switch.us.us [ -; CHECK-NEXT: i32 1, label %inc.us.us - -; CHECK: inc.us.us: ; preds = %second_switch.us.us, %loop_begin.us.us -; CHECK-NEXT: call void @incf() noreturn nounwind -; CHECK-NEXT: br label %loop_begin.backedge.us.us - -; CHECK: second_switch.us.us: ; preds = %loop_begin.us.us -; CHECK-NEXT: switch i32 1, label %default.us.us [ -; CHECK-NEXT: i32 1, label %inc.us.us - -; CHECK: .split.us.split: ; preds = %.split.us..split.us.split_crit_edge -; CHECK-NEXT: br label %loop_begin.us - -; CHECK: loop_begin.us: ; preds = %loop_begin.backedge.us, %.split.us.split -; CHECK-NEXT: %var_val.us = load i32* %var -; CHECK-NEXT: switch i32 1, label %second_switch.us [ -; CHECK-NEXT: i32 1, label %inc.us - -; CHECK: inc.us: ; preds = %second_switch.us.inc.us_crit_edge, %loop_begin.us -; CHECK-NEXT: call void @incf() noreturn nounwind -; CHECK-NEXT: br label %loop_begin.backedge.us - -; CHECK: second_switch.us: ; preds = %loop_begin.us -; CHECK-NEXT: switch i32 %d, label %default.us [ -; CHECK-NEXT: i32 1, label %second_switch.us.inc.us_crit_edge -; CHECK-NEXT: ] - -; CHECK: second_switch.us.inc.us_crit_edge: ; preds = %second_switch.us -; CHECK-NEXT: br i1 true, label %us-unreachable8, label %inc.us - -; CHECK: .split: ; preds = %..split_crit_edge -; CHECK-NEXT: %3 = icmp eq i32 %d, 1 -; CHECK-NEXT: br i1 %3, label %.split.split.us, label %.split..split.split_crit_edge - -; CHECK: .split..split.split_crit_edge: ; preds = %.split -; CHECK-NEXT: br label %.split.split - -; CHECK: .split.split.us: ; preds = %.split -; CHECK-NEXT: br label %loop_begin.us1 - -; CHECK: loop_begin.us1: ; preds = %loop_begin.backedge.us6, %.split.split.us -; CHECK-NEXT: %var_val.us2 = load i32* %var -; CHECK-NEXT: switch i32 %c, label %second_switch.us4 [ -; CHECK-NEXT: i32 1, label %loop_begin.inc_crit_edge.us -; CHECK-NEXT: ] - -; CHECK: inc.us3: ; preds = %loop_begin.inc_crit_edge.us, %second_switch.us4 -; CHECK-NEXT: call void @incf() noreturn nounwind -; CHECK-NEXT: br label %loop_begin.backedge.us6 - -; CHECK: second_switch.us4: ; preds = %loop_begin.us1 -; CHECK-NEXT: switch i32 1, label %default.us5 [ -; CHECK-NEXT: i32 1, label %inc.us3 -; CHECK-NEXT: ] - -; CHECK: loop_begin.inc_crit_edge.us: ; preds = %loop_begin.us1 -; CHECK-NEXT: br i1 true, label %us-unreachable.us-lcssa.us, label %inc.us3 - -; CHECK: .split.split: ; preds = %.split..split.split_crit_edge -; CHECK-NEXT: br label %loop_begin - -; CHECK: loop_begin: ; preds = %loop_begin.backedge, %.split.split -; CHECK-NEXT: %var_val = load i32* %var -; CHECK-NEXT: switch i32 %c, label %second_switch [ -; CHECK-NEXT: i32 1, label %loop_begin.inc_crit_edge -; CHECK-NEXT: ] - -; CHECK: loop_begin.inc_crit_edge: ; preds = %loop_begin -; CHECK-NEXT: br i1 true, label %us-unreachable.us-lcssa, label %inc - -; CHECK: second_switch: ; preds = %loop_begin -; CHECK-NEXT: switch i32 %d, label %default [ -; CHECK-NEXT: i32 1, label %second_switch.inc_crit_edge -; CHECK-NEXT: ] - -; CHECK: second_switch.inc_crit_edge: ; preds = %second_switch -; CHECK-NEXT: br i1 true, label %us-unreachable7, label %inc - - -define i32 @test(i32* %var) { - %mem = alloca i32 - store i32 2, i32* %mem - %c = load i32* %mem - %d = load i32* %mem - - br label %loop_begin - -loop_begin: - - %var_val = load i32* %var - - switch i32 %c, label %second_switch [ - i32 1, label %inc - ] - -second_switch: - switch i32 %d, label %default [ - i32 1, label %inc - ] - -inc: - call void @incf() noreturn nounwind - br label %loop_begin - -default: - br label %loop_begin - -loop_exit: - ret i32 0 -} - -declare void @incf() noreturn -declare void @decf() noreturn From rafael.espindola at gmail.com Wed Dec 21 20:58:12 2011 From: rafael.espindola at gmail.com (Rafael Espindola) Date: Thu, 22 Dec 2011 02:58:12 -0000 Subject: [llvm-commits] [llvm] r147132 - /llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMELFObjectWriter.cpp Message-ID: <20111222025812.D65F92A6C12C@llvm.org> Author: rafael Date: Wed Dec 21 20:58:12 2011 New Revision: 147132 URL: http://llvm.org/viewvc/llvm-project?rev=147132&view=rev Log: Make the virtual methods in ARMELFObjectWriter public. Modified: llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMELFObjectWriter.cpp Modified: llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMELFObjectWriter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMELFObjectWriter.cpp?rev=147132&r1=147131&r2=147132&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMELFObjectWriter.cpp (original) +++ llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMELFObjectWriter.cpp Wed Dec 21 20:58:12 2011 @@ -23,12 +23,6 @@ namespace { class ARMELFObjectWriter : public MCELFObjectTargetWriter { enum { DefaultEABIVersion = 0x05000000U }; - - const MCSymbol *ExplicitRelSym(const MCAssembler &Asm, - const MCValue &Target, - const MCFragment &F, - const MCFixup &Fixup, - bool IsPCRel) const; unsigned GetRelocTypeInner(const MCValue &Target, const MCFixup &Fixup, bool IsPCRel) const; @@ -38,11 +32,16 @@ ARMELFObjectWriter(uint8_t OSABI); virtual ~ARMELFObjectWriter(); - protected: + virtual unsigned GetRelocType(const MCValue &Target, const MCFixup &Fixup, bool IsPCRel, bool IsRelocWithSymbol, int64_t Addend) const; virtual unsigned getEFlags() const; + virtual const MCSymbol *ExplicitRelSym(const MCAssembler &Asm, + const MCValue &Target, + const MCFragment &F, + const MCFixup &Fixup, + bool IsPCRel) const; }; } From rafael.espindola at gmail.com Wed Dec 21 21:03:17 2011 From: rafael.espindola at gmail.com (Rafael Espindola) Date: Thu, 22 Dec 2011 03:03:17 -0000 Subject: [llvm-commits] [llvm] r147133 - in /llvm/trunk/lib: MC/ELFObjectWriter.cpp MC/ELFObjectWriter.h Target/Mips/MCTargetDesc/CMakeLists.txt Target/Mips/MCTargetDesc/MipsAsmBackend.cpp Target/Mips/MCTargetDesc/MipsELFObjectWriter.cpp Target/Mips/MCTargetDesc/MipsMCTargetDesc.h Message-ID: <20111222030317.A1A6B2A6C12C@llvm.org> Author: rafael Date: Wed Dec 21 21:03:17 2011 New Revision: 147133 URL: http://llvm.org/viewvc/llvm-project?rev=147133&view=rev Log: Move the Mips only bits of the ELF writer to lib/Target/Mips. Added: llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsELFObjectWriter.cpp Modified: llvm/trunk/lib/MC/ELFObjectWriter.cpp llvm/trunk/lib/MC/ELFObjectWriter.h llvm/trunk/lib/Target/Mips/MCTargetDesc/CMakeLists.txt llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsAsmBackend.cpp llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.h Modified: llvm/trunk/lib/MC/ELFObjectWriter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/ELFObjectWriter.cpp?rev=147133&r1=147132&r2=147133&view=diff ============================================================================== --- llvm/trunk/lib/MC/ELFObjectWriter.cpp (original) +++ llvm/trunk/lib/MC/ELFObjectWriter.cpp Wed Dec 21 21:03:17 2011 @@ -27,8 +27,6 @@ #include "llvm/Support/CommandLine.h" #include "llvm/ADT/StringSwitch.h" -#include "../Target/Mips/MCTargetDesc/MipsFixupKinds.h" - #include using namespace llvm; @@ -1262,9 +1260,8 @@ case ELF::EM_PPC: case ELF::EM_PPC64: case ELF::EM_MBLAZE: - return new ELFObjectWriter(MOTW, OS, IsLittleEndian); break; case ELF::EM_MIPS: - return new MipsELFObjectWriter(MOTW, OS, IsLittleEndian); break; + return new ELFObjectWriter(MOTW, OS, IsLittleEndian); break; default: llvm_unreachable("Unsupported architecture"); break; } } @@ -1277,100 +1274,3 @@ return TargetObjectWriter->GetRelocType(Target, Fixup, IsPCRel, IsRelocWithSymbol, Addend); } - -/// START OF SUBCLASSES for ELFObjectWriter -//===- MipsELFObjectWriter -------------------------------------------===// - -MipsELFObjectWriter::MipsELFObjectWriter(MCELFObjectTargetWriter *MOTW, - raw_ostream &_OS, - bool IsLittleEndian) - : ELFObjectWriter(MOTW, _OS, IsLittleEndian) {} - -MipsELFObjectWriter::~MipsELFObjectWriter() {} - -// FIXME: get the real EABI Version from the Triple. -unsigned MipsELFObjectWriter::getEFlags() const { - return ELF::EF_MIPS_NOREORDER | ELF::EF_MIPS_ARCH_32R2; -} - -const MCSymbol *MipsELFObjectWriter::ExplicitRelSym(const MCAssembler &Asm, - const MCValue &Target, - const MCFragment &F, - const MCFixup &Fixup, - bool IsPCRel) const { - assert(Target.getSymA() && "SymA cannot be 0."); - const MCSymbol &Sym = Target.getSymA()->getSymbol(); - - if (Sym.getSection().getKind().isMergeableCString() || - Sym.getSection().getKind().isMergeableConst()) - return &Sym; - - return NULL; -} - -unsigned MipsELFObjectWriter::GetRelocType(const MCValue &Target, - const MCFixup &Fixup, - bool IsPCRel, - bool IsRelocWithSymbol, - int64_t Addend) const { - // determine the type of the relocation - unsigned Type = (unsigned)ELF::R_MIPS_NONE; - unsigned Kind = (unsigned)Fixup.getKind(); - - switch (Kind) { - default: - llvm_unreachable("invalid fixup kind!"); - case FK_Data_4: - Type = ELF::R_MIPS_32; - break; - case FK_GPRel_4: - Type = ELF::R_MIPS_GPREL32; - break; - case Mips::fixup_Mips_GPREL16: - Type = ELF::R_MIPS_GPREL16; - break; - case Mips::fixup_Mips_26: - Type = ELF::R_MIPS_26; - break; - case Mips::fixup_Mips_CALL16: - Type = ELF::R_MIPS_CALL16; - break; - case Mips::fixup_Mips_GOT_Global: - case Mips::fixup_Mips_GOT_Local: - Type = ELF::R_MIPS_GOT16; - break; - case Mips::fixup_Mips_HI16: - Type = ELF::R_MIPS_HI16; - break; - case Mips::fixup_Mips_LO16: - Type = ELF::R_MIPS_LO16; - break; - case Mips::fixup_Mips_TLSGD: - Type = ELF::R_MIPS_TLS_GD; - break; - case Mips::fixup_Mips_GOTTPREL: - Type = ELF::R_MIPS_TLS_GOTTPREL; - break; - case Mips::fixup_Mips_TPREL_HI: - Type = ELF::R_MIPS_TLS_TPREL_HI16; - break; - case Mips::fixup_Mips_TPREL_LO: - Type = ELF::R_MIPS_TLS_TPREL_LO16; - break; - case Mips::fixup_Mips_TLSLDM: - Type = ELF::R_MIPS_TLS_LDM; - break; - case Mips::fixup_Mips_DTPREL_HI: - Type = ELF::R_MIPS_TLS_DTPREL_HI16; - break; - case Mips::fixup_Mips_DTPREL_LO: - Type = ELF::R_MIPS_TLS_DTPREL_LO16; - break; - case Mips::fixup_Mips_Branch_PCRel: - case Mips::fixup_Mips_PC16: - Type = ELF::R_MIPS_PC16; - break; - } - - return Type; -} Modified: llvm/trunk/lib/MC/ELFObjectWriter.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/ELFObjectWriter.h?rev=147133&r1=147132&r2=147133&view=diff ============================================================================== --- llvm/trunk/lib/MC/ELFObjectWriter.h (original) +++ llvm/trunk/lib/MC/ELFObjectWriter.h Wed Dec 21 21:03:17 2011 @@ -354,29 +354,6 @@ bool IsPCRel, bool IsRelocWithSymbol, int64_t Addend) const; }; - - //===- MipsELFObjectWriter -------------------------------------------===// - - class MipsELFObjectWriter : public ELFObjectWriter { - public: - MipsELFObjectWriter(MCELFObjectTargetWriter *MOTW, - raw_ostream &_OS, - bool IsLittleEndian); - - virtual ~MipsELFObjectWriter(); - virtual unsigned getEFlags() const; - - protected: - virtual const MCSymbol *ExplicitRelSym(const MCAssembler &Asm, - const MCValue &Target, - const MCFragment &F, - const MCFixup &Fixup, - bool IsPCRel) const; - - virtual unsigned GetRelocType(const MCValue &Target, const MCFixup &Fixup, - bool IsPCRel, bool IsRelocWithSymbol, - int64_t Addend) const; - }; } #endif Modified: llvm/trunk/lib/Target/Mips/MCTargetDesc/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MCTargetDesc/CMakeLists.txt?rev=147133&r1=147132&r2=147133&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/MCTargetDesc/CMakeLists.txt (original) +++ llvm/trunk/lib/Target/Mips/MCTargetDesc/CMakeLists.txt Wed Dec 21 21:03:17 2011 @@ -3,6 +3,7 @@ MipsMCAsmInfo.cpp MipsMCCodeEmitter.cpp MipsMCTargetDesc.cpp + MipsELFObjectWriter.cpp ) add_dependencies(LLVMMipsDesc MipsCommonTableGen) Modified: llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsAsmBackend.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsAsmBackend.cpp?rev=147133&r1=147132&r2=147133&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsAsmBackend.cpp (original) +++ llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsAsmBackend.cpp Wed Dec 21 21:03:17 2011 @@ -69,15 +69,6 @@ } namespace { - -class MipsELFObjectWriter : public MCELFObjectTargetWriter { -public: - MipsELFObjectWriter(bool is64Bit, uint8_t OSABI, uint16_t EMachine, - bool HasRelocationAddend) - : MCELFObjectTargetWriter(is64Bit, OSABI, EMachine, - HasRelocationAddend) {} -}; - class MipsAsmBackend : public MCAsmBackend { public: MipsAsmBackend(const Target &T) : MCAsmBackend() {} @@ -206,12 +197,7 @@ : MipsAsmBackend(T), OSABI(_OSABI) {} MCObjectWriter *createObjectWriter(raw_ostream &OS) const { - return createELFObjectWriter(createELFObjectTargetWriter(), - OS, /*IsLittleEndian*/ false); - } - - MCELFObjectTargetWriter *createELFObjectTargetWriter() const { - return new MipsELFObjectWriter(false, OSABI, ELF::EM_MIPS, false); + return createMipsELFObjectWriter(OS, /*IsLittleEndian*/ false, OSABI); } }; @@ -223,12 +209,7 @@ : MipsAsmBackend(T), OSABI(_OSABI) {} MCObjectWriter *createObjectWriter(raw_ostream &OS) const { - return createELFObjectWriter(createELFObjectTargetWriter(), - OS, /*IsLittleEndian*/ true); - } - - MCELFObjectTargetWriter *createELFObjectTargetWriter() const { - return new MipsELFObjectWriter(false, OSABI, ELF::EM_MIPS, false); + return createMipsELFObjectWriter(OS, /*IsLittleEndian*/ true, OSABI); } }; } // namespace Added: llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsELFObjectWriter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsELFObjectWriter.cpp?rev=147133&view=auto ============================================================================== --- llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsELFObjectWriter.cpp (added) +++ llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsELFObjectWriter.cpp Wed Dec 21 21:03:17 2011 @@ -0,0 +1,137 @@ +//===-- MipsELFObjectWriter.cpp - Mips ELF Writer ---------------------------===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// + +#include "MCTargetDesc/MipsFixupKinds.h" +#include "MCTargetDesc/MipsMCTargetDesc.h" +#include "llvm/MC/MCELFObjectWriter.h" +#include "llvm/MC/MCExpr.h" +#include "llvm/MC/MCSection.h" +#include "llvm/MC/MCValue.h" +#include "llvm/Support/ErrorHandling.h" + +using namespace llvm; + +namespace { + class MipsELFObjectWriter : public MCELFObjectTargetWriter { + public: + MipsELFObjectWriter(uint8_t OSABI); + + virtual ~MipsELFObjectWriter(); + + virtual unsigned GetRelocType(const MCValue &Target, const MCFixup &Fixup, + bool IsPCRel, bool IsRelocWithSymbol, + int64_t Addend) const; + virtual unsigned getEFlags() const; + virtual const MCSymbol *ExplicitRelSym(const MCAssembler &Asm, + const MCValue &Target, + const MCFragment &F, + const MCFixup &Fixup, + bool IsPCRel) const; + }; +} + +MipsELFObjectWriter::MipsELFObjectWriter(uint8_t OSABI) + : MCELFObjectTargetWriter(/*Is64Bit*/ false, OSABI, ELF::EM_MIPS, + /*HasRelocationAddend*/ false) {} + +MipsELFObjectWriter::~MipsELFObjectWriter() {} + +// FIXME: get the real EABI Version from the Triple. +unsigned MipsELFObjectWriter::getEFlags() const { + return ELF::EF_MIPS_NOREORDER | ELF::EF_MIPS_ARCH_32R2; +} + +const MCSymbol *MipsELFObjectWriter::ExplicitRelSym(const MCAssembler &Asm, + const MCValue &Target, + const MCFragment &F, + const MCFixup &Fixup, + bool IsPCRel) const { + assert(Target.getSymA() && "SymA cannot be 0."); + const MCSymbol &Sym = Target.getSymA()->getSymbol(); + + if (Sym.getSection().getKind().isMergeableCString() || + Sym.getSection().getKind().isMergeableConst()) + return &Sym; + + return NULL; +} + +unsigned MipsELFObjectWriter::GetRelocType(const MCValue &Target, + const MCFixup &Fixup, + bool IsPCRel, + bool IsRelocWithSymbol, + int64_t Addend) const { + // determine the type of the relocation + unsigned Type = (unsigned)ELF::R_MIPS_NONE; + unsigned Kind = (unsigned)Fixup.getKind(); + + switch (Kind) { + default: + llvm_unreachable("invalid fixup kind!"); + case FK_Data_4: + Type = ELF::R_MIPS_32; + break; + case FK_GPRel_4: + Type = ELF::R_MIPS_GPREL32; + break; + case Mips::fixup_Mips_GPREL16: + Type = ELF::R_MIPS_GPREL16; + break; + case Mips::fixup_Mips_26: + Type = ELF::R_MIPS_26; + break; + case Mips::fixup_Mips_CALL16: + Type = ELF::R_MIPS_CALL16; + break; + case Mips::fixup_Mips_GOT_Global: + case Mips::fixup_Mips_GOT_Local: + Type = ELF::R_MIPS_GOT16; + break; + case Mips::fixup_Mips_HI16: + Type = ELF::R_MIPS_HI16; + break; + case Mips::fixup_Mips_LO16: + Type = ELF::R_MIPS_LO16; + break; + case Mips::fixup_Mips_TLSGD: + Type = ELF::R_MIPS_TLS_GD; + break; + case Mips::fixup_Mips_GOTTPREL: + Type = ELF::R_MIPS_TLS_GOTTPREL; + break; + case Mips::fixup_Mips_TPREL_HI: + Type = ELF::R_MIPS_TLS_TPREL_HI16; + break; + case Mips::fixup_Mips_TPREL_LO: + Type = ELF::R_MIPS_TLS_TPREL_LO16; + break; + case Mips::fixup_Mips_TLSLDM: + Type = ELF::R_MIPS_TLS_LDM; + break; + case Mips::fixup_Mips_DTPREL_HI: + Type = ELF::R_MIPS_TLS_DTPREL_HI16; + break; + case Mips::fixup_Mips_DTPREL_LO: + Type = ELF::R_MIPS_TLS_DTPREL_LO16; + break; + case Mips::fixup_Mips_Branch_PCRel: + case Mips::fixup_Mips_PC16: + Type = ELF::R_MIPS_PC16; + break; + } + + return Type; +} + +MCObjectWriter *llvm::createMipsELFObjectWriter(raw_ostream &OS, + bool IsLittleEndian, + uint8_t OSABI) { + MCELFObjectTargetWriter *MOTW = new MipsELFObjectWriter(OSABI); + return createELFObjectWriter(MOTW, OS, IsLittleEndian); +} Modified: llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.h?rev=147133&r1=147132&r2=147133&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.h (original) +++ llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.h Wed Dec 21 21:03:17 2011 @@ -14,6 +14,8 @@ #ifndef MIPSMCTARGETDESC_H #define MIPSMCTARGETDESC_H +#include "llvm/Support/DataTypes.h" + namespace llvm { class MCAsmBackend; class MCCodeEmitter; @@ -36,6 +38,9 @@ MCAsmBackend *createMipsAsmBackend(const Target &T, StringRef TT); +MCObjectWriter *createMipsELFObjectWriter(raw_ostream &OS, + bool IsLittleEndian, + uint8_t OSABI); } // End llvm namespace // Defines symbolic names for Mips registers. This defines a mapping from From eli.friedman at gmail.com Wed Dec 21 21:15:35 2011 From: eli.friedman at gmail.com (Eli Friedman) Date: Thu, 22 Dec 2011 03:15:35 -0000 Subject: [llvm-commits] [llvm] r147134 - /llvm/trunk/lib/Support/APInt.cpp Message-ID: <20111222031535.551052A6C12C@llvm.org> Author: efriedma Date: Wed Dec 21 21:15:35 2011 New Revision: 147134 URL: http://llvm.org/viewvc/llvm-project?rev=147134&view=rev Log: Fix APInt::rotl and APInt::rotr so that they work correctly. Found while writing some code that tried to use them. Modified: llvm/trunk/lib/Support/APInt.cpp Modified: llvm/trunk/lib/Support/APInt.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Support/APInt.cpp?rev=147134&r1=147133&r2=147134&view=diff ============================================================================== --- llvm/trunk/lib/Support/APInt.cpp (original) +++ llvm/trunk/lib/Support/APInt.cpp Wed Dec 21 21:15:35 2011 @@ -1338,14 +1338,10 @@ } APInt APInt::rotl(unsigned rotateAmt) const { + rotateAmt %= BitWidth; if (rotateAmt == 0) return *this; - // Don't get too fancy, just use existing shift/or facilities - APInt hi(*this); - APInt lo(*this); - hi.shl(rotateAmt); - lo.lshr(BitWidth - rotateAmt); - return hi | lo; + return shl(rotateAmt) | lshr(BitWidth - rotateAmt); } APInt APInt::rotr(const APInt &rotateAmt) const { @@ -1353,14 +1349,10 @@ } APInt APInt::rotr(unsigned rotateAmt) const { + rotateAmt %= BitWidth; if (rotateAmt == 0) return *this; - // Don't get too fancy, just use existing shift/or facilities - APInt hi(*this); - APInt lo(*this); - lo.lshr(rotateAmt); - hi.shl(BitWidth - rotateAmt); - return hi | lo; + return lshr(rotateAmt) | shl(BitWidth - rotateAmt); } // Square Root - this method computes and returns the square root of "this". From rafael.espindola at gmail.com Wed Dec 21 21:24:43 2011 From: rafael.espindola at gmail.com (Rafael Espindola) Date: Thu, 22 Dec 2011 03:24:43 -0000 Subject: [llvm-commits] [llvm] r147135 - in /llvm/trunk/lib/MC: ELFObjectWriter.cpp ELFObjectWriter.h Message-ID: <20111222032443.F20062A6C12C@llvm.org> Author: rafael Date: Wed Dec 21 21:24:43 2011 New Revision: 147135 URL: http://llvm.org/viewvc/llvm-project?rev=147135&view=rev Log: Misc cleanups. Modified: llvm/trunk/lib/MC/ELFObjectWriter.cpp llvm/trunk/lib/MC/ELFObjectWriter.h Modified: llvm/trunk/lib/MC/ELFObjectWriter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/ELFObjectWriter.cpp?rev=147135&r1=147134&r2=147135&view=diff ============================================================================== --- llvm/trunk/lib/MC/ELFObjectWriter.cpp (original) +++ llvm/trunk/lib/MC/ELFObjectWriter.cpp Wed Dec 21 21:24:43 2011 @@ -1253,24 +1253,5 @@ MCObjectWriter *llvm::createELFObjectWriter(MCELFObjectTargetWriter *MOTW, raw_ostream &OS, bool IsLittleEndian) { - switch (MOTW->getEMachine()) { - case ELF::EM_386: - case ELF::EM_X86_64: - case ELF::EM_ARM: - case ELF::EM_PPC: - case ELF::EM_PPC64: - case ELF::EM_MBLAZE: - case ELF::EM_MIPS: - return new ELFObjectWriter(MOTW, OS, IsLittleEndian); break; - default: llvm_unreachable("Unsupported architecture"); break; - } -} - -unsigned ELFObjectWriter::GetRelocType(const MCValue &Target, - const MCFixup &Fixup, - bool IsPCRel, - bool IsRelocWithSymbol, - int64_t Addend) const { - return TargetObjectWriter->GetRelocType(Target, Fixup, IsPCRel, - IsRelocWithSymbol, Addend); + return new ELFObjectWriter(MOTW, OS, IsLittleEndian); } Modified: llvm/trunk/lib/MC/ELFObjectWriter.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/ELFObjectWriter.h?rev=147135&r1=147134&r2=147135&view=diff ============================================================================== --- llvm/trunk/lib/MC/ELFObjectWriter.h (original) +++ llvm/trunk/lib/MC/ELFObjectWriter.h Wed Dec 21 21:24:43 2011 @@ -140,18 +140,18 @@ unsigned ShstrtabIndex; - virtual const MCSymbol *SymbolToReloc(const MCAssembler &Asm, - const MCValue &Target, - const MCFragment &F, - const MCFixup &Fixup, - bool IsPCRel) const; - - // For arch-specific emission of explicit reloc symbol - virtual const MCSymbol *ExplicitRelSym(const MCAssembler &Asm, - const MCValue &Target, - const MCFragment &F, - const MCFixup &Fixup, - bool IsPCRel) const { + const MCSymbol *SymbolToReloc(const MCAssembler &Asm, + const MCValue &Target, + const MCFragment &F, + const MCFixup &Fixup, + bool IsPCRel) const; + + // TargetObjectWriter wrappers. + const MCSymbol *ExplicitRelSym(const MCAssembler &Asm, + const MCValue &Target, + const MCFragment &F, + const MCFixup &Fixup, + bool IsPCRel) const { return TargetObjectWriter->ExplicitRelSym(Asm, Target, F, Fixup, IsPCRel); } @@ -159,6 +159,16 @@ bool hasRelocationAddend() const { return TargetObjectWriter->hasRelocationAddend(); } + unsigned getEFlags() const { + return TargetObjectWriter->getEFlags(); + } + unsigned GetRelocType(const MCValue &Target, const MCFixup &Fixup, + bool IsPCRel, bool IsRelocWithSymbol, + int64_t Addend) const { + return TargetObjectWriter->GetRelocType(Target, Fixup, IsPCRel, + IsRelocWithSymbol, Addend); + } + public: ELFObjectWriter(MCELFObjectTargetWriter *MOTW, @@ -240,30 +250,26 @@ F.getContents() += StringRef(buf, 8); } - virtual void WriteHeader(uint64_t SectionDataSize, - unsigned NumberOfSections); + void WriteHeader(uint64_t SectionDataSize, + unsigned NumberOfSections); - virtual unsigned getEFlags() const { - return TargetObjectWriter->getEFlags(); - } - - virtual void WriteSymbolEntry(MCDataFragment *SymtabF, - MCDataFragment *ShndxF, - uint64_t name, uint8_t info, - uint64_t value, uint64_t size, - uint8_t other, uint32_t shndx, - bool Reserved); + void WriteSymbolEntry(MCDataFragment *SymtabF, + MCDataFragment *ShndxF, + uint64_t name, uint8_t info, + uint64_t value, uint64_t size, + uint8_t other, uint32_t shndx, + bool Reserved); - virtual void WriteSymbol(MCDataFragment *SymtabF, MCDataFragment *ShndxF, + void WriteSymbol(MCDataFragment *SymtabF, MCDataFragment *ShndxF, ELFSymbolData &MSD, const MCAsmLayout &Layout); typedef DenseMap SectionIndexMapTy; - virtual void WriteSymbolTable(MCDataFragment *SymtabF, - MCDataFragment *ShndxF, - const MCAssembler &Asm, - const MCAsmLayout &Layout, - const SectionIndexMapTy &SectionIndexMap); + void WriteSymbolTable(MCDataFragment *SymtabF, + MCDataFragment *ShndxF, + const MCAssembler &Asm, + const MCAsmLayout &Layout, + const SectionIndexMapTy &SectionIndexMap); virtual void RecordRelocation(const MCAssembler &Asm, const MCAsmLayout &Layout, @@ -271,8 +277,8 @@ const MCFixup &Fixup, MCValue Target, uint64_t &FixedValue); - virtual uint64_t getSymbolIndexInSymbolTable(const MCAssembler &Asm, - const MCSymbol *S); + uint64_t getSymbolIndexInSymbolTable(const MCAssembler &Asm, + const MCSymbol *S); // Map from a group section to the signature symbol typedef DenseMap GroupMapTy; @@ -288,14 +294,14 @@ /// \param StringTable [out] - The string table data. /// \param StringIndexMap [out] - Map from symbol names to offsets in the /// string table. - virtual void ComputeSymbolTable(MCAssembler &Asm, + void ComputeSymbolTable(MCAssembler &Asm, const SectionIndexMapTy &SectionIndexMap, - RevGroupMapTy RevGroupMap, - unsigned NumRegularSections); + RevGroupMapTy RevGroupMap, + unsigned NumRegularSections); - virtual void ComputeIndexMap(MCAssembler &Asm, - SectionIndexMapTy &SectionIndexMap, - const RelMapTy &RelMap); + void ComputeIndexMap(MCAssembler &Asm, + SectionIndexMapTy &SectionIndexMap, + const RelMapTy &RelMap); void CreateRelocationSections(MCAssembler &Asm, MCAsmLayout &Layout, RelMapTy &RelMap); @@ -303,17 +309,17 @@ void WriteRelocations(MCAssembler &Asm, MCAsmLayout &Layout, const RelMapTy &RelMap); - virtual void CreateMetadataSections(MCAssembler &Asm, MCAsmLayout &Layout, - SectionIndexMapTy &SectionIndexMap, - const RelMapTy &RelMap); + void CreateMetadataSections(MCAssembler &Asm, MCAsmLayout &Layout, + SectionIndexMapTy &SectionIndexMap, + const RelMapTy &RelMap); // Create the sections that show up in the symbol table. Currently // those are the .note.GNU-stack section and the group sections. - virtual void CreateIndexedSections(MCAssembler &Asm, MCAsmLayout &Layout, - GroupMapTy &GroupMap, - RevGroupMapTy &RevGroupMap, - SectionIndexMapTy &SectionIndexMap, - const RelMapTy &RelMap); + void CreateIndexedSections(MCAssembler &Asm, MCAsmLayout &Layout, + GroupMapTy &GroupMap, + RevGroupMapTy &RevGroupMap, + SectionIndexMapTy &SectionIndexMap, + const RelMapTy &RelMap); virtual void ExecutePostLayoutBinding(MCAssembler &Asm, const MCAsmLayout &Layout); @@ -326,14 +332,14 @@ void ComputeSectionOrder(MCAssembler &Asm, std::vector &Sections); - virtual void WriteSecHdrEntry(uint32_t Name, uint32_t Type, uint64_t Flags, + void WriteSecHdrEntry(uint32_t Name, uint32_t Type, uint64_t Flags, uint64_t Address, uint64_t Offset, uint64_t Size, uint32_t Link, uint32_t Info, uint64_t Alignment, uint64_t EntrySize); - virtual void WriteRelocationsFragment(const MCAssembler &Asm, - MCDataFragment *F, - const MCSectionData *SD); + void WriteRelocationsFragment(const MCAssembler &Asm, + MCDataFragment *F, + const MCSectionData *SD); virtual bool IsSymbolRefDifferenceFullyResolvedImpl(const MCAssembler &Asm, @@ -343,16 +349,11 @@ bool IsPCRel) const; virtual void WriteObject(MCAssembler &Asm, const MCAsmLayout &Layout); - virtual void WriteSection(MCAssembler &Asm, + void WriteSection(MCAssembler &Asm, const SectionIndexMapTy &SectionIndexMap, uint32_t GroupSymbolIndex, uint64_t Offset, uint64_t Size, uint64_t Alignment, const MCSectionELF &Section); - - protected: - virtual unsigned GetRelocType(const MCValue &Target, const MCFixup &Fixup, - bool IsPCRel, bool IsRelocWithSymbol, - int64_t Addend) const; }; } From rafael.espindola at gmail.com Wed Dec 21 21:38:00 2011 From: rafael.espindola at gmail.com (Rafael Espindola) Date: Thu, 22 Dec 2011 03:38:00 -0000 Subject: [llvm-commits] [llvm] r147136 - in /llvm/trunk/lib/MC: ELFObjectWriter.cpp ELFObjectWriter.h Message-ID: <20111222033800.AA4212A6C12C@llvm.org> Author: rafael Date: Wed Dec 21 21:38:00 2011 New Revision: 147136 URL: http://llvm.org/viewvc/llvm-project?rev=147136&view=rev Log: Kill the monstrosity that was ELFObjectWriter.h. Removed: llvm/trunk/lib/MC/ELFObjectWriter.h Modified: llvm/trunk/lib/MC/ELFObjectWriter.cpp Modified: llvm/trunk/lib/MC/ELFObjectWriter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/ELFObjectWriter.cpp?rev=147136&r1=147135&r2=147136&view=diff ============================================================================== --- llvm/trunk/lib/MC/ELFObjectWriter.cpp (original) +++ llvm/trunk/lib/MC/ELFObjectWriter.cpp Wed Dec 21 21:38:00 2011 @@ -11,13 +11,19 @@ // //===----------------------------------------------------------------------===// -#include "ELFObjectWriter.h" +#include "MCELF.h" +#include "llvm/ADT/OwningPtr.h" +#include "llvm/ADT/SmallPtrSet.h" +#include "llvm/ADT/SmallString.h" #include "llvm/ADT/STLExtras.h" #include "llvm/ADT/StringMap.h" #include "llvm/ADT/Twine.h" #include "llvm/MC/MCAsmBackend.h" #include "llvm/MC/MCAsmLayout.h" +#include "llvm/MC/MCAssembler.h" #include "llvm/MC/MCContext.h" +#include "llvm/MC/MCELFObjectWriter.h" +#include "llvm/MC/MCELFSymbolFlags.h" #include "llvm/MC/MCExpr.h" #include "llvm/MC/MCSectionELF.h" #include "llvm/MC/MCValue.h" @@ -33,6 +39,330 @@ #undef DEBUG_TYPE #define DEBUG_TYPE "reloc-info" +namespace { +class ELFObjectWriter : public MCObjectWriter { + protected: + + static bool isFixupKindPCRel(const MCAssembler &Asm, unsigned Kind); + static bool RelocNeedsGOT(MCSymbolRefExpr::VariantKind Variant); + static uint64_t SymbolValue(MCSymbolData &Data, const MCAsmLayout &Layout); + static bool isInSymtab(const MCAssembler &Asm, const MCSymbolData &Data, + bool Used, bool Renamed); + static bool isLocal(const MCSymbolData &Data, bool isSignature, + bool isUsedInReloc); + static bool IsELFMetaDataSection(const MCSectionData &SD); + static uint64_t DataSectionSize(const MCSectionData &SD); + static uint64_t GetSectionFileSize(const MCAsmLayout &Layout, + const MCSectionData &SD); + static uint64_t GetSectionAddressSize(const MCAsmLayout &Layout, + const MCSectionData &SD); + + void WriteDataSectionData(MCAssembler &Asm, + const MCAsmLayout &Layout, + const MCSectionELF &Section); + + /*static bool isFixupKindX86RIPRel(unsigned Kind) { + return Kind == X86::reloc_riprel_4byte || + Kind == X86::reloc_riprel_4byte_movq_load; + }*/ + + /// ELFSymbolData - Helper struct for containing some precomputed + /// information on symbols. + struct ELFSymbolData { + MCSymbolData *SymbolData; + uint64_t StringIndex; + uint32_t SectionIndex; + + // Support lexicographic sorting. + bool operator<(const ELFSymbolData &RHS) const { + if (MCELF::GetType(*SymbolData) == ELF::STT_FILE) + return true; + if (MCELF::GetType(*RHS.SymbolData) == ELF::STT_FILE) + return false; + return SymbolData->getSymbol().getName() < + RHS.SymbolData->getSymbol().getName(); + } + }; + + /// @name Relocation Data + /// @{ + + struct ELFRelocationEntry { + // Make these big enough for both 32-bit and 64-bit + uint64_t r_offset; + int Index; + unsigned Type; + const MCSymbol *Symbol; + uint64_t r_addend; + + ELFRelocationEntry() + : r_offset(0), Index(0), Type(0), Symbol(0), r_addend(0) {} + + ELFRelocationEntry(uint64_t RelocOffset, int Idx, + unsigned RelType, const MCSymbol *Sym, + uint64_t Addend) + : r_offset(RelocOffset), Index(Idx), Type(RelType), + Symbol(Sym), r_addend(Addend) {} + + // Support lexicographic sorting. + bool operator<(const ELFRelocationEntry &RE) const { + return RE.r_offset < r_offset; + } + }; + + /// The target specific ELF writer instance. + llvm::OwningPtr TargetObjectWriter; + + SmallPtrSet UsedInReloc; + SmallPtrSet WeakrefUsedInReloc; + DenseMap Renames; + + llvm::DenseMap > Relocations; + DenseMap SectionStringTableIndex; + + /// @} + /// @name Symbol Table Data + /// @{ + + SmallString<256> StringTable; + std::vector LocalSymbolData; + std::vector ExternalSymbolData; + std::vector UndefinedSymbolData; + + /// @} + + bool NeedsGOT; + + bool NeedsSymtabShndx; + + // This holds the symbol table index of the last local symbol. + unsigned LastLocalSymbolIndex; + // This holds the .strtab section index. + unsigned StringTableIndex; + // This holds the .symtab section index. + unsigned SymbolTableIndex; + + unsigned ShstrtabIndex; + + + const MCSymbol *SymbolToReloc(const MCAssembler &Asm, + const MCValue &Target, + const MCFragment &F, + const MCFixup &Fixup, + bool IsPCRel) const; + + // TargetObjectWriter wrappers. + const MCSymbol *ExplicitRelSym(const MCAssembler &Asm, + const MCValue &Target, + const MCFragment &F, + const MCFixup &Fixup, + bool IsPCRel) const { + return TargetObjectWriter->ExplicitRelSym(Asm, Target, F, Fixup, IsPCRel); + } + + bool is64Bit() const { return TargetObjectWriter->is64Bit(); } + bool hasRelocationAddend() const { + return TargetObjectWriter->hasRelocationAddend(); + } + unsigned getEFlags() const { + return TargetObjectWriter->getEFlags(); + } + unsigned GetRelocType(const MCValue &Target, const MCFixup &Fixup, + bool IsPCRel, bool IsRelocWithSymbol, + int64_t Addend) const { + return TargetObjectWriter->GetRelocType(Target, Fixup, IsPCRel, + IsRelocWithSymbol, Addend); + } + + + public: + ELFObjectWriter(MCELFObjectTargetWriter *MOTW, + raw_ostream &_OS, bool IsLittleEndian) + : MCObjectWriter(_OS, IsLittleEndian), + TargetObjectWriter(MOTW), + NeedsGOT(false), NeedsSymtabShndx(false){ + } + + virtual ~ELFObjectWriter(); + + void WriteWord(uint64_t W) { + if (is64Bit()) + Write64(W); + else + Write32(W); + } + + void StringLE16(char *buf, uint16_t Value) { + buf[0] = char(Value >> 0); + buf[1] = char(Value >> 8); + } + + void StringLE32(char *buf, uint32_t Value) { + StringLE16(buf, uint16_t(Value >> 0)); + StringLE16(buf + 2, uint16_t(Value >> 16)); + } + + void StringLE64(char *buf, uint64_t Value) { + StringLE32(buf, uint32_t(Value >> 0)); + StringLE32(buf + 4, uint32_t(Value >> 32)); + } + + void StringBE16(char *buf ,uint16_t Value) { + buf[0] = char(Value >> 8); + buf[1] = char(Value >> 0); + } + + void StringBE32(char *buf, uint32_t Value) { + StringBE16(buf, uint16_t(Value >> 16)); + StringBE16(buf + 2, uint16_t(Value >> 0)); + } + + void StringBE64(char *buf, uint64_t Value) { + StringBE32(buf, uint32_t(Value >> 32)); + StringBE32(buf + 4, uint32_t(Value >> 0)); + } + + void String8(MCDataFragment &F, uint8_t Value) { + char buf[1]; + buf[0] = Value; + F.getContents() += StringRef(buf, 1); + } + + void String16(MCDataFragment &F, uint16_t Value) { + char buf[2]; + if (isLittleEndian()) + StringLE16(buf, Value); + else + StringBE16(buf, Value); + F.getContents() += StringRef(buf, 2); + } + + void String32(MCDataFragment &F, uint32_t Value) { + char buf[4]; + if (isLittleEndian()) + StringLE32(buf, Value); + else + StringBE32(buf, Value); + F.getContents() += StringRef(buf, 4); + } + + void String64(MCDataFragment &F, uint64_t Value) { + char buf[8]; + if (isLittleEndian()) + StringLE64(buf, Value); + else + StringBE64(buf, Value); + F.getContents() += StringRef(buf, 8); + } + + void WriteHeader(uint64_t SectionDataSize, + unsigned NumberOfSections); + + void WriteSymbolEntry(MCDataFragment *SymtabF, + MCDataFragment *ShndxF, + uint64_t name, uint8_t info, + uint64_t value, uint64_t size, + uint8_t other, uint32_t shndx, + bool Reserved); + + void WriteSymbol(MCDataFragment *SymtabF, MCDataFragment *ShndxF, + ELFSymbolData &MSD, + const MCAsmLayout &Layout); + + typedef DenseMap SectionIndexMapTy; + void WriteSymbolTable(MCDataFragment *SymtabF, + MCDataFragment *ShndxF, + const MCAssembler &Asm, + const MCAsmLayout &Layout, + const SectionIndexMapTy &SectionIndexMap); + + virtual void RecordRelocation(const MCAssembler &Asm, + const MCAsmLayout &Layout, + const MCFragment *Fragment, + const MCFixup &Fixup, + MCValue Target, uint64_t &FixedValue); + + uint64_t getSymbolIndexInSymbolTable(const MCAssembler &Asm, + const MCSymbol *S); + + // Map from a group section to the signature symbol + typedef DenseMap GroupMapTy; + // Map from a signature symbol to the group section + typedef DenseMap RevGroupMapTy; + // Map from a section to the section with the relocations + typedef DenseMap RelMapTy; + // Map from a section to its offset + typedef DenseMap SectionOffsetMapTy; + + /// ComputeSymbolTable - Compute the symbol table data + /// + /// \param StringTable [out] - The string table data. + /// \param StringIndexMap [out] - Map from symbol names to offsets in the + /// string table. + void ComputeSymbolTable(MCAssembler &Asm, + const SectionIndexMapTy &SectionIndexMap, + RevGroupMapTy RevGroupMap, + unsigned NumRegularSections); + + void ComputeIndexMap(MCAssembler &Asm, + SectionIndexMapTy &SectionIndexMap, + const RelMapTy &RelMap); + + void CreateRelocationSections(MCAssembler &Asm, MCAsmLayout &Layout, + RelMapTy &RelMap); + + void WriteRelocations(MCAssembler &Asm, MCAsmLayout &Layout, + const RelMapTy &RelMap); + + void CreateMetadataSections(MCAssembler &Asm, MCAsmLayout &Layout, + SectionIndexMapTy &SectionIndexMap, + const RelMapTy &RelMap); + + // Create the sections that show up in the symbol table. Currently + // those are the .note.GNU-stack section and the group sections. + void CreateIndexedSections(MCAssembler &Asm, MCAsmLayout &Layout, + GroupMapTy &GroupMap, + RevGroupMapTy &RevGroupMap, + SectionIndexMapTy &SectionIndexMap, + const RelMapTy &RelMap); + + virtual void ExecutePostLayoutBinding(MCAssembler &Asm, + const MCAsmLayout &Layout); + + void WriteSectionHeader(MCAssembler &Asm, const GroupMapTy &GroupMap, + const MCAsmLayout &Layout, + const SectionIndexMapTy &SectionIndexMap, + const SectionOffsetMapTy &SectionOffsetMap); + + void ComputeSectionOrder(MCAssembler &Asm, + std::vector &Sections); + + void WriteSecHdrEntry(uint32_t Name, uint32_t Type, uint64_t Flags, + uint64_t Address, uint64_t Offset, + uint64_t Size, uint32_t Link, uint32_t Info, + uint64_t Alignment, uint64_t EntrySize); + + void WriteRelocationsFragment(const MCAssembler &Asm, + MCDataFragment *F, + const MCSectionData *SD); + + virtual bool + IsSymbolRefDifferenceFullyResolvedImpl(const MCAssembler &Asm, + const MCSymbolData &DataA, + const MCFragment &FB, + bool InSet, + bool IsPCRel) const; + + virtual void WriteObject(MCAssembler &Asm, const MCAsmLayout &Layout); + void WriteSection(MCAssembler &Asm, + const SectionIndexMapTy &SectionIndexMap, + uint32_t GroupSymbolIndex, + uint64_t Offset, uint64_t Size, uint64_t Alignment, + const MCSectionELF &Section); + }; +} + bool ELFObjectWriter::isFixupKindPCRel(const MCAssembler &Asm, unsigned Kind) { const MCFixupKindInfo &FKI = Asm.getBackend().getFixupKindInfo((MCFixupKind) Kind); Removed: llvm/trunk/lib/MC/ELFObjectWriter.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/ELFObjectWriter.h?rev=147135&view=auto ============================================================================== --- llvm/trunk/lib/MC/ELFObjectWriter.h (original) +++ llvm/trunk/lib/MC/ELFObjectWriter.h (removed) @@ -1,360 +0,0 @@ -//===- lib/MC/ELFObjectWriter.h - ELF File Writer -------------------------===// -// -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. -// -//===----------------------------------------------------------------------===// -// -// This file implements ELF object file writer information. -// -//===----------------------------------------------------------------------===// - -#ifndef LLVM_MC_ELFOBJECTWRITER_H -#define LLVM_MC_ELFOBJECTWRITER_H - -#include "MCELF.h" -#include "llvm/ADT/OwningPtr.h" -#include "llvm/ADT/SmallPtrSet.h" -#include "llvm/ADT/SmallString.h" -#include "llvm/ADT/STLExtras.h" -#include "llvm/MC/MCAssembler.h" -#include "llvm/MC/MCELFObjectWriter.h" -#include "llvm/MC/MCELFSymbolFlags.h" -#include "llvm/MC/MCObjectWriter.h" -#include "llvm/MC/MCExpr.h" -#include "llvm/MC/MCSymbol.h" - -#include - -namespace llvm { - -class MCSection; -class MCDataFragment; -class MCSectionELF; - -class ELFObjectWriter : public MCObjectWriter { - protected: - - static bool isFixupKindPCRel(const MCAssembler &Asm, unsigned Kind); - static bool RelocNeedsGOT(MCSymbolRefExpr::VariantKind Variant); - static uint64_t SymbolValue(MCSymbolData &Data, const MCAsmLayout &Layout); - static bool isInSymtab(const MCAssembler &Asm, const MCSymbolData &Data, - bool Used, bool Renamed); - static bool isLocal(const MCSymbolData &Data, bool isSignature, - bool isUsedInReloc); - static bool IsELFMetaDataSection(const MCSectionData &SD); - static uint64_t DataSectionSize(const MCSectionData &SD); - static uint64_t GetSectionFileSize(const MCAsmLayout &Layout, - const MCSectionData &SD); - static uint64_t GetSectionAddressSize(const MCAsmLayout &Layout, - const MCSectionData &SD); - - void WriteDataSectionData(MCAssembler &Asm, - const MCAsmLayout &Layout, - const MCSectionELF &Section); - - /*static bool isFixupKindX86RIPRel(unsigned Kind) { - return Kind == X86::reloc_riprel_4byte || - Kind == X86::reloc_riprel_4byte_movq_load; - }*/ - - /// ELFSymbolData - Helper struct for containing some precomputed - /// information on symbols. - struct ELFSymbolData { - MCSymbolData *SymbolData; - uint64_t StringIndex; - uint32_t SectionIndex; - - // Support lexicographic sorting. - bool operator<(const ELFSymbolData &RHS) const { - if (MCELF::GetType(*SymbolData) == ELF::STT_FILE) - return true; - if (MCELF::GetType(*RHS.SymbolData) == ELF::STT_FILE) - return false; - return SymbolData->getSymbol().getName() < - RHS.SymbolData->getSymbol().getName(); - } - }; - - /// @name Relocation Data - /// @{ - - struct ELFRelocationEntry { - // Make these big enough for both 32-bit and 64-bit - uint64_t r_offset; - int Index; - unsigned Type; - const MCSymbol *Symbol; - uint64_t r_addend; - - ELFRelocationEntry() - : r_offset(0), Index(0), Type(0), Symbol(0), r_addend(0) {} - - ELFRelocationEntry(uint64_t RelocOffset, int Idx, - unsigned RelType, const MCSymbol *Sym, - uint64_t Addend) - : r_offset(RelocOffset), Index(Idx), Type(RelType), - Symbol(Sym), r_addend(Addend) {} - - // Support lexicographic sorting. - bool operator<(const ELFRelocationEntry &RE) const { - return RE.r_offset < r_offset; - } - }; - - /// The target specific ELF writer instance. - llvm::OwningPtr TargetObjectWriter; - - SmallPtrSet UsedInReloc; - SmallPtrSet WeakrefUsedInReloc; - DenseMap Renames; - - llvm::DenseMap > Relocations; - DenseMap SectionStringTableIndex; - - /// @} - /// @name Symbol Table Data - /// @{ - - SmallString<256> StringTable; - std::vector LocalSymbolData; - std::vector ExternalSymbolData; - std::vector UndefinedSymbolData; - - /// @} - - bool NeedsGOT; - - bool NeedsSymtabShndx; - - // This holds the symbol table index of the last local symbol. - unsigned LastLocalSymbolIndex; - // This holds the .strtab section index. - unsigned StringTableIndex; - // This holds the .symtab section index. - unsigned SymbolTableIndex; - - unsigned ShstrtabIndex; - - - const MCSymbol *SymbolToReloc(const MCAssembler &Asm, - const MCValue &Target, - const MCFragment &F, - const MCFixup &Fixup, - bool IsPCRel) const; - - // TargetObjectWriter wrappers. - const MCSymbol *ExplicitRelSym(const MCAssembler &Asm, - const MCValue &Target, - const MCFragment &F, - const MCFixup &Fixup, - bool IsPCRel) const { - return TargetObjectWriter->ExplicitRelSym(Asm, Target, F, Fixup, IsPCRel); - } - - bool is64Bit() const { return TargetObjectWriter->is64Bit(); } - bool hasRelocationAddend() const { - return TargetObjectWriter->hasRelocationAddend(); - } - unsigned getEFlags() const { - return TargetObjectWriter->getEFlags(); - } - unsigned GetRelocType(const MCValue &Target, const MCFixup &Fixup, - bool IsPCRel, bool IsRelocWithSymbol, - int64_t Addend) const { - return TargetObjectWriter->GetRelocType(Target, Fixup, IsPCRel, - IsRelocWithSymbol, Addend); - } - - - public: - ELFObjectWriter(MCELFObjectTargetWriter *MOTW, - raw_ostream &_OS, bool IsLittleEndian) - : MCObjectWriter(_OS, IsLittleEndian), - TargetObjectWriter(MOTW), - NeedsGOT(false), NeedsSymtabShndx(false){ - } - - virtual ~ELFObjectWriter(); - - void WriteWord(uint64_t W) { - if (is64Bit()) - Write64(W); - else - Write32(W); - } - - void StringLE16(char *buf, uint16_t Value) { - buf[0] = char(Value >> 0); - buf[1] = char(Value >> 8); - } - - void StringLE32(char *buf, uint32_t Value) { - StringLE16(buf, uint16_t(Value >> 0)); - StringLE16(buf + 2, uint16_t(Value >> 16)); - } - - void StringLE64(char *buf, uint64_t Value) { - StringLE32(buf, uint32_t(Value >> 0)); - StringLE32(buf + 4, uint32_t(Value >> 32)); - } - - void StringBE16(char *buf ,uint16_t Value) { - buf[0] = char(Value >> 8); - buf[1] = char(Value >> 0); - } - - void StringBE32(char *buf, uint32_t Value) { - StringBE16(buf, uint16_t(Value >> 16)); - StringBE16(buf + 2, uint16_t(Value >> 0)); - } - - void StringBE64(char *buf, uint64_t Value) { - StringBE32(buf, uint32_t(Value >> 32)); - StringBE32(buf + 4, uint32_t(Value >> 0)); - } - - void String8(MCDataFragment &F, uint8_t Value) { - char buf[1]; - buf[0] = Value; - F.getContents() += StringRef(buf, 1); - } - - void String16(MCDataFragment &F, uint16_t Value) { - char buf[2]; - if (isLittleEndian()) - StringLE16(buf, Value); - else - StringBE16(buf, Value); - F.getContents() += StringRef(buf, 2); - } - - void String32(MCDataFragment &F, uint32_t Value) { - char buf[4]; - if (isLittleEndian()) - StringLE32(buf, Value); - else - StringBE32(buf, Value); - F.getContents() += StringRef(buf, 4); - } - - void String64(MCDataFragment &F, uint64_t Value) { - char buf[8]; - if (isLittleEndian()) - StringLE64(buf, Value); - else - StringBE64(buf, Value); - F.getContents() += StringRef(buf, 8); - } - - void WriteHeader(uint64_t SectionDataSize, - unsigned NumberOfSections); - - void WriteSymbolEntry(MCDataFragment *SymtabF, - MCDataFragment *ShndxF, - uint64_t name, uint8_t info, - uint64_t value, uint64_t size, - uint8_t other, uint32_t shndx, - bool Reserved); - - void WriteSymbol(MCDataFragment *SymtabF, MCDataFragment *ShndxF, - ELFSymbolData &MSD, - const MCAsmLayout &Layout); - - typedef DenseMap SectionIndexMapTy; - void WriteSymbolTable(MCDataFragment *SymtabF, - MCDataFragment *ShndxF, - const MCAssembler &Asm, - const MCAsmLayout &Layout, - const SectionIndexMapTy &SectionIndexMap); - - virtual void RecordRelocation(const MCAssembler &Asm, - const MCAsmLayout &Layout, - const MCFragment *Fragment, - const MCFixup &Fixup, - MCValue Target, uint64_t &FixedValue); - - uint64_t getSymbolIndexInSymbolTable(const MCAssembler &Asm, - const MCSymbol *S); - - // Map from a group section to the signature symbol - typedef DenseMap GroupMapTy; - // Map from a signature symbol to the group section - typedef DenseMap RevGroupMapTy; - // Map from a section to the section with the relocations - typedef DenseMap RelMapTy; - // Map from a section to its offset - typedef DenseMap SectionOffsetMapTy; - - /// ComputeSymbolTable - Compute the symbol table data - /// - /// \param StringTable [out] - The string table data. - /// \param StringIndexMap [out] - Map from symbol names to offsets in the - /// string table. - void ComputeSymbolTable(MCAssembler &Asm, - const SectionIndexMapTy &SectionIndexMap, - RevGroupMapTy RevGroupMap, - unsigned NumRegularSections); - - void ComputeIndexMap(MCAssembler &Asm, - SectionIndexMapTy &SectionIndexMap, - const RelMapTy &RelMap); - - void CreateRelocationSections(MCAssembler &Asm, MCAsmLayout &Layout, - RelMapTy &RelMap); - - void WriteRelocations(MCAssembler &Asm, MCAsmLayout &Layout, - const RelMapTy &RelMap); - - void CreateMetadataSections(MCAssembler &Asm, MCAsmLayout &Layout, - SectionIndexMapTy &SectionIndexMap, - const RelMapTy &RelMap); - - // Create the sections that show up in the symbol table. Currently - // those are the .note.GNU-stack section and the group sections. - void CreateIndexedSections(MCAssembler &Asm, MCAsmLayout &Layout, - GroupMapTy &GroupMap, - RevGroupMapTy &RevGroupMap, - SectionIndexMapTy &SectionIndexMap, - const RelMapTy &RelMap); - - virtual void ExecutePostLayoutBinding(MCAssembler &Asm, - const MCAsmLayout &Layout); - - void WriteSectionHeader(MCAssembler &Asm, const GroupMapTy &GroupMap, - const MCAsmLayout &Layout, - const SectionIndexMapTy &SectionIndexMap, - const SectionOffsetMapTy &SectionOffsetMap); - - void ComputeSectionOrder(MCAssembler &Asm, - std::vector &Sections); - - void WriteSecHdrEntry(uint32_t Name, uint32_t Type, uint64_t Flags, - uint64_t Address, uint64_t Offset, - uint64_t Size, uint32_t Link, uint32_t Info, - uint64_t Alignment, uint64_t EntrySize); - - void WriteRelocationsFragment(const MCAssembler &Asm, - MCDataFragment *F, - const MCSectionData *SD); - - virtual bool - IsSymbolRefDifferenceFullyResolvedImpl(const MCAssembler &Asm, - const MCSymbolData &DataA, - const MCFragment &FB, - bool InSet, - bool IsPCRel) const; - - virtual void WriteObject(MCAssembler &Asm, const MCAsmLayout &Layout); - void WriteSection(MCAssembler &Asm, - const SectionIndexMapTy &SectionIndexMap, - uint32_t GroupSymbolIndex, - uint64_t Offset, uint64_t Size, uint64_t Alignment, - const MCSectionELF &Section); - }; -} - -#endif From rafael.espindola at gmail.com Wed Dec 21 22:58:14 2011 From: rafael.espindola at gmail.com (=?ISO-8859-1?Q?Rafael_=C1vila_de_Esp=EDndola?=) Date: Wed, 21 Dec 2011 23:58:14 -0500 Subject: [llvm-commits] [llvm] r146604 - in /llvm/trunk: lib/CodeGen/MachineSink.cpp test/CodeGen/ARM/2011-12-14-machine-sink.ll In-Reply-To: References: <20111214232038.E9C9D2A6C12C@llvm.org> <5FF21D31-13D7-4EAA-99FC-EFC1AFA0C8F7@apple.com> <618FAA67-0A0A-4D20-9E58-491632F2BA7C@apple.com> <91FF2423-D67D-4E80-985B-532E27DF3799@apple.com> Message-ID: <4EF2B8E6.7020202@gmail.com> On 21/12/11 02:57 AM, Anton Korobeynikov wrote: >> One alternative for you is to reproduce segfault in debugger and investigate what is being compiled. >> >> Other alternative is to narrow down the particular MI sink that is difference maker. You can do this by disabling this patch and adding a artificial threshold in Machine Sink pass to control how many instructions are sinked. One you know the critical MI sink, you can investigate how it impacts other passes, including register allocator, down the road. >> >> I am afraid, there is not any easy answer. > Previously one could use bugpoint to reduce such problems > automatically via splitting the code into two parts, compiling one > part with gcc and another - via llvm. > Though, I doubt this will work right now since cbe is broken now. That > said, you do not have any automatic reduction in such cases and should > do everything by hands. > Bugpoint can use a "safe llc", so it might be possible to use "llc -regalloc=basic" as the safe compiler, but I haven't used that recently. Cheers, Rafael From rdivacky at freebsd.org Thu Dec 22 01:59:51 2011 From: rdivacky at freebsd.org (Roman Divacky) Date: Thu, 22 Dec 2011 08:59:51 +0100 Subject: [llvm-commits] Anyone using the PPC ELF object writer? In-Reply-To: <4EF28C98.1080705@gmail.com> References: <4EF28C98.1080705@gmail.com> Message-ID: <20111222075951.GA38959@freebsd.org> On Wed, Dec 21, 2011 at 08:49:12PM -0500, Rafael ?vila de Esp?ndola wrote: > I am refactoring the object writers and noticed that no test depends on > adjustFixupOffset. Is it dead code and should be removed or are we > missing tests? I commited a start of the object writer support, it's good enough to assemble hello world and some more simple stuff but by no means finished. Do you have any reason for removing it besides no tests? roman From chandlerc at gmail.com Thu Dec 22 03:26:37 2011 From: chandlerc at gmail.com (Chandler Carruth) Date: Thu, 22 Dec 2011 09:26:37 -0000 Subject: [llvm-commits] [llvm] r147142 - in /llvm/trunk: lib/Analysis/BranchProbabilityInfo.cpp test/Analysis/BranchProbabilityInfo/noreturn.ll Message-ID: <20111222092637.B42A82A6C12C@llvm.org> Author: chandlerc Date: Thu Dec 22 03:26:37 2011 New Revision: 147142 URL: http://llvm.org/viewvc/llvm-project?rev=147142&view=rev Log: Make the unreachable probability much much heavier. The previous probability wouldn't be considered "hot" in some weird loop structures or other compounding probability patterns. This makes it much harder to confuse, but isn't really a principled fix. I'd actually like it if we could model a zero probability, as it would make this much easier to reason about. Suggestions for how to do this better are welcome. Modified: llvm/trunk/lib/Analysis/BranchProbabilityInfo.cpp llvm/trunk/test/Analysis/BranchProbabilityInfo/noreturn.ll Modified: llvm/trunk/lib/Analysis/BranchProbabilityInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/BranchProbabilityInfo.cpp?rev=147142&r1=147141&r2=147142&view=diff ============================================================================== --- llvm/trunk/lib/Analysis/BranchProbabilityInfo.cpp (original) +++ llvm/trunk/lib/Analysis/BranchProbabilityInfo.cpp Thu Dec 22 03:26:37 2011 @@ -65,8 +65,9 @@ /// /// This is the weight for a branch not being taken toward a block that /// terminates (eventually) in unreachable. Such a branch is essentially never -/// taken. -static const uint32_t UR_NONTAKEN_WEIGHT = 1023; +/// taken. Set the weight to an absurdly high value so that nested loops don't +/// easily subsume it. +static const uint32_t UR_NONTAKEN_WEIGHT = 1024*1024 - 1; static const uint32_t PH_TAKEN_WEIGHT = 20; static const uint32_t PH_NONTAKEN_WEIGHT = 12; Modified: llvm/trunk/test/Analysis/BranchProbabilityInfo/noreturn.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Analysis/BranchProbabilityInfo/noreturn.ll?rev=147142&r1=147141&r2=147142&view=diff ============================================================================== --- llvm/trunk/test/Analysis/BranchProbabilityInfo/noreturn.ll (original) +++ llvm/trunk/test/Analysis/BranchProbabilityInfo/noreturn.ll Thu Dec 22 03:26:37 2011 @@ -8,8 +8,8 @@ entry: %cond = icmp eq i32 %a, 42 br i1 %cond, label %exit, label %abort -; CHECK: edge entry -> exit probability is 1023 / 1024 -; CHECK: edge entry -> abort probability is 1 / 1024 +; CHECK: edge entry -> exit probability is 1048575 / 1048576 +; CHECK: edge entry -> abort probability is 1 / 1048576 abort: call void @abort() noreturn @@ -26,11 +26,11 @@ i32 2, label %case_b i32 3, label %case_c i32 4, label %case_d] -; CHECK: edge entry -> exit probability is 1023 / 1027 -; CHECK: edge entry -> case_a probability is 1 / 1027 -; CHECK: edge entry -> case_b probability is 1 / 1027 -; CHECK: edge entry -> case_c probability is 1 / 1027 -; CHECK: edge entry -> case_d probability is 1 / 1027 +; CHECK: edge entry -> exit probability is 1048575 / 1048579 +; CHECK: edge entry -> case_a probability is 1 / 1048579 +; CHECK: edge entry -> case_b probability is 1 / 1048579 +; CHECK: edge entry -> case_c probability is 1 / 1048579 +; CHECK: edge entry -> case_d probability is 1 / 1048579 case_a: br label %case_b @@ -55,8 +55,8 @@ entry: %cond1 = icmp eq i32 %a, 42 br i1 %cond1, label %exit, label %dom -; CHECK: edge entry -> exit probability is 1023 / 1024 -; CHECK: edge entry -> dom probability is 1 / 1024 +; CHECK: edge entry -> exit probability is 1048575 / 1048576 +; CHECK: edge entry -> dom probability is 1 / 1048576 dom: %cond2 = icmp ult i32 %a, 42 From stpworld at narod.ru Thu Dec 22 03:59:56 2011 From: stpworld at narod.ru (Stepan Dyatkovskiy) Date: Thu, 22 Dec 2011 13:59:56 +0400 Subject: [llvm-commits] [llvm] r146578 - in /llvm/trunk: lib/Transforms/Scalar/LoopUnswitch.cpp test/Transforms/LoopUnswitch/2011-11-18-SimpleSwitch.ll test/Transforms/LoopUnswitch/2011-11-18-TwoSwitches-Threshold.ll test/Transforms/LoopUnswitch/2011-11-18-TwoSwitches.ll In-Reply-To: <01A21900-6703-4740-81EE-EB282C8D02A8@apple.com> References: <20111214191917.910052A6C12C@llvm.org> <01A21900-6703-4740-81EE-EB282C8D02A8@apple.com> Message-ID: <4EF2FF9C.7000805@narod.ru> OK. Thanks, Chad. Now I have a time and I look at it. -Stepan. Chad Rosier wrote: > Hi Stepan, > I noticed this patch caused an ~8% compile-time regression for MultiSource/Benchmarks/Prolangs-C++/shapes/shapes for ARMv7 -O3 -mthumb. If you have a moment would you mind taking a look? The test-suite can be downloaded from the llvm repository (See: http://llvm.org/docs/TestingGuide.html#testsuite). Here are the command line arguments I used to reproduce the regression: > > /Users/mcrosier/llvm-clean/Release+Asserts/Release+Asserts/bin/clang++ -I/Users/mcrosier/llvm-clean/Release+Asserts/projects/test-suite/MultiSource/Benchmarks/Prolangs-C++/shapes -I/Users/mcrosier/llvm-clean/llvm/projects/test-suite/MultiSource/Benchmarks/Prolangs-C++/shapes -I/Users/mcrosier/llvm-clean/Release+Asserts/projects/test-suite/../../../llvm/projects/test-suite/include -I../../../../include -I/Users/mcrosier/llvm-clean/Release+Asserts/include -I/Users/mcrosier/llvm-clean/llvm/include -D_GNU_SOURCE -D__STDC_LIMIT_MACROS -DNDEBUG -DSMALL_PROBLEM_SIZE -O3 -mthumb -miphoneos-version-min=4.0 -Wl,--no-demangle -ccc-install-dir /Developer/Platforms/iPhoneOS.platform/Developer/usr/bin -arch armv7 -isysroot /Developer/Platforms/iPhoneOS.platform/Developer/SDKs/iPhoneOS6.0.Internal.sdk -c /Users/mcrosier/llvm-clean/llvm/projects/test-suite/MultiSource/Benchmarks/Prolangs-C++/shapes/bjarne.cpp -o Output/bjarne.llvm.o > > Chad > > For Apple's record this is being tracked by. > > On Dec 14, 2011, at 11:19 AM, Stepan Dyatkovskiy wrote: > >> Author: dyatkovskiy >> Date: Wed Dec 14 13:19:17 2011 >> New Revision: 146578 >> >> URL: http://llvm.org/viewvc/llvm-project?rev=146578&view=rev >> Log: >> Fix for bug #11429: Wrong behaviour for switches. Small improvement for code size heuristics. >> >> Added: >> llvm/trunk/test/Transforms/LoopUnswitch/2011-11-18-SimpleSwitch.ll >> llvm/trunk/test/Transforms/LoopUnswitch/2011-11-18-TwoSwitches-Threshold.ll >> llvm/trunk/test/Transforms/LoopUnswitch/2011-11-18-TwoSwitches.ll >> Modified: >> llvm/trunk/lib/Transforms/Scalar/LoopUnswitch.cpp >> >> Modified: llvm/trunk/lib/Transforms/Scalar/LoopUnswitch.cpp >> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/LoopUnswitch.cpp?rev=146578&r1=146577&r2=146578&view=diff >> ============================================================================== >> --- llvm/trunk/lib/Transforms/Scalar/LoopUnswitch.cpp (original) >> +++ llvm/trunk/lib/Transforms/Scalar/LoopUnswitch.cpp Wed Dec 14 13:19:17 2011 >> @@ -71,7 +71,9 @@ >> // LoopProcessWorklist - Used to check if second loop needs processing >> // after RewriteLoopBodyWithConditionConstant rewrites first loop. >> std::vector LoopProcessWorklist; >> - SmallPtrSet UnswitchedVals; >> + >> + // FIXME: Consider custom class for this. >> + std::map > UnswitchedVals; >> >> bool OptimizeForSize; >> bool redoLoop; >> @@ -117,7 +119,15 @@ >> private: >> >> virtual void releaseMemory() { >> - UnswitchedVals.clear(); >> + // We need to forget about all switches in the current loop. >> + // FIXME: Do it better than enumerating all blocks of code >> + // and see if it is a switch instruction. >> + for (Loop::block_iterator I = currentLoop->block_begin(), >> + E = currentLoop->block_end(); I != E; ++I) { >> + SwitchInst* SI = dyn_cast((*I)->getTerminator()); >> + if (SI) >> + UnswitchedVals.erase(SI); >> + } >> } >> >> /// RemoveLoopFromWorklist - If the specified loop is on the loop worklist, >> @@ -128,6 +138,12 @@ >> if (I != LoopProcessWorklist.end()) >> LoopProcessWorklist.erase(I); >> } >> + >> + /// For new loop switches we clone info about values that was >> + /// already unswitched and has redundant successors. >> + /// Note, that new loop data is stored inside the VMap. >> + void CloneUnswitchedVals(const ValueToValueMapTy& VMap, >> + const BasicBlock* SrcBB); >> >> void initLoopData() { >> loopHeader = currentLoop->getHeader(); >> @@ -255,13 +271,25 @@ >> } else if (SwitchInst *SI = dyn_cast(TI)) { >> Value *LoopCond = FindLIVLoopCondition(SI->getCondition(), >> currentLoop, Changed); >> - if (LoopCond&& SI->getNumCases()> 1) { >> + unsigned NumCases = SI->getNumCases(); >> + if (LoopCond&& NumCases> 1) { >> // Find a value to unswitch on: >> // FIXME: this should chose the most expensive case! >> // FIXME: scan for a case with a non-critical edge? >> - Constant *UnswitchVal = SI->getCaseValue(1); >> + Constant *UnswitchVal = NULL; >> + >> // Do not process same value again and again. >> - if (!UnswitchedVals.insert(UnswitchVal)) >> + // At this point we have some cases already unswitched and >> + // some not yet unswitched. Let's find the first not yet unswitched one. >> + for (unsigned i = 1; i< NumCases; ++i) { >> + Constant* UnswitchValCandidate = SI->getCaseValue(i); >> + if (!UnswitchedVals[SI].count(UnswitchValCandidate)) { >> + UnswitchVal = UnswitchValCandidate; >> + break; >> + } >> + } >> + >> + if (!UnswitchVal) >> continue; >> >> if (UnswitchIfProfitable(LoopCond, UnswitchVal)) { >> @@ -287,6 +315,23 @@ >> return Changed; >> } >> >> +/// For new loop switches we clone info about values that was >> +/// already unswitched and has redundant successors. >> +/// Not that new loop data is stored inside the VMap. >> +void LoopUnswitch::CloneUnswitchedVals(const ValueToValueMapTy& VMap, >> + const BasicBlock* SrcBB) { >> + >> + const SwitchInst* SI = dyn_cast(SrcBB->getTerminator()); >> + if (SI&& UnswitchedVals.count(SI)) { >> + // Don't clone a totally simplified switch. >> + if (isa(SI->getCondition())) >> + return; >> + Value* I = VMap.lookup(SI); >> + assert(I&& "All instructions that are in SrcBB must be in VMap."); >> + UnswitchedVals[cast(I)] = UnswitchedVals[SI]; >> + } >> +} >> + >> /// isTrivialLoopExitBlock - Check to see if all paths from BB exit the >> /// loop with no side effects (including infinite loops). >> /// >> @@ -378,14 +423,25 @@ >> // Check to see if a successor of the switch is guaranteed to go to the >> // latch block or exit through a one exit block without having any >> // side-effects. If so, determine the value of Cond that causes it to do >> - // this. Note that we can't trivially unswitch on the default case. >> - for (unsigned i = 1, e = SI->getNumSuccessors(); i != e; ++i) >> - if ((LoopExitBB = isTrivialLoopExitBlock(currentLoop, >> + // this. >> + // Note that we can't trivially unswitch on the default case or >> + // on already unswitched cases. >> + for (unsigned i = 1, e = SI->getNumSuccessors(); i != e; ++i) { >> + BasicBlock* LoopExitCandidate; >> + if ((LoopExitCandidate = isTrivialLoopExitBlock(currentLoop, >> SI->getSuccessor(i)))) { >> // Okay, we found a trivial case, remember the value that is trivial. >> - if (Val) *Val = SI->getCaseValue(i); >> + ConstantInt* CaseVal = SI->getCaseValue(i); >> + >> + // Check that it was not unswitched before, since already unswitched >> + // trivial vals are looks trivial too. >> + if (UnswitchedVals[SI].count(CaseVal)) >> + continue; >> + LoopExitBB = LoopExitCandidate; >> + if (Val) *Val = CaseVal; >> break; >> } >> + } >> } >> >> // If we didn't find a single unique LoopExit block, or if the loop exit block >> @@ -447,8 +503,14 @@ >> // expansion, and the number of basic blocks, to avoid loops with >> // large numbers of branches which cause loop unswitching to go crazy. >> // This is a very ad-hoc heuristic. >> - if (Metrics.NumInsts> Threshold || >> - Metrics.NumBlocks * 5> Threshold || >> + >> + unsigned NumUnswitched = >> + (NumSwitches + NumBranches) + 1 /*take in account current iteration*/; >> + >> + unsigned NumInsts = Metrics.NumInsts * NumUnswitched; >> + unsigned NumBlocks = Metrics.NumBlocks * NumUnswitched; >> + >> + if (NumInsts> Threshold || NumBlocks * 5> Threshold || >> Metrics.containsIndirectBr || Metrics.isRecursive) { >> DEBUG(dbgs()<< "NOT unswitching loop %" >> << currentLoop->getHeader()->getName()<< ", cost too high:" >> @@ -620,6 +682,12 @@ >> ValueToValueMapTy VMap; >> for (unsigned i = 0, e = LoopBlocks.size(); i != e; ++i) { >> BasicBlock *NewBB = CloneBasicBlock(LoopBlocks[i], VMap, ".us", F); >> + >> + // Inherit simplified switches info for NewBB >> + // We needn't pass NewBB since its instructions are already contained >> + // inside the VMap. >> + CloneUnswitchedVals(VMap, LoopBlocks[i]); >> + >> NewBlocks.push_back(NewBB); >> VMap[LoopBlocks[i]] = NewBB; // Keep the BB mapping. >> LPM->cloneBasicBlockSimpleAnalysis(LoopBlocks[i], NewBB, L); >> @@ -945,6 +1013,9 @@ >> BasicBlock *Switch = SI->getParent(); >> BasicBlock *SISucc = SI->getSuccessor(DeadCase); >> BasicBlock *Latch = L->getLoopLatch(); >> + >> + UnswitchedVals[SI].insert(Val); >> + >> if (!SI->findCaseDest(SISucc)) continue; // Edge is critical. >> // If the DeadCase successor dominates the loop latch, then the >> // transformation isn't safe since it will delete the sole predecessor edge >> >> Added: llvm/trunk/test/Transforms/LoopUnswitch/2011-11-18-SimpleSwitch.ll >> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/LoopUnswitch/2011-11-18-SimpleSwitch.ll?rev=146578&view=auto >> ============================================================================== >> --- llvm/trunk/test/Transforms/LoopUnswitch/2011-11-18-SimpleSwitch.ll (added) >> +++ llvm/trunk/test/Transforms/LoopUnswitch/2011-11-18-SimpleSwitch.ll Wed Dec 14 13:19:17 2011 >> @@ -0,0 +1,91 @@ >> +; RUN: opt -loop-unswitch -disable-output -stats -info-output-file -< %s | FileCheck --check-prefix=STATS %s >> +; RUN: opt -S -loop-unswitch -verify-loop-info -verify-dom-info %s | FileCheck %s >> + >> +; STATS: 1 loop-simplify - Number of pre-header or exit blocks inserted >> +; STATS: 2 loop-unswitch - Number of switches unswitched >> + >> +; CHECK: %1 = icmp eq i32 %c, 1 >> +; CHECK-NEXT: br i1 %1, label %.split.us, label %..split_crit_edge >> + >> +; CHECK: ..split_crit_edge: ; preds = %0 >> +; CHECK-NEXT: br label %.split >> + >> +; CHECK: .split.us: ; preds = %0 >> +; CHECK-NEXT: br label %loop_begin.us >> + >> +; CHECK: loop_begin.us: ; preds = %loop_begin.backedge.us, %.split.us >> +; CHECK-NEXT: %var_val.us = load i32* %var >> +; CHECK-NEXT: switch i32 1, label %default.us-lcssa.us [ >> +; CHECK-NEXT: i32 1, label %inc.us >> + >> +; CHECK: inc.us: ; preds = %loop_begin.us >> +; CHECK-NEXT: call void @incf() noreturn nounwind >> +; CHECK-NEXT: br label %loop_begin.backedge.us >> + >> +; CHECK: .split: ; preds = %..split_crit_edge >> +; CHECK-NEXT: %2 = icmp eq i32 %c, 2 >> +; CHECK-NEXT: br i1 %2, label %.split.split.us, label %.split..split.split_crit_edge >> + >> +; CHECK: .split..split.split_crit_edge: ; preds = %.split >> +; CHECK-NEXT: br label %.split.split >> + >> +; CHECK: .split.split.us: ; preds = %.split >> +; CHECK-NEXT: br label %loop_begin.us1 >> + >> +; CHECK: loop_begin.us1: ; preds = %loop_begin.backedge.us5, %.split.split.us >> +; CHECK-NEXT: %var_val.us2 = load i32* %var >> +; CHECK-NEXT: switch i32 2, label %default.us-lcssa.us-lcssa.us [ >> +; CHECK-NEXT: i32 1, label %inc.us3 >> +; CHECK-NEXT: i32 2, label %dec.us4 >> +; CHECK-NEXT: ] >> + >> +; CHECK: dec.us4: ; preds = %loop_begin.us1 >> +; CHECK-NEXT: call void @decf() noreturn nounwind >> +; CHECK-NEXT: br label %loop_begin.backedge.us5 >> + >> +; CHECK: .split.split: ; preds = %.split..split.split_crit_edge >> +; CHECK-NEXT: br label %loop_begin >> + >> +; CHECK: loop_begin: ; preds = %loop_begin.backedge, %.split.split >> +; CHECK-NEXT: %var_val = load i32* %var >> +; CHECK-NEXT: switch i32 %c, label %default.us-lcssa.us-lcssa [ >> +; CHECK-NEXT: i32 1, label %inc >> +; CHECK-NEXT: i32 2, label %dec >> +; CHECK-NEXT: ] >> + >> +; CHECK: inc: ; preds = %loop_begin >> +; CHECK-NEXT: br i1 true, label %us-unreachable.us-lcssa, label %inc.split >> + >> +; CHECK: dec: ; preds = %loop_begin >> +; CHECK-NEXT: br i1 true, label %us-unreachable6, label %dec.split >> + >> +define i32 @test(i32* %var) { >> + %mem = alloca i32 >> + store i32 2, i32* %mem >> + %c = load i32* %mem >> + >> + br label %loop_begin >> + >> +loop_begin: >> + >> + %var_val = load i32* %var >> + >> + switch i32 %c, label %default [ >> + i32 1, label %inc >> + i32 2, label %dec >> + ] >> + >> +inc: >> + call void @incf() noreturn nounwind >> + br label %loop_begin >> +dec: >> + call void @decf() noreturn nounwind >> + br label %loop_begin >> +default: >> + br label %loop_exit >> +loop_exit: >> + ret i32 0 >> +} >> + >> +declare void @incf() noreturn >> +declare void @decf() noreturn >> >> Added: llvm/trunk/test/Transforms/LoopUnswitch/2011-11-18-TwoSwitches-Threshold.ll >> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/LoopUnswitch/2011-11-18-TwoSwitches-Threshold.ll?rev=146578&view=auto >> ============================================================================== >> --- llvm/trunk/test/Transforms/LoopUnswitch/2011-11-18-TwoSwitches-Threshold.ll (added) >> +++ llvm/trunk/test/Transforms/LoopUnswitch/2011-11-18-TwoSwitches-Threshold.ll Wed Dec 14 13:19:17 2011 >> @@ -0,0 +1,84 @@ >> +; RUN: opt -loop-unswitch -loop-unswitch-threshold 30 -disable-output -stats -info-output-file -< %s | FileCheck --check-prefix=STATS %s >> +; RUN: opt -S -loop-unswitch -loop-unswitch-threshold 30 -verify-loop-info -verify-dom-info %s | FileCheck %s >> + >> +; STATS: 1 loop-simplify - Number of pre-header or exit blocks inserted >> +; STATS: 1 loop-unswitch - Number of switches unswitched >> + >> +; ModuleID = '../llvm/test/Transforms/LoopUnswitch/2011-11-18-TwoSwitches.ll' >> + >> +; CHECK: %1 = icmp eq i32 %c, 1 >> +; CHECK-NEXT: br i1 %1, label %.split.us, label %..split_crit_edge >> + >> +; CHECK: ..split_crit_edge: ; preds = %0 >> +; CHECK-NEXT: br label %.split >> + >> +; CHECK: .split.us: ; preds = %0 >> +; CHECK-NEXT: br label %loop_begin.us >> + >> +; CHECK: loop_begin.us: ; preds = %loop_begin.backedge.us, %.split.us >> +; CHECK: switch i32 1, label %second_switch.us [ >> +; CHECK-NEXT: i32 1, label %inc.us >> + >> +; CHECK: inc.us: ; preds = %second_switch.us, %loop_begin.us >> +; CHECK-NEXT: call void @incf() noreturn nounwind >> +; CHECK-NEXT: br label %loop_begin.backedge.us >> + >> +; CHECK: second_switch.us: ; preds = %loop_begin.us >> +; CHECK-NEXT: switch i32 %d, label %default.us [ >> +; CHECK-NEXT: i32 1, label %inc.us >> +; CHECK-NEXT: ] >> + >> +; CHECK: .split: ; preds = %..split_crit_edge >> +; CHECK-NEXT: br label %loop_begin >> + >> +; CHECK: loop_begin: ; preds = %loop_begin.backedge, %.split >> +; CHECK: switch i32 %c, label %second_switch [ >> +; CHECK-NEXT: i32 1, label %loop_begin.inc_crit_edge >> +; CHECK-NEXT: ] >> + >> +; CHECK: loop_begin.inc_crit_edge: ; preds = %loop_begin >> +; CHECK-NEXT: br i1 true, label %us-unreachable, label %inc >> + >> +; CHECK: second_switch: ; preds = %loop_begin >> +; CHECK-NEXT: switch i32 %d, label %default [ >> +; CHECK-NEXT: i32 1, label %inc >> +; CHECK-NEXT: ] >> + >> +; CHECK: inc: ; preds = %loop_begin.inc_crit_edge, %second_switch >> +; CHECK-NEXT: call void @incf() noreturn nounwind >> +; CHECK-NEXT: br label %loop_begin.backedge >> + >> +define i32 @test(i32* %var) { >> + %mem = alloca i32 >> + store i32 2, i32* %mem >> + %c = load i32* %mem >> + %d = load i32* %mem >> + >> + br label %loop_begin >> + >> +loop_begin: >> + >> + %var_val = load i32* %var >> + >> + switch i32 %c, label %second_switch [ >> + i32 1, label %inc >> + ] >> + >> +second_switch: >> + switch i32 %d, label %default [ >> + i32 1, label %inc >> + ] >> + >> +inc: >> + call void @incf() noreturn nounwind >> + br label %loop_begin >> + >> +default: >> + br label %loop_begin >> + >> +loop_exit: >> + ret i32 0 >> +} >> + >> +declare void @incf() noreturn >> +declare void @decf() noreturn >> >> Added: llvm/trunk/test/Transforms/LoopUnswitch/2011-11-18-TwoSwitches.ll >> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/LoopUnswitch/2011-11-18-TwoSwitches.ll?rev=146578&view=auto >> ============================================================================== >> --- llvm/trunk/test/Transforms/LoopUnswitch/2011-11-18-TwoSwitches.ll (added) >> +++ llvm/trunk/test/Transforms/LoopUnswitch/2011-11-18-TwoSwitches.ll Wed Dec 14 13:19:17 2011 >> @@ -0,0 +1,138 @@ >> +; RUN: opt -loop-unswitch -loop-unswitch-threshold 1000 -disable-output -stats -info-output-file -< %s | FileCheck --check-prefix=STATS %s >> +; RUN: opt -S -loop-unswitch -loop-unswitch-threshold 1000 -verify-loop-info -verify-dom-info %s | FileCheck %s >> + >> +; STATS: 1 loop-simplify - Number of pre-header or exit blocks inserted >> +; STATS: 3 loop-unswitch - Number of switches unswitched >> + >> +; CHECK: %1 = icmp eq i32 %c, 1 >> +; CHECK-NEXT: br i1 %1, label %.split.us, label %..split_crit_edge >> + >> +; CHECK: ..split_crit_edge: ; preds = %0 >> +; CHECK-NEXT: br label %.split >> + >> +; CHECK: .split.us: ; preds = %0 >> +; CHECK-NEXT: %2 = icmp eq i32 %d, 1 >> +; CHECK-NEXT: br i1 %2, label %.split.us.split.us, label %.split.us..split.us.split_crit_edge >> + >> +; CHECK: .split.us..split.us.split_crit_edge: ; preds = %.split.us >> +; CHECK-NEXT: br label %.split.us.split >> + >> +; CHECK: .split.us.split.us: ; preds = %.split.us >> +; CHECK-NEXT: br label %loop_begin.us.us >> + >> +; CHECK: loop_begin.us.us: ; preds = %loop_begin.backedge.us.us, %.split.us.split.us >> +; CHECK-NEXT: %var_val.us.us = load i32* %var >> +; CHECK-NEXT: switch i32 1, label %second_switch.us.us [ >> +; CHECK-NEXT: i32 1, label %inc.us.us >> + >> +; CHECK: inc.us.us: ; preds = %second_switch.us.us, %loop_begin.us.us >> +; CHECK-NEXT: call void @incf() noreturn nounwind >> +; CHECK-NEXT: br label %loop_begin.backedge.us.us >> + >> +; CHECK: second_switch.us.us: ; preds = %loop_begin.us.us >> +; CHECK-NEXT: switch i32 1, label %default.us.us [ >> +; CHECK-NEXT: i32 1, label %inc.us.us >> + >> +; CHECK: .split.us.split: ; preds = %.split.us..split.us.split_crit_edge >> +; CHECK-NEXT: br label %loop_begin.us >> + >> +; CHECK: loop_begin.us: ; preds = %loop_begin.backedge.us, %.split.us.split >> +; CHECK-NEXT: %var_val.us = load i32* %var >> +; CHECK-NEXT: switch i32 1, label %second_switch.us [ >> +; CHECK-NEXT: i32 1, label %inc.us >> + >> +; CHECK: inc.us: ; preds = %second_switch.us.inc.us_crit_edge, %loop_begin.us >> +; CHECK-NEXT: call void @incf() noreturn nounwind >> +; CHECK-NEXT: br label %loop_begin.backedge.us >> + >> +; CHECK: second_switch.us: ; preds = %loop_begin.us >> +; CHECK-NEXT: switch i32 %d, label %default.us [ >> +; CHECK-NEXT: i32 1, label %second_switch.us.inc.us_crit_edge >> +; CHECK-NEXT: ] >> + >> +; CHECK: second_switch.us.inc.us_crit_edge: ; preds = %second_switch.us >> +; CHECK-NEXT: br i1 true, label %us-unreachable8, label %inc.us >> + >> +; CHECK: .split: ; preds = %..split_crit_edge >> +; CHECK-NEXT: %3 = icmp eq i32 %d, 1 >> +; CHECK-NEXT: br i1 %3, label %.split.split.us, label %.split..split.split_crit_edge >> + >> +; CHECK: .split..split.split_crit_edge: ; preds = %.split >> +; CHECK-NEXT: br label %.split.split >> + >> +; CHECK: .split.split.us: ; preds = %.split >> +; CHECK-NEXT: br label %loop_begin.us1 >> + >> +; CHECK: loop_begin.us1: ; preds = %loop_begin.backedge.us6, %.split.split.us >> +; CHECK-NEXT: %var_val.us2 = load i32* %var >> +; CHECK-NEXT: switch i32 %c, label %second_switch.us4 [ >> +; CHECK-NEXT: i32 1, label %loop_begin.inc_crit_edge.us >> +; CHECK-NEXT: ] >> + >> +; CHECK: inc.us3: ; preds = %loop_begin.inc_crit_edge.us, %second_switch.us4 >> +; CHECK-NEXT: call void @incf() noreturn nounwind >> +; CHECK-NEXT: br label %loop_begin.backedge.us6 >> + >> +; CHECK: second_switch.us4: ; preds = %loop_begin.us1 >> +; CHECK-NEXT: switch i32 1, label %default.us5 [ >> +; CHECK-NEXT: i32 1, label %inc.us3 >> +; CHECK-NEXT: ] >> + >> +; CHECK: loop_begin.inc_crit_edge.us: ; preds = %loop_begin.us1 >> +; CHECK-NEXT: br i1 true, label %us-unreachable.us-lcssa.us, label %inc.us3 >> + >> +; CHECK: .split.split: ; preds = %.split..split.split_crit_edge >> +; CHECK-NEXT: br label %loop_begin >> + >> +; CHECK: loop_begin: ; preds = %loop_begin.backedge, %.split.split >> +; CHECK-NEXT: %var_val = load i32* %var >> +; CHECK-NEXT: switch i32 %c, label %second_switch [ >> +; CHECK-NEXT: i32 1, label %loop_begin.inc_crit_edge >> +; CHECK-NEXT: ] >> + >> +; CHECK: loop_begin.inc_crit_edge: ; preds = %loop_begin >> +; CHECK-NEXT: br i1 true, label %us-unreachable.us-lcssa, label %inc >> + >> +; CHECK: second_switch: ; preds = %loop_begin >> +; CHECK-NEXT: switch i32 %d, label %default [ >> +; CHECK-NEXT: i32 1, label %second_switch.inc_crit_edge >> +; CHECK-NEXT: ] >> + >> +; CHECK: second_switch.inc_crit_edge: ; preds = %second_switch >> +; CHECK-NEXT: br i1 true, label %us-unreachable7, label %inc >> + >> + >> +define i32 @test(i32* %var) { >> + %mem = alloca i32 >> + store i32 2, i32* %mem >> + %c = load i32* %mem >> + %d = load i32* %mem >> + >> + br label %loop_begin >> + >> +loop_begin: >> + >> + %var_val = load i32* %var >> + >> + switch i32 %c, label %second_switch [ >> + i32 1, label %inc >> + ] >> + >> +second_switch: >> + switch i32 %d, label %default [ >> + i32 1, label %inc >> + ] >> + >> +inc: >> + call void @incf() noreturn nounwind >> + br label %loop_begin >> + >> +default: >> + br label %loop_begin >> + >> +loop_exit: >> + ret i32 0 >> +} >> + >> +declare void @incf() noreturn >> +declare void @decf() noreturn >> >> >> _______________________________________________ >> llvm-commits mailing list >> llvm-commits at cs.uiuc.edu >> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits > From rafael.espindola at gmail.com Thu Dec 22 07:17:22 2011 From: rafael.espindola at gmail.com (=?ISO-8859-1?Q?Rafael_=C1vila_de_Esp=EDndola?=) Date: Thu, 22 Dec 2011 08:17:22 -0500 Subject: [llvm-commits] Anyone using the PPC ELF object writer? In-Reply-To: <20111222075951.GA38959@freebsd.org> References: <4EF28C98.1080705@gmail.com> <20111222075951.GA38959@freebsd.org> Message-ID: <4EF32DE2.1030602@gmail.com> > I commited a start of the object writer support, it's good enough to > assemble hello world and some more simple stuff but by no means finished. > > Do you have any reason for removing it besides no tests? I did not remove it, but refactored it to lib/Target/PorwerPC. While doing this I noticed that all tests would still pass with adjustFixupOffset disabled, so I don't have a lot of confidence that nothing else was broken by the refactoring. Do you have a test that uses ppc's adjustFixupOffset? Could you add it to the testsuite? > roman Thanks, Rafael From rafael.espindola at gmail.com Thu Dec 22 07:41:11 2011 From: rafael.espindola at gmail.com (=?ISO-8859-1?Q?Rafael_=C1vila_de_Esp=EDndola?=) Date: Thu, 22 Dec 2011 08:41:11 -0500 Subject: [llvm-commits] [llvm] r146977 - /llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp In-Reply-To: References: <20111220173813.0BD732A6C12C@llvm.org> Message-ID: <4EF33377.8030405@gmail.com> > Why no tests needed? We should have tests that just exercise the > parsing, no? If not, I think it would be good to wait on commit until > enough functionality is there to at least have a sanity test. > Essentially, you should have enough tests here to ensure you didn't > commit an 'abort()' or a divide by zero. Agreed. Jason, can you add a test showing that we at least parse eabi_attribute and .arch? Thanks, Rafael From rafael.espindola at gmail.com Thu Dec 22 07:54:55 2011 From: rafael.espindola at gmail.com (=?UTF-8?B?UmFmYWVsIMOBdmlsYSBkZSBFc3DDrW5kb2xh?=) Date: Thu, 22 Dec 2011 08:54:55 -0500 Subject: [llvm-commits] [PATCH] Add basic ELF Dyld loader (on behalf of Andy Kaylor) In-Reply-To: <2C2ECF4B05BCF3489866AB805260FEC5065068774E@rrsmsx509.amr.corp.intel.com> References: <2C2ECF4B05BCF3489866AB805260FEC50630AE0806@rrsmsx509.amr.corp.intel.com> <4EE8F09A.2060302@gmail.com> <5A9BD224CEA58D4CB62235967D650C161733538E@orsmsx509.amr.corp.intel.com> <4EECD207.6020507@gmail.com> <2C2ECF4B05BCF3489866AB805260FEC5065068774E@rrsmsx509.amr.corp.intel.com> Message-ID: <4EF336AF.3090903@gmail.com> On 19/12/11 03:16 PM, Malea, Daniel wrote: > Hi all, > > Thanks everyone for your input; here's an updated patch with passing tests! In addition to running the existing ExecutionEngine tests against MCJIT, we added a few new test cases. To run them against the MCJIT implementation, invoke lit with the "--param jit_impl=mcjit" option, which then causes lli to be invoked with "-use-mcjit". > > Compared to the last iteration of the patch, here?s exactly what has changed: > - Removed "default:" case in switch statement as per Rafael?s suggestion > - Moved RuntimeDyldMachO::isKnownFormat() into isCompatibleFormat() of the same class > - Added 6 new test cases in test/ExecutionEngine > - Added ?XFAIL: mcjit? to tests we expect not to pass > - Updated lit.cfg and existing ExecutionEngine tests to handle the jit_impl parameter > - Updated lli to use the default memory manager (to enable MCJIT to even run) > - Removed Objective-C specific name handling behavior from the MCJIT memory manager > > Regarding the last point, I'm not really confident that just removing the objective-c specific behavior is correct, but it seems like language specific things should probably not go in something called "MCJITMemoryManager". Perhaps Jim Grosbach can comment as he is on the commit logs for the code being touched. Maybe we should rename the existing implementation to something like ObjCMCJITMemoryManager? > > Regarding the tests, the code isn't quite robust enough to enable all the existing ExecutionEngine tests to pass due to known issues with external function calls and globals; but nonetheless the following existing tests do pass, at least on (Ubuntu) Linux ia64: > This is really cool! You might be able to say "%lli" instead of "lli %jit_impl", similar to what we do with %clang_cc1 I will let Jim do the final review as he knows that code better. Cheers, Rafael From rafael.espindola at gmail.com Thu Dec 22 08:01:18 2011 From: rafael.espindola at gmail.com (Rafael Espindola) Date: Thu, 22 Dec 2011 14:01:18 -0000 Subject: [llvm-commits] [llvm] r147143 - in /llvm/trunk: autoconf/configure.ac configure Message-ID: <20111222140119.0ECE52A6C12C@llvm.org> Author: rafael Date: Thu Dec 22 08:01:18 2011 New Revision: 147143 URL: http://llvm.org/viewvc/llvm-project?rev=147143&view=rev Log: Add configure support for kfreebsd and hurd. Patch by Sylvestre Ledru. Fixes pr11620. Modified: llvm/trunk/autoconf/configure.ac llvm/trunk/configure Modified: llvm/trunk/autoconf/configure.ac URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/autoconf/configure.ac?rev=147143&r1=147142&r2=147143&view=diff ============================================================================== --- llvm/trunk/autoconf/configure.ac (original) +++ llvm/trunk/autoconf/configure.ac Thu Dec 22 08:01:18 2011 @@ -189,7 +189,7 @@ llvm_cv_no_link_all_option="-Wl,-noall_load" llvm_cv_os_type="Minix" llvm_cv_platform_type="Unix" ;; - *-*-freebsd*) + *-*-freebsd* | *-*-kfreebsd-gnu) llvm_cv_link_all_option="-Wl,--whole-archive" llvm_cv_no_link_all_option="-Wl,--no-whole-archive" llvm_cv_os_type="FreeBSD" @@ -224,6 +224,11 @@ llvm_cv_no_link_all_option="-Wl,--no-whole-archive" llvm_cv_os_type="Linux" llvm_cv_platform_type="Unix" ;; + *-*-gnu*) + llvm_cv_link_all_option="-Wl,--whole-archive" + llvm_cv_no_link_all_option="-Wl,--no-whole-archive" + llvm_cv_os_type="GNU" + llvm_cv_platform_type="Unix" ;; *-*-solaris*) llvm_cv_link_all_option="-Wl,-z,allextract" llvm_cv_no_link_all_option="-Wl,-z,defaultextract" Modified: llvm/trunk/configure URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/configure?rev=147143&r1=147142&r2=147143&view=diff ============================================================================== --- llvm/trunk/configure (original) +++ llvm/trunk/configure Thu Dec 22 08:01:18 2011 @@ -3693,7 +3693,7 @@ llvm_cv_no_link_all_option="-Wl,-noall_load" llvm_cv_os_type="Minix" llvm_cv_platform_type="Unix" ;; - *-*-freebsd*) + *-*-freebsd* | *-*-kfreebsd-gnu) llvm_cv_link_all_option="-Wl,--whole-archive" llvm_cv_no_link_all_option="-Wl,--no-whole-archive" llvm_cv_os_type="FreeBSD" @@ -3728,6 +3728,11 @@ llvm_cv_no_link_all_option="-Wl,--no-whole-archive" llvm_cv_os_type="Linux" llvm_cv_platform_type="Unix" ;; + *-*-gnu*) + llvm_cv_link_all_option="-Wl,--whole-archive" + llvm_cv_no_link_all_option="-Wl,--no-whole-archive" + llvm_cv_os_type="GNU" + llvm_cv_platform_type="Unix" ;; *-*-solaris*) llvm_cv_link_all_option="-Wl,-z,allextract" llvm_cv_no_link_all_option="-Wl,-z,defaultextract" @@ -10495,7 +10500,7 @@ lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2 lt_status=$lt_dlunknown cat > conftest.$ac_ext < Author: d0k Date: Thu Dec 22 08:22:14 2011 New Revision: 147144 URL: http://llvm.org/viewvc/llvm-project?rev=147144&view=rev Log: Give string constants generated by IRBuilder private linkage. Fixes PR11640. Modified: llvm/trunk/lib/VMCore/IRBuilder.cpp llvm/trunk/test/Transforms/SimplifyLibCalls/Printf.ll Modified: llvm/trunk/lib/VMCore/IRBuilder.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/IRBuilder.cpp?rev=147144&r1=147143&r2=147144&view=diff ============================================================================== --- llvm/trunk/lib/VMCore/IRBuilder.cpp (original) +++ llvm/trunk/lib/VMCore/IRBuilder.cpp Thu Dec 22 08:22:14 2011 @@ -27,7 +27,7 @@ Constant *StrConstant = ConstantArray::get(Context, Str, true); Module &M = *BB->getParent()->getParent(); GlobalVariable *GV = new GlobalVariable(M, StrConstant->getType(), - true, GlobalValue::InternalLinkage, + true, GlobalValue::PrivateLinkage, StrConstant, "", 0, false); GV->setName(Name); GV->setUnnamedAddr(true); Modified: llvm/trunk/test/Transforms/SimplifyLibCalls/Printf.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/SimplifyLibCalls/Printf.ll?rev=147144&r1=147143&r2=147144&view=diff ============================================================================== --- llvm/trunk/test/Transforms/SimplifyLibCalls/Printf.ll (original) +++ llvm/trunk/test/Transforms/SimplifyLibCalls/Printf.ll Thu Dec 22 08:22:14 2011 @@ -3,7 +3,7 @@ @str = internal constant [13 x i8] c"hello world\0A\00" ; <[13 x i8]*> [#uses=1] @str1 = internal constant [2 x i8] c"h\00" ; <[2 x i8]*> [#uses=1] -; CHECK: internal unnamed_addr constant [12 x i8] c"hello world\00" +; CHECK: private unnamed_addr constant [12 x i8] c"hello world\00" declare i32 @printf(i8*, ...) From klimek at google.com Thu Dec 22 08:55:43 2011 From: klimek at google.com (Manuel Klimek) Date: Thu, 22 Dec 2011 15:55:43 +0100 Subject: [llvm-commits] [PATCH] Removes most of the templating from the JSON parser Message-ID: I'm happy to apply this if people feel like this improves the situation. I'm not sure it does, though, which is why I'd like to get comments on it first. Better? Worse? The same? Ideas how to make it better? Rietveld: http://codereview.appspot.com/5504072 Cheers, /Manuel -------------- next part -------------- A non-text attachment was scrubbed... Name: json-remove-templates.patch Type: text/x-patch Size: 18686 bytes Desc: not available Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20111222/a0059c25/attachment.bin From grosbach at apple.com Thu Dec 22 11:04:50 2011 From: grosbach at apple.com (Jim Grosbach) Date: Thu, 22 Dec 2011 17:04:50 -0000 Subject: [llvm-commits] [llvm] r147150 - /llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Message-ID: <20111222170450.C33032A6C12C@llvm.org> Author: grosbach Date: Thu Dec 22 11:04:50 2011 New Revision: 147150 URL: http://llvm.org/viewvc/llvm-project?rev=147150&view=rev Log: Nuke invalid comment from copy/paste. Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp?rev=147150&r1=147149&r2=147150&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp (original) +++ llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Thu Dec 22 11:04:50 2011 @@ -5835,7 +5835,6 @@ case ARM::LSLr: ShiftTy = ARM_AM::lsl; break; case ARM::RORr: ShiftTy = ARM_AM::ror; break; } - // A shift by zero is a plain MOVr, not a MOVsi. unsigned Shifter = ARM_AM::getSORegOpc(ShiftTy, 0); MCInst TmpInst; TmpInst.setOpcode(ARM::MOVsr); From grosbach at apple.com Thu Dec 22 11:17:10 2011 From: grosbach at apple.com (Jim Grosbach) Date: Thu, 22 Dec 2011 17:17:10 -0000 Subject: [llvm-commits] [llvm] r147151 - /llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Message-ID: <20111222171710.48AE62A6C12C@llvm.org> Author: grosbach Date: Thu Dec 22 11:17:10 2011 New Revision: 147151 URL: http://llvm.org/viewvc/llvm-project?rev=147151&view=rev Log: Tidy up. Trailing whitespace. Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp?rev=147151&r1=147150&r2=147151&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp (original) +++ llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Thu Dec 22 11:17:10 2011 @@ -3189,14 +3189,14 @@ .Case("faultmask", 19) .Case("control", 20) .Default(~0U); - + if (FlagsVal == ~0U) return MatchOperand_NoMatch; if (!hasV7Ops() && FlagsVal >= 17 && FlagsVal <= 19) // basepri, basepri_max and faultmask only valid for V7m. return MatchOperand_NoMatch; - + Parser.Lex(); // Eat identifier token. Operands.push_back(ARMOperand::CreateMSRMask(FlagsVal, S)); return MatchOperand_Success; From grosbach at apple.com Thu Dec 22 11:37:00 2011 From: grosbach at apple.com (Jim Grosbach) Date: Thu, 22 Dec 2011 17:37:00 -0000 Subject: [llvm-commits] [llvm] r147152 - /llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Message-ID: <20111222173700.E164C2A6C12C@llvm.org> Author: grosbach Date: Thu Dec 22 11:37:00 2011 New Revision: 147152 URL: http://llvm.org/viewvc/llvm-project?rev=147152&view=rev Log: ARM assembly parser canonicallize on 'lsl' for shift-by-zero form. Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp?rev=147152&r1=147151&r2=147152&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp (original) +++ llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Thu Dec 22 11:37:00 2011 @@ -2421,6 +2421,10 @@ Error(ImmLoc, "immediate shift value out of range"); return -1; } + // shift by zero is a nop. Always send it through as lsl. + // ('as' compatibility) + if (Imm == 0) + ShiftTy = ARM_AM::lsl; } else if (Parser.getTok().is(AsmToken::Identifier)) { ShiftReg = tryParseRegister(); SMLoc L = Parser.getTok().getLoc(); From grosbach at apple.com Thu Dec 22 12:04:04 2011 From: grosbach at apple.com (Jim Grosbach) Date: Thu, 22 Dec 2011 18:04:04 -0000 Subject: [llvm-commits] [llvm] r147153 - in /llvm/trunk: lib/Target/ARM/AsmParser/ARMAsmParser.cpp test/MC/ARM/arm-aliases.s Message-ID: <20111222180404.976A52A6C12C@llvm.org> Author: grosbach Date: Thu Dec 22 12:04:04 2011 New Revision: 147153 URL: http://llvm.org/viewvc/llvm-project?rev=147153&view=rev Log: ARM assembler should accept shift-by-zero for any shifted-immediate operand. Just treat it as-if the shift wasn't there at all. 'as' compatibility. rdar://10604767 Added: llvm/trunk/test/MC/ARM/arm-aliases.s Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp?rev=147153&r1=147152&r2=147153&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp (original) +++ llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Thu Dec 22 12:04:04 2011 @@ -6201,6 +6201,39 @@ } return false; } + case ARM::ANDrsi: + case ARM::ORRrsi: + case ARM::EORrsi: + case ARM::BICrsi: + case ARM::SUBrsi: + case ARM::ADDrsi: { + unsigned newOpc; + ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(Inst.getOperand(3).getImm()); + if (SOpc == ARM_AM::rrx) return false; + switch (Inst.getOpcode()) { + default: assert("unexpected opcode!"); + case ARM::ANDrsi: newOpc = ARM::ANDrr; break; + case ARM::ORRrsi: newOpc = ARM::ORRrr; break; + case ARM::EORrsi: newOpc = ARM::EORrr; break; + case ARM::BICrsi: newOpc = ARM::BICrr; break; + case ARM::SUBrsi: newOpc = ARM::SUBrr; break; + case ARM::ADDrsi: newOpc = ARM::ADDrr; break; + } + // If the shift is by zero, use the non-shifted instruction definition. + if (ARM_AM::getSORegOffset(Inst.getOperand(3).getImm()) == 0) { + MCInst TmpInst; + TmpInst.setOpcode(newOpc); + TmpInst.addOperand(Inst.getOperand(0)); + TmpInst.addOperand(Inst.getOperand(1)); + TmpInst.addOperand(Inst.getOperand(2)); + TmpInst.addOperand(Inst.getOperand(4)); + TmpInst.addOperand(Inst.getOperand(5)); + TmpInst.addOperand(Inst.getOperand(6)); + Inst = TmpInst; + return true; + } + return false; + } case ARM::t2IT: { // The mask bits for all but the first condition are represented as // the low bit of the condition code value implies 't'. We currently Added: llvm/trunk/test/MC/ARM/arm-aliases.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/arm-aliases.s?rev=147153&view=auto ============================================================================== --- llvm/trunk/test/MC/ARM/arm-aliases.s (added) +++ llvm/trunk/test/MC/ARM/arm-aliases.s Thu Dec 22 12:04:04 2011 @@ -0,0 +1,17 @@ +@ RUN: llvm-mc -triple=armv7-apple-darwin -show-encoding < %s | FileCheck %s + .syntax unified + +@ Shift-by-zero should canonicalize to no shift at all (lsl #0 encoding) + add r1, r2, r3, lsl #0 + sub r1, r2, r3, ror #0 + eor r1, r2, r3, lsr #0 + orr r1, r2, r3, asr #0 + and r1, r2, r3, ror #0 + bic r1, r2, r3, lsl #0 + +@ CHECK: add r1, r2, r3 @ encoding: [0x03,0x10,0x82,0xe0] +@ CHECK: sub r1, r2, r3 @ encoding: [0x03,0x10,0x42,0xe0] +@ CHECK: eor r1, r2, r3 @ encoding: [0x03,0x10,0x22,0xe0] +@ CHECK: orr r1, r2, r3 @ encoding: [0x03,0x10,0x82,0xe1] +@ CHECK: and r1, r2, r3 @ encoding: [0x03,0x10,0x02,0xe0] +@ CHECK: bic r1, r2, r3 @ encoding: [0x03,0x10,0xc2,0xe1] From ahatanak at gmail.com Thu Dec 22 12:10:29 2011 From: ahatanak at gmail.com (Akira Hatanaka) Date: Thu, 22 Dec 2011 10:10:29 -0800 Subject: [llvm-commits] [llvm] r146604 - in /llvm/trunk: lib/CodeGen/MachineSink.cpp test/CodeGen/ARM/2011-12-14-machine-sink.ll In-Reply-To: <4EF2B8E6.7020202@gmail.com> References: <20111214232038.E9C9D2A6C12C@llvm.org> <5FF21D31-13D7-4EAA-99FC-EFC1AFA0C8F7@apple.com> <618FAA67-0A0A-4D20-9E58-491632F2BA7C@apple.com> <91FF2423-D67D-4E80-985B-532E27DF3799@apple.com> <4EF2B8E6.7020202@gmail.com> Message-ID: It turns out that the failure was caused by a bug in MipsInstrInfo::storeRegToStackSlot and loadRegFromStackSlot. A MachineMemOperand was not being added to the generated instruction, which was causing MachineLICM to incorrectly determine it is safe to move a load out of a loop. So this wasn't a mis-compilation caused by a bug in Machine Sink or the register allocator. Sorry for the false alarm and thank you for your help. 2011/12/21 Rafael ?vila de Esp?ndola : > On 21/12/11 02:57 AM, Anton Korobeynikov wrote: >>> One alternative for you is to reproduce segfault in debugger and investigate what is being compiled. >>> >>> Other alternative is to narrow down the particular MI sink that is difference maker. You can do this by disabling this patch and adding a artificial threshold in Machine Sink pass to control how many instructions are sinked. One you know the critical MI sink, you can investigate how it impacts other passes, including register allocator, down the road. >>> >>> I am afraid, there is not any easy answer. >> Previously one could use bugpoint to reduce such problems >> automatically via splitting the code into two parts, compiling one >> part with gcc and another - via llvm. >> Though, I doubt this will work right now since cbe is broken now. That >> said, you do not have any automatic reduction in such cases and should >> do everything by hands. >> > > Bugpoint can use a "safe llc", so it might be possible to use "llc > -regalloc=basic" as the safe compiler, but I haven't used that recently. > > Cheers, > Rafael > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From dpatel at apple.com Thu Dec 22 12:14:09 2011 From: dpatel at apple.com (Devang Patel) Date: Thu, 22 Dec 2011 10:14:09 -0800 Subject: [llvm-commits] [llvm] r146604 - in /llvm/trunk: lib/CodeGen/MachineSink.cpp test/CodeGen/ARM/2011-12-14-machine-sink.ll In-Reply-To: References: <20111214232038.E9C9D2A6C12C@llvm.org> <5FF21D31-13D7-4EAA-99FC-EFC1AFA0C8F7@apple.com> <618FAA67-0A0A-4D20-9E58-491632F2BA7C@apple.com> <91FF2423-D67D-4E80-985B-532E27DF3799@apple.com> <4EF2B8E6.7020202@gmail.com> Message-ID: On Dec 22, 2011, at 10:10 AM, Akira Hatanaka wrote: > It turns out that the failure was caused by a bug in > MipsInstrInfo::storeRegToStackSlot and loadRegFromStackSlot. A > MachineMemOperand was not being added to the generated instruction, > which was causing MachineLICM to incorrectly determine it is safe to > move a load out of a loop. So this wasn't a mis-compilation caused by > a bug in Machine Sink or the register allocator. woot! I'm glad that you're able to resolve this. - Devang From clattner at apple.com Thu Dec 22 12:25:12 2011 From: clattner at apple.com (Chris Lattner) Date: Thu, 22 Dec 2011 10:25:12 -0800 Subject: [llvm-commits] [PATCH] Removes most of the templating from the JSON parser In-Reply-To: References: Message-ID: On Dec 22, 2011, at 6:55 AM, Manuel Klimek wrote: > I'm happy to apply this if people feel like this improves the > situation. I'm not sure it does, though, which is why I'd like to get > comments on it first. Better? Worse? The same? Ideas how to make it > better? > > Rietveld: http://codereview.appspot.com/5504072 I think that this is a lot better. An improvement would be to keep some of the trivial methods (e.g. AtomIterator::AtomIterator) inline, which IMO makes things easier to read, and is probably better for performance. -Chris From rafael.espindola at gmail.com Thu Dec 22 12:38:06 2011 From: rafael.espindola at gmail.com (Rafael Espindola) Date: Thu, 22 Dec 2011 18:38:06 -0000 Subject: [llvm-commits] [llvm] r147154 - in /llvm/trunk/lib/Target/PowerPC/MCTargetDesc: PPCAsmBackend.cpp PPCELFObjectWriter.cpp Message-ID: <20111222183806.63B4A2A6C12C@llvm.org> Author: rafael Date: Thu Dec 22 12:38:06 2011 New Revision: 147154 URL: http://llvm.org/viewvc/llvm-project?rev=147154&view=rev Log: Fix an incomplete refactoring of the ppc backend. Thanks to rdivacky for reporting it. It does need some some tests... Modified: llvm/trunk/lib/Target/PowerPC/MCTargetDesc/PPCAsmBackend.cpp llvm/trunk/lib/Target/PowerPC/MCTargetDesc/PPCELFObjectWriter.cpp Modified: llvm/trunk/lib/Target/PowerPC/MCTargetDesc/PPCAsmBackend.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/MCTargetDesc/PPCAsmBackend.cpp?rev=147154&r1=147153&r2=147154&view=diff ============================================================================== --- llvm/trunk/lib/Target/PowerPC/MCTargetDesc/PPCAsmBackend.cpp (original) +++ llvm/trunk/lib/Target/PowerPC/MCTargetDesc/PPCAsmBackend.cpp Thu Dec 22 12:38:06 2011 @@ -57,13 +57,6 @@ MCValue Target, uint64_t &FixedValue) {} }; -class PPCELFObjectWriter : public MCELFObjectTargetWriter { -public: - PPCELFObjectWriter(bool Is64Bit, uint8_t OSABI, uint16_t EMachine, - bool HasRelocationAddend, bool isLittleEndian) - : MCELFObjectTargetWriter(Is64Bit, OSABI, EMachine, HasRelocationAddend) {} -}; - class PPCAsmBackend : public MCAsmBackend { const Target &TheTarget; public: @@ -175,12 +168,7 @@ MCObjectWriter *createObjectWriter(raw_ostream &OS) const { bool is64 = getPointerSize() == 8; - return createELFObjectWriter(new PPCELFObjectWriter( - /*Is64Bit=*/is64, - OSABI, - is64 ? ELF::EM_PPC64 : ELF::EM_PPC, - /*addend*/ true, /*isLittleEndian*/ false), - OS, /*IsLittleEndian=*/false); + return createPPCELFObjectWriter(OS, is64, OSABI); } virtual bool doesSectionRequireSymbols(const MCSection &Section) const { Modified: llvm/trunk/lib/Target/PowerPC/MCTargetDesc/PPCELFObjectWriter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/MCTargetDesc/PPCELFObjectWriter.cpp?rev=147154&r1=147153&r2=147154&view=diff ============================================================================== --- llvm/trunk/lib/Target/PowerPC/MCTargetDesc/PPCELFObjectWriter.cpp (original) +++ llvm/trunk/lib/Target/PowerPC/MCTargetDesc/PPCELFObjectWriter.cpp Thu Dec 22 12:38:06 2011 @@ -31,7 +31,7 @@ PPCELFObjectWriter::PPCELFObjectWriter(bool Is64Bit, uint8_t OSABI) : MCELFObjectTargetWriter(Is64Bit, OSABI, Is64Bit ? ELF::EM_PPC64 : ELF::EM_PPC, - /*HasRelocationAddend*/ false) {} + /*HasRelocationAddend*/ true) {} PPCELFObjectWriter::~PPCELFObjectWriter() { } @@ -99,5 +99,5 @@ bool Is64Bit, uint8_t OSABI) { MCELFObjectTargetWriter *MOTW = new PPCELFObjectWriter(Is64Bit, OSABI); - return createELFObjectWriter(MOTW, OS, /*IsLittleEndian=*/true); + return createELFObjectWriter(MOTW, OS, /*IsLittleEndian=*/false); } From stpworld at narod.ru Thu Dec 22 12:48:11 2011 From: stpworld at narod.ru (Stepan Dyatkovskiy) Date: Thu, 22 Dec 2011 22:48:11 +0400 Subject: [llvm-commits] [LLVM, SwitchInst, case ranges] Auxiliary patch #1 In-Reply-To: <4EEB9C52.1050301@narod.ru> References: <4EAA9B5D.802@narod.ru> <4EAA9DE8.80000@free.fr> <485181319805488@web67.yandex.ru> <4EAB079D.6000606@free.fr> <4EB18F12.6060409@narod.ru> <4EB7C319.1000709@narod.ru> <4EDE7D75.704@narod.ru> <4EDFD0F4.1040204@narod.ru> <4EE25B61.9070006@narod.ru> <4EE5C06C.3050705@narod.ru> <333531323974498@web57.yandex.ru> <4EEB9C52.1050301@narod.ru> Message-ID: <4EF37B6B.6000205@narod.ru> Ping. Stepan Dyatkovskiy wrote: > Ping. > > -Stepan. From klimek at google.com Thu Dec 22 13:07:22 2011 From: klimek at google.com (Manuel Klimek) Date: Thu, 22 Dec 2011 20:07:22 +0100 Subject: [llvm-commits] [PATCH] Removes most of the templating from the JSON parser In-Reply-To: References: Message-ID: On Thu, Dec 22, 2011 at 7:25 PM, Chris Lattner wrote: > > On Dec 22, 2011, at 6:55 AM, Manuel Klimek wrote: > >> I'm happy to apply this if people feel like this improves the >> situation. I'm not sure it does, though, which is why I'd like to get >> comments on it first. Better? Worse? The same? Ideas how to make it >> better? >> >> Rietveld: http://codereview.appspot.com/5504072 > > I think that this is a lot better. ?An improvement would be to keep some of the trivial methods (e.g. AtomIterator::AtomIterator) inline, which IMO makes things easier to read, and is probably better for performance. It does not matter for the performance cases I benchmark at all (they're pretty much parseString bound), but I'll happily inline the trivial stuff (I outlined mainly because of your comment :). Will check that in then. Thanks for your review! /Manuel From grosbach at apple.com Thu Dec 22 13:20:45 2011 From: grosbach at apple.com (Jim Grosbach) Date: Thu, 22 Dec 2011 19:20:45 -0000 Subject: [llvm-commits] [llvm] r147158 - in /llvm/trunk/lib/Target/ARM: ARMInstrVFP.td AsmParser/ARMAsmParser.cpp Message-ID: <20111222192045.EA1442A6C12C@llvm.org> Author: grosbach Date: Thu Dec 22 13:20:45 2011 New Revision: 147158 URL: http://llvm.org/viewvc/llvm-project?rev=147158&view=rev Log: ARM pre-UAL aliases. fcmp[sd]. Modified: llvm/trunk/lib/Target/ARM/ARMInstrVFP.td llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Modified: llvm/trunk/lib/Target/ARM/ARMInstrVFP.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrVFP.td?rev=147158&r1=147157&r2=147158&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrVFP.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrVFP.td Thu Dec 22 13:20:45 2011 @@ -1197,6 +1197,8 @@ def : VFP2MnemonicAlias<"fmacs", "vmla.f32">; def : VFP2MnemonicAlias<"fcpys", "vmov.f32">; def : VFP2MnemonicAlias<"fcpyd", "vmov.f64">; +def : VFP2MnemonicAlias<"fcmps", "vcmp.f32">; +def : VFP2MnemonicAlias<"fcmpd", "vcmp.f64">; def : VFP2MnemonicAlias<"fdivs", "vdiv.f32">; def : VFP2MnemonicAlias<"fdivd", "vdiv.f64">; Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp?rev=147158&r1=147157&r2=147158&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp (original) +++ llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Thu Dec 22 13:20:45 2011 @@ -4508,7 +4508,7 @@ Mnemonic == "vrsqrts" || Mnemonic == "srs" || Mnemonic == "flds" || Mnemonic == "fmrs" || Mnemonic == "fsqrts" || Mnemonic == "fsubs" || Mnemonic == "fsts" || Mnemonic == "fcpys" || Mnemonic == "fdivs" || - Mnemonic == "fmuls" || + Mnemonic == "fmuls" || Mnemonic == "fcmps" || (Mnemonic == "movs" && isThumb()))) { Mnemonic = Mnemonic.slice(0, Mnemonic.size() - 1); CarrySetting = true; From sabre at nondot.org Thu Dec 22 13:20:52 2011 From: sabre at nondot.org (Chris Lattner) Date: Thu, 22 Dec 2011 19:20:52 -0000 Subject: [llvm-commits] [llvm] r147159 - /llvm/trunk/include/llvm/Type.h Message-ID: <20111222192052.212372A6C12C@llvm.org> Author: lattner Date: Thu Dec 22 13:20:51 2011 New Revision: 147159 URL: http://llvm.org/viewvc/llvm-project?rev=147159&view=rev Log: fix typo Modified: llvm/trunk/include/llvm/Type.h Modified: llvm/trunk/include/llvm/Type.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Type.h?rev=147159&r1=147158&r2=147159&view=diff ============================================================================== --- llvm/trunk/include/llvm/Type.h (original) +++ llvm/trunk/include/llvm/Type.h Thu Dec 22 13:20:51 2011 @@ -47,7 +47,7 @@ enum TypeID { // PrimitiveTypes - make sure LastPrimitiveTyID stays up to date. VoidTyID = 0, ///< 0: type with no size - HalfTyID, ///< 1: 32-bit floating point type + HalfTyID, ///< 1: 16-bit floating point type FloatTyID, ///< 2: 32-bit floating point type DoubleTyID, ///< 3: 64-bit floating point type X86_FP80TyID, ///< 4: 80-bit floating point type (X87) From daniel at zuster.org Thu Dec 22 13:24:11 2011 From: daniel at zuster.org (Daniel Dunbar) Date: Thu, 22 Dec 2011 19:24:11 -0000 Subject: [llvm-commits] [zorg] r147161 - /zorg/trunk/lnt/lnt/server/db/testsuitedb.py Message-ID: <20111222192411.5F6C32A6C12C@llvm.org> Author: ddunbar Date: Thu Dec 22 13:24:11 2011 New Revision: 147161 URL: http://llvm.org/viewvc/llvm-project?rev=147161&view=rev Log: [lnt/v0.4]: lnt.server.db.testsuitedb: Fix a bug in reassignment of Order ordinals. - We could end up presenting non-unique ordinal values to the DB because of how SA flushing works. - The current solution for this problem is really horrible, but I'd rather figure out how to fix it once I have good test cases for the (performance) problem. Modified: zorg/trunk/lnt/lnt/server/db/testsuitedb.py Modified: zorg/trunk/lnt/lnt/server/db/testsuitedb.py URL: http://llvm.org/viewvc/llvm-project/zorg/trunk/lnt/lnt/server/db/testsuitedb.py?rev=147161&r1=147160&r2=147161&view=diff ============================================================================== --- zorg/trunk/lnt/lnt/server/db/testsuitedb.py (original) +++ zorg/trunk/lnt/lnt/server/db/testsuitedb.py Thu Dec 22 13:24:11 2011 @@ -392,11 +392,23 @@ orders.sort() # Assign ordinals. - for i,o in enumerate(orders): + # + # We iterate in reverse order to guarantee that we do not create + # unique conflicts. + for i in range(len(orders)-1,-1,-1): # FIXME: Figure out whether or not SA checks modified status on # write or on value change. + o = orders[i] if o.ordinal != i: o.ordinal = i + # We have to flush now in order to assure that SA will not + # present non-unique values to the database. + # + # FIXME: This is really horrible from a performance point of + # view. If we can't figure out how to get SA to do a batch + # update then we should write the SQL query to do the update + # directly. + self.v4db.session.flush() # Finally, add the new order. self.add(order) From daniel at zuster.org Thu Dec 22 13:24:15 2011 From: daniel at zuster.org (Daniel Dunbar) Date: Thu, 22 Dec 2011 19:24:15 -0000 Subject: [llvm-commits] [zorg] r147162 - in /zorg/trunk/lnt/lnt/server: db/testsuitedb.py ui/views.py Message-ID: <20111222192415.F10CA2A6C12C@llvm.org> Author: ddunbar Date: Thu Dec 22 13:24:15 2011 New Revision: 147162 URL: http://llvm.org/viewvc/llvm-project?rev=147162&view=rev Log: [lnt/v0.4]: lnt.server.db.testsuitedb: Move get_adjacent_runs_on_machine onto TestSuiteDB. Modified: zorg/trunk/lnt/lnt/server/db/testsuitedb.py zorg/trunk/lnt/lnt/server/ui/views.py Modified: zorg/trunk/lnt/lnt/server/db/testsuitedb.py URL: http://llvm.org/viewvc/llvm-project/zorg/trunk/lnt/lnt/server/db/testsuitedb.py?rev=147162&r1=147161&r2=147162&view=diff ============================================================================== --- zorg/trunk/lnt/lnt/server/db/testsuitedb.py (original) +++ zorg/trunk/lnt/lnt/server/db/testsuitedb.py Thu Dec 22 13:24:15 2011 @@ -571,3 +571,49 @@ def getRun(self, id): return self.query(self.Run).filter_by(id=id).one() + + def get_adjacent_runs_on_machine(self, run, N, direction = -1): + """ + get_adjacent_runs_on_machine(run, N, direction = -1) -> [Run*] + + Return the N runs which have been submitted to the same machine and are + adjacent to the given run. + + The actual number of runs returned may be greater than N in situations + where multiple reports were received for the same order. + + The runs will be reported starting with the runs closest to the given + run's order. + + The direction must be -1 or 1 and specified whether or not the + preceeding or following runs should be returned. + """ + assert direction in (-1, 1), "invalid direction" + + ordinal = run.order.ordinal + direction + # FIXME: This probably isn't a great way to limit our search, at least + # for SQLite which can't answer this quickly. + last_ordinal = self.query(self.Order).count() + while 0 <= ordinal <= last_ordinal and N > 0: + # Find all the runs on this machine for the current ordinal. + found_any = False + for item in self.query(self.Run).\ + join(self.Order).\ + filter(self.Order.ordinal == ordinal).\ + filter(self.Run.machine == run.machine): + yield item + found_any = True + + # If we found any, decrement the number of orders remaining to find + # runs for. + if found_any: + N -= 1 + + # Update the ordinal we are searching for runs for. + ordinal += direction + + def get_previous_runs_on_machine(self, run, N): + return self.get_adjacent_runs_on_machine(run, N, direction = -1) + + def get_next_runs_on_machine(self, run, N): + return self.get_adjacent_runs_on_machine(run, N, direction = 1) Modified: zorg/trunk/lnt/lnt/server/ui/views.py URL: http://llvm.org/viewvc/llvm-project/zorg/trunk/lnt/lnt/server/ui/views.py?rev=147162&r1=147161&r2=147162&view=diff ============================================================================== --- zorg/trunk/lnt/lnt/server/ui/views.py (original) +++ zorg/trunk/lnt/lnt/server/ui/views.py Thu Dec 22 13:24:15 2011 @@ -638,34 +638,6 @@ testsuite_name=g.testsuite_name, id=id, associated_runs=associated_runs) -def get_adjacent_runs_on_machine(ts, run, N): - prev_runs = [] - ordinal = run.order.ordinal - 1 - while ordinal >= 0 and (len(prev_runs) < N or - run.order.ordinal - ordinal < N): - # Find all the runs on this machine from the previous order. - prev_runs.extend(ts.query(ts.Run).\ - join(ts.Order).\ - filter(ts.Order.ordinal == ordinal).\ - filter(ts.Run.machine == run.machine)) - ordinal = ordinal - 1 - - next_runs = [] - ordinal = run.order.ordinal + 1 - # FIXME: This probably isn't a great way to limit our search, at least for - # SQLite which can't answer this quickly. - last_ordinal = ts.query(ts.Order).count() - while ordinal != last_ordinal and (len(next_runs) < N or - ordinal - run.order.ordinal < N): - # Find all the runs on this machine from the next order. - next_runs.extend(ts.query(ts.Run).\ - join(ts.Order).\ - filter(ts.Order.ordinal == ordinal).\ - filter(ts.Run.machine == run.machine)) - ordinal = ordinal + 1 - - return next_runs[::-1] + [run] + prev_runs - @v4_route("//report") def v4_report(id): db = request.get_db() @@ -699,7 +671,9 @@ run = ts.getRun(id) # Find the neighboring runs, by order. - neighboring_runs = get_adjacent_runs_on_machine(ts, run, N = 3) + prev_runs = list(ts.get_previous_runs_on_machine(run, N = 3)) + next_runs = list(ts.get_next_runs_on_machine(run, N = 3)) + neighboring_runs = next_runs[::-1] + [run] + prev_runs # Parse the view options. options = {} From daniel at zuster.org Thu Dec 22 13:24:21 2011 From: daniel at zuster.org (Daniel Dunbar) Date: Thu, 22 Dec 2011 19:24:21 -0000 Subject: [llvm-commits] [zorg] r147163 - in /zorg/trunk/lnt/lnt: server/db/testsuitedb.py server/reporting/ server/reporting/__init__.py server/reporting/runs.py server/ui/views.py util/NTEmailReport.py Message-ID: <20111222192421.CB9BD2A6C12C@llvm.org> Author: ddunbar Date: Thu Dec 22 13:24:21 2011 New Revision: 147163 URL: http://llvm.org/viewvc/llvm-project?rev=147163&view=rev Log: [lnt/v0.4] lnt.server.reporting: Start defining V4 report implementation. Added: zorg/trunk/lnt/lnt/server/reporting/ zorg/trunk/lnt/lnt/server/reporting/__init__.py zorg/trunk/lnt/lnt/server/reporting/runs.py Modified: zorg/trunk/lnt/lnt/server/db/testsuitedb.py zorg/trunk/lnt/lnt/server/ui/views.py zorg/trunk/lnt/lnt/util/NTEmailReport.py Modified: zorg/trunk/lnt/lnt/server/db/testsuitedb.py URL: http://llvm.org/viewvc/llvm-project/zorg/trunk/lnt/lnt/server/db/testsuitedb.py?rev=147163&r1=147162&r2=147163&view=diff ============================================================================== --- zorg/trunk/lnt/lnt/server/db/testsuitedb.py (original) +++ zorg/trunk/lnt/lnt/server/db/testsuitedb.py Thu Dec 22 13:24:21 2011 @@ -40,6 +40,14 @@ # Create parameterized model classes for this test suite. class ParameterizedMixin(object): + # Class variable to allow finding the associated test suite from + # model instances. + testsuite = self + + # Class variable (expected to be defined by subclasses) to allow + # easy access to the field list for parameterized model classes. + fields = None + def get_field(self, field): return getattr(self, field.name) Added: zorg/trunk/lnt/lnt/server/reporting/__init__.py URL: http://llvm.org/viewvc/llvm-project/zorg/trunk/lnt/lnt/server/reporting/__init__.py?rev=147163&view=auto ============================================================================== --- zorg/trunk/lnt/lnt/server/reporting/__init__.py (added) +++ zorg/trunk/lnt/lnt/server/reporting/__init__.py Thu Dec 22 13:24:21 2011 @@ -0,0 +1 @@ +__all__ = [] Added: zorg/trunk/lnt/lnt/server/reporting/runs.py URL: http://llvm.org/viewvc/llvm-project/zorg/trunk/lnt/lnt/server/reporting/runs.py?rev=147163&view=auto ============================================================================== --- zorg/trunk/lnt/lnt/server/reporting/runs.py (added) +++ zorg/trunk/lnt/lnt/server/reporting/runs.py Thu Dec 22 13:24:21 2011 @@ -0,0 +1,132 @@ +""" +Report functionality centered around individual runs. +""" + +import StringIO +import os + +def generate_run_report(run, baseurl, only_html_body = False, + num_comparison_runs = 10): + """ + generate_run_report(...) -> (str: subject, str: text_report, + str: html_report) + + Generate a comprehensive report on the results of the given individual + run, suitable for emailing or presentation on a web page. + """ + + assert num_comparison_runs > 0 + + + ts = run.testsuite + machine = run.machine + machine_parameters = machine.parameters + + # Gather the runs to use for statistical data. + comparison_window = list(ts.get_previous_runs_on_machine( + run, num_comparison_runs)) + + # Get the specific run to compare to. + if comparison_window: + compare_to = comparison_window[0] + else: + compare_to = None + + # Begin report generation... + subject = """%s test results: %s""" % ( + machine.name, run.start_time.strftime('%Y-%m-%d %H:%M:%S %Z PST')) + report = StringIO.StringIO() + html_report = StringIO.StringIO() + + # Generate the report header. + if baseurl[-1] == '/': + baseurl = baseurl[:-1] + + report_url = """%s/%d/""" % (baseurl, run.id) + print >>report, report_url + print >>report, """Nickname: %s:%d""" % (machine.name, machine.id) + if 'name' in machine_parameters: + print >>report, """Name: %s""" % (machine_parameters['name'],) + print >>report, """Comparing:""" + # FIXME: Remove hard coded field use here. + print >>report, """ Run: %d, Order: %s, Start Time: %s, End Time: %s""" % ( + run.id, run.order.llvm_project_revision, run.start_time, run.end_time) + if compare_to: + # FIXME: Remove hard coded field use here. + print >>report, (""" To: %d, Order: %s, """ + """Start Time: %s, End Time: %s""") % ( + compare_to.id, compare_to.order.llvm_project_revision, + compare_to.start_time, compare_to.end_time) + if run.machine != compare_to.machine: + print >>report, """*** WARNING ***:""", + print >>report, """comparison is against a different machine""", + print >>report, """(%s:%d)""" % (compare_to.machine.name, + compare_to.machine.id) + else: + print >>report, """ To: (none)""" + print >>report + + # Generate the HTML report header. + print >>html_report, """\ +

%s

+""" % subject + print >>html_report, """\ +""" % (report_url, report_url) + print >>html_report, "" % ( + machine.name, machine.id) + if 'name' in machine_parameters: + print >>html_report, """""" % ( + machine_parameters['name'],) + print >>html_report, """

URL	%s
Nickname	%s:%d
Name	%s

""" + print >>html_report, """\ +

+ + + + + + + + """ + # FIXME: Remove hard coded field use here. + print >>html_report, """\ +""" % ( + run.id, run.order.llvm_project_revision, run.start_time, run.end_time) + if compare_to: + # FIXME: Remove hard coded field use here. + print >>html_report, """\ +""" % ( + compare_to.id, compare_to.order.llvm_project_revision, + compare_to.start_time, compare_to.end_time) + else: + print >>html_report, """""" + print >>html_report, """
Run ID Order Start Time End Time
Current %d %s %s %s
Previous %d %s %s %s
No Previous Run
""" + if compare_to and run.machine != compare_to.machine: + print >>html_report, """

Run	ID	Order	Start Time	End Time
Current	%d	%s	%s	%s
Previous	%d	%s	%s	%s
No Previous Run

*** WARNING ***:""", + print >>html_report, """comparison is against a different machine""", + print >>html_report, """(%s:%d)

""" % (compare_to.machine.name, compare_to.machine.id) + # Generate the summary of the changes. + total_changes = sum(len(bucket) + for _,field_results in test_results + for name,bucket,_ in field_results + if name != 'Unchanged Tests') + + print >>report, """===============""" + print >>report, """Tests Summary""" + print >>report, """===============""" + print >>report + print >>html_report, """ +

Tests Summary

+ + +""" + # For now, we aggregate across all bucket types for reports. + for i,(name,_,_) in enumerate(test_results[0][1]): + num_items = sum(len(field_results[i][1]) + for _,field_results in test_results) + if num_items: + print >>report, '%s: %d' % (name, num_items) + print >>html_report, """ +""" % ( + name, num_items) + print >>report, """Total Tests: %d""" % num_total_tests + print >>report + print >>html_report, """ + + + +

Status Group	#
%s	%d
Total Tests	%d

+""" % num_total_tests + + # Finish up the HTML report (wrapping the body, if necessary). html_report = html_report.getvalue() if not only_html_body: # We embed the additional resources, so that the message is self @@ -116,7 +218,7 @@ style_css = open(os.path.join(static_path, "style.css")).read() - html_report = """ + html_report = """\