From chandlerc at google.com Mon Jan 2 00:14:40 2012 From: chandlerc at google.com (Chandler Carruth) Date: Sun, 1 Jan 2012 22:14:40 -0800 Subject: [llvm-commits] [pr11677][patch] Eagerly materialize functions whose BBs are used in global variables inits In-Reply-To: <4EFF24CB.2020407@gmail.com> References: <4EFEA724.3090104@gmail.com> <4EFF24CB.2020407@gmail.com> Message-ID: This looks fine to me... A couple of minor points: - Can you add some comments describing the iterator invalidation issues that motivated this design? - I think the unit test needs the boiler plate comment block at the top. - I'd name the test itself after the PR number rather than putting it in a comment (which is likely to not stay attached). -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20120101/845de247/attachment.html From rafael.espindola at gmail.com Mon Jan 2 01:49:53 2012 From: rafael.espindola at gmail.com (Rafael Espindola) Date: Mon, 02 Jan 2012 07:49:53 -0000 Subject: [llvm-commits] [llvm] r147425 - in /llvm/trunk: lib/Bitcode/Reader/BitcodeReader.cpp lib/Bitcode/Reader/BitcodeReader.h unittests/CMakeLists.txt unittests/VMCore/pr11677.cpp Message-ID: <20120102074953.9494E2A6C12C@llvm.org> Author: rafael Date: Mon Jan 2 01:49:53 2012 New Revision: 147425 URL: http://llvm.org/viewvc/llvm-project?rev=147425&view=rev Log: Materialize functions whose basic blocks are used by global variables. Fixes PR11677. Added: llvm/trunk/unittests/VMCore/pr11677.cpp Modified: llvm/trunk/lib/Bitcode/Reader/BitcodeReader.cpp llvm/trunk/lib/Bitcode/Reader/BitcodeReader.h llvm/trunk/unittests/CMakeLists.txt Modified: llvm/trunk/lib/Bitcode/Reader/BitcodeReader.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Bitcode/Reader/BitcodeReader.cpp?rev=147425&r1=147424&r2=147425&view=diff ============================================================================== --- llvm/trunk/lib/Bitcode/Reader/BitcodeReader.cpp (original) +++ llvm/trunk/lib/Bitcode/Reader/BitcodeReader.cpp Mon Jan 2 01:49:53 2012 @@ -27,6 +27,13 @@ #include "llvm/OperandTraits.h" using namespace llvm; +void BitcodeReader::materializeForwardReferencedFunctions() { + while (!BlockAddrFwdRefs.empty()) { + Function *F = BlockAddrFwdRefs.begin()->first; + F->Materialize(); + } +} + void BitcodeReader::FreeState() { if (BufferOwned) delete Buffer; @@ -2779,6 +2786,9 @@ } // Have the BitcodeReader dtor delete 'Buffer'. R->setBufferOwned(true); + + R->materializeForwardReferencedFunctions(); + return M; } Modified: llvm/trunk/lib/Bitcode/Reader/BitcodeReader.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Bitcode/Reader/BitcodeReader.h?rev=147425&r1=147424&r2=147425&view=diff ============================================================================== --- llvm/trunk/lib/Bitcode/Reader/BitcodeReader.h (original) +++ llvm/trunk/lib/Bitcode/Reader/BitcodeReader.h Mon Jan 2 01:49:53 2012 @@ -184,7 +184,9 @@ ~BitcodeReader() { FreeState(); } - + + void materializeForwardReferencedFunctions(); + void FreeState(); /// setBufferOwned - If this is true, the reader will destroy the MemoryBuffer Modified: llvm/trunk/unittests/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/unittests/CMakeLists.txt?rev=147425&r1=147424&r2=147425&view=diff ============================================================================== --- llvm/trunk/unittests/CMakeLists.txt (original) +++ llvm/trunk/unittests/CMakeLists.txt Mon Jan 2 01:49:53 2012 @@ -112,6 +112,7 @@ VMCore/PassManagerTest.cpp VMCore/ValueMapTest.cpp VMCore/VerifierTest.cpp + VMCore/pr11677.cpp ) # MSVC9 and 8 cannot compile ValueMapTest.cpp due to their bug. Added: llvm/trunk/unittests/VMCore/pr11677.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/unittests/VMCore/pr11677.cpp?rev=147425&view=auto ============================================================================== --- llvm/trunk/unittests/VMCore/pr11677.cpp (added) +++ llvm/trunk/unittests/VMCore/pr11677.cpp Mon Jan 2 01:49:53 2012 @@ -0,0 +1,64 @@ +//===- llvm/unittest/VMCore/pr11677.cpp - Test for blockaddr --------------===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// + +#include "llvm/Analysis/Verifier.h" +#include "llvm/Bitcode/BitstreamWriter.h" +#include "llvm/Bitcode/ReaderWriter.h" +#include "llvm/Constants.h" +#include "llvm/Instructions.h" +#include "llvm/LLVMContext.h" +#include "llvm/Module.h" +#include "llvm/PassManager.h" +#include "llvm/Support/MemoryBuffer.h" +#include "gtest/gtest.h" + +namespace llvm { +namespace { + +static Module *makeLLVMModule() { + Module* Mod = new Module("test-mem", getGlobalContext()); + + FunctionType* FuncTy = + FunctionType::get(Type::getVoidTy(Mod->getContext()), false); + Function* Func = Function::Create(FuncTy,GlobalValue::ExternalLinkage, + "func", Mod); + + BasicBlock* Entry = BasicBlock::Create(Mod->getContext(), "entry", Func); + new UnreachableInst(Mod->getContext(), Entry); + + BasicBlock* BB = BasicBlock::Create(Mod->getContext(), "bb", Func); + new UnreachableInst(Mod->getContext(), BB); + + PointerType* Int8Ptr = Type::getInt8PtrTy(Mod->getContext()); + new GlobalVariable(*Mod, Int8Ptr, /*isConstant=*/true, + GlobalValue::ExternalLinkage, + BlockAddress::get(BB), "table"); + + return Mod; +} + +static void writeModuleToBuffer(std::vector &Buffer) { + Module *Mod = makeLLVMModule(); + BitstreamWriter Stream(Buffer); + WriteBitcodeToStream(Mod, Stream); +} + +TEST(PR11677, BlockAddr) { + std::vector Mem; + writeModuleToBuffer(Mem); + StringRef Data((const char*)&Mem[0], Mem.size()); + MemoryBuffer *Buffer = MemoryBuffer::getMemBuffer(Data, "test", false); + std::string errMsg; + Module *m = getLazyBitcodeModule(Buffer, getGlobalContext(), &errMsg); + PassManager passes; + passes.add(createVerifierPass()); + passes.run(*m); +} +} +} From nadav.rotem at intel.com Mon Jan 2 02:05:47 2012 From: nadav.rotem at intel.com (Nadav Rotem) Date: Mon, 02 Jan 2012 08:05:47 -0000 Subject: [llvm-commits] [llvm] r147426 - in /llvm/trunk: lib/Target/X86/X86ISelLowering.cpp test/CodeGen/X86/2011-12-28-vselecti8.ll test/CodeGen/X86/sext-blend.ll test/CodeGen/X86/sse2-blend.ll test/CodeGen/X86/sse41-blend.ll Message-ID: <20120102080547.693982A6C12C@llvm.org> Author: nadav Date: Mon Jan 2 02:05:46 2012 New Revision: 147426 URL: http://llvm.org/viewvc/llvm-project?rev=147426&view=rev Log: Optimize the sequence blend(sign_extend(x)) to blend(shl(x)) since SSE blend instructions only look at the highest bit. Added: llvm/trunk/test/CodeGen/X86/sext-blend.ll Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp llvm/trunk/test/CodeGen/X86/2011-12-28-vselecti8.ll llvm/trunk/test/CodeGen/X86/sse2-blend.ll llvm/trunk/test/CodeGen/X86/sse41-blend.ll Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=147426&r1=147425&r2=147426&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original) +++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Mon Jan 2 02:05:46 2012 @@ -13133,6 +13133,24 @@ } } + // The VSELECT instruction is lowered to SSE blend instructions. In many cases + // the mask is sign-extended to fill the entire lane. However, we only care + // for the highest bit. Convert sign_extend to srl because it is cheaper. + // (vselect(sign_extend(x))) -> vselect(srl(x)) + if (N->getOpcode() == ISD::VSELECT && + Cond.getOpcode() == ISD::SIGN_EXTEND_INREG && Cond.hasOneUse()) { + EVT CondVT = Cond.getValueType(); + EVT SExtTy = cast(Cond.getOperand(1))->getVT(); + unsigned BitsDiff = CondVT.getScalarType().getSizeInBits() - + SExtTy.getScalarType().getSizeInBits(); + + EVT ShiftType = EVT::getVectorVT(*DAG.getContext(), + MVT::i32, CondVT.getVectorNumElements()); + SDValue SHL = DAG.getNode(ISD::SHL, DL, CondVT, Cond.getOperand(0), + DAG.getConstant(BitsDiff, ShiftType)); + return DAG.getNode(ISD::VSELECT, DL, VT, SHL, LHS, RHS); + } + return SDValue(); } Modified: llvm/trunk/test/CodeGen/X86/2011-12-28-vselecti8.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2011-12-28-vselecti8.ll?rev=147426&r1=147425&r2=147426&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/X86/2011-12-28-vselecti8.ll (original) +++ llvm/trunk/test/CodeGen/X86/2011-12-28-vselecti8.ll Mon Jan 2 02:05:46 2012 @@ -5,8 +5,10 @@ ; CHECK: @foo8 ; CHECK: psll -; CHECK: psraw -; CHECK: pblendvb +; CHECK-NOT: sra +; CHECK: pandn +; CHECK: pand +; CHECK: or ; CHECK: ret define void @foo8(float* nocapture %RET) nounwind { allocas: Added: llvm/trunk/test/CodeGen/X86/sext-blend.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/sext-blend.ll?rev=147426&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/X86/sext-blend.ll (added) +++ llvm/trunk/test/CodeGen/X86/sext-blend.ll Mon Jan 2 02:05:46 2012 @@ -0,0 +1,15 @@ +; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=corei7 -promote-elements -mattr=+sse41 | FileCheck %s + +; CHECK: foo +define <4 x double> @foo(<4 x double> %x, <4 x double> %y) { + ; CHECK: cmpnlepd + ; CHECK: psllq + ; CHECK-NEXT: blendvpd + ; CHECK: psllq + ; CHECK-NEXT: blendvpd + ; CHECK: ret + %min_is_x = fcmp ult <4 x double> %x, %y + %min = select <4 x i1> %min_is_x, <4 x double> %x, <4 x double> %y + ret <4 x double> %min +} + Modified: llvm/trunk/test/CodeGen/X86/sse2-blend.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/sse2-blend.ll?rev=147426&r1=147425&r2=147426&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/X86/sse2-blend.ll (original) +++ llvm/trunk/test/CodeGen/X86/sse2-blend.ll Mon Jan 2 02:05:46 2012 @@ -28,10 +28,10 @@ ; Without forcing instructions, fall back to the preferred PS domain. ; CHECK: vsel_i64 -; CHECK: xorps -; CHECK: andps -; CHECK: andnps -; CHECK: orps +; CHECK: pxor +; CHECK: and +; CHECK: andn +; CHECK: or ; CHECK: ret define void at vsel_i64(<4 x i64>* %v1, <4 x i64>* %v2) { @@ -44,10 +44,10 @@ ; Without forcing instructions, fall back to the preferred PS domain. ; CHECK: vsel_double -; CHECK: xorps -; CHECK: andps -; CHECK: andnps -; CHECK: orps +; CHECK: xor +; CHECK: and +; CHECK: andn +; CHECK: or ; CHECK: ret define void at vsel_double(<4 x double>* %v1, <4 x double>* %v2) { Modified: llvm/trunk/test/CodeGen/X86/sse41-blend.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/sse41-blend.ll?rev=147426&r1=147425&r2=147426&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/X86/sse41-blend.ll (original) +++ llvm/trunk/test/CodeGen/X86/sse41-blend.ll Mon Jan 2 02:05:46 2012 @@ -36,6 +36,7 @@ ;CHECK: vsel_double +;CHECK-NOT: sra ;CHECK: blendvpd ;CHECK: ret define <4 x double> @vsel_double(<4 x double> %v1, <4 x double> %v2) { @@ -54,6 +55,7 @@ ;CHECK: vsel_i8 +;CHECK-NOT: sra ;CHECK: pblendvb ;CHECK: ret define <16 x i8> @vsel_i8(<16 x i8> %v1, <16 x i8> %v2) { @@ -65,6 +67,7 @@ ; CHECK: A define <2 x double> @A(<2 x double> %x, <2 x double> %y) { ; CHECK: cmplepd + ; CHECK-NOT: sra ; CHECK: blendvpd %max_is_x = fcmp oge <2 x double> %x, %y %max = select <2 x i1> %max_is_x, <2 x double> %x, <2 x double> %y @@ -74,6 +77,7 @@ ; CHECK: B define <2 x double> @B(<2 x double> %x, <2 x double> %y) { ; CHECK: cmpnlepd + ; CHECK-NOT: sra ; CHECK: blendvpd %min_is_x = fcmp ult <2 x double> %x, %y %min = select <2 x i1> %min_is_x, <2 x double> %x, <2 x double> %y From elena.demikhovsky at intel.com Mon Jan 2 02:18:18 2012 From: elena.demikhovsky at intel.com (Demikhovsky, Elena) Date: Mon, 2 Jan 2012 08:18:18 +0000 Subject: [llvm-commits] X86SSELevel for AVX architecture In-Reply-To: References: Message-ID: I think that ?HasAVX? should always cover ?HasSSE42? and ?HasSSE42orAVX? is redundant in this case. And ?HasAVX2? will cover ?HasAVX?. I propose to change in X86Subtarget constructor from: if (HasAVX) X86SSELevel = NoMMXSSE; to if (HasAVX) X86SSELevel = SSE42; - Elena From: llvm-commits-bounces at cs.uiuc.edu [mailto:llvm-commits-bounces at cs.uiuc.edu] On Behalf Of Craig Topper Sent: Sunday, January 01, 2012 21:56 To: Umansky, Victor Cc: llvm-commits at cs.uiuc.edu Subject: Re: [llvm-commits] X86SSELevel for AVX architecture Missed the CRC32 instructions. They have now been fixed in r147411. On Sun, Jan 1, 2012 at 1:44 PM, Craig Topper > wrote: Fixed sfence, mfence, lfence, clflush, monitor, and mwait in r147409. On Sun, Jan 1, 2012 at 1:06 PM, Craig Topper > wrote: This is similar to the fix for the prefetch instruction in r146163. I think the fence instructions and clflush are similarly broken. I'll see if I can find any others and I'll commit a fix. On Sun, Jan 1, 2012 at 10:18 AM, Umansky, Victor > wrote: Hi Evan, I noticed that in X86Subtarget constructor you set ?X86SSELevel? member of the class as ?NoMMXSSE? in the case when HasAVX member is set to ?true?. Effectively that invalidates SSE features for AVX architecture - because hasSSEn() accessors return ?false? when HasAVXn() is ?true?. I wonder whether this is the behavior which you?d like to enforce ? as conceptually AVX architecture complements SSE rather than replaces it completely. I noticed this problem after discovering that LLVM fails to lower ?sse2.fence? intrinsic when generating a code for AVX architecture ? because this intrinsic is conditioned on hasSSE2() being ?true?. Is that case was somehow missed from regression testing, or there is another way to lower that intrinsic? I?d appreciate your clarifications. Best Regards, Victor Umansky --------------------------------------------------------------------- Intel Israel (74) Limited This e-mail and any attachments may contain confidential material for the sole use of the intended recipient(s). Any review or distribution by others is strictly prohibited. If you are not the intended recipient, please contact the sender and delete all copies. _______________________________________________ llvm-commits mailing list llvm-commits at cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits -- ~Craig -- ~Craig -- ~Craig --------------------------------------------------------------------- Intel Israel (74) Limited This e-mail and any attachments may contain confidential material for the sole use of the intended recipient(s). Any review or distribution by others is strictly prohibited. If you are not the intended recipient, please contact the sender and delete all copies. -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20120102/073cacaf/attachment.html From craig.topper at gmail.com Mon Jan 2 02:25:17 2012 From: craig.topper at gmail.com (Craig Topper) Date: Mon, 2 Jan 2012 00:25:17 -0800 Subject: [llvm-commits] X86SSELevel for AVX architecture In-Reply-To: References: Message-ID: The instruction selection patterns are not ordered correctly to prefer AVX version of instructions over SSE versions. So until the patterns are properly ordered or we make the HasSSE functions specifically check that AVX is not enabled we can't change the code in X86Subtarget. On Mon, Jan 2, 2012 at 12:18 AM, Demikhovsky, Elena < elena.demikhovsky at intel.com> wrote: > I think that ?HasAVX? should always cover ?HasSSE42? and ?HasSSE42orAVX? > is redundant in this case.**** > > And ?HasAVX2? will cover ?HasAVX?.**** > > I propose to change in X86Subtarget constructor from:**** > > if (HasAVX)**** > > X86SSELevel = NoMMXSSE;**** > > ** ** > > to**** > > if (HasAVX)**** > > X86SSELevel = SSE42;**** > > ** ** > > *- Elena***** > > *From:* llvm-commits-bounces at cs.uiuc.edu [mailto: > llvm-commits-bounces at cs.uiuc.edu] *On Behalf Of *Craig Topper > *Sent:* Sunday, January 01, 2012 21:56 > *To:* Umansky, Victor > *Cc:* llvm-commits at cs.uiuc.edu > *Subject:* Re: [llvm-commits] X86SSELevel for AVX architecture**** > > ** ** > > Missed the CRC32 instructions. They have now been fixed in r147411.**** > > On Sun, Jan 1, 2012 at 1:44 PM, Craig Topper > wrote:**** > > Fixed sfence, mfence, lfence, clflush, monitor, and mwait in r147409.**** > > ** ** > > On Sun, Jan 1, 2012 at 1:06 PM, Craig Topper > wrote:**** > > This is similar to the fix for the prefetch instruction in r146163. I > think the fence instructions and clflush are similarly broken. I'll see if > I can find any others and I'll commit a fix.**** > > On Sun, Jan 1, 2012 at 10:18 AM, Umansky, Victor > wrote:**** > > Hi Evan,**** > > **** > > I noticed that in X86Subtarget constructor you set ?X86SSELevel? member > of the class as ?NoMMXSSE? in the case when HasAVX member is set to > ?true?.**** > > Effectively that invalidates SSE features for AVX architecture - because > hasSSEn() accessors return ?false? when HasAVXn() is ?true?.**** > > I wonder whether this is the behavior which you?d like to enforce ? as > conceptually AVX architecture complements SSE rather than replaces it > completely.**** > > **** > > I noticed this problem after discovering that LLVM fails to lower > ?sse2.fence? intrinsic when generating a code for AVX architecture ? > because this intrinsic is conditioned on hasSSE2() being ?true?.**** > > Is that case was somehow missed from regression testing, or there is > another way to lower that intrinsic?**** > > **** > > I?d appreciate your clarifications.**** > > **** > > Best Regards,**** > > Victor Umansky**** > > **** > > --------------------------------------------------------------------- > Intel Israel (74) Limited > > This e-mail and any attachments may contain confidential material for > the sole use of the intended recipient(s). Any review or distribution > by others is strictly prohibited. If you are not the intended > recipient, please contact the sender and delete all copies.**** > > ** ** > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits**** > > > > > -- > ~Craig**** > > > > **** > > -- > ~Craig**** > > > > > -- > ~Craig**** > --------------------------------------------------------------------- > Intel Israel (74) Limited > > This e-mail and any attachments may contain confidential material for > the sole use of the intended recipient(s). Any review or distribution > by others is strictly prohibited. If you are not the intended > recipient, please contact the sender and delete all copies. > -- ~Craig -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20120102/f2452f15/attachment.html From chandlerc at gmail.com Mon Jan 2 02:40:40 2012 From: chandlerc at gmail.com (Chandler Carruth) Date: Mon, 02 Jan 2012 08:40:40 -0000 Subject: [llvm-commits] [llvm] r147427 - /llvm/trunk/unittests/VMCore/Makefile Message-ID: <20120102084041.5B0CF2A6C12D@llvm.org> Author: chandlerc Date: Mon Jan 2 02:40:40 2012 New Revision: 147427 URL: http://llvm.org/viewvc/llvm-project?rev=147427&view=rev Log: Fix unittest makefile after r147425. This should unbreak the makefile build. This didn't show up in the CMake build because the CMake build for the unittests is rather poorly factored. This probably isn't the correct fix. This should be a bitcode reader unittest not a VMCore unittest. I'll move it and clean various parts of the unittest up in a follow-up patch, but I wanted to unbreak the bots. Modified: llvm/trunk/unittests/VMCore/Makefile Modified: llvm/trunk/unittests/VMCore/Makefile URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/unittests/VMCore/Makefile?rev=147427&r1=147426&r2=147427&view=diff ============================================================================== --- llvm/trunk/unittests/VMCore/Makefile (original) +++ llvm/trunk/unittests/VMCore/Makefile Mon Jan 2 02:40:40 2012 @@ -9,7 +9,7 @@ LEVEL = ../.. TESTNAME = VMCore -LINK_COMPONENTS := core support target ipa +LINK_COMPONENTS := core support bitreader bitwriter target ipa include $(LEVEL)/Makefile.config include $(LLVM_SRC_ROOT)/unittests/Makefile.unittest From craig.topper at gmail.com Mon Jan 2 02:46:48 2012 From: craig.topper at gmail.com (Craig Topper) Date: Mon, 02 Jan 2012 08:46:48 -0000 Subject: [llvm-commits] [llvm] r147428 - in /llvm/trunk/lib/Target/X86: X86ISelLowering.cpp X86InstrSSE.td Message-ID: <20120102084652.9BAB72A6C12D@llvm.org> Author: ctopper Date: Mon Jan 2 02:46:48 2012 New Revision: 147428 URL: http://llvm.org/viewvc/llvm-project?rev=147428&view=rev Log: Make CanXFormVExtractWithShuffleIntoLoad reject loads with multiple uses. Also make it return false if there's not even a load at all. This makes the code better match the code in DAGCombiner that it tries to match. These two changes prevent some cases where vector_shuffles were making it to instruction selection and causing the older shuffle selection code to be triggered. Also needed to fix a bad pattern that this change exposed. This is the first step towards getting rid of the old shuffle selection support. No test cases yet because there's no way to tell whether a shuffle was handled in the legalize stage or at instruction selection. Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp llvm/trunk/lib/Target/X86/X86InstrSSE.td Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=147428&r1=147427&r2=147428&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original) +++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Mon Jan 2 02:46:48 2012 @@ -6268,31 +6268,27 @@ if (V.getOpcode() == ISD::BITCAST) V = V.getOperand(0); - if (ISD::isNormalLoad(V.getNode())) { - // Is the original load suitable? - LoadSDNode *LN0 = cast(V); - - // FIXME: avoid the multi-use bug that is preventing lots of - // of foldings to be detected, this is still wrong of course, but - // give the temporary desired behavior, and if it happens that - // the load has real more uses, during isel it will not fold, and - // will generate poor code. - if (!LN0 || LN0->isVolatile()) // || !LN0->hasOneUse() - return false; + if (!ISD::isNormalLoad(V.getNode())) + return false; - if (!HasShuffleIntoBitcast) - return true; + // Is the original load suitable? + LoadSDNode *LN0 = cast(V); - // If there's a bitcast before the shuffle, check if the load type and - // alignment is valid. - unsigned Align = LN0->getAlignment(); - unsigned NewAlign = - TLI.getTargetData()->getABITypeAlignment( - VT.getTypeForEVT(*DAG.getContext())); + if (!LN0 || !LN0->hasNUsesOfValue(1,0) || LN0->isVolatile()) + return false; - if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, VT)) - return false; - } + if (!HasShuffleIntoBitcast) + return true; + + // If there's a bitcast before the shuffle, check if the load type and + // alignment is valid. + unsigned Align = LN0->getAlignment(); + unsigned NewAlign = + TLI.getTargetData()->getABITypeAlignment( + VT.getTypeForEVT(*DAG.getContext())); + + if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, VT)) + return false; return true; } Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrSSE.td?rev=147428&r1=147427&r2=147428&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86InstrSSE.td (original) +++ llvm/trunk/lib/Target/X86/X86InstrSSE.td Mon Jan 2 02:46:48 2012 @@ -1236,10 +1236,10 @@ // Store patterns def : Pat<(store (f64 (vector_extract - (v2f64 (X86Unpckh VR128:$src, (undef))), (iPTR 0))), addr:$dst), + (v2f64 (X86Unpckh VR128:$src, VR128:$src)), (iPTR 0))), addr:$dst), (VMOVHPSmr addr:$dst, VR128:$src)>; def : Pat<(store (f64 (vector_extract - (v2f64 (X86Unpckh VR128:$src, (undef))), (iPTR 0))), addr:$dst), + (v2f64 (X86Unpckh VR128:$src, VR128:$src)), (iPTR 0))), addr:$dst), (VMOVHPDmr addr:$dst, VR128:$src)>; } @@ -1259,7 +1259,7 @@ // Store patterns def : Pat<(store (f64 (vector_extract - (v2f64 (X86Unpckh VR128:$src, (undef))), (iPTR 0))), addr:$dst), + (v2f64 (X86Unpckh VR128:$src, VR128:$src)), (iPTR 0))), addr:$dst), (MOVHPSmr addr:$dst, VR128:$src)>; } @@ -1279,7 +1279,7 @@ // Store patterns def : Pat<(store (f64 (vector_extract - (v2f64 (X86Unpckh VR128:$src, (undef))), (iPTR 0))),addr:$dst), + (v2f64 (X86Unpckh VR128:$src, VR128:$src)), (iPTR 0))),addr:$dst), (MOVHPDmr addr:$dst, VR128:$src)>; } From baldrick at free.fr Mon Jan 2 02:52:22 2012 From: baldrick at free.fr (Duncan Sands) Date: Mon, 02 Jan 2012 08:52:22 -0000 Subject: [llvm-commits] [dragonegg] r147429 - /dragonegg/trunk/src/Constants.cpp Message-ID: <20120102085222.1789A2A6C12C@llvm.org> Author: baldrick Date: Mon Jan 2 02:52:21 2012 New Revision: 147429 URL: http://llvm.org/viewvc/llvm-project?rev=147429&view=rev Log: If the initializer for a global array is not homogeneous (i.e. not all elements have the same type), it may still be almost homogeneous (i.e. most elements have the same type). This patch teaches the logic to use a ConstantArray for any homogeneous parts, and a ConstantStruct for the rest. This reduces the size of human readable IR files if the homogeneous part is huge, since (eg) printing a 32k array of zeros only takes a few bytes, while printing it as a struct with 32k elements takes megabytes. Modified: dragonegg/trunk/src/Constants.cpp Modified: dragonegg/trunk/src/Constants.cpp URL: http://llvm.org/viewvc/llvm-project/dragonegg/trunk/src/Constants.cpp?rev=147429&r1=147428&r2=147429&view=diff ============================================================================== --- dragonegg/trunk/src/Constants.cpp (original) +++ dragonegg/trunk/src/Constants.cpp Mon Jan 2 02:52:21 2012 @@ -979,20 +979,15 @@ // return a struct instead of an array. This can occur in cases where we have // an array of unions, and the various unions had different parts initialized. // While there, compute the maximum element alignment. - bool UseStruct = false; + bool isHomogeneous = true; Type *ActualEltTy = Elts[0]->getType(); unsigned MaxAlign = TD.getABITypeAlignment(ActualEltTy); for (unsigned i = 1; i != NumElts; ++i) if (Elts[i]->getType() != ActualEltTy) { MaxAlign = std::max(TD.getABITypeAlignment(Elts[i]->getType()), MaxAlign); - UseStruct = true; + isHomogeneous = false; } - // If any elements are more aligned than the GCC type then we need to return a - // packed struct. This can happen if the user forced a small alignment on the - // array type. - bool Pack = MaxAlign * 8 > TYPE_ALIGN(TREE_TYPE(exp)); - // We guarantee that initializers are always at least as big as the LLVM type // for the initializer. If needed, append padding to ensure this. uint64_t TypeSize = TD.getTypeAllocSizeInBits(InitTy); @@ -1001,12 +996,40 @@ assert(PadBits % BITS_PER_UNIT == 0 && "Non-unit type size?"); unsigned Units = PadBits / BITS_PER_UNIT; Elts.push_back(UndefValue::get(GetUnitType(Context, Units))); - UseStruct = true; + isHomogeneous = false; } + // If any elements are more aligned than the GCC type then we need to return a + // packed struct. This can happen if the user forced a small alignment on the + // array type. + if (MaxAlign * 8 > TYPE_ALIGN(TREE_TYPE(exp))) + return ConstantStruct::getAnon(Context, Elts, /*Packed*/true); + // Return as a struct if the contents are not homogeneous. - if (UseStruct || Pack) - return ConstantStruct::getAnon(Context, Elts, Pack); + if (!isHomogeneous) { + std::vector StructElts; + unsigned First = 0, E = Elts.size(); + while (First < E) { + // Find the maximal value of Last s.t. all elements in the range + // [First, Last) have the same type. + Type *Ty = Elts[First]->getType(); + unsigned Last = First + 1; + for (; Last != E; ++Last) + if (Elts[Last]->getType() != Ty) + break; + unsigned NumSameType = Last - First; + Constant *StructElt; + if (NumSameType == 1) + StructElt = Elts[First]; + else + StructElt = ConstantArray::get(ArrayType::get(Ty, NumSameType), + ArrayRef(&Elts[First], + NumSameType)); + StructElts.push_back(StructElt); + First = Last; + } + return ConstantStruct::getAnon(Context, StructElts); + } // Make the IR more pleasant by returning as a vector if the GCC type was a // vector. However this is only correct if the initial values had the same From craig.topper at gmail.com Mon Jan 2 03:17:37 2012 From: craig.topper at gmail.com (Craig Topper) Date: Mon, 02 Jan 2012 09:17:37 -0000 Subject: [llvm-commits] [llvm] r147430 - /llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Message-ID: <20120102091737.A36A31BE003@llvm.org> Author: ctopper Date: Mon Jan 2 03:17:37 2012 New Revision: 147430 URL: http://llvm.org/viewvc/llvm-project?rev=147430&view=rev Log: Miscellaneous shuffle lowering cleanup. No functional changes. Primarily converting the indexing loops to unsigned to be consistent across functions. Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=147430&r1=147429&r2=147430&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original) +++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Mon Jan 2 03:17:37 2012 @@ -3194,12 +3194,11 @@ return false; // Lower quadword copied in order or undef. - for (int i = 0; i != 4; ++i) - if (Mask[i] >= 0 && Mask[i] != i) - return false; + if (!isSequentialOrUndefInRange(Mask, 0, 4, 0)) + return false; // Upper quadword shuffled. - for (int i = 4; i != 8; ++i) + for (unsigned i = 4; i != 8; ++i) if (Mask[i] >= 0 && (Mask[i] < 4 || Mask[i] > 7)) return false; @@ -3219,12 +3218,11 @@ return false; // Upper quadword copied in order. - for (int i = 4; i != 8; ++i) - if (Mask[i] >= 0 && Mask[i] != i) - return false; + if (!isSequentialOrUndefInRange(Mask, 4, 4, 4)) + return false; // Lower quadword shuffled. - for (int i = 0; i != 4; ++i) + for (unsigned i = 0; i != 4; ++i) if (Mask[i] >= 4) return false; @@ -3321,7 +3319,7 @@ // VPERMILPS works with masks. if (NumElems == 4 || l == 0 || Mask[i+QuarterStart] < 0) continue; - if (!isUndefOrEqual(Idx, Mask[i+QuarterStart]+HalfSize)) + if (!isUndefOrEqual(Idx, Mask[i+QuarterStart]+LaneStart)) return false; } } @@ -3332,18 +3330,17 @@ /// getShuffleVSHUFPYImmediate - Return the appropriate immediate to shuffle /// the specified VECTOR_MASK mask with VSHUFPSY/VSHUFPDY instructions. -static unsigned getShuffleVSHUFPYImmediate(SDNode *N) { - ShuffleVectorSDNode *SVOp = cast(N); +static unsigned getShuffleVSHUFPYImmediate(ShuffleVectorSDNode *SVOp) { EVT VT = SVOp->getValueType(0); - int NumElems = VT.getVectorNumElements(); + unsigned NumElems = VT.getVectorNumElements(); assert(VT.getSizeInBits() == 256 && "Only supports 256-bit types"); assert((NumElems == 4 || NumElems == 8) && "Only supports v4 and v8 types"); - int HalfSize = NumElems/2; + unsigned HalfSize = NumElems/2; unsigned Mul = (NumElems == 8) ? 2 : 1; unsigned Mask = 0; - for (int i = 0; i != NumElems; ++i) { + for (unsigned i = 0; i != NumElems; ++i) { int Elt = SVOp->getMaskElt(i); if (Elt < 0) continue; @@ -3672,12 +3669,12 @@ if (VT.getSizeInBits() == 256) return false; - int NumElts = VT.getVectorNumElements(); + unsigned NumElts = VT.getVectorNumElements(); if (!isUndefOrEqual(Mask[0], NumElts)) return false; - for (int i = 1; i < NumElts; ++i) + for (unsigned i = 1; i != NumElts; ++i) if (!isUndefOrEqual(Mask[i], i)) return false; @@ -3704,11 +3701,11 @@ // The shuffle result is divided into half A and half B. In total the two // sources have 4 halves, namely: C, D, E, F. The final values of A and // B must come from C, D, E or F. - int HalfSize = VT.getVectorNumElements()/2; + unsigned HalfSize = VT.getVectorNumElements()/2; bool MatchA = false, MatchB = false; // Check if A comes from one of C, D, E, F. - for (int Half = 0; Half < 4; ++Half) { + for (unsigned Half = 0; Half != 4; ++Half) { if (isSequentialOrUndefInRange(Mask, 0, HalfSize, Half*HalfSize)) { MatchA = true; break; @@ -3716,7 +3713,7 @@ } // Check if B comes from one of C, D, E, F. - for (int Half = 0; Half < 4; ++Half) { + for (unsigned Half = 0; Half != 4; ++Half) { if (isSequentialOrUndefInRange(Mask, HalfSize, HalfSize, Half*HalfSize)) { MatchB = true; break; @@ -3731,16 +3728,16 @@ static unsigned getShuffleVPERM2X128Immediate(ShuffleVectorSDNode *SVOp) { EVT VT = SVOp->getValueType(0); - int HalfSize = VT.getVectorNumElements()/2; + unsigned HalfSize = VT.getVectorNumElements()/2; - int FstHalf = 0, SndHalf = 0; - for (int i = 0; i < HalfSize; ++i) { + unsigned FstHalf = 0, SndHalf = 0; + for (unsigned i = 0; i < HalfSize; ++i) { if (SVOp->getMaskElt(i) > 0) { FstHalf = SVOp->getMaskElt(i)/HalfSize; break; } } - for (int i = HalfSize; i < HalfSize*2; ++i) { + for (unsigned i = HalfSize; i < HalfSize*2; ++i) { if (SVOp->getMaskElt(i) > 0) { SndHalf = SVOp->getMaskElt(i)/HalfSize; break; @@ -3759,20 +3756,19 @@ /// with the same restriction that lanes can't be crossed. static bool isVPERMILPMask(const SmallVectorImpl &Mask, EVT VT, bool HasAVX) { - int NumElts = VT.getVectorNumElements(); - int NumLanes = VT.getSizeInBits()/128; - if (!HasAVX) return false; + unsigned NumElts = VT.getVectorNumElements(); // Only match 256-bit with 32/64-bit types if (VT.getSizeInBits() != 256 || (NumElts != 4 && NumElts != 8)) return false; - int LaneSize = NumElts/NumLanes; - for (int l = 0; l != NumLanes; ++l) { - int LaneStart = l*LaneSize; - for (int i = 0; i != LaneSize; ++i) { + unsigned NumLanes = VT.getSizeInBits()/128; + unsigned LaneSize = NumElts/NumLanes; + for (unsigned l = 0; l != NumLanes; ++l) { + unsigned LaneStart = l*LaneSize; + for (unsigned i = 0; i != LaneSize; ++i) { if (!isUndefOrInRange(Mask[i+LaneStart], LaneStart, LaneStart+LaneSize)) return false; if (NumElts == 4 || l == 0) @@ -3780,7 +3776,7 @@ // VPERMILPS handling if (Mask[i] < 0) continue; - if (!isUndefOrEqual(Mask[i+LaneStart], Mask[i]+LaneSize)) + if (!isUndefOrEqual(Mask[i+LaneStart], Mask[i]+LaneStart)) return false; } } @@ -3793,9 +3789,9 @@ static unsigned getShuffleVPERMILPImmediate(ShuffleVectorSDNode *SVOp) { EVT VT = SVOp->getValueType(0); - int NumElts = VT.getVectorNumElements(); - int NumLanes = VT.getSizeInBits()/128; - int LaneSize = NumElts/NumLanes; + unsigned NumElts = VT.getVectorNumElements(); + unsigned NumLanes = VT.getSizeInBits()/128; + unsigned LaneSize = NumElts/NumLanes; // Although the mask is equal for both lanes do it twice to get the cases // where a mask will match because the same mask element is undef on the @@ -3803,7 +3799,7 @@ // such as: shuffle , which is completely valid. unsigned Shift = (LaneSize == 4) ? 2 : 1; unsigned Mask = 0; - for (int i = 0; i != NumElts; ++i) { + for (unsigned i = 0; i != NumElts; ++i) { int MaskElt = SVOp->getMaskElt(i); if (MaskElt < 0) continue; @@ -3822,14 +3818,14 @@ /// element of vector 2 and the other elements to come from vector 1 in order. static bool isCommutedMOVLMask(const SmallVectorImpl &Mask, EVT VT, bool V2IsSplat = false, bool V2IsUndef = false) { - int NumOps = VT.getVectorNumElements(); + unsigned NumOps = VT.getVectorNumElements(); if (NumOps != 2 && NumOps != 4 && NumOps != 8 && NumOps != 16) return false; if (!isUndefOrEqual(Mask[0], 0)) return false; - for (int i = 1; i < NumOps; ++i) + for (unsigned i = 1; i != NumOps; ++i) if (!(isUndefOrEqual(Mask[i], i+NumOps) || (V2IsUndef && isUndefOrInRange(Mask[i], NumOps, NumOps*2)) || (V2IsSplat && isUndefOrEqual(Mask[i], NumOps)))) @@ -3893,7 +3889,7 @@ return false; // "i" is the value the indexed mask element must have - for (unsigned i = 0; i < NumElems; i += 2) + for (unsigned i = 0; i != NumElems; i += 2) if (!isUndefOrEqual(N->getMaskElt(i), i) || !isUndefOrEqual(N->getMaskElt(i+1), i)) return false; @@ -3906,15 +3902,15 @@ /// version of MOVDDUP. static bool isMOVDDUPYMask(const SmallVectorImpl &Mask, EVT VT, bool HasAVX) { - int NumElts = VT.getVectorNumElements(); + unsigned NumElts = VT.getVectorNumElements(); if (!HasAVX || VT.getSizeInBits() != 256 || NumElts != 4) return false; - for (int i = 0; i != NumElts/2; ++i) + for (unsigned i = 0; i != NumElts/2; ++i) if (!isUndefOrEqual(Mask[i], 0)) return false; - for (int i = NumElts/2; i != NumElts; ++i) + for (unsigned i = NumElts/2; i != NumElts; ++i) if (!isUndefOrEqual(Mask[i], NumElts/2)) return false; return true; @@ -3929,11 +3925,11 @@ if (VT.getSizeInBits() != 128) return false; - int e = VT.getVectorNumElements() / 2; - for (int i = 0; i < e; ++i) + unsigned e = VT.getVectorNumElements() / 2; + for (unsigned i = 0; i != e; ++i) if (!isUndefOrEqual(N->getMaskElt(i), i)) return false; - for (int i = 0; i < e; ++i) + for (unsigned i = 0; i != e; ++i) if (!isUndefOrEqual(N->getMaskElt(e+i), i)) return false; return true; @@ -3981,14 +3977,14 @@ /// the specified VECTOR_SHUFFLE mask with PSHUF* and SHUFP* instructions. unsigned X86::getShuffleSHUFImmediate(SDNode *N) { ShuffleVectorSDNode *SVOp = cast(N); - int NumOperands = SVOp->getValueType(0).getVectorNumElements(); + unsigned NumOperands = SVOp->getValueType(0).getVectorNumElements(); unsigned Shift = (NumOperands == 4) ? 2 : 1; unsigned Mask = 0; - for (int i = 0; i < NumOperands; ++i) { + for (unsigned i = 0; i != NumOperands; ++i) { int Val = SVOp->getMaskElt(NumOperands-i-1); if (Val < 0) Val = 0; - if (Val >= NumOperands) Val -= NumOperands; + if (Val >= (int)NumOperands) Val -= NumOperands; Mask |= Val; if (i != NumOperands - 1) Mask <<= Shift; From chandlerc at gmail.com Mon Jan 2 03:19:48 2012 From: chandlerc at gmail.com (Chandler Carruth) Date: Mon, 02 Jan 2012 09:19:48 -0000 Subject: [llvm-commits] [llvm] r147431 - in /llvm/trunk/unittests: Bitcode/ Bitcode/BitReaderTest.cpp Bitcode/Makefile CMakeLists.txt Makefile VMCore/Makefile VMCore/pr11677.cpp Message-ID: <20120102091948.9C2891BE003@llvm.org> Author: chandlerc Date: Mon Jan 2 03:19:48 2012 New Revision: 147431 URL: http://llvm.org/viewvc/llvm-project?rev=147431&view=rev Log: Undo the hack in r147427 and move this unittest to a better home. This is testing the bitcode reader's functionality, not VMCore's. Add the what is a hope sufficient build system mojo to build and run a new unittest. Also clean up some of the test's naming. The goal for the file should be to unittest the Bitcode Reader, and this is just one particular test among potentially many in the future. Also, reverse my position and relegate the PR# to a comment, but stash the comment on the same line as the test name so it doesn't get lost. This makes the code more self-documenting hopefully w/o losing track of the PR number. Added: llvm/trunk/unittests/Bitcode/ llvm/trunk/unittests/Bitcode/BitReaderTest.cpp - copied, changed from r147427, llvm/trunk/unittests/VMCore/pr11677.cpp llvm/trunk/unittests/Bitcode/Makefile - copied, changed from r147427, llvm/trunk/unittests/VMCore/Makefile Removed: llvm/trunk/unittests/VMCore/pr11677.cpp Modified: llvm/trunk/unittests/CMakeLists.txt llvm/trunk/unittests/Makefile llvm/trunk/unittests/VMCore/Makefile Copied: llvm/trunk/unittests/Bitcode/BitReaderTest.cpp (from r147427, llvm/trunk/unittests/VMCore/pr11677.cpp) URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/unittests/Bitcode/BitReaderTest.cpp?p2=llvm/trunk/unittests/Bitcode/BitReaderTest.cpp&p1=llvm/trunk/unittests/VMCore/pr11677.cpp&r1=147427&r2=147431&rev=147431&view=diff ============================================================================== --- llvm/trunk/unittests/VMCore/pr11677.cpp (original) +++ llvm/trunk/unittests/Bitcode/BitReaderTest.cpp Mon Jan 2 03:19:48 2012 @@ -1,4 +1,4 @@ -//===- llvm/unittest/VMCore/pr11677.cpp - Test for blockaddr --------------===// +//===- llvm/unittest/Bitcode/BitReaderTest.cpp - Tests for BitReader ------===// // // The LLVM Compiler Infrastructure // @@ -49,7 +49,7 @@ WriteBitcodeToStream(Mod, Stream); } -TEST(PR11677, BlockAddr) { +TEST(BitReaderTest, MaterializeFunctionsForBlockAddr) { // PR11677 std::vector Mem; writeModuleToBuffer(Mem); StringRef Data((const char*)&Mem[0], Mem.size()); @@ -60,5 +60,6 @@ passes.add(createVerifierPass()); passes.run(*m); } + } } Copied: llvm/trunk/unittests/Bitcode/Makefile (from r147427, llvm/trunk/unittests/VMCore/Makefile) URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/unittests/Bitcode/Makefile?p2=llvm/trunk/unittests/Bitcode/Makefile&p1=llvm/trunk/unittests/VMCore/Makefile&r1=147427&r2=147431&rev=147431&view=diff ============================================================================== --- llvm/trunk/unittests/VMCore/Makefile (original) +++ llvm/trunk/unittests/Bitcode/Makefile Mon Jan 2 03:19:48 2012 @@ -1,4 +1,4 @@ -##===- unittests/VMCore/Makefile ---------------------------*- Makefile -*-===## +##===- unittests/Bitcode/Makefile --------------------------*- Makefile -*-===## # # The LLVM Compiler Infrastructure # @@ -8,8 +8,8 @@ ##===----------------------------------------------------------------------===## LEVEL = ../.. -TESTNAME = VMCore -LINK_COMPONENTS := core support bitreader bitwriter target ipa +TESTNAME = Bitcode +LINK_COMPONENTS := core support bitreader bitwriter include $(LEVEL)/Makefile.config include $(LLVM_SRC_ROOT)/unittests/Makefile.unittest Modified: llvm/trunk/unittests/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/unittests/CMakeLists.txt?rev=147431&r1=147430&r2=147431&view=diff ============================================================================== --- llvm/trunk/unittests/CMakeLists.txt (original) +++ llvm/trunk/unittests/CMakeLists.txt Mon Jan 2 03:19:48 2012 @@ -112,7 +112,6 @@ VMCore/PassManagerTest.cpp VMCore/ValueMapTest.cpp VMCore/VerifierTest.cpp - VMCore/pr11677.cpp ) # MSVC9 and 8 cannot compile ValueMapTest.cpp due to their bug. @@ -123,6 +122,10 @@ add_llvm_unittest(VMCore ${VMCoreSources}) +add_llvm_unittest(Bitcode + Bitcode/BitReaderTest.cpp + ) + set(LLVM_LINK_COMPONENTS Support Core Modified: llvm/trunk/unittests/Makefile URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/unittests/Makefile?rev=147431&r1=147430&r2=147431&view=diff ============================================================================== --- llvm/trunk/unittests/Makefile (original) +++ llvm/trunk/unittests/Makefile Mon Jan 2 03:19:48 2012 @@ -9,7 +9,7 @@ LEVEL = .. -PARALLEL_DIRS = ADT ExecutionEngine Support Transforms VMCore Analysis +PARALLEL_DIRS = ADT ExecutionEngine Support Transforms VMCore Analysis Bitcode include $(LEVEL)/Makefile.common Modified: llvm/trunk/unittests/VMCore/Makefile URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/unittests/VMCore/Makefile?rev=147431&r1=147430&r2=147431&view=diff ============================================================================== --- llvm/trunk/unittests/VMCore/Makefile (original) +++ llvm/trunk/unittests/VMCore/Makefile Mon Jan 2 03:19:48 2012 @@ -9,7 +9,7 @@ LEVEL = ../.. TESTNAME = VMCore -LINK_COMPONENTS := core support bitreader bitwriter target ipa +LINK_COMPONENTS := core support target ipa include $(LEVEL)/Makefile.config include $(LLVM_SRC_ROOT)/unittests/Makefile.unittest Removed: llvm/trunk/unittests/VMCore/pr11677.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/unittests/VMCore/pr11677.cpp?rev=147430&view=auto ============================================================================== --- llvm/trunk/unittests/VMCore/pr11677.cpp (original) +++ llvm/trunk/unittests/VMCore/pr11677.cpp (removed) @@ -1,64 +0,0 @@ -//===- llvm/unittest/VMCore/pr11677.cpp - Test for blockaddr --------------===// -// -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. -// -//===----------------------------------------------------------------------===// - -#include "llvm/Analysis/Verifier.h" -#include "llvm/Bitcode/BitstreamWriter.h" -#include "llvm/Bitcode/ReaderWriter.h" -#include "llvm/Constants.h" -#include "llvm/Instructions.h" -#include "llvm/LLVMContext.h" -#include "llvm/Module.h" -#include "llvm/PassManager.h" -#include "llvm/Support/MemoryBuffer.h" -#include "gtest/gtest.h" - -namespace llvm { -namespace { - -static Module *makeLLVMModule() { - Module* Mod = new Module("test-mem", getGlobalContext()); - - FunctionType* FuncTy = - FunctionType::get(Type::getVoidTy(Mod->getContext()), false); - Function* Func = Function::Create(FuncTy,GlobalValue::ExternalLinkage, - "func", Mod); - - BasicBlock* Entry = BasicBlock::Create(Mod->getContext(), "entry", Func); - new UnreachableInst(Mod->getContext(), Entry); - - BasicBlock* BB = BasicBlock::Create(Mod->getContext(), "bb", Func); - new UnreachableInst(Mod->getContext(), BB); - - PointerType* Int8Ptr = Type::getInt8PtrTy(Mod->getContext()); - new GlobalVariable(*Mod, Int8Ptr, /*isConstant=*/true, - GlobalValue::ExternalLinkage, - BlockAddress::get(BB), "table"); - - return Mod; -} - -static void writeModuleToBuffer(std::vector &Buffer) { - Module *Mod = makeLLVMModule(); - BitstreamWriter Stream(Buffer); - WriteBitcodeToStream(Mod, Stream); -} - -TEST(PR11677, BlockAddr) { - std::vector Mem; - writeModuleToBuffer(Mem); - StringRef Data((const char*)&Mem[0], Mem.size()); - MemoryBuffer *Buffer = MemoryBuffer::getMemBuffer(Data, "test", false); - std::string errMsg; - Module *m = getLazyBitcodeModule(Buffer, getGlobalContext(), &errMsg); - PassManager passes; - passes.add(createVerifierPass()); - passes.run(*m); -} -} -} From baldrick at free.fr Mon Jan 2 03:33:28 2012 From: baldrick at free.fr (Duncan Sands) Date: Mon, 02 Jan 2012 09:33:28 -0000 Subject: [llvm-commits] [zorg] r147432 - /zorg/trunk/buildbot/osuosl/master/config/slaves.py Message-ID: <20120102093328.7A1E41BE003@llvm.org> Author: baldrick Date: Mon Jan 2 03:33:28 2012 New Revision: 147432 URL: http://llvm.org/viewvc/llvm-project?rev=147432&view=rev Log: Comment out offline slaves. Add gcc66 and gcc110. Modified: zorg/trunk/buildbot/osuosl/master/config/slaves.py Modified: zorg/trunk/buildbot/osuosl/master/config/slaves.py URL: http://llvm.org/viewvc/llvm-project/zorg/trunk/buildbot/osuosl/master/config/slaves.py?rev=147432&r1=147431&r2=147432&view=diff ============================================================================== --- zorg/trunk/buildbot/osuosl/master/config/slaves.py (original) +++ zorg/trunk/buildbot/osuosl/master/config/slaves.py Mon Jan 2 03:33:28 2012 @@ -64,50 +64,50 @@ create_slave("gcc17", properties={'jobs' : 4}, max_builds=1), # gcc20 1TB 2x6x2.93 GHz Intel Dual Xeon X5670 2.93 GHz 12 cores 24 threads / 24 GB RAM / Debian amd64 create_slave("gcc20", properties={'jobs' : 12}, max_builds=1), - # gcc30 17G 0.4 GHz Alpha EV56 / 2GB RAM / AlphaServer 1200 5/400 => offline, to relocate - create_slave("gcc30", properties={'jobs' : 1}, max_builds=1), - # gcc31 51G 2x0.4 GHz TI UltraSparc II (BlackBird) / 2 GB RAM / Sun Enterprise 250 => offline, to relocate - create_slave("gcc31", properties={'jobs' : 1}, max_builds=1), - # gcc33 19033 1TB 0.8 GHz Freescale i.MX515 / 512 MB RAM / Efika MX Client Dev Board / Ubuntu armv7l - create_slave("gcc33", properties={'jobs' : 1}, max_builds=1), - # gcc34 19034 1TB 0.8 GHz Freescale i.MX515 / 512 MB RAM / Efika MX Client Dev Board / Ubuntu armv7l - create_slave("gcc34", properties={'jobs' : 1}, max_builds=1), - # gcc35 19035 1TB 0.8 GHz Freescale i.MX515 (ARM Cortex-A8) / 512 MB RAM / Efika MX Client Dev Board / Debian armel - create_slave("gcc35", properties={'jobs' : 1}, max_builds=1), - # gcc36 19036 1TB 0.8 GHz Freescale i.MX515 (ARM Cortex-A8) / 512 MB RAM / Efika MX Client Dev Board / Debian armel (?) - create_slave("gcc36", properties={'jobs' : 1}, max_builds=1), - # gcc37 19037 1TB 0.8 GHz Freescale i.MX515 / 512 MB RAM / Efika MX Client Dev Board / Ubuntu armv7l - create_slave("gcc37", properties={'jobs' : 1}, max_builds=1), +# # gcc30 17G 0.4 GHz Alpha EV56 / 2GB RAM / AlphaServer 1200 5/400 => offline, to relocate +# create_slave("gcc30", properties={'jobs' : 1}, max_builds=1), +# # gcc31 51G 2x0.4 GHz TI UltraSparc II (BlackBird) / 2 GB RAM / Sun Enterprise 250 => offline, to relocate +# create_slave("gcc31", properties={'jobs' : 1}, max_builds=1), +# # gcc33 19033 1TB 0.8 GHz Freescale i.MX515 / 512 MB RAM / Efika MX Client Dev Board / Ubuntu armv7l +# create_slave("gcc33", properties={'jobs' : 1}, max_builds=1), +# # gcc34 19034 1TB 0.8 GHz Freescale i.MX515 / 512 MB RAM / Efika MX Client Dev Board / Ubuntu armv7l +# create_slave("gcc34", properties={'jobs' : 1}, max_builds=1), +# # gcc35 19035 1TB 0.8 GHz Freescale i.MX515 (ARM Cortex-A8) / 512 MB RAM / Efika MX Client Dev Board / Debian armel +# create_slave("gcc35", properties={'jobs' : 1}, max_builds=1), +# # gcc36 19036 1TB 0.8 GHz Freescale i.MX515 (ARM Cortex-A8) / 512 MB RAM / Efika MX Client Dev Board / Debian armel (?) +# create_slave("gcc36", properties={'jobs' : 1}, max_builds=1), +# # gcc37 19037 1TB 0.8 GHz Freescale i.MX515 / 512 MB RAM / Efika MX Client Dev Board / Ubuntu armv7l +# create_slave("gcc37", properties={'jobs' : 1}, max_builds=1), # gcc38 1TB 3.2 GHz IBM Cell BE / 256 MB RAM / Sony Playstation 3 / Debian powerpc create_slave("gcc38", properties={'jobs' : 1}, max_builds=1), - # gcc40 160G 1.8 GHz IBM PowerPC 970 (G5) / 512 MB RAM / Apple PowerMac G5 / Debian powerpc - create_slave("gcc40", properties={'jobs' : 1}, max_builds=1), +# # gcc40 160G 1.8 GHz IBM PowerPC 970 (G5) / 512 MB RAM / Apple PowerMac G5 / Debian powerpc +# create_slave("gcc40", properties={'jobs' : 1}, max_builds=1), # gcc42 9092 160G 0.8 GHz ICT Loongson 2F / 512 MB RAM / Lemote Fuloong 6004 Linux mini PC / Debian mipsel create_slave("gcc42", properties={'jobs' : 1}, max_builds=1), - # gcc43 9093 60G 1.4 GHz Powerpc G4 7447A / 1GB RAM / Apple Mac Mini - create_slave("gcc43", properties={'jobs' : 1}, max_builds=1), +# # gcc43 9093 60G 1.4 GHz Powerpc G4 7447A / 1GB RAM / Apple Mac Mini +# create_slave("gcc43", properties={'jobs' : 1}, max_builds=1), # gcc45 19045 1TB 4x3.0 GHz AMD Athlon II X4 640 / 4 GB RAM / Debian i386 create_slave("gcc45", properties={'jobs' : 2}, max_builds=1), # gcc46 250G 1.66 GHz Intel Atom D510 2 cores 4 threads / 4 GB RAM / Debian amd64 create_slave("gcc46", properties={'jobs' : 2}, max_builds=1), # gcc47 250G 1.66 GHz Intel Atom D510 2 cores 4 threads / 4 GB RAM / Debian amd64 create_slave("gcc47", properties={'jobs' : 2}, max_builds=1), - # gcc50 9080 250G 0.6 GHz ARM XScale-80219 / 512 MB RAM / Thecus N2100 NAS - create_slave("gcc50", properties={'jobs' : 1}, max_builds=1), +# # gcc50 9080 250G 0.6 GHz ARM XScale-80219 / 512 MB RAM / Thecus N2100 NAS +# create_slave("gcc50", properties={'jobs' : 1}, max_builds=1), # gcc51 9081 60G 0.8 GHz ICT Loongson 2F / 1 GB RAM / Lemote YeeLoong 8089 notebook / Debian mipsel create_slave("gcc51", properties={'jobs' : 1}, max_builds=1), - # gcc52 9082 1TB 0.8 GHz ICT Loongson 2F / 512 MB RAM / Gdium Liberty 1000 notebook / Mandriva 2009.1 mipsel - create_slave("gcc52", properties={'jobs' : 1}, max_builds=1), - # gcc53 9083 80G 2x1.25 GHz PowerPC 7455 G4 / 1.5 GB RAM / PowerMac G4 dual processor - create_slave("gcc53", properties={'jobs' : 1}, max_builds=1), +# # gcc52 9082 1TB 0.8 GHz ICT Loongson 2F / 512 MB RAM / Gdium Liberty 1000 notebook / Mandriva 2009.1 mipsel +# create_slave("gcc52", properties={'jobs' : 1}, max_builds=1), +# # gcc53 9083 80G 2x1.25 GHz PowerPC 7455 G4 / 1.5 GB RAM / PowerMac G4 dual processor +# create_slave("gcc53", properties={'jobs' : 1}, max_builds=1), # gcc54 36G 0.5 GHz TI UltraSparc IIe (Hummingbird) / 1.5 GB RAM / Sun Netra T1 200 / Debian sparc create_slave("gcc54", properties={'jobs' : 1}, max_builds=1), - # gcc55 9085 250G 1.2 GHz Marvell Kirkwood 88F6281 (Feroceon) / 512 MB RAM / Marvell SheevaPlug / Ubuntu armel - create_slave("gcc55", properties={'jobs' : 1}, max_builds=1), - # gcc56 9086 320G 1.2 GHz Marvell Kirkwood 88F6281 (Feroceon) / 512 MB RAM / Marvell SheevaPlug / Ubuntu armel - create_slave("gcc56", properties={'jobs' : 1}, max_builds=1), - # gcc57 9087 320G 1.2 GHz Marvell Kirkwood 88F6281 (Feroceon) / 512 MB RAM / Marvell SheevaPlug / Ubuntu armel - create_slave("gcc57", properties={'jobs' : 1}, max_builds=1), +# # gcc55 9085 250G 1.2 GHz Marvell Kirkwood 88F6281 (Feroceon) / 512 MB RAM / Marvell SheevaPlug / Ubuntu armel +# create_slave("gcc55", properties={'jobs' : 1}, max_builds=1), +# # gcc56 9086 320G 1.2 GHz Marvell Kirkwood 88F6281 (Feroceon) / 512 MB RAM / Marvell SheevaPlug / Ubuntu armel +# create_slave("gcc56", properties={'jobs' : 1}, max_builds=1), +# # gcc57 9087 320G 1.2 GHz Marvell Kirkwood 88F6281 (Feroceon) / 512 MB RAM / Marvell SheevaPlug / Ubuntu armel +# create_slave("gcc57", properties={'jobs' : 1}, max_builds=1), # gcc60 9200 72G 2x1.3 GHz Intel Itanium 2 (Madison) / 6 GB RAM / HP zx6000 / Debian ia64 create_slave("gcc60", properties={'jobs' : 1}, max_builds=1), # gcc61 9201 36G 2x0.55 GHz HP PA-8600 / 3.5 GB RAM / HP 9000/785/J6000 / Debian hppa @@ -118,16 +118,20 @@ create_slave("gcc63", properties={'jobs' : 16}, max_builds=1), # gcc64 9204 72G 1 GHz Sun UltraSPARC-IIIi / 1 GB RAM / Sun V210 / OpenBSD 4.6 sparc64 create_slave("gcc64", properties={'jobs' : 1}, max_builds=1), + # gcc66 9206 72G 2x1.3 GHz Intel Itanium 2 (Madison) / 12 GB RAM / HP rx2600 / Debian ia64 + create_slave("gcc66", properties={'jobs' : 1}, max_builds=1), # gcc70 160G 2x3.2 GHz Intel Xeon 3.2E (Irwindale) / 3 GB RAM / Dell Poweredge SC1425 / NetBSD amd64 create_slave("gcc70", properties={'jobs' : 1}, max_builds=1), - # gcc100 1TB 2x2.6 GHz AMD Opteron 252 / 1GB RAM running Debian x86_64 - create_slave("gcc100", properties={'jobs' : 1}, max_builds=1), - # gcc101 1TB 2x2.6 GHz AMD Opteron 252 / 1GB RAM running FreeBSD 8 x86_64 - create_slave("gcc101", properties={'jobs' : 1}, max_builds=1), - # gcc200 8010 80G 4x0.4 GHz TI UltraSparc II (BlackBird) / 4 GB RAM / Sun E250 / Gentoo sparc64 - create_slave("gcc200", properties={'jobs' : 2}, max_builds=1), - # gcc201 8011 80G 4x0.4 GHz TI UltraSparc II (BlackBird) / 4 GB RAM / Sun E250 / Gentoo sparc64 - create_slave("gcc201", properties={'jobs' : 2}, max_builds=1), +# # gcc100 1TB 2x2.6 GHz AMD Opteron 252 / 1GB RAM running Debian x86_64 +# create_slave("gcc100", properties={'jobs' : 1}, max_builds=1), +# # gcc101 1TB 2x2.6 GHz AMD Opteron 252 / 1GB RAM running FreeBSD 8 x86_64 +# create_slave("gcc101", properties={'jobs' : 1}, max_builds=1), + # gcc110 2TB 4x16x3.55 GHz IBM POWER7 / 64 GB RAM / IBM Power 730 Express server / Fedora ppc64 + create_slave("gcc110", properties={'jobs' : 2}, max_builds=1), +# # gcc200 8010 80G 4x0.4 GHz TI UltraSparc II (BlackBird) / 4 GB RAM / Sun E250 / Gentoo sparc64 +# create_slave("gcc200", properties={'jobs' : 2}, max_builds=1), +# # gcc201 8011 80G 4x0.4 GHz TI UltraSparc II (BlackBird) / 4 GB RAM / Sun E250 / Gentoo sparc64 +# create_slave("gcc201", properties={'jobs' : 2}, max_builds=1), # AMD Athlon(tm) 64 X2 Dual Core 3800+, Ubuntu x86_64 create_slave("grosser1", properties={'jobs': 2}, max_builds=1), From STPWORLD at narod.ru Mon Jan 2 03:53:27 2012 From: STPWORLD at narod.ru (Stepan Dyatkovskiy) Date: Mon, 02 Jan 2012 13:53:27 +0400 Subject: [llvm-commits] [LLVM, opt, LoopUnswitch] Compile-time improvements. In-Reply-To: <4EFDAB2C.5000606@narod.ru> References: <4EFDAB2C.5000606@narod.ru> Message-ID: <640641325498007@web20.yandex.ru> ping. -Stepan. 30.12.2011, 16:14, "Stepan Dyatkovskiy" : > Hi. A made some fixes that improves compile-time: > > 1. Size heuristics changed. Now we calculate number of unswitching > branches only once per loop. > 2. Some checks was moved from UnswitchIfProfitable to > processCurrentLoop, since it is not changed during processCurrentLoop > iteration. It allows decide to skip some loops at an early stage. > > I checked the compile-time on test > > MultiSource/Benchmarks/Prolangs-C++/shapes/shapes > (there was compile time regression after my previous patch). > > Relative to my previous patch the compile-time improved on ~8.5%. Relative > to old revisions (before r146578) the compile time is improved on ~2%. > > Please find the patch in attachment for review. > > -Stepan. > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From STPWORLD at narod.ru Mon Jan 2 03:56:00 2012 From: STPWORLD at narod.ru (Stepan Dyatkovskiy) Date: Mon, 02 Jan 2012 13:56:00 +0400 Subject: [llvm-commits] [LLVM, PR11652 PATCH]: Fixed Bug 11652 - assertion failures when Type.cpp is compiled with -Os In-Reply-To: <4EFE13EC.2010801@narod.ru> References: <4EFE13EC.2010801@narod.ru> Message-ID: <551701325498160@web74.yandex.ru> ping. -Stepan. 30.12.2011, 23:41, "Stepan Dyatkovskiy" : > The problem is in Type.h. The fields in Type class are declared in next > order: > ???TypeID ??ID : 8; > ???unsigned SubclassData : 24; > ???unsigned NumContainedTys; > > Attempt to set new SubclassData value rewrites lowest byte in > NumContainedTys when -Os is set. GCC bug? Anyway setting SubclassData > with two workaround strings fixes the problem: > > ??void setSubclassData(unsigned val) { > ?????unsigned tmp = NumContainedTys; ?// Workaround for GCC -Os > ?????SubclassData = val; > ?????NumContainedTys = tmp; ?// Workaround for GCC -Os > ?????// Ensure we don't have any accidental truncation. > ?????assert(SubclassData == val && "Subclass data too large for field"); > ???} > > Probably there is another ways to protect NumContainedTys from overwritting? > > Please find the patch in attachment for review. > > -Stepan. > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From STPWORLD at narod.ru Mon Jan 2 03:59:22 2012 From: STPWORLD at narod.ru (Stepan Dyatkovskiy) Date: Mon, 02 Jan 2012 13:59:22 +0400 Subject: [llvm-commits] [LLVM, SwitchInst, case ranges] Auxiliary patch #1 In-Reply-To: <4EFCAA6A.20203@narod.ru> References: <4EAA9B5D.802@narod.ru> <4EAA9DE8.80000@free.fr> <485181319805488@web67.yandex.ru> <4EAB079D.6000606@free.fr> <4EB18F12.6060409@narod.ru> <4EB7C319.1000709@narod.ru> <4EDE7D75.704@narod.ru> <4EDFD0F4.1040204@narod.ru> <4EE25B61.9070006@narod.ru> <4EE5C06C.3050705@narod.ru> <333531323974498@web57.yandex.ru> <4EEB9C52.1050301@narod.ru> <4EF37B6B.6000205@narod.ru> <4EFA0748.9080702@narod.ru> <4EFCAA6A.20203@narod.ru> Message-ID: <610731325498362@web6.yandex.ru> Ping again and again :-) -Stepan. 29.12.2011, 21:59, "Stepan Dyatkovskiy" : > Ping. > -Stepan. > > Stepan Dyatkovskiy wrote: > >> ?ping. >> ?Stepan Dyatkovskiy wrote: >>> ?Ping. >>> >>> ?Stepan Dyatkovskiy wrote: >>>> ?Ping. >>>> >>>> ?-Stepan. From baldrick at free.fr Mon Jan 2 04:02:45 2012 From: baldrick at free.fr (Duncan Sands) Date: Mon, 02 Jan 2012 11:02:45 +0100 Subject: [llvm-commits] [LLVM, PR11652 PATCH]: Fixed Bug 11652 - assertion failures when Type.cpp is compiled with -Os In-Reply-To: <4EFE13EC.2010801@narod.ru> References: <4EFE13EC.2010801@narod.ru> Message-ID: <4F0180C5.1080206@free.fr> Hi Stepan, > The problem is in Type.h. The fields in Type class are declared in next order: > TypeID ID : 8; > unsigned SubclassData : 24; > unsigned NumContainedTys; does the problem still occur if you flip the order of ID and SubclassData? I.e. unsigned SubclassData : 24; TypeID ID : 8; unsigned NumContainedTys; ? Ciao, Duncan. > > Attempt to set new SubclassData value rewrites lowest byte in NumContainedTys > when -Os is set. GCC bug? Anyway setting SubclassData with two workaround > strings fixes the problem: > > void setSubclassData(unsigned val) { > unsigned tmp = NumContainedTys; // Workaround for GCC -Os > SubclassData = val; > NumContainedTys = tmp; // Workaround for GCC -Os > // Ensure we don't have any accidental truncation. > assert(SubclassData == val && "Subclass data too large for field"); > } > > Probably there is another ways to protect NumContainedTys from overwritting? > > Please find the patch in attachment for review. > > -Stepan. > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From STPWORLD at narod.ru Mon Jan 2 04:30:40 2012 From: STPWORLD at narod.ru (Stepan Dyatkovskiy) Date: Mon, 02 Jan 2012 14:30:40 +0400 Subject: [llvm-commits] [LLVM, PR11652 PATCH]: Fixed Bug 11652 - assertion failures when Type.cpp is compiled with -Os In-Reply-To: <4F0180C5.1080206@free.fr> References: <4EFE13EC.2010801@narod.ru> <4F0180C5.1080206@free.fr> Message-ID: <191841325500240@web28.yandex.ru> I tried it doesn't helps. Now it seems that ID is overwritten. 4807 unexpected failures. -Stepan. 02.01.2012, 14:02, "Duncan Sands" : > Hi Stepan, > >> ?The problem is in Type.h. The fields in Type class are declared in next order: >> ?TypeID ID : 8; >> ?unsigned SubclassData : 24; >> ?unsigned NumContainedTys; > > does the problem still occur if you flip the order of ID and SubclassData? > I.e. > ???unsigned SubclassData : 24; > ???TypeID ID : 8; > ???unsigned NumContainedTys; > ? > Ciao, Duncan. > >> ?Attempt to set new SubclassData value rewrites lowest byte in NumContainedTys >> ?when -Os is set. GCC bug? Anyway setting SubclassData with two workaround >> ?strings fixes the problem: >> >> ?void setSubclassData(unsigned val) { >> ?unsigned tmp = NumContainedTys; // Workaround for GCC -Os >> ?SubclassData = val; >> ?NumContainedTys = tmp; // Workaround for GCC -Os >> ?// Ensure we don't have any accidental truncation. >> ?assert(SubclassData == val && "Subclass data too large for field"); >> ?} >> >> ?Probably there is another ways to protect NumContainedTys from overwritting? >> >> ?Please find the patch in attachment for review. >> >> ?-Stepan. >> >> ?_______________________________________________ >> ?llvm-commits mailing list >> ?llvm-commits at cs.uiuc.edu >> ?http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From baldrick at free.fr Mon Jan 2 04:38:10 2012 From: baldrick at free.fr (Duncan Sands) Date: Mon, 02 Jan 2012 11:38:10 +0100 Subject: [llvm-commits] [LLVM, PR11652 PATCH]: Fixed Bug 11652 - assertion failures when Type.cpp is compiled with -Os In-Reply-To: <191841325500240@web28.yandex.ru> References: <4EFE13EC.2010801@narod.ru> <4F0180C5.1080206@free.fr> <191841325500240@web28.yandex.ru> Message-ID: <4F018912.3000107@free.fr> Hi Stepan, > I tried it doesn't helps. Now it seems that ID is overwritten. 4807 unexpected failures. OK, thanks for the info. How about doing the bit fiddling yourself instead? I.e. rather than trying to fool the optimizers, don't use bitfields: declare an unsigned field IDAndSubclassData and store and load values from it using explicit shifts etc. This would then completely avoid all problems coming from misoptimization of bitfields (which has happened a lot historically), and would be less fragile than trying to fool the optimizers via some magic incantation. Ciao, Duncan. > -Stepan. > > 02.01.2012, 14:02, "Duncan Sands": >> Hi Stepan, >> >>> The problem is in Type.h. The fields in Type class are declared in next order: >>> TypeID ID : 8; >>> unsigned SubclassData : 24; >>> unsigned NumContainedTys; >> >> does the problem still occur if you flip the order of ID and SubclassData? >> I.e. >> unsigned SubclassData : 24; >> TypeID ID : 8; >> unsigned NumContainedTys; >> ? >> Ciao, Duncan. >> >>> Attempt to set new SubclassData value rewrites lowest byte in NumContainedTys >>> when -Os is set. GCC bug? Anyway setting SubclassData with two workaround >>> strings fixes the problem: >>> >>> void setSubclassData(unsigned val) { >>> unsigned tmp = NumContainedTys; // Workaround for GCC -Os >>> SubclassData = val; >>> NumContainedTys = tmp; // Workaround for GCC -Os >>> // Ensure we don't have any accidental truncation. >>> assert(SubclassData == val&& "Subclass data too large for field"); >>> } >>> >>> Probably there is another ways to protect NumContainedTys from overwritting? >>> >>> Please find the patch in attachment for review. >>> >>> -Stepan. >>> >>> _______________________________________________ >>> llvm-commits mailing list >>> llvm-commits at cs.uiuc.edu >>> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits >> >> _______________________________________________ >> llvm-commits mailing list >> llvm-commits at cs.uiuc.edu >> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From STPWORLD at narod.ru Mon Jan 2 04:55:53 2012 From: STPWORLD at narod.ru (Stepan Dyatkovskiy) Date: Mon, 02 Jan 2012 14:55:53 +0400 Subject: [llvm-commits] [LLVM, PR11652 PATCH]: Fixed Bug 11652 - assertion failures when Type.cpp is compiled with -Os In-Reply-To: <4F018912.3000107@free.fr> References: <4EFE13EC.2010801@narod.ru> <4F0180C5.1080206@free.fr> <191841325500240@web28.yandex.ru> <4F018912.3000107@free.fr> Message-ID: <200971325501753@web58.yandex.ru> ID is used very extensively in Type.h. We need to fix a lots, so we need to fix all methods like: bool isIntegerTy() const { return ID == IntegerTyID; } But in the same time we can apply some working decision until gcc bug will fixed. May be add some dummy field? TypeID ID : 8; unsigned SubclassData : 24; unsigned KungFuPanda; // Will protect NumContainedTys from overwriting. unsigned NumContainedTys; // Will OK. -Stepan. 02.01.2012, 14:38, "Duncan Sands" : > Hi Stepan, > >> ?I tried it doesn't helps. Now it seems that ID is overwritten. 4807 unexpected failures. > > OK, thanks for the info. ?How about doing the bit fiddling yourself instead? > I.e. rather than trying to fool the optimizers, don't use bitfields: declare > an unsigned field IDAndSubclassData and store and load values from it using > explicit shifts etc. ?This would then completely avoid all problems coming > from misoptimization of bitfields (which has happened a lot historically), > and would be less fragile than trying to fool the optimizers via some magic > incantation. > > Ciao, Duncan. > >> ?-Stepan. >> >> ?02.01.2012, 14:02, "Duncan Sands": >>> ?Hi Stepan, >>>> ???The problem is in Type.h. The fields in Type class are declared in next order: >>>> ???TypeID ID : 8; >>>> ???unsigned SubclassData : 24; >>>> ???unsigned NumContainedTys; >>> ?does the problem still occur if you flip the order of ID and SubclassData? >>> ?I.e. >>> ?????unsigned SubclassData : 24; >>> ?????TypeID ID : 8; >>> ?????unsigned NumContainedTys; >>> ?? >>> ?Ciao, Duncan. >>>> ???Attempt to set new SubclassData value rewrites lowest byte in NumContainedTys >>>> ???when -Os is set. GCC bug? Anyway setting SubclassData with two workaround >>>> ???strings fixes the problem: >>>> >>>> ???void setSubclassData(unsigned val) { >>>> ???unsigned tmp = NumContainedTys; // Workaround for GCC -Os >>>> ???SubclassData = val; >>>> ???NumContainedTys = tmp; // Workaround for GCC -Os >>>> ???// Ensure we don't have any accidental truncation. >>>> ???assert(SubclassData == val&& ?"Subclass data too large for field"); >>>> ???} >>>> >>>> ???Probably there is another ways to protect NumContainedTys from overwritting? >>>> >>>> ???Please find the patch in attachment for review. >>>> >>>> ???-Stepan. >>>> >>>> ???_______________________________________________ >>>> ???llvm-commits mailing list >>>> ???llvm-commits at cs.uiuc.edu >>>> ???http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits >>> ?_______________________________________________ >>> ?llvm-commits mailing list >>> ?llvm-commits at cs.uiuc.edu >>> ?http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From baldrick at free.fr Mon Jan 2 05:04:53 2012 From: baldrick at free.fr (Duncan Sands) Date: Mon, 02 Jan 2012 12:04:53 +0100 Subject: [llvm-commits] [LLVM, PR11652 PATCH]: Fixed Bug 11652 - assertion failures when Type.cpp is compiled with -Os In-Reply-To: <200971325501753@web58.yandex.ru> References: <4EFE13EC.2010801@narod.ru> <4F0180C5.1080206@free.fr> <191841325500240@web28.yandex.ru> <4F018912.3000107@free.fr> <200971325501753@web58.yandex.ru> Message-ID: <4F018F55.1040604@free.fr> Hi Stepan, > ID is used very extensively in Type.h. We need to fix a lots, so we need to fix all methods like: > bool isIntegerTy() const { return ID == IntegerTyID; } you could turn ID into a private method that extracts the id part of the field. Then you just need to turn ID into ID() in places such as isIntegerTy. Likewise for SubclassData. > But in the same time we can apply some working decision until gcc bug will fixed. > May be add some dummy field? > TypeID ID : 8; > unsigned SubclassData : 24; > unsigned KungFuPanda; // Will protect NumContainedTys from overwriting. > unsigned NumContainedTys; // Will OK. Even if the gcc bug is fixed, people will be using older compilers with the bug for years to come. So this field would be around essentially forever. Given that, I don't think this is a good solution. If you are prepared to make the class bigger, you might as well not have the fields be bitfields at all (and change the order so that things are well packed). Ciao, Duncan. > > -Stepan. > > 02.01.2012, 14:38, "Duncan Sands": >> Hi Stepan, >> >>> I tried it doesn't helps. Now it seems that ID is overwritten. 4807 unexpected failures. >> >> OK, thanks for the info. How about doing the bit fiddling yourself instead? >> I.e. rather than trying to fool the optimizers, don't use bitfields: declare >> an unsigned field IDAndSubclassData and store and load values from it using >> explicit shifts etc. This would then completely avoid all problems coming >> from misoptimization of bitfields (which has happened a lot historically), >> and would be less fragile than trying to fool the optimizers via some magic >> incantation. >> >> Ciao, Duncan. >> >>> -Stepan. >>> >>> 02.01.2012, 14:02, "Duncan Sands": >>>> Hi Stepan, >>>>> The problem is in Type.h. The fields in Type class are declared in next order: >>>>> TypeID ID : 8; >>>>> unsigned SubclassData : 24; >>>>> unsigned NumContainedTys; >>>> does the problem still occur if you flip the order of ID and SubclassData? >>>> I.e. >>>> unsigned SubclassData : 24; >>>> TypeID ID : 8; >>>> unsigned NumContainedTys; >>>> ? >>>> Ciao, Duncan. >>>>> Attempt to set new SubclassData value rewrites lowest byte in NumContainedTys >>>>> when -Os is set. GCC bug? Anyway setting SubclassData with two workaround >>>>> strings fixes the problem: >>>>> >>>>> void setSubclassData(unsigned val) { >>>>> unsigned tmp = NumContainedTys; // Workaround for GCC -Os >>>>> SubclassData = val; >>>>> NumContainedTys = tmp; // Workaround for GCC -Os >>>>> // Ensure we don't have any accidental truncation. >>>>> assert(SubclassData == val&& "Subclass data too large for field"); >>>>> } >>>>> >>>>> Probably there is another ways to protect NumContainedTys from overwritting? >>>>> >>>>> Please find the patch in attachment for review. >>>>> >>>>> -Stepan. >>>>> >>>>> _______________________________________________ >>>>> llvm-commits mailing list >>>>> llvm-commits at cs.uiuc.edu >>>>> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits >>>> _______________________________________________ >>>> llvm-commits mailing list >>>> llvm-commits at cs.uiuc.edu >>>> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From STPWORLD at narod.ru Mon Jan 2 06:39:17 2012 From: STPWORLD at narod.ru (Stepan Dyatkovskiy) Date: Mon, 02 Jan 2012 16:39:17 +0400 Subject: [llvm-commits] [LLVM, PR11652 PATCH]: Fixed Bug 11652 - assertion failures when Type.cpp is compiled with -Os In-Reply-To: <4F018F55.1040604@free.fr> References: <4EFE13EC.2010801@narod.ru> <4F0180C5.1080206@free.fr> <191841325500240@web28.yandex.ru> <4F018912.3000107@free.fr> <200971325501753@web58.yandex.ru> <4F018F55.1040604@free.fr> Message-ID: <1136931325507957@web94.yandex.ru> OK. Please look at patch in attachment. I'm not sure that it is better than previous patch. Probably the first one looks like a workaround, but it changes setSubclassData only. New patch changes set/getSubclassData set/getTypeID, and all methods that uses ID. -Stepan. 02.01.2012, 15:04, "Duncan Sands" : > Hi Stepan, > >> ?ID is used very extensively in Type.h. We need to fix a lots, so we need to fix all methods like: >> ?bool isIntegerTy() const { return ID == IntegerTyID; } > > you could turn ID into a private method that extracts the id part of the field. > Then you just need to turn ID into ID() in places such as isIntegerTy. ?Likewise > for SubclassData. > >> ?But in the same time we can apply some working decision until gcc bug will fixed. >> ?May be add some dummy field? >> ????TypeID ??ID : 8; >> ????unsigned SubclassData : 24; >> ????unsigned KungFuPanda; ???????// Will protect NumContainedTys from overwriting. >> ????unsigned NumContainedTys; // Will OK. > > Even if the gcc bug is fixed, people will be using ?older compilers with the bug > for years to come. ?So this field would be around essentially forever. ?Given > that, I don't think this is a good solution. ?If you are prepared to make the > class bigger, you might as well not have the fields be bitfields at all (and > change the order so that things are well packed). > > Ciao, Duncan. > >> ?-Stepan. >> >> ?02.01.2012, 14:38, "Duncan Sands": >>> ?Hi Stepan, >>>> ???I tried it doesn't helps. Now it seems that ID is overwritten. 4807 unexpected failures. >>> ?OK, thanks for the info. ?How about doing the bit fiddling yourself instead? >>> ?I.e. rather than trying to fool the optimizers, don't use bitfields: declare >>> ?an unsigned field IDAndSubclassData and store and load values from it using >>> ?explicit shifts etc. ?This would then completely avoid all problems coming >>> ?from misoptimization of bitfields (which has happened a lot historically), >>> ?and would be less fragile than trying to fool the optimizers via some magic >>> ?incantation. >>> >>> ?Ciao, Duncan. >>>> ???-Stepan. >>>> >>>> ???02.01.2012, 14:02, "Duncan Sands": >>>>> ???Hi Stepan, >>>>>> ?????The problem is in Type.h. The fields in Type class are declared in next order: >>>>>> ?????TypeID ID : 8; >>>>>> ?????unsigned SubclassData : 24; >>>>>> ?????unsigned NumContainedTys; >>>>> ???does the problem still occur if you flip the order of ID and SubclassData? >>>>> ???I.e. >>>>> ???????unsigned SubclassData : 24; >>>>> ???????TypeID ID : 8; >>>>> ???????unsigned NumContainedTys; >>>>> ???? >>>>> ???Ciao, Duncan. >>>>>> ?????Attempt to set new SubclassData value rewrites lowest byte in NumContainedTys >>>>>> ?????when -Os is set. GCC bug? Anyway setting SubclassData with two workaround >>>>>> ?????strings fixes the problem: >>>>>> >>>>>> ?????void setSubclassData(unsigned val) { >>>>>> ?????unsigned tmp = NumContainedTys; // Workaround for GCC -Os >>>>>> ?????SubclassData = val; >>>>>> ?????NumContainedTys = tmp; // Workaround for GCC -Os >>>>>> ?????// Ensure we don't have any accidental truncation. >>>>>> ?????assert(SubclassData == val&& ???"Subclass data too large for field"); >>>>>> ?????} >>>>>> >>>>>> ?????Probably there is another ways to protect NumContainedTys from overwritting? >>>>>> >>>>>> ?????Please find the patch in attachment for review. >>>>>> >>>>>> ?????-Stepan. >>>>>> >>>>>> ?????_______________________________________________ >>>>>> ?????llvm-commits mailing list >>>>>> ?????llvm-commits at cs.uiuc.edu >>>>>> ?????http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits >>>>> ???_______________________________________________ >>>>> ???llvm-commits mailing list >>>>> ???llvm-commits at cs.uiuc.edu >>>>> ???http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits -------------- next part -------------- A non-text attachment was scrubbed... Name: 11652-2.0.patch Type: application/octet-stream Size: 10161 bytes Desc: not available Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20120102/e7f1d18c/attachment.obj From elena.demikhovsky at intel.com Mon Jan 2 08:14:17 2012 From: elena.demikhovsky at intel.com (Demikhovsky, Elena) Date: Mon, 2 Jan 2012 14:14:17 +0000 Subject: [llvm-commits] [llvm] r147399 - in /llvm/trunk: lib/CodeGen/SelectionDAG/LegalizeDAG.cpp test/CodeGen/X86/avx-shuffle-x86_32.ll Please review In-Reply-To: <4F009B73.70103@gmail.com> References: <20120101162247.B625F2A6C12C@llvm.org> <4F009B73.70103@gmail.com> Message-ID: I fixed the patch and want to commit it. I re-checked all and CodeGen/ARM/vext.ll passes now. Please review. - Elena -----Original Message----- From: Rafael ?vila de Esp?ndola [mailto:rafael.espindola at gmail.com] Sent: Sunday, January 01, 2012 19:44 To: Demikhovsky, Elena Cc: llvm-commits at cs.uiuc.edu Subject: Re: [llvm-commits] [llvm] r147399 - in /llvm/trunk: lib/CodeGen/SelectionDAG/LegalizeDAG.cpp test/CodeGen/X86/avx-shuffle-x86_32.ll On 01/01/12 11:22 AM, Elena Demikhovsky wrote: > Author: delena > Date: Sun Jan 1 10:22:47 2012 > New Revision: 147399 > > URL: http://llvm.org/viewvc/llvm-project?rev=147399&view=rev > Log: > Fixed a bug in SelectionDAG.cpp. > The failure seen on win32, when i64 type is illegal. > It happens on stage of conversion VECTOR_SHUFFLE to BUILD_VECTOR. > > The failure message is: > llc: SelectionDAG.cpp:784: void VerifyNodeCommon(llvm::SDNode*): Assertion `(I->getValueType() == EltVT || (EltVT.isInteger() && I->getValueType().isInteger() && EltVT.bitsLE(I->getValueType()))) && "Wrong operand type!"' failed. > > I added a special test that checks vector shuffle on win32. > Hi Elena, I reverted this because it broke CodeGen/ARM/vext.ll, which made the bots red. Cheers, Rafael --------------------------------------------------------------------- Intel Israel (74) Limited This e-mail and any attachments may contain confidential material for the sole use of the intended recipient(s). Any review or distribution by others is strictly prohibited. If you are not the intended recipient, please contact the sender and delete all copies. -------------- next part -------------- A non-text attachment was scrubbed... Name: legalize_dag.diff Type: application/octet-stream Size: 3789 bytes Desc: legalize_dag.diff Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20120102/250d5dd7/attachment-0001.obj From baldrick at free.fr Mon Jan 2 09:25:53 2012 From: baldrick at free.fr (Duncan Sands) Date: Mon, 02 Jan 2012 16:25:53 +0100 Subject: [llvm-commits] [LLVM, PR11652 PATCH]: Fixed Bug 11652 - assertion failures when Type.cpp is compiled with -Os In-Reply-To: <1136931325507957@web94.yandex.ru> References: <4EFE13EC.2010801@narod.ru> <4F0180C5.1080206@free.fr> <191841325500240@web28.yandex.ru> <4F018912.3000107@free.fr> <200971325501753@web58.yandex.ru> <4F018F55.1040604@free.fr> <1136931325507957@web94.yandex.ru> Message-ID: <4F01CC81.4010909@free.fr> Hi Stepan, > OK. Please look at patch in attachment. > I'm not sure that it is better than previous patch. Probably the first one looks like a workaround, but it changes setSubclassData only. New patch changes set/getSubclassData set/getTypeID, and all methods that uses ID. thanks for doing this. I think it is a better abstraction to have getters and setters for ID, like the ones that already exist for SubclassData. Can you therefore split the patch in two: one patch that adds getters and setters, and then a second one that drops the bitfield in favour of explicit bit fiddling. Additional comments: - you made some lines too long (> 80 columns). - this is not your fault, but I think there should be a check that ID values fit in the allocated space, for example by checking somehow that there is enough room for every value of the TypeID type. Alternatively, in setTypeID check that the value you read back out matches the value put in. The constructor can also set the ID. It should probably initialize IDAndSubclassData to zero, and then call setTypeID in the body of the constructor to set the value. Ciao, Duncan. > > -Stepan. > > 02.01.2012, 15:04, "Duncan Sands": >> Hi Stepan, >> >>> ID is used very extensively in Type.h. We need to fix a lots, so we need to fix all methods like: >>> bool isIntegerTy() const { return ID == IntegerTyID; } >> >> you could turn ID into a private method that extracts the id part of the field. >> Then you just need to turn ID into ID() in places such as isIntegerTy. Likewise >> for SubclassData. >> >>> But in the same time we can apply some working decision until gcc bug will fixed. >>> May be add some dummy field? >>> TypeID ID : 8; >>> unsigned SubclassData : 24; >>> unsigned KungFuPanda; // Will protect NumContainedTys from overwriting. >>> unsigned NumContainedTys; // Will OK. >> >> Even if the gcc bug is fixed, people will be using older compilers with the bug >> for years to come. So this field would be around essentially forever. Given >> that, I don't think this is a good solution. If you are prepared to make the >> class bigger, you might as well not have the fields be bitfields at all (and >> change the order so that things are well packed). >> >> Ciao, Duncan. >> >>> -Stepan. >>> >>> 02.01.2012, 14:38, "Duncan Sands": >>>> Hi Stepan, >>>>> I tried it doesn't helps. Now it seems that ID is overwritten. 4807 unexpected failures. >>>> OK, thanks for the info. How about doing the bit fiddling yourself instead? >>>> I.e. rather than trying to fool the optimizers, don't use bitfields: declare >>>> an unsigned field IDAndSubclassData and store and load values from it using >>>> explicit shifts etc. This would then completely avoid all problems coming >>>> from misoptimization of bitfields (which has happened a lot historically), >>>> and would be less fragile than trying to fool the optimizers via some magic >>>> incantation. >>>> >>>> Ciao, Duncan. >>>>> -Stepan. >>>>> >>>>> 02.01.2012, 14:02, "Duncan Sands": >>>>>> Hi Stepan, >>>>>>> The problem is in Type.h. The fields in Type class are declared in next order: >>>>>>> TypeID ID : 8; >>>>>>> unsigned SubclassData : 24; >>>>>>> unsigned NumContainedTys; >>>>>> does the problem still occur if you flip the order of ID and SubclassData? >>>>>> I.e. >>>>>> unsigned SubclassData : 24; >>>>>> TypeID ID : 8; >>>>>> unsigned NumContainedTys; >>>>>> ? >>>>>> Ciao, Duncan. >>>>>>> Attempt to set new SubclassData value rewrites lowest byte in NumContainedTys >>>>>>> when -Os is set. GCC bug? Anyway setting SubclassData with two workaround >>>>>>> strings fixes the problem: >>>>>>> >>>>>>> void setSubclassData(unsigned val) { >>>>>>> unsigned tmp = NumContainedTys; // Workaround for GCC -Os >>>>>>> SubclassData = val; >>>>>>> NumContainedTys = tmp; // Workaround for GCC -Os >>>>>>> // Ensure we don't have any accidental truncation. >>>>>>> assert(SubclassData == val&& "Subclass data too large for field"); >>>>>>> } >>>>>>> >>>>>>> Probably there is another ways to protect NumContainedTys from overwritting? >>>>>>> >>>>>>> Please find the patch in attachment for review. >>>>>>> >>>>>>> -Stepan. >>>>>>> >>>>>>> _______________________________________________ >>>>>>> llvm-commits mailing list >>>>>>> llvm-commits at cs.uiuc.edu >>>>>>> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits >>>>>> _______________________________________________ >>>>>> llvm-commits mailing list >>>>>> llvm-commits at cs.uiuc.edu >>>>>> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From rafael.espindola at gmail.com Mon Jan 2 10:56:24 2012 From: rafael.espindola at gmail.com (=?windows-1252?Q?Rafael_=C1vila_de_Esp=EDndola?=) Date: Mon, 02 Jan 2012 11:56:24 -0500 Subject: [llvm-commits] [llvm] r147399 - in /llvm/trunk: lib/CodeGen/SelectionDAG/LegalizeDAG.cpp test/CodeGen/X86/avx-shuffle-x86_32.ll Please review In-Reply-To: References: <20120101162247.B625F2A6C12C@llvm.org> <4F009B73.70103@gmail.com> Message-ID: <4F01E1B8.303@gmail.com> On 02/01/12 09:14 AM, Demikhovsky, Elena wrote: > I fixed the patch and want to commit it. > I re-checked all and CodeGen/ARM/vext.ll passes now. > > Please review. I am not sure I can approve a patch in this area, but if it is just a fixed version of the previous patch it is probably OK. > > - Elena Cheers, Rafael From baldrick at free.fr Mon Jan 2 10:55:01 2012 From: baldrick at free.fr (Duncan Sands) Date: Mon, 02 Jan 2012 16:55:01 -0000 Subject: [llvm-commits] [llvm] r147435 - /llvm/trunk/docs/CommandGuide/lit.pod Message-ID: <20120102165501.55D9A2A6C12C@llvm.org> Author: baldrick Date: Mon Jan 2 10:55:01 2012 New Revision: 147435 URL: http://llvm.org/viewvc/llvm-project?rev=147435&view=rev Log: Correct spelling. Modified: llvm/trunk/docs/CommandGuide/lit.pod Modified: llvm/trunk/docs/CommandGuide/lit.pod URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/CommandGuide/lit.pod?rev=147435&r1=147434&r2=147435&view=diff ============================================================================== --- llvm/trunk/docs/CommandGuide/lit.pod (original) +++ llvm/trunk/docs/CommandGuide/lit.pod Mon Jan 2 10:55:01 2012 @@ -208,7 +208,7 @@ The test succeeded, but it was expected to fail. This is used for tests which were specified as expected to fail, but are now succeeding (generally because -the feautre they test was broken and has been fixed). +the feature they test was broken and has been fixed). =item B From chandlerc at google.com Mon Jan 2 11:36:14 2012 From: chandlerc at google.com (Chandler Carruth) Date: Mon, 2 Jan 2012 09:36:14 -0800 Subject: [llvm-commits] [PATCH][CMake] PR10050. In-Reply-To: References: Message-ID: On Thu, Dec 29, 2011 at 8:09 AM, arrowdodger <6yearold at gmail.com> wrote: > Updated patches attached. Changes: > 1. All generating targets are now running only when user is invoking > install rule. Credits go to @sakra on SO. > 2. Wrapped some common code into macros, put them into > cmake/modules/AddLLVM.cmake. > 3. Create .tar.gz's only if both tar and gzip are found, otherwise warn > user and don't even generate targets. > 4. Code style fixes. Thanks, but there are some real problems with how this is structured. The first two are easy to fix, but the last may not be. 1) The macros are strangely formed in a few ways. First, please avoid magical arrays filled in with the results of your macro. They're very hard to understand. I'd much rather that each macro produces a new target which other things can then depend on, or populates an array the name of which is passed into the macro. Also, why make the user write a foreach loop around the files? It seems like you could have them provide a list of files rather than a single file, and do the looping inside the macro. Finally, please allow the user to specify the actual filename rather than the basename of the podfile. Compute the basename yourself, as this will make both the use of the macro easier to understand and it's implementation more clear. 2) Please use something more distinct such as 'llvm-docs-*' as the custom target names; 'llvm-ps' looks too much like it could be one of the actual LLVM tools. 3) I don't understand why you can't use normal CMake dependencies to connect the install rules to the actual build steps. It seems like you could use install(FILES ${HTML_FILES} ...) or some equivalent construct. CMake should be handling the dependency computations and ensuring that those files are build for 'make install'. If CMake cannot do this naturally with its own dependency information, then I fear it may not be worth adding this to the CMake builds, and they will be less functional than the autotools builds. I think re-executing the make tool is an unacceptable design wart. I also have trouble believing CMake can't represent this pattern, but I haven't tried my hand at it... -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20120102/946560bb/attachment.html From eli.friedman at gmail.com Mon Jan 2 11:57:22 2012 From: eli.friedman at gmail.com (Eli Friedman) Date: Mon, 2 Jan 2012 09:57:22 -0800 Subject: [llvm-commits] [llvm] r147399 - in /llvm/trunk: lib/CodeGen/SelectionDAG/LegalizeDAG.cpp test/CodeGen/X86/avx-shuffle-x86_32.ll Please review In-Reply-To: References: <20120101162247.B625F2A6C12C@llvm.org> <4F009B73.70103@gmail.com> Message-ID: 2012/1/2 Demikhovsky, Elena : > I fixed the patch and want to commit it. > I re-checked all and CodeGen/ARM/vext.ll passes now. > > Please review. What changed to fix this patch? For the following: + // EltVT gets smaller + assert(factor > 0); + SmallVector NewMask(32U, -1); Where does the "32U" come from in "NewMask(32U, -1)"? For the following: + for (unsigned i = 0; i < VT.getVectorNumElements(); ++i) { + if (Mask[i] < 0) { + for (unsigned fi = 0; fi < factor; ++fi) + NewMask[i*factor+fi] = Mask[i]; + } + else { + for (unsigned fi = 0; fi < factor; ++fi) + NewMask[i*factor+fi] = Mask[i]*factor+fi; + } + Mask = NewMask; + } The assignment Mask = NewMask inside the loop looks very suspicious: are you sure that's correct? -Eli From STPWORLD at narod.ru Mon Jan 2 13:46:37 2012 From: STPWORLD at narod.ru (Stepan Dyatkovskiy) Date: Mon, 02 Jan 2012 23:46:37 +0400 Subject: [llvm-commits] [LLVM, PR11652 PATCH]: Fixed Bug 11652 - assertion failures when Type.cpp is compiled with -Os In-Reply-To: <4F01CC81.4010909@free.fr> References: <4EFE13EC.2010801@narod.ru> <4F0180C5.1080206@free.fr> <191841325500240@web28.yandex.ru> <4F018912.3000107@free.fr> <200971325501753@web58.yandex.ru> <4F018F55.1040604@free.fr> <1136931325507957@web94.yandex.ru> <4F01CC81.4010909@free.fr> Message-ID: <359001325533597@web8.yandex.ru> Hi, Duncan. Please find the first patch in attachment. Replacement: ID with getTypeID(). - Stepan 02.01.2012, 19:25, "Duncan Sands" : > Hi Stepan, > >> ?OK. Please look at patch in attachment. >> ?I'm not sure that it is better than previous patch. Probably the first one looks like a workaround, but it changes setSubclassData only. New patch changes set/getSubclassData set/getTypeID, and all methods that uses ID. > > thanks for doing this. ?I think it is a better abstraction to have getters > and setters for ID, like the ones that already exist for SubclassData. ?Can > you therefore split the patch in two: one patch that adds getters and setters, > and then a second one that drops the bitfield in favour of explicit bit > fiddling. > > Additional comments: > ???- you made some lines too long (> 80 columns). > ???- this is not your fault, but I think there should be a check that ID values > ?????fit in the allocated space, for example by checking somehow that there is > ?????enough room for every value of the TypeID type. ?Alternatively, in setTypeID > ?????check that the value you read back out matches the value put in. ?The > ?????constructor can also set the ID. ?It should probably initialize > ?????IDAndSubclassData to zero, and then call setTypeID in the body of the > ?????constructor to set the value. > > Ciao, Duncan. > >> ?-Stepan. >> >> ?02.01.2012, 15:04, "Duncan Sands": >>> ?Hi Stepan, >>>> ???ID is used very extensively in Type.h. We need to fix a lots, so we need to fix all methods like: >>>> ???bool isIntegerTy() const { return ID == IntegerTyID; } >>> ?you could turn ID into a private method that extracts the id part of the field. >>> ?Then you just need to turn ID into ID() in places such as isIntegerTy. ?Likewise >>> ?for SubclassData. >>>> ???But in the same time we can apply some working decision until gcc bug will fixed. >>>> ???May be add some dummy field? >>>> ??????TypeID ??ID : 8; >>>> ??????unsigned SubclassData : 24; >>>> ??????unsigned KungFuPanda; ???????// Will protect NumContainedTys from overwriting. >>>> ??????unsigned NumContainedTys; // Will OK. >>> ?Even if the gcc bug is fixed, people will be using ?older compilers with the bug >>> ?for years to come. ?So this field would be around essentially forever. ?Given >>> ?that, I don't think this is a good solution. ?If you are prepared to make the >>> ?class bigger, you might as well not have the fields be bitfields at all (and >>> ?change the order so that things are well packed). >>> >>> ?Ciao, Duncan. >>>> ???-Stepan. >>>> >>>> ???02.01.2012, 14:38, "Duncan Sands": >>>>> ???Hi Stepan, >>>>>> ?????I tried it doesn't helps. Now it seems that ID is overwritten. 4807 unexpected failures. >>>>> ???OK, thanks for the info. ?How about doing the bit fiddling yourself instead? >>>>> ???I.e. rather than trying to fool the optimizers, don't use bitfields: declare >>>>> ???an unsigned field IDAndSubclassData and store and load values from it using >>>>> ???explicit shifts etc. ?This would then completely avoid all problems coming >>>>> ???from misoptimization of bitfields (which has happened a lot historically), >>>>> ???and would be less fragile than trying to fool the optimizers via some magic >>>>> ???incantation. >>>>> >>>>> ???Ciao, Duncan. >>>>>> ?????-Stepan. >>>>>> >>>>>> ?????02.01.2012, 14:02, "Duncan Sands": >>>>>>> ?????Hi Stepan, >>>>>>>> ???????The problem is in Type.h. The fields in Type class are declared in next order: >>>>>>>> ???????TypeID ID : 8; >>>>>>>> ???????unsigned SubclassData : 24; >>>>>>>> ???????unsigned NumContainedTys; >>>>>>> ?????does the problem still occur if you flip the order of ID and SubclassData? >>>>>>> ?????I.e. >>>>>>> ?????????unsigned SubclassData : 24; >>>>>>> ?????????TypeID ID : 8; >>>>>>> ?????????unsigned NumContainedTys; >>>>>>> ?????? >>>>>>> ?????Ciao, Duncan. >>>>>>>> ???????Attempt to set new SubclassData value rewrites lowest byte in NumContainedTys >>>>>>>> ???????when -Os is set. GCC bug? Anyway setting SubclassData with two workaround >>>>>>>> ???????strings fixes the problem: >>>>>>>> >>>>>>>> ???????void setSubclassData(unsigned val) { >>>>>>>> ???????unsigned tmp = NumContainedTys; // Workaround for GCC -Os >>>>>>>> ???????SubclassData = val; >>>>>>>> ???????NumContainedTys = tmp; // Workaround for GCC -Os >>>>>>>> ???????// Ensure we don't have any accidental truncation. >>>>>>>> ???????assert(SubclassData == val&& ?????"Subclass data too large for field"); >>>>>>>> ???????} >>>>>>>> >>>>>>>> ???????Probably there is another ways to protect NumContainedTys from overwritting? >>>>>>>> >>>>>>>> ???????Please find the patch in attachment for review. >>>>>>>> >>>>>>>> ???????-Stepan. >>>>>>>> >>>>>>>> ???????_______________________________________________ >>>>>>>> ???????llvm-commits mailing list >>>>>>>> ???????llvm-commits at cs.uiuc.edu >>>>>>>> ???????http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits >>>>>>> ?????_______________________________________________ >>>>>>> ?????llvm-commits mailing list >>>>>>> ?????llvm-commits at cs.uiuc.edu >>>>>>> ?????http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits -------------- next part -------------- A non-text attachment was scrubbed... Name: 11652-2.0-getTypeID.patch Type: application/octet-stream Size: 8638 bytes Desc: not available Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20120102/94ad7d5c/attachment.obj From atrick at apple.com Mon Jan 2 15:25:11 2012 From: atrick at apple.com (Andrew Trick) Date: Mon, 02 Jan 2012 21:25:11 -0000 Subject: [llvm-commits] [llvm] r147439 - in /llvm/trunk: lib/Analysis/ScalarEvolutionExpander.cpp test/Transforms/LoopStrengthReduce/2012-02-nopreheader.ll Message-ID: <20120102212511.1D2ED2A6C12C@llvm.org> Author: atrick Date: Mon Jan 2 15:25:10 2012 New Revision: 147439 URL: http://llvm.org/viewvc/llvm-project?rev=147439&view=rev Log: Fix SCEVExpander to handle loops with no preheader when LSR gives it a "phony" insertion point. Fixes rdar://10619599: "SelectionDAGBuilder shouldn't visit PHI nodes!" assert Added: llvm/trunk/test/Transforms/LoopStrengthReduce/2012-02-nopreheader.ll Modified: llvm/trunk/lib/Analysis/ScalarEvolutionExpander.cpp Modified: llvm/trunk/lib/Analysis/ScalarEvolutionExpander.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/ScalarEvolutionExpander.cpp?rev=147439&r1=147438&r2=147439&view=diff ============================================================================== --- llvm/trunk/lib/Analysis/ScalarEvolutionExpander.cpp (original) +++ llvm/trunk/lib/Analysis/ScalarEvolutionExpander.cpp Mon Jan 2 15:25:10 2012 @@ -1443,6 +1443,12 @@ if (!L) break; if (BasicBlock *Preheader = L->getLoopPreheader()) InsertPt = Preheader->getTerminator(); + else { + // LSR sets the insertion point for AddRec start/step values to the + // block start to simplify value reuse, even though it's an invalid + // position. SCEVExpander must correct for this in all cases. + InsertPt = L->getHeader()->getFirstInsertionPt(); + } } else { // If the SCEV is computable at this level, insert it into the header // after the PHIs (and after any other instructions that we've inserted Added: llvm/trunk/test/Transforms/LoopStrengthReduce/2012-02-nopreheader.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/LoopStrengthReduce/2012-02-nopreheader.ll?rev=147439&view=auto ============================================================================== --- llvm/trunk/test/Transforms/LoopStrengthReduce/2012-02-nopreheader.ll (added) +++ llvm/trunk/test/Transforms/LoopStrengthReduce/2012-02-nopreheader.ll Mon Jan 2 15:25:10 2012 @@ -0,0 +1,50 @@ +; RUN: opt -loop-reduce -S < %s | FileCheck %s +; +; "SelectionDAGBuilder shouldn't visit PHI nodes!" assert. + +target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128-f128:128:128-n8:16:32" +target triple = "i386-apple-darwin" + +; LSR should convert the inner loop (bb7.us) IV (j.01.us) into float*. +; This involves a nested AddRec, the outer AddRec's loop invariant components +; cannot find a preheader, so they should be expanded in the loop header +; (bb7.lr.ph.us) below the existing phi i.12.us. +; CHECK: @nopreheader +; CHECK: bb7.lr.ph.us: +; CHECK: %lsr.iv = phi float* +; CHECK: bb7.us: +; CHECK: %lsr.iv2 = phi float* +define void @nopreheader(float* nocapture %a, i32 %n) nounwind { +entry: + %0 = sdiv i32 %n, undef + indirectbr i8* undef, [label %bb10.preheader] + +bb10.preheader: ; preds = %bb4 + indirectbr i8* undef, [label %bb8.preheader.lr.ph, label %return] + +bb8.preheader.lr.ph: ; preds = %bb10.preheader + indirectbr i8* null, [label %bb7.lr.ph.us, label %bb9] + +bb7.lr.ph.us: ; preds = %bb9.us, %bb8.preheader.lr.ph + %i.12.us = phi i32 [ %2, %bb9.us ], [ 0, %bb8.preheader.lr.ph ] + %tmp30 = mul i32 %0, %i.12.us + indirectbr i8* undef, [label %bb7.us] + +bb7.us: ; preds = %bb7.lr.ph.us, %bb7.us + %j.01.us = phi i32 [ 0, %bb7.lr.ph.us ], [ %1, %bb7.us ] + %tmp31 = add i32 %tmp30, %j.01.us + %scevgep9 = getelementptr float* %a, i32 %tmp31 + store float undef, float* %scevgep9, align 1 + %1 = add nsw i32 %j.01.us, 1 + indirectbr i8* undef, [label %bb9.us, label %bb7.us] + +bb9.us: ; preds = %bb7.us + %2 = add nsw i32 %i.12.us, 1 + indirectbr i8* undef, [label %bb7.lr.ph.us, label %return] + +bb9: ; preds = %bb9, %bb8.preheader.lr.ph + indirectbr i8* undef, [label %bb9, label %return] + +return: ; preds = %bb9, %bb9.us, %bb10.preheader + ret void +} From baldrick at free.fr Tue Jan 3 02:32:27 2012 From: baldrick at free.fr (Duncan Sands) Date: Tue, 03 Jan 2012 09:32:27 +0100 Subject: [llvm-commits] [LLVM, PR11652 PATCH]: Fixed Bug 11652 - assertion failures when Type.cpp is compiled with -Os In-Reply-To: <359001325533597@web8.yandex.ru> References: <4EFE13EC.2010801@narod.ru> <4F0180C5.1080206@free.fr> <191841325500240@web28.yandex.ru> <4F018912.3000107@free.fr> <200971325501753@web58.yandex.ru> <4F018F55.1040604@free.fr> <1136931325507957@web94.yandex.ru> <4F01CC81.4010909@free.fr> <359001325533597@web8.yandex.ru> Message-ID: <4F02BD1B.7070808@free.fr> Hi Stepan, this looks fine except for a pointless include of stdint.h. Please apply, except for the include. Thanks for doing this, Duncan. > Hi, Duncan. Please find the first patch in attachment. Replacement: ID with getTypeID(). > - Stepan > > 02.01.2012, 19:25, "Duncan Sands": >> Hi Stepan, >> >>> OK. Please look at patch in attachment. >>> I'm not sure that it is better than previous patch. Probably the first one looks like a workaround, but it changes setSubclassData only. New patch changes set/getSubclassData set/getTypeID, and all methods that uses ID. >> >> thanks for doing this. I think it is a better abstraction to have getters >> and setters for ID, like the ones that already exist for SubclassData. Can >> you therefore split the patch in two: one patch that adds getters and setters, >> and then a second one that drops the bitfield in favour of explicit bit >> fiddling. >> >> Additional comments: >> - you made some lines too long (> 80 columns). >> - this is not your fault, but I think there should be a check that ID values >> fit in the allocated space, for example by checking somehow that there is >> enough room for every value of the TypeID type. Alternatively, in setTypeID >> check that the value you read back out matches the value put in. The >> constructor can also set the ID. It should probably initialize >> IDAndSubclassData to zero, and then call setTypeID in the body of the >> constructor to set the value. >> >> Ciao, Duncan. >> >>> -Stepan. >>> >>> 02.01.2012, 15:04, "Duncan Sands": >>>> Hi Stepan, >>>>> ID is used very extensively in Type.h. We need to fix a lots, so we need to fix all methods like: >>>>> bool isIntegerTy() const { return ID == IntegerTyID; } >>>> you could turn ID into a private method that extracts the id part of the field. >>>> Then you just need to turn ID into ID() in places such as isIntegerTy. Likewise >>>> for SubclassData. >>>>> But in the same time we can apply some working decision until gcc bug will fixed. >>>>> May be add some dummy field? >>>>> TypeID ID : 8; >>>>> unsigned SubclassData : 24; >>>>> unsigned KungFuPanda; // Will protect NumContainedTys from overwriting. >>>>> unsigned NumContainedTys; // Will OK. >>>> Even if the gcc bug is fixed, people will be using older compilers with the bug >>>> for years to come. So this field would be around essentially forever. Given >>>> that, I don't think this is a good solution. If you are prepared to make the >>>> class bigger, you might as well not have the fields be bitfields at all (and >>>> change the order so that things are well packed). >>>> >>>> Ciao, Duncan. >>>>> -Stepan. >>>>> >>>>> 02.01.2012, 14:38, "Duncan Sands": >>>>>> Hi Stepan, >>>>>>> I tried it doesn't helps. Now it seems that ID is overwritten. 4807 unexpected failures. >>>>>> OK, thanks for the info. How about doing the bit fiddling yourself instead? >>>>>> I.e. rather than trying to fool the optimizers, don't use bitfields: declare >>>>>> an unsigned field IDAndSubclassData and store and load values from it using >>>>>> explicit shifts etc. This would then completely avoid all problems coming >>>>>> from misoptimization of bitfields (which has happened a lot historically), >>>>>> and would be less fragile than trying to fool the optimizers via some magic >>>>>> incantation. >>>>>> >>>>>> Ciao, Duncan. >>>>>>> -Stepan. >>>>>>> >>>>>>> 02.01.2012, 14:02, "Duncan Sands": >>>>>>>> Hi Stepan, >>>>>>>>> The problem is in Type.h. The fields in Type class are declared in next order: >>>>>>>>> TypeID ID : 8; >>>>>>>>> unsigned SubclassData : 24; >>>>>>>>> unsigned NumContainedTys; >>>>>>>> does the problem still occur if you flip the order of ID and SubclassData? >>>>>>>> I.e. >>>>>>>> unsigned SubclassData : 24; >>>>>>>> TypeID ID : 8; >>>>>>>> unsigned NumContainedTys; >>>>>>>> ? >>>>>>>> Ciao, Duncan. >>>>>>>>> Attempt to set new SubclassData value rewrites lowest byte in NumContainedTys >>>>>>>>> when -Os is set. GCC bug? Anyway setting SubclassData with two workaround >>>>>>>>> strings fixes the problem: >>>>>>>>> >>>>>>>>> void setSubclassData(unsigned val) { >>>>>>>>> unsigned tmp = NumContainedTys; // Workaround for GCC -Os >>>>>>>>> SubclassData = val; >>>>>>>>> NumContainedTys = tmp; // Workaround for GCC -Os >>>>>>>>> // Ensure we don't have any accidental truncation. >>>>>>>>> assert(SubclassData == val&& "Subclass data too large for field"); >>>>>>>>> } >>>>>>>>> >>>>>>>>> Probably there is another ways to protect NumContainedTys from overwritting? >>>>>>>>> >>>>>>>>> Please find the patch in attachment for review. >>>>>>>>> >>>>>>>>> -Stepan. >>>>>>>>> >>>>>>>>> _______________________________________________ >>>>>>>>> llvm-commits mailing list >>>>>>>>> llvm-commits at cs.uiuc.edu >>>>>>>>> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits >>>>>>>> _______________________________________________ >>>>>>>> llvm-commits mailing list >>>>>>>> llvm-commits at cs.uiuc.edu >>>>>>>> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From STPWORLD at narod.ru Tue Jan 3 02:50:38 2012 From: STPWORLD at narod.ru (Stepan Dyatkovskiy) Date: Tue, 03 Jan 2012 12:50:38 +0400 Subject: [llvm-commits] [LLVM, PR11652 PATCH]: Fixed Bug 11652 - assertion failures when Type.cpp is compiled with -Os In-Reply-To: <4F02BD1B.7070808@free.fr> References: <4EFE13EC.2010801@narod.ru> <4F0180C5.1080206@free.fr> <191841325500240@web28.yandex.ru> <4F018912.3000107@free.fr> <200971325501753@web58.yandex.ru> <4F018F55.1040604@free.fr> <1136931325507957@web94.yandex.ru> <4F01CC81.4010909@free.fr> <359001325533597@web8.yandex.ru> <4F02BD1B.7070808@free.fr> Message-ID: <673781325580638@web123.yandex.ru> Hi Duncan, can I use DataTypes.h instead? -Stepan. 03.01.2012, 12:32, "Duncan Sands" : > Hi Stepan, this looks fine except for a pointless include of stdint.h. ?Please > apply, except for the include. > > Thanks for doing this, > > Duncan. > >> ?Hi, Duncan. Please find the first patch in attachment. Replacement: ID with getTypeID(). >> ?- Stepan >> >> ?02.01.2012, 19:25, "Duncan Sands": >>> ?Hi Stepan, >>>> ???OK. Please look at patch in attachment. >>>> ???I'm not sure that it is better than previous patch. Probably the first one looks like a workaround, but it changes setSubclassData only. New patch changes set/getSubclassData set/getTypeID, and all methods that uses ID. >>> ?thanks for doing this. ?I think it is a better abstraction to have getters >>> ?and setters for ID, like the ones that already exist for SubclassData. ?Can >>> ?you therefore split the patch in two: one patch that adds getters and setters, >>> ?and then a second one that drops the bitfield in favour of explicit bit >>> ?fiddling. >>> >>> ?Additional comments: >>> ?????- you made some lines too long (> ?80 columns). >>> ?????- this is not your fault, but I think there should be a check that ID values >>> ???????fit in the allocated space, for example by checking somehow that there is >>> ???????enough room for every value of the TypeID type. ?Alternatively, in setTypeID >>> ???????check that the value you read back out matches the value put in. ?The >>> ???????constructor can also set the ID. ?It should probably initialize >>> ???????IDAndSubclassData to zero, and then call setTypeID in the body of the >>> ???????constructor to set the value. >>> >>> ?Ciao, Duncan. >>>> ???-Stepan. >>>> >>>> ???02.01.2012, 15:04, "Duncan Sands": >>>>> ???Hi Stepan, >>>>>> ?????ID is used very extensively in Type.h. We need to fix a lots, so we need to fix all methods like: >>>>>> ?????bool isIntegerTy() const { return ID == IntegerTyID; } >>>>> ???you could turn ID into a private method that extracts the id part of the field. >>>>> ???Then you just need to turn ID into ID() in places such as isIntegerTy. ?Likewise >>>>> ???for SubclassData. >>>>>> ?????But in the same time we can apply some working decision until gcc bug will fixed. >>>>>> ?????May be add some dummy field? >>>>>> ????????TypeID ??ID : 8; >>>>>> ????????unsigned SubclassData : 24; >>>>>> ????????unsigned KungFuPanda; ???????// Will protect NumContainedTys from overwriting. >>>>>> ????????unsigned NumContainedTys; // Will OK. >>>>> ???Even if the gcc bug is fixed, people will be using ?older compilers with the bug >>>>> ???for years to come. ?So this field would be around essentially forever. ?Given >>>>> ???that, I don't think this is a good solution. ?If you are prepared to make the >>>>> ???class bigger, you might as well not have the fields be bitfields at all (and >>>>> ???change the order so that things are well packed). >>>>> >>>>> ???Ciao, Duncan. >>>>>> ?????-Stepan. >>>>>> >>>>>> ?????02.01.2012, 14:38, "Duncan Sands": >>>>>>> ?????Hi Stepan, >>>>>>>> ???????I tried it doesn't helps. Now it seems that ID is overwritten. 4807 unexpected failures. >>>>>>> ?????OK, thanks for the info. ?How about doing the bit fiddling yourself instead? >>>>>>> ?????I.e. rather than trying to fool the optimizers, don't use bitfields: declare >>>>>>> ?????an unsigned field IDAndSubclassData and store and load values from it using >>>>>>> ?????explicit shifts etc. ?This would then completely avoid all problems coming >>>>>>> ?????from misoptimization of bitfields (which has happened a lot historically), >>>>>>> ?????and would be less fragile than trying to fool the optimizers via some magic >>>>>>> ?????incantation. >>>>>>> >>>>>>> ?????Ciao, Duncan. >>>>>>>> ???????-Stepan. >>>>>>>> >>>>>>>> ???????02.01.2012, 14:02, "Duncan Sands": >>>>>>>>> ???????Hi Stepan, >>>>>>>>>> ?????????The problem is in Type.h. The fields in Type class are declared in next order: >>>>>>>>>> ?????????TypeID ID : 8; >>>>>>>>>> ?????????unsigned SubclassData : 24; >>>>>>>>>> ?????????unsigned NumContainedTys; >>>>>>>>> ???????does the problem still occur if you flip the order of ID and SubclassData? >>>>>>>>> ???????I.e. >>>>>>>>> ???????????unsigned SubclassData : 24; >>>>>>>>> ???????????TypeID ID : 8; >>>>>>>>> ???????????unsigned NumContainedTys; >>>>>>>>> ???????? >>>>>>>>> ???????Ciao, Duncan. >>>>>>>>>> ?????????Attempt to set new SubclassData value rewrites lowest byte in NumContainedTys >>>>>>>>>> ?????????when -Os is set. GCC bug? Anyway setting SubclassData with two workaround >>>>>>>>>> ?????????strings fixes the problem: >>>>>>>>>> >>>>>>>>>> ?????????void setSubclassData(unsigned val) { >>>>>>>>>> ?????????unsigned tmp = NumContainedTys; // Workaround for GCC -Os >>>>>>>>>> ?????????SubclassData = val; >>>>>>>>>> ?????????NumContainedTys = tmp; // Workaround for GCC -Os >>>>>>>>>> ?????????// Ensure we don't have any accidental truncation. >>>>>>>>>> ?????????assert(SubclassData == val&& ???????"Subclass data too large for field"); >>>>>>>>>> ?????????} >>>>>>>>>> >>>>>>>>>> ?????????Probably there is another ways to protect NumContainedTys from overwritting? >>>>>>>>>> >>>>>>>>>> ?????????Please find the patch in attachment for review. >>>>>>>>>> >>>>>>>>>> ?????????-Stepan. >>>>>>>>>> >>>>>>>>>> ?????????_______________________________________________ >>>>>>>>>> ?????????llvm-commits mailing list >>>>>>>>>> ?????????llvm-commits at cs.uiuc.edu >>>>>>>>>> ?????????http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits >>>>>>>>> ???????_______________________________________________ >>>>>>>>> ???????llvm-commits mailing list >>>>>>>>> ???????llvm-commits at cs.uiuc.edu >>>>>>>>> ???????http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From baldrick at free.fr Tue Jan 3 02:51:54 2012 From: baldrick at free.fr (Duncan Sands) Date: Tue, 03 Jan 2012 09:51:54 +0100 Subject: [llvm-commits] [LLVM, PR11652 PATCH]: Fixed Bug 11652 - assertion failures when Type.cpp is compiled with -Os In-Reply-To: <673781325580638@web123.yandex.ru> References: <4EFE13EC.2010801@narod.ru> <4F0180C5.1080206@free.fr> <191841325500240@web28.yandex.ru> <4F018912.3000107@free.fr> <200971325501753@web58.yandex.ru> <4F018F55.1040604@free.fr> <1136931325507957@web94.yandex.ru> <4F01CC81.4010909@free.fr> <359001325533597@web8.yandex.ru> <4F02BD1B.7070808@free.fr> <673781325580638@web123.yandex.ru> Message-ID: <4F02C1AA.1080707@free.fr> Hi Stepan, > Hi Duncan, can I use DataTypes.h instead? this patch doesn't require either. It is the next patch that needs it, right? Ciao, Duncan. > -Stepan. > > 03.01.2012, 12:32, "Duncan Sands": >> Hi Stepan, this looks fine except for a pointless include of stdint.h. Please >> apply, except for the include. >> >> Thanks for doing this, >> >> Duncan. >> >>> Hi, Duncan. Please find the first patch in attachment. Replacement: ID with getTypeID(). >>> - Stepan >>> >>> 02.01.2012, 19:25, "Duncan Sands": >>>> Hi Stepan, >>>>> OK. Please look at patch in attachment. >>>>> I'm not sure that it is better than previous patch. Probably the first one looks like a workaround, but it changes setSubclassData only. New patch changes set/getSubclassData set/getTypeID, and all methods that uses ID. >>>> thanks for doing this. I think it is a better abstraction to have getters >>>> and setters for ID, like the ones that already exist for SubclassData. Can >>>> you therefore split the patch in two: one patch that adds getters and setters, >>>> and then a second one that drops the bitfield in favour of explicit bit >>>> fiddling. >>>> >>>> Additional comments: >>>> - you made some lines too long (> 80 columns). >>>> - this is not your fault, but I think there should be a check that ID values >>>> fit in the allocated space, for example by checking somehow that there is >>>> enough room for every value of the TypeID type. Alternatively, in setTypeID >>>> check that the value you read back out matches the value put in. The >>>> constructor can also set the ID. It should probably initialize >>>> IDAndSubclassData to zero, and then call setTypeID in the body of the >>>> constructor to set the value. >>>> >>>> Ciao, Duncan. >>>>> -Stepan. >>>>> >>>>> 02.01.2012, 15:04, "Duncan Sands": >>>>>> Hi Stepan, >>>>>>> ID is used very extensively in Type.h. We need to fix a lots, so we need to fix all methods like: >>>>>>> bool isIntegerTy() const { return ID == IntegerTyID; } >>>>>> you could turn ID into a private method that extracts the id part of the field. >>>>>> Then you just need to turn ID into ID() in places such as isIntegerTy. Likewise >>>>>> for SubclassData. >>>>>>> But in the same time we can apply some working decision until gcc bug will fixed. >>>>>>> May be add some dummy field? >>>>>>> TypeID ID : 8; >>>>>>> unsigned SubclassData : 24; >>>>>>> unsigned KungFuPanda; // Will protect NumContainedTys from overwriting. >>>>>>> unsigned NumContainedTys; // Will OK. >>>>>> Even if the gcc bug is fixed, people will be using older compilers with the bug >>>>>> for years to come. So this field would be around essentially forever. Given >>>>>> that, I don't think this is a good solution. If you are prepared to make the >>>>>> class bigger, you might as well not have the fields be bitfields at all (and >>>>>> change the order so that things are well packed). >>>>>> >>>>>> Ciao, Duncan. >>>>>>> -Stepan. >>>>>>> >>>>>>> 02.01.2012, 14:38, "Duncan Sands": >>>>>>>> Hi Stepan, >>>>>>>>> I tried it doesn't helps. Now it seems that ID is overwritten. 4807 unexpected failures. >>>>>>>> OK, thanks for the info. How about doing the bit fiddling yourself instead? >>>>>>>> I.e. rather than trying to fool the optimizers, don't use bitfields: declare >>>>>>>> an unsigned field IDAndSubclassData and store and load values from it using >>>>>>>> explicit shifts etc. This would then completely avoid all problems coming >>>>>>>> from misoptimization of bitfields (which has happened a lot historically), >>>>>>>> and would be less fragile than trying to fool the optimizers via some magic >>>>>>>> incantation. >>>>>>>> >>>>>>>> Ciao, Duncan. >>>>>>>>> -Stepan. >>>>>>>>> >>>>>>>>> 02.01.2012, 14:02, "Duncan Sands": >>>>>>>>>> Hi Stepan, >>>>>>>>>>> The problem is in Type.h. The fields in Type class are declared in next order: >>>>>>>>>>> TypeID ID : 8; >>>>>>>>>>> unsigned SubclassData : 24; >>>>>>>>>>> unsigned NumContainedTys; >>>>>>>>>> does the problem still occur if you flip the order of ID and SubclassData? >>>>>>>>>> I.e. >>>>>>>>>> unsigned SubclassData : 24; >>>>>>>>>> TypeID ID : 8; >>>>>>>>>> unsigned NumContainedTys; >>>>>>>>>> ? >>>>>>>>>> Ciao, Duncan. >>>>>>>>>>> Attempt to set new SubclassData value rewrites lowest byte in NumContainedTys >>>>>>>>>>> when -Os is set. GCC bug? Anyway setting SubclassData with two workaround >>>>>>>>>>> strings fixes the problem: >>>>>>>>>>> >>>>>>>>>>> void setSubclassData(unsigned val) { >>>>>>>>>>> unsigned tmp = NumContainedTys; // Workaround for GCC -Os >>>>>>>>>>> SubclassData = val; >>>>>>>>>>> NumContainedTys = tmp; // Workaround for GCC -Os >>>>>>>>>>> // Ensure we don't have any accidental truncation. >>>>>>>>>>> assert(SubclassData == val&& "Subclass data too large for field"); >>>>>>>>>>> } >>>>>>>>>>> >>>>>>>>>>> Probably there is another ways to protect NumContainedTys from overwritting? >>>>>>>>>>> >>>>>>>>>>> Please find the patch in attachment for review. >>>>>>>>>>> >>>>>>>>>>> -Stepan. >>>>>>>>>>> >>>>>>>>>>> _______________________________________________ >>>>>>>>>>> llvm-commits mailing list >>>>>>>>>>> llvm-commits at cs.uiuc.edu >>>>>>>>>>> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits >>>>>>>>>> _______________________________________________ >>>>>>>>>> llvm-commits mailing list >>>>>>>>>> llvm-commits at cs.uiuc.edu >>>>>>>>>> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From elena.demikhovsky at intel.com Tue Jan 3 03:06:59 2012 From: elena.demikhovsky at intel.com (Demikhovsky, Elena) Date: Tue, 3 Jan 2012 09:06:59 +0000 Subject: [llvm-commits] [llvm] r147399 - in /llvm/trunk: lib/CodeGen/SelectionDAG/LegalizeDAG.cpp test/CodeGen/X86/avx-shuffle-x86_32.ll Please review In-Reply-To: References: <20120101162247.B625F2A6C12C@llvm.org> <4F009B73.70103@gmail.com> Message-ID: Eli, You are right about the mask. I fixed it. Please look again. - Elena -----Original Message----- From: Eli Friedman [mailto:eli.friedman at gmail.com] Sent: Monday, January 02, 2012 19:57 To: Demikhovsky, Elena Cc: Rafael ?vila de Esp?ndola; llvm-commits at cs.uiuc.edu Subject: Re: [llvm-commits] [llvm] r147399 - in /llvm/trunk: lib/CodeGen/SelectionDAG/LegalizeDAG.cpp test/CodeGen/X86/avx-shuffle-x86_32.ll Please review 2012/1/2 Demikhovsky, Elena : > I fixed the patch and want to commit it. > I re-checked all and CodeGen/ARM/vext.ll passes now. > > Please review. What changed to fix this patch? For the following: + // EltVT gets smaller + assert(factor > 0); + SmallVector NewMask(32U, -1); Where does the "32U" come from in "NewMask(32U, -1)"? For the following: + for (unsigned i = 0; i < VT.getVectorNumElements(); ++i) { + if (Mask[i] < 0) { + for (unsigned fi = 0; fi < factor; ++fi) + NewMask[i*factor+fi] = Mask[i]; + } + else { + for (unsigned fi = 0; fi < factor; ++fi) + NewMask[i*factor+fi] = Mask[i]*factor+fi; + } + Mask = NewMask; + } The assignment Mask = NewMask inside the loop looks very suspicious: are you sure that's correct? -Eli --------------------------------------------------------------------- Intel Israel (74) Limited This e-mail and any attachments may contain confidential material for the sole use of the intended recipient(s). Any review or distribution by others is strictly prohibited. If you are not the intended recipient, please contact the sender and delete all copies. -------------- next part -------------- A non-text attachment was scrubbed... Name: legalize_dag2.diff Type: application/octet-stream Size: 3805 bytes Desc: legalize_dag2.diff Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20120103/a4d89be8/attachment.obj From baldrick at free.fr Tue Jan 3 03:13:14 2012 From: baldrick at free.fr (Duncan Sands) Date: Tue, 03 Jan 2012 10:13:14 +0100 Subject: [llvm-commits] [llvm] r147399 - in /llvm/trunk: lib/CodeGen/SelectionDAG/LegalizeDAG.cpp test/CodeGen/X86/avx-shuffle-x86_32.ll Please review In-Reply-To: References: <20120101162247.B625F2A6C12C@llvm.org> <4F009B73.70103@gmail.com> Message-ID: <4F02C6AA.2070907@free.fr> Hi Elena, what about his other comments? In particular I too would have liked to know what was wrong in the first version, i.e. what change "I fixed the patch" was referring to. Ciao, Duncan. > You are right about the mask. I fixed it. > Please look again. > > > - Elena > > -----Original Message----- > From: Eli Friedman [mailto:eli.friedman at gmail.com] > Sent: Monday, January 02, 2012 19:57 > To: Demikhovsky, Elena > Cc: Rafael ?vila de Esp?ndola; llvm-commits at cs.uiuc.edu > Subject: Re: [llvm-commits] [llvm] r147399 - in /llvm/trunk: lib/CodeGen/SelectionDAG/LegalizeDAG.cpp test/CodeGen/X86/avx-shuffle-x86_32.ll Please review > > 2012/1/2 Demikhovsky, Elena: >> I fixed the patch and want to commit it. >> I re-checked all and CodeGen/ARM/vext.ll passes now. >> >> Please review. > > What changed to fix this patch? > > For the following: > + // EltVT gets smaller > + assert(factor> 0); > + SmallVector NewMask(32U, -1); > > Where does the "32U" come from in "NewMask(32U, -1)"? > > For the following: > + for (unsigned i = 0; i< VT.getVectorNumElements(); ++i) { > + if (Mask[i]< 0) { > + for (unsigned fi = 0; fi< factor; ++fi) > + NewMask[i*factor+fi] = Mask[i]; > + } > + else { > + for (unsigned fi = 0; fi< factor; ++fi) > + NewMask[i*factor+fi] = Mask[i]*factor+fi; > + } > + Mask = NewMask; > + } > > The assignment Mask = NewMask inside the loop looks very suspicious: > are you sure that's correct? > > -Eli > --------------------------------------------------------------------- > Intel Israel (74) Limited > > This e-mail and any attachments may contain confidential material for > the sole use of the intended recipient(s). Any review or distribution > by others is strictly prohibited. If you are not the intended > recipient, please contact the sender and delete all copies. > > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From elena.demikhovsky at intel.com Tue Jan 3 03:35:29 2012 From: elena.demikhovsky at intel.com (Demikhovsky, Elena) Date: Tue, 3 Jan 2012 09:35:29 +0000 Subject: [llvm-commits] [llvm] r147399 - in /llvm/trunk: lib/CodeGen/SelectionDAG/LegalizeDAG.cpp test/CodeGen/X86/avx-shuffle-x86_32.ll Please review In-Reply-To: <4F02C6AA.2070907@free.fr> References: <20120101162247.B625F2A6C12C@llvm.org> <4F009B73.70103@gmail.com> <4F02C6AA.2070907@free.fr> Message-ID: This is the original code that converts VECTOR_SHUFFLE that can be lowered to BUILD_VECTOR. if (!TLI.isTypeLegal(EltVT)) { EVT EltVT = TLI.getTypeToTransformTo(*DAG.getContext(), EltVT); } The code failed with assertion on Win32 because "i64" was transfromed to "i32" and BUILD_VECTOR has illegal form. In the first patch I assumed that the legal type is always smaller than original and this assumption was wrong. In this patch I check that "i64" > "i32" and then rebuild "shuffle" before transforming it to BUILD_VECTOR. The "rebuild" means that I convert v4i64 shuffle operation to v8i32 and convert the mask. If the original mask was 5 -1 2 4 the new mask will be 10, 11, -1, -1, 4, 5, 8, 9 - Elena -----Original Message----- From: llvm-commits-bounces at cs.uiuc.edu [mailto:llvm-commits-bounces at cs.uiuc.edu] On Behalf Of Duncan Sands Sent: Tuesday, January 03, 2012 11:13 To: llvm-commits at cs.uiuc.edu Subject: Re: [llvm-commits] [llvm] r147399 - in /llvm/trunk: lib/CodeGen/SelectionDAG/LegalizeDAG.cpp test/CodeGen/X86/avx-shuffle-x86_32.ll Please review Hi Elena, what about his other comments? In particular I too would have liked to know what was wrong in the first version, i.e. what change "I fixed the patch" was referring to. Ciao, Duncan. > You are right about the mask. I fixed it. > Please look again. > > > - Elena > > -----Original Message----- > From: Eli Friedman [mailto:eli.friedman at gmail.com] > Sent: Monday, January 02, 2012 19:57 > To: Demikhovsky, Elena > Cc: Rafael ?vila de Esp?ndola; llvm-commits at cs.uiuc.edu > Subject: Re: [llvm-commits] [llvm] r147399 - in /llvm/trunk: lib/CodeGen/SelectionDAG/LegalizeDAG.cpp test/CodeGen/X86/avx-shuffle-x86_32.ll Please review > > 2012/1/2 Demikhovsky, Elena: >> I fixed the patch and want to commit it. >> I re-checked all and CodeGen/ARM/vext.ll passes now. >> >> Please review. > > What changed to fix this patch? > > For the following: > + // EltVT gets smaller > + assert(factor> 0); > + SmallVector NewMask(32U, -1); > > Where does the "32U" come from in "NewMask(32U, -1)"? > > For the following: > + for (unsigned i = 0; i< VT.getVectorNumElements(); ++i) { > + if (Mask[i]< 0) { > + for (unsigned fi = 0; fi< factor; ++fi) > + NewMask[i*factor+fi] = Mask[i]; > + } > + else { > + for (unsigned fi = 0; fi< factor; ++fi) > + NewMask[i*factor+fi] = Mask[i]*factor+fi; > + } > + Mask = NewMask; > + } > > The assignment Mask = NewMask inside the loop looks very suspicious: > are you sure that's correct? > > -Eli > --------------------------------------------------------------------- > Intel Israel (74) Limited > > This e-mail and any attachments may contain confidential material for > the sole use of the intended recipient(s). Any review or distribution > by others is strictly prohibited. If you are not the intended > recipient, please contact the sender and delete all copies. > > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits _______________________________________________ llvm-commits mailing list llvm-commits at cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits --------------------------------------------------------------------- Intel Israel (74) Limited This e-mail and any attachments may contain confidential material for the sole use of the intended recipient(s). Any review or distribution by others is strictly prohibited. If you are not the intended recipient, please contact the sender and delete all copies. From grosser at fim.uni-passau.de Tue Jan 3 03:50:29 2012 From: grosser at fim.uni-passau.de (Tobias Grosser) Date: Tue, 03 Jan 2012 09:50:29 -0000 Subject: [llvm-commits] [polly] r147442 - /polly/trunk/www/publications.html Message-ID: <20120103095029.A2ECD2A6C12C@llvm.org> Author: grosser Date: Tue Jan 3 03:50:29 2012 New Revision: 147442 URL: http://llvm.org/viewvc/llvm-project?rev=147442&view=rev Log: Update publications - Add the LLVM Developer Meeting 2012 talk - Add papers used within Polly and papers interesting to read in general Modified: polly/trunk/www/publications.html Modified: polly/trunk/www/publications.html URL: http://llvm.org/viewvc/llvm-project/polly/trunk/www/publications.html?rev=147442&r1=147441&r2=147442&view=diff ============================================================================== --- polly/trunk/www/publications.html (original) +++ polly/trunk/www/publications.html Tue Jan 3 03:50:29 2012 @@ -15,8 +15,17 @@

Polly: Publications

-

2011

+

Publications involving Polly

+

2011

    +
  • Polly - First Successful Optimizations - How to proceed?
    + Tobias Grosser, Ragesh A
    + LLVM Developer Meeting 2011
    Slides, Video + (Computer), Video + (Mobile)
  • A Framework for Automatic OpenMP Code Generation
    Raghesh A
    Masters Thesis (May 2011)
    @@ -38,17 +47,66 @@ href="publications/grosser-impact-2011-slides.pdf">Slides
-

2010

+

2010

+ +

Publications used within Polly

+

Polyhedral library

+
    +
  • isl: An Integer Set Library for the Polyhedral Model
    + Sven Verdoolaege
    + ICMS 2010 +
    • +
+

Optimization

+
    +
  • A Practical Automatic Polyhedral Parallelizer and Locality Optimizer +
    + Uday Bondhugula, Alberto Hartono, J. Ramanujam, P. Sadayappan
    + PLDI 2008 +
    • +
+

Code Generation

+
    +
  • Code Generation in the Polyhedral Model Is Easier Than You Think +
    + Cedric Bastoul
    + PACT 2004 +
    • +
+

Interesting Publications

+ + Publications that are not yet used or implemented in Polly, but that are + interesting to look at either to understand general concepts or to implement + the corresponding ideas. This list is incomplete and papers are added as + we hear about them.
+

GPGPU

+
    +
  • Automatic C-to-CUDA Code Generation for Affine Programs +
    + Muthu Manikandan Baskaran, J. Ramanujam and P. Sadayappan
    + CC 2010 +
    • +
+

Vectorization

+
    +
  • Joint Scheduling and Layout Optimization to Enable Multi-Level + Vectorization +
    + Nicolas Vasilache, Benoit Meister, Muthu Baskaran, Richard Lethin
    + IMPACT 2012 (upcoming) +
    • +
+ From grosser at fim.uni-passau.de Tue Jan 3 04:00:55 2012 From: grosser at fim.uni-passau.de (Tobias Grosser) Date: Tue, 03 Jan 2012 10:00:55 -0000 Subject: [llvm-commits] [polly] r147443 - /polly/trunk/www/publications.html Message-ID: <20120103100055.7C9232A6C12C@llvm.org> Author: grosser Date: Tue Jan 3 04:00:55 2012 New Revision: 147443 URL: http://llvm.org/viewvc/llvm-project?rev=147443&view=rev Log: Add Udays PhD thesis Modified: polly/trunk/www/publications.html Modified: polly/trunk/www/publications.html URL: http://llvm.org/viewvc/llvm-project/polly/trunk/www/publications.html?rev=147443&r1=147442&r2=147443&view=diff ============================================================================== --- polly/trunk/www/publications.html (original) +++ polly/trunk/www/publications.html Tue Jan 3 04:00:55 2012 @@ -74,6 +74,12 @@ Uday Bondhugula, Alberto Hartono, J. Ramanujam, P. Sadayappan
PLDI 2008 +
  • Effective Automatic Parallelization and Locality Optimization using + the Polyhedral Model +
    + Uday Bondhugula
    + PhD thesis 2008 +

    • Code Generation

      From grosser at fim.uni-passau.de Tue Jan 3 04:10:05 2012 From: grosser at fim.uni-passau.de (Tobias Grosser) Date: Tue, 03 Jan 2012 10:10:05 -0000 Subject: [llvm-commits] [polly] r147444 - /polly/trunk/www/publications.html Message-ID: <20120103101005.D937C2A6C12C@llvm.org> Author: grosser Date: Tue Jan 3 04:10:05 2012 New Revision: 147444 URL: http://llvm.org/viewvc/llvm-project?rev=147444&view=rev Log: www: Papers about iterative compilation and non static control Modified: polly/trunk/www/publications.html Modified: polly/trunk/www/publications.html URL: http://llvm.org/viewvc/llvm-project/polly/trunk/www/publications.html?rev=147444&r1=147443&r2=147444&view=diff ============================================================================== --- polly/trunk/www/publications.html (original) +++ polly/trunk/www/publications.html Tue Jan 3 04:10:05 2012 @@ -112,7 +112,30 @@ IMPACT 2012 (upcoming)
    - +

    Iterative Compilation

    +
      +
    • Iterative optimization in the polyhedral model: Part I, + one-dimensional time. +
      + Louis-Noel Pouchet, Cedric Bastoul, Albert Cohen and Nicolas Vasilache
      + CGO 2007 +
      • +
    • Iterative optimization in the polyhedral model: Part II, + multidimensional time. +
      + Louis-Noel Pouchet, Cedric Bastoul, Albert Cohen and John Cavazos
      + PLDI 2008 +
      • +
    +

    Non-static Control

    +
      +
    • The Polyhedral Model Is More Widely Applicable Than You Think +
      + Mohamed-Walid Benabderrahmane, Louis-No??l Pouchet, Albert Cohen, C??dric + Bastoul.
      + CC 2010 +
      • +
    From eli.friedman at gmail.com Tue Jan 3 04:33:24 2012 From: eli.friedman at gmail.com (Eli Friedman) Date: Tue, 3 Jan 2012 02:33:24 -0800 Subject: [llvm-commits] [llvm] r147399 - in /llvm/trunk: lib/CodeGen/SelectionDAG/LegalizeDAG.cpp test/CodeGen/X86/avx-shuffle-x86_32.ll Please review In-Reply-To: References: <20120101162247.B625F2A6C12C@llvm.org> <4F009B73.70103@gmail.com> Message-ID: + SmallVector Mask(32U, -1); cast(Node)->getMask(Mask); What's the point of initializing the vector when it gets rebuilt in the next line? + if (NewEltVT.bitsLT(EltVT)) { It might be worth a short comment noting that BUILD_VECTOR operands are allowed to be wider than the element type. + // Convert shuffle node. + // If original node was v4i64 and the new EltVT is i32, + // cast operands to v8i32 and re-build the mask. "For example, if the original node was..." Please commit with those changes. -Eli On Tue, Jan 3, 2012 at 1:06 AM, Demikhovsky, Elena wrote: > Eli, > You are right about the mask. I fixed it. > Please look again. > > > - Elena > > -----Original Message----- > From: Eli Friedman [mailto:eli.friedman at gmail.com] > Sent: Monday, January 02, 2012 19:57 > To: Demikhovsky, Elena > Cc: Rafael ?vila de Esp?ndola; llvm-commits at cs.uiuc.edu > Subject: Re: [llvm-commits] [llvm] r147399 - in /llvm/trunk: lib/CodeGen/SelectionDAG/LegalizeDAG.cpp test/CodeGen/X86/avx-shuffle-x86_32.ll Please review > > 2012/1/2 Demikhovsky, Elena : >> I fixed the patch and want to commit it. >> I re-checked all and CodeGen/ARM/vext.ll passes now. >> >> Please review. > > What changed to fix this patch? > > For the following: > + ? ? ? ?// EltVT gets smaller > + ? ? ? ?assert(factor > 0); > + ? ? ? ?SmallVector NewMask(32U, -1); > > Where does the "32U" come from in "NewMask(32U, -1)"? > > For the following: > + ? ? ? ?for (unsigned i = 0; i < VT.getVectorNumElements(); ++i) { > + ? ? ? ? ?if (Mask[i] < 0) { > + ? ? ? ? ? ?for (unsigned fi = 0; fi < factor; ++fi) > + ? ? ? ? ? ? ?NewMask[i*factor+fi] = Mask[i]; > + ? ? ? ? ?} > + ? ? ? ? ?else { > + ? ? ? ? ? ?for (unsigned fi = 0; fi < factor; ++fi) > + ? ? ? ? ? ? ?NewMask[i*factor+fi] = Mask[i]*factor+fi; > + ? ? ? ? ?} > + ? ? ? ? ?Mask = NewMask; > + ? ? ? ?} > > The assignment Mask = NewMask inside the loop looks very suspicious: > are you sure that's correct? > > -Eli > --------------------------------------------------------------------- > Intel Israel (74) Limited > > This e-mail and any attachments may contain confidential material for > the sole use of the intended recipient(s). Any review or distribution > by others is strictly prohibited. If you are not the intended > recipient, please contact the sender and delete all copies. From elena.demikhovsky at intel.com Tue Jan 3 05:59:05 2012 From: elena.demikhovsky at intel.com (Elena Demikhovsky) Date: Tue, 03 Jan 2012 11:59:05 -0000 Subject: [llvm-commits] [llvm] r147445 - in /llvm/trunk: lib/CodeGen/SelectionDAG/LegalizeDAG.cpp test/CodeGen/X86/avx-shuffle-x86_32.ll Message-ID: <20120103115905.4438A2A6C12C@llvm.org> Author: delena Date: Tue Jan 3 05:59:04 2012 New Revision: 147445 URL: http://llvm.org/viewvc/llvm-project?rev=147445&view=rev Log: Fixed a bug in SelectionDAG.cpp. The failure seen on win32, when i64 type is illegal. It happens on stage of conversion VECTOR_SHUFFLE to BUILD_VECTOR. The failure message is: llc: SelectionDAG.cpp:784: void VerifyNodeCommon(llvm::SDNode*): Assertion `(I->getValueType() == EltVT || (EltVT.isInteger() && I->getValueType().isInteger() && EltVT.bitsLE(I->getValueType()))) && "Wrong operand type!"' failed. I added a special test that checks vector shuffle on win32. Added: llvm/trunk/test/CodeGen/X86/avx-shuffle-x86_32.ll (with props) Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp?rev=147445&r1=147444&r2=147445&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Tue Jan 3 05:59:04 2012 @@ -2795,15 +2795,58 @@ Node->getOperand(2), dl)); break; case ISD::VECTOR_SHUFFLE: { - SmallVector Mask; + SmallVector Mask; cast(Node)->getMask(Mask); EVT VT = Node->getValueType(0); EVT EltVT = VT.getVectorElementType(); - if (!TLI.isTypeLegal(EltVT)) - EltVT = TLI.getTypeToTransformTo(*DAG.getContext(), EltVT); + SDValue Op0 = Node->getOperand(0); + SDValue Op1 = Node->getOperand(1); + if (!TLI.isTypeLegal(EltVT)) { + + EVT NewEltVT = TLI.getTypeToTransformTo(*DAG.getContext(), EltVT); + + // BUILD_VECTOR operands are allowed to be wider than the element type. + // But if NewEltVT is smaller that EltVT the BUILD_VECTOR does not accept it + if (NewEltVT.bitsLT(EltVT)) { + + // Convert shuffle node. + // If original node was v4i64 and the new EltVT is i32, + // cast operands to v8i32 and re-build the mask. + + // Calculate new VT, the size of the new VT should be equal to original. + EVT NewVT = EVT::getVectorVT(*DAG.getContext(), NewEltVT, + VT.getSizeInBits()/NewEltVT.getSizeInBits()); + assert(NewVT.bitsEq(VT)); + + // cast operands to new VT + Op0 = DAG.getNode(ISD::BITCAST, dl, NewVT, Op0); + Op1 = DAG.getNode(ISD::BITCAST, dl, NewVT, Op1); + + // Convert the shuffle mask + unsigned int factor = NewVT.getVectorNumElements()/VT.getVectorNumElements(); + + // EltVT gets smaller + assert(factor > 0); + SmallVector NewMask; + + for (unsigned i = 0; i < VT.getVectorNumElements(); ++i) { + if (Mask[i] < 0) { + for (unsigned fi = 0; fi < factor; ++fi) + NewMask.push_back(Mask[i]); + } + else { + for (unsigned fi = 0; fi < factor; ++fi) + NewMask.push_back(Mask[i]*factor+fi); + } + } + Mask = NewMask; + VT = NewVT; + } + EltVT = NewEltVT; + } unsigned NumElems = VT.getVectorNumElements(); - SmallVector Ops; + SmallVector Ops; for (unsigned i = 0; i != NumElems; ++i) { if (Mask[i] < 0) { Ops.push_back(DAG.getUNDEF(EltVT)); @@ -2812,13 +2855,14 @@ unsigned Idx = Mask[i]; if (Idx < NumElems) Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, - Node->getOperand(0), + Op0, DAG.getIntPtrConstant(Idx))); else Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, - Node->getOperand(1), + Op1, DAG.getIntPtrConstant(Idx - NumElems))); } + Tmp1 = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &Ops[0], Ops.size()); Results.push_back(Tmp1); break; Added: llvm/trunk/test/CodeGen/X86/avx-shuffle-x86_32.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx-shuffle-x86_32.ll?rev=147445&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/X86/avx-shuffle-x86_32.ll (added) +++ llvm/trunk/test/CodeGen/X86/avx-shuffle-x86_32.ll Tue Jan 3 05:59:04 2012 @@ -0,0 +1,8 @@ +; RUN: llc < %s -mtriple=i686-pc-win32 -mcpu=corei7-avx -mattr=+avx | FileCheck %s + +define <4 x i64> @test1(<4 x i64> %a) nounwind { + %b = shufflevector <4 x i64> %a, <4 x i64> undef, <4 x i32> + ret <4 x i64>%b + ; CHECK test1: + ; CHECK: vinsertf128 + } Propchange: llvm/trunk/test/CodeGen/X86/avx-shuffle-x86_32.ll ------------------------------------------------------------------------------ svn:executable = * From stpworld at narod.ru Tue Jan 3 08:05:04 2012 From: stpworld at narod.ru (Stepan Dyatkovskiy) Date: Tue, 03 Jan 2012 14:05:04 -0000 Subject: [llvm-commits] [llvm] r147446 - in /llvm/trunk: include/llvm/Type.h lib/VMCore/Type.cpp Message-ID: <20120103140504.469EF1BE003@llvm.org> Author: dyatkovskiy Date: Tue Jan 3 08:05:04 2012 New Revision: 147446 URL: http://llvm.org/viewvc/llvm-project?rev=147446&view=rev Log: Type: replaced usage of ID with getTypeID(). Modified: llvm/trunk/include/llvm/Type.h llvm/trunk/lib/VMCore/Type.cpp Modified: llvm/trunk/include/llvm/Type.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Type.h?rev=147446&r1=147445&r2=147446&view=diff ============================================================================== --- llvm/trunk/include/llvm/Type.h (original) +++ llvm/trunk/include/llvm/Type.h Tue Jan 3 08:05:04 2012 @@ -120,49 +120,51 @@ TypeID getTypeID() const { return ID; } /// isVoidTy - Return true if this is 'void'. - bool isVoidTy() const { return ID == VoidTyID; } + bool isVoidTy() const { return getTypeID() == VoidTyID; } /// isHalfTy - Return true if this is 'half', a 16-bit IEEE fp type. - bool isHalfTy() const { return ID == HalfTyID; } + bool isHalfTy() const { return getTypeID() == HalfTyID; } /// isFloatTy - Return true if this is 'float', a 32-bit IEEE fp type. - bool isFloatTy() const { return ID == FloatTyID; } + bool isFloatTy() const { return getTypeID() == FloatTyID; } /// isDoubleTy - Return true if this is 'double', a 64-bit IEEE fp type. - bool isDoubleTy() const { return ID == DoubleTyID; } + bool isDoubleTy() const { return getTypeID() == DoubleTyID; } /// isX86_FP80Ty - Return true if this is x86 long double. - bool isX86_FP80Ty() const { return ID == X86_FP80TyID; } + bool isX86_FP80Ty() const { return getTypeID() == X86_FP80TyID; } /// isFP128Ty - Return true if this is 'fp128'. - bool isFP128Ty() const { return ID == FP128TyID; } + bool isFP128Ty() const { return getTypeID() == FP128TyID; } /// isPPC_FP128Ty - Return true if this is powerpc long double. - bool isPPC_FP128Ty() const { return ID == PPC_FP128TyID; } + bool isPPC_FP128Ty() const { return getTypeID() == PPC_FP128TyID; } /// isFloatingPointTy - Return true if this is one of the five floating point /// types bool isFloatingPointTy() const { - return ID == HalfTyID || ID == FloatTyID || ID == DoubleTyID || - ID == X86_FP80TyID || ID == FP128TyID || ID == PPC_FP128TyID; + return getTypeID() == HalfTyID || getTypeID() == FloatTyID || + getTypeID() == DoubleTyID || + getTypeID() == X86_FP80TyID || getTypeID() == FP128TyID || + getTypeID() == PPC_FP128TyID; } /// isX86_MMXTy - Return true if this is X86 MMX. - bool isX86_MMXTy() const { return ID == X86_MMXTyID; } + bool isX86_MMXTy() const { return getTypeID() == X86_MMXTyID; } /// isFPOrFPVectorTy - Return true if this is a FP type or a vector of FP. /// bool isFPOrFPVectorTy() const; /// isLabelTy - Return true if this is 'label'. - bool isLabelTy() const { return ID == LabelTyID; } + bool isLabelTy() const { return getTypeID() == LabelTyID; } /// isMetadataTy - Return true if this is 'metadata'. - bool isMetadataTy() const { return ID == MetadataTyID; } + bool isMetadataTy() const { return getTypeID() == MetadataTyID; } /// isIntegerTy - True if this is an instance of IntegerType. /// - bool isIntegerTy() const { return ID == IntegerTyID; } + bool isIntegerTy() const { return getTypeID() == IntegerTyID; } /// isIntegerTy - Return true if this is an IntegerType of the given width. bool isIntegerTy(unsigned Bitwidth) const; @@ -174,23 +176,23 @@ /// isFunctionTy - True if this is an instance of FunctionType. /// - bool isFunctionTy() const { return ID == FunctionTyID; } + bool isFunctionTy() const { return getTypeID() == FunctionTyID; } /// isStructTy - True if this is an instance of StructType. /// - bool isStructTy() const { return ID == StructTyID; } + bool isStructTy() const { return getTypeID() == StructTyID; } /// isArrayTy - True if this is an instance of ArrayType. /// - bool isArrayTy() const { return ID == ArrayTyID; } + bool isArrayTy() const { return getTypeID() == ArrayTyID; } /// isPointerTy - True if this is an instance of PointerType. /// - bool isPointerTy() const { return ID == PointerTyID; } + bool isPointerTy() const { return getTypeID() == PointerTyID; } /// isVectorTy - True if this is an instance of VectorType. /// - bool isVectorTy() const { return ID == VectorTyID; } + bool isVectorTy() const { return getTypeID() == VectorTyID; } /// canLosslesslyBitCastTo - Return true if this type could be converted /// with a lossless BitCast to type 'Ty'. For example, i8* to i32*. BitCasts @@ -206,14 +208,14 @@ /// Here are some useful little methods to query what type derived types are /// Note that all other types can just compare to see if this == Type::xxxTy; /// - bool isPrimitiveType() const { return ID <= LastPrimitiveTyID; } - bool isDerivedType() const { return ID >= FirstDerivedTyID; } + bool isPrimitiveType() const { return getTypeID() <= LastPrimitiveTyID; } + bool isDerivedType() const { return getTypeID() >= FirstDerivedTyID; } /// isFirstClassType - Return true if the type is "first class", meaning it /// is a valid type for a Value. /// bool isFirstClassType() const { - return ID != FunctionTyID && ID != VoidTyID; + return getTypeID() != FunctionTyID && getTypeID() != VoidTyID; } /// isSingleValueType - Return true if the type is a valid type for a @@ -221,8 +223,9 @@ /// and array types. /// bool isSingleValueType() const { - return (ID != VoidTyID && isPrimitiveType()) || - ID == IntegerTyID || ID == PointerTyID || ID == VectorTyID; + return (getTypeID() != VoidTyID && isPrimitiveType()) || + getTypeID() == IntegerTyID || getTypeID() == PointerTyID || + getTypeID() == VectorTyID; } /// isAggregateType - Return true if the type is an aggregate type. This @@ -231,7 +234,7 @@ /// does not include vector types. /// bool isAggregateType() const { - return ID == StructTyID || ID == ArrayTyID; + return getTypeID() == StructTyID || getTypeID() == ArrayTyID; } /// isSized - Return true if it makes sense to take the size of this type. To @@ -240,12 +243,14 @@ /// bool isSized() const { // If it's a primitive, it is always sized. - if (ID == IntegerTyID || isFloatingPointTy() || ID == PointerTyID || - ID == X86_MMXTyID) + if (getTypeID() == IntegerTyID || isFloatingPointTy() || + getTypeID() == PointerTyID || + getTypeID() == X86_MMXTyID) return true; // If it is not something that can have a size (e.g. a function or label), // it doesn't have a size. - if (ID != StructTyID && ID != ArrayTyID && ID != VectorTyID) + if (getTypeID() != StructTyID && getTypeID() != ArrayTyID && + getTypeID() != VectorTyID) return false; // Otherwise we have to try harder to decide. return isSizedDerivedType(); Modified: llvm/trunk/lib/VMCore/Type.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/Type.cpp?rev=147446&r1=147445&r2=147446&view=diff ============================================================================== --- llvm/trunk/lib/VMCore/Type.cpp (original) +++ llvm/trunk/lib/VMCore/Type.cpp Tue Jan 3 08:05:04 2012 @@ -66,7 +66,7 @@ bool Type::isIntOrIntVectorTy() const { if (isIntegerTy()) return true; - if (ID != Type::VectorTyID) return false; + if (getTypeID() != Type::VectorTyID) return false; return cast(this)->getElementType()->isIntegerTy(); } @@ -74,11 +74,12 @@ /// isFPOrFPVectorTy - Return true if this is a FP type or a vector of FP types. /// bool Type::isFPOrFPVectorTy() const { - if (ID == Type::HalfTyID || ID == Type::FloatTyID || ID == Type::DoubleTyID || - ID == Type::FP128TyID || ID == Type::X86_FP80TyID || - ID == Type::PPC_FP128TyID) + if (getTypeID() == Type::HalfTyID || getTypeID() == Type::FloatTyID || + getTypeID() == Type::DoubleTyID || + getTypeID() == Type::FP128TyID || getTypeID() == Type::X86_FP80TyID || + getTypeID() == Type::PPC_FP128TyID) return true; - if (ID != Type::VectorTyID) return false; + if (getTypeID() != Type::VectorTyID) return false; return cast(this)->getElementType()->isFloatingPointTy(); } @@ -167,12 +168,12 @@ if (const VectorType *VTy = dyn_cast(this)) return VTy->getElementType()->getFPMantissaWidth(); assert(isFloatingPointTy() && "Not a floating point type!"); - if (ID == HalfTyID) return 11; - if (ID == FloatTyID) return 24; - if (ID == DoubleTyID) return 53; - if (ID == X86_FP80TyID) return 64; - if (ID == FP128TyID) return 113; - assert(ID == PPC_FP128TyID && "unknown fp type"); + if (getTypeID() == HalfTyID) return 11; + if (getTypeID() == FloatTyID) return 24; + if (getTypeID() == DoubleTyID) return 53; + if (getTypeID() == X86_FP80TyID) return 64; + if (getTypeID() == FP128TyID) return 113; + assert(getTypeID() == PPC_FP128TyID && "unknown fp type"); return -1; } From STPWORLD at narod.ru Tue Jan 3 08:12:43 2012 From: STPWORLD at narod.ru (Stepan Dyatkovskiy) Date: Tue, 03 Jan 2012 18:12:43 +0400 Subject: [llvm-commits] [LLVM, PR11652 PATCH]: Fixed Bug 11652 - assertion failures when Type.cpp is compiled with -Os In-Reply-To: <4F02C1AA.1080707@free.fr> References: <4EFE13EC.2010801@narod.ru> <4F0180C5.1080206@free.fr> <191841325500240@web28.yandex.ru> <4F018912.3000107@free.fr> <200971325501753@web58.yandex.ru> <4F018F55.1040604@free.fr> <1136931325507957@web94.yandex.ru> <4F01CC81.4010909@free.fr> <359001325533597@web8.yandex.ru> <4F02BD1B.7070808@free.fr> <673781325580638@web123.yandex.ru> <4F02C1AA.1080707@free.fr> Message-ID: <602271325599963@web1.yandex.ru> Oh.. of course. Commited as r147446. For next patch, did you mean that I should check that TypeID was properly stored in its 8 bits? Something like this: void setTypeID(TypeID ID) { IDAndSubclassData = (ID & 0xFF) | (IDAndSubclassData & 0xFFFFFF00); assert(IDAndSubclassData & 0xFF == ID && "Type data too large for field"); } -Stepan 03.01.2012, 12:51, "Duncan Sands" : > Hi Stepan, > >> ?Hi Duncan, can I use DataTypes.h instead? > > this patch doesn't require either. ?It is the next patch that needs it, right? > > Ciao, Duncan. > >> ?-Stepan. >> >> ?03.01.2012, 12:32, "Duncan Sands": >>> ?Hi Stepan, this looks fine except for a pointless include of stdint.h. ?Please >>> ?apply, except for the include. >>> >>> ?Thanks for doing this, >>> >>> ?Duncan. >>>> ???Hi, Duncan. Please find the first patch in attachment. Replacement: ID with getTypeID(). >>>> ???- Stepan >>>> >>>> ???02.01.2012, 19:25, "Duncan Sands": >>>>> ???Hi Stepan, >>>>>> ?????OK. Please look at patch in attachment. >>>>>> ?????I'm not sure that it is better than previous patch. Probably the first one looks like a workaround, but it changes setSubclassData only. New patch changes set/getSubclassData set/getTypeID, and all methods that uses ID. >>>>> ???thanks for doing this. ?I think it is a better abstraction to have getters >>>>> ???and setters for ID, like the ones that already exist for SubclassData. ?Can >>>>> ???you therefore split the patch in two: one patch that adds getters and setters, >>>>> ???and then a second one that drops the bitfield in favour of explicit bit >>>>> ???fiddling. >>>>> >>>>> ???Additional comments: >>>>> ???????- you made some lines too long (> ???80 columns). >>>>> ???????- this is not your fault, but I think there should be a check that ID values >>>>> ?????????fit in the allocated space, for example by checking somehow that there is >>>>> ?????????enough room for every value of the TypeID type. ?Alternatively, in setTypeID >>>>> ?????????check that the value you read back out matches the value put in. ?The >>>>> ?????????constructor can also set the ID. ?It should probably initialize >>>>> ?????????IDAndSubclassData to zero, and then call setTypeID in the body of the >>>>> ?????????constructor to set the value. >>>>> >>>>> ???Ciao, Duncan. >>>>>> ?????-Stepan. >>>>>> >>>>>> ?????02.01.2012, 15:04, "Duncan Sands": >>>>>>> ?????Hi Stepan, >>>>>>>> ???????ID is used very extensively in Type.h. We need to fix a lots, so we need to fix all methods like: >>>>>>>> ???????bool isIntegerTy() const { return ID == IntegerTyID; } >>>>>>> ?????you could turn ID into a private method that extracts the id part of the field. >>>>>>> ?????Then you just need to turn ID into ID() in places such as isIntegerTy. ?Likewise >>>>>>> ?????for SubclassData. >>>>>>>> ???????But in the same time we can apply some working decision until gcc bug will fixed. >>>>>>>> ???????May be add some dummy field? >>>>>>>> ??????????TypeID ??ID : 8; >>>>>>>> ??????????unsigned SubclassData : 24; >>>>>>>> ??????????unsigned KungFuPanda; ???????// Will protect NumContainedTys from overwriting. >>>>>>>> ??????????unsigned NumContainedTys; // Will OK. >>>>>>> ?????Even if the gcc bug is fixed, people will be using ?older compilers with the bug >>>>>>> ?????for years to come. ?So this field would be around essentially forever. ?Given >>>>>>> ?????that, I don't think this is a good solution. ?If you are prepared to make the >>>>>>> ?????class bigger, you might as well not have the fields be bitfields at all (and >>>>>>> ?????change the order so that things are well packed). >>>>>>> >>>>>>> ?????Ciao, Duncan. >>>>>>>> ???????-Stepan. >>>>>>>> >>>>>>>> ???????02.01.2012, 14:38, "Duncan Sands": >>>>>>>>> ???????Hi Stepan, >>>>>>>>>> ?????????I tried it doesn't helps. Now it seems that ID is overwritten. 4807 unexpected failures. >>>>>>>>> ???????OK, thanks for the info. ?How about doing the bit fiddling yourself instead? >>>>>>>>> ???????I.e. rather than trying to fool the optimizers, don't use bitfields: declare >>>>>>>>> ???????an unsigned field IDAndSubclassData and store and load values from it using >>>>>>>>> ???????explicit shifts etc. ?This would then completely avoid all problems coming >>>>>>>>> ???????from misoptimization of bitfields (which has happened a lot historically), >>>>>>>>> ???????and would be less fragile than trying to fool the optimizers via some magic >>>>>>>>> ???????incantation. >>>>>>>>> >>>>>>>>> ???????Ciao, Duncan. >>>>>>>>>> ?????????-Stepan. >>>>>>>>>> >>>>>>>>>> ?????????02.01.2012, 14:02, "Duncan Sands": >>>>>>>>>>> ?????????Hi Stepan, >>>>>>>>>>>> ???????????The problem is in Type.h. The fields in Type class are declared in next order: >>>>>>>>>>>> ???????????TypeID ID : 8; >>>>>>>>>>>> ???????????unsigned SubclassData : 24; >>>>>>>>>>>> ???????????unsigned NumContainedTys; >>>>>>>>>>> ?????????does the problem still occur if you flip the order of ID and SubclassData? >>>>>>>>>>> ?????????I.e. >>>>>>>>>>> ?????????????unsigned SubclassData : 24; >>>>>>>>>>> ?????????????TypeID ID : 8; >>>>>>>>>>> ?????????????unsigned NumContainedTys; >>>>>>>>>>> ?????????? >>>>>>>>>>> ?????????Ciao, Duncan. >>>>>>>>>>>> ???????????Attempt to set new SubclassData value rewrites lowest byte in NumContainedTys >>>>>>>>>>>> ???????????when -Os is set. GCC bug? Anyway setting SubclassData with two workaround >>>>>>>>>>>> ???????????strings fixes the problem: >>>>>>>>>>>> >>>>>>>>>>>> ???????????void setSubclassData(unsigned val) { >>>>>>>>>>>> ???????????unsigned tmp = NumContainedTys; // Workaround for GCC -Os >>>>>>>>>>>> ???????????SubclassData = val; >>>>>>>>>>>> ???????????NumContainedTys = tmp; // Workaround for GCC -Os >>>>>>>>>>>> ???????????// Ensure we don't have any accidental truncation. >>>>>>>>>>>> ???????????assert(SubclassData == val&& ?????????"Subclass data too large for field"); >>>>>>>>>>>> ???????????} >>>>>>>>>>>> >>>>>>>>>>>> ???????????Probably there is another ways to protect NumContainedTys from overwritting? >>>>>>>>>>>> >>>>>>>>>>>> ???????????Please find the patch in attachment for review. >>>>>>>>>>>> >>>>>>>>>>>> ???????????-Stepan. >>>>>>>>>>>> >>>>>>>>>>>> ???????????_______________________________________________ >>>>>>>>>>>> ???????????llvm-commits mailing list >>>>>>>>>>>> ???????????llvm-commits at cs.uiuc.edu >>>>>>>>>>>> ???????????http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits >>>>>>>>>>> ?????????_______________________________________________ >>>>>>>>>>> ?????????llvm-commits mailing list >>>>>>>>>>> ?????????llvm-commits at cs.uiuc.edu >>>>>>>>>>> ?????????http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From baldrick at free.fr Tue Jan 3 08:21:18 2012 From: baldrick at free.fr (Duncan Sands) Date: Tue, 03 Jan 2012 15:21:18 +0100 Subject: [llvm-commits] [LLVM, PR11652 PATCH]: Fixed Bug 11652 - assertion failures when Type.cpp is compiled with -Os In-Reply-To: <602271325599963@web1.yandex.ru> References: <4EFE13EC.2010801@narod.ru> <4F0180C5.1080206@free.fr> <191841325500240@web28.yandex.ru> <4F018912.3000107@free.fr> <200971325501753@web58.yandex.ru> <4F018F55.1040604@free.fr> <1136931325507957@web94.yandex.ru> <4F01CC81.4010909@free.fr> <359001325533597@web8.yandex.ru> <4F02BD1B.7070808@free.fr> <673781325580638@web123.yandex.ru> <4F02C1AA.1080707@free.fr> <602271325599963@web1.yandex.ru> Message-ID: <4F030EDE.1090002@free.fr> Hi Stepan, > Oh.. of course. Commited as r147446. For next patch, did you mean that I should check that TypeID was properly stored in its 8 bits? Something like this: > > void setTypeID(TypeID ID) { > IDAndSubclassData = (ID& 0xFF) | (IDAndSubclassData& 0xFFFFFF00); > assert(IDAndSubclassData& 0xFF == ID&& "Type data too large for field"); > } yes, something like that. Better to use assert(getTypeID() == ID && "Type data too large for field!"); though IMO. Ciao, Duncan. > > -Stepan > > 03.01.2012, 12:51, "Duncan Sands": >> Hi Stepan, >> >>> Hi Duncan, can I use DataTypes.h instead? >> >> this patch doesn't require either. It is the next patch that needs it, right? >> >> Ciao, Duncan. >> >>> -Stepan. >>> >>> 03.01.2012, 12:32, "Duncan Sands": >>>> Hi Stepan, this looks fine except for a pointless include of stdint.h. Please >>>> apply, except for the include. >>>> >>>> Thanks for doing this, >>>> >>>> Duncan. >>>>> Hi, Duncan. Please find the first patch in attachment. Replacement: ID with getTypeID(). >>>>> - Stepan >>>>> >>>>> 02.01.2012, 19:25, "Duncan Sands": >>>>>> Hi Stepan, >>>>>>> OK. Please look at patch in attachment. >>>>>>> I'm not sure that it is better than previous patch. Probably the first one looks like a workaround, but it changes setSubclassData only. New patch changes set/getSubclassData set/getTypeID, and all methods that uses ID. >>>>>> thanks for doing this. I think it is a better abstraction to have getters >>>>>> and setters for ID, like the ones that already exist for SubclassData. Can >>>>>> you therefore split the patch in two: one patch that adds getters and setters, >>>>>> and then a second one that drops the bitfield in favour of explicit bit >>>>>> fiddling. >>>>>> >>>>>> Additional comments: >>>>>> - you made some lines too long (> 80 columns). >>>>>> - this is not your fault, but I think there should be a check that ID values >>>>>> fit in the allocated space, for example by checking somehow that there is >>>>>> enough room for every value of the TypeID type. Alternatively, in setTypeID >>>>>> check that the value you read back out matches the value put in. The >>>>>> constructor can also set the ID. It should probably initialize >>>>>> IDAndSubclassData to zero, and then call setTypeID in the body of the >>>>>> constructor to set the value. >>>>>> >>>>>> Ciao, Duncan. >>>>>>> -Stepan. >>>>>>> >>>>>>> 02.01.2012, 15:04, "Duncan Sands": >>>>>>>> Hi Stepan, >>>>>>>>> ID is used very extensively in Type.h. We need to fix a lots, so we need to fix all methods like: >>>>>>>>> bool isIntegerTy() const { return ID == IntegerTyID; } >>>>>>>> you could turn ID into a private method that extracts the id part of the field. >>>>>>>> Then you just need to turn ID into ID() in places such as isIntegerTy. Likewise >>>>>>>> for SubclassData. >>>>>>>>> But in the same time we can apply some working decision until gcc bug will fixed. >>>>>>>>> May be add some dummy field? >>>>>>>>> TypeID ID : 8; >>>>>>>>> unsigned SubclassData : 24; >>>>>>>>> unsigned KungFuPanda; // Will protect NumContainedTys from overwriting. >>>>>>>>> unsigned NumContainedTys; // Will OK. >>>>>>>> Even if the gcc bug is fixed, people will be using older compilers with the bug >>>>>>>> for years to come. So this field would be around essentially forever. Given >>>>>>>> that, I don't think this is a good solution. If you are prepared to make the >>>>>>>> class bigger, you might as well not have the fields be bitfields at all (and >>>>>>>> change the order so that things are well packed). >>>>>>>> >>>>>>>> Ciao, Duncan. >>>>>>>>> -Stepan. >>>>>>>>> >>>>>>>>> 02.01.2012, 14:38, "Duncan Sands": >>>>>>>>>> Hi Stepan, >>>>>>>>>>> I tried it doesn't helps. Now it seems that ID is overwritten. 4807 unexpected failures. >>>>>>>>>> OK, thanks for the info. How about doing the bit fiddling yourself instead? >>>>>>>>>> I.e. rather than trying to fool the optimizers, don't use bitfields: declare >>>>>>>>>> an unsigned field IDAndSubclassData and store and load values from it using >>>>>>>>>> explicit shifts etc. This would then completely avoid all problems coming >>>>>>>>>> from misoptimization of bitfields (which has happened a lot historically), >>>>>>>>>> and would be less fragile than trying to fool the optimizers via some magic >>>>>>>>>> incantation. >>>>>>>>>> >>>>>>>>>> Ciao, Duncan. >>>>>>>>>>> -Stepan. >>>>>>>>>>> >>>>>>>>>>> 02.01.2012, 14:02, "Duncan Sands": >>>>>>>>>>>> Hi Stepan, >>>>>>>>>>>>> The problem is in Type.h. The fields in Type class are declared in next order: >>>>>>>>>>>>> TypeID ID : 8; >>>>>>>>>>>>> unsigned SubclassData : 24; >>>>>>>>>>>>> unsigned NumContainedTys; >>>>>>>>>>>> does the problem still occur if you flip the order of ID and SubclassData? >>>>>>>>>>>> I.e. >>>>>>>>>>>> unsigned SubclassData : 24; >>>>>>>>>>>> TypeID ID : 8; >>>>>>>>>>>> unsigned NumContainedTys; >>>>>>>>>>>> ? >>>>>>>>>>>> Ciao, Duncan. >>>>>>>>>>>>> Attempt to set new SubclassData value rewrites lowest byte in NumContainedTys >>>>>>>>>>>>> when -Os is set. GCC bug? Anyway setting SubclassData with two workaround >>>>>>>>>>>>> strings fixes the problem: >>>>>>>>>>>>> >>>>>>>>>>>>> void setSubclassData(unsigned val) { >>>>>>>>>>>>> unsigned tmp = NumContainedTys; // Workaround for GCC -Os >>>>>>>>>>>>> SubclassData = val; >>>>>>>>>>>>> NumContainedTys = tmp; // Workaround for GCC -Os >>>>>>>>>>>>> // Ensure we don't have any accidental truncation. >>>>>>>>>>>>> assert(SubclassData == val&& "Subclass data too large for field"); >>>>>>>>>>>>> } >>>>>>>>>>>>> >>>>>>>>>>>>> Probably there is another ways to protect NumContainedTys from overwritting? >>>>>>>>>>>>> >>>>>>>>>>>>> Please find the patch in attachment for review. >>>>>>>>>>>>> >>>>>>>>>>>>> -Stepan. >>>>>>>>>>>>> >>>>>>>>>>>>> _______________________________________________ >>>>>>>>>>>>> llvm-commits mailing list >>>>>>>>>>>>> llvm-commits at cs.uiuc.edu >>>>>>>>>>>>> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits >>>>>>>>>>>> _______________________________________________ >>>>>>>>>>>> llvm-commits mailing list >>>>>>>>>>>> llvm-commits at cs.uiuc.edu >>>>>>>>>>>> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From jan_sjodin at yahoo.com Tue Jan 3 10:12:39 2012 From: jan_sjodin at yahoo.com (Jan Sjodin) Date: Tue, 3 Jan 2012 08:12:39 -0800 (PST) Subject: [llvm-commits] XOP Intrinsics patch Message-ID: <1325607159.50862.YahooMailNeo@web161503.mail.bf1.yahoo.com> This patch adds XOP intrinsics (including tests). Ok to commit? - Jan -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20120103/f9b8462a/attachment-0001.html -------------- next part -------------- A non-text attachment was scrubbed... Name: 0060_xop_intrinsics.patch Type: application/octet-stream Size: 104655 bytes Desc: not available Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20120103/f9b8462a/attachment-0001.obj From andy.zhang at intel.com Tue Jan 3 10:45:15 2012 From: andy.zhang at intel.com (Zhang, Andy) Date: Tue, 3 Jan 2012 16:45:15 +0000 Subject: [llvm-commits] Intel Atom optimization - use LEA to adjust stack pointer In-Reply-To: <5CED04BC-2514-4235-9364-9FFB13E415EE@2pi.dk> References: <9A83F73AEA08BB46A2799C5D4C16BFED011A38BC09@rrsmsx509.amr.corp.intel.com> <5C9B2DB6AAFD914E864AF9803780B66A7EAC@FMSMSX108.amr.corp.intel.com> <5CED04BC-2514-4235-9364-9FFB13E415EE@2pi.dk> Message-ID: <5C9B2DB6AAFD914E864AF9803780B66A94D2@FMSMSX108.amr.corp.intel.com> On Friday, December 23, 2011 11:06 PM, Jakob Stoklund Olesen wrote: > Hi Andy, > > Please submit the TableGen changes as an independent patch. > > From a quick glance, you also need to make sure you follow LLVM's style > for braces etc. > > if (isSub) > + { > MI->setFlag(MachineInstr::FrameSetup); > - MI->getOperand(3).setIsDead(); // The EFLAGS implicit def is dead. > + } > > Why add braces here? > > /jakob Hi Jakob, I'll submit the TableGen part of the patch separately. I put braces there in case another line is added to the body of the if-statement in the future and the braces are accidentally overlooked. But they should be on the previous line anyway. I can remove the braces from all of the single-statement if-blocks that I added, for consistency with the rest of that file. Regards, Andy From jan_sjodin at yahoo.com Tue Jan 3 11:05:12 2012 From: jan_sjodin at yahoo.com (Jan Sjodin) Date: Tue, 3 Jan 2012 09:05:12 -0800 (PST) Subject: [llvm-commits] XOP Intrinsics patch In-Reply-To: <1325607159.50862.YahooMailNeo@web161503.mail.bf1.yahoo.com> References: <1325607159.50862.YahooMailNeo@web161503.mail.bf1.yahoo.com> Message-ID: <1325610312.92696.YahooMailNeo@web161505.mail.bf1.yahoo.com> I noticed the changes to FMA4 etc. I will make some modifications to this patch.. - Jan >________________________________ > From: Jan Sjodin >To: "llvm-commits at cs.uiuc.edu" >Sent: Tuesday, January 3, 2012 11:12 AM >Subject: [llvm-commits] XOP Intrinsics patch > > >This patch adds XOP intrinsics (including tests). Ok to commit? > > > >- Jan > >_______________________________________________ >llvm-commits mailing list >llvm-commits at cs.uiuc.edu >http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits > > > -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20120103/399f307a/attachment.html From andy.zhang at intel.com Tue Jan 3 11:23:08 2012 From: andy.zhang at intel.com (Zhang, Andy) Date: Tue, 3 Jan 2012 17:23:08 +0000 Subject: [llvm-commits] [PATCH] Modify tablegen to use constants when there are more than 32 subtarget features Message-ID: <5C9B2DB6AAFD914E864AF9803780B66A94FA@FMSMSX108.amr.corp.intel.com> Currently, TableGen uses an anonymous enum for subtarget features. When compiling with Visual C++, enums are always 'int's, so with more than 32 subtarget features, some values will overflow. The attached patch modifies TableGen to emit 'const uint64_t' for subtarget features when there are more than 32 of them. It was split off from my earlier patch for Atom optimizations, as requested. If this looks OK, could it be committed to trunk? Thanks, Andy -------------- next part -------------- A non-text attachment was scrubbed... Name: tblgen.diff Type: application/octet-stream Size: 1695 bytes Desc: tblgen.diff Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20120103/56f04a98/attachment.obj From craig.topper at gmail.com Tue Jan 3 12:14:10 2012 From: craig.topper at gmail.com (Craig Topper) Date: Tue, 3 Jan 2012 10:14:10 -0800 Subject: [llvm-commits] XOP Intrinsics patch In-Reply-To: <1325607159.50862.YahooMailNeo@web161503.mail.bf1.yahoo.com> References: <1325607159.50862.YahooMailNeo@web161503.mail.bf1.yahoo.com> Message-ID: All integer vector loads in patterns need to be memopv2i64(!28-bit) or memopv4i64(256-bit) and bitcasted to the correct type because all integer vector loads are promoted to v2i64 or v4i64. So for instance +def : Pat<(int_x86_xop_vphsubwd (alignedloadv8i16 addr:$src1)), + (VPHSUBWDrm addr:$src1)>; Needs to be +def : Pat<(int_x86_xop_vphsubwd (bc_v8i16 (memopv2i64 addr:$src1))), + (VPHSUBWDrm addr:$src1)>; ~Craig On Tue, Jan 3, 2012 at 8:12 AM, Jan Sjodin wrote: > This patch adds XOP intrinsics (including tests). Ok to commit? > > - Jan > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits > > -- ~Craig -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20120103/e7403366/attachment.html From craig.topper at gmail.com Tue Jan 3 12:17:49 2012 From: craig.topper at gmail.com (Craig Topper) Date: Tue, 3 Jan 2012 10:17:49 -0800 Subject: [llvm-commits] XOP Intrinsics patch In-Reply-To: References: <1325607159.50862.YahooMailNeo@web161503.mail.bf1.yahoo.com> Message-ID: Adding some testcases that use the load patterns would probably be good too. I've been fixing a lot of these sort of patterns lately because they didn't understand the integer promotion. ~Craig On Tue, Jan 3, 2012 at 10:14 AM, Craig Topper wrote: > All integer vector loads in patterns need to be memopv2i64(!28-bit) or > memopv4i64(256-bit) and bitcasted to the correct type because all integer > vector loads are promoted to v2i64 or v4i64. So for instance > > +def : Pat<(int_x86_xop_vphsubwd (alignedloadv8i16 addr:$src1)), > + (VPHSUBWDrm addr:$src1)>; > > Needs to be > > +def : Pat<(int_x86_xop_vphsubwd (bc_v8i16 (memopv2i64 addr:$src1))), > + (VPHSUBWDrm addr:$src1)>; > > ~Craig > > On Tue, Jan 3, 2012 at 8:12 AM, Jan Sjodin wrote: > >> This patch adds XOP intrinsics (including tests). Ok to commit? >> >> - Jan >> >> _______________________________________________ >> llvm-commits mailing list >> llvm-commits at cs.uiuc.edu >> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits >> >> > > > -- > ~Craig > -- ~Craig -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20120103/c0729efb/attachment.html From dpatel at apple.com Tue Jan 3 12:22:10 2012 From: dpatel at apple.com (Devang Patel) Date: Tue, 03 Jan 2012 18:22:10 -0000 Subject: [llvm-commits] [llvm] r147453 - in /llvm/trunk/lib/Target/X86: X86InstrFPStack.td X86InstrShiftRotate.td Message-ID: <20120103182211.103ED2A6C12C@llvm.org> Author: dpatel Date: Tue Jan 3 12:22:10 2012 New Revision: 147453 URL: http://llvm.org/viewvc/llvm-project?rev=147453&view=rev Log: Intel style asm variant does not need '%' prefix. Modified: llvm/trunk/lib/Target/X86/X86InstrFPStack.td llvm/trunk/lib/Target/X86/X86InstrShiftRotate.td Modified: llvm/trunk/lib/Target/X86/X86InstrFPStack.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrFPStack.td?rev=147453&r1=147452&r2=147453&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86InstrFPStack.td (original) +++ llvm/trunk/lib/Target/X86/X86InstrFPStack.td Tue Jan 3 12:22:10 2012 @@ -225,22 +225,22 @@ // of some of the 'reverse' forms of the fsub and fdiv instructions. As such, // we have to put some 'r's in and take them out of weird places. def ADD_FST0r : FPST0rInst <0xC0, "fadd\t$op">; -def ADD_FrST0 : FPrST0Inst <0xC0, "fadd\t{%st(0), $op|$op, %ST(0)}">; +def ADD_FrST0 : FPrST0Inst <0xC0, "fadd\t{%st(0), $op|$op, ST(0)}">; def ADD_FPrST0 : FPrST0PInst<0xC0, "faddp\t$op">; def SUBR_FST0r : FPST0rInst <0xE8, "fsubr\t$op">; -def SUB_FrST0 : FPrST0Inst <0xE8, "fsub{r}\t{%st(0), $op|$op, %ST(0)}">; +def SUB_FrST0 : FPrST0Inst <0xE8, "fsub{r}\t{%st(0), $op|$op, ST(0)}">; def SUB_FPrST0 : FPrST0PInst<0xE8, "fsub{r}p\t$op">; def SUB_FST0r : FPST0rInst <0xE0, "fsub\t$op">; -def SUBR_FrST0 : FPrST0Inst <0xE0, "fsub{|r}\t{%st(0), $op|$op, %ST(0)}">; +def SUBR_FrST0 : FPrST0Inst <0xE0, "fsub{|r}\t{%st(0), $op|$op, ST(0)}">; def SUBR_FPrST0 : FPrST0PInst<0xE0, "fsub{|r}p\t$op">; def MUL_FST0r : FPST0rInst <0xC8, "fmul\t$op">; -def MUL_FrST0 : FPrST0Inst <0xC8, "fmul\t{%st(0), $op|$op, %ST(0)}">; +def MUL_FrST0 : FPrST0Inst <0xC8, "fmul\t{%st(0), $op|$op, ST(0)}">; def MUL_FPrST0 : FPrST0PInst<0xC8, "fmulp\t$op">; def DIVR_FST0r : FPST0rInst <0xF8, "fdivr\t$op">; -def DIV_FrST0 : FPrST0Inst <0xF8, "fdiv{r}\t{%st(0), $op|$op, %ST(0)}">; +def DIV_FrST0 : FPrST0Inst <0xF8, "fdiv{r}\t{%st(0), $op|$op, ST(0)}">; def DIV_FPrST0 : FPrST0PInst<0xF8, "fdiv{r}p\t$op">; def DIV_FST0r : FPST0rInst <0xF0, "fdiv\t$op">; -def DIVR_FrST0 : FPrST0Inst <0xF0, "fdiv{|r}\t{%st(0), $op|$op, %ST(0)}">; +def DIVR_FrST0 : FPrST0Inst <0xF0, "fdiv{|r}\t{%st(0), $op|$op, ST(0)}">; def DIVR_FPrST0 : FPrST0PInst<0xF0, "fdiv{|r}p\t$op">; def COM_FST0r : FPST0rInst <0xD0, "fcom\t$op">; @@ -330,21 +330,21 @@ let Predicates = [HasCMov] in { // These are not factored because there's no clean way to pass DA/DB. def CMOVB_F : FPI<0xC0, AddRegFrm, (outs RST:$op), (ins), - "fcmovb\t{$op, %st(0)|%ST(0), $op}">, DA; + "fcmovb\t{$op, %st(0)|ST(0), $op}">, DA; def CMOVBE_F : FPI<0xD0, AddRegFrm, (outs RST:$op), (ins), - "fcmovbe\t{$op, %st(0)|%ST(0), $op}">, DA; + "fcmovbe\t{$op, %st(0)|ST(0), $op}">, DA; def CMOVE_F : FPI<0xC8, AddRegFrm, (outs RST:$op), (ins), - "fcmove\t{$op, %st(0)|%ST(0), $op}">, DA; + "fcmove\t{$op, %st(0)|ST(0), $op}">, DA; def CMOVP_F : FPI<0xD8, AddRegFrm, (outs RST:$op), (ins), - "fcmovu\t {$op, %st(0)|%ST(0), $op}">, DA; + "fcmovu\t {$op, %st(0)|ST(0), $op}">, DA; def CMOVNB_F : FPI<0xC0, AddRegFrm, (outs RST:$op), (ins), - "fcmovnb\t{$op, %st(0)|%ST(0), $op}">, DB; + "fcmovnb\t{$op, %st(0)|ST(0), $op}">, DB; def CMOVNBE_F: FPI<0xD0, AddRegFrm, (outs RST:$op), (ins), - "fcmovnbe\t{$op, %st(0)|%ST(0), $op}">, DB; + "fcmovnbe\t{$op, %st(0)|ST(0), $op}">, DB; def CMOVNE_F : FPI<0xC8, AddRegFrm, (outs RST:$op), (ins), - "fcmovne\t{$op, %st(0)|%ST(0), $op}">, DB; + "fcmovne\t{$op, %st(0)|ST(0), $op}">, DB; def CMOVNP_F : FPI<0xD8, AddRegFrm, (outs RST:$op), (ins), - "fcmovnu\t{$op, %st(0)|%ST(0), $op}">, DB; + "fcmovnu\t{$op, %st(0)|ST(0), $op}">, DB; } // Predicates = [HasCMov] // Floating point loads & stores. Modified: llvm/trunk/lib/Target/X86/X86InstrShiftRotate.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrShiftRotate.td?rev=147453&r1=147452&r2=147453&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86InstrShiftRotate.td (original) +++ llvm/trunk/lib/Target/X86/X86InstrShiftRotate.td Tue Jan 3 12:22:10 2012 @@ -27,7 +27,7 @@ "shl{l}\t{%cl, $dst|$dst, CL}", [(set GR32:$dst, (shl GR32:$src1, CL))]>; def SHL64rCL : RI<0xD3, MRM4r, (outs GR64:$dst), (ins GR64:$src1), - "shl{q}\t{%cl, $dst|$dst, %CL}", + "shl{q}\t{%cl, $dst|$dst, CL}", [(set GR64:$dst, (shl GR64:$src1, CL))]>; } // Uses = [CL] @@ -74,7 +74,7 @@ "shl{l}\t{%cl, $dst|$dst, CL}", [(store (shl (loadi32 addr:$dst), CL), addr:$dst)]>; def SHL64mCL : RI<0xD3, MRM4m, (outs), (ins i64mem:$dst), - "shl{q}\t{%cl, $dst|$dst, %CL}", + "shl{q}\t{%cl, $dst|$dst, CL}", [(store (shl (loadi64 addr:$dst), CL), addr:$dst)]>; } def SHL8mi : Ii8<0xC0, MRM4m, (outs), (ins i8mem :$dst, i8imm:$src), @@ -118,7 +118,7 @@ "shr{l}\t{%cl, $dst|$dst, CL}", [(set GR32:$dst, (srl GR32:$src1, CL))]>; def SHR64rCL : RI<0xD3, MRM5r, (outs GR64:$dst), (ins GR64:$src1), - "shr{q}\t{%cl, $dst|$dst, %CL}", + "shr{q}\t{%cl, $dst|$dst, CL}", [(set GR64:$dst, (srl GR64:$src1, CL))]>; } @@ -163,7 +163,7 @@ "shr{l}\t{%cl, $dst|$dst, CL}", [(store (srl (loadi32 addr:$dst), CL), addr:$dst)]>; def SHR64mCL : RI<0xD3, MRM5m, (outs), (ins i64mem:$dst), - "shr{q}\t{%cl, $dst|$dst, %CL}", + "shr{q}\t{%cl, $dst|$dst, CL}", [(store (srl (loadi64 addr:$dst), CL), addr:$dst)]>; } def SHR8mi : Ii8<0xC0, MRM5m, (outs), (ins i8mem :$dst, i8imm:$src), @@ -206,7 +206,7 @@ "sar{l}\t{%cl, $dst|$dst, CL}", [(set GR32:$dst, (sra GR32:$src1, CL))]>; def SAR64rCL : RI<0xD3, MRM7r, (outs GR64:$dst), (ins GR64:$src1), - "sar{q}\t{%cl, $dst|$dst, %CL}", + "sar{q}\t{%cl, $dst|$dst, CL}", [(set GR64:$dst, (sra GR64:$src1, CL))]>; } @@ -252,7 +252,7 @@ "sar{l}\t{%cl, $dst|$dst, CL}", [(store (sra (loadi32 addr:$dst), CL), addr:$dst)]>; def SAR64mCL : RI<0xD3, MRM7m, (outs), (ins i64mem:$dst), - "sar{q}\t{%cl, $dst|$dst, %CL}", + "sar{q}\t{%cl, $dst|$dst, CL}", [(store (sra (loadi64 addr:$dst), CL), addr:$dst)]>; } def SAR8mi : Ii8<0xC0, MRM7m, (outs), (ins i8mem :$dst, i8imm:$src), @@ -424,7 +424,7 @@ "rol{l}\t{%cl, $dst|$dst, CL}", [(set GR32:$dst, (rotl GR32:$src1, CL))]>; def ROL64rCL : RI<0xD3, MRM0r, (outs GR64:$dst), (ins GR64:$src1), - "rol{q}\t{%cl, $dst|$dst, %CL}", + "rol{q}\t{%cl, $dst|$dst, CL}", [(set GR64:$dst, (rotl GR64:$src1, CL))]>; } @@ -469,7 +469,7 @@ "rol{l}\t{%cl, $dst|$dst, CL}", [(store (rotl (loadi32 addr:$dst), CL), addr:$dst)]>; def ROL64mCL : RI<0xD3, MRM0m, (outs), (ins i64mem:$dst), - "rol{q}\t{%cl, $dst|$dst, %CL}", + "rol{q}\t{%cl, $dst|$dst, %cl}", [(store (rotl (loadi64 addr:$dst), CL), addr:$dst)]>; } def ROL8mi : Ii8<0xC0, MRM0m, (outs), (ins i8mem :$dst, i8imm:$src1), @@ -513,7 +513,7 @@ "ror{l}\t{%cl, $dst|$dst, CL}", [(set GR32:$dst, (rotr GR32:$src1, CL))]>; def ROR64rCL : RI<0xD3, MRM1r, (outs GR64:$dst), (ins GR64:$src1), - "ror{q}\t{%cl, $dst|$dst, %CL}", + "ror{q}\t{%cl, $dst|$dst, CL}", [(set GR64:$dst, (rotr GR64:$src1, CL))]>; } @@ -558,7 +558,7 @@ "ror{l}\t{%cl, $dst|$dst, CL}", [(store (rotr (loadi32 addr:$dst), CL), addr:$dst)]>; def ROR64mCL : RI<0xD3, MRM1m, (outs), (ins i64mem:$dst), - "ror{q}\t{%cl, $dst|$dst, %CL}", + "ror{q}\t{%cl, $dst|$dst, CL}", [(store (rotr (loadi64 addr:$dst), CL), addr:$dst)]>; } def ROR8mi : Ii8<0xC0, MRM1m, (outs), (ins i8mem :$dst, i8imm:$src), @@ -618,12 +618,12 @@ [(set GR32:$dst, (X86shrd GR32:$src1, GR32:$src2, CL))]>, TB; def SHLD64rrCL : RI<0xA5, MRMDestReg, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2), - "shld{q}\t{%cl, $src2, $dst|$dst, $src2, %CL}", + "shld{q}\t{%cl, $src2, $dst|$dst, $src2, CL}", [(set GR64:$dst, (X86shld GR64:$src1, GR64:$src2, CL))]>, TB; def SHRD64rrCL : RI<0xAD, MRMDestReg, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2), - "shrd{q}\t{%cl, $src2, $dst|$dst, $src2, %CL}", + "shrd{q}\t{%cl, $src2, $dst|$dst, $src2, CL}", [(set GR64:$dst, (X86shrd GR64:$src1, GR64:$src2, CL))]>, TB; } @@ -694,11 +694,11 @@ addr:$dst)]>, TB; def SHLD64mrCL : RI<0xA5, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2), - "shld{q}\t{%cl, $src2, $dst|$dst, $src2, %CL}", + "shld{q}\t{%cl, $src2, $dst|$dst, $src2, CL}", [(store (X86shld (loadi64 addr:$dst), GR64:$src2, CL), addr:$dst)]>, TB; def SHRD64mrCL : RI<0xAD, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2), - "shrd{q}\t{%cl, $src2, $dst|$dst, $src2, %CL}", + "shrd{q}\t{%cl, $src2, $dst|$dst, $src2, CL}", [(store (X86shrd (loadi64 addr:$dst), GR64:$src2, CL), addr:$dst)]>, TB; } From nicholas at mxc.ca Tue Jan 3 12:22:43 2012 From: nicholas at mxc.ca (Nick Lewycky) Date: Tue, 03 Jan 2012 18:22:43 -0000 Subject: [llvm-commits] [llvm] r147454 - /llvm/trunk/lib/CodeGen/RenderMachineFunction.cpp Message-ID: <20120103182243.DC9402A6C12C@llvm.org> Author: nicholas Date: Tue Jan 3 12:22:43 2012 New Revision: 147454 URL: http://llvm.org/viewvc/llvm-project?rev=147454&view=rev Log: Fix typo in ruler. No functionality change. Modified: llvm/trunk/lib/CodeGen/RenderMachineFunction.cpp Modified: llvm/trunk/lib/CodeGen/RenderMachineFunction.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/RenderMachineFunction.cpp?rev=147454&r1=147453&r2=147454&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/RenderMachineFunction.cpp (original) +++ llvm/trunk/lib/CodeGen/RenderMachineFunction.cpp Tue Jan 3 12:22:43 2012 @@ -1,4 +1,4 @@ -//===-- llvm/CodeGen/RenderMachineFunction.cpp - MF->HTML -----s-----------===// +//===-- llvm/CodeGen/RenderMachineFunction.cpp - MF->HTML -----------------===// // // The LLVM Compiler Infrastructure // From jan_sjodin at yahoo.com Tue Jan 3 12:35:18 2012 From: jan_sjodin at yahoo.com (Jan Sjodin) Date: Tue, 3 Jan 2012 10:35:18 -0800 (PST) Subject: [llvm-commits] XOP Intrinsics patch In-Reply-To: References: <1325607159.50862.YahooMailNeo@web161503.mail.bf1.yahoo.com> Message-ID: <1325615718.39602.YahooMailNeo@web161506.mail.bf1.yahoo.com> Yes, I saw your fixes after I sent out this patch. I will fix accordingly and also try and include the intrinsics patterns in the encoding. Thanks, Jan >________________________________ > From: Craig Topper >To: Jan Sjodin >Cc: "llvm-commits at cs.uiuc.edu" >Sent: Tuesday, January 3, 2012 1:17 PM >Subject: Re: [llvm-commits] XOP Intrinsics patch > > >Adding some testcases that use the load patterns would probably be good too. I've been fixing a lot of these sort of patterns lately because they didn't understand the integer promotion. > >~Craig > > >On Tue, Jan 3, 2012 at 10:14 AM, Craig Topper wrote: > >All integer vector loads in patterns need to be memopv2i64(!28-bit) or memopv4i64(256-bit) and bitcasted to the correct type because all integer vector loads are promoted to v2i64 or v4i64. So for instance >> >>+def : Pat<(int_x86_xop_vphsubwd (alignedloadv8i16 addr:$src1)), >>+????????? (VPHSUBWDrm addr:$src1)>; >> >>Needs to be >> >>+def : Pat<(int_x86_xop_vphsubwd (bc_v8i16 (memopv2i64 addr:$src1))), >>+????????? (VPHSUBWDrm addr:$src1)>; >> >>~Craig >> >> >>On Tue, Jan 3, 2012 at 8:12 AM, Jan Sjodin wrote: >> >>This patch adds XOP intrinsics (including tests). Ok to commit? >>> >>> >>>- Jan >>> >>> >>>_______________________________________________ >>>llvm-commits mailing list >>>llvm-commits at cs.uiuc.edu >>>http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits >>> >>> >> >> >>-- >>~Craig >> > > >-- >~Craig > > > -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20120103/c05879a4/attachment.html From echristo at apple.com Tue Jan 3 12:38:37 2012 From: echristo at apple.com (Eric Christopher) Date: Tue, 03 Jan 2012 18:38:37 -0000 Subject: [llvm-commits] [llvm] r147456 - /llvm/trunk/docs/SourceLevelDebugging.html Message-ID: <20120103183837.D5F882A6C12C@llvm.org> Author: echristo Date: Tue Jan 3 12:38:37 2012 New Revision: 147456 URL: http://llvm.org/viewvc/llvm-project?rev=147456&view=rev Log: Fix typo. Modified: llvm/trunk/docs/SourceLevelDebugging.html Modified: llvm/trunk/docs/SourceLevelDebugging.html URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/SourceLevelDebugging.html?rev=147456&r1=147455&r2=147456&view=diff ============================================================================== --- llvm/trunk/docs/SourceLevelDebugging.html (original) +++ llvm/trunk/docs/SourceLevelDebugging.html Tue Jan 3 12:38:37 2012 @@ -576,7 +576,7 @@ i64, ;; Offset in bits i32, ;; Flags to encode attributes, e.g. private metadata, ;; Reference to type derived from - metadata, ;; (optional) Name of the Objective C property assoicated with + metadata, ;; (optional) Name of the Objective C property associated with ;; Objective-C an ivar metadata, ;; (optional) Name of the Objective C property getter selector. metadata, ;; (optional) Name of the Objective C property setter selector. From STPWORLD at narod.ru Tue Jan 3 12:50:21 2012 From: STPWORLD at narod.ru (Stepan Dyatkovskiy) Date: Tue, 03 Jan 2012 22:50:21 +0400 Subject: [llvm-commits] [LLVM, PR11652 PATCH]: Fixed Bug 11652 - assertion failures when Type.cpp is compiled with -Os In-Reply-To: <4F030EDE.1090002@free.fr> References: <4EFE13EC.2010801@narod.ru> <4F0180C5.1080206@free.fr> <191841325500240@web28.yandex.ru> <4F018912.3000107@free.fr> <200971325501753@web58.yandex.ru> <4F018F55.1040604@free.fr> <1136931325507957@web94.yandex.ru> <4F01CC81.4010909@free.fr> <359001325533597@web8.yandex.ru> <4F02BD1B.7070808@free.fr> <673781325580638@web123.yandex.ru> <4F02C1AA.1080707@free.fr> <602271325599963@web1.yandex.ru> <4F030EDE.1090002@free.fr> Message-ID: <200591325616621@web103.yandex.ru> Hi, Duncan. Please find the second patch attached. -Stepan. 03.01.2012, 18:21, "Duncan Sands" : > Hi Stepan, > >> ?Oh.. of course. Commited as r147446. For next patch, did you mean that I should check that TypeID was properly stored in its 8 bits? Something like this: >> >> ?void setTypeID(TypeID ID) { >> ?????IDAndSubclassData = (ID& ?0xFF) | (IDAndSubclassData& ?0xFFFFFF00); >> ?????assert(IDAndSubclassData& ?0xFF == ID&& ?"Type data too large for field"); >> ?} > > yes, something like that. ?Better to use > > ???assert(getTypeID() == ID && "Type data too large for field!"); > > though IMO. > > Ciao, Duncan. > >> ?-Stepan >> >> ?03.01.2012, 12:51, "Duncan Sands": >>> ?Hi Stepan, >>>> ???Hi Duncan, can I use DataTypes.h instead? >>> ?this patch doesn't require either. ?It is the next patch that needs it, right? >>> >>> ?Ciao, Duncan. >>>> ???-Stepan. >>>> >>>> ???03.01.2012, 12:32, "Duncan Sands": >>>>> ???Hi Stepan, this looks fine except for a pointless include of stdint.h. ?Please >>>>> ???apply, except for the include. >>>>> >>>>> ???Thanks for doing this, >>>>> >>>>> ???Duncan. >>>>>> ?????Hi, Duncan. Please find the first patch in attachment. Replacement: ID with getTypeID(). >>>>>> ?????- Stepan >>>>>> >>>>>> ?????02.01.2012, 19:25, "Duncan Sands": >>>>>>> ?????Hi Stepan, >>>>>>>> ???????OK. Please look at patch in attachment. >>>>>>>> ???????I'm not sure that it is better than previous patch. Probably the first one looks like a workaround, but it changes setSubclassData only. New patch changes set/getSubclassData set/getTypeID, and all methods that uses ID. >>>>>>> ?????thanks for doing this. ?I think it is a better abstraction to have getters >>>>>>> ?????and setters for ID, like the ones that already exist for SubclassData. ?Can >>>>>>> ?????you therefore split the patch in two: one patch that adds getters and setters, >>>>>>> ?????and then a second one that drops the bitfield in favour of explicit bit >>>>>>> ?????fiddling. >>>>>>> >>>>>>> ?????Additional comments: >>>>>>> ?????????- you made some lines too long (> ?????80 columns). >>>>>>> ?????????- this is not your fault, but I think there should be a check that ID values >>>>>>> ???????????fit in the allocated space, for example by checking somehow that there is >>>>>>> ???????????enough room for every value of the TypeID type. ?Alternatively, in setTypeID >>>>>>> ???????????check that the value you read back out matches the value put in. ?The >>>>>>> ???????????constructor can also set the ID. ?It should probably initialize >>>>>>> ???????????IDAndSubclassData to zero, and then call setTypeID in the body of the >>>>>>> ???????????constructor to set the value. >>>>>>> >>>>>>> ?????Ciao, Duncan. >>>>>>>> ???????-Stepan. >>>>>>>> >>>>>>>> ???????02.01.2012, 15:04, "Duncan Sands": >>>>>>>>> ???????Hi Stepan, >>>>>>>>>> ?????????ID is used very extensively in Type.h. We need to fix a lots, so we need to fix all methods like: >>>>>>>>>> ?????????bool isIntegerTy() const { return ID == IntegerTyID; } >>>>>>>>> ???????you could turn ID into a private method that extracts the id part of the field. >>>>>>>>> ???????Then you just need to turn ID into ID() in places such as isIntegerTy. ?Likewise >>>>>>>>> ???????for SubclassData. >>>>>>>>>> ?????????But in the same time we can apply some working decision until gcc bug will fixed. >>>>>>>>>> ?????????May be add some dummy field? >>>>>>>>>> ????????????TypeID ??ID : 8; >>>>>>>>>> ????????????unsigned SubclassData : 24; >>>>>>>>>> ????????????unsigned KungFuPanda; ???????// Will protect NumContainedTys from overwriting. >>>>>>>>>> ????????????unsigned NumContainedTys; // Will OK. >>>>>>>>> ???????Even if the gcc bug is fixed, people will be using ?older compilers with the bug >>>>>>>>> ???????for years to come. ?So this field would be around essentially forever. ?Given >>>>>>>>> ???????that, I don't think this is a good solution. ?If you are prepared to make the >>>>>>>>> ???????class bigger, you might as well not have the fields be bitfields at all (and >>>>>>>>> ???????change the order so that things are well packed). >>>>>>>>> >>>>>>>>> ???????Ciao, Duncan. >>>>>>>>>> ?????????-Stepan. >>>>>>>>>> >>>>>>>>>> ?????????02.01.2012, 14:38, "Duncan Sands": >>>>>>>>>>> ?????????Hi Stepan, >>>>>>>>>>>> ???????????I tried it doesn't helps. Now it seems that ID is overwritten. 4807 unexpected failures. >>>>>>>>>>> ?????????OK, thanks for the info. ?How about doing the bit fiddling yourself instead? >>>>>>>>>>> ?????????I.e. rather than trying to fool the optimizers, don't use bitfields: declare >>>>>>>>>>> ?????????an unsigned field IDAndSubclassData and store and load values from it using >>>>>>>>>>> ?????????explicit shifts etc. ?This would then completely avoid all problems coming >>>>>>>>>>> ?????????from misoptimization of bitfields (which has happened a lot historically), >>>>>>>>>>> ?????????and would be less fragile than trying to fool the optimizers via some magic >>>>>>>>>>> ?????????incantation. >>>>>>>>>>> >>>>>>>>>>> ?????????Ciao, Duncan. >>>>>>>>>>>> ???????????-Stepan. >>>>>>>>>>>> >>>>>>>>>>>> ???????????02.01.2012, 14:02, "Duncan Sands": >>>>>>>>>>>>> ???????????Hi Stepan, >>>>>>>>>>>>>> ?????????????The problem is in Type.h. The fields in Type class are declared in next order: >>>>>>>>>>>>>> ?????????????TypeID ID : 8; >>>>>>>>>>>>>> ?????????????unsigned SubclassData : 24; >>>>>>>>>>>>>> ?????????????unsigned NumContainedTys; >>>>>>>>>>>>> ???????????does the problem still occur if you flip the order of ID and SubclassData? >>>>>>>>>>>>> ???????????I.e. >>>>>>>>>>>>> ???????????????unsigned SubclassData : 24; >>>>>>>>>>>>> ???????????????TypeID ID : 8; >>>>>>>>>>>>> ???????????????unsigned NumContainedTys; >>>>>>>>>>>>> ???????????? >>>>>>>>>>>>> ???????????Ciao, Duncan. >>>>>>>>>>>>>> ?????????????Attempt to set new SubclassData value rewrites lowest byte in NumContainedTys >>>>>>>>>>>>>> ?????????????when -Os is set. GCC bug? Anyway setting SubclassData with two workaround >>>>>>>>>>>>>> ?????????????strings fixes the problem: >>>>>>>>>>>>>> >>>>>>>>>>>>>> ?????????????void setSubclassData(unsigned val) { >>>>>>>>>>>>>> ?????????????unsigned tmp = NumContainedTys; // Workaround for GCC -Os >>>>>>>>>>>>>> ?????????????SubclassData = val; >>>>>>>>>>>>>> ?????????????NumContainedTys = tmp; // Workaround for GCC -Os >>>>>>>>>>>>>> ?????????????// Ensure we don't have any accidental truncation. >>>>>>>>>>>>>> ?????????????assert(SubclassData == val&& ???????????"Subclass data too large for field"); >>>>>>>>>>>>>> ?????????????} >>>>>>>>>>>>>> >>>>>>>>>>>>>> ?????????????Probably there is another ways to protect NumContainedTys from overwritting? >>>>>>>>>>>>>> >>>>>>>>>>>>>> ?????????????Please find the patch in attachment for review. >>>>>>>>>>>>>> >>>>>>>>>>>>>> ?????????????-Stepan. >>>>>>>>>>>>>> >>>>>>>>>>>>>> ?????????????_______________________________________________ >>>>>>>>>>>>>> ?????????????llvm-commits mailing list >>>>>>>>>>>>>> ?????????????llvm-commits at cs.uiuc.edu >>>>>>>>>>>>>> ?????????????http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits >>>>>>>>>>>>> ???????????_______________________________________________ >>>>>>>>>>>>> ???????????llvm-commits mailing list >>>>>>>>>>>>> ???????????llvm-commits at cs.uiuc.edu >>>>>>>>>>>>> ???????????http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits -------------- next part -------------- A non-text attachment was scrubbed... Name: 11652-2.0-gettersfix.patch Type: text/x-patch Size: 2267 bytes Desc: not available Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20120103/0ba1ba2b/attachment.bin From STPWORLD at narod.ru Tue Jan 3 12:50:44 2012 From: STPWORLD at narod.ru (Stepan Dyatkovskiy) Date: Tue, 03 Jan 2012 22:50:44 +0400 Subject: [llvm-commits] [LLVM, opt, LoopUnswitch] Compile-time improvements. In-Reply-To: <640641325498007@web20.yandex.ru> References: <4EFDAB2C.5000606@narod.ru> <640641325498007@web20.yandex.ru> Message-ID: <200741325616644@web103.yandex.ru> Ping. -Stepan. 02.01.2012, 13:53, "Stepan Dyatkovskiy" : > ping. > -Stepan. > > 30.12.2011, 16:14, "Stepan Dyatkovskiy" : > >> ?Hi. A made some fixes that improves compile-time: >> >> ?1. Size heuristics changed. Now we calculate number of unswitching >> ?branches only once per loop. >> ?2. Some checks was moved from UnswitchIfProfitable to >> ?processCurrentLoop, since it is not changed during processCurrentLoop >> ?iteration. It allows decide to skip some loops at an early stage. >> >> ?I checked the compile-time on test >> >> ?MultiSource/Benchmarks/Prolangs-C++/shapes/shapes >> ?(there was compile time regression after my previous patch). >> >> ?Relative to my previous patch the compile-time improved on ~8.5%. Relative >> ?to old revisions (before r146578) the compile time is improved on ~2%. >> >> ?Please find the patch in attachment for review. >> >> ?-Stepan. >> >> ?_______________________________________________ >> ?llvm-commits mailing list >> ?llvm-commits at cs.uiuc.edu >> ?http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From STPWORLD at narod.ru Tue Jan 3 12:51:08 2012 From: STPWORLD at narod.ru (Stepan Dyatkovskiy) Date: Tue, 03 Jan 2012 22:51:08 +0400 Subject: [llvm-commits] [LLVM, SwitchInst, case ranges] Auxiliary patch #1 In-Reply-To: <610731325498362@web6.yandex.ru> References: <4EAA9B5D.802@narod.ru> <4EAA9DE8.80000@free.fr> <485181319805488@web67.yandex.ru> <4EAB079D.6000606@free.fr> <4EB18F12.6060409@narod.ru> <4EB7C319.1000709@narod.ru> <4EDE7D75.704@narod.ru> <4EDFD0F4.1040204@narod.ru> <4EE25B61.9070006@narod.ru> <4EE5C06C.3050705@narod.ru> <333531323974498@web57.yandex.ru> <4EEB9C52.1050301@narod.ru> <4EF37B6B.6000205@narod.ru> <4EFA0748.9080702@narod.ru> <4EFCAA6A.20203@narod.ru> <610731325498362@web6.yandex.ru> Message-ID: <200871325616668@web103.yandex.ru> Ping. -- Truly yours, Stepan Dyatkovskiy 02.01.2012, 13:59, "Stepan Dyatkovskiy" : > Ping again and again :-) > -Stepan. > > 29.12.2011, 21:59, "Stepan Dyatkovskiy" : > >> ?Ping. >> ?-Stepan. >> >> ?Stepan Dyatkovskiy wrote: >>> ??ping. >>> ??Stepan Dyatkovskiy wrote: >>>> ??Ping. >>>> >>>> ??Stepan Dyatkovskiy wrote: >>>>> ??Ping. >>>>> >>>>> ??-Stepan. From bob.wilson at apple.com Tue Jan 3 12:59:25 2012 From: bob.wilson at apple.com (Bob Wilson) Date: Tue, 03 Jan 2012 18:59:25 -0000 Subject: [llvm-commits] [compiler-rt] r147458 - in /compiler-rt/trunk/lib: clear_cache.c trampoline_setup.c Message-ID: <20120103185925.636BA2A6C12C@llvm.org> Author: bwilson Date: Tue Jan 3 12:59:25 2012 New Revision: 147458 URL: http://llvm.org/viewvc/llvm-project?rev=147458&view=rev Log: Fix missing include of int_lib.h and ppc ifdef for FreeBSD. Patch provided by Ed Schouten! Modified: compiler-rt/trunk/lib/clear_cache.c compiler-rt/trunk/lib/trampoline_setup.c Modified: compiler-rt/trunk/lib/clear_cache.c URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/lib/clear_cache.c?rev=147458&r1=147457&r2=147458&view=diff ============================================================================== --- compiler-rt/trunk/lib/clear_cache.c (original) +++ compiler-rt/trunk/lib/clear_cache.c Tue Jan 3 12:59:25 2012 @@ -8,6 +8,8 @@ * ===----------------------------------------------------------------------=== */ +#include "int_lib.h" + #if __APPLE__ #include #endif Modified: compiler-rt/trunk/lib/trampoline_setup.c URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/lib/trampoline_setup.c?rev=147458&r1=147457&r2=147458&view=diff ============================================================================== --- compiler-rt/trunk/lib/trampoline_setup.c (original) +++ compiler-rt/trunk/lib/trampoline_setup.c Tue Jan 3 12:59:25 2012 @@ -20,7 +20,7 @@ * and then jumps to the target nested function. */ -#if __ppc__ +#if __ppc__ && !defined(__powerpc64__) void __trampoline_setup(uint32_t* trampOnStack, int trampSizeAllocated, const void* realFunc, void* localsPtr) { @@ -44,4 +44,4 @@ /* clear instruction cache */ __clear_cache(trampOnStack, &trampOnStack[10]); } -#endif /* __ppc__ */ +#endif /* __ppc__ && !defined(__powerpc64__) */ From bob.wilson at apple.com Tue Jan 3 13:02:43 2012 From: bob.wilson at apple.com (Bob Wilson) Date: Tue, 03 Jan 2012 11:02:43 -0800 Subject: [llvm-commits] [Patch] FreeBSD-specific modifications to compiler-rt In-Reply-To: <20111231190756.GY1895@hoeg.nl> References: <20111231190756.GY1895@hoeg.nl> Message-ID: I have applied those changes in svn r147458. On Dec 31, 2011, at 11:07 AM, Ed Schouten wrote: > Hi, > > The C runtime library that is shipped with FreeBSD is an almost > unmodified copy of compiler-rt. It would be nice if we could get the two > small local changes upstreamed as well. > > Change #1: > > clear_cache.c can call compilerrt_abort() on non-x86 non-Apple > architectures. Prevent a build failure on those architectures by > properly including "int_lib.h". > > --- lib/clear_cache.c > +++ lib/clear_cache.c > @@ -8,6 +8,8 @@ > * ===----------------------------------------------------------------------=== > */ > > +#include "int_lib.h" > + > #if __APPLE__ > #include > #endif > > Change #2: > > The code provided in trampoline_setup.c only seems to apply to 32-bit > PowerPC systems -- not 64-bit systems. Don't cause a build failure on > those systems. > > --- lib/trampoline_setup.c > +++ lib/trampoline_setup.c > @@ -20,7 +20,7 @@ > * and then jumps to the target nested function. > */ > > -#if __ppc__ > +#if __ppc__ && !defined(__powerpc64__) > void __trampoline_setup(uint32_t* trampOnStack, int trampSizeAllocated, > const void* realFunc, void* localsPtr) > { > > -- > Ed Schouten > WWW: http://80386.nl/ > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From matthewbg at google.com Tue Jan 3 13:03:59 2012 From: matthewbg at google.com (Matt Beaumont-Gay) Date: Tue, 03 Jan 2012 19:03:59 -0000 Subject: [llvm-commits] [llvm] r147459 - /llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Message-ID: <20120103190359.D3B372A6C12C@llvm.org> Author: matthewbg Date: Tue Jan 3 13:03:59 2012 New Revision: 147459 URL: http://llvm.org/viewvc/llvm-project?rev=147459&view=rev Log: Fix malformed assert. If anybody has strong feelings about 'default: assert(0 && "blah")' vs 'default: llvm_unreachable("blah")', feel free to regularize the instances of each in this file. Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp?rev=147459&r1=147458&r2=147459&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp (original) +++ llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Tue Jan 3 13:03:59 2012 @@ -6192,7 +6192,7 @@ ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(Inst.getOperand(3).getImm()); if (SOpc == ARM_AM::rrx) return false; switch (Inst.getOpcode()) { - default: assert("unexpected opcode!"); + default: assert(0 && "unexpected opcode!"); case ARM::ANDrsi: newOpc = ARM::ANDrr; break; case ARM::ORRrsi: newOpc = ARM::ORRrr; break; case ARM::EORrsi: newOpc = ARM::EORrr; break; From sabre at nondot.org Tue Jan 3 13:09:13 2012 From: sabre at nondot.org (Chris Lattner) Date: Tue, 03 Jan 2012 19:09:13 -0000 Subject: [llvm-commits] [www] r147460 - /www/trunk/devmtg/2011-11/index.html Message-ID: <20120103190913.A584F2A6C12C@llvm.org> Author: lattner Date: Tue Jan 3 13:09:12 2012 New Revision: 147460 URL: http://llvm.org/viewvc/llvm-project?rev=147460&view=rev Log: add some video links Modified: www/trunk/devmtg/2011-11/index.html Modified: www/trunk/devmtg/2011-11/index.html URL: http://llvm.org/viewvc/llvm-project/www/trunk/devmtg/2011-11/index.html?rev=147460&r1=147459&r2=147460&view=diff ============================================================================== --- www/trunk/devmtg/2011-11/index.html (original) +++ www/trunk/devmtg/2011-11/index.html Tue Jan 3 13:09:12 2012 @@ -51,8 +51,7 @@ [Slides] -

    [Video] (Computer) -
    [Video] (Mobile)

    +

    [Video]

    Extending Clang
    Doug Gregor, Apple @@ -103,8 +102,7 @@ [Slides] -

    [Video] (Computer) -
    [Video] (Mobile)

    +

    [Video]

    LLVM MC In Practice
    Jim Grosbach, Owen Anderson Apple @@ -140,8 +138,7 @@ [Slides] -

    [Video] (Computer) -
    [Video] (Mobile)

    +

    [Video]

    Register Allocation in LLVM 3.0
    Jakob Olesen, Apple From daniel at zuster.org Tue Jan 3 13:10:08 2012 From: daniel at zuster.org (Daniel Dunbar) Date: Tue, 03 Jan 2012 19:10:08 -0000 Subject: [llvm-commits] [zorg] r147461 - /zorg/trunk/lnt/lnt/server/reporting/analysis.py Message-ID: <20120103191008.16FD82A6C12C@llvm.org> Author: ddunbar Date: Tue Jan 3 13:10:07 2012 New Revision: 147461 URL: http://llvm.org/viewvc/llvm-project?rev=147461&view=rev Log: [lnt/v0.4] lnt.server.ui/v4: Fix stddev estimation when all prev samples failed. Modified: zorg/trunk/lnt/lnt/server/reporting/analysis.py Modified: zorg/trunk/lnt/lnt/server/reporting/analysis.py URL: http://llvm.org/viewvc/llvm-project/zorg/trunk/lnt/lnt/server/reporting/analysis.py?rev=147461&r1=147460&r2=147461&view=diff ============================================================================== --- zorg/trunk/lnt/lnt/server/reporting/analysis.py (original) +++ zorg/trunk/lnt/lnt/server/reporting/analysis.py Tue Jan 3 13:10:07 2012 @@ -98,13 +98,13 @@ # runs. # # FIXME: This is using the wrong status kind. :/ - prev_samples = [v for run in comparison_window - for v in self.sample_map.get((run.id, test_id), ())] + prev_samples = [s for run in comparison_window + for s in self.sample_map.get((run.id, test_id), ())] + # Filter out failing samples. + if status_field: + prev_samples = [s for s in prev_samples + if s.get_field(status_field) == PASS] if prev_samples: - # Filter out failing samples. - if status_field: - prev_samples = [s for s in prev_samples - if s.get_field(status_field) == PASS] prev_values = [s.get_field(field) for s in prev_samples] stddev = stats.standard_deviation(prev_values) From daniel at zuster.org Tue Jan 3 13:10:12 2012 From: daniel at zuster.org (Daniel Dunbar) Date: Tue, 03 Jan 2012 19:10:12 -0000 Subject: [llvm-commits] [zorg] r147462 - /zorg/trunk/lnt/lnt/server/reporting/runs.py Message-ID: <20120103191012.60EA32A6C12C@llvm.org> Author: ddunbar Date: Tue Jan 3 13:10:12 2012 New Revision: 147462 URL: http://llvm.org/viewvc/llvm-project?rev=147462&view=rev Log: [lnt/v0.4] lnt.server.reporting: Add report time to reports. Modified: zorg/trunk/lnt/lnt/server/reporting/runs.py Modified: zorg/trunk/lnt/lnt/server/reporting/runs.py URL: http://llvm.org/viewvc/llvm-project/zorg/trunk/lnt/lnt/server/reporting/runs.py?rev=147462&r1=147461&r2=147462&view=diff ============================================================================== --- zorg/trunk/lnt/lnt/server/reporting/runs.py (original) +++ zorg/trunk/lnt/lnt/server/reporting/runs.py Tue Jan 3 13:10:12 2012 @@ -4,6 +4,7 @@ import StringIO import os +import time import urllib import lnt.server.reporting.analysis @@ -22,6 +23,8 @@ assert num_comparison_runs > 0 + start_time = time.time() + ts = run.testsuite machine = run.machine machine_parameters = machine.parameters @@ -220,9 +223,15 @@

    Changes Detail

    """ for field,field_results in test_results: - _add_report_changes_detail(field, field_results, report, + _add_report_changes_detail(ts, field, field_results, report, html_report, report_url) + report_time = time.time() - start_time + print >>report, "Report Time: %.2fs" % (report_time,) + print >>html_report, """ +
    +Report Time: %.2fs""" % (report_time,) + # Finish up the HTML report (wrapping the body, if necessary). html_report = html_report.getvalue() if not only_html_body: @@ -248,8 +257,9 @@ return subject, report.getvalue(), html_report -def _add_report_changes_detail(field, field_results, report, html_report, +def _add_report_changes_detail(ts, field, field_results, report, html_report, report_url): + field_index = ts.sample_fields.index(field) field_display_name = { "compile_time" : "Compile Time", "execution_time" : "Execution Time" }.get(field.name) for bucket_name,bucket,show_perf in field_results: @@ -291,7 +301,8 @@ cr.previous, cr.current, stddev_value) # Link the regression to the chart of its performance. - form_data = urllib.urlencode([('test.%d' % test_id, 'on')]) + form_data = urllib.urlencode([('test.%d' % test_id, + str(field_index))]) linked_name = '%s' % ( os.path.join(report_url, "graph"), form_data, name) From daniel at zuster.org Tue Jan 3 13:10:15 2012 From: daniel at zuster.org (Daniel Dunbar) Date: Tue, 03 Jan 2012 19:10:15 -0000 Subject: [llvm-commits] [zorg] r147463 - in /zorg/trunk/lnt/lnt/server/ui: templates/v4_graph.html views.py Message-ID: <20120103191015.AE52D1BE003@llvm.org> Author: ddunbar Date: Tue Jan 3 13:10:15 2012 New Revision: 147463 URL: http://llvm.org/viewvc/llvm-project?rev=147463&view=rev Log: [lnt/v0.4] lnt.server.ui/v4: Add graph support for V4 databases. Added: zorg/trunk/lnt/lnt/server/ui/templates/v4_graph.html Modified: zorg/trunk/lnt/lnt/server/ui/views.py Added: zorg/trunk/lnt/lnt/server/ui/templates/v4_graph.html URL: http://llvm.org/viewvc/llvm-project/zorg/trunk/lnt/lnt/server/ui/templates/v4_graph.html?rev=147463&view=auto ============================================================================== --- zorg/trunk/lnt/lnt/server/ui/templates/v4_graph.html (added) +++ zorg/trunk/lnt/lnt/server/ui/templates/v4_graph.html Tue Jan 3 13:10:15 2012 @@ -0,0 +1,107 @@ +{% import "v4_utils.html" as v4_utils %} +{% import "utils.html" as utils %} + +{% set machine = run.machine %} + +{% extends "layout.html" %} +{% set components = [(ts.name, v4_url_for("v4_overview")), + ('machine', v4_url_for("v4_machine", id=machine.id))] %} +{% block head %} + + + +{% endblock %} + +{% block title %}Graph{% endblock %} + +{# Add JS to initialize the graph. #} +{% block onload %}init(){% endblock %} +{% block javascript %} +function init() { + graph = new Graph2D("graph"); + graph.clearColor = [1, 1, 1]; + +{% for plot in graph_plots %} + {{ plot }} +{% endfor %} + + graph.xAxis.format = graph.xAxis.formats.normal; + graph.draw(); +} +{% endblock %} + +{% block body %} + +{% call v4_utils.v4_run_page(ts, machine, run, compare_to, neighboring_runs) %} + +{{ utils.render_popup_begin('view_options', 'View Options', true) }} +
    +Show Median Absolute Deviation: +
    + +Show Standard Deviation: +
    + +Show Linear Regression: +
    + +Show Points For Failures: +
    + +Show Sample Points: +
    + +Show All Sample Points: +
    + +{# Add all the hidden fields. #} +{% for name,value in request.args.items() %} + {% if name.startswith('test.') %} + + {% endif %} +{% endfor %} + + +
    +{{ utils.render_popup_end() }} + +

    Graph

    + + + + + +
    + + + + +{% for name,field_name,col in legend %} + + + + + +{% endfor %} +
    Test
     {{name}}{{field_name}}
    +
    + +Shift-Left Mouse: Pan
    +Alt/Meta-Left Mouse: Zoom
    +Wheel: Zoom (Shift Slows)
    +     +
    +

    +Plots: {{ num_plots }}
    +Num Points: {{ num_points }}
    + +{% endcall %} + +{% endblock %} Modified: zorg/trunk/lnt/lnt/server/ui/views.py URL: http://llvm.org/viewvc/llvm-project/zorg/trunk/lnt/lnt/server/ui/views.py?rev=147463&r1=147462&r2=147463&view=diff ============================================================================== --- zorg/trunk/lnt/lnt/server/ui/views.py (original) +++ zorg/trunk/lnt/lnt/server/ui/views.py Tue Jan 3 13:10:15 2012 @@ -681,6 +681,10 @@ # Find the neighboring runs, by order. prev_runs = list(ts.get_previous_runs_on_machine(run, N = 3)) next_runs = list(ts.get_next_runs_on_machine(run, N = 3)) + if prev_runs: + compare_to = prev_runs[0] + else: + compare_to = None neighboring_runs = next_runs[::-1] + [run] + prev_runs # Parse the view options. @@ -717,7 +721,7 @@ baseurl=v4_url_for('v4_overview', _external=True), was_added=True, will_commit=True, only_html_body=True) - return render_template("v4_run.html", ts=ts, run=run, + return render_template("v4_run.html", ts=ts, run=run, compare_to=compare_to, options=options, neighboring_runs=neighboring_runs, text_report=text_report, html_report=html_report) @@ -732,3 +736,182 @@ abort(404) return render_template("v4_order.html", ts=ts, order=order) + + at v4_route("//graph") +def v4_graph(id): + from lnt.server.ui import util + from lnt.testing import PASS + from lnt.util import stats + from lnt.external.stats import stats as ext_stats + + ts = request.get_testsuite() + run = ts.query(ts.Run).filter_by(id=id).first() + if run is None: + abort(404) + + # Find the neighboring runs, by order. + prev_runs = list(ts.get_previous_runs_on_machine(run, N = 3)) + next_runs = list(ts.get_next_runs_on_machine(run, N = 3)) + if prev_runs: + compare_to = prev_runs[0] + else: + compare_to = None + neighboring_runs = next_runs[::-1] + [run] + prev_runs + + # Parse the view options. + options = {} + options['show_mad'] = show_mad = bool(request.args.get('show_mad')) + options['show_stddev'] = show_stddev = bool(request.args.get('show_stddev')) + options['show_points'] = show_points = bool(request.args.get('show_points')) + options['show_all_points'] = show_all_points = bool( + request.args.get('show_all_points')) + options['show_linear_regression'] = show_linear_regression = bool( + request.args.get('show_linear_regression', True)) + options['show_failures'] = show_failures = bool( + request.args.get('show_failures')) + + # Load the graph parameters. + graph_tests = [] + for name,value in request.args.items(): + # Tests to graph are passed as test.=. + if not name.startswith(str('test.')): + continue + + # Extract the test id string and convert to integers. + test_id_str = name[5:] + try: + test_id = int(test_id_str) + field_index = int(value) + except: + return abort(400) + + # Get the test and the field. + if not (0 <= field_index < len(ts.sample_fields)): + return abort(400) + + test = ts.query(ts.Test).filter(ts.Test.id == test_id).one() + field = ts.sample_fields[field_index] + + graph_tests.append((test, field)) + + # Order the plots by test name and then field. + graph_tests.sort(key = lambda (t,f): (t.name, f.name)) + + # Build the graph data. + legend = [] + graph_plots = [] + num_points = 0 + num_plots = len(graph_tests) + for i,(test,field) in enumerate(graph_tests): + # Determine the base plot color. + col = list(util.makeDarkColor(float(i) / num_plots)) + legend.append((test.name, field.name, tuple(col))) + + # Load all the field values for this test on the same machine. + # + # FIXME: Don't join to Order here, aggregate this across all the tests + # we want to load. Actually, we should just make this a single query. + q = ts.query(field.column, ts.Order.ordinal).\ + join(ts.Run).join(ts.Order).\ + filter(ts.Run.machine == run.machine).\ + filter(ts.Sample.test == test) + + # Unless all samples requested, filter out failing tests. + if not show_failures: + if field.status_field: + q = q.filter(field.status_field.column == PASS) + + # Aggregate by run order id. + data = util.multidict((r,v) + for v,r in q).items() + data.sort() + + # Compute the graph points. + errorbar_data = [] + points_data = [] + pts = [] + for x,values in data: + pts.append((x, min(values))) + + # Add the individual points, if requested. + if show_points: + if show_all_points: + for v in values: + points_data.append((x, v)) + else: + points_data.append((x, min_value)) + + # Add the standard deviation error bar, if requested. + if show_stddev: + mean = stats.mean(values) + sigma = stats.standard_deviation(values) + errorbar_data.append((x, mean - sigma, mean + sigma)) + + # Add the MAD error bar, if requested. + if show_mad: + med = stats.median(values) + mad = stats.median_absolute_deviation(values, med) + errorbar_data.append((x, med - mad, med + mad)) + + # Add the minimum line plot. + num_points += len(data) + graph_plots.append("graph.addPlot([%s], %s);" % ( + ','.join(['[%.4f,%.4f]' % (t,v) + for t,v in pts]), + "new Graph2D_LinePlotStyle(1, %r)" % col)) + + # Add regression line, if requested. + if show_linear_regression: + xs = [t for t,v in pts] + ys = [v for t,v in pts] + + # We compute the regression line in terms of a normalized X scale. + x_min, x_max = min(xs), max(xs) + try: + norm_xs = [(x - x_min) / (x_max - x_min) + for x in xs] + except ZeroDivisionError: + norm_xs = xs + + try: + info = ext_stats.linregress(norm_xs, ys) + except ZeroDivisionError: + info = None + except ValueError: + info = None + + if info is not None: + slope, intercept,_,_,_ = info + + reglin_col = [c*.5 for c in col] + pts = ','.join('[%.4f,%.4f]' % pt + for pt in [(x_min, 0.0 * slope + intercept), + (x_max, 1.0 * slope + intercept)]) + style = "new Graph2D_LinePlotStyle(4, %r)" % ([.7, .7, .7],) + graph_plots.append("graph.addPlot([%s], %s);" % ( + pts,style)) + style = "new Graph2D_LinePlotStyle(2, %r)" % (reglin_col,) + graph_plots.append("graph.addPlot([%s], %s);" % ( + pts,style)) + + # Add the points plot, if used. + if points_data: + pts_col = (0,0,0) + graph_plots.append("graph.addPlot([%s], %s);" % ( + ','.join(['[%.4f,%.4f]' % (t,v) + for t,v in points_data]), + "new Graph2D_PointPlotStyle(1, %r)" % (pts_col,))) + + # Add the error bar plot, if used. + if errorbar_data: + bar_col = [c*.7 for c in col] + graph_plots.append("graph.addPlot([%s], %s);" % ( + ','.join(['[%.4f,%.4f,%.4f]' % (x,y_min,y_max) + for x,y_min,y_max in errorbar_data]), + "new Graph2D_ErrorBarPlotStyle(1, %r)" % (bar_col,))) + + return render_template("v4_graph.html", ts=ts, run=run, + compare_to=compare_to, options=options, + num_plots=num_plots, num_points=num_points, + neighboring_runs=neighboring_runs, + graph_plots=graph_plots, legend=legend) From daniel at zuster.org Tue Jan 3 13:10:18 2012 From: daniel at zuster.org (Daniel Dunbar) Date: Tue, 03 Jan 2012 19:10:18 -0000 Subject: [llvm-commits] [zorg] r147464 - /zorg/trunk/lnt/lnt/server/reporting/analysis.py Message-ID: <20120103191018.82A062A6C12C@llvm.org> Author: ddunbar Date: Tue Jan 3 13:10:18 2012 New Revision: 147464 URL: http://llvm.org/viewvc/llvm-project?rev=147464&view=rev Log: [lnt/v0.4] lnt.server.ui/v4: Speed up report generation by not materializing Sample objects. Modified: zorg/trunk/lnt/lnt/server/reporting/analysis.py Modified: zorg/trunk/lnt/lnt/server/reporting/analysis.py URL: http://llvm.org/viewvc/llvm-project/zorg/trunk/lnt/lnt/server/reporting/analysis.py?rev=147464&r1=147463&r2=147464&view=diff ============================================================================== --- zorg/trunk/lnt/lnt/server/reporting/analysis.py (original) +++ zorg/trunk/lnt/lnt/server/reporting/analysis.py Tue Jan 3 13:10:18 2012 @@ -16,8 +16,13 @@ def get_run_comparison_result(self, run, compare_to, test_id, field, comparison_window=[]): + field_index = self.testsuite.sample_fields.index(field) + # Get the field which indicates the requested field's status. status_field = field.status_field + if status_field: + status_field_index = self.testsuite.sample_fields.index( + status_field) # Load the sample data for the current and previous runs and the # comparison window. @@ -43,13 +48,13 @@ run_failed = prev_failed = False if status_field: for sample in run_samples: - run_failed |= sample.get_field(status_field) == FAIL + run_failed |= sample[status_field_index] == FAIL for sample in prev_samples: - prev_failed |= sample.get_field(status_field) == FAIL + prev_failed |= sample[status_field_index] == FAIL # Get the current and previous values. - run_values = [s.get_field(field) for s in run_samples] - prev_values = [s.get_field(field) for s in prev_samples] + run_values = [s[field_index] for s in run_samples] + prev_values = [s[field_index] for s in prev_samples] if run_values: run_value = min(run_values) else: @@ -103,9 +108,9 @@ # Filter out failing samples. if status_field: prev_samples = [s for s in prev_samples - if s.get_field(status_field) == PASS] + if s[status_field_index] == PASS] if prev_samples: - prev_values = [s.get_field(field) + prev_values = [s[field_index] for s in prev_samples] stddev = stats.standard_deviation(prev_values) MAD = stats.median_absolute_deviation(prev_values) @@ -124,10 +129,19 @@ return # Batch load all of the samples for the needed runs. - q = self.testsuite.query(self.testsuite.Sample) + # + # We speed things up considerably by loading the column data directly + # here instead of requiring SA to materialize Sample objects. + columns = [self.testsuite.Sample.run_id, + self.testsuite.Sample.test_id] + columns.extend(f.column for f in self.testsuite.sample_fields) + q = self.testsuite.query(*columns) q = q.filter(self.testsuite.Sample.run_id.in_(to_load)) - for sample in q: - self.sample_map[(sample.run_id, sample.test_id)] = sample + for data in q: + run_id = data[0] + test_id = data[1] + sample_values = data[2:] + self.sample_map[(run_id, test_id)] = sample_values self.loaded_run_ids |= to_load From sabre at nondot.org Tue Jan 3 13:14:58 2012 From: sabre at nondot.org (Chris Lattner) Date: Tue, 03 Jan 2012 19:14:58 -0000 Subject: [llvm-commits] [www] r147465 - /www/trunk/devmtg/2011-11/index.html Message-ID: <20120103191458.D3ACD2A6C12C@llvm.org> Author: lattner Date: Tue Jan 3 13:14:58 2012 New Revision: 147465 URL: http://llvm.org/viewvc/llvm-project?rev=147465&view=rev Log: a dragon ate Chandler's slides - they can be seen in the video, remove the link Modified: www/trunk/devmtg/2011-11/index.html Modified: www/trunk/devmtg/2011-11/index.html URL: http://llvm.org/viewvc/llvm-project/www/trunk/devmtg/2011-11/index.html?rev=147465&r1=147464&r2=147465&view=diff ============================================================================== --- www/trunk/devmtg/2011-11/index.html (original) +++ www/trunk/devmtg/2011-11/index.html Tue Jan 3 13:14:58 2012 @@ -65,8 +65,8 @@ Intel OpenCL SDK Vectorizer
    Nadav Rotem, Intel -[Slides] -

    [Video] (Computer) + +[Video] (Computer)
    [Video] (Mobile)

    Clang MapReduce -- Automatic C++ Refactoring at Google Scale
    Chandler Carruth, Google From baldrick at free.fr Tue Jan 3 13:44:48 2012 From: baldrick at free.fr (Duncan Sands) Date: Tue, 03 Jan 2012 20:44:48 +0100 Subject: [llvm-commits] [LLVM, PR11652 PATCH]: Fixed Bug 11652 - assertion failures when Type.cpp is compiled with -Os In-Reply-To: <200591325616621@web103.yandex.ru> References: <4EFE13EC.2010801@narod.ru> <4F0180C5.1080206@free.fr> <191841325500240@web28.yandex.ru> <4F018912.3000107@free.fr> <200971325501753@web58.yandex.ru> <4F018F55.1040604@free.fr> <1136931325507957@web94.yandex.ru> <4F01CC81.4010909@free.fr> <359001325533597@web8.yandex.ru> <4F02BD1B.7070808@free.fr> <673781325580638@web123.yandex.ru> <4F02C1AA.1080707@free.fr> <602271325599963@web1.yandex.ru> <4F030EDE.1090002@free.fr> <200591325616621@web103.yandex.ru> Message-ID: <4F035AB0.5080202@free.fr> Hi Stepan, > Hi, Duncan. Please find the second patch attached. looks good to me. Please put the include for DataTypes after the include for Casting to keep them in alphabetical order and then apply. Ciao, Duncan. > -Stepan. > > 03.01.2012, 18:21, "Duncan Sands": >> Hi Stepan, >> >>> Oh.. of course. Commited as r147446. For next patch, did you mean that I should check that TypeID was properly stored in its 8 bits? Something like this: >>> >>> void setTypeID(TypeID ID) { >>> IDAndSubclassData = (ID& 0xFF) | (IDAndSubclassData& 0xFFFFFF00); >>> assert(IDAndSubclassData& 0xFF == ID&& "Type data too large for field"); >>> } >> >> yes, something like that. Better to use >> >> assert(getTypeID() == ID&& "Type data too large for field!"); >> >> though IMO. >> >> Ciao, Duncan. >> >>> -Stepan >>> >>> 03.01.2012, 12:51, "Duncan Sands": >>>> Hi Stepan, >>>>> Hi Duncan, can I use DataTypes.h instead? >>>> this patch doesn't require either. It is the next patch that needs it, right? >>>> >>>> Ciao, Duncan. >>>>> -Stepan. >>>>> >>>>> 03.01.2012, 12:32, "Duncan Sands": >>>>>> Hi Stepan, this looks fine except for a pointless include of stdint.h. Please >>>>>> apply, except for the include. >>>>>> >>>>>> Thanks for doing this, >>>>>> >>>>>> Duncan. >>>>>>> Hi, Duncan. Please find the first patch in attachment. Replacement: ID with getTypeID(). >>>>>>> - Stepan >>>>>>> >>>>>>> 02.01.2012, 19:25, "Duncan Sands": >>>>>>>> Hi Stepan, >>>>>>>>> OK. Please look at patch in attachment. >>>>>>>>> I'm not sure that it is better than previous patch. Probably the first one looks like a workaround, but it changes setSubclassData only. New patch changes set/getSubclassData set/getTypeID, and all methods that uses ID. >>>>>>>> thanks for doing this. I think it is a better abstraction to have getters >>>>>>>> and setters for ID, like the ones that already exist for SubclassData. Can >>>>>>>> you therefore split the patch in two: one patch that adds getters and setters, >>>>>>>> and then a second one that drops the bitfield in favour of explicit bit >>>>>>>> fiddling. >>>>>>>> >>>>>>>> Additional comments: >>>>>>>> - you made some lines too long (> 80 columns). >>>>>>>> - this is not your fault, but I think there should be a check that ID values >>>>>>>> fit in the allocated space, for example by checking somehow that there is >>>>>>>> enough room for every value of the TypeID type. Alternatively, in setTypeID >>>>>>>> check that the value you read back out matches the value put in. The >>>>>>>> constructor can also set the ID. It should probably initialize >>>>>>>> IDAndSubclassData to zero, and then call setTypeID in the body of the >>>>>>>> constructor to set the value. >>>>>>>> >>>>>>>> Ciao, Duncan. >>>>>>>>> -Stepan. >>>>>>>>> >>>>>>>>> 02.01.2012, 15:04, "Duncan Sands": >>>>>>>>>> Hi Stepan, >>>>>>>>>>> ID is used very extensively in Type.h. We need to fix a lots, so we need to fix all methods like: >>>>>>>>>>> bool isIntegerTy() const { return ID == IntegerTyID; } >>>>>>>>>> you could turn ID into a private method that extracts the id part of the field. >>>>>>>>>> Then you just need to turn ID into ID() in places such as isIntegerTy. Likewise >>>>>>>>>> for SubclassData. >>>>>>>>>>> But in the same time we can apply some working decision until gcc bug will fixed. >>>>>>>>>>> May be add some dummy field? >>>>>>>>>>> TypeID ID : 8; >>>>>>>>>>> unsigned SubclassData : 24; >>>>>>>>>>> unsigned KungFuPanda; // Will protect NumContainedTys from overwriting. >>>>>>>>>>> unsigned NumContainedTys; // Will OK. >>>>>>>>>> Even if the gcc bug is fixed, people will be using older compilers with the bug >>>>>>>>>> for years to come. So this field would be around essentially forever. Given >>>>>>>>>> that, I don't think this is a good solution. If you are prepared to make the >>>>>>>>>> class bigger, you might as well not have the fields be bitfields at all (and >>>>>>>>>> change the order so that things are well packed). >>>>>>>>>> >>>>>>>>>> Ciao, Duncan. >>>>>>>>>>> -Stepan. >>>>>>>>>>> >>>>>>>>>>> 02.01.2012, 14:38, "Duncan Sands": >>>>>>>>>>>> Hi Stepan, >>>>>>>>>>>>> I tried it doesn't helps. Now it seems that ID is overwritten. 4807 unexpected failures. >>>>>>>>>>>> OK, thanks for the info. How about doing the bit fiddling yourself instead? >>>>>>>>>>>> I.e. rather than trying to fool the optimizers, don't use bitfields: declare >>>>>>>>>>>> an unsigned field IDAndSubclassData and store and load values from it using >>>>>>>>>>>> explicit shifts etc. This would then completely avoid all problems coming >>>>>>>>>>>> from misoptimization of bitfields (which has happened a lot historically), >>>>>>>>>>>> and would be less fragile than trying to fool the optimizers via some magic >>>>>>>>>>>> incantation. >>>>>>>>>>>> >>>>>>>>>>>> Ciao, Duncan. >>>>>>>>>>>>> -Stepan. >>>>>>>>>>>>> >>>>>>>>>>>>> 02.01.2012, 14:02, "Duncan Sands": >>>>>>>>>>>>>> Hi Stepan, >>>>>>>>>>>>>>> The problem is in Type.h. The fields in Type class are declared in next order: >>>>>>>>>>>>>>> TypeID ID : 8; >>>>>>>>>>>>>>> unsigned SubclassData : 24; >>>>>>>>>>>>>>> unsigned NumContainedTys; >>>>>>>>>>>>>> does the problem still occur if you flip the order of ID and SubclassData? >>>>>>>>>>>>>> I.e. >>>>>>>>>>>>>> unsigned SubclassData : 24; >>>>>>>>>>>>>> TypeID ID : 8; >>>>>>>>>>>>>> unsigned NumContainedTys; >>>>>>>>>>>>>> ? >>>>>>>>>>>>>> Ciao, Duncan. >>>>>>>>>>>>>>> Attempt to set new SubclassData value rewrites lowest byte in NumContainedTys >>>>>>>>>>>>>>> when -Os is set. GCC bug? Anyway setting SubclassData with two workaround >>>>>>>>>>>>>>> strings fixes the problem: >>>>>>>>>>>>>>> >>>>>>>>>>>>>>> void setSubclassData(unsigned val) { >>>>>>>>>>>>>>> unsigned tmp = NumContainedTys; // Workaround for GCC -Os >>>>>>>>>>>>>>> SubclassData = val; >>>>>>>>>>>>>>> NumContainedTys = tmp; // Workaround for GCC -Os >>>>>>>>>>>>>>> // Ensure we don't have any accidental truncation. >>>>>>>>>>>>>>> assert(SubclassData == val&& "Subclass data too large for field"); >>>>>>>>>>>>>>> } >>>>>>>>>>>>>>> >>>>>>>>>>>>>>> Probably there is another ways to protect NumContainedTys from overwritting? >>>>>>>>>>>>>>> >>>>>>>>>>>>>>> Please find the patch in attachment for review. >>>>>>>>>>>>>>> >>>>>>>>>>>>>>> -Stepan. >>>>>>>>>>>>>>> >>>>>>>>>>>>>>> _______________________________________________ >>>>>>>>>>>>>>> llvm-commits mailing list >>>>>>>>>>>>>>> llvm-commits at cs.uiuc.edu >>>>>>>>>>>>>>> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits >>>>>>>>>>>>>> _______________________________________________ >>>>>>>>>>>>>> llvm-commits mailing list >>>>>>>>>>>>>> llvm-commits at cs.uiuc.edu >>>>>>>>>>>>>> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From jan_sjodin at yahoo.com Tue Jan 3 14:00:48 2012 From: jan_sjodin at yahoo.com (Jan Sjodin) Date: Tue, 3 Jan 2012 12:00:48 -0800 (PST) Subject: [llvm-commits] XOP Intrinsics patch In-Reply-To: References: <1325607159.50862.YahooMailNeo@web161503.mail.bf1.yahoo.com> Message-ID: <1325620848.29233.YahooMailNeo@web161506.mail.bf1.yahoo.com> >All integer vector loads in patterns need to be memopv2i64(!28-bit) or memopv4i64(256-bit) and bitcasted to the correct type because all integer vector loads are promoted to v2i64 or v4i64. So for instance > >+def : Pat<(int_x86_xop_vphsubwd (alignedloadv8i16 addr:$src1)), >+????????? (VPHSUBWDrm addr:$src1)>; > >Needs to be > >+def : Pat<(int_x86_xop_vphsubwd (bc_v8i16 (memopv2i64 addr:$src1))), >+????????? (VPHSUBWDrm addr:$src1)>; > If the promotion always happens, maybe it would be best to remove patterns like: def memopv8i16 : PatFrag<(ops node:$ptr), (v8i16 (memop node:$ptr))>; def memopv16i8 : PatFrag<(ops node:$ptr), (v16i8 (memop node:$ptr))>; - Jan From stpworld at narod.ru Tue Jan 3 14:04:35 2012 From: stpworld at narod.ru (Stepan Dyatkovskiy) Date: Tue, 03 Jan 2012 20:04:35 -0000 Subject: [llvm-commits] [llvm] r147470 - /llvm/trunk/include/llvm/Type.h Message-ID: <20120103200435.6D9752A6C12C@llvm.org> Author: dyatkovskiy Date: Tue Jan 3 14:04:35 2012 New Revision: 147470 URL: http://llvm.org/viewvc/llvm-project?rev=147470&view=rev Log: Fix for PR11652: assertion failures when Type.cpp is compiled with -Os Modified: llvm/trunk/include/llvm/Type.h Modified: llvm/trunk/include/llvm/Type.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Type.h?rev=147470&r1=147469&r2=147470&view=diff ============================================================================== --- llvm/trunk/include/llvm/Type.h (original) +++ llvm/trunk/include/llvm/Type.h Tue Jan 3 14:04:35 2012 @@ -16,6 +16,7 @@ #define LLVM_TYPE_H #include "llvm/Support/Casting.h" +#include "llvm/Support/DataTypes.h" namespace llvm { @@ -75,21 +76,32 @@ /// Context - This refers to the LLVMContext in which this type was uniqued. LLVMContext &Context; - TypeID ID : 8; // The current base type of this type. - unsigned SubclassData : 24; // Space for subclasses to store data + // Due to Ubuntu GCC bug 910363: + // https://bugs.launchpad.net/ubuntu/+source/gcc-4.5/+bug/910363 + // Bitpack ID and SubclassData manually. + // Note: TypeID : low 8 bit; SubclassData : high 24 bit. + uint32_t IDAndSubclassData; protected: friend class LLVMContextImpl; explicit Type(LLVMContext &C, TypeID tid) - : Context(C), ID(tid), SubclassData(0), - NumContainedTys(0), ContainedTys(0) {} + : Context(C), IDAndSubclassData(0), + NumContainedTys(0), ContainedTys(0) { + setTypeID(tid); + } ~Type() {} - - unsigned getSubclassData() const { return SubclassData; } + + void setTypeID(TypeID ID) { + IDAndSubclassData = (ID & 0xFF) | (IDAndSubclassData & 0xFFFFFF00); + assert(getTypeID() == ID && "TypeID data too large for field"); + } + + unsigned getSubclassData() const { return IDAndSubclassData >> 8; } + void setSubclassData(unsigned val) { - SubclassData = val; + IDAndSubclassData = (IDAndSubclassData & 0xFF) | (val << 8); // Ensure we don't have any accidental truncation. - assert(SubclassData == val && "Subclass data too large for field"); + assert(getSubclassData() == val && "Subclass data too large for field"); } /// NumContainedTys - Keeps track of how many Type*'s there are in the @@ -117,7 +129,7 @@ /// getTypeID - Return the type id for the type. This will return one /// of the TypeID enum elements defined above. /// - TypeID getTypeID() const { return ID; } + TypeID getTypeID() const { return (TypeID)(IDAndSubclassData & 0xFF); } /// isVoidTy - Return true if this is 'void'. bool isVoidTy() const { return getTypeID() == VoidTyID; } From STPWORLD at narod.ru Tue Jan 3 14:08:35 2012 From: STPWORLD at narod.ru (Stepan Dyatkovskiy) Date: Wed, 04 Jan 2012 00:08:35 +0400 Subject: [llvm-commits] [LLVM, PR11652 PATCH]: Fixed Bug 11652 - assertion failures when Type.cpp is compiled with -Os In-Reply-To: <4F035AB0.5080202@free.fr> References: <4EFE13EC.2010801@narod.ru> <4F0180C5.1080206@free.fr> <191841325500240@web28.yandex.ru> <4F018912.3000107@free.fr> <200971325501753@web58.yandex.ru> <4F018F55.1040604@free.fr> <1136931325507957@web94.yandex.ru> <4F01CC81.4010909@free.fr> <359001325533597@web8.yandex.ru> <4F02BD1B.7070808@free.fr> <673781325580638@web123.yandex.ru> <4F02C1AA.1080707@free.fr> <602271325599963@web1.yandex.ru> <4F030EDE.1090002@free.fr> <200591325616621@web103.yandex.ru> <4F035AB0.5080202@free.fr> Message-ID: <781091325621315@web133.yandex.ru> OK. Commited as r147470. -Stepan. 03.01.2012, 23:44, "Duncan Sands" : > Hi Stepan, > >> ?Hi, Duncan. Please find the second patch attached. > > looks good to me. ?Please put the include for DataTypes after the > include for Casting to keep them in alphabetical order and then apply. > > Ciao, Duncan. > >> ?-Stepan. >> >> ?03.01.2012, 18:21, "Duncan Sands": >>> ?Hi Stepan, >>>> ???Oh.. of course. Commited as r147446. For next patch, did you mean that I should check that TypeID was properly stored in its 8 bits? Something like this: >>>> >>>> ???void setTypeID(TypeID ID) { >>>> ???????IDAndSubclassData = (ID& ???0xFF) | (IDAndSubclassData& ???0xFFFFFF00); >>>> ???????assert(IDAndSubclassData& ???0xFF == ID&& ???"Type data too large for field"); >>>> ???} >>> ?yes, something like that. ?Better to use >>> >>> ?????assert(getTypeID() == ID&& ?"Type data too large for field!"); >>> >>> ?though IMO. >>> >>> ?Ciao, Duncan. >>>> ???-Stepan >>>> >>>> ???03.01.2012, 12:51, "Duncan Sands": >>>>> ???Hi Stepan, >>>>>> ?????Hi Duncan, can I use DataTypes.h instead? >>>>> ???this patch doesn't require either. ?It is the next patch that needs it, right? >>>>> >>>>> ???Ciao, Duncan. >>>>>> ?????-Stepan. >>>>>> >>>>>> ?????03.01.2012, 12:32, "Duncan Sands": >>>>>>> ?????Hi Stepan, this looks fine except for a pointless include of stdint.h. ?Please >>>>>>> ?????apply, except for the include. >>>>>>> >>>>>>> ?????Thanks for doing this, >>>>>>> >>>>>>> ?????Duncan. >>>>>>>> ???????Hi, Duncan. Please find the first patch in attachment. Replacement: ID with getTypeID(). >>>>>>>> ???????- Stepan >>>>>>>> >>>>>>>> ???????02.01.2012, 19:25, "Duncan Sands": >>>>>>>>> ???????Hi Stepan, >>>>>>>>>> ?????????OK. Please look at patch in attachment. >>>>>>>>>> ?????????I'm not sure that it is better than previous patch. Probably the first one looks like a workaround, but it changes setSubclassData only. New patch changes set/getSubclassData set/getTypeID, and all methods that uses ID. >>>>>>>>> ???????thanks for doing this. ?I think it is a better abstraction to have getters >>>>>>>>> ???????and setters for ID, like the ones that already exist for SubclassData. ?Can >>>>>>>>> ???????you therefore split the patch in two: one patch that adds getters and setters, >>>>>>>>> ???????and then a second one that drops the bitfield in favour of explicit bit >>>>>>>>> ???????fiddling. >>>>>>>>> >>>>>>>>> ???????Additional comments: >>>>>>>>> ???????????- you made some lines too long (> ???????80 columns). >>>>>>>>> ???????????- this is not your fault, but I think there should be a check that ID values >>>>>>>>> ?????????????fit in the allocated space, for example by checking somehow that there is >>>>>>>>> ?????????????enough room for every value of the TypeID type. ?Alternatively, in setTypeID >>>>>>>>> ?????????????check that the value you read back out matches the value put in. ?The >>>>>>>>> ?????????????constructor can also set the ID. ?It should probably initialize >>>>>>>>> ?????????????IDAndSubclassData to zero, and then call setTypeID in the body of the >>>>>>>>> ?????????????constructor to set the value. >>>>>>>>> >>>>>>>>> ???????Ciao, Duncan. >>>>>>>>>> ?????????-Stepan. >>>>>>>>>> >>>>>>>>>> ?????????02.01.2012, 15:04, "Duncan Sands": >>>>>>>>>>> ?????????Hi Stepan, >>>>>>>>>>>> ???????????ID is used very extensively in Type.h. We need to fix a lots, so we need to fix all methods like: >>>>>>>>>>>> ???????????bool isIntegerTy() const { return ID == IntegerTyID; } >>>>>>>>>>> ?????????you could turn ID into a private method that extracts the id part of the field. >>>>>>>>>>> ?????????Then you just need to turn ID into ID() in places such as isIntegerTy. ?Likewise >>>>>>>>>>> ?????????for SubclassData. >>>>>>>>>>>> ???????????But in the same time we can apply some working decision until gcc bug will fixed. >>>>>>>>>>>> ???????????May be add some dummy field? >>>>>>>>>>>> ??????????????TypeID ??ID : 8; >>>>>>>>>>>> ??????????????unsigned SubclassData : 24; >>>>>>>>>>>> ??????????????unsigned KungFuPanda; ???????// Will protect NumContainedTys from overwriting. >>>>>>>>>>>> ??????????????unsigned NumContainedTys; // Will OK. >>>>>>>>>>> ?????????Even if the gcc bug is fixed, people will be using ?older compilers with the bug >>>>>>>>>>> ?????????for years to come. ?So this field would be around essentially forever. ?Given >>>>>>>>>>> ?????????that, I don't think this is a good solution. ?If you are prepared to make the >>>>>>>>>>> ?????????class bigger, you might as well not have the fields be bitfields at all (and >>>>>>>>>>> ?????????change the order so that things are well packed). >>>>>>>>>>> >>>>>>>>>>> ?????????Ciao, Duncan. >>>>>>>>>>>> ???????????-Stepan. >>>>>>>>>>>> >>>>>>>>>>>> ???????????02.01.2012, 14:38, "Duncan Sands": >>>>>>>>>>>>> ???????????Hi Stepan, >>>>>>>>>>>>>> ?????????????I tried it doesn't helps. Now it seems that ID is overwritten. 4807 unexpected failures. >>>>>>>>>>>>> ???????????OK, thanks for the info. ?How about doing the bit fiddling yourself instead? >>>>>>>>>>>>> ???????????I.e. rather than trying to fool the optimizers, don't use bitfields: declare >>>>>>>>>>>>> ???????????an unsigned field IDAndSubclassData and store and load values from it using >>>>>>>>>>>>> ???????????explicit shifts etc. ?This would then completely avoid all problems coming >>>>>>>>>>>>> ???????????from misoptimization of bitfields (which has happened a lot historically), >>>>>>>>>>>>> ???????????and would be less fragile than trying to fool the optimizers via some magic >>>>>>>>>>>>> ???????????incantation. >>>>>>>>>>>>> >>>>>>>>>>>>> ???????????Ciao, Duncan. >>>>>>>>>>>>>> ?????????????-Stepan. >>>>>>>>>>>>>> >>>>>>>>>>>>>> ?????????????02.01.2012, 14:02, "Duncan Sands": >>>>>>>>>>>>>>> ?????????????Hi Stepan, >>>>>>>>>>>>>>>> ???????????????The problem is in Type.h. The fields in Type class are declared in next order: >>>>>>>>>>>>>>>> ???????????????TypeID ID : 8; >>>>>>>>>>>>>>>> ???????????????unsigned SubclassData : 24; >>>>>>>>>>>>>>>> ???????????????unsigned NumContainedTys; >>>>>>>>>>>>>>> ?????????????does the problem still occur if you flip the order of ID and SubclassData? >>>>>>>>>>>>>>> ?????????????I.e. >>>>>>>>>>>>>>> ?????????????????unsigned SubclassData : 24; >>>>>>>>>>>>>>> ?????????????????TypeID ID : 8; >>>>>>>>>>>>>>> ?????????????????unsigned NumContainedTys; >>>>>>>>>>>>>>> ?????????????? >>>>>>>>>>>>>>> ?????????????Ciao, Duncan. >>>>>>>>>>>>>>>> ???????????????Attempt to set new SubclassData value rewrites lowest byte in NumContainedTys >>>>>>>>>>>>>>>> ???????????????when -Os is set. GCC bug? Anyway setting SubclassData with two workaround >>>>>>>>>>>>>>>> ???????????????strings fixes the problem: >>>>>>>>>>>>>>>> >>>>>>>>>>>>>>>> ???????????????void setSubclassData(unsigned val) { >>>>>>>>>>>>>>>> ???????????????unsigned tmp = NumContainedTys; // Workaround for GCC -Os >>>>>>>>>>>>>>>> ???????????????SubclassData = val; >>>>>>>>>>>>>>>> ???????????????NumContainedTys = tmp; // Workaround for GCC -Os >>>>>>>>>>>>>>>> ???????????????// Ensure we don't have any accidental truncation. >>>>>>>>>>>>>>>> ???????????????assert(SubclassData == val&& ?????????????"Subclass data too large for field"); >>>>>>>>>>>>>>>> ???????????????} >>>>>>>>>>>>>>>> >>>>>>>>>>>>>>>> ???????????????Probably there is another ways to protect NumContainedTys from overwritting? >>>>>>>>>>>>>>>> >>>>>>>>>>>>>>>> ???????????????Please find the patch in attachment for review. >>>>>>>>>>>>>>>> >>>>>>>>>>>>>>>> ???????????????-Stepan. >>>>>>>>>>>>>>>> >>>>>>>>>>>>>>>> ???????????????_______________________________________________ >>>>>>>>>>>>>>>> ???????????????llvm-commits mailing list >>>>>>>>>>>>>>>> ???????????????llvm-commits at cs.uiuc.edu >>>>>>>>>>>>>>>> ???????????????http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits >>>>>>>>>>>>>>> ?????????????_______________________________________________ >>>>>>>>>>>>>>> ?????????????llvm-commits mailing list >>>>>>>>>>>>>>> ?????????????llvm-commits at cs.uiuc.edu >>>>>>>>>>>>>>> ?????????????http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From lhames at gmail.com Tue Jan 3 14:05:57 2012 From: lhames at gmail.com (Lang Hames) Date: Tue, 03 Jan 2012 20:05:57 -0000 Subject: [llvm-commits] [llvm] r147471 - /llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp Message-ID: <20120103200558.0B06B2A6C12C@llvm.org> Author: lhames Date: Tue Jan 3 14:05:57 2012 New Revision: 147471 URL: http://llvm.org/viewvc/llvm-project?rev=147471&view=rev Log: Clarified assert text. Modified: llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp Modified: llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp?rev=147471&r1=147470&r2=147471&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp (original) +++ llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp Tue Jan 3 14:05:57 2012 @@ -646,7 +646,7 @@ SmallVectorImpl *dead) { DEBUG(dbgs() << "Shrink: " << *li << '\n'); assert(TargetRegisterInfo::isVirtualRegister(li->reg) - && "Can't only shrink physical registers"); + && "Can only shrink virtual registers"); // Find all the values used, including PHI kills. SmallVector, 16> WorkList; From resistor at mac.com Tue Jan 3 14:09:02 2012 From: resistor at mac.com (Owen Anderson) Date: Tue, 03 Jan 2012 20:09:02 -0000 Subject: [llvm-commits] [llvm] r147472 - /llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp Message-ID: <20120103200902.AF5E42A6C12C@llvm.org> Author: resistor Date: Tue Jan 3 14:09:02 2012 New Revision: 147472 URL: http://llvm.org/viewvc/llvm-project?rev=147472&view=rev Log: Remove the restriction that target intrinsics can only involve legal types. Targets can perfects well support intrinsics on illegal types, as long as they are prepared to perform custom expansion during type legalization. For example, a target where i64 is illegal might still support the i64 intrinsic operation using pairs of i32's. ARM already does some expansions like this for non-intrinsic operations. Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp?rev=147472&r1=147471&r2=147472&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp Tue Jan 3 14:09:02 2012 @@ -3508,19 +3508,11 @@ // Add all operands of the call to the operand list. for (unsigned i = 0, e = I.getNumArgOperands(); i != e; ++i) { SDValue Op = getValue(I.getArgOperand(i)); - assert(TLI.isTypeLegal(Op.getValueType()) && - "Intrinsic uses a non-legal type?"); Ops.push_back(Op); } SmallVector ValueVTs; ComputeValueVTs(TLI, I.getType(), ValueVTs); -#ifndef NDEBUG - for (unsigned Val = 0, E = ValueVTs.size(); Val != E; ++Val) { - assert(TLI.isTypeLegal(ValueVTs[Val]) && - "Intrinsic uses a non-legal type?"); - } -#endif // NDEBUG if (HasChain) ValueVTs.push_back(MVT::Other); From nicholas at mxc.ca Tue Jan 3 14:33:01 2012 From: nicholas at mxc.ca (Nick Lewycky) Date: Tue, 03 Jan 2012 20:33:01 -0000 Subject: [llvm-commits] [llvm] r147474 - /llvm/trunk/lib/Support/ConstantRange.cpp Message-ID: <20120103203301.1528F2A6C12C@llvm.org> Author: nicholas Date: Tue Jan 3 14:33:00 2012 New Revision: 147474 URL: http://llvm.org/viewvc/llvm-project?rev=147474&view=rev Log: Conform to the style guide; remove 'else' after 'return'. Also remove an extra if-statement by turning it into an assert. No functionality change. Modified: llvm/trunk/lib/Support/ConstantRange.cpp Modified: llvm/trunk/lib/Support/ConstantRange.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Support/ConstantRange.cpp?rev=147474&r1=147473&r2=147474&view=diff ============================================================================== --- llvm/trunk/lib/Support/ConstantRange.cpp (original) +++ llvm/trunk/lib/Support/ConstantRange.cpp Tue Jan 3 14:33:00 2012 @@ -161,8 +161,7 @@ APInt ConstantRange::getUnsignedMax() const { if (isFullSet() || isWrappedSet()) return APInt::getMaxValue(getBitWidth()); - else - return getUpper() - 1; + return getUpper() - 1; } /// getUnsignedMin - Return the smallest unsigned value contained in the @@ -171,8 +170,7 @@ APInt ConstantRange::getUnsignedMin() const { if (isFullSet() || (isWrappedSet() && getUpper() != 0)) return APInt::getMinValue(getBitWidth()); - else - return getLower(); + return getLower(); } /// getSignedMax - Return the largest signed value contained in the @@ -183,14 +181,11 @@ if (!isWrappedSet()) { if (getLower().sle(getUpper() - 1)) return getUpper() - 1; - else - return SignedMax; - } else { - if (getLower().isNegative() == getUpper().isNegative()) - return SignedMax; - else - return getUpper() - 1; + return SignedMax; } + if (getLower().isNegative() == getUpper().isNegative()) + return SignedMax; + return getUpper() - 1; } /// getSignedMin - Return the smallest signed value contained in the @@ -201,18 +196,13 @@ if (!isWrappedSet()) { if (getLower().sle(getUpper() - 1)) return getLower(); - else + return SignedMin; + } + if ((getUpper() - 1).slt(getLower())) { + if (getUpper() != SignedMin) return SignedMin; - } else { - if ((getUpper() - 1).slt(getLower())) { - if (getUpper() != SignedMin) - return SignedMin; - else - return getLower(); - } else { - return getLower(); - } } + return getLower(); } /// contains - Return true if the specified value is in the set. @@ -223,8 +213,7 @@ if (!isWrappedSet()) return Lower.ule(V) && V.ult(Upper); - else - return Lower.ule(V) || V.ult(Upper); + return Lower.ule(V) || V.ult(Upper); } /// contains - Return true if the argument is a subset of this range. @@ -284,15 +273,14 @@ return ConstantRange(CR.Lower, Upper); return CR; - } else { - if (Upper.ult(CR.Upper)) - return *this; + } + if (Upper.ult(CR.Upper)) + return *this; - if (Lower.ult(CR.Upper)) - return ConstantRange(Lower, CR.Upper); + if (Lower.ult(CR.Upper)) + return ConstantRange(Lower, CR.Upper); - return ConstantRange(getBitWidth(), false); - } + return ConstantRange(getBitWidth(), false); } if (isWrappedSet() && !CR.isWrappedSet()) { @@ -305,9 +293,9 @@ if (getSetSize().ult(CR.getSetSize())) return *this; - else - return CR; - } else if (CR.Lower.ult(Lower)) { + return CR; + } + if (CR.Lower.ult(Lower)) { if (CR.Upper.ule(Lower)) return ConstantRange(getBitWidth(), false); @@ -320,15 +308,15 @@ if (CR.Lower.ult(Upper)) { if (getSetSize().ult(CR.getSetSize())) return *this; - else - return CR; + return CR; } if (CR.Lower.ult(Lower)) return ConstantRange(Lower, CR.Upper); return CR; - } else if (CR.Upper.ult(Lower)) { + } + if (CR.Upper.ult(Lower)) { if (CR.Lower.ult(Lower)) return *this; @@ -336,8 +324,7 @@ } if (getSetSize().ult(CR.getSetSize())) return *this; - else - return CR; + return CR; } @@ -362,8 +349,7 @@ APInt d1 = CR.Lower - Upper, d2 = Lower - CR.Upper; if (d1.ult(d2)) return ConstantRange(Lower, CR.Upper); - else - return ConstantRange(CR.Lower, Upper); + return ConstantRange(CR.Lower, Upper); } APInt L = Lower, U = Upper; @@ -396,8 +382,7 @@ APInt d1 = CR.Lower - Upper, d2 = Lower - CR.Upper; if (d1.ult(d2)) return ConstantRange(Lower, CR.Upper); - else - return ConstantRange(CR.Lower, Upper); + return ConstantRange(CR.Lower, Upper); } // ----U L----- : this @@ -407,13 +392,11 @@ // ------U L---- : this // L-----U : CR - if (CR.Lower.ult(Upper) && CR.Upper.ult(Lower)) - return ConstantRange(Lower, CR.Upper); + assert(CR.Lower.ult(Upper) && CR.Upper.ult(Lower) && + "ConstantRange::unionWith missed a case with one range wrapped"); + return ConstantRange(Lower, CR.Upper); } - assert(isWrappedSet() && CR.isWrappedSet() && - "ConstantRange::unionWith missed wrapped union unwrapped case"); - // ------U L---- and ------U L---- : this // -U L----------- and ------------U L : CR if (CR.Lower.ule(Upper) || Lower.ule(CR.Upper)) @@ -479,10 +462,9 @@ unsigned SrcTySize = getBitWidth(); if (SrcTySize > DstTySize) return truncate(DstTySize); - else if (SrcTySize < DstTySize) + if (SrcTySize < DstTySize) return zeroExtend(DstTySize); - else - return *this; + return *this; } /// sextOrTrunc - make this range have the bit width given by \p DstTySize. The @@ -491,10 +473,9 @@ unsigned SrcTySize = getBitWidth(); if (SrcTySize > DstTySize) return truncate(DstTySize); - else if (SrcTySize < DstTySize) + if (SrcTySize < DstTySize) return signExtend(DstTySize); - else - return *this; + return *this; } ConstantRange @@ -673,11 +654,10 @@ } ConstantRange ConstantRange::inverse() const { - if (isFullSet()) { + if (isFullSet()) return ConstantRange(getBitWidth(), /*isFullSet=*/false); - } else if (isEmptySet()) { + if (isEmptySet()) return ConstantRange(getBitWidth(), /*isFullSet=*/true); - } return ConstantRange(Upper, Lower); } From sabre at nondot.org Tue Jan 3 14:37:44 2012 From: sabre at nondot.org (Chris Lattner) Date: Tue, 03 Jan 2012 20:37:44 -0000 Subject: [llvm-commits] [www] r147475 - /www/trunk/devmtg/2011-11/index.html Message-ID: <20120103203744.4805C2A6C12C@llvm.org> Author: lattner Date: Tue Jan 3 14:37:43 2012 New Revision: 147475 URL: http://llvm.org/viewvc/llvm-project?rev=147475&view=rev Log: fini Modified: www/trunk/devmtg/2011-11/index.html Modified: www/trunk/devmtg/2011-11/index.html URL: http://llvm.org/viewvc/llvm-project/www/trunk/devmtg/2011-11/index.html?rev=147475&r1=147474&r2=147475&view=diff ============================================================================== --- www/trunk/devmtg/2011-11/index.html (original) +++ www/trunk/devmtg/2011-11/index.html Tue Jan 3 14:37:43 2012 @@ -43,7 +43,6 @@

    Agenda
    -

    More videos and slides coming soon.

    From sabre at nondot.org Tue Jan 3 14:38:19 2012 From: sabre at nondot.org (Chris Lattner) Date: Tue, 03 Jan 2012 20:38:19 -0000 Subject: [llvm-commits] [www] r147476 - /www/trunk/devmtg/2011-11/index.html Message-ID: <20120103203819.9D0A72A6C12C@llvm.org> Author: lattner Date: Tue Jan 3 14:38:19 2012 New Revision: 147476 URL: http://llvm.org/viewvc/llvm-project?rev=147476&view=rev Log: it's not an agenda anymore. Modified: www/trunk/devmtg/2011-11/index.html Modified: www/trunk/devmtg/2011-11/index.html URL: http://llvm.org/viewvc/llvm-project/www/trunk/devmtg/2011-11/index.html?rev=147476&r1=147475&r2=147476&view=diff ============================================================================== --- www/trunk/devmtg/2011-11/index.html (original) +++ www/trunk/devmtg/2011-11/index.html Tue Jan 3 14:38:19 2012 @@ -4,7 +4,7 @@
    MediaTalk
      -
    1. Agenda
      2. +
    2. Talk Slides and Videos
    3. Talk Abstracts
    4. Poster Abstracts
    @@ -42,7 +42,7 @@

    -
    Agenda
    +
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    From mcrosier at apple.com Tue Jan 3 15:05:52 2012 From: mcrosier at apple.com (Chad Rosier) Date: Tue, 03 Jan 2012 21:05:52 -0000 Subject: [llvm-commits] [llvm] r147481 - in /llvm/trunk: lib/Target/X86/X86ISelLowering.cpp lib/Target/X86/X86InstrSSE.td test/CodeGen/X86/avx-shuffle.ll Message-ID: <20120103210552.B5CF22A6C12C@llvm.org> Author: mcrosier Date: Tue Jan 3 15:05:52 2012 New Revision: 147481 URL: http://llvm.org/viewvc/llvm-project?rev=147481&view=rev Log: Enhance DAGCombine for transforming 128->256 casts into a vmovaps, rather then a vxorps + vinsertf128 pair if the original vector came from a load. rdar://10594409 Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp llvm/trunk/lib/Target/X86/X86InstrSSE.td llvm/trunk/test/CodeGen/X86/avx-shuffle.ll Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=147481&r1=147480&r2=147481&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original) +++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Tue Jan 3 15:05:52 2012 @@ -12731,6 +12731,20 @@ !isUndefOrEqual(SVOp->getMaskElt(i+NumElems/2), NumElems)) return SDValue(); + // If V1 is coming from a vector load then just fold to a VZEXT_LOAD. + if (LoadSDNode *Ld = dyn_cast(V1.getOperand(0))) { + SDVTList Tys = DAG.getVTList(MVT::v4i64, MVT::Other); + SDValue Ops[] = { Ld->getChain(), Ld->getBasePtr() }; + SDValue ResNode = + DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, dl, Tys, Ops, 2, + Ld->getMemoryVT(), + Ld->getPointerInfo(), + Ld->getAlignment(), + false/*isVolatile*/, true/*ReadMem*/, + false/*WriteMem*/); + return DAG.getNode(ISD::BITCAST, dl, VT, ResNode); + } + // Emit a zeroed vector and insert the desired subvector on its // first half. SDValue Zeros = getZeroVector(VT, true /* HasXMMInt */, DAG, dl); Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrSSE.td?rev=147481&r1=147480&r2=147481&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86InstrSSE.td (original) +++ llvm/trunk/lib/Target/X86/X86InstrSSE.td Tue Jan 3 15:05:52 2012 @@ -4719,6 +4719,11 @@ (VMOVZQI2PQIrm addr:$src)>; } +let Predicates = [HasAVX] in { +def : Pat<(v4i64 (X86vzload addr:$src)), + (SUBREG_TO_REG (i32 0), (VMOVAPSrm addr:$src), sub_xmm)>; +} + //===---------------------------------------------------------------------===// // Moving from XMM to XMM and clear upper 64 bits. Note, there is a bug in // IA32 document. movq xmm1, xmm2 does clear the high bits. Modified: llvm/trunk/test/CodeGen/X86/avx-shuffle.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx-shuffle.ll?rev=147481&r1=147480&r2=147481&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/X86/avx-shuffle.ll (original) +++ llvm/trunk/test/CodeGen/X86/avx-shuffle.ll Tue Jan 3 15:05:52 2012 @@ -31,4 +31,27 @@ ret <8 x float> %b ; CHECK: test4: ; CHECK: vinsertf128 +} + +; rdar://10594409 +define <8 x float> @test5(float* nocapture %f) nounwind uwtable readonly ssp { +entry: + %0 = bitcast float* %f to <4 x float>* + %1 = load <4 x float>* %0, align 16 +; CHECK: vmovaps +; CHECK-NOT: vxorps +; CHECK-NOT: vinsertf128 + %shuffle.i = shufflevector <4 x float> %1, <4 x float> , <8 x i32> + ret <8 x float> %shuffle.i +} + +define <4 x double> @test6(double* nocapture %d) nounwind uwtable readonly ssp { +entry: + %0 = bitcast double* %d to <2 x double>* + %1 = load <2 x double>* %0, align 16 +; CHECK: vmovaps +; CHECK-NOT: vxorps +; CHECK-NOT: vinsertf128 + %shuffle.i = shufflevector <2 x double> %1, <2 x double> , <4 x i32> + ret <4 x double> %shuffle.i } \ No newline at end of file From mcrosier at apple.com Tue Jan 3 15:11:37 2012 From: mcrosier at apple.com (Chad Rosier) Date: Tue, 03 Jan 2012 13:11:37 -0800 Subject: [llvm-commits] [PATCH] AVX vmovaps +vxoprs + vinsertf128 DAG combine to vmovaps In-Reply-To: References: <9B9D99A1-48D5-4E4A-A32B-C97F167EFB51@apple.com> Message-ID: Thanks, Bruno. Committed llvm revision 147481 with the suggested changes. Chad On Dec 30, 2011, at 1:07 PM, Bruno Cardoso Lopes wrote: > Hi Chad, > > On Thu, Dec 22, 2011 at 12:12 AM, Chad Rosier wrote: >> This patch is for an AVX specific DAGcombine optimization. >> >> The following code: >> >> __m256 foo(float *f) { >> return _mm256_castps128_ps256 (_mm_load_ps(f)); >> } >> >> generates this assembly: >> >> vmovaps (%rdi), %xmm0 >> vxorps %ymm1, %ymm1, %ymm1 >> vinsertf128 $0, %xmm0, %ymm1, %ymm0 >> >> On AVX enabled processors, the vmovaps will zero the upper bits (255:128) of the corresponding YMM register. Therefore, the vxorps and vinsertf128 instructions are not necessary. >> >> This patch implements a DAG combine that removes the unnecessary vxorps and vinsertf128 instructions. Currently, this is only working as an enhancement to one of Bruno's DAGcombines (r135727), but I do plan on making this more general in the future. > > LGTM, just a few comments: > > + return DAG.getNode(ISD::BITCAST, dl, VT, ResNode); > > Since you're early returning here, > > + } else { > + // Emit a zeroed vector and insert the desired subvector on its > + // first half. > + SDValue Zeros = getZeroVector(VT, true /* HasXMMInt */, DAG, dl); > + SDValue InsV = Insert128BitVector(Zeros, V1.getOperand(0), > + DAG.getConstant(0, MVT::i32), DAG, dl); > + return DCI.CombineTo(N, InsV); > + } > > to follow llvm coding style, you don't need the "else". > > +def X86vzload128 : SDNode<"X86ISD::VZEXT_LOAD128", SDTLoad, > + [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; > > + // VZEXT_LOAD128 - Load vector and zero extend. > + VZEXT_LOAD128, > + > > Why not use the previous X86vzload and VZEXT_LOAD instead? You can you > use it and still match it right by using v4i64 in the pattern. > > > -- > Bruno Cardoso Lopes > http://www.brunocardoso.cc From eli.friedman at gmail.com Tue Jan 3 15:14:54 2012 From: eli.friedman at gmail.com (Eli Friedman) Date: Tue, 3 Jan 2012 13:14:54 -0800 Subject: [llvm-commits] [llvm] r147426 - in /llvm/trunk: lib/Target/X86/X86ISelLowering.cpp test/CodeGen/X86/2011-12-28-vselecti8.ll test/CodeGen/X86/sext-blend.ll test/CodeGen/X86/sse2-blend.ll test/CodeGen/X86/sse41-blend.ll In-Reply-To: <20120102080547.693982A6C12C@llvm.org> References: <20120102080547.693982A6C12C@llvm.org> Message-ID: On Mon, Jan 2, 2012 at 12:05 AM, Nadav Rotem wrote: > Author: nadav > Date: Mon Jan ?2 02:05:46 2012 > New Revision: 147426 > > URL: http://llvm.org/viewvc/llvm-project?rev=147426&view=rev > Log: > > Optimize the sequence blend(sign_extend(x)) to blend(shl(x)) since SSE blend instructions only look at the highest bit. This patch is causing http://llvm.org/bugs/show_bug.cgi?id=11696 ; please revert. -Eli > Added: > ? ?llvm/trunk/test/CodeGen/X86/sext-blend.ll > Modified: > ? ?llvm/trunk/lib/Target/X86/X86ISelLowering.cpp > ? ?llvm/trunk/test/CodeGen/X86/2011-12-28-vselecti8.ll > ? ?llvm/trunk/test/CodeGen/X86/sse2-blend.ll > ? ?llvm/trunk/test/CodeGen/X86/sse41-blend.ll > > Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=147426&r1=147425&r2=147426&view=diff > ============================================================================== > --- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original) > +++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Mon Jan ?2 02:05:46 2012 > @@ -13133,6 +13133,24 @@ > ? ? ? } > ? } > > + ?// The VSELECT instruction is lowered to SSE blend instructions. In many cases > + ?// the mask is sign-extended to fill the entire lane. However, we only care > + ?// for the highest bit. Convert sign_extend to srl because it is cheaper. > + ?// (vselect(sign_extend(x))) -> ?vselect(srl(x)) > + ?if (N->getOpcode() == ISD::VSELECT && > + ? ? ?Cond.getOpcode() == ISD::SIGN_EXTEND_INREG && Cond.hasOneUse()) { > + ? ?EVT CondVT = Cond.getValueType(); > + ? ?EVT SExtTy = cast(Cond.getOperand(1))->getVT(); > + ? ?unsigned BitsDiff = CondVT.getScalarType().getSizeInBits() - > + ? ? ? ? ? ? ? ? ? ? ? ?SExtTy.getScalarType().getSizeInBits(); > + > + ? ?EVT ShiftType = EVT::getVectorVT(*DAG.getContext(), > + ? ? ? ? ? ? ? ?MVT::i32, CondVT.getVectorNumElements()); > + ? ?SDValue SHL = DAG.getNode(ISD::SHL, DL, CondVT, Cond.getOperand(0), > + ? ? ? ? ? ? ? ?DAG.getConstant(BitsDiff, ShiftType)); > + ? ?return DAG.getNode(ISD::VSELECT, DL, VT, SHL, LHS, RHS); > + ?} > + > ? return SDValue(); > ?} > > > Modified: llvm/trunk/test/CodeGen/X86/2011-12-28-vselecti8.ll > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2011-12-28-vselecti8.ll?rev=147426&r1=147425&r2=147426&view=diff > ============================================================================== > --- llvm/trunk/test/CodeGen/X86/2011-12-28-vselecti8.ll (original) > +++ llvm/trunk/test/CodeGen/X86/2011-12-28-vselecti8.ll Mon Jan ?2 02:05:46 2012 > @@ -5,8 +5,10 @@ > > ?; CHECK: @foo8 > ?; CHECK: psll > -; CHECK: psraw > -; CHECK: pblendvb > +; CHECK-NOT: sra > +; CHECK: pandn > +; CHECK: pand > +; CHECK: or > ?; CHECK: ret > ?define void @foo8(float* nocapture %RET) nounwind { > ?allocas: > > Added: llvm/trunk/test/CodeGen/X86/sext-blend.ll > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/sext-blend.ll?rev=147426&view=auto > ============================================================================== > --- llvm/trunk/test/CodeGen/X86/sext-blend.ll (added) > +++ llvm/trunk/test/CodeGen/X86/sext-blend.ll Mon Jan ?2 02:05:46 2012 > @@ -0,0 +1,15 @@ > +; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=corei7 -promote-elements -mattr=+sse41 | FileCheck %s > + > +; CHECK: foo > +define <4 x double> @foo(<4 x double> %x, <4 x double> %y) { > + ?; CHECK: cmpnlepd > + ?; CHECK: psllq > + ?; CHECK-NEXT: blendvpd > + ?; CHECK: psllq > + ?; CHECK-NEXT: blendvpd > + ?; CHECK: ret > + ?%min_is_x = fcmp ult <4 x double> %x, %y > + ?%min = select <4 x i1> %min_is_x, <4 x double> %x, <4 x double> %y > + ?ret <4 x double> %min > +} > + > > Modified: llvm/trunk/test/CodeGen/X86/sse2-blend.ll > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/sse2-blend.ll?rev=147426&r1=147425&r2=147426&view=diff > ============================================================================== > --- llvm/trunk/test/CodeGen/X86/sse2-blend.ll (original) > +++ llvm/trunk/test/CodeGen/X86/sse2-blend.ll Mon Jan ?2 02:05:46 2012 > @@ -28,10 +28,10 @@ > > ?; Without forcing instructions, fall back to the preferred PS domain. > ?; CHECK: vsel_i64 > -; CHECK: xorps > -; CHECK: andps > -; CHECK: andnps > -; CHECK: orps > +; CHECK: pxor > +; CHECK: and > +; CHECK: andn > +; CHECK: or > ?; CHECK: ret > > ?define void at vsel_i64(<4 x i64>* %v1, <4 x i64>* %v2) { > @@ -44,10 +44,10 @@ > > ?; Without forcing instructions, fall back to the preferred PS domain. > ?; CHECK: vsel_double > -; CHECK: xorps > -; CHECK: andps > -; CHECK: andnps > -; CHECK: orps > +; CHECK: xor > +; CHECK: and > +; CHECK: andn > +; CHECK: or > ?; CHECK: ret > > ?define void at vsel_double(<4 x double>* %v1, <4 x double>* %v2) { > > Modified: llvm/trunk/test/CodeGen/X86/sse41-blend.ll > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/sse41-blend.ll?rev=147426&r1=147425&r2=147426&view=diff > ============================================================================== > --- llvm/trunk/test/CodeGen/X86/sse41-blend.ll (original) > +++ llvm/trunk/test/CodeGen/X86/sse41-blend.ll Mon Jan ?2 02:05:46 2012 > @@ -36,6 +36,7 @@ > > > ?;CHECK: vsel_double > +;CHECK-NOT: sra > ?;CHECK: blendvpd > ?;CHECK: ret > ?define <4 x double> @vsel_double(<4 x double> %v1, <4 x double> %v2) { > @@ -54,6 +55,7 @@ > > > ?;CHECK: vsel_i8 > +;CHECK-NOT: sra > ?;CHECK: pblendvb > ?;CHECK: ret > ?define <16 x i8> @vsel_i8(<16 x i8> %v1, <16 x i8> %v2) { > @@ -65,6 +67,7 @@ > ?; CHECK: A > ?define <2 x double> @A(<2 x double> %x, <2 x double> %y) { > ? ; CHECK: cmplepd > + ?; CHECK-NOT: sra > ? ; CHECK: blendvpd > ? %max_is_x = fcmp oge <2 x double> %x, %y > ? %max = select <2 x i1> %max_is_x, <2 x double> %x, <2 x double> %y > @@ -74,6 +77,7 @@ > ?; CHECK: B > ?define <2 x double> @B(<2 x double> %x, <2 x double> %y) { > ? ; CHECK: cmpnlepd > + ?; CHECK-NOT: sra > ? ; CHECK: blendvpd > ? %min_is_x = fcmp ult <2 x double> %x, %y > ? %min = select <2 x i1> %min_is_x, <2 x double> %x, <2 x double> %y > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From craig.topper at gmail.com Tue Jan 3 15:23:01 2012 From: craig.topper at gmail.com (Craig Topper) Date: Tue, 3 Jan 2012 13:23:01 -0800 Subject: [llvm-commits] XOP Intrinsics patch In-Reply-To: <1325620848.29233.YahooMailNeo@web161506.mail.bf1.yahoo.com> References: <1325607159.50862.YahooMailNeo@web161503.mail.bf1.yahoo.com> <1325620848.29233.YahooMailNeo@web161506.mail.bf1.yahoo.com> Message-ID: On Tue, Jan 3, 2012 at 12:00 PM, Jan Sjodin wrote: > >All integer vector loads in patterns need to be memopv2i64(!28-bit) or > memopv4i64(256-bit) and bitcasted to the correct type because all integer > vector loads are promoted to v2i64 or v4i64. So for instance > > > > >+def : Pat<(int_x86_xop_vphsubwd (alignedloadv8i16 addr:$src1)), > >+ (VPHSUBWDrm addr:$src1)>; > > > >Needs to be > > > >+def : Pat<(int_x86_xop_vphsubwd (bc_v8i16 (memopv2i64 addr:$src1))), > >+ (VPHSUBWDrm addr:$src1)>; > > > > If the promotion always happens, maybe it would be best to remove patterns > like: > > def memopv8i16 : PatFrag<(ops node:$ptr), (v8i16 (memop node:$ptr))>; > def memopv16i8 : PatFrag<(ops node:$ptr), (v16i8 (memop node:$ptr))>; > > > - Jan > > I had meant to do that after I was sure they were all gone. I'll try to check on that tonight and see if they can be removed now. -- ~Craig -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20120103/6c85f878/attachment.html From clattner at apple.com Tue Jan 3 15:28:49 2012 From: clattner at apple.com (Chris Lattner) Date: Tue, 03 Jan 2012 13:28:49 -0800 Subject: [llvm-commits] [llvm] r147431 - in /llvm/trunk/unittests: Bitcode/ Bitcode/BitReaderTest.cpp Bitcode/Makefile CMakeLists.txt Makefile VMCore/Makefile VMCore/pr11677.cpp In-Reply-To: <20120102091948.9C2891BE003@llvm.org> References: <20120102091948.9C2891BE003@llvm.org> Message-ID: <1F59E691-F155-4C99-9E6F-F68F3D5EE070@apple.com> On Jan 2, 2012, at 1:19 AM, Chandler Carruth wrote: > Author: chandlerc > Date: Mon Jan 2 03:19:48 2012 > New Revision: 147431 > > URL: http://llvm.org/viewvc/llvm-project?rev=147431&view=rev > Log: > Undo the hack in r147427 and move this unittest to a better home. This > is testing the bitcode reader's functionality, not VMCore's. Add the > what is a hope sufficient build system mojo to build and run a new > unittest. > > Also clean up some of the test's naming. The goal for the file should be > to unittest the Bitcode Reader, and this is just one particular test > among potentially many in the future. Also, reverse my position and > relegate the PR# to a comment, but stash the comment on the same line as > the test name so it doesn't get lost. This makes the code more > self-documenting hopefully w/o losing track of the PR number. Ugh. Why is this worth having a unit test for? Is the pain/benefit ratio here actually in favor of having the test? -Chris From clattner at apple.com Tue Jan 3 15:33:56 2012 From: clattner at apple.com (Chris Lattner) Date: Tue, 03 Jan 2012 13:33:56 -0800 Subject: [llvm-commits] [llvm] r147426 - in /llvm/trunk: lib/Target/X86/X86ISelLowering.cpp test/CodeGen/X86/2011-12-28-vselecti8.ll test/CodeGen/X86/sext-blend.ll test/CodeGen/X86/sse2-blend.ll test/CodeGen/X86/sse41-blend.ll In-Reply-To: <20120102080547.693982A6C12C@llvm.org> References: <20120102080547.693982A6C12C@llvm.org> Message-ID: On Jan 2, 2012, at 12:05 AM, Nadav Rotem wrote: > Author: nadav > Date: Mon Jan 2 02:05:46 2012 > New Revision: 147426 > > URL: http://llvm.org/viewvc/llvm-project?rev=147426&view=rev > Log: > > Optimize the sequence blend(sign_extend(x)) to blend(shl(x)) since SSE blend instructions only look at the highest bit. Hi Nadav, This could be more implemented in InstCombiner::SimplifyDemandedVectorElts in a much more general way. Knowing that blend only demands the top bit can enable many other optimizations. -Chris From clattner at apple.com Tue Jan 3 15:51:15 2012 From: clattner at apple.com (Chris Lattner) Date: Tue, 03 Jan 2012 13:51:15 -0800 Subject: [llvm-commits] [llvm] r147426 - in /llvm/trunk: lib/Target/X86/X86ISelLowering.cpp test/CodeGen/X86/2011-12-28-vselecti8.ll test/CodeGen/X86/sext-blend.ll test/CodeGen/X86/sse2-blend.ll test/CodeGen/X86/sse41-blend.ll In-Reply-To: References: <20120102080547.693982A6C12C@llvm.org> Message-ID: <53D63537-B084-465C-8F14-02FF074A6BF9@apple.com> On Jan 3, 2012, at 1:33 PM, Chris Lattner wrote: > > On Jan 2, 2012, at 12:05 AM, Nadav Rotem wrote: > >> Author: nadav >> Date: Mon Jan 2 02:05:46 2012 >> New Revision: 147426 >> >> URL: http://llvm.org/viewvc/llvm-project?rev=147426&view=rev >> Log: >> >> Optimize the sequence blend(sign_extend(x)) to blend(shl(x)) since SSE blend instructions only look at the highest bit. > > Hi Nadav, > > This could be more implemented in InstCombiner::SimplifyDemandedVectorElts in a much more general way. Knowing that blend only demands the top bit can enable many other optimizations. Oh, a correction. Since blend is elementwise, it should actually go in SimplifyDemandedBits. SimplifyDemandedVectorElts is for cases where only some elements are demanded (like the SS operations). -Chris From chandlerc at gmail.com Tue Jan 3 15:55:43 2012 From: chandlerc at gmail.com (Chandler Carruth) Date: Tue, 3 Jan 2012 13:55:43 -0800 Subject: [llvm-commits] [llvm] r147431 - in /llvm/trunk/unittests: Bitcode/ Bitcode/BitReaderTest.cpp Bitcode/Makefile CMakeLists.txt Makefile VMCore/Makefile VMCore/pr11677.cpp In-Reply-To: <1F59E691-F155-4C99-9E6F-F68F3D5EE070@apple.com> References: <20120102091948.9C2891BE003@llvm.org> <1F59E691-F155-4C99-9E6F-F68F3D5EE070@apple.com> Message-ID: On Tue, Jan 3, 2012 at 1:28 PM, Chris Lattner wrote: > > On Jan 2, 2012, at 1:19 AM, Chandler Carruth wrote: > > > Author: chandlerc > > Date: Mon Jan 2 03:19:48 2012 > > New Revision: 147431 > > > > URL: http://llvm.org/viewvc/llvm-project?rev=147431&view=rev > > Log: > > Undo the hack in r147427 and move this unittest to a better home. This > > is testing the bitcode reader's functionality, not VMCore's. Add the > > what is a hope sufficient build system mojo to build and run a new > > unittest. > > > > Also clean up some of the test's naming. The goal for the file should be > > to unittest the Bitcode Reader, and this is just one particular test > > among potentially many in the future. Also, reverse my position and > > relegate the PR# to a comment, but stash the comment on the same line as > > the test name so it doesn't get lost. This makes the code more > > self-documenting hopefully w/o losing track of the PR number. > > Ugh. Why is this worth having a unit test for? Is the pain/benefit ratio > here actually in favor of having the test? > What pain are you feeling from this unit test? That the code to implement the unit test is ugly? I certainly don't like that part of it... I think this is still worth having because this wasn't just a new unit test, this was a regression test for a bug we actually hit during LTO. It seems reasonable to want to test that we don't re-introduce the bug. However, I also think that writing tests like this could be *much* cleaner and simpler in order to reduce the pain of adding and maintaining them. I was hoping to wait for test #2 or #3 before investing in that infrastructure, but I can do it sooner if you'd just like to see what it would look like. I've been thinking about it a while and have some ideas of what I would really like tests of this nature to look like... -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20120103/c9728f50/attachment-0001.html From clattner at apple.com Tue Jan 3 15:58:37 2012 From: clattner at apple.com (Chris Lattner) Date: Tue, 03 Jan 2012 13:58:37 -0800 Subject: [llvm-commits] [llvm] r147431 - in /llvm/trunk/unittests: Bitcode/ Bitcode/BitReaderTest.cpp Bitcode/Makefile CMakeLists.txt Makefile VMCore/Makefile VMCore/pr11677.cpp In-Reply-To: References: <20120102091948.9C2891BE003@llvm.org> <1F59E691-F155-4C99-9E6F-F68F3D5EE070@apple.com> Message-ID: On Jan 3, 2012, at 1:55 PM, Chandler Carruth wrote: > > Also clean up some of the test's naming. The goal for the file should be > > to unittest the Bitcode Reader, and this is just one particular test > > among potentially many in the future. Also, reverse my position and > > relegate the PR# to a comment, but stash the comment on the same line as > > the test name so it doesn't get lost. This makes the code more > > self-documenting hopefully w/o losing track of the PR number. > > Ugh. Why is this worth having a unit test for? Is the pain/benefit ratio here actually in favor of having the test? > > What pain are you feeling from this unit test? That the code to implement the unit test is ugly? I certainly don't like that part of it? The fact that a 2 line patch has a testcase that is an order of magnitude larger than it, requires another unit test to be linked (slowing down builds), the fact that Rafael had to waste his (presumably valuable ;-) time writing it, etc. This seems like a complete waste of time. > I think this is still worth having because this wasn't just a new unit test, this was a regression test for a bug we actually hit during LTO. It seems reasonable to want to test that we don't re-introduce the bug. Why not write this as an LTO test in llvm/test/Linker then? > However, I also think that writing tests like this could be *much* cleaner and simpler in order to reduce the pain of adding and maintaining them. I was hoping to wait for test #2 or #3 before investing in that infrastructure, but I can do it sooner if you'd just like to see what it would look like. I've been thinking about it a while and have some ideas of what I would really like tests of this nature to look like... Why not just use the proper infrastructure we already have for this, instead of pushing unit tests? -Chris -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20120103/967c1f1c/attachment.html From nadav.rotem at intel.com Tue Jan 3 16:12:28 2012 From: nadav.rotem at intel.com (Nadav Rotem) Date: Tue, 03 Jan 2012 22:12:28 -0000 Subject: [llvm-commits] [llvm] r147484 - in /llvm/trunk: lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp test/CodeGen/X86/promote.ll Message-ID: <20120103221228.DD7752A6C12C@llvm.org> Author: nadav Date: Tue Jan 3 16:12:28 2012 New Revision: 147484 URL: http://llvm.org/viewvc/llvm-project?rev=147484&view=rev Log: Fix incorrect widening of the bitcast sdnode in case the incoming operand is integer-promoted. Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp llvm/trunk/test/CodeGen/X86/promote.ll Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp?rev=147484&r1=147483&r2=147484&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp Tue Jan 3 16:12:28 2012 @@ -1571,6 +1571,12 @@ case TargetLowering::TypeLegal: break; case TargetLowering::TypePromoteInteger: + // If the incoming type is a vector that is being promoted, then + // we know that the elements are arranged differently and that we + // must perform the conversion using a stack slot. + if (InVT.isVector()) + break; + // If the InOp is promoted to the same size, convert it. Otherwise, // fall out of the switch and widen the promoted input. InOp = GetPromotedInteger(InOp); Modified: llvm/trunk/test/CodeGen/X86/promote.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/promote.ll?rev=147484&r1=147483&r2=147484&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/X86/promote.ll (original) +++ llvm/trunk/test/CodeGen/X86/promote.ll Tue Jan 3 16:12:28 2012 @@ -29,3 +29,14 @@ ret i32 0 ; CHECK: ret } + +; CHECK: bitcast_widen +define <2 x float> @bitcast_widen(<4 x i32> %in) nounwind readnone { +entry: +; CHECK-NOT: pshufd + %x = shufflevector <4 x i32> %in, <4 x i32> undef, <2 x i32> + %y = bitcast <2 x i32> %x to <2 x float> + ret <2 x float> %y +; CHECK: ret +} + From nadav.rotem at intel.com Tue Jan 3 16:19:43 2012 From: nadav.rotem at intel.com (Nadav Rotem) Date: Tue, 03 Jan 2012 22:19:43 -0000 Subject: [llvm-commits] [llvm] r147485 - in /llvm/trunk: lib/Target/X86/X86ISelLowering.cpp test/CodeGen/X86/2011-12-28-vselecti8.ll test/CodeGen/X86/sext-blend.ll test/CodeGen/X86/sse2-blend.ll test/CodeGen/X86/sse41-blend.ll Message-ID: <20120103221943.2E1E82A6C12C@llvm.org> Author: nadav Date: Tue Jan 3 16:19:42 2012 New Revision: 147485 URL: http://llvm.org/viewvc/llvm-project?rev=147485&view=rev Log: Revert 147426 because it caused pr11696. Removed: llvm/trunk/test/CodeGen/X86/sext-blend.ll Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp llvm/trunk/test/CodeGen/X86/2011-12-28-vselecti8.ll llvm/trunk/test/CodeGen/X86/sse2-blend.ll llvm/trunk/test/CodeGen/X86/sse41-blend.ll Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=147485&r1=147484&r2=147485&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original) +++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Tue Jan 3 16:19:42 2012 @@ -13139,24 +13139,6 @@ } } - // The VSELECT instruction is lowered to SSE blend instructions. In many cases - // the mask is sign-extended to fill the entire lane. However, we only care - // for the highest bit. Convert sign_extend to srl because it is cheaper. - // (vselect(sign_extend(x))) -> vselect(srl(x)) - if (N->getOpcode() == ISD::VSELECT && - Cond.getOpcode() == ISD::SIGN_EXTEND_INREG && Cond.hasOneUse()) { - EVT CondVT = Cond.getValueType(); - EVT SExtTy = cast(Cond.getOperand(1))->getVT(); - unsigned BitsDiff = CondVT.getScalarType().getSizeInBits() - - SExtTy.getScalarType().getSizeInBits(); - - EVT ShiftType = EVT::getVectorVT(*DAG.getContext(), - MVT::i32, CondVT.getVectorNumElements()); - SDValue SHL = DAG.getNode(ISD::SHL, DL, CondVT, Cond.getOperand(0), - DAG.getConstant(BitsDiff, ShiftType)); - return DAG.getNode(ISD::VSELECT, DL, VT, SHL, LHS, RHS); - } - return SDValue(); } Modified: llvm/trunk/test/CodeGen/X86/2011-12-28-vselecti8.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2011-12-28-vselecti8.ll?rev=147485&r1=147484&r2=147485&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/X86/2011-12-28-vselecti8.ll (original) +++ llvm/trunk/test/CodeGen/X86/2011-12-28-vselecti8.ll Tue Jan 3 16:19:42 2012 @@ -5,10 +5,8 @@ ; CHECK: @foo8 ; CHECK: psll -; CHECK-NOT: sra -; CHECK: pandn -; CHECK: pand -; CHECK: or +; CHECK: psraw +; CHECK: pblendvb ; CHECK: ret define void @foo8(float* nocapture %RET) nounwind { allocas: Removed: llvm/trunk/test/CodeGen/X86/sext-blend.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/sext-blend.ll?rev=147484&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/X86/sext-blend.ll (original) +++ llvm/trunk/test/CodeGen/X86/sext-blend.ll (removed) @@ -1,15 +0,0 @@ -; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=corei7 -promote-elements -mattr=+sse41 | FileCheck %s - -; CHECK: foo -define <4 x double> @foo(<4 x double> %x, <4 x double> %y) { - ; CHECK: cmpnlepd - ; CHECK: psllq - ; CHECK-NEXT: blendvpd - ; CHECK: psllq - ; CHECK-NEXT: blendvpd - ; CHECK: ret - %min_is_x = fcmp ult <4 x double> %x, %y - %min = select <4 x i1> %min_is_x, <4 x double> %x, <4 x double> %y - ret <4 x double> %min -} - Modified: llvm/trunk/test/CodeGen/X86/sse2-blend.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/sse2-blend.ll?rev=147485&r1=147484&r2=147485&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/X86/sse2-blend.ll (original) +++ llvm/trunk/test/CodeGen/X86/sse2-blend.ll Tue Jan 3 16:19:42 2012 @@ -28,10 +28,10 @@ ; Without forcing instructions, fall back to the preferred PS domain. ; CHECK: vsel_i64 -; CHECK: pxor -; CHECK: and -; CHECK: andn -; CHECK: or +; CHECK: xorps +; CHECK: andps +; CHECK: andnps +; CHECK: orps ; CHECK: ret define void at vsel_i64(<4 x i64>* %v1, <4 x i64>* %v2) { @@ -44,10 +44,10 @@ ; Without forcing instructions, fall back to the preferred PS domain. ; CHECK: vsel_double -; CHECK: xor -; CHECK: and -; CHECK: andn -; CHECK: or +; CHECK: xorps +; CHECK: andps +; CHECK: andnps +; CHECK: orps ; CHECK: ret define void at vsel_double(<4 x double>* %v1, <4 x double>* %v2) { Modified: llvm/trunk/test/CodeGen/X86/sse41-blend.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/sse41-blend.ll?rev=147485&r1=147484&r2=147485&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/X86/sse41-blend.ll (original) +++ llvm/trunk/test/CodeGen/X86/sse41-blend.ll Tue Jan 3 16:19:42 2012 @@ -36,7 +36,6 @@ ;CHECK: vsel_double -;CHECK-NOT: sra ;CHECK: blendvpd ;CHECK: ret define <4 x double> @vsel_double(<4 x double> %v1, <4 x double> %v2) { @@ -55,7 +54,6 @@ ;CHECK: vsel_i8 -;CHECK-NOT: sra ;CHECK: pblendvb ;CHECK: ret define <16 x i8> @vsel_i8(<16 x i8> %v1, <16 x i8> %v2) { @@ -67,7 +65,6 @@ ; CHECK: A define <2 x double> @A(<2 x double> %x, <2 x double> %y) { ; CHECK: cmplepd - ; CHECK-NOT: sra ; CHECK: blendvpd %max_is_x = fcmp oge <2 x double> %x, %y %max = select <2 x i1> %max_is_x, <2 x double> %x, <2 x double> %y @@ -77,7 +74,6 @@ ; CHECK: B define <2 x double> @B(<2 x double> %x, <2 x double> %y) { ; CHECK: cmpnlepd - ; CHECK-NOT: sra ; CHECK: blendvpd %min_is_x = fcmp ult <2 x double> %x, %y %min = select <2 x i1> %min_is_x, <2 x double> %x, <2 x double> %y From chandlerc at gmail.com Tue Jan 3 16:34:09 2012 From: chandlerc at gmail.com (Chandler Carruth) Date: Tue, 3 Jan 2012 14:34:09 -0800 Subject: [llvm-commits] [llvm] r147431 - in /llvm/trunk/unittests: Bitcode/ Bitcode/BitReaderTest.cpp Bitcode/Makefile CMakeLists.txt Makefile VMCore/Makefile VMCore/pr11677.cpp In-Reply-To: References: <20120102091948.9C2891BE003@llvm.org> <1F59E691-F155-4C99-9E6F-F68F3D5EE070@apple.com> Message-ID: On Tue, Jan 3, 2012 at 1:58 PM, Chris Lattner wrote: > Why not write this as an LTO test in llvm/test/Linker then? > ... > Why not just use the proper infrastructure we already have for this, > instead of pushing unit tests? > Ah, for this you would have to ask Rafael. I assumed (perhaps erroneously) that the existing infrastructure couldn't test this particular behavior, and that a unit test (and its accompanying infrastructure) was being added specifically to enable testing bugs of that nature. If the existing LTO tests can exercise the code, awesome. -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20120103/58c8f778/attachment.html From stoklund at 2pi.dk Tue Jan 3 16:34:31 2012 From: stoklund at 2pi.dk (Jakob Stoklund Olesen) Date: Tue, 03 Jan 2012 22:34:31 -0000 Subject: [llvm-commits] [llvm] r147486 - /llvm/trunk/lib/CodeGen/VirtRegMap.cpp Message-ID: <20120103223431.728402A6C12C@llvm.org> Author: stoklund Date: Tue Jan 3 16:34:31 2012 New Revision: 147486 URL: http://llvm.org/viewvc/llvm-project?rev=147486&view=rev Log: Assert when reserved registers have been assigned. This can only happen if the set of reserved registers changes during register allocation. Modified: llvm/trunk/lib/CodeGen/VirtRegMap.cpp Modified: llvm/trunk/lib/CodeGen/VirtRegMap.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/VirtRegMap.cpp?rev=147486&r1=147485&r2=147486&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/VirtRegMap.cpp (original) +++ llvm/trunk/lib/CodeGen/VirtRegMap.cpp Tue Jan 3 16:34:31 2012 @@ -112,6 +112,9 @@ SmallVector SuperDeads; SmallVector SuperDefs; SmallVector SuperKills; +#ifndef NDEBUG + BitVector Reserved = TRI->getReservedRegs(*MF); +#endif for (MachineFunction::iterator MBBI = MF->begin(), MBBE = MF->end(); MBBI != MBBE; ++MBBI) { @@ -129,6 +132,7 @@ unsigned VirtReg = MO.getReg(); unsigned PhysReg = getPhys(VirtReg); assert(PhysReg != NO_PHYS_REG && "Instruction uses unmapped VirtReg"); + assert(!Reserved.test(PhysReg) && "Reserved register assignment"); // Preserve semantics of sub-register operands. if (MO.getSubReg()) { From stoklund at 2pi.dk Tue Jan 3 16:34:36 2012 From: stoklund at 2pi.dk (Jakob Stoklund Olesen) Date: Tue, 03 Jan 2012 22:34:36 -0000 Subject: [llvm-commits] [llvm] r147487 - in /llvm/trunk: lib/Target/ARM/ARMBaseInstrInfo.cpp lib/Target/ARM/ARMBaseRegisterInfo.cpp test/CodeGen/ARM/fast-isel-deadcode.ll test/CodeGen/Thumb2/aligned-spill.ll Message-ID: <20120103223436.47CFF2A6C12C@llvm.org> Author: stoklund Date: Tue Jan 3 16:34:35 2012 New Revision: 147487 URL: http://llvm.org/viewvc/llvm-project?rev=147487&view=rev Log: Revert r146997, "Heed spill slot alignment on ARM." This patch caused a miscompilation of oggenc because a frame pointer was suddenly needed halfway through register allocation. Modified: llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp llvm/trunk/test/CodeGen/ARM/fast-isel-deadcode.ll llvm/trunk/test/CodeGen/Thumb2/aligned-spill.ll Modified: llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp?rev=147487&r1=147486&r2=147487&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp Tue Jan 3 16:34:35 2012 @@ -765,8 +765,7 @@ break; case 16: if (ARM::QPRRegClass.hasSubClassEq(RC)) { - // Use aligned spills if the stack can be realigned. - if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) { + if (Align >= 16 && getRegisterInfo().needsStackRealignment(MF)) { AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VST1q64Pseudo)) .addFrameIndex(FI).addImm(16) .addReg(SrcReg, getKillRegState(isKill)) @@ -915,7 +914,7 @@ break; case 16: if (ARM::QPRRegClass.hasSubClassEq(RC)) { - if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) { + if (Align >= 16 && getRegisterInfo().needsStackRealignment(MF)) { AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLD1q64Pseudo), DestReg) .addFrameIndex(FI).addImm(16) .addMemOperand(MMO)); Modified: llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp?rev=147487&r1=147486&r2=147487&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp Tue Jan 3 16:34:35 2012 @@ -542,7 +542,7 @@ const MachineFrameInfo *MFI = MF.getFrameInfo(); const Function *F = MF.getFunction(); unsigned StackAlign = MF.getTarget().getFrameLowering()->getStackAlignment(); - bool requiresRealignment = ((MFI->getMaxAlignment() > StackAlign) || + bool requiresRealignment = ((MFI->getLocalFrameMaxAlign() > StackAlign) || F->hasFnAttr(Attribute::StackAlignment)); return requiresRealignment && canRealignStack(MF); Modified: llvm/trunk/test/CodeGen/ARM/fast-isel-deadcode.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/fast-isel-deadcode.ll?rev=147487&r1=147486&r2=147487&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/ARM/fast-isel-deadcode.ll (original) +++ llvm/trunk/test/CodeGen/ARM/fast-isel-deadcode.ll Tue Jan 3 16:34:35 2012 @@ -15,7 +15,8 @@ ; THUMB-NOT: sxtb ; THUMB: movs r0, #0 ; THUMB: movt r0, #0 -; THUMB: pop +; THUMB: add sp, #32 +; THUMb: pop {r7, pc} ret i32 0 } Modified: llvm/trunk/test/CodeGen/Thumb2/aligned-spill.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb2/aligned-spill.ll?rev=147487&r1=147486&r2=147487&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/Thumb2/aligned-spill.ll (original) +++ llvm/trunk/test/CodeGen/Thumb2/aligned-spill.ll Tue Jan 3 16:34:35 2012 @@ -1,4 +1,4 @@ -; RUN: llc < %s -mcpu=cortex-a8 | FileCheck %s +; DONT: llc < %s -mcpu=cortex-a8 | FileCheck %s ; RUN: llc < %s -mcpu=cortex-a8 -align-neon-spills | FileCheck %s --check-prefix=NEON target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:32:64-v128:32:128-a0:0:32-n32-S32" target triple = "thumbv7-apple-ios" From stoklund at 2pi.dk Tue Jan 3 17:04:28 2012 From: stoklund at 2pi.dk (Jakob Stoklund Olesen) Date: Tue, 03 Jan 2012 23:04:28 -0000 Subject: [llvm-commits] [llvm] r147491 - /llvm/trunk/utils/TableGen/SubtargetEmitter.cpp Message-ID: <20120103230428.EC1A82A6C12C@llvm.org> Author: stoklund Date: Tue Jan 3 17:04:28 2012 New Revision: 147491 URL: http://llvm.org/viewvc/llvm-project?rev=147491&view=rev Log: Don't use enums larger than 1 << 31 for target features. Patch by Andy Zhang! Modified: llvm/trunk/utils/TableGen/SubtargetEmitter.cpp Modified: llvm/trunk/utils/TableGen/SubtargetEmitter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/SubtargetEmitter.cpp?rev=147491&r1=147490&r2=147491&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/SubtargetEmitter.cpp (original) +++ llvm/trunk/utils/TableGen/SubtargetEmitter.cpp Tue Jan 3 17:04:28 2012 @@ -39,28 +39,41 @@ OS << "namespace " << Target << " {\n"; - // Open enumeration - OS << "enum {\n"; + // For bit flag enumerations with more than 32 items, emit constants. + // Emit an enum for everything else. + if (isBits && N > 32) { + // For each record + for (unsigned i = 0; i < N; i++) { + // Next record + Record *Def = DefList[i]; - // For each record - for (unsigned i = 0; i < N;) { - // Next record - Record *Def = DefList[i]; + // Get and emit name and expression (1 << i) + OS << " const uint64_t " << Def->getName() << " = 1ULL << " << i << ";\n"; + } + } else { + // Open enumeration + OS << "enum {\n"; - // Get and emit name - OS << " " << Def->getName(); + // For each record + for (unsigned i = 0; i < N;) { + // Next record + Record *Def = DefList[i]; - // If bit flags then emit expression (1 << i) - if (isBits) OS << " = " << " 1ULL << " << i; + // Get and emit name + OS << " " << Def->getName(); - // Depending on 'if more in the list' emit comma - if (++i < N) OS << ","; + // If bit flags then emit expression (1 << i) + if (isBits) OS << " = " << " 1ULL << " << i; - OS << "\n"; - } + // Depending on 'if more in the list' emit comma + if (++i < N) OS << ","; - // Close enumeration - OS << "};\n"; + OS << "\n"; + } + + // Close enumeration + OS << "};\n"; + } OS << "}\n"; } From stoklund at 2pi.dk Tue Jan 3 17:08:28 2012 From: stoklund at 2pi.dk (Jakob Stoklund Olesen) Date: Tue, 03 Jan 2012 15:08:28 -0800 Subject: [llvm-commits] [PATCH] Modify tablegen to use constants when there are more than 32 subtarget features In-Reply-To: <5C9B2DB6AAFD914E864AF9803780B66A94FA@FMSMSX108.amr.corp.intel.com> References: <5C9B2DB6AAFD914E864AF9803780B66A94FA@FMSMSX108.amr.corp.intel.com> Message-ID: <626E0DC7-D9EF-4D23-B745-B65D412F1291@2pi.dk> On Jan 3, 2012, at 9:23 AM, Zhang, Andy wrote: > Currently, TableGen uses an anonymous enum for subtarget features. When > compiling with Visual C++, enums are always 'int's, so with more than 32 subtarget > features, some values will overflow. > > The attached patch modifies TableGen to emit 'const uint64_t' for subtarget > features when there are more than 32 of them. It was split off from my > earlier patch for Atom optimizations, as requested. > > If this looks OK, could it be committed to trunk? Committed r147491. Thanks, /jakob From mcrosier at apple.com Tue Jan 3 17:19:12 2012 From: mcrosier at apple.com (Chad Rosier) Date: Tue, 03 Jan 2012 23:19:12 -0000 Subject: [llvm-commits] [llvm] r147495 - /llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Message-ID: <20120103231912.AB1362A6C12C@llvm.org> Author: mcrosier Date: Tue Jan 3 17:19:12 2012 New Revision: 147495 URL: http://llvm.org/viewvc/llvm-project?rev=147495&view=rev Log: Fix 80-column violations. Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=147495&r1=147494&r2=147495&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original) +++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Tue Jan 3 17:19:12 2012 @@ -7438,9 +7438,9 @@ } -/// LowerShiftParts - Lower SRA_PARTS and friends, which return two i32 values and -/// take a 2 x i32 value to shift plus a shift amount. -SDValue X86TargetLowering::LowerShiftParts(SDValue Op, SelectionDAG &DAG) const { +/// LowerShiftParts - Lower SRA_PARTS and friends, which return two i32 values +/// and take a 2 x i32 value to shift plus a shift amount. +SDValue X86TargetLowering::LowerShiftParts(SDValue Op, SelectionDAG &DAG) const{ assert(Op.getNumOperands() == 3 && "Not a double-shift!"); EVT VT = Op.getValueType(); unsigned VTBits = VT.getSizeInBits(); @@ -13958,7 +13958,8 @@ // Bitcast the loaded value to a vector of the original element type, in // the size of the target vector type. - SDValue SlicedVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, ScalarInVector); + SDValue SlicedVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, + ScalarInVector); unsigned SizeRatio = RegSz/MemSz; // Redistribute the loaded elements into the different locations. From rafael.espindola at gmail.com Tue Jan 3 17:39:44 2012 From: rafael.espindola at gmail.com (=?ISO-8859-1?Q?Rafael_=C1vila_de_Esp=EDndola?=) Date: Tue, 03 Jan 2012 18:39:44 -0500 Subject: [llvm-commits] [llvm] r147431 - in /llvm/trunk/unittests: Bitcode/ Bitcode/BitReaderTest.cpp Bitcode/Makefile CMakeLists.txt Makefile VMCore/Makefile VMCore/pr11677.cpp In-Reply-To: References: <20120102091948.9C2891BE003@llvm.org> <1F59E691-F155-4C99-9E6F-F68F3D5EE070@apple.com> Message-ID: <4F0391C0.1040403@gmail.com> > Why not write this as an LTO test in llvm/test/Linker then? > I was only able to make this particular manifestation of the bug show up with the C lto api or by emulating what it was doing. What is needed is running the verifier before the function is materialized. I wrote a unit test because I could not reproduce it with the tools in the repository, and depending on an external tool (gold) would be bad. An option that I considered was changing opt to (optionally?) use the lazy bitcode reader. With that I think this test could become just llvm-as %s -o %t.bc opt -verify %t.bc Would that be better? > > Why not just use the proper infrastructure we already have for this, > instead of pushing unit tests? > > -Chris > Cheers, Rafael From sabre at nondot.org Tue Jan 3 17:47:06 2012 From: sabre at nondot.org (Chris Lattner) Date: Tue, 03 Jan 2012 23:47:06 -0000 Subject: [llvm-commits] [llvm] r147501 - in /llvm/trunk: include/llvm/LLVMContext.h lib/VMCore/LLVMContext.cpp Message-ID: <20120103234706.376162A6C12C@llvm.org> Author: lattner Date: Tue Jan 3 17:47:05 2012 New Revision: 147501 URL: http://llvm.org/viewvc/llvm-project?rev=147501&view=rev Log: generalize LLVMContext::emitError to take a twine instead of a StringRef. Modified: llvm/trunk/include/llvm/LLVMContext.h llvm/trunk/lib/VMCore/LLVMContext.cpp Modified: llvm/trunk/include/llvm/LLVMContext.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/LLVMContext.h?rev=147501&r1=147500&r2=147501&view=diff ============================================================================== --- llvm/trunk/include/llvm/LLVMContext.h (original) +++ llvm/trunk/include/llvm/LLVMContext.h Tue Jan 3 17:47:05 2012 @@ -19,6 +19,7 @@ class LLVMContextImpl; class StringRef; +class Twine; class Instruction; class Module; class SMDiagnostic; @@ -80,9 +81,9 @@ /// be prepared to drop the erroneous construct on the floor and "not crash". /// The generated code need not be correct. The error message will be /// implicitly prefixed with "error: " and should not end with a ".". - void emitError(unsigned LocCookie, StringRef ErrorStr); - void emitError(const Instruction *I, StringRef ErrorStr); - void emitError(StringRef ErrorStr); + void emitError(unsigned LocCookie, const Twine &ErrorStr); + void emitError(const Instruction *I, const Twine &ErrorStr); + void emitError(const Twine &ErrorStr); private: // DO NOT IMPLEMENT Modified: llvm/trunk/lib/VMCore/LLVMContext.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/LLVMContext.cpp?rev=147501&r1=147500&r2=147501&view=diff ============================================================================== --- llvm/trunk/lib/VMCore/LLVMContext.cpp (original) +++ llvm/trunk/lib/VMCore/LLVMContext.cpp Tue Jan 3 17:47:05 2012 @@ -83,11 +83,11 @@ return pImpl->InlineAsmDiagContext; } -void LLVMContext::emitError(StringRef ErrorStr) { +void LLVMContext::emitError(const Twine &ErrorStr) { emitError(0U, ErrorStr); } -void LLVMContext::emitError(const Instruction *I, StringRef ErrorStr) { +void LLVMContext::emitError(const Instruction *I, const Twine &ErrorStr) { unsigned LocCookie = 0; if (const MDNode *SrcLoc = I->getMetadata("srcloc")) { if (SrcLoc->getNumOperands() != 0) @@ -97,7 +97,7 @@ return emitError(LocCookie, ErrorStr); } -void LLVMContext::emitError(unsigned LocCookie, StringRef ErrorStr) { +void LLVMContext::emitError(unsigned LocCookie, const Twine &ErrorStr) { // If there is no error handler installed, just print the error and exit. if (pImpl->InlineAsmDiagHandler == 0) { errs() << "error: " << ErrorStr << "\n"; From sabre at nondot.org Tue Jan 3 17:51:01 2012 From: sabre at nondot.org (Chris Lattner) Date: Tue, 03 Jan 2012 23:51:01 -0000 Subject: [llvm-commits] [llvm] r147502 - /llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp Message-ID: <20120103235101.E57BE2A6C12C@llvm.org> Author: lattner Date: Tue Jan 3 17:51:01 2012 New Revision: 147502 URL: http://llvm.org/viewvc/llvm-project?rev=147502&view=rev Log: Turn a few more inline asm errors into "emitErrors" instead of fatal errors. Before we'd get: $ clang t.c fatal error: error in backend: Invalid operand for inline asm constraint 'i'! Now we get: $ clang t.c t.c:16:5: error: invalid operand for inline asm constraint 'i'! "movq (%4), %%mm0\n" ^ Which at least gets us the inline asm that is the problem. Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp?rev=147502&r1=147501&r2=147502&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp Tue Jan 3 17:51:01 2012 @@ -6138,9 +6138,13 @@ // Copy the output from the appropriate register. Find a register that // we can use. - if (OpInfo.AssignedRegs.Regs.empty()) - report_fatal_error("Couldn't allocate output reg for constraint '" + - Twine(OpInfo.ConstraintCode) + "'!"); + if (OpInfo.AssignedRegs.Regs.empty()) { + LLVMContext &Ctx = *DAG.getContext(); + Ctx.emitError(CS.getInstruction(), + "couldn't allocate output register for constraint '" + + Twine(OpInfo.ConstraintCode) + "'"); + break; + } // If this is an indirect operand, store through the pointer after the // asm. @@ -6240,9 +6244,13 @@ std::vector Ops; TLI.LowerAsmOperandForConstraint(InOperandVal, OpInfo.ConstraintCode, Ops, DAG); - if (Ops.empty()) - report_fatal_error("Invalid operand for inline asm constraint '" + - Twine(OpInfo.ConstraintCode) + "'!"); + if (Ops.empty()) { + LLVMContext &Ctx = *DAG.getContext(); + Ctx.emitError(CS.getInstruction(), + "invalid operand for inline asm constraint '" + + Twine(OpInfo.ConstraintCode) + "'"); + break; + } // Add information to the INLINEASM node to know about this input. unsigned ResOpType = @@ -6273,9 +6281,13 @@ "Don't know how to handle indirect register inputs yet!"); // Copy the input into the appropriate registers. - if (OpInfo.AssignedRegs.Regs.empty()) - report_fatal_error("Couldn't allocate input reg for constraint '" + - Twine(OpInfo.ConstraintCode) + "'!"); + if (OpInfo.AssignedRegs.Regs.empty()) { + LLVMContext &Ctx = *DAG.getContext(); + Ctx.emitError(CS.getInstruction(), + "couldn't allocate input reg for constraint '" + + Twine(OpInfo.ConstraintCode) + "'"); + break; + } OpInfo.AssignedRegs.getCopyToRegs(InOperandVal, DAG, getCurDebugLoc(), Chain, &Flag); From daniel at zuster.org Tue Jan 3 18:49:49 2012 From: daniel at zuster.org (Daniel Dunbar) Date: Wed, 04 Jan 2012 00:49:49 -0000 Subject: [llvm-commits] [zorg] r147507 - in /zorg/trunk/lnt/lnt: lnttool/import_data.py server/config.py server/ui/app.py Message-ID: <20120104004949.9C64B2A6C12C@llvm.org> Author: ddunbar Date: Tue Jan 3 18:49:49 2012 New Revision: 147507 URL: http://llvm.org/viewvc/llvm-project?rev=147507&view=rev Log: [lnt/v0.4] lnt.server.config: Add a get_database method to centralize the version based instantiation, and switch to it. Modified: zorg/trunk/lnt/lnt/lnttool/import_data.py zorg/trunk/lnt/lnt/server/config.py zorg/trunk/lnt/lnt/server/ui/app.py Modified: zorg/trunk/lnt/lnt/lnttool/import_data.py URL: http://llvm.org/viewvc/llvm-project/zorg/trunk/lnt/lnt/lnttool/import_data.py?rev=147507&r1=147506&r2=147507&view=diff ============================================================================== --- zorg/trunk/lnt/lnt/lnttool/import_data.py (original) +++ zorg/trunk/lnt/lnt/lnttool/import_data.py Tue Jan 3 18:49:49 2012 @@ -48,19 +48,8 @@ exec open(config) in config_data config = lnt.server.config.Config.fromData(config, config_data) - # Get the database entry to use. - db_entry = config.databases.get(opts.database) - if db_entry is None: - parser.error("invalid database name") - - # Load the appropriate version of the database. - if db_entry.db_version == '0.3': - db = lnt.db.perfdb.PerfDB(db_entry.path, echo=opts.show_sql) - elif db_entry.db_version == '0.4': - db = lnt.server.db.v4db.V4DB(db_entry.path, echo=opts.show_sql) - else: - raise NotImplementedError,"unable to import to version %r database" % ( - db_entry.db_version,) + # Get the database. + db = config.get_database(opts.database, echo=opts.show_sql) # Load the database. success = True Modified: zorg/trunk/lnt/lnt/server/config.py URL: http://llvm.org/viewvc/llvm-project/zorg/trunk/lnt/lnt/server/config.py?rev=147507&r1=147506&r2=147507&view=diff ============================================================================== --- zorg/trunk/lnt/lnt/server/config.py (original) +++ zorg/trunk/lnt/lnt/server/config.py Tue Jan 3 18:49:49 2012 @@ -5,6 +5,9 @@ import os import re +import lnt.db.perfdb +import lnt.server.db.v4db + class EmailConfig: @staticmethod def fromData(data): @@ -94,3 +97,24 @@ while self.zorgURL.endswith('/'): self.zorgURL = zorgURL[:-1] self.databases = databases + + def get_database(self, name, echo=False): + """ + get_database(name, echo=False) -> db or None + + Return the appropriate instance of the database with the given name, or + None if there is no database with that name.""" + + # Get the database entry. + db_entry = self.databases.get(name) + if db_entry is None: + return None + + # Instantiate the appropriate database version. + if db_entry.db_version == '0.3': + return lnt.db.perfdb.PerfDB(db_entry.path, echo=echo) + if db_entry.db_version == '0.4': + return lnt.server.db.v4db.V4DB(db_entry.path, echo=echo) + + raise NotImplementedError,"unable to import to version %r database" % ( + db_entry.db_version,) Modified: zorg/trunk/lnt/lnt/server/ui/app.py URL: http://llvm.org/viewvc/llvm-project/zorg/trunk/lnt/lnt/server/ui/app.py?rev=147507&r1=147506&r2=147507&view=diff ============================================================================== --- zorg/trunk/lnt/lnt/server/ui/app.py (original) +++ zorg/trunk/lnt/lnt/server/ui/app.py Tue Jan 3 18:49:49 2012 @@ -44,20 +44,18 @@ def get_db(self): if self.db is None: - if g.db_info.db_version == '0.3': - self.db = perfdb.PerfDB(g.db_info.path) - else: - self.db = lnt.server.db.v4db.V4DB(g.db_info.path) + echo = bool(self.args.get('db_log') or self.form.get('db_log')) + + self.db = current_app.old_config.get_database(g.db_name, echo=echo) # Enable SQL logging with db_log. # # FIXME: Conditionalize on an is_production variable. - if self.args.get('db_log') or self.form.get('db_log'): + if echo: import logging, StringIO g.db_log = StringIO.StringIO() logger = logging.getLogger("sqlalchemy") logger.addHandler(logging.StreamHandler(g.db_log)) - self.db.engine.echo = True return self.db From daniel at zuster.org Tue Jan 3 18:49:53 2012 From: daniel at zuster.org (Daniel Dunbar) Date: Wed, 04 Jan 2012 00:49:53 -0000 Subject: [llvm-commits] [zorg] r147508 - in /zorg/trunk/lnt/lnt: server/config.py server/db/v4db.py util/ImportData.py Message-ID: <20120104004953.36F972A6C12C@llvm.org> Author: ddunbar Date: Tue Jan 3 18:49:52 2012 New Revision: 147508 URL: http://llvm.org/viewvc/llvm-project?rev=147508&view=rev Log: [lnt/v0.4] lnt.util.ImportData: Add a "shadow import" feature which allows database entries to configure a "shadow" database to always duplicate import submissions into. - Useful for bringing up a new database schema, for example. Imagine that!!! Modified: zorg/trunk/lnt/lnt/server/config.py zorg/trunk/lnt/lnt/server/db/v4db.py zorg/trunk/lnt/lnt/util/ImportData.py Modified: zorg/trunk/lnt/lnt/server/config.py URL: http://llvm.org/viewvc/llvm-project/zorg/trunk/lnt/lnt/server/config.py?rev=147508&r1=147507&r2=147508&view=diff ============================================================================== --- zorg/trunk/lnt/lnt/server/config.py (original) +++ zorg/trunk/lnt/lnt/server/config.py Tue Jan 3 18:49:52 2012 @@ -52,15 +52,17 @@ bool(dict.get('showGeneral')), bool(dict.get('showSimple')), str(dict.get('db_version', '0.3')), + dict.get('shadow_import', None), email_config) def __init__(self, path, showNightlytest, showGeneral, showSimple, - db_version, email_config): + db_version, shadow_import, email_config): self.path = path self.showGeneral = showGeneral self.showNightlytest = showNightlytest self.showSimple = showSimple self.db_version = db_version + self.shadow_import = shadow_import self.email_config = email_config class Config: Modified: zorg/trunk/lnt/lnt/server/db/v4db.py URL: http://llvm.org/viewvc/llvm-project/zorg/trunk/lnt/lnt/server/db/v4db.py?rev=147508&r1=147507&r2=147508&view=diff ============================================================================== --- zorg/trunk/lnt/lnt/server/db/v4db.py (original) +++ zorg/trunk/lnt/lnt/server/db/v4db.py Tue Jan 3 18:49:52 2012 @@ -119,6 +119,10 @@ tag,) db = self.testsuite.get(db_name) + if db is None: + raise ValueError,"test suite %r not present in this database!" % ( + db_name) + return db.importDataFromDict(data) def get_db_summary(self): Modified: zorg/trunk/lnt/lnt/util/ImportData.py URL: http://llvm.org/viewvc/llvm-project/zorg/trunk/lnt/lnt/util/ImportData.py?rev=147508&r1=147507&r2=147508&view=diff ============================================================================== --- zorg/trunk/lnt/lnt/util/ImportData.py (original) +++ zorg/trunk/lnt/lnt/util/ImportData.py Tue Jan 3 18:49:52 2012 @@ -100,6 +100,25 @@ result['report_time'] = time.time() - importStartTime result['total_time'] = time.time() - startTime + # If this database has a shadow import configured, import the run into that + # database as well. + db_config = config.databases[db_name] + if db_config.shadow_import: + # Load the shadow database to import into. + shadow_name = db_config.shadow_import + shadow_db = config.get_database(shadow_name) + if shadow_db is None: + raise ValueError,("invalid configuration, shadow import " + "database %r does not exist") % shadow_name + + # Perform the shadow import. + shadow_result = import_and_report(config, shadow_name, + shadow_db, file, format, commit, + show_sample_count, disable_email) + + # Append the shadow result to the result. + result['shadow_result'] = shadow_result + result['success'] = True return result From kcc at google.com Tue Jan 3 19:02:14 2012 From: kcc at google.com (Kostya Serebryany) Date: Wed, 04 Jan 2012 01:02:14 -0000 Subject: [llvm-commits] [llvm] r147509 - /llvm/trunk/test/Instrumentation/AddressSanitizer/instrument_load_then_store.ll Message-ID: <20120104010214.EA5912A6C12C@llvm.org> Author: kcc Date: Tue Jan 3 19:02:14 2012 New Revision: 147509 URL: http://llvm.org/viewvc/llvm-project?rev=147509&view=rev Log: [asan] one more test for asan instrumentation: (*a)++ should be instrumented only once. Added: llvm/trunk/test/Instrumentation/AddressSanitizer/instrument_load_then_store.ll Added: llvm/trunk/test/Instrumentation/AddressSanitizer/instrument_load_then_store.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Instrumentation/AddressSanitizer/instrument_load_then_store.ll?rev=147509&view=auto ============================================================================== --- llvm/trunk/test/Instrumentation/AddressSanitizer/instrument_load_then_store.ll (added) +++ llvm/trunk/test/Instrumentation/AddressSanitizer/instrument_load_then_store.ll Tue Jan 3 19:02:14 2012 @@ -0,0 +1,25 @@ +; Test that AddressSanitizer instruments "(*a)++" only once. +; RUN: opt < %s -asan -S -asan-opt=1 | FileCheck %s -check-prefix=OPT1 +; RUN: opt < %s -asan -S -asan-opt=0 | FileCheck %s -check-prefix=OPT0 + +target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64" +target triple = "x86_64-unknown-linux-gnu" +define void @IncrementMe(i32* %a) { +entry: + %tmp1 = load i32* %a, align 4 + %tmp2 = add i32 %tmp1, 1 + store i32 %tmp2, i32* %a, align 4 + ret void +} + +; With optimizations enabled we should see only one call to __asan_report_* +; OPT1: IncrementMe +; OPT1: __asan_report_ +; OPT1-NOT: __asan_report_ +; OPT1: asan.module_ctor + +; Without optimizations we should see two calls to __asan_report_* +; OPT0: IncrementMe +; OPT0: __asan_report_ +; OPT0: __asan_report_ +; OPT0: asan.module_ctor From daniel at zuster.org Tue Jan 3 19:15:36 2012 From: daniel at zuster.org (Daniel Dunbar) Date: Wed, 04 Jan 2012 01:15:36 -0000 Subject: [llvm-commits] [zorg] r147510 - /zorg/trunk/lnt/lnt/server/ui/views.py Message-ID: <20120104011536.269DC2A6C12C@llvm.org> Author: ddunbar Date: Tue Jan 3 19:15:35 2012 New Revision: 147510 URL: http://llvm.org/viewvc/llvm-project?rev=147510&view=rev Log: [lnt/v0.4] lnt.server.ui/submitRun: Allow submission to v4 databases. Modified: zorg/trunk/lnt/lnt/server/ui/views.py Modified: zorg/trunk/lnt/lnt/server/ui/views.py URL: http://llvm.org/viewvc/llvm-project/zorg/trunk/lnt/lnt/server/ui/views.py?rev=147510&r1=147509&r2=147510&view=diff ============================================================================== --- zorg/trunk/lnt/lnt/server/ui/views.py (original) +++ zorg/trunk/lnt/lnt/server/ui/views.py Tue Jan 3 19:15:35 2012 @@ -90,7 +90,7 @@ def browse(): return render_template("browse.html") - at db_route('/submitRun', methods=('GET', 'POST')) + at db_route('/submitRun', only_v3=False, methods=('GET', 'POST')) def submit_run(): from lnt.util import ImportData From mcrosier at apple.com Tue Jan 3 19:30:09 2012 From: mcrosier at apple.com (Chad Rosier) Date: Tue, 03 Jan 2012 17:30:09 -0800 Subject: [llvm-commits] [llvm] r147308 - in /llvm/trunk: lib/Target/X86/X86ISelLowering.cpp test/CodeGen/X86/avx-shuffle.ll In-Reply-To: <20111228081401.E07221BE003@llvm.org> References: <20111228081401.E07221BE003@llvm.org> Message-ID: <1C6CDAB6-82FE-4107-A408-C874F50BF5EA@apple.com> Hi Elena, Just a few comments below. On Dec 28, 2011, at 12:14 AM, Elena Demikhovsky wrote: > Author: delena > Date: Wed Dec 28 02:14:01 2011 > New Revision: 147308 > > URL: http://llvm.org/viewvc/llvm-project?rev=147308&view=rev > Log: > Fixed a bug in LowerVECTOR_SHUFFLE and LowerBUILD_VECTOR. > Matching MOVLP mask for AVX (265-bit vectors) was wrong. > The failure was detected by conformance tests. As far as I can tell this patch is addressing two bugs, one in LowerBUILD_VECTOR and another with LowerVECTOR_SHUFFLE/MOVLP. These should really be fixed in two separate commits. > > Modified: > llvm/trunk/lib/Target/X86/X86ISelLowering.cpp > llvm/trunk/test/CodeGen/X86/avx-shuffle.ll > > Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=147308&r1=147307&r2=147308&view=diff > ============================================================================== > --- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original) > +++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Wed Dec 28 02:14:01 2011 > @@ -3448,6 +3448,11 @@ > /// isMOVLPMask - Return true if the specified VECTOR_SHUFFLE operand > /// specifies a shuffle of elements that is suitable for input to MOVLP{S|D}. > bool X86::isMOVLPMask(ShuffleVectorSDNode *N) { > + EVT VT = N->getValueType(0); > + > + if (VT.getSizeInBits() != 128) > + return false; > + I'm not sure I agree with the approach taken here... > unsigned NumElems = N->getValueType(0).getVectorNumElements(); > > if (NumElems != 2 && NumElems != 4) > @@ -3666,6 +3671,8 @@ > static bool isMOVLMask(const SmallVectorImpl &Mask, EVT VT) { > if (VT.getVectorElementType().getSizeInBits() < 32) > return false; > + if (VT.getSizeInBits() == 256) > + return false; ..and here. Aren't these functions behaving correctly? I believe the real problem is the code that is predicated upon these functions; they don't fully support codegen when AVX is enabled. And one moot point.. The conditional statements that checks the size of the vectors could be more consistent (i.e., both (VT.getSizeInBits != 128) or (VT.getSizeInBits != 128), but not a combination of the two). > int NumElts = VT.getVectorNumElements(); > > @@ -5158,16 +5165,30 @@ > return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item); > } else if (ExtVT == MVT::i32 || ExtVT == MVT::f32 || ExtVT == MVT::f64 || > (ExtVT == MVT::i64 && Subtarget->is64Bit())) { > + if (VT.getSizeInBits() == 256) { > + > + EVT VT128 = EVT::getVectorVT(*DAG.getContext(), ExtVT, NumElems / 2); > + Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT128, Item); > + SDValue ZeroVec = getZeroVector(VT, true, DAG, dl); > + return Insert128BitVector(ZeroVec, Item, DAG.getConstant(0, MVT::i32), > + DAG, dl); > + } > Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item); > // Turn it into a MOVL (i.e. movss, movsd, or movd) to a zero vector. > return getShuffleVectorZeroOrUndef(Item, 0, true,Subtarget->hasXMMInt(), > DAG); > } else if (ExtVT == MVT::i16 || ExtVT == MVT::i8) { > Item = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Item); > - unsigned NumBits = VT.getSizeInBits(); > - assert((NumBits == 128 || NumBits == 256) && > - "Expected an SSE or AVX value type!"); > - EVT MiddleVT = NumBits == 128 ? MVT::v4i32 : MVT::v8i32; > + if (VT.getSizeInBits() == 256) { > + > + EVT VT128 = EVT::getVectorVT(*DAG.getContext(), ExtVT, NumElems / 2); > + Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT128, Item); > + SDValue ZeroVec = getZeroVector(VT, true, DAG, dl); > + return Insert128BitVector(ZeroVec, Item, DAG.getConstant(0, MVT::i32), > + DAG, dl); > + } > + assert (VT.getSizeInBits() == 128 || "Expected an SSE value type!"); > + EVT MiddleVT = MVT::v4i32; > Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MiddleVT, Item); > Item = getShuffleVectorZeroOrUndef(Item, 0, true, > Subtarget->hasXMMInt(), DAG); > > Modified: llvm/trunk/test/CodeGen/X86/avx-shuffle.ll > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx-shuffle.ll?rev=147308&r1=147307&r2=147308&view=diff > ============================================================================== > --- llvm/trunk/test/CodeGen/X86/avx-shuffle.ll (original) > +++ llvm/trunk/test/CodeGen/X86/avx-shuffle.ll Wed Dec 28 02:14:01 2011 > @@ -13,8 +13,22 @@ > define <3 x i64> @test2(<2 x i64> %v) nounwind readnone { > ; CHECK: test2: > ; CHECK: vxorpd > -; CHECK: vmovsd > +; CHECK: vperm2f128 > %1 = shufflevector <2 x i64> %v, <2 x i64> %v, <3 x i32> > %2 = shufflevector <3 x i64> zeroinitializer, <3 x i64> %1, <3 x i32> > ret <3 x i64> %2 > } > + > +define <4 x i64> @test3(<4 x i64> %a, <4 x i64> %b) nounwind { > + %c = shufflevector <4 x i64> %a, <4 x i64> %b, <4 x i32> > + ret <4 x i64> %c > +; CHECK: test3: > +; CHECK: vperm2f128 > +} > + > +define <8 x float> @test4(float %a) nounwind { > + %b = insertelement <8 x float> zeroinitializer, float %a, i32 0 > + ret <8 x float> %b > +; CHECK: test4: > +; CHECK: vinsertf128 > +} > \ No newline at end of file > Please make sure your test case ends with a newline. This was fixed in r147481. Chad > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From mcrosier at apple.com Tue Jan 3 19:35:30 2012 From: mcrosier at apple.com (Chad Rosier) Date: Tue, 03 Jan 2012 17:35:30 -0800 Subject: [llvm-commits] [llvm] r147308 - in /llvm/trunk: lib/Target/X86/X86ISelLowering.cpp test/CodeGen/X86/avx-shuffle.ll In-Reply-To: <1C6CDAB6-82FE-4107-A408-C874F50BF5EA@apple.com> References: <20111228081401.E07221BE003@llvm.org> <1C6CDAB6-82FE-4107-A408-C874F50BF5EA@apple.com> Message-ID: On Jan 3, 2012, at 5:30 PM, Chad Rosier wrote: > Hi Elena, > Just a few comments below. > > On Dec 28, 2011, at 12:14 AM, Elena Demikhovsky wrote: > >> Author: delena >> Date: Wed Dec 28 02:14:01 2011 >> New Revision: 147308 >> >> URL: http://llvm.org/viewvc/llvm-project?rev=147308&view=rev >> Log: >> Fixed a bug in LowerVECTOR_SHUFFLE and LowerBUILD_VECTOR. >> Matching MOVLP mask for AVX (265-bit vectors) was wrong. >> The failure was detected by conformance tests. > > As far as I can tell this patch is addressing two bugs, one in LowerBUILD_VECTOR and another with LowerVECTOR_SHUFFLE/MOVLP. These should really be fixed in two separate commits. > >> >> Modified: >> llvm/trunk/lib/Target/X86/X86ISelLowering.cpp >> llvm/trunk/test/CodeGen/X86/avx-shuffle.ll >> >> Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp >> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=147308&r1=147307&r2=147308&view=diff >> ============================================================================== >> --- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original) >> +++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Wed Dec 28 02:14:01 2011 >> @@ -3448,6 +3448,11 @@ >> /// isMOVLPMask - Return true if the specified VECTOR_SHUFFLE operand >> /// specifies a shuffle of elements that is suitable for input to MOVLP{S|D}. >> bool X86::isMOVLPMask(ShuffleVectorSDNode *N) { >> + EVT VT = N->getValueType(0); >> + >> + if (VT.getSizeInBits() != 128) >> + return false; >> + > > I'm not sure I agree with the approach taken here... > >> unsigned NumElems = N->getValueType(0).getVectorNumElements(); >> >> if (NumElems != 2 && NumElems != 4) >> @@ -3666,6 +3671,8 @@ >> static bool isMOVLMask(const SmallVectorImpl &Mask, EVT VT) { >> if (VT.getVectorElementType().getSizeInBits() < 32) >> return false; >> + if (VT.getSizeInBits() == 256) >> + return false; > > ..and here. Aren't these functions behaving correctly? I believe the real problem is the code that is predicated upon these functions; they don't fully support codegen when AVX is enabled. > > And one moot point.. The conditional statements that checks the size of the vectors could be more consistent (i.e., both (VT.getSizeInBits != 128) or (VT.getSizeInBits != 128), but not a combination of the two). (i.e., both (VT.getSizeInBits != 128) or (VT.getSizeInBits == 256), ...) >> int NumElts = VT.getVectorNumElements(); >> >> @@ -5158,16 +5165,30 @@ >> return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item); >> } else if (ExtVT == MVT::i32 || ExtVT == MVT::f32 || ExtVT == MVT::f64 || >> (ExtVT == MVT::i64 && Subtarget->is64Bit())) { >> + if (VT.getSizeInBits() == 256) { >> + >> + EVT VT128 = EVT::getVectorVT(*DAG.getContext(), ExtVT, NumElems / 2); >> + Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT128, Item); >> + SDValue ZeroVec = getZeroVector(VT, true, DAG, dl); >> + return Insert128BitVector(ZeroVec, Item, DAG.getConstant(0, MVT::i32), >> + DAG, dl); >> + } >> Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item); >> // Turn it into a MOVL (i.e. movss, movsd, or movd) to a zero vector. >> return getShuffleVectorZeroOrUndef(Item, 0, true,Subtarget->hasXMMInt(), >> DAG); >> } else if (ExtVT == MVT::i16 || ExtVT == MVT::i8) { >> Item = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Item); >> - unsigned NumBits = VT.getSizeInBits(); >> - assert((NumBits == 128 || NumBits == 256) && >> - "Expected an SSE or AVX value type!"); >> - EVT MiddleVT = NumBits == 128 ? MVT::v4i32 : MVT::v8i32; >> + if (VT.getSizeInBits() == 256) { >> + >> + EVT VT128 = EVT::getVectorVT(*DAG.getContext(), ExtVT, NumElems / 2); >> + Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT128, Item); >> + SDValue ZeroVec = getZeroVector(VT, true, DAG, dl); >> + return Insert128BitVector(ZeroVec, Item, DAG.getConstant(0, MVT::i32), >> + DAG, dl); >> + } >> + assert (VT.getSizeInBits() == 128 || "Expected an SSE value type!"); >> + EVT MiddleVT = MVT::v4i32; >> Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MiddleVT, Item); >> Item = getShuffleVectorZeroOrUndef(Item, 0, true, >> Subtarget->hasXMMInt(), DAG); >> >> Modified: llvm/trunk/test/CodeGen/X86/avx-shuffle.ll >> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx-shuffle.ll?rev=147308&r1=147307&r2=147308&view=diff >> ============================================================================== >> --- llvm/trunk/test/CodeGen/X86/avx-shuffle.ll (original) >> +++ llvm/trunk/test/CodeGen/X86/avx-shuffle.ll Wed Dec 28 02:14:01 2011 >> @@ -13,8 +13,22 @@ >> define <3 x i64> @test2(<2 x i64> %v) nounwind readnone { >> ; CHECK: test2: >> ; CHECK: vxorpd >> -; CHECK: vmovsd >> +; CHECK: vperm2f128 >> %1 = shufflevector <2 x i64> %v, <2 x i64> %v, <3 x i32> >> %2 = shufflevector <3 x i64> zeroinitializer, <3 x i64> %1, <3 x i32> >> ret <3 x i64> %2 >> } >> + >> +define <4 x i64> @test3(<4 x i64> %a, <4 x i64> %b) nounwind { >> + %c = shufflevector <4 x i64> %a, <4 x i64> %b, <4 x i32> >> + ret <4 x i64> %c >> +; CHECK: test3: >> +; CHECK: vperm2f128 >> +} >> + >> +define <8 x float> @test4(float %a) nounwind { >> + %b = insertelement <8 x float> zeroinitializer, float %a, i32 0 >> + ret <8 x float> %b >> +; CHECK: test4: >> +; CHECK: vinsertf128 >> +} >> \ No newline at end of file >> > > Please make sure your test case ends with a newline. This was fixed in r147481. > > Chad > >> _______________________________________________ >> llvm-commits mailing list >> llvm-commits at cs.uiuc.edu >> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits > From evan.cheng at apple.com Tue Jan 3 19:41:39 2012 From: evan.cheng at apple.com (Evan Cheng) Date: Wed, 04 Jan 2012 01:41:39 -0000 Subject: [llvm-commits] [llvm] r147512 - in /llvm/trunk: lib/Target/X86/X86ISelLowering.cpp test/CodeGen/X86/jump_sign.ll Message-ID: <20120104014139.D2FE92A6C12C@llvm.org> Author: evancheng Date: Tue Jan 3 19:41:39 2012 New Revision: 147512 URL: http://llvm.org/viewvc/llvm-project?rev=147512&view=rev Log: For x86, canonicalize max (x > y) ? x : y => (x >= y) ? x : y So for something like (x - y) > 0 : (x - y) ? 0 It will be (x - y) >= 0 : (x - y) ? 0 This makes is possible to test sign-bit and eliminate a comparison against zero. e.g. subl %esi, %edi testl %edi, %edi movl $0, %eax cmovgl %edi, %eax => xorl %eax, %eax subl %esi, $edi cmovsl %eax, %edi rdar://10633221 Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp llvm/trunk/test/CodeGen/X86/jump_sign.ll Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=147512&r1=147511&r2=147512&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original) +++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Tue Jan 3 19:41:39 2012 @@ -13139,6 +13139,37 @@ } } + // Canonicalize max and min: + // (x > y) ? x : y -> (x >= y) ? x : y + // (x < y) ? x : y -> (x <= y) ? x : y + // This allows use of COND_S / COND_NS (see TranslateX86CC) which eliminates + // the need for an extra compare + // against zero. e.g. + // (x - y) > 0 : (x - y) ? 0 -> (x - y) >= 0 : (x - y) ? 0 + // subl %esi, %edi + // testl %edi, %edi + // movl $0, %eax + // cmovgl %edi, %eax + // => + // xorl %eax, %eax + // subl %esi, $edi + // cmovsl %eax, %edi + if (N->getOpcode() == ISD::SELECT && Cond.getOpcode() == ISD::SETCC && + DAG.isEqualTo(LHS, Cond.getOperand(0)) && + DAG.isEqualTo(RHS, Cond.getOperand(1))) { + ISD::CondCode CC = cast(Cond.getOperand(2))->get(); + switch (CC) { + default: break; + case ISD::SETLT: + case ISD::SETGT: { + ISD::CondCode NewCC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGE; + Cond = DAG.getSetCC(Cond.getDebugLoc(), Cond.getValueType(), + Cond.getOperand(0), Cond.getOperand(1), NewCC); + return DAG.getNode(ISD::SELECT, DL, VT, Cond, LHS, RHS); + } + } + } + return SDValue(); } Modified: llvm/trunk/test/CodeGen/X86/jump_sign.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/jump_sign.ll?rev=147512&r1=147511&r2=147512&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/X86/jump_sign.ll (original) +++ llvm/trunk/test/CodeGen/X86/jump_sign.ll Tue Jan 3 19:41:39 2012 @@ -1,7 +1,9 @@ -; RUN: llc < %s -march=x86 | grep jns +; RUN: llc < %s -march=x86 | FileCheck %s define i32 @f(i32 %X) { entry: +; CHECK: f: +; CHECK: jns %tmp1 = add i32 %X, 1 ; [#uses=1] %tmp = icmp slt i32 %tmp1, 0 ; [#uses=1] br i1 %tmp, label %cond_true, label %cond_next @@ -18,3 +20,15 @@ declare i32 @bar(...) declare i32 @baz(...) + +; rdar://10633221 +define i32 @g(i32 %a, i32 %b) nounwind { +entry: +; CHECK: g: +; CHECK-NOT: test +; CHECK: cmovs + %sub = sub nsw i32 %a, %b + %cmp = icmp sgt i32 %sub, 0 + %cond = select i1 %cmp, i32 %sub, i32 0 + ret i32 %cond +} From evan.cheng at apple.com Tue Jan 3 19:55:05 2012 From: evan.cheng at apple.com (Evan Cheng) Date: Wed, 04 Jan 2012 01:55:05 -0000 Subject: [llvm-commits] [llvm] r147513 - in /llvm/trunk: lib/Target/ARM/ test/CodeGen/ARM/ test/CodeGen/Thumb/ test/CodeGen/Thumb2/ Message-ID: <20120104015505.570FC2A6C12C@llvm.org> Author: evancheng Date: Tue Jan 3 19:55:04 2012 New Revision: 147513 URL: http://llvm.org/viewvc/llvm-project?rev=147513&view=rev Log: Fix more places which should be checking for iOS, not darwin. Modified: llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.h llvm/trunk/lib/Target/ARM/ARMFrameLowering.cpp llvm/trunk/lib/Target/ARM/Thumb1FrameLowering.cpp llvm/trunk/test/CodeGen/ARM/2007-01-19-InfiniteLoop.ll llvm/trunk/test/CodeGen/ARM/2010-12-07-PEIBug.ll llvm/trunk/test/CodeGen/ARM/2011-08-25-ldmia_ret.ll llvm/trunk/test/CodeGen/ARM/arm-returnaddr.ll llvm/trunk/test/CodeGen/ARM/debug-info-arg.ll llvm/trunk/test/CodeGen/ARM/hello.ll llvm/trunk/test/CodeGen/ARM/ifcvt10.ll llvm/trunk/test/CodeGen/ARM/ifcvt5.ll llvm/trunk/test/CodeGen/ARM/ifcvt6.ll llvm/trunk/test/CodeGen/ARM/insn-sched1.ll llvm/trunk/test/CodeGen/ARM/lsr-unfolded-offset.ll llvm/trunk/test/CodeGen/Thumb/large-stack.ll llvm/trunk/test/CodeGen/Thumb2/2010-11-22-EpilogueBug.ll llvm/trunk/test/CodeGen/Thumb2/thumb2-ifcvt2.ll llvm/trunk/test/CodeGen/Thumb2/thumb2-ldm.ll Modified: llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.h?rev=147513&r1=147512&r2=147513&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.h (original) +++ llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.h Tue Jan 3 19:55:04 2012 @@ -35,7 +35,7 @@ /// isARMArea1Register - Returns true if the register is a low register (r0-r7) /// or a stack/pc register that we should push/pop. -static inline bool isARMArea1Register(unsigned Reg, bool isDarwin) { +static inline bool isARMArea1Register(unsigned Reg, bool isIOS) { using namespace ARM; switch (Reg) { case R0: case R1: case R2: case R3: @@ -43,25 +43,25 @@ case LR: case SP: case PC: return true; case R8: case R9: case R10: case R11: - // For darwin we want r7 and lr to be next to each other. - return !isDarwin; + // For iOS we want r7 and lr to be next to each other. + return !isIOS; default: return false; } } -static inline bool isARMArea2Register(unsigned Reg, bool isDarwin) { +static inline bool isARMArea2Register(unsigned Reg, bool isIOS) { using namespace ARM; switch (Reg) { case R8: case R9: case R10: case R11: - // Darwin has this second area. - return isDarwin; + // iOS has this second area. + return isIOS; default: return false; } } -static inline bool isARMArea3Register(unsigned Reg, bool isDarwin) { +static inline bool isARMArea3Register(unsigned Reg, bool isIOS) { using namespace ARM; switch (Reg) { case D15: case D14: case D13: case D12: Modified: llvm/trunk/lib/Target/ARM/ARMFrameLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMFrameLowering.cpp?rev=147513&r1=147512&r2=147513&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMFrameLowering.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMFrameLowering.cpp Tue Jan 3 19:55:04 2012 @@ -41,8 +41,8 @@ bool ARMFrameLowering::hasFP(const MachineFunction &MF) const { const TargetRegisterInfo *RegInfo = MF.getTarget().getRegisterInfo(); - // Mac OS X requires FP not to be clobbered for backtracing purpose. - if (STI.isTargetDarwin()) + // iOS requires FP not to be clobbered for backtracing purpose. + if (STI.isTargetIOS()) return true; const MachineFrameInfo *MFI = MF.getFrameInfo(); @@ -183,7 +183,7 @@ case ARM::R11: if (Reg == FramePtr) FramePtrSpillFI = FI; - if (STI.isTargetDarwin()) { + if (STI.isTargetIOS()) { AFI->addGPRCalleeSavedArea2Frame(FI); GPRCS2Size += 4; } else { @@ -206,8 +206,8 @@ if (GPRCS1Size > 0) MBBI++; // Set FP to point to the stack slot that contains the previous FP. - // For Darwin, FP is R7, which has now been stored in spill area 1. - // Otherwise, if this is not Darwin, all the callee-saved registers go + // For iOS, FP is R7, which has now been stored in spill area 1. + // Otherwise, if this is not iOS, all the callee-saved registers go // into spill area 1, including the FP in R11. In either case, it is // now safe to emit this assignment. bool HasFP = hasFP(MF); @@ -383,7 +383,7 @@ ARMCC::AL, 0, TII); else { // It's not possible to restore SP from FP in a single instruction. - // For Darwin, this looks like: + // For iOS, this looks like: // mov sp, r7 // sub sp, #24 // This is bad, if an interrupt is taken after the mov, sp is in an @@ -583,7 +583,7 @@ unsigned LastReg = 0; for (; i != 0; --i) { unsigned Reg = CSI[i-1].getReg(); - if (!(Func)(Reg, STI.isTargetDarwin())) continue; + if (!(Func)(Reg, STI.isTargetIOS())) continue; // D-registers in the aligned area DPRCS2 are NOT spilled here. if (Reg >= ARM::D8 && Reg < ARM::D8 + NumAlignedDPRCS2Regs) @@ -656,7 +656,7 @@ bool DeleteRet = false; for (; i != 0; --i) { unsigned Reg = CSI[i-1].getReg(); - if (!(Func)(Reg, STI.isTargetDarwin())) continue; + if (!(Func)(Reg, STI.isTargetIOS())) continue; // The aligned reloads from area DPRCS2 are not inserted here. if (Reg >= ARM::D8 && Reg < ARM::D8 + NumAlignedDPRCS2Regs) @@ -1256,7 +1256,7 @@ if (Spilled) { NumGPRSpills++; - if (!STI.isTargetDarwin()) { + if (!STI.isTargetIOS()) { if (Reg == ARM::LR) LRSpilled = true; CS1Spilled = true; @@ -1276,7 +1276,7 @@ break; } } else { - if (!STI.isTargetDarwin()) { + if (!STI.isTargetIOS()) { UnspilledCS1GPRs.push_back(Reg); continue; } Modified: llvm/trunk/lib/Target/ARM/Thumb1FrameLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Thumb1FrameLowering.cpp?rev=147513&r1=147512&r2=147513&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/Thumb1FrameLowering.cpp (original) +++ llvm/trunk/lib/Target/ARM/Thumb1FrameLowering.cpp Tue Jan 3 19:55:04 2012 @@ -101,7 +101,7 @@ case ARM::R11: if (Reg == FramePtr) FramePtrSpillFI = FI; - if (STI.isTargetDarwin()) { + if (STI.isTargetIOS()) { AFI->addGPRCalleeSavedArea2Frame(FI); GPRCS2Size += 4; } else { Modified: llvm/trunk/test/CodeGen/ARM/2007-01-19-InfiniteLoop.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/2007-01-19-InfiniteLoop.ll?rev=147513&r1=147512&r2=147513&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/ARM/2007-01-19-InfiniteLoop.ll (original) +++ llvm/trunk/test/CodeGen/ARM/2007-01-19-InfiniteLoop.ll Tue Jan 3 19:55:04 2012 @@ -1,4 +1,4 @@ -; RUN: llc < %s -mtriple=arm-apple-darwin -mattr=+v6,+vfp2 | FileCheck %s +; RUN: llc < %s -mtriple=arm-apple-ios -mattr=+v6,+vfp2 | FileCheck %s @quant_coef = external global [6 x [4 x [4 x i32]]] ; <[6 x [4 x [4 x i32]]]*> [#uses=1] @dequant_coef = external global [6 x [4 x [4 x i32]]] ; <[6 x [4 x [4 x i32]]]*> [#uses=1] Modified: llvm/trunk/test/CodeGen/ARM/2010-12-07-PEIBug.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/2010-12-07-PEIBug.ll?rev=147513&r1=147512&r2=147513&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/ARM/2010-12-07-PEIBug.ll (original) +++ llvm/trunk/test/CodeGen/ARM/2010-12-07-PEIBug.ll Tue Jan 3 19:55:04 2012 @@ -1,4 +1,4 @@ -; RUN: llc < %s -mtriple=thumbv7-apple-darwin10 -mcpu=cortex-a8 | FileCheck %s +; RUN: llc < %s -mtriple=thumbv7-apple-ios -mcpu=cortex-a8 | FileCheck %s ; rdar://8728956 define hidden void @foo() nounwind ssp { Modified: llvm/trunk/test/CodeGen/ARM/2011-08-25-ldmia_ret.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/2011-08-25-ldmia_ret.ll?rev=147513&r1=147512&r2=147513&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/ARM/2011-08-25-ldmia_ret.ll (original) +++ llvm/trunk/test/CodeGen/ARM/2011-08-25-ldmia_ret.ll Tue Jan 3 19:55:04 2012 @@ -1,4 +1,4 @@ -; RUN: llc < %s -mtriple=thumbv7-apple-darwin -mcpu=cortex-a9 | FileCheck %s +; RUN: llc < %s -mtriple=thumbv7-apple-ios -mcpu=cortex-a9 | FileCheck %s ; Test that ldmia_ret preserves implicit operands for return values. ; ; This CFG is reduced from a benchmark miscompile. With current Modified: llvm/trunk/test/CodeGen/ARM/arm-returnaddr.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/arm-returnaddr.ll?rev=147513&r1=147512&r2=147513&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/ARM/arm-returnaddr.ll (original) +++ llvm/trunk/test/CodeGen/ARM/arm-returnaddr.ll Tue Jan 3 19:55:04 2012 @@ -1,7 +1,7 @@ -; RUN: llc < %s -mtriple=arm-apple-darwin | FileCheck %s -; RUN: llc < %s -mtriple=thumbv6-apple-darwin | FileCheck %s -; RUN: llc < %s -mtriple=arm-apple-darwin -regalloc=basic | FileCheck %s -; RUN: llc < %s -mtriple=thumbv6-apple-darwin -regalloc=basic | FileCheck %s +; RUN: llc < %s -mtriple=arm-apple-ios | FileCheck %s +; RUN: llc < %s -mtriple=thumbv6-apple-ios | FileCheck %s +; RUN: llc < %s -mtriple=arm-apple-ios -regalloc=basic | FileCheck %s +; RUN: llc < %s -mtriple=thumbv6-apple-ios -regalloc=basic | FileCheck %s ; rdar://8015977 ; rdar://8020118 Modified: llvm/trunk/test/CodeGen/ARM/debug-info-arg.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/debug-info-arg.ll?rev=147513&r1=147512&r2=147513&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/ARM/debug-info-arg.ll (original) +++ llvm/trunk/test/CodeGen/ARM/debug-info-arg.ll Tue Jan 3 19:55:04 2012 @@ -2,7 +2,7 @@ ; Test to check argument y's debug info uses FI ; Radar 10048772 target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:32:64-v128:32:128-a0:0:32-n32" -target triple = "thumbv7-apple-macosx10.7.0" +target triple = "thumbv7-apple-ios" %struct.tag_s = type { i32, i32, i32 } Modified: llvm/trunk/test/CodeGen/ARM/hello.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/hello.ll?rev=147513&r1=147512&r2=147513&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/ARM/hello.ll (original) +++ llvm/trunk/test/CodeGen/ARM/hello.ll Tue Jan 3 19:55:04 2012 @@ -2,7 +2,7 @@ ; RUN: llc < %s -mtriple=armv6-linux-gnueabi | grep mov | count 1 ; RUN: llc < %s -mtriple=armv6-linux-gnu --disable-fp-elim | \ ; RUN: grep mov | count 2 -; RUN: llc < %s -mtriple=armv6-apple-darwin | grep mov | count 2 +; RUN: llc < %s -mtriple=armv6-apple-ios | grep mov | count 2 @str = internal constant [12 x i8] c"Hello World\00" Modified: llvm/trunk/test/CodeGen/ARM/ifcvt10.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/ifcvt10.ll?rev=147513&r1=147512&r2=147513&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/ARM/ifcvt10.ll (original) +++ llvm/trunk/test/CodeGen/ARM/ifcvt10.ll Tue Jan 3 19:55:04 2012 @@ -1,4 +1,4 @@ -; RUN: llc < %s -mtriple=arm-apple-darwin -mcpu=cortex-a9 | FileCheck %s +; RUN: llc < %s -mtriple=arm-apple-ios -mcpu=cortex-a9 | FileCheck %s ; rdar://8402126 ; Make sure if-converter is not predicating vldmia and ldmia. These are ; micro-coded and would have long issue latency even if predicated on Modified: llvm/trunk/test/CodeGen/ARM/ifcvt5.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/ifcvt5.ll?rev=147513&r1=147512&r2=147513&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/ARM/ifcvt5.ll (original) +++ llvm/trunk/test/CodeGen/ARM/ifcvt5.ll Tue Jan 3 19:55:04 2012 @@ -1,4 +1,4 @@ -; RUN: llc < %s -mtriple=armv7-apple-darwin | FileCheck %s +; RUN: llc < %s -mtriple=armv7-apple-ios | FileCheck %s @x = external global i32* ; [#uses=1] Modified: llvm/trunk/test/CodeGen/ARM/ifcvt6.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/ifcvt6.ll?rev=147513&r1=147512&r2=147513&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/ARM/ifcvt6.ll (original) +++ llvm/trunk/test/CodeGen/ARM/ifcvt6.ll Tue Jan 3 19:55:04 2012 @@ -1,4 +1,4 @@ -; RUN: llc < %s -mtriple=armv7-apple-darwin | FileCheck %s +; RUN: llc < %s -mtriple=armv7-apple-ios | FileCheck %s define void @foo(i32 %X, i32 %Y) { entry: Modified: llvm/trunk/test/CodeGen/ARM/insn-sched1.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/insn-sched1.ll?rev=147513&r1=147512&r2=147513&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/ARM/insn-sched1.ll (original) +++ llvm/trunk/test/CodeGen/ARM/insn-sched1.ll Tue Jan 3 19:55:04 2012 @@ -1,5 +1,5 @@ ; RUN: llc < %s -march=arm -mattr=+v6 -; RUN: llc < %s -mtriple=arm-apple-darwin -mattr=+v6 |\ +; RUN: llc < %s -mtriple=arm-apple-ios -mattr=+v6 |\ ; RUN: grep mov | count 3 define i32 @test(i32 %x) { Modified: llvm/trunk/test/CodeGen/ARM/lsr-unfolded-offset.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/lsr-unfolded-offset.ll?rev=147513&r1=147512&r2=147513&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/ARM/lsr-unfolded-offset.ll (original) +++ llvm/trunk/test/CodeGen/ARM/lsr-unfolded-offset.ll Tue Jan 3 19:55:04 2012 @@ -12,7 +12,7 @@ ; CHECK: add target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:32-f32:32:32-f64:32:32-v64:32:64-v128:32:128-a0:0:32-n32" -target triple = "thumbv7-apple-macosx10.7.0" +target triple = "thumbv7-apple-ios" %struct.partition_entry = type { i32, i32, i64, i64 } Modified: llvm/trunk/test/CodeGen/Thumb/large-stack.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb/large-stack.ll?rev=147513&r1=147512&r2=147513&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/Thumb/large-stack.ll (original) +++ llvm/trunk/test/CodeGen/Thumb/large-stack.ll Tue Jan 3 19:55:04 2012 @@ -1,4 +1,4 @@ -; RUN: llc < %s -mtriple=thumb-apple-darwin | FileCheck %s +; RUN: llc < %s -mtriple=thumb-apple-ios | FileCheck %s define void @test1() { ; CHECK: test1: Modified: llvm/trunk/test/CodeGen/Thumb2/2010-11-22-EpilogueBug.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb2/2010-11-22-EpilogueBug.ll?rev=147513&r1=147512&r2=147513&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/Thumb2/2010-11-22-EpilogueBug.ll (original) +++ llvm/trunk/test/CodeGen/Thumb2/2010-11-22-EpilogueBug.ll Tue Jan 3 19:55:04 2012 @@ -1,5 +1,5 @@ ; rdar://8465407 -; RUN: llc < %s -mtriple=thumbv7-apple-darwin | FileCheck %s +; RUN: llc < %s -mtriple=thumbv7-apple-ios | FileCheck %s %struct.buf = type opaque Modified: llvm/trunk/test/CodeGen/Thumb2/thumb2-ifcvt2.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb2/thumb2-ifcvt2.ll?rev=147513&r1=147512&r2=147513&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/Thumb2/thumb2-ifcvt2.ll (original) +++ llvm/trunk/test/CodeGen/Thumb2/thumb2-ifcvt2.ll Tue Jan 3 19:55:04 2012 @@ -1,4 +1,4 @@ -; RUN: llc < %s -mtriple=thumbv7-apple-darwin | FileCheck %s +; RUN: llc < %s -mtriple=thumbv7-apple-ios | FileCheck %s define void @foo(i32 %X, i32 %Y) { entry: Modified: llvm/trunk/test/CodeGen/Thumb2/thumb2-ldm.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb2/thumb2-ldm.ll?rev=147513&r1=147512&r2=147513&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/Thumb2/thumb2-ldm.ll (original) +++ llvm/trunk/test/CodeGen/Thumb2/thumb2-ldm.ll Tue Jan 3 19:55:04 2012 @@ -1,4 +1,4 @@ -; RUN: llc < %s -mtriple=thumbv7-apple-darwin -mattr=+thumb2 | FileCheck %s +; RUN: llc < %s -mtriple=thumbv7-apple-ios -mattr=+thumb2 | FileCheck %s @X = external global [0 x i32] ; <[0 x i32]*> [#uses=5] From kcc at google.com Tue Jan 3 20:08:46 2012 From: kcc at google.com (Kostya Serebryany) Date: Wed, 04 Jan 2012 02:08:46 -0000 Subject: [llvm-commits] [compiler-rt] r147514 - /compiler-rt/trunk/lib/asan/tests/asan_test.cc Message-ID: <20120104020846.CCF8C2A6C12C@llvm.org> Author: kcc Date: Tue Jan 3 20:08:46 2012 New Revision: 147514 URL: http://llvm.org/viewvc/llvm-project?rev=147514&view=rev Log: [asan] remove objdump-based tests in favour of much simpler LLVM-ish tests Modified: compiler-rt/trunk/lib/asan/tests/asan_test.cc Modified: compiler-rt/trunk/lib/asan/tests/asan_test.cc URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/lib/asan/tests/asan_test.cc?rev=147514&r1=147513&r2=147514&view=diff ============================================================================== --- compiler-rt/trunk/lib/asan/tests/asan_test.cc (original) +++ compiler-rt/trunk/lib/asan/tests/asan_test.cc Tue Jan 3 20:08:46 2012 @@ -61,89 +61,6 @@ static uint32_t global_seed = 0; -class ObjdumpOfMyself { - public: - explicit ObjdumpOfMyself(const string &binary) { - is_correct = true; - string objdump_name = APPLE ? "gobjdump" : "objdump"; - string prog = objdump_name + " -d " + binary; - // TODO(glider): popen() succeeds even if the file does not exist. - FILE *pipe = popen(prog.c_str(), "r"); - string objdump; - if (pipe) { - const int kBuffSize = 4096; - char buff[kBuffSize+1]; - int read_bytes; - while ((read_bytes = fread(buff, 1, kBuffSize, pipe)) > 0) { - buff[read_bytes] = 0; - objdump.append(buff); - } - pclose(pipe); - } else { - is_correct = false; - } - // cut the objdump into functions - string fn, next_fn; - size_t next_start; - for (size_t start = fn_start(objdump, 0, &fn); - start != string::npos; - start = next_start, fn = next_fn) { - next_start = fn_start(objdump, start, &next_fn); - // fprintf(stderr, "start: %d next_start = %d fn: %s\n", - // (int)start, (int)next_start, fn.c_str()); - // Mac OS adds the "_" prefix to function names. - if (fn.find(APPLE ? "_Disasm" : "Disasm") == string::npos) { - continue; - } - string fn_body = objdump.substr(start, next_start - start); - // fprintf(stderr, "%s:\n%s", fn.c_str(), fn_body.c_str()); - functions_[fn] = fn_body; - } - } - - string &GetFuncDisasm(const string &fn) { - return functions_[fn]; - } - - int CountInsnInFunc(const string &fn, const vector &insns) { - // Mac OS adds the "_" prefix to function names. - string fn_ref = APPLE ? "_" + fn : fn; - const string &disasm = GetFuncDisasm(fn_ref); - if (disasm.empty()) return -1; - size_t counter = 0; - for (size_t i = 0; i < insns.size(); i++) { - size_t pos = 0; - while ((pos = disasm.find(insns[i], pos)) != string::npos) { - counter++; - pos++; - } - } - return counter; - } - - bool IsCorrect() { return is_correct; } - - private: - size_t fn_start(const string &objdump, size_t start_pos, string *fn) { - size_t pos = objdump.find(">:\n", start_pos); - if (pos == string::npos) - return string::npos; - size_t beg = pos; - while (beg > 0 && objdump[beg - 1] != '<') - beg--; - *fn = objdump.substr(beg, pos - beg); - return pos + 3; - } - - map functions_; - bool is_correct; -}; - -static ObjdumpOfMyself *objdump_of_myself() { - static ObjdumpOfMyself *o = new ObjdumpOfMyself(progname); - return o; -} - const size_t kLargeMalloc = 1 << 24; template @@ -1561,76 +1478,6 @@ free(strdup(Ident("123"))); } -TEST(AddressSanitizer, ObjdumpTest) { - ObjdumpOfMyself *o = objdump_of_myself(); - EXPECT_TRUE(o->IsCorrect()); -} - -extern "C" { -__attribute__((noinline)) -static void DisasmSimple() { - Ident(0); -} - -__attribute__((noinline)) -static void DisasmParamWrite(int *a) { - *a = 1; -} - -__attribute__((noinline)) -static void DisasmParamInc(int *a) { - (*a)++; -} - -__attribute__((noinline)) -static void DisasmParamReadIfWrite(int *a) { - if (*a) - *a = 1; -} - -__attribute__((noinline)) -static int DisasmParamIfReadWrite(int *a, int cond) { - int res = 0; - if (cond) - res = *a; - *a = 0; - return res; -} - -static int GLOBAL; - -__attribute__((noinline)) -static void DisasmWriteGlob() { - GLOBAL = 1; -} -} // extern "C" - -TEST(AddressSanitizer, DisasmTest) { - int a; - DisasmSimple(); - DisasmParamWrite(&a); - DisasmParamInc(&a); - Ident(DisasmWriteGlob)(); - DisasmParamReadIfWrite(&a); - - a = 7; - EXPECT_EQ(7, DisasmParamIfReadWrite(&a, Ident(1))); - EXPECT_EQ(0, a); - - ObjdumpOfMyself *o = objdump_of_myself(); - vector insns; - insns.push_back("ud2"); - insns.push_back("__asan_report_"); - EXPECT_EQ(0, o->CountInsnInFunc("DisasmSimple", insns)); - EXPECT_EQ(1, o->CountInsnInFunc("DisasmParamWrite", insns)); - EXPECT_EQ(1, o->CountInsnInFunc("DisasmParamInc", insns)); - EXPECT_EQ(0, o->CountInsnInFunc("DisasmWriteGlob", insns)); - - // TODO(kcc): implement these (needs just one __asan_report). - EXPECT_EQ(2, o->CountInsnInFunc("DisasmParamReadIfWrite", insns)); - EXPECT_EQ(2, o->CountInsnInFunc("DisasmParamIfReadWrite", insns)); -} - // Currently we create and poison redzone at right of global variables. char glob5[5]; static char static110[110]; From ahatanaka at mips.com Tue Jan 3 20:45:01 2012 From: ahatanaka at mips.com (Akira Hatanaka) Date: Wed, 04 Jan 2012 02:45:01 -0000 Subject: [llvm-commits] [llvm] r147516 - in /llvm/trunk: lib/Target/Mips/MipsISelLowering.cpp test/CodeGen/Mips/2008-08-01-AsmInline.ll test/CodeGen/Mips/inlineasm64.ll Message-ID: <20120104024501.749E32A6C12C@llvm.org> Author: ahatanak Date: Tue Jan 3 20:45:01 2012 New Revision: 147516 URL: http://llvm.org/viewvc/llvm-project?rev=147516&view=rev Log: Have getRegForInlineAsmConstraint return the correct register class when target is Mips64. Added: llvm/trunk/test/CodeGen/Mips/inlineasm64.ll Modified: llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp llvm/trunk/test/CodeGen/Mips/2008-08-01-AsmInline.ll Modified: llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp?rev=147516&r1=147515&r2=147516&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp (original) +++ llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp Tue Jan 3 20:45:01 2012 @@ -2871,14 +2871,19 @@ case 'd': // Address register. Same as 'r' unless generating MIPS16 code. case 'y': // Same as 'r'. Exists for compatibility. case 'r': - return std::make_pair(0U, Mips::CPURegsRegisterClass); + if (VT == MVT::i32) + return std::make_pair(0U, Mips::CPURegsRegisterClass); + assert(VT == MVT::i64 && "Unexpected type."); + return std::make_pair(0U, Mips::CPU64RegsRegisterClass); case 'f': if (VT == MVT::f32) return std::make_pair(0U, Mips::FGR32RegisterClass); - if (VT == MVT::f64) - if ((!Subtarget->isSingleFloat()) && (!Subtarget->isFP64bit())) + if ((VT == MVT::f64) && (!Subtarget->isSingleFloat())) { + if (Subtarget->isFP64bit()) + return std::make_pair(0U, Mips::FGR64RegisterClass); + else return std::make_pair(0U, Mips::AFGR64RegisterClass); - break; + } } } return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT); Modified: llvm/trunk/test/CodeGen/Mips/2008-08-01-AsmInline.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/2008-08-01-AsmInline.ll?rev=147516&r1=147515&r2=147516&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/Mips/2008-08-01-AsmInline.ll (original) +++ llvm/trunk/test/CodeGen/Mips/2008-08-01-AsmInline.ll Tue Jan 3 20:45:01 2012 @@ -1,4 +1,5 @@ ; RUN: llc -march=mips < %s | FileCheck %s +; RUN: llc -march=mips64el -mcpu=mips64r2 -mattr=n64 < %s | FileCheck %s %struct.DWstruct = type { i32, i32 } @@ -13,3 +14,40 @@ %res = add i32 %asmresult, %asmresult1 ret i32 %res } + + at gi2 = external global i32 + at gi1 = external global i32 + at gi0 = external global i32 + at gf0 = external global float + at gf1 = external global float + at gd0 = external global double + at gd1 = external global double + +define void @foo0() nounwind { +entry: +; CHECK: addu + %0 = load i32* @gi1, align 4 + %1 = load i32* @gi0, align 4 + %2 = tail call i32 asm "addu $0, $1, $2", "=r,r,r"(i32 %0, i32 %1) nounwind + store i32 %2, i32* @gi2, align 4 + ret void +} + +define void @foo2() nounwind { +entry: +; CHECK: neg.s + %0 = load float* @gf1, align 4 + %1 = tail call float asm "neg.s $0, $1", "=f,f"(float %0) nounwind + store float %1, float* @gf0, align 4 + ret void +} + +define void @foo3() nounwind { +entry: +; CHECK: neg.d + %0 = load double* @gd1, align 8 + %1 = tail call double asm "neg.d $0, $1", "=f,f"(double %0) nounwind + store double %1, double* @gd0, align 8 + ret void +} + Added: llvm/trunk/test/CodeGen/Mips/inlineasm64.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/inlineasm64.ll?rev=147516&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/Mips/inlineasm64.ll (added) +++ llvm/trunk/test/CodeGen/Mips/inlineasm64.ll Tue Jan 3 20:45:01 2012 @@ -0,0 +1,17 @@ +; RUN: llc -march=mips64el -mcpu=mips64r2 -mattr=n64 < %s | FileCheck %s + + at gl2 = external global i64 + at gl1 = external global i64 + at gl0 = external global i64 + +define void @foo1() nounwind { +entry: +; CHECK: foo1 +; CHECK: daddu + %0 = load i64* @gl1, align 8 + %1 = load i64* @gl0, align 8 + %2 = tail call i64 asm "daddu $0, $1, $2", "=r,r,r"(i64 %0, i64 %1) nounwind + store i64 %2, i64* @gl2, align 8 + ret void +} + From rafael.espindola at gmail.com Tue Jan 3 20:56:27 2012 From: rafael.espindola at gmail.com (=?ISO-8859-1?Q?Rafael_=C1vila_de_Esp=EDndola?=) Date: Tue, 03 Jan 2012 21:56:27 -0500 Subject: [llvm-commits] [pr11697][patch] Implement linking of symbols with different visibilities Message-ID: <4F03BFDB.1000504@gmail.com> The LLVM IL linker currently refuses to link symbols if the visibilities are different. This causes problems when using LTO and -fvisibility-inlines-hidden. This patch implements the rules of the System V Application Binary Interface (http://sco.com/developers/gabi/2009-10-26/ch4.symtab.html), so that we get consistent behavior with and without LTO. This does mean that when using -fvisibility-inlines-hidden, if we have an explicit template instantiation definition in a library(.so), then every use of an inline method of that class must see an explicit template instantiation declaration or we can end up with a hidden symbol in the library. I think this is OK because: * That is already the case when *not* doing LTO and using gold (the gnu bfd linker is not conformant with the spec). * -fvisibility-inlines-hidden already breaks the standard a bit (pointer comparisons), so saying that it requires explicit template instantiation declaratios when a definition is used is not too bad. * As Eli pointed out on IRC, LTO supersedes -fvisibility-inlines-hidden. At the IL level we differentiate weak_odr and linkonce_odr. All that we need is for the link to still work if someone ends up using both LTO and -fvisibility-inlines-hidden. Thanks a lot to Eli and Ian for the comments and pointers. Cheers, Rafael -------------- next part -------------- An embedded and charset-unspecified text was scrubbed... Name: pr11697.patch Url: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20120103/7bf0e9e9/attachment.pl From ahatanaka at mips.com Tue Jan 3 21:02:47 2012 From: ahatanaka at mips.com (Akira Hatanaka) Date: Wed, 04 Jan 2012 03:02:47 -0000 Subject: [llvm-commits] [llvm] r147518 - in /llvm/trunk/lib/Target/Mips: Mips64InstrInfo.td MipsInstrInfo.td Message-ID: <20120104030248.02EE02A6C12C@llvm.org> Author: ahatanak Date: Tue Jan 3 21:02:47 2012 New Revision: 147518 URL: http://llvm.org/viewvc/llvm-project?rev=147518&view=rev Log: - Define base classes for Jump-and-link instructions and make 32-bit and 64-bit versions derive from them. - JALR64 is not needed since N64 does not emit jal. - Add template parameter to BranchLink that sets the rt field. - Fix the set of temporary registers for O32 and N64. Modified: llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td llvm/trunk/lib/Target/Mips/MipsInstrInfo.td Modified: llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td?rev=147518&r1=147517&r2=147518&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td (original) +++ llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td Tue Jan 3 21:02:47 2012 @@ -54,30 +54,6 @@ shift_rotate_imm; -// Jump and Link (Call) -let isCall=1, hasDelaySlot=1, - // All calls clobber the non-callee saved registers... - Defs = [AT, V0, V1, A0, A1, A2, A3, T0, T1, T2, T3, T4, T5, T6, T7, T8, T9, - K0, K1, D0, D1, D2, D3, D4, D5, D6, D7, D8, D9], Uses = [GP] in { - class JumpLink64 op, string instr_asm>: - FJ; - - class JumpLinkReg64 op, bits<6> func, string instr_asm>: - FR { - let rt = 0; - let rd = 31; - let shamt = 0; - } - - class BranchLink64: - FI<0x1, (outs), (ins CPU64Regs:$rs, brtarget:$imm16, variable_ops), - !strconcat(instr_asm, "\t$rs, $imm16"), [], IIBranch>; -} - // Mul, Div class Mult64 func, string instr_asm, InstrItinClass itin>: Mult; @@ -175,8 +151,6 @@ /// Jump and Branch Instructions def JR64 : JumpFR<0x00, 0x08, "jr", CPU64Regs>; -def JAL64 : JumpLink64<0x03, "jal">; -def JALR64 : JumpLinkReg64<0x00, 0x09, "jalr">; def BEQ64 : CBranch<0x04, "beq", seteq, CPU64Regs>; def BNE64 : CBranch<0x05, "bne", setne, CPU64Regs>; def BGEZ64 : CBranchZero<0x01, 1, "bgez", setge, CPU64Regs>; @@ -184,6 +158,15 @@ def BLEZ64 : CBranchZero<0x07, 0, "blez", setle, CPU64Regs>; def BLTZ64 : CBranchZero<0x01, 0, "bltz", setlt, CPU64Regs>; +// NOTE: These registers are N64's temporary registers. N32 has a different +// set of temporary registers. +let Defs = [AT_64, V0_64, V1_64, A0_64, A1_64, A2_64, A3_64, T0_64, T1_64, + T2_64, T3_64, T4_64, T5_64, T6_64, T7_64, T8_64, T9_64, K0_64, + K1_64, D0_64, D1_64, D2_64, D3_64, D4_64, D5_64, D6_64, D7_64, + D8_64, D9_64, D10_64, D11_64, D12_64, D13_64, D14_64, D15_64, + D16_64, D17_64, D18_64, D19_64, D20_64, D21_64, D22_64, D23_64] in +def JALR64 : JumpLinkReg<0x00, 0x09, "jalr", CPU64Regs>; + /// Multiply and Divide Instructions. def DMULT : Mult64<0x1c, "dmult", IIImul>; def DMULTu : Mult64<0x1d, "dmultu", IIImul>; Modified: llvm/trunk/lib/Target/Mips/MipsInstrInfo.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsInstrInfo.td?rev=147518&r1=147517&r2=147518&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/MipsInstrInfo.td (original) +++ llvm/trunk/lib/Target/Mips/MipsInstrInfo.td Tue Jan 3 21:02:47 2012 @@ -522,26 +522,26 @@ } // Jump and Link (Call) -let isCall=1, hasDelaySlot=1, - // All calls clobber the non-callee saved registers... - Defs = [AT, V0, V1, A0, A1, A2, A3, T0, T1, T2, T3, T4, T5, T6, T7, T8, T9, - K0, K1, D0, D1, D2, D3, D4, D5, D6, D7, D8, D9], Uses = [GP] in { +let isCall=1, hasDelaySlot=1 in { class JumpLink op, string instr_asm>: FJ; - class JumpLinkReg op, bits<6> func, string instr_asm>: - FR { + class JumpLinkReg op, bits<6> func, string instr_asm, + RegisterClass RC>: + FR { let rt = 0; let rd = 31; let shamt = 0; } - class BranchLink: - FI<0x1, (outs), (ins CPURegs:$rs, brtarget:$imm16, variable_ops), - !strconcat(instr_asm, "\t$rs, $imm16"), [], IIBranch>; + class BranchLink _rt, RegisterClass RC>: + FI<0x1, (outs), (ins RC:$rs, brtarget:$imm16, variable_ops), + !strconcat(instr_asm, "\t$rs, $imm16"), [], IIBranch> { + let rt = _rt; + } } // Mul, Div @@ -855,8 +855,6 @@ /// Jump and Branch Instructions def J : JumpFJ<0x02, "j">; def JR : JumpFR<0x00, 0x08, "jr", CPURegs>; -def JAL : JumpLink<0x03, "jal">; -def JALR : JumpLinkReg<0x00, 0x09, "jalr">; def B : UncondBranch<0x04, "b">; def BEQ : CBranch<0x04, "beq", seteq, CPURegs>; def BNE : CBranch<0x05, "bne", setne, CPURegs>; @@ -865,10 +863,14 @@ def BLEZ : CBranchZero<0x06, 0, "blez", setle, CPURegs>; def BLTZ : CBranchZero<0x01, 0, "bltz", setlt, CPURegs>; -let rt=0x11 in - def BGEZAL : BranchLink<"bgezal">; -let rt=0x10 in - def BLTZAL : BranchLink<"bltzal">; +// All calls clobber the non-callee saved registers... +let Defs = [AT, V0, V1, A0, A1, A2, A3, T0, T1, T2, T3, T4, T5, T6, T7, T8, T9, + K0, K1, GP, D0, D1, D2, D3, D4, D5, D6, D7, D8, D9] in { + def JAL : JumpLink<0x03, "jal">; + def JALR : JumpLinkReg<0x00, 0x09, "jalr", CPURegs>; + def BGEZAL : BranchLink<"bgezal", 0x11, CPURegs>; + def BLTZAL : BranchLink<"bltzal", 0x10, CPURegs>; +} let isReturn=1, isTerminator=1, hasDelaySlot=1, isBarrier=1, hasCtrlDep=1, rd=0, rt=0, shamt=0 in From ahatanaka at mips.com Tue Jan 3 21:09:26 2012 From: ahatanaka at mips.com (Akira Hatanaka) Date: Wed, 04 Jan 2012 03:09:26 -0000 Subject: [llvm-commits] [llvm] r147519 - in /llvm/trunk/lib/Target/Mips: Mips64InstrInfo.td MipsInstrInfo.td Message-ID: <20120104030926.776512A6C12C@llvm.org> Author: ahatanak Date: Tue Jan 3 21:09:26 2012 New Revision: 147519 URL: http://llvm.org/viewvc/llvm-project?rev=147519&view=rev Log: Rename immLUiOpnd. Modified: llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td llvm/trunk/lib/Target/Mips/MipsInstrInfo.td Modified: llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td?rev=147519&r1=147518&r2=147519&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td (original) +++ llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td Tue Jan 3 21:09:26 2012 @@ -214,7 +214,7 @@ (DADDiu ZERO_64, imm:$in)>; def : Pat<(i64 immZExt16:$in), (ORi64 ZERO_64, imm:$in)>; -def : Pat<(i64 immLUiOpnd:$in), +def : Pat<(i64 immLow16Zero:$in), (LUi64 (HI16 imm:$in))>; // 32-bit immediates Modified: llvm/trunk/lib/Target/Mips/MipsInstrInfo.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsInstrInfo.td?rev=147519&r1=147518&r2=147519&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/MipsInstrInfo.td (original) +++ llvm/trunk/lib/Target/Mips/MipsInstrInfo.td Tue Jan 3 21:09:26 2012 @@ -220,7 +220,7 @@ }], LO16>; // Immediate can be loaded with LUi (32-bit int with lower 16-bit cleared). -def immLUiOpnd : PatLeaf<(imm), [{ +def immLow16Zero : PatLeaf<(imm), [{ int64_t Val = N->getSExtValue(); return isInt<32>(Val) && !(Val & 0xffff); }]>; @@ -940,7 +940,7 @@ (ADDiu ZERO, imm:$in)>; def : Pat<(i32 immZExt16:$in), (ORi ZERO, imm:$in)>; -def : Pat<(i32 immLUiOpnd:$in), +def : Pat<(i32 immLow16Zero:$in), (LUi (HI16 imm:$in))>; // Arbitrary immediates From geek4civic at gmail.com Tue Jan 3 21:52:23 2012 From: geek4civic at gmail.com (NAKAMURA Takumi) Date: Wed, 04 Jan 2012 03:52:23 -0000 Subject: [llvm-commits] [llvm] r147521 - /llvm/trunk/test/CodeGen/X86/jump_sign.ll Message-ID: <20120104035223.E05212A6C12C@llvm.org> Author: chapuni Date: Tue Jan 3 21:52:23 2012 New Revision: 147521 URL: http://llvm.org/viewvc/llvm-project?rev=147521&view=rev Log: test/CodeGen/X86/jump_sign.ll: Add -mcpu=pentiumpro for non-x86 hosts. It uses "cmov". Modified: llvm/trunk/test/CodeGen/X86/jump_sign.ll Modified: llvm/trunk/test/CodeGen/X86/jump_sign.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/jump_sign.ll?rev=147521&r1=147520&r2=147521&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/X86/jump_sign.ll (original) +++ llvm/trunk/test/CodeGen/X86/jump_sign.ll Tue Jan 3 21:52:23 2012 @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=x86 | FileCheck %s +; RUN: llc < %s -march=x86 -mcpu=pentiumpro | FileCheck %s define i32 @f(i32 %X) { entry: From nicholas at mxc.ca Tue Jan 3 23:15:16 2012 From: nicholas at mxc.ca (Nick Lewycky) Date: Tue, 03 Jan 2012 21:15:16 -0800 Subject: [llvm-commits] [llvm] r147391 - in /llvm/trunk: lib/Transforms/InstCombine/InstCombineShifts.cpp test/Transforms/InstCombine/shift.ll In-Reply-To: <4F007682.9020905@free.fr> References: <20111231213023.1E8B72A6C12C@llvm.org> <4F006C9A.4080709@free.fr> <4F0075F9.5080709@mxc.ca> <4F007682.9020905@free.fr> Message-ID: <4F03E064.8050602@mxc.ca> On 01/01/2012 07:06 AM, Duncan Sands wrote: > Hi Nick, > >>>> @@ -603,9 +602,16 @@ >>>> // (X>>? C1)<< C2 --> X>>? (C1-C2)& (-1<< C2) >>>> if (I.getOpcode() == Instruction::Shl&& >>>> ShiftOp->getOpcode() != Instruction::Shl) { >>>> - Value *Shift = Builder->CreateBinOp(ShiftOp->getOpcode(), X, >>>> - ConstantInt::get(Ty, ShiftDiff)); >>>> - >>>> + ConstantInt *ShiftDiffCst = ConstantInt::get(Ty, ShiftDiff); >>>> + if (ShiftOp->isExact()) { >>>> + // (X>>?exact C1)<< C2 --> X>>?exact (C1-C2) >>> >>> what happens if C2 is bigger than C1? >> >> We won't reach here. It extracts C1 and C2 into ShiftAmt1 and >> ShiftAmt2 and does >> if (ShiftAmt1 == ShiftAmt2) { ... } else if (ShiftAmt1 < ShiftAmt2) { >> ... } else >> { our transform here }. > > OK, thanks. However if C2 is bigger than C1 then, thanks to the exact > flag, you > can just turn it into a left shift (without an "and"). Likewise, for C1 > == C2 > the pair of shifts becomes a no-op. But maybe those are handled already? We handle the exact bit in the C1 == C2 case already. When C2 > C1, you can't use exact to remove the 'and' operation the shl is adding more zero bits than the shr guaranteed would be there, with or without exact. There may be something more you can do with nuw/nsw on the 'shl', but I couldn't see anything obvious. Nick From baldrick at free.fr Wed Jan 4 01:51:13 2012 From: baldrick at free.fr (Duncan Sands) Date: Wed, 04 Jan 2012 08:51:13 +0100 Subject: [llvm-commits] [llvm] r147391 - in /llvm/trunk: lib/Transforms/InstCombine/InstCombineShifts.cpp test/Transforms/InstCombine/shift.ll In-Reply-To: <4F03E064.8050602@mxc.ca> References: <20111231213023.1E8B72A6C12C@llvm.org> <4F006C9A.4080709@free.fr> <4F0075F9.5080709@mxc.ca> <4F007682.9020905@free.fr> <4F03E064.8050602@mxc.ca> Message-ID: <4F0404F1.1060906@free.fr> Hi Nick, >>>>> @@ -603,9 +602,16 @@ >>>>> // (X>>? C1)<< C2 --> X>>? (C1-C2)& (-1<< C2) >>>>> if (I.getOpcode() == Instruction::Shl&& >>>>> ShiftOp->getOpcode() != Instruction::Shl) { >>>>> - Value *Shift = Builder->CreateBinOp(ShiftOp->getOpcode(), X, >>>>> - ConstantInt::get(Ty, ShiftDiff)); >>>>> - >>>>> + ConstantInt *ShiftDiffCst = ConstantInt::get(Ty, ShiftDiff); >>>>> + if (ShiftOp->isExact()) { >>>>> + // (X>>?exact C1)<< C2 --> X>>?exact (C1-C2) >>>> >>>> what happens if C2 is bigger than C1? >>> >>> We won't reach here. It extracts C1 and C2 into ShiftAmt1 and >>> ShiftAmt2 and does >>> if (ShiftAmt1 == ShiftAmt2) { ... } else if (ShiftAmt1 < ShiftAmt2) { >>> ... } else >>> { our transform here }. >> >> OK, thanks. However if C2 is bigger than C1 then, thanks to the exact >> flag, you >> can just turn it into a left shift (without an "and"). Likewise, for C1 >> == C2 >> the pair of shifts becomes a no-op. But maybe those are handled already? > > We handle the exact bit in the C1 == C2 case already. When C2 > C1, you can't > use exact to remove the 'and' operation the shl is adding more zero bits than > the shr guaranteed would be there, with or without exact. not sure what you are saying here. As far as I can see (X >>exact 1) << 3 is the same thing as X << 2. The point of an exact shift is that it is invertible: (X >>exact N) << N equals X. Thus, writing (X >>exact 1) << 3 as ((X >>exact 1) << 1) << 2, you get that it simplifies to X << 2 by the above. No "and" required. Am I missing something? Ciao, Duncan. There may be something > more you can do with nuw/nsw on the 'shl', but I couldn't see anything obvious. From nicholas at mxc.ca Wed Jan 4 02:02:48 2012 From: nicholas at mxc.ca (Nick Lewycky) Date: Wed, 04 Jan 2012 00:02:48 -0800 Subject: [llvm-commits] [llvm] r147391 - in /llvm/trunk: lib/Transforms/InstCombine/InstCombineShifts.cpp test/Transforms/InstCombine/shift.ll In-Reply-To: <4F0404F1.1060906@free.fr> References: <20111231213023.1E8B72A6C12C@llvm.org> <4F006C9A.4080709@free.fr> <4F0075F9.5080709@mxc.ca> <4F007682.9020905@free.fr> <4F03E064.8050602@mxc.ca> <4F0404F1.1060906@free.fr> Message-ID: <4F0407A8.2030803@mxc.ca> On 01/03/2012 11:51 PM, Duncan Sands wrote: > Hi Nick, > >>>>>> @@ -603,9 +602,16 @@ >>>>>> // (X>>? C1)<< C2 --> X>>? (C1-C2)& (-1<< C2) >>>>>> if (I.getOpcode() == Instruction::Shl&& >>>>>> ShiftOp->getOpcode() != Instruction::Shl) { >>>>>> - Value *Shift = Builder->CreateBinOp(ShiftOp->getOpcode(), X, >>>>>> - ConstantInt::get(Ty, ShiftDiff)); >>>>>> - >>>>>> + ConstantInt *ShiftDiffCst = ConstantInt::get(Ty, ShiftDiff); >>>>>> + if (ShiftOp->isExact()) { >>>>>> + // (X>>?exact C1)<< C2 --> X>>?exact (C1-C2) >>>>> >>>>> what happens if C2 is bigger than C1? >>>> >>>> We won't reach here. It extracts C1 and C2 into ShiftAmt1 and >>>> ShiftAmt2 and does >>>> if (ShiftAmt1 == ShiftAmt2) { ... } else if (ShiftAmt1 < ShiftAmt2) { >>>> ... } else >>>> { our transform here }. >>> >>> OK, thanks. However if C2 is bigger than C1 then, thanks to the exact >>> flag, you >>> can just turn it into a left shift (without an "and"). Likewise, for C1 >>> == C2 >>> the pair of shifts becomes a no-op. But maybe those are handled already? >> >> We handle the exact bit in the C1 == C2 case already. When C2 > C1, >> you can't >> use exact to remove the 'and' operation the shl is adding more zero >> bits than >> the shr guaranteed would be there, with or without exact. > > not sure what you are saying here. As far as I can see (X >>exact 1) << > 3 is > the same thing as X << 2. The point of an exact shift is that it is > invertible: > (X >>exact N) << N equals X. Thus, writing (X >>exact 1) << 3 as > ((X >>exact 1) << 1) << 2, you get that it simplifies to X << 2 by the > above. > No "and" required. Am I missing something? Nope, you're right. (I confused myself, thinking that the 'and' was still necessary to clear the bottom bits, but that we should shrink the size of the and constant but not remove it. Of course, a shift-left always fills in zeros.) Patch on the way. :) Nick > > Ciao, Duncan. > > There may be something >> more you can do with nuw/nsw on the 'shl', but I couldn't see anything >> obvious. > > > From craig.topper at gmail.com Wed Jan 4 02:07:44 2012 From: craig.topper at gmail.com (Craig Topper) Date: Wed, 04 Jan 2012 08:07:44 -0000 Subject: [llvm-commits] [llvm] r147525 - /llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Message-ID: <20120104080744.4B8652A6C12C@llvm.org> Author: ctopper Date: Wed Jan 4 02:07:43 2012 New Revision: 147525 URL: http://llvm.org/viewvc/llvm-project?rev=147525&view=rev Log: Implement VECTOR_SHUFFLE canonicalizations during DAG combine. Modified: llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Modified: llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp?rev=147525&r1=147524&r2=147525&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Wed Jan 4 02:07:43 2012 @@ -7254,15 +7254,63 @@ unsigned NumElts = VT.getVectorNumElements(); SDValue N0 = N->getOperand(0); + SDValue N1 = N->getOperand(1); assert(N0.getValueType().getVectorNumElements() == NumElts && "Vector shuffle must be normalized in DAG"); - // FIXME: implement canonicalizations from DAG.getVectorShuffle() + // Canonicalize shuffle undef, undef -> undef + if (N0.getOpcode() == ISD::UNDEF && N1.getOpcode() == ISD::UNDEF) + return DAG.getUNDEF(VT); + + ShuffleVectorSDNode *SVN = cast(N); + + // Canonicalize shuffle v, v -> v, undef + if (N0 == N1) { + SmallVector NewMask; + for (unsigned i = 0; i != NumElts; ++i) { + int Idx = SVN->getMaskElt(i); + if (Idx >= (int)NumElts) Idx -= NumElts; + NewMask.push_back(Idx); + } + return DAG.getVectorShuffle(VT, N->getDebugLoc(), N0, DAG.getUNDEF(VT), + &NewMask[0]); + } + + // Canonicalize shuffle undef, v -> v, undef. Commute the shuffle mask. + if (N0.getOpcode() == ISD::UNDEF) { + SmallVector NewMask; + for (unsigned i = 0; i != NumElts; ++i) { + int Idx = SVN->getMaskElt(i); + if (Idx < 0) + NewMask.push_back(Idx); + else if (Idx < (int)NumElts) + NewMask.push_back(Idx + NumElts); + else + NewMask.push_back(Idx - NumElts); + } + return DAG.getVectorShuffle(VT, N->getDebugLoc(), N1, DAG.getUNDEF(VT), + &NewMask[0]); + } + + // Remove references to rhs if it is undef + if (N1.getOpcode() == ISD::UNDEF) { + bool Changed = false; + SmallVector NewMask; + for (unsigned i = 0; i != NumElts; ++i) { + int Idx = SVN->getMaskElt(i); + if (Idx >= (int)NumElts) { + Idx = -1; + Changed = true; + } + NewMask.push_back(Idx); + } + if (Changed) + return DAG.getVectorShuffle(VT, N->getDebugLoc(), N0, N1, &NewMask[0]); + } // If it is a splat, check if the argument vector is another splat or a // build_vector with all scalar elements the same. - ShuffleVectorSDNode *SVN = cast(N); if (SVN->isSplat() && SVN->getSplatIndex() < (int)NumElts) { SDNode *V = N0.getNode(); From STPWORLD at narod.ru Wed Jan 4 02:16:08 2012 From: STPWORLD at narod.ru (Stepan Dyatkovskiy) Date: Wed, 04 Jan 2012 12:16:08 +0400 Subject: [llvm-commits] [LLVM, opt, LoopUnswitch] Compile-time improvements. In-Reply-To: <200741325616644@web103.yandex.ru> References: <4EFDAB2C.5000606@narod.ru> <640641325498007@web20.yandex.ru> <200741325616644@web103.yandex.ru> Message-ID: <885601325664968@web89.yandex.ru> Ping. -Stepan 03.01.2012, 22:50, "Stepan Dyatkovskiy" : > Ping. > -Stepan. > > 02.01.2012, 13:53, "Stepan Dyatkovskiy" : > >> ?ping. >> ?-Stepan. >> >> ?30.12.2011, 16:14, "Stepan Dyatkovskiy" : >>> ??Hi. A made some fixes that improves compile-time: >>> >>> ??1. Size heuristics changed. Now we calculate number of unswitching >>> ??branches only once per loop. >>> ??2. Some checks was moved from UnswitchIfProfitable to >>> ??processCurrentLoop, since it is not changed during processCurrentLoop >>> ??iteration. It allows decide to skip some loops at an early stage. >>> >>> ??I checked the compile-time on test >>> >>> ??MultiSource/Benchmarks/Prolangs-C++/shapes/shapes >>> ??(there was compile time regression after my previous patch). >>> >>> ??Relative to my previous patch the compile-time improved on ~8.5%. Relative >>> ??to old revisions (before r146578) the compile time is improved on ~2%. >>> >>> ??Please find the patch in attachment for review. >>> >>> ??-Stepan. >>> >>> ??_______________________________________________ >>> ??llvm-commits mailing list >>> ??llvm-commits at cs.uiuc.edu >>> ??http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From elena.demikhovsky at intel.com Wed Jan 4 02:50:10 2012 From: elena.demikhovsky at intel.com (Demikhovsky, Elena) Date: Wed, 4 Jan 2012 08:50:10 +0000 Subject: [llvm-commits] [llvm] r147308 - in /llvm/trunk: lib/Target/X86/X86ISelLowering.cpp test/CodeGen/X86/avx-shuffle.ll In-Reply-To: <1C6CDAB6-82FE-4107-A408-C874F50BF5EA@apple.com> References: <20111228081401.E07221BE003@llvm.org> <1C6CDAB6-82FE-4107-A408-C874F50BF5EA@apple.com> Message-ID: I fixed two bugs together because after I fixed VECTOR_SHUFFLE with MOVL mask the shuffle node was not lowered and it came to BUILD_VECTOR and failed there. The MOVL / MOVLP instructions work for 128-bit vectors. I'm running conformance tests on AVX and see that many shuffle cases generate wrong instruction set. I'm trying to fix one-by-one and I have several fixes if one fix causes fail in another place. - Elena -----Original Message----- From: Chad Rosier [mailto:mcrosier at apple.com] Sent: Wednesday, January 04, 2012 03:30 To: Demikhovsky, Elena Cc: llvm-commits at cs.uiuc.edu Subject: Re: [llvm-commits] [llvm] r147308 - in /llvm/trunk: lib/Target/X86/X86ISelLowering.cpp test/CodeGen/X86/avx-shuffle.ll Hi Elena, Just a few comments below. On Dec 28, 2011, at 12:14 AM, Elena Demikhovsky wrote: > Author: delena > Date: Wed Dec 28 02:14:01 2011 > New Revision: 147308 > > URL: http://llvm.org/viewvc/llvm-project?rev=147308&view=rev > Log: > Fixed a bug in LowerVECTOR_SHUFFLE and LowerBUILD_VECTOR. > Matching MOVLP mask for AVX (265-bit vectors) was wrong. > The failure was detected by conformance tests. As far as I can tell this patch is addressing two bugs, one in LowerBUILD_VECTOR and another with LowerVECTOR_SHUFFLE/MOVLP. These should really be fixed in two separate commits. > > Modified: > llvm/trunk/lib/Target/X86/X86ISelLowering.cpp > llvm/trunk/test/CodeGen/X86/avx-shuffle.ll > > Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=147308&r1=147307&r2=147308&view=diff > ============================================================================== > --- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original) > +++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Wed Dec 28 02:14:01 2011 > @@ -3448,6 +3448,11 @@ > /// isMOVLPMask - Return true if the specified VECTOR_SHUFFLE operand > /// specifies a shuffle of elements that is suitable for input to MOVLP{S|D}. > bool X86::isMOVLPMask(ShuffleVectorSDNode *N) { > + EVT VT = N->getValueType(0); > + > + if (VT.getSizeInBits() != 128) > + return false; > + I'm not sure I agree with the approach taken here... > unsigned NumElems = N->getValueType(0).getVectorNumElements(); > > if (NumElems != 2 && NumElems != 4) > @@ -3666,6 +3671,8 @@ > static bool isMOVLMask(const SmallVectorImpl &Mask, EVT VT) { > if (VT.getVectorElementType().getSizeInBits() < 32) > return false; > + if (VT.getSizeInBits() == 256) > + return false; ..and here. Aren't these functions behaving correctly? I believe the real problem is the code that is predicated upon these functions; they don't fully support codegen when AVX is enabled. And one moot point.. The conditional statements that checks the size of the vectors could be more consistent (i.e., both (VT.getSizeInBits != 128) or (VT.getSizeInBits != 128), but not a combination of the two). > int NumElts = VT.getVectorNumElements(); > > @@ -5158,16 +5165,30 @@ > return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item); > } else if (ExtVT == MVT::i32 || ExtVT == MVT::f32 || ExtVT == MVT::f64 || > (ExtVT == MVT::i64 && Subtarget->is64Bit())) { > + if (VT.getSizeInBits() == 256) { > + > + EVT VT128 = EVT::getVectorVT(*DAG.getContext(), ExtVT, NumElems / 2); > + Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT128, Item); > + SDValue ZeroVec = getZeroVector(VT, true, DAG, dl); > + return Insert128BitVector(ZeroVec, Item, DAG.getConstant(0, MVT::i32), > + DAG, dl); > + } > Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item); > // Turn it into a MOVL (i.e. movss, movsd, or movd) to a zero vector. > return getShuffleVectorZeroOrUndef(Item, 0, true,Subtarget->hasXMMInt(), > DAG); > } else if (ExtVT == MVT::i16 || ExtVT == MVT::i8) { > Item = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Item); > - unsigned NumBits = VT.getSizeInBits(); > - assert((NumBits == 128 || NumBits == 256) && > - "Expected an SSE or AVX value type!"); > - EVT MiddleVT = NumBits == 128 ? MVT::v4i32 : MVT::v8i32; > + if (VT.getSizeInBits() == 256) { > + > + EVT VT128 = EVT::getVectorVT(*DAG.getContext(), ExtVT, NumElems / 2); > + Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT128, Item); > + SDValue ZeroVec = getZeroVector(VT, true, DAG, dl); > + return Insert128BitVector(ZeroVec, Item, DAG.getConstant(0, MVT::i32), > + DAG, dl); > + } > + assert (VT.getSizeInBits() == 128 || "Expected an SSE value type!"); > + EVT MiddleVT = MVT::v4i32; > Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MiddleVT, Item); > Item = getShuffleVectorZeroOrUndef(Item, 0, true, > Subtarget->hasXMMInt(), DAG); > > Modified: llvm/trunk/test/CodeGen/X86/avx-shuffle.ll > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx-shuffle.ll?rev=147308&r1=147307&r2=147308&view=diff > ============================================================================== > --- llvm/trunk/test/CodeGen/X86/avx-shuffle.ll (original) > +++ llvm/trunk/test/CodeGen/X86/avx-shuffle.ll Wed Dec 28 02:14:01 2011 > @@ -13,8 +13,22 @@ > define <3 x i64> @test2(<2 x i64> %v) nounwind readnone { > ; CHECK: test2: > ; CHECK: vxorpd > -; CHECK: vmovsd > +; CHECK: vperm2f128 > %1 = shufflevector <2 x i64> %v, <2 x i64> %v, <3 x i32> > %2 = shufflevector <3 x i64> zeroinitializer, <3 x i64> %1, <3 x i32> > ret <3 x i64> %2 > } > + > +define <4 x i64> @test3(<4 x i64> %a, <4 x i64> %b) nounwind { > + %c = shufflevector <4 x i64> %a, <4 x i64> %b, <4 x i32> > + ret <4 x i64> %c > +; CHECK: test3: > +; CHECK: vperm2f128 > +} > + > +define <8 x float> @test4(float %a) nounwind { > + %b = insertelement <8 x float> zeroinitializer, float %a, i32 0 > + ret <8 x float> %b > +; CHECK: test4: > +; CHECK: vinsertf128 > +} > \ No newline at end of file > Please make sure your test case ends with a newline. This was fixed in r147481. Chad > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits --------------------------------------------------------------------- Intel Israel (74) Limited This e-mail and any attachments may contain confidential material for the sole use of the intended recipient(s). Any review or distribution by others is strictly prohibited. If you are not the intended recipient, please contact the sender and delete all copies. From baldrick at free.fr Wed Jan 4 03:09:51 2012 From: baldrick at free.fr (Duncan Sands) Date: Wed, 04 Jan 2012 10:09:51 +0100 Subject: [llvm-commits] [llvm] r147512 - in /llvm/trunk: lib/Target/X86/X86ISelLowering.cpp test/CodeGen/X86/jump_sign.ll In-Reply-To: <20120104014139.D2FE92A6C12C@llvm.org> References: <20120104014139.D2FE92A6C12C@llvm.org> Message-ID: <4F04175F.20503@free.fr> Hi Evan, > For x86, canonicalize max > (x> y) ? x : y > => > (x>= y) ? x : y maybe it is useful to handle (x < y) ? y : x too, or will that have been canonicalized to (y > x) ? y : x by the IR optimizers already? Ciao, Duncan. > > So for something like > (x - y)> 0 : (x - y) ? 0 > It will be > (x - y)>= 0 : (x - y) ? 0 > > This makes is possible to test sign-bit and eliminate a comparison against > zero. e.g. > subl %esi, %edi > testl %edi, %edi > movl $0, %eax > cmovgl %edi, %eax > => > xorl %eax, %eax > subl %esi, $edi > cmovsl %eax, %edi > > rdar://10633221 > > Modified: > llvm/trunk/lib/Target/X86/X86ISelLowering.cpp > llvm/trunk/test/CodeGen/X86/jump_sign.ll > > Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=147512&r1=147511&r2=147512&view=diff > ============================================================================== > --- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original) > +++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Tue Jan 3 19:41:39 2012 > @@ -13139,6 +13139,37 @@ > } > } > > + // Canonicalize max and min: > + // (x> y) ? x : y -> (x>= y) ? x : y > + // (x< y) ? x : y -> (x<= y) ? x : y > + // This allows use of COND_S / COND_NS (see TranslateX86CC) which eliminates > + // the need for an extra compare > + // against zero. e.g. > + // (x - y)> 0 : (x - y) ? 0 -> (x - y)>= 0 : (x - y) ? 0 > + // subl %esi, %edi > + // testl %edi, %edi > + // movl $0, %eax > + // cmovgl %edi, %eax > + // => > + // xorl %eax, %eax > + // subl %esi, $edi > + // cmovsl %eax, %edi > + if (N->getOpcode() == ISD::SELECT&& Cond.getOpcode() == ISD::SETCC&& > + DAG.isEqualTo(LHS, Cond.getOperand(0))&& > + DAG.isEqualTo(RHS, Cond.getOperand(1))) { > + ISD::CondCode CC = cast(Cond.getOperand(2))->get(); > + switch (CC) { > + default: break; > + case ISD::SETLT: > + case ISD::SETGT: { > + ISD::CondCode NewCC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGE; > + Cond = DAG.getSetCC(Cond.getDebugLoc(), Cond.getValueType(), > + Cond.getOperand(0), Cond.getOperand(1), NewCC); > + return DAG.getNode(ISD::SELECT, DL, VT, Cond, LHS, RHS); > + } > + } > + } > + > return SDValue(); > } > > > Modified: llvm/trunk/test/CodeGen/X86/jump_sign.ll > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/jump_sign.ll?rev=147512&r1=147511&r2=147512&view=diff > ============================================================================== > --- llvm/trunk/test/CodeGen/X86/jump_sign.ll (original) > +++ llvm/trunk/test/CodeGen/X86/jump_sign.ll Tue Jan 3 19:41:39 2012 > @@ -1,7 +1,9 @@ > -; RUN: llc< %s -march=x86 | grep jns > +; RUN: llc< %s -march=x86 | FileCheck %s > > define i32 @f(i32 %X) { > entry: > +; CHECK: f: > +; CHECK: jns > %tmp1 = add i32 %X, 1 ; [#uses=1] > %tmp = icmp slt i32 %tmp1, 0 ; [#uses=1] > br i1 %tmp, label %cond_true, label %cond_next > @@ -18,3 +20,15 @@ > declare i32 @bar(...) > > declare i32 @baz(...) > + > +; rdar://10633221 > +define i32 @g(i32 %a, i32 %b) nounwind { > +entry: > +; CHECK: g: > +; CHECK-NOT: test > +; CHECK: cmovs > + %sub = sub nsw i32 %a, %b > + %cmp = icmp sgt i32 %sub, 0 > + %cond = select i1 %cmp, i32 %sub, i32 0 > + ret i32 %cond > +} > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From craig.topper at gmail.com Wed Jan 4 03:23:09 2012 From: craig.topper at gmail.com (Craig Topper) Date: Wed, 04 Jan 2012 09:23:09 -0000 Subject: [llvm-commits] [llvm] r147527 - /llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp Message-ID: <20120104092310.11CAB2A6C12C@llvm.org> Author: ctopper Date: Wed Jan 4 03:23:09 2012 New Revision: 147527 URL: http://llvm.org/viewvc/llvm-project?rev=147527&view=rev Log: Allow vector shuffle normalizing to use concat vector even if the sources are commuted in the shuffle mask. Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp?rev=147527&r1=147526&r2=147527&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp Wed Jan 4 03:23:09 2012 @@ -2778,12 +2778,13 @@ TLI.getValueType(I.getType()), InVec, InIdx)); } -// Utility for visitShuffleVector - Returns true if the mask is mask starting -// from SIndx and increasing to the element length (undefs are allowed). -static bool SequentialMask(SmallVectorImpl &Mask, unsigned SIndx) { - unsigned MaskNumElts = Mask.size(); - for (unsigned i = 0; i != MaskNumElts; ++i) - if ((Mask[i] >= 0) && (Mask[i] != (int)(i + SIndx))) +// Utility for visitShuffleVector - Return true if every element in Mask, +// begining // from position Pos and ending in Pos+Size, falls within the +// specified sequential range [L, L+Pos). or is undef. +static bool isSequentialInRange(const SmallVectorImpl &Mask, + int Pos, int Size, int Low) { + for (int i = Pos, e = Pos+Size; i != e; ++i, ++Low) + if (Mask[i] >= 0 && Mask[i] != Low) return false; return true; } @@ -2820,11 +2821,23 @@ // Mask is longer than the source vectors and is a multiple of the source // vectors. We can use concatenate vector to make the mask and vectors // lengths match. - if (SrcNumElts*2 == MaskNumElts && SequentialMask(Mask, 0)) { - // The shuffle is concatenating two vectors together. - setValue(&I, DAG.getNode(ISD::CONCAT_VECTORS, getCurDebugLoc(), - VT, Src1, Src2)); - return; + if (SrcNumElts*2 == MaskNumElts) { + // First check for Src1 in low and Src2 in high + if (isSequentialInRange(Mask, 0, SrcNumElts, 0) && + isSequentialInRange(Mask, SrcNumElts, SrcNumElts, SrcNumElts)) { + // The shuffle is concatenating two vectors together. + setValue(&I, DAG.getNode(ISD::CONCAT_VECTORS, getCurDebugLoc(), + VT, Src1, Src2)); + return; + } + // Then check for Src2 in low and Src1 in high + if (isSequentialInRange(Mask, 0, SrcNumElts, SrcNumElts) && + isSequentialInRange(Mask, SrcNumElts, SrcNumElts, 0)) { + // The shuffle is concatenating two vectors together. + setValue(&I, DAG.getNode(ISD::CONCAT_VECTORS, getCurDebugLoc(), + VT, Src2, Src1)); + return; + } } // Pad both vectors with undefs to make them the same length as the mask. From nicholas at mxc.ca Wed Jan 4 03:28:29 2012 From: nicholas at mxc.ca (Nick Lewycky) Date: Wed, 04 Jan 2012 09:28:29 -0000 Subject: [llvm-commits] [llvm] r147528 - in /llvm/trunk: lib/Transforms/InstCombine/InstCombineShifts.cpp lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp test/Transforms/InstCombine/shift.ll Message-ID: <20120104092829.A9DE61BE003@llvm.org> Author: nicholas Date: Wed Jan 4 03:28:29 2012 New Revision: 147528 URL: http://llvm.org/viewvc/llvm-project?rev=147528&view=rev Log: Teach instcombine all sorts of great stuff about shifts that have exact, nuw or nsw bits on them. Modified: llvm/trunk/lib/Transforms/InstCombine/InstCombineShifts.cpp llvm/trunk/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp llvm/trunk/test/Transforms/InstCombine/shift.ll Modified: llvm/trunk/lib/Transforms/InstCombine/InstCombineShifts.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/InstCombine/InstCombineShifts.cpp?rev=147528&r1=147527&r2=147528&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/InstCombine/InstCombineShifts.cpp (original) +++ llvm/trunk/lib/Transforms/InstCombine/InstCombineShifts.cpp Wed Jan 4 03:28:29 2012 @@ -576,7 +576,16 @@ ShiftOp->getOpcode() != Instruction::Shl) { assert(ShiftOp->getOpcode() == Instruction::LShr || ShiftOp->getOpcode() == Instruction::AShr); - Value *Shift = Builder->CreateShl(X, ConstantInt::get(Ty, ShiftDiff)); + ConstantInt *ShiftDiffCst = ConstantInt::get(Ty, ShiftDiff); + if (ShiftOp->isExact()) { + // (X >>?,exact C1) << C2 --> X << (C2-C1) + BinaryOperator *NewShl = BinaryOperator::Create(Instruction::Shl, + X, ShiftDiffCst); + NewShl->setHasNoUnsignedWrap(I.hasNoUnsignedWrap()); + NewShl->setHasNoSignedWrap(I.hasNoSignedWrap()); + return NewShl; + } + Value *Shift = Builder->CreateShl(X, ShiftDiffCst); APInt Mask(APInt::getHighBitsSet(TypeBits, TypeBits - ShiftAmt2)); return BinaryOperator::CreateAnd(Shift, @@ -587,14 +596,35 @@ if (I.getOpcode() == Instruction::LShr && ShiftOp->getOpcode() == Instruction::Shl) { assert(ShiftOp->getOpcode() == Instruction::Shl); - Value *Shift = Builder->CreateLShr(X, ConstantInt::get(Ty, ShiftDiff)); + ConstantInt *ShiftDiffCst = ConstantInt::get(Ty, ShiftDiff); + // (X <>u C2 --> X >>u (C2-C1) + if (ShiftOp->hasNoUnsignedWrap()) { + BinaryOperator *NewLShr = BinaryOperator::Create(Instruction::LShr, + X, ShiftDiffCst); + NewLShr->setIsExact(I.isExact()); + return NewLShr; + } + Value *Shift = Builder->CreateLShr(X, ShiftDiffCst); APInt Mask(APInt::getLowBitsSet(TypeBits, TypeBits - ShiftAmt2)); return BinaryOperator::CreateAnd(Shift, ConstantInt::get(I.getContext(),Mask)); } - - // We can't handle (X << C1) >>s C2, it shifts arbitrary bits in. + + // We can't handle (X << C1) >>s C2, it shifts arbitrary bits in. However, + // we can handle (X <>s C2 since it only shifts in sign bits. + if (I.getOpcode() == Instruction::AShr && + ShiftOp->getOpcode() == Instruction::Shl) { + assert(ShiftOp->getOpcode() == Instruction::Shl); + if (ShiftOp->hasNoSignedWrap()) { + // (X <>s C2 --> X >>s (C2-C1) + ConstantInt *ShiftDiffCst = ConstantInt::get(Ty, ShiftDiff); + BinaryOperator *NewAShr = BinaryOperator::Create(Instruction::AShr, + X, ShiftDiffCst); + NewAShr->setIsExact(I.isExact()); + return NewAShr; + } + } } else { assert(ShiftAmt2 < ShiftAmt1); uint32_t ShiftDiff = ShiftAmt1-ShiftAmt2; @@ -620,14 +650,34 @@ // (X << C1) >>u C2 --> X << (C1-C2) & (-1 >> C2) if (I.getOpcode() == Instruction::LShr && ShiftOp->getOpcode() == Instruction::Shl) { - Value *Shift = Builder->CreateShl(X, ConstantInt::get(Ty, ShiftDiff)); + ConstantInt *ShiftDiffCst = ConstantInt::get(Ty, ShiftDiff); + if (ShiftOp->hasNoUnsignedWrap()) { + // (X <>u C2 --> X <setHasNoUnsignedWrap(true); + return NewShl; + } + Value *Shift = Builder->CreateShl(X, ShiftDiffCst); APInt Mask(APInt::getLowBitsSet(TypeBits, TypeBits - ShiftAmt2)); return BinaryOperator::CreateAnd(Shift, ConstantInt::get(I.getContext(),Mask)); } - // We can't handle (X << C1) >>a C2, it shifts arbitrary bits in. + // We can't handle (X << C1) >>s C2, it shifts arbitrary bits in. However, + // we can handle (X <>s C2 since it only shifts in sign bits. + if (I.getOpcode() == Instruction::AShr && + ShiftOp->getOpcode() == Instruction::Shl) { + if (ShiftOp->hasNoSignedWrap()) { + // (X <>s C2 --> X <setHasNoSignedWrap(true); + return NewShl; + } + } } } return 0; Modified: llvm/trunk/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp?rev=147528&r1=147527&r2=147528&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp (original) +++ llvm/trunk/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp Wed Jan 4 03:28:29 2012 @@ -682,8 +682,9 @@ if (BitWidth <= ShiftAmt || KnownZero[BitWidth-ShiftAmt-1] || (HighBits & ~DemandedMask) == HighBits) { // Perform the logical shift right. - Instruction *NewVal = BinaryOperator::CreateLShr( - I->getOperand(0), SA, I->getName()); + BinaryOperator *NewVal = BinaryOperator::CreateLShr(I->getOperand(0), + SA, I->getName()); + NewVal->setIsExact(cast(I)->isExact()); return InsertNewInstWith(NewVal, *I); } else if ((KnownOne & SignBit) != 0) { // New bits are known one. KnownOne |= HighBits; Modified: llvm/trunk/test/Transforms/InstCombine/shift.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstCombine/shift.ll?rev=147528&r1=147527&r2=147528&view=diff ============================================================================== --- llvm/trunk/test/Transforms/InstCombine/shift.ll (original) +++ llvm/trunk/test/Transforms/InstCombine/shift.ll Wed Jan 4 03:28:29 2012 @@ -560,3 +560,57 @@ ; CHECK-NEXT: %z = lshr exact i32 %a, 2 ; CHECK-NEXT: ret i32 %z } + +define i32 @test48(i32 %x) { + %A = lshr exact i32 %x, 1 + %B = shl i32 %A, 3 + ret i32 %B +; CHECK: @test48 +; CHECK-NEXT: %B = shl i32 %x, 2 +; CHECK-NEXT: ret i32 %B +} + +define i32 @test49(i32 %x) { + %A = ashr exact i32 %x, 1 + %B = shl i32 %A, 3 + ret i32 %B +; CHECK: @test49 +; CHECK-NEXT: %B = shl i32 %x, 2 +; CHECK-NEXT: ret i32 %B +} + +define i32 @test50(i32 %x) { + %A = shl nsw i32 %x, 1 + %B = ashr i32 %A, 3 + ret i32 %B +; CHECK: @test50 +; CHECK-NEXT: %B = ashr i32 %x, 2 +; CHECK-NEXT: ret i32 %B +} + +define i32 @test51(i32 %x) { + %A = shl nuw i32 %x, 1 + %B = lshr i32 %A, 3 + ret i32 %B +; CHECK: @test51 +; CHECK-NEXT: %B = lshr i32 %x, 2 +; CHECK-NEXT: ret i32 %B +} + +define i32 @test52(i32 %x) { + %A = shl nsw i32 %x, 3 + %B = ashr i32 %A, 1 + ret i32 %B +; CHECK: @test52 +; CHECK-NEXT: %B = shl nsw i32 %x, 2 +; CHECK-NEXT: ret i32 %B +} + +define i32 @test53(i32 %x) { + %A = shl nuw i32 %x, 3 + %B = lshr i32 %A, 1 + ret i32 %B +; CHECK: @test53 +; CHECK-NEXT: %B = shl nuw i32 %x, 2 +; CHECK-NEXT: ret i32 %B +} From nicholas at mxc.ca Wed Jan 4 03:42:30 2012 From: nicholas at mxc.ca (Nick Lewycky) Date: Wed, 04 Jan 2012 09:42:30 -0000 Subject: [llvm-commits] [llvm] r147529 - /llvm/trunk/lib/Transforms/InstCombine/InstCombineShifts.cpp Message-ID: <20120104094230.59DA22A6C12C@llvm.org> Author: nicholas Date: Wed Jan 4 03:42:30 2012 New Revision: 147529 URL: http://llvm.org/viewvc/llvm-project?rev=147529&view=rev Log: Remove pointless asserts. Modified: llvm/trunk/lib/Transforms/InstCombine/InstCombineShifts.cpp Modified: llvm/trunk/lib/Transforms/InstCombine/InstCombineShifts.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/InstCombine/InstCombineShifts.cpp?rev=147529&r1=147528&r2=147529&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/InstCombine/InstCombineShifts.cpp (original) +++ llvm/trunk/lib/Transforms/InstCombine/InstCombineShifts.cpp Wed Jan 4 03:42:30 2012 @@ -595,7 +595,6 @@ // (X << C1) >>u C2 --> X >>u (C2-C1) & (-1 >> C2) if (I.getOpcode() == Instruction::LShr && ShiftOp->getOpcode() == Instruction::Shl) { - assert(ShiftOp->getOpcode() == Instruction::Shl); ConstantInt *ShiftDiffCst = ConstantInt::get(Ty, ShiftDiff); // (X <>u C2 --> X >>u (C2-C1) if (ShiftOp->hasNoUnsignedWrap()) { @@ -615,7 +614,6 @@ // we can handle (X <>s C2 since it only shifts in sign bits. if (I.getOpcode() == Instruction::AShr && ShiftOp->getOpcode() == Instruction::Shl) { - assert(ShiftOp->getOpcode() == Instruction::Shl); if (ShiftOp->hasNoSignedWrap()) { // (X <>s C2 --> X >>s (C2-C1) ConstantInt *ShiftDiffCst = ConstantInt::get(Ty, ShiftDiff); From rdivacky at freebsd.org Wed Jan 4 08:47:31 2012 From: rdivacky at freebsd.org (Roman Divacky) Date: Wed, 4 Jan 2012 15:47:31 +0100 Subject: [llvm-commits] [llvm] r147528 - in /llvm/trunk: lib/Transforms/InstCombine/InstCombineShifts.cpp lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp test/Transforms/InstCombine/shift.ll In-Reply-To: <20120104092829.A9DE61BE003@llvm.org> References: <20120104092829.A9DE61BE003@llvm.org> Message-ID: <20120104144731.GA76771@freebsd.org> > + if (I.getOpcode() == Instruction::AShr && > + ShiftOp->getOpcode() == Instruction::Shl) { > + assert(ShiftOp->getOpcode() == Instruction::Shl); You dont need the assert as you tested this in the if condition. From mcrosier at apple.com Wed Jan 4 12:21:00 2012 From: mcrosier at apple.com (Chad Rosier) Date: Wed, 04 Jan 2012 10:21:00 -0800 Subject: [llvm-commits] [llvm] r147308 - in /llvm/trunk: lib/Target/X86/X86ISelLowering.cpp test/CodeGen/X86/avx-shuffle.ll In-Reply-To: References: <20111228081401.E07221BE003@llvm.org> <1C6CDAB6-82FE-4107-A408-C874F50BF5EA@apple.com> Message-ID: On Jan 4, 2012, at 12:50 AM, Demikhovsky, Elena wrote: > I fixed two bugs together because after I fixed VECTOR_SHUFFLE with MOVL mask the shuffle node was not lowered and it came to BUILD_VECTOR and failed there. Ok, that makes sense. Thanks for the clarification. > The MOVL / MOVLP instructions work for 128-bit vectors. I'm running conformance tests on AVX and see that many shuffle cases generate wrong instruction set. I'm trying to fix one-by-one and I have several fixes if one fix causes fail in another place. My primary concern here is that while we may have fixed the incorrect cases we may have also regressed the correct cases. My first though would be to add the (VT.getSizeInBits() == 128) predicate at the MOVL/MOVLP call sites (rather then in the isMOVL*Mask() function) for the cases that don't properly handle AVX. Chad > - Elena > > -----Original Message----- > From: Chad Rosier [mailto:mcrosier at apple.com] > Sent: Wednesday, January 04, 2012 03:30 > To: Demikhovsky, Elena > Cc: llvm-commits at cs.uiuc.edu > Subject: Re: [llvm-commits] [llvm] r147308 - in /llvm/trunk: lib/Target/X86/X86ISelLowering.cpp test/CodeGen/X86/avx-shuffle.ll > > Hi Elena, > Just a few comments below. > > On Dec 28, 2011, at 12:14 AM, Elena Demikhovsky wrote: > >> Author: delena >> Date: Wed Dec 28 02:14:01 2011 >> New Revision: 147308 >> >> URL: http://llvm.org/viewvc/llvm-project?rev=147308&view=rev >> Log: >> Fixed a bug in LowerVECTOR_SHUFFLE and LowerBUILD_VECTOR. >> Matching MOVLP mask for AVX (265-bit vectors) was wrong. >> The failure was detected by conformance tests. > > As far as I can tell this patch is addressing two bugs, one in LowerBUILD_VECTOR and another with LowerVECTOR_SHUFFLE/MOVLP. These should really be fixed in two separate commits. > >> >> Modified: >> llvm/trunk/lib/Target/X86/X86ISelLowering.cpp >> llvm/trunk/test/CodeGen/X86/avx-shuffle.ll >> >> Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp >> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=147308&r1=147307&r2=147308&view=diff >> ============================================================================== >> --- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original) >> +++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Wed Dec 28 02:14:01 2011 >> @@ -3448,6 +3448,11 @@ >> /// isMOVLPMask - Return true if the specified VECTOR_SHUFFLE operand >> /// specifies a shuffle of elements that is suitable for input to MOVLP{S|D}. >> bool X86::isMOVLPMask(ShuffleVectorSDNode *N) { >> + EVT VT = N->getValueType(0); >> + >> + if (VT.getSizeInBits() != 128) >> + return false; >> + > > I'm not sure I agree with the approach taken here... > >> unsigned NumElems = N->getValueType(0).getVectorNumElements(); >> >> if (NumElems != 2 && NumElems != 4) >> @@ -3666,6 +3671,8 @@ >> static bool isMOVLMask(const SmallVectorImpl &Mask, EVT VT) { >> if (VT.getVectorElementType().getSizeInBits() < 32) >> return false; >> + if (VT.getSizeInBits() == 256) >> + return false; > > ..and here. Aren't these functions behaving correctly? I believe the real problem is the code that is predicated upon these functions; they don't fully support codegen when AVX is enabled. > > And one moot point.. The conditional statements that checks the size of the vectors could be more consistent (i.e., both (VT.getSizeInBits != 128) or (VT.getSizeInBits != 128), but not a combination of the two). > >> int NumElts = VT.getVectorNumElements(); >> >> @@ -5158,16 +5165,30 @@ >> return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item); >> } else if (ExtVT == MVT::i32 || ExtVT == MVT::f32 || ExtVT == MVT::f64 || >> (ExtVT == MVT::i64 && Subtarget->is64Bit())) { >> + if (VT.getSizeInBits() == 256) { >> + >> + EVT VT128 = EVT::getVectorVT(*DAG.getContext(), ExtVT, NumElems / 2); >> + Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT128, Item); >> + SDValue ZeroVec = getZeroVector(VT, true, DAG, dl); >> + return Insert128BitVector(ZeroVec, Item, DAG.getConstant(0, MVT::i32), >> + DAG, dl); >> + } >> Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item); >> // Turn it into a MOVL (i.e. movss, movsd, or movd) to a zero vector. >> return getShuffleVectorZeroOrUndef(Item, 0, true,Subtarget->hasXMMInt(), >> DAG); >> } else if (ExtVT == MVT::i16 || ExtVT == MVT::i8) { >> Item = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Item); >> - unsigned NumBits = VT.getSizeInBits(); >> - assert((NumBits == 128 || NumBits == 256) && >> - "Expected an SSE or AVX value type!"); >> - EVT MiddleVT = NumBits == 128 ? MVT::v4i32 : MVT::v8i32; >> + if (VT.getSizeInBits() == 256) { >> + >> + EVT VT128 = EVT::getVectorVT(*DAG.getContext(), ExtVT, NumElems / 2); >> + Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT128, Item); >> + SDValue ZeroVec = getZeroVector(VT, true, DAG, dl); >> + return Insert128BitVector(ZeroVec, Item, DAG.getConstant(0, MVT::i32), >> + DAG, dl); >> + } >> + assert (VT.getSizeInBits() == 128 || "Expected an SSE value type!"); >> + EVT MiddleVT = MVT::v4i32; >> Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MiddleVT, Item); >> Item = getShuffleVectorZeroOrUndef(Item, 0, true, >> Subtarget->hasXMMInt(), DAG); >> >> Modified: llvm/trunk/test/CodeGen/X86/avx-shuffle.ll >> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx-shuffle.ll?rev=147308&r1=147307&r2=147308&view=diff >> ============================================================================== >> --- llvm/trunk/test/CodeGen/X86/avx-shuffle.ll (original) >> +++ llvm/trunk/test/CodeGen/X86/avx-shuffle.ll Wed Dec 28 02:14:01 2011 >> @@ -13,8 +13,22 @@ >> define <3 x i64> @test2(<2 x i64> %v) nounwind readnone { >> ; CHECK: test2: >> ; CHECK: vxorpd >> -; CHECK: vmovsd >> +; CHECK: vperm2f128 >> %1 = shufflevector <2 x i64> %v, <2 x i64> %v, <3 x i32> >> %2 = shufflevector <3 x i64> zeroinitializer, <3 x i64> %1, <3 x i32> >> ret <3 x i64> %2 >> } >> + >> +define <4 x i64> @test3(<4 x i64> %a, <4 x i64> %b) nounwind { >> + %c = shufflevector <4 x i64> %a, <4 x i64> %b, <4 x i32> >> + ret <4 x i64> %c >> +; CHECK: test3: >> +; CHECK: vperm2f128 >> +} >> + >> +define <8 x float> @test4(float %a) nounwind { >> + %b = insertelement <8 x float> zeroinitializer, float %a, i32 0 >> + ret <8 x float> %b >> +; CHECK: test4: >> +; CHECK: vinsertf128 >> +} >> \ No newline at end of file >> > > Please make sure your test case ends with a newline. This was fixed in r147481. > > Chad > >> _______________________________________________ >> llvm-commits mailing list >> llvm-commits at cs.uiuc.edu >> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits > > --------------------------------------------------------------------- > Intel Israel (74) Limited > > This e-mail and any attachments may contain confidential material for > the sole use of the intended recipient(s). Any review or distribution > by others is strictly prohibited. If you are not the intended > recipient, please contact the sender and delete all copies. > From daniel at zuster.org Wed Jan 4 12:33:50 2012 From: daniel at zuster.org (Daniel Dunbar) Date: Wed, 04 Jan 2012 18:33:50 -0000 Subject: [llvm-commits] [zorg] r147537 - /zorg/trunk/lnt/lnt/util/ImportData.py Message-ID: <20120104183350.641A42A6C12C@llvm.org> Author: ddunbar Date: Wed Jan 4 12:33:50 2012 New Revision: 147537 URL: http://llvm.org/viewvc/llvm-project?rev=147537&view=rev Log: [lnt/v0.4] lnt.util.ImportData: Fix a crash when no config object is available. Modified: zorg/trunk/lnt/lnt/util/ImportData.py Modified: zorg/trunk/lnt/lnt/util/ImportData.py URL: http://llvm.org/viewvc/llvm-project/zorg/trunk/lnt/lnt/util/ImportData.py?rev=147537&r1=147536&r2=147537&view=diff ============================================================================== --- zorg/trunk/lnt/lnt/util/ImportData.py (original) +++ zorg/trunk/lnt/lnt/util/ImportData.py Wed Jan 4 12:33:50 2012 @@ -102,9 +102,9 @@ # If this database has a shadow import configured, import the run into that # database as well. - db_config = config.databases[db_name] - if db_config.shadow_import: + if config and config.databases[db_name].shadow_import: # Load the shadow database to import into. + db_config = config.databases[db_name] shadow_name = db_config.shadow_import shadow_db = config.get_database(shadow_name) if shadow_db is None: From daniel at zuster.org Wed Jan 4 12:33:53 2012 From: daniel at zuster.org (Daniel Dunbar) Date: Wed, 04 Jan 2012 18:33:53 -0000 Subject: [llvm-commits] [zorg] r147538 - /zorg/trunk/lnt/lnt/server/db/testsuitedb.py Message-ID: <20120104183353.7E2922A6C12C@llvm.org> Author: ddunbar Date: Wed Jan 4 12:33:53 2012 New Revision: 147538 URL: http://llvm.org/viewvc/llvm-project?rev=147538&view=rev Log: [lnt/v0.4] lnt.server.db.testsuitedb: Prevent a crash in cases where SA wants to compare model instances to some sentinel objects (which is poor form, but whatever). Modified: zorg/trunk/lnt/lnt/server/db/testsuitedb.py Modified: zorg/trunk/lnt/lnt/server/db/testsuitedb.py URL: http://llvm.org/viewvc/llvm-project/zorg/trunk/lnt/lnt/server/db/testsuitedb.py?rev=147538&r1=147537&r2=147538&view=diff ============================================================================== --- zorg/trunk/lnt/lnt/server/db/testsuitedb.py (original) +++ zorg/trunk/lnt/lnt/server/db/testsuitedb.py Wed Jan 4 12:33:53 2012 @@ -144,6 +144,12 @@ db_key_name, self.__class__.__name__, self.ordinal, fields) def __cmp__(self, b): + # SA occassionally uses comparison to check model instances + # verse some sentinels, so we ensure we support comparison + # against non-instances. + if self.__class__ is not b.__class__: + return -1 + return cmp(tuple(self.get_field(item) for item in self.fields), tuple(b.get_field(item) From daniel at zuster.org Wed Jan 4 12:33:56 2012 From: daniel at zuster.org (Daniel Dunbar) Date: Wed, 04 Jan 2012 18:33:56 -0000 Subject: [llvm-commits] [zorg] r147539 - /zorg/trunk/lnt/lnt/server/db/v4db.py Message-ID: <20120104183356.5B7832A6C12C@llvm.org> Author: ddunbar Date: Wed Jan 4 12:33:56 2012 New Revision: 147539 URL: http://llvm.org/viewvc/llvm-project?rev=147539&view=rev Log: [lnt/v0.4] lnt.server.db.v4db: Don't let the summary object potentially reuse the database cursor which may have come from another thread. This isn't the right fix, but this class is slated for termination anyway. Modified: zorg/trunk/lnt/lnt/server/db/v4db.py Modified: zorg/trunk/lnt/lnt/server/db/v4db.py URL: http://llvm.org/viewvc/llvm-project/zorg/trunk/lnt/lnt/server/db/v4db.py?rev=147539&r1=147538&r2=147539&view=diff ============================================================================== --- zorg/trunk/lnt/lnt/server/db/v4db.py (original) +++ zorg/trunk/lnt/lnt/server/db/v4db.py Wed Jan 4 12:33:56 2012 @@ -136,10 +136,15 @@ def __init__(self, db): self.db = db + # Load all the test suite names now so that we don't attempt to reuse a + # cursor later. + # + # FIXME: Really, we just need to eliminate this object. + self.testsuites = list(self.db.testsuite) @property def suites(self): - for name in self.db.testsuite: + for name in self.testsuites: yield V4DBSummary.SuiteSummary(name, ("v4", name)) def is_up_to_date(self, db): From ahatanaka at mips.com Wed Jan 4 13:29:12 2012 From: ahatanaka at mips.com (Akira Hatanaka) Date: Wed, 04 Jan 2012 19:29:12 -0000 Subject: [llvm-commits] [llvm] r147541 - /llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp Message-ID: <20120104192912.28FD52A6C12E@llvm.org> Author: ahatanak Date: Wed Jan 4 13:29:11 2012 New Revision: 147541 URL: http://llvm.org/viewvc/llvm-project?rev=147541&view=rev Log: Enable -soft-float for MIPS. Modified: llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp Modified: llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp?rev=147541&r1=147540&r2=147541&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp (original) +++ llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp Wed Jan 4 13:29:11 2012 @@ -92,17 +92,20 @@ // Set up the register classes addRegisterClass(MVT::i32, Mips::CPURegsRegisterClass); - addRegisterClass(MVT::f32, Mips::FGR32RegisterClass); if (HasMips64) addRegisterClass(MVT::i64, Mips::CPU64RegsRegisterClass); - // When dealing with single precision only, use libcalls - if (!Subtarget->isSingleFloat()) { - if (HasMips64) - addRegisterClass(MVT::f64, Mips::FGR64RegisterClass); - else - addRegisterClass(MVT::f64, Mips::AFGR64RegisterClass); + if (!TM.Options.UseSoftFloat) { + addRegisterClass(MVT::f32, Mips::FGR32RegisterClass); + + // When dealing with single precision only, use libcalls + if (!Subtarget->isSingleFloat()) { + if (HasMips64) + addRegisterClass(MVT::f64, Mips::FGR64RegisterClass); + else + addRegisterClass(MVT::f64, Mips::AFGR64RegisterClass); + } } // Load extented operations for i1 types must be promoted From spop at codeaurora.org Wed Jan 4 13:47:23 2012 From: spop at codeaurora.org (Sebastian Pop) Date: Wed, 04 Jan 2012 19:47:23 -0000 Subject: [llvm-commits] [llvm] r147542 - in /llvm/trunk: autoconf/configure.ac cmake/config-ix.cmake configure include/llvm/Config/config.h.cmake include/llvm/Config/config.h.in include/llvm/Config/llvm-config.h.cmake include/llvm/Config/llvm-config.h.in include/llvm/Support/Host.h lib/Support/CommandLine.cpp lib/Support/TargetRegistry.cpp lib/Support/Unix/Host.inc lib/Support/Windows/Host.inc projects/sample/autoconf/configure.ac projects/sample/configure Message-ID: <20120104194723.7F0572A6C12C@llvm.org> Author: spop Date: Wed Jan 4 13:47:22 2012 New Revision: 147542 URL: http://llvm.org/viewvc/llvm-project?rev=147542&view=rev Log: use getHostTriple instead of getDefaultTargetTriple in getClosestTargetForJIT Get back getHostTriple. For JIT compilation, use the host triple instead of the default target: this fixes some JIT testcases that used to fail when the compiler has been configured as a cross compiler. Modified: llvm/trunk/autoconf/configure.ac llvm/trunk/cmake/config-ix.cmake llvm/trunk/configure llvm/trunk/include/llvm/Config/config.h.cmake llvm/trunk/include/llvm/Config/config.h.in llvm/trunk/include/llvm/Config/llvm-config.h.cmake llvm/trunk/include/llvm/Config/llvm-config.h.in llvm/trunk/include/llvm/Support/Host.h llvm/trunk/lib/Support/CommandLine.cpp llvm/trunk/lib/Support/TargetRegistry.cpp llvm/trunk/lib/Support/Unix/Host.inc llvm/trunk/lib/Support/Windows/Host.inc llvm/trunk/projects/sample/autoconf/configure.ac llvm/trunk/projects/sample/configure Modified: llvm/trunk/autoconf/configure.ac URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/autoconf/configure.ac?rev=147542&r1=147541&r2=147542&view=diff ============================================================================== --- llvm/trunk/autoconf/configure.ac (original) +++ llvm/trunk/autoconf/configure.ac Wed Jan 4 13:47:22 2012 @@ -1484,6 +1484,8 @@ [Installation directory for man pages]) AC_DEFINE_UNQUOTED(LLVM_CONFIGTIME, "$LLVM_CONFIGTIME", [Time at which LLVM was configured]) +AC_DEFINE_UNQUOTED(LLVM_HOST_TRIPLE, "$host", + [Host triple LLVM will run on]) AC_DEFINE_UNQUOTED(LLVM_DEFAULT_TARGET_TRIPLE, "$target", [Target triple LLVM will generate code for by default]) Modified: llvm/trunk/cmake/config-ix.cmake URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/cmake/config-ix.cmake?rev=147542&r1=147541&r2=147542&view=diff ============================================================================== --- llvm/trunk/cmake/config-ix.cmake (original) +++ llvm/trunk/cmake/config-ix.cmake Wed Jan 4 13:47:22 2012 @@ -288,13 +288,16 @@ check_cxx_compiler_flag("-Wno-variadic-macros" SUPPORTS_NO_VARIADIC_MACROS_FLAG) include(GetTargetTriple) +get_target_triple(LLVM_HOST_TRIPLE) get_target_triple(LLVM_DEFAULT_TARGET_TRIPLE) +set(HOST_TRIPLE "${LLVM_HOST_TRIPLE}") set(TARGET_TRIPLE "${LLVM_DEFAULT_TARGET_TRIPLE}") # Determine the native architecture. string(TOLOWER "${LLVM_TARGET_ARCH}" LLVM_NATIVE_ARCH) if( LLVM_NATIVE_ARCH STREQUAL "host" ) + string(REGEX MATCH "^[^-]*" LLVM_NATIVE_ARCH ${LLVM_HOST_TRIPLE}) string(REGEX MATCH "^[^-]*" LLVM_NATIVE_ARCH ${LLVM_DEFAULT_TARGET_TRIPLE}) endif () Modified: llvm/trunk/configure URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/configure?rev=147542&r1=147541&r2=147542&view=diff ============================================================================== --- llvm/trunk/configure (original) +++ llvm/trunk/configure Wed Jan 4 13:47:22 2012 @@ -20913,6 +20913,11 @@ cat >>confdefs.h <<_ACEOF +#define LLVM_HOST_TRIPLE "$host" +_ACEOF + + +cat >>confdefs.h <<_ACEOF #define LLVM_DEFAULT_TARGET_TRIPLE "$target" _ACEOF Modified: llvm/trunk/include/llvm/Config/config.h.cmake URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Config/config.h.cmake?rev=147542&r1=147541&r2=147542&view=diff ============================================================================== --- llvm/trunk/include/llvm/Config/config.h.cmake (original) +++ llvm/trunk/include/llvm/Config/config.h.cmake Wed Jan 4 13:47:22 2012 @@ -560,6 +560,9 @@ /* Has gcc/MSVC atomic intrinsics */ #cmakedefine01 LLVM_HAS_ATOMICS +/* Host triple LLVM will run on */ +#cmakedefine LLVM_HOST_TRIPLE "${LLVM_HOST_TRIPLE}" + /* Installation directory for include files */ #cmakedefine LLVM_INCLUDEDIR "${LLVM_INCLUDEDIR}" Modified: llvm/trunk/include/llvm/Config/config.h.in URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Config/config.h.in?rev=147542&r1=147541&r2=147542&view=diff ============================================================================== --- llvm/trunk/include/llvm/Config/config.h.in (original) +++ llvm/trunk/include/llvm/Config/config.h.in Wed Jan 4 13:47:22 2012 @@ -558,6 +558,9 @@ /* Has gcc/MSVC atomic intrinsics */ #undef LLVM_HAS_ATOMICS +/* Host triple LLVM will run on */ +#undef LLVM_HOST_TRIPLE + /* Installation directory for include files */ #undef LLVM_INCLUDEDIR Modified: llvm/trunk/include/llvm/Config/llvm-config.h.cmake URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Config/llvm-config.h.cmake?rev=147542&r1=147541&r2=147542&view=diff ============================================================================== --- llvm/trunk/include/llvm/Config/llvm-config.h.cmake (original) +++ llvm/trunk/include/llvm/Config/llvm-config.h.cmake Wed Jan 4 13:47:22 2012 @@ -40,6 +40,9 @@ /* Has gcc/MSVC atomic intrinsics */ #cmakedefine01 LLVM_HAS_ATOMICS +/* Host triple LLVM will run on */ +#cmakedefine LLVM_HOST_TRIPLE "${LLVM_HOST_TRIPLE}" + /* Installation directory for include files */ #cmakedefine LLVM_INCLUDEDIR "${LLVM_INCLUDEDIR}" Modified: llvm/trunk/include/llvm/Config/llvm-config.h.in URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Config/llvm-config.h.in?rev=147542&r1=147541&r2=147542&view=diff ============================================================================== --- llvm/trunk/include/llvm/Config/llvm-config.h.in (original) +++ llvm/trunk/include/llvm/Config/llvm-config.h.in Wed Jan 4 13:47:22 2012 @@ -40,6 +40,9 @@ /* Has gcc/MSVC atomic intrinsics */ #undef LLVM_HAS_ATOMICS +/* Host triple LLVM will run on */ +#undef LLVM_HOST_TRIPLE + /* Installation directory for include files */ #undef LLVM_INCLUDEDIR Modified: llvm/trunk/include/llvm/Support/Host.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Support/Host.h?rev=147542&r1=147541&r2=147542&view=diff ============================================================================== --- llvm/trunk/include/llvm/Support/Host.h (original) +++ llvm/trunk/include/llvm/Support/Host.h Wed Jan 4 13:47:22 2012 @@ -33,6 +33,14 @@ return !isLittleEndianHost(); } + /// getHostTriple() - Return the host where the compiler will be running. + /// + /// The host triple is a string in the format of: + /// CPU_TYPE-VENDOR-OPERATING_SYSTEM + /// or + /// CPU_TYPE-VENDOR-KERNEL-OPERATING_SYSTEM + std::string getHostTriple(); + /// getDefaultTargetTriple() - Return the default target triple the compiler /// has been configured to produce code for. /// Modified: llvm/trunk/lib/Support/CommandLine.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Support/CommandLine.cpp?rev=147542&r1=147541&r2=147542&view=diff ============================================================================== --- llvm/trunk/lib/Support/CommandLine.cpp (original) +++ llvm/trunk/lib/Support/CommandLine.cpp Wed Jan 4 13:47:22 2012 @@ -1373,6 +1373,7 @@ << " Built " << __DATE__ << " (" << __TIME__ << ").\n" #endif << " Default target: " << sys::getDefaultTargetTriple() << '\n' + << " Host: " << sys::getHostTriple() << '\n' << " Host CPU: " << CPU << '\n'; } void operator=(bool OptionWasSpecified) { Modified: llvm/trunk/lib/Support/TargetRegistry.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Support/TargetRegistry.cpp?rev=147542&r1=147541&r2=147542&view=diff ============================================================================== --- llvm/trunk/lib/Support/TargetRegistry.cpp (original) +++ llvm/trunk/lib/Support/TargetRegistry.cpp Wed Jan 4 13:47:22 2012 @@ -84,7 +84,7 @@ } const Target *TargetRegistry::getClosestTargetForJIT(std::string &Error) { - const Target *TheTarget = lookupTarget(sys::getDefaultTargetTriple(), Error); + const Target *TheTarget = lookupTarget(sys::getHostTriple(), Error); if (TheTarget && !TheTarget->hasJIT()) { Error = "No JIT compatible target available for this host"; Modified: llvm/trunk/lib/Support/Unix/Host.inc URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Support/Unix/Host.inc?rev=147542&r1=147541&r2=147542&view=diff ============================================================================== --- llvm/trunk/lib/Support/Unix/Host.inc (original) +++ llvm/trunk/lib/Support/Unix/Host.inc Wed Jan 4 13:47:22 2012 @@ -35,13 +35,9 @@ return info.release; } -std::string sys::getDefaultTargetTriple() { - StringRef TargetTripleString(LLVM_DEFAULT_TARGET_TRIPLE); - std::pair ArchSplit = TargetTripleString.split('-'); - - // Normalize the arch, since the target triple may not actually match the target. +std::string getTriple(StringRef &TripleString) { + std::pair ArchSplit = TripleString.split('-'); std::string Arch = ArchSplit.first; - std::string Triple(Arch); Triple += '-'; Triple += ArchSplit.second; @@ -61,3 +57,13 @@ return Triple; } + +std::string sys::getDefaultTargetTriple() { + StringRef TargetTripleString(LLVM_DEFAULT_TARGET_TRIPLE); + return getTriple(TargetTripleString); +} + +std::string sys::getHostTriple() { + StringRef HostTripleString(LLVM_HOST_TRIPLE); + return getTriple(HostTripleString); +} Modified: llvm/trunk/lib/Support/Windows/Host.inc URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Support/Windows/Host.inc?rev=147542&r1=147541&r2=147542&view=diff ============================================================================== --- llvm/trunk/lib/Support/Windows/Host.inc (original) +++ llvm/trunk/lib/Support/Windows/Host.inc Wed Jan 4 13:47:22 2012 @@ -20,3 +20,7 @@ std::string sys::getDefaultTargetTriple() { return LLVM_DEFAULT_TARGET_TRIPLE; } + +std::string sys::getHostTriple() { + return LLVM_HOST_TRIPLE; +} Modified: llvm/trunk/projects/sample/autoconf/configure.ac URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/projects/sample/autoconf/configure.ac?rev=147542&r1=147541&r2=147542&view=diff ============================================================================== --- llvm/trunk/projects/sample/autoconf/configure.ac (original) +++ llvm/trunk/projects/sample/autoconf/configure.ac Wed Jan 4 13:47:22 2012 @@ -1390,6 +1390,8 @@ [Installation directory for man pages]) AC_DEFINE_UNQUOTED(LLVM_CONFIGTIME, "$LLVM_CONFIGTIME", [Time at which LLVM was configured]) +AC_DEFINE_UNQUOTED(LLVM_HOST_TRIPLE, "$host", + [Host triple LLVM will run on]) AC_DEFINE_UNQUOTED(LLVM_DEFAULT_TARGET_TRIPLE, "$target", [Target triple LLVM will generate code for by default]) Modified: llvm/trunk/projects/sample/configure URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/projects/sample/configure?rev=147542&r1=147541&r2=147542&view=diff ============================================================================== --- llvm/trunk/projects/sample/configure (original) +++ llvm/trunk/projects/sample/configure Wed Jan 4 13:47:22 2012 @@ -8854,7 +8854,7 @@ shlibpath_var=LD_LIBRARY_PATH ;; -freebsd1*) +freebsd1.*) dynamic_linker=no ;; @@ -8877,7 +8877,7 @@ objformat=`/usr/bin/objformat` else case $host_os in - freebsd[123]*) objformat=aout ;; + freebsd[123].*) objformat=aout ;; *) objformat=elf ;; esac fi @@ -8895,7 +8895,7 @@ esac shlibpath_var=LD_LIBRARY_PATH case $host_os in - freebsd2*) + freebsd2.*) shlibpath_overrides_runpath=yes ;; freebsd3.[01]* | freebsdelf3.[01]*) @@ -10409,7 +10409,7 @@ lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2 lt_status=$lt_dlunknown cat > conftest.$ac_ext <>confdefs.h <<_ACEOF +#define LLVM_HOST_TRIPLE "$host" +_ACEOF + + +cat >>confdefs.h <<_ACEOF #define LLVM_DEFAULT_TARGET_TRIPLE "$target" _ACEOF From spop at codeaurora.org Wed Jan 4 14:11:19 2012 From: spop at codeaurora.org (Sebastian Pop) Date: Wed, 04 Jan 2012 20:11:19 -0000 Subject: [llvm-commits] [polly] r147543 - in /polly/trunk/www: get_started.html polly.sh Message-ID: <20120104201119.1687A2A6C12C@llvm.org> Author: spop Date: Wed Jan 4 14:11:18 2012 New Revision: 147543 URL: http://llvm.org/viewvc/llvm-project?rev=147543&view=rev Log: add polly.sh script Added: polly/trunk/www/polly.sh Modified: polly/trunk/www/get_started.html Modified: polly/trunk/www/get_started.html URL: http://llvm.org/viewvc/llvm-project/polly/trunk/www/get_started.html?rev=147543&r1=147542&r2=147543&view=diff ============================================================================== --- polly/trunk/www/get_started.html (original) +++ polly/trunk/www/get_started.html Wed Jan 4 14:11:18 2012 @@ -150,6 +150,12 @@ To check if Polly works correctly you can run make polly-test for the cmake build or make polly-test -C tools/polly/test/ for the autoconf build. + +

    Automatize

    + +To automate the checkout, update, build, and test of Polly, one can +use this script that contains all the commands +from this page in a single bash script. Added: polly/trunk/www/polly.sh URL: http://llvm.org/viewvc/llvm-project/polly/trunk/www/polly.sh?rev=147543&view=auto ============================================================================== --- polly/trunk/www/polly.sh (added) +++ polly/trunk/www/polly.sh Wed Jan 4 14:11:18 2012 @@ -0,0 +1,64 @@ +#!/bin/bash -xe + +export BASE=`pwd` +export LLVM_SRC=${BASE}/llvm +export POLLY_SRC=${LLVM_SRC}/tools/polly +export CLOOG_SRC=${BASE}/cloog_src +export CLOOG_INSTALL=${BASE}/cloog_install +export LLVM_BUILD=${BASE}/llvm_build +export SCOPLIB_DIR=${BASE}/scoplib-0.2.0 +export POCC_DIR=${BASE}/pocc-1.0-rc3.1 + +if [ -e /proc/cpuinfo ]; then + procs=`cat /proc/cpuinfo | grep processor | wc -l` +else + procs=1 +fi + +if ! test -d ${LLVM_SRC}; then + git clone http://llvm.org/git/llvm.git ${LLVM_SRC} +fi + +if ! test -d ${POLLY_SRC}; then + git clone http://llvm.org/git/polly.git ${POLLY_SRC} +fi + +${POLLY_SRC}/utils/checkout_cloog.sh ${CLOOG_SRC} +cd ${CLOOG_SRC} + +if ! test -e ${CLOOG_SRC}/config.log; then + ./configure --prefix=${CLOOG_INSTALL} +fi +make +make install +cd ${BASE} + +if ! test -d ${POCC_DIR}; then + wget http://www.cse.ohio-state.edu/~pouchet/software/pocc/download/pocc-1.0-rc3.1-full.tar.gz + tar xzf pocc-1.0-rc3.1-full.tar.gz + cd ${POCC_DIR} + ./install.sh + cd ${BASE} +fi +export PATH=${POCC_DIR}/bin:$PATH + +if ! test -d ${SCOPLIB_DIR}; then + wget http://www.cse.ohio-state.edu/~pouchet/software/pocc/download/modules/scoplib-0.2.0.tar.gz + tar xzf scoplib-0.2.0.tar.gz + cd ${SCOPLIB_DIR} + ./configure --enable-mp-version --prefix=${SCOPLIB_DIR}/usr + make -j${procs} -l${procs} && make install +fi + +mkdir -p ${LLVM_BUILD} +cd ${LLVM_BUILD} + +if which cmake ; then + cmake -DCMAKE_PREFIX_PATH=${CLOOG_INSTALL} ${LLVM_SRC} + make -j$procs -l$procs + make polly-test +else + ${LLVM_SRC}/configure --with-cloog=${CLOOG_INSTALL} --with-isl=${CLOOG_INSTALL} + make -j$procs -l$procs + make polly-test -C tools/polly/test/ +fi From benny.kra at googlemail.com Wed Jan 4 14:20:08 2012 From: benny.kra at googlemail.com (Benjamin Kramer) Date: Wed, 04 Jan 2012 20:20:08 -0000 Subject: [llvm-commits] [llvm] r147544 - /llvm/trunk/include/llvm/Analysis/Dominators.h Message-ID: <20120104202008.CDCD12A6C12C@llvm.org> Author: d0k Date: Wed Jan 4 14:20:08 2012 New Revision: 147544 URL: http://llvm.org/viewvc/llvm-project?rev=147544&view=rev Log: Simplify code. No functionality change. Using DenseMap iterators isn't free as they have to check for empty buckets. Dominator queries are common so this gives a minor speedup. Modified: llvm/trunk/include/llvm/Analysis/Dominators.h Modified: llvm/trunk/include/llvm/Analysis/Dominators.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Analysis/Dominators.h?rev=147544&r1=147543&r2=147544&view=diff ============================================================================== --- llvm/trunk/include/llvm/Analysis/Dominators.h (original) +++ llvm/trunk/include/llvm/Analysis/Dominators.h Wed Jan 4 14:20:08 2012 @@ -321,8 +321,7 @@ /// block. This is the same as using operator[] on this class. /// inline DomTreeNodeBase *getNode(NodeT *BB) const { - typename DomTreeNodeMapType::const_iterator I = DomTreeNodes.find(BB); - return I != DomTreeNodes.end() ? I->second : 0; + return DomTreeNodes.lookup(BB); } /// getRootNode - This returns the entry node for the CFG of the function. If @@ -623,9 +622,8 @@ } DomTreeNodeBase *getNodeForBlock(NodeT *BB) { - typename DomTreeNodeMapType::iterator I = this->DomTreeNodes.find(BB); - if (I != this->DomTreeNodes.end() && I->second) - return I->second; + if (DomTreeNodeBase *Node = getNode(BB)) + return Node; // Haven't calculated this node yet? Get or calculate the node for the // immediate dominator. @@ -641,8 +639,7 @@ } inline NodeT *getIDom(NodeT *BB) const { - typename DenseMap::const_iterator I = IDoms.find(BB); - return I != IDoms.end() ? I->second : 0; + return IDoms.lookup(BB); } inline void addRoot(NodeT* BB) { From joerg at britannica.bec.de Wed Jan 4 14:39:20 2012 From: joerg at britannica.bec.de (Joerg Sonnenberger) Date: Wed, 4 Jan 2012 21:39:20 +0100 Subject: [llvm-commits] [llvm] r147542 - in /llvm/trunk: autoconf/configure.ac cmake/config-ix.cmake configure include/llvm/Config/config.h.cmake include/llvm/Config/config.h.in include/llvm/Config/llvm-config.h.cmake include/llvm/Config/llvm-config.h.in include/llvm/Support/Host.h lib/Support/CommandLine.cpp lib/Support/TargetRegistry.cpp lib/Support/Unix/Host.inc lib/Support/Windows/Host.inc projects/sample/autoconf/configure.ac projects/sample/configure In-Reply-To: <20120104194723.7F0572A6C12C@llvm.org> References: <20120104194723.7F0572A6C12C@llvm.org> Message-ID: <20120104203920.GA25733@britannica.bec.de> On Wed, Jan 04, 2012 at 07:47:23PM -0000, Sebastian Pop wrote: > use getHostTriple instead of getDefaultTargetTriple in getClosestTargetForJIT > > Get back getHostTriple. > > For JIT compilation, use the host triple instead of the default > target: this fixes some JIT testcases that used to fail when the > compiler has been configured as a cross compiler. I think this is wrong. Can such changes please discussed before? Strictly speaking, running e.g. i386-linux on x86_64-netbsd is a cross-compiler. It can never the less work. If the only reason for this complications is the test suite, you should teach it to skip JIT for the cross-compilation case. Joerg From baldrick at free.fr Wed Jan 4 14:47:22 2012 From: baldrick at free.fr (Duncan Sands) Date: Wed, 04 Jan 2012 21:47:22 +0100 Subject: [llvm-commits] [llvm] r146822 - in /llvm/trunk: lib/Transforms/Utils/SimplifyCFG.cpp test/Transforms/SimplifyCFG/PredictNestedBranch.ll In-Reply-To: <20111217063238.57E6C2A6C12C@llvm.org> References: <20111217063238.57E6C2A6C12C@llvm.org> Message-ID: <4F04BADA.5090403@free.fr> Hi Peter, > SimplifyCFG now predicts some conditional branches to true or false depending on previous branch on same comparison operands. > > For example, > > if (a == b) { > if (a> b) // this is false if b is a constant then GVN will replace all instances of a with b in the if block, resulting in "if (b > b)" which will then be simplified to false. The GVN code could easily be taught to also handle the case in which b is not a constant. In fact that's how I first did it, but it didn't result in many improvements, so I didn't think it was worth the (small) compile time cost and so I committed the "constant b only" version instead. It would be easy to resurrect it. It only does something useful when the original condition is == (or !=), but since it would replace a by b everywhere in the block it can simplify all kinds of things in the block. What do you think - worth boosting the GVN code? Ciao, Duncan. > > Fixes some of the issues on > > Added: > llvm/trunk/test/Transforms/SimplifyCFG/PredictNestedBranch.ll > Modified: > llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp > > Modified: llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp?rev=146822&r1=146821&r2=146822&view=diff > ============================================================================== > --- llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp (original) > +++ llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp Sat Dec 17 00:32:38 2011 > @@ -12,6 +12,7 @@ > //===----------------------------------------------------------------------===// > > #define DEBUG_TYPE "simplifycfg" > +#include "llvm/Transforms/Utils/CmpInstAnalysis.h" > #include "llvm/Transforms/Utils/Local.h" > #include "llvm/Constants.h" > #include "llvm/Instructions.h" > @@ -1702,6 +1703,47 @@ > } > } > > + // Treat "if (cond1) { if (cond2) {} }" as "cond1& cond2" and fold. > + // This gives us the value of what cond2 is given cond1 is already known to > + // be true. > + if (ICmpInst *LHS = dyn_cast(PBI->getCondition())) { > + if (ICmpInst *RHS = dyn_cast(BI->getCondition())) { > + ICmpInst::Predicate LHSCC = LHS->getPredicate(), > + RHSCC = RHS->getPredicate(); > + if (PredicatesFoldable(LHSCC, RHSCC)) { > + if (LHS->getOperand(0) == RHS->getOperand(1)&& > + LHS->getOperand(1) == RHS->getOperand(0)) > + LHS->swapOperands(); > + if (LHS->getOperand(0) == RHS->getOperand(0)&& > + LHS->getOperand(1) == RHS->getOperand(1)&& > + BB->getSinglePredecessor()) { > + Value *Op0 = LHS->getOperand(0), *Op1 = LHS->getOperand(1); > + bool CondIsTrue = PBI->getSuccessor(0) == BB; > + unsigned LHSCode = getICmpCode(LHS, !CondIsTrue); > + unsigned RHSCode = getICmpCode(RHS); > + unsigned Code = LHSCode& RHSCode; > + > + Value *ConstantCondition = NULL; > + // If the resultant code is the same as the LHS code then as that > + // code is known to be true we can make RHS now be true. > + if (Code == LHSCode) > + ConstantCondition = ConstantInt::get( > + CmpInst::makeCmpResultType(LHS->getType()), 1); > + else { > + bool isSigned = LHS->isSigned() || RHS->isSigned(); > + CmpInst::Predicate IgnoredNewPred; > + ConstantCondition = getICmpValue(isSigned, Code, Op0, Op1, > + IgnoredNewPred); > + } > + if (ConstantCondition) { > + RHS->replaceAllUsesWith(ConstantCondition); > + return true; > + } > + } > + } > + } > + } > + > // If this is a conditional branch in an empty block, and if any > // predecessors is a conditional branch to one of our destinations, > // fold the conditions into logical ops and one cond br. > > Added: llvm/trunk/test/Transforms/SimplifyCFG/PredictNestedBranch.ll > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/SimplifyCFG/PredictNestedBranch.ll?rev=146822&view=auto > ============================================================================== > --- llvm/trunk/test/Transforms/SimplifyCFG/PredictNestedBranch.ll (added) > +++ llvm/trunk/test/Transforms/SimplifyCFG/PredictNestedBranch.ll Sat Dec 17 00:32:38 2011 > @@ -0,0 +1,152 @@ > + > +; RUN: opt< %s -simplifycfg -dce -S | FileCheck %s > + > +; Test that when == is true, all 6 comparisons evaluate to true or false > +; ie, a == b implies a> b is false, but a>= b is true, and so on > +define void @testEqTrue(i32 %a, i32 %b) { > +; CHECK: @testEqTrue > +; CHECK: icmp eq i32 %a, %b > +; CHECK: call void @_Z1gi(i32 0) > +; a == b implies a == b > +; CHECK-NEXT: call void @_Z1gi(i32 1) > +; a == b implies a>= b > +; CHECK-NEXT: call void @_Z1gi(i32 3) > +; a == b implies a<= b > +; CHECK-NEXT: call void @_Z1gi(i32 4) > +; CHECK: ret void > +entry: > + %cmp = icmp eq i32 %a, %b > + br i1 %cmp, label %if.then, label %if.end18 > + > +if.then: ; preds = %entry > + call void @_Z1gi(i32 0) > + %cmp1 = icmp eq i32 %a, %b > + br i1 %cmp1, label %if.then2, label %if.end > + > +if.then2: ; preds = %if.then > + call void @_Z1gi(i32 1) > + br label %if.end > + > +if.end: ; preds = %if.then2, %if.then > + %cmp3 = icmp ne i32 %a, %b > + br i1 %cmp3, label %if.then4, label %if.end5 > + > +if.then4: ; preds = %if.end > + call void @_Z1gi(i32 2) > + br label %if.end5 > + > +if.end5: ; preds = %if.then4, %if.end > + %cmp6 = icmp sge i32 %a, %b > + br i1 %cmp6, label %if.then7, label %if.end8 > + > +if.then7: ; preds = %if.end5 > + call void @_Z1gi(i32 3) > + br label %if.end8 > + > +if.end8: ; preds = %if.then7, %if.end5 > + %cmp9 = icmp sle i32 %a, %b > + br i1 %cmp9, label %if.then10, label %if.end11 > + > +if.then10: ; preds = %if.end8 > + call void @_Z1gi(i32 4) > + br label %if.end11 > + > +if.end11: ; preds = %if.then10, %if.end8 > + %cmp12 = icmp sgt i32 %a, %b > + br i1 %cmp12, label %if.then13, label %if.end14 > + > +if.then13: ; preds = %if.end11 > + call void @_Z1gi(i32 5) > + br label %if.end14 > + > +if.end14: ; preds = %if.then13, %if.end11 > + %cmp15 = icmp slt i32 %a, %b > + br i1 %cmp15, label %if.then16, label %if.end18 > + > +if.then16: ; preds = %if.end14 > + call void @_Z1gi(i32 6) > + br label %if.end18 > + > +if.end18: ; preds = %if.end14, %if.then16, %entry > + ret void > +} > + > +; Test that when == is false, all 6 comparisons evaluate to true or false > +; ie, a == b implies a> b is false, but a>= b is true, and so on > +define void @testEqFalse(i32 %a, i32 %b) { > +; CHECK: @testEqFalse > +; CHECK: icmp eq i32 %a, %b > +; CHECK: call void @_Z1gi(i32 0) > +; CHECK-NOT: call void @_Z1gi(i32 1) > +; CHECK-NOT: icmp ne > +; CHECK: call void @_Z1gi(i32 2) > +; CHECK: icmp sge > +; CHECK: call void @_Z1gi(i32 3) > +; CHECK: icmp sle > +; CHECK: call void @_Z1gi(i32 4) > +; CHECK: icmp sgt > +; CHECK: call void @_Z1gi(i32 5) > +; CHECK: icmp slt > +; CHECK: call void @_Z1gi(i32 6) > +; CHECK: ret void > +entry: > + %cmp = icmp eq i32 %a, %b > + br i1 %cmp, label %if.then, label %if.else > + > +if.then: ; preds = %entry > + call void @_Z1gi(i32 0) > + br label %if.end18 > + > +if.else: > + %cmp1 = icmp eq i32 %a, %b > + br i1 %cmp1, label %if.then2, label %if.end > + > +if.then2: ; preds = %if.then > + call void @_Z1gi(i32 1) > + br label %if.end > + > +if.end: ; preds = %if.then2, %if.then > + %cmp3 = icmp ne i32 %a, %b > + br i1 %cmp3, label %if.then4, label %if.end5 > + > +if.then4: ; preds = %if.end > + call void @_Z1gi(i32 2) > + br label %if.end5 > + > +if.end5: ; preds = %if.then4, %if.end > + %cmp6 = icmp sge i32 %a, %b > + br i1 %cmp6, label %if.then7, label %if.end8 > + > +if.then7: ; preds = %if.end5 > + call void @_Z1gi(i32 3) > + br label %if.end8 > + > +if.end8: ; preds = %if.then7, %if.end5 > + %cmp9 = icmp sle i32 %a, %b > + br i1 %cmp9, label %if.then10, label %if.end11 > + > +if.then10: ; preds = %if.end8 > + call void @_Z1gi(i32 4) > + br label %if.end11 > + > +if.end11: ; preds = %if.then10, %if.end8 > + %cmp12 = icmp sgt i32 %a, %b > + br i1 %cmp12, label %if.then13, label %if.end14 > + > +if.then13: ; preds = %if.end11 > + call void @_Z1gi(i32 5) > + br label %if.end14 > + > +if.end14: ; preds = %if.then13, %if.end11 > + %cmp15 = icmp slt i32 %a, %b > + br i1 %cmp15, label %if.then16, label %if.end18 > + > +if.then16: ; preds = %if.end14 > + call void @_Z1gi(i32 6) > + br label %if.end18 > + > +if.end18: ; preds = %if.end14, %if.then16, %entry > + ret void > +} > + > +declare void @_Z1gi(i32) > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From benny.kra at googlemail.com Wed Jan 4 14:45:14 2012 From: benny.kra at googlemail.com (Benjamin Kramer) Date: Wed, 04 Jan 2012 20:45:14 -0000 Subject: [llvm-commits] [llvm] r147546 - /llvm/trunk/include/llvm/ADT/StringMap.h Message-ID: <20120104204514.9F8E42A6C12C@llvm.org> Author: d0k Date: Wed Jan 4 14:45:14 2012 New Revision: 147546 URL: http://llvm.org/viewvc/llvm-project?rev=147546&view=rev Log: StringMap.find never points to an empty bucket or tombstone, skip the check. Modified: llvm/trunk/include/llvm/ADT/StringMap.h Modified: llvm/trunk/include/llvm/ADT/StringMap.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/ADT/StringMap.h?rev=147546&r1=147545&r2=147546&view=diff ============================================================================== --- llvm/trunk/include/llvm/ADT/StringMap.h (original) +++ llvm/trunk/include/llvm/ADT/StringMap.h Wed Jan 4 14:45:14 2012 @@ -280,13 +280,13 @@ iterator find(StringRef Key) { int Bucket = FindKey(Key); if (Bucket == -1) return end(); - return iterator(TheTable+Bucket); + return iterator(TheTable+Bucket, true); } const_iterator find(StringRef Key) const { int Bucket = FindKey(Key); if (Bucket == -1) return end(); - return const_iterator(TheTable+Bucket); + return const_iterator(TheTable+Bucket, true); } /// lookup - Return the entry for the specified key, or a default From spop at codeaurora.org Wed Jan 4 15:14:13 2012 From: spop at codeaurora.org (Sebastian Pop) Date: Wed, 4 Jan 2012 15:14:13 -0600 Subject: [llvm-commits] [llvm] r147542 - in /llvm/trunk: autoconf/configure.ac cmake/config-ix.cmake configure include/llvm/Config/config.h.cmake include/llvm/Config/config.h.in include/llvm/Config/llvm-config.h.cmake include/llvm/Config/llvm-config.h.in Message-ID: On Wed, Jan 4, 2012 at 2:39 PM, Joerg Sonnenberger wrote: > On Wed, Jan 04, 2012 at 07:47:23PM -0000, Sebastian Pop wrote: >> use getHostTriple instead of getDefaultTargetTriple in getClosestTargetForJIT >> >> Get back getHostTriple. >> >> For JIT compilation, use the host triple instead of the default >> target: this fixes some JIT testcases that used to fail when the >> compiler has been configured as a cross compiler. > > I think this is wrong. Can such changes please discussed before? Yes, thanks for speaking up. (For reference, on Dec 27 I have sent a message asking for comments http://lists.cs.uiuc.edu/pipermail/llvmdev/2011-December/046484.html ) > Strictly speaking, running e.g. i386-linux on x86_64-netbsd is a > cross-compiler. It can never the less work. I am sorry to not see all the details of your example, could you please give more details? So you have a cross compiler hosted on x86_64-netbsd and targeting i386-linux. When you run LLVM as a JIT you would like it to run on the host x86_64-netbsd, right? Then it also has to produce code for the host x86_64-netbsd, and not for the target i386-linux, as I'm assuming that the include files are different than your host OS. Am I misunderstanding your example? Thanks for clarifying your point. Sebastian -- Qualcomm Innovation Center, Inc is a member of Code Aurora Forum From peter_cooper at apple.com Wed Jan 4 15:24:32 2012 From: peter_cooper at apple.com (Peter Cooper) Date: Wed, 04 Jan 2012 13:24:32 -0800 Subject: [llvm-commits] [llvm] r146822 - in /llvm/trunk: lib/Transforms/Utils/SimplifyCFG.cpp test/Transforms/SimplifyCFG/PredictNestedBranch.ll In-Reply-To: <4F04BADA.5090403@free.fr> References: <20111217063238.57E6C2A6C12C@llvm.org> <4F04BADA.5090403@free.fr> Message-ID: <0AF83E0A-B4E5-4678-B9E4-D19280A04A0B@apple.com> Hi Duncan I would assume that boosting GVN and replacing all a's with b's in your example, even if not constant would be a good thing. We might then only have one of them live at a time for example. The code in SimplifyCFG is slightly more general in that it can handle other conditions like knowing that 'a < b' means that 'a > b' is false and other such combinations. Thanks, Pete On Jan 4, 2012, at 12:47 PM, Duncan Sands wrote: > Hi Peter, > >> SimplifyCFG now predicts some conditional branches to true or false depending on previous branch on same comparison operands. >> >> For example, >> >> if (a == b) { >> if (a> b) // this is false > > if b is a constant then GVN will replace all instances of a with b in the > if block, resulting in "if (b > b)" which will then be simplified to false. > The GVN code could easily be taught to also handle the case in which b is not > a constant. In fact that's how I first did it, but it didn't result in > many improvements, so I didn't think it was worth the (small) compile time > cost and so I committed the "constant b only" version instead. It would be > easy to resurrect it. It only does something useful when the original > condition is == (or !=), but since it would replace a by b everywhere in the > block it can simplify all kinds of things in the block. What do you think - > worth boosting the GVN code? > > Ciao, Duncan. > >> >> Fixes some of the issues on >> >> Added: >> llvm/trunk/test/Transforms/SimplifyCFG/PredictNestedBranch.ll >> Modified: >> llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp >> >> Modified: llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp >> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp?rev=146822&r1=146821&r2=146822&view=diff >> ============================================================================== >> --- llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp (original) >> +++ llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp Sat Dec 17 00:32:38 2011 >> @@ -12,6 +12,7 @@ >> //===----------------------------------------------------------------------===// >> >> #define DEBUG_TYPE "simplifycfg" >> +#include "llvm/Transforms/Utils/CmpInstAnalysis.h" >> #include "llvm/Transforms/Utils/Local.h" >> #include "llvm/Constants.h" >> #include "llvm/Instructions.h" >> @@ -1702,6 +1703,47 @@ >> } >> } >> >> + // Treat "if (cond1) { if (cond2) {} }" as "cond1& cond2" and fold. >> + // This gives us the value of what cond2 is given cond1 is already known to >> + // be true. >> + if (ICmpInst *LHS = dyn_cast(PBI->getCondition())) { >> + if (ICmpInst *RHS = dyn_cast(BI->getCondition())) { >> + ICmpInst::Predicate LHSCC = LHS->getPredicate(), >> + RHSCC = RHS->getPredicate(); >> + if (PredicatesFoldable(LHSCC, RHSCC)) { >> + if (LHS->getOperand(0) == RHS->getOperand(1)&& >> + LHS->getOperand(1) == RHS->getOperand(0)) >> + LHS->swapOperands(); >> + if (LHS->getOperand(0) == RHS->getOperand(0)&& >> + LHS->getOperand(1) == RHS->getOperand(1)&& >> + BB->getSinglePredecessor()) { >> + Value *Op0 = LHS->getOperand(0), *Op1 = LHS->getOperand(1); >> + bool CondIsTrue = PBI->getSuccessor(0) == BB; >> + unsigned LHSCode = getICmpCode(LHS, !CondIsTrue); >> + unsigned RHSCode = getICmpCode(RHS); >> + unsigned Code = LHSCode& RHSCode; >> + >> + Value *ConstantCondition = NULL; >> + // If the resultant code is the same as the LHS code then as that >> + // code is known to be true we can make RHS now be true. >> + if (Code == LHSCode) >> + ConstantCondition = ConstantInt::get( >> + CmpInst::makeCmpResultType(LHS->getType()), 1); >> + else { >> + bool isSigned = LHS->isSigned() || RHS->isSigned(); >> + CmpInst::Predicate IgnoredNewPred; >> + ConstantCondition = getICmpValue(isSigned, Code, Op0, Op1, >> + IgnoredNewPred); >> + } >> + if (ConstantCondition) { >> + RHS->replaceAllUsesWith(ConstantCondition); >> + return true; >> + } >> + } >> + } >> + } >> + } >> + >> // If this is a conditional branch in an empty block, and if any >> // predecessors is a conditional branch to one of our destinations, >> // fold the conditions into logical ops and one cond br. >> >> Added: llvm/trunk/test/Transforms/SimplifyCFG/PredictNestedBranch.ll >> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/SimplifyCFG/PredictNestedBranch.ll?rev=146822&view=auto >> ============================================================================== >> --- llvm/trunk/test/Transforms/SimplifyCFG/PredictNestedBranch.ll (added) >> +++ llvm/trunk/test/Transforms/SimplifyCFG/PredictNestedBranch.ll Sat Dec 17 00:32:38 2011 >> @@ -0,0 +1,152 @@ >> + >> +; RUN: opt< %s -simplifycfg -dce -S | FileCheck %s >> + >> +; Test that when == is true, all 6 comparisons evaluate to true or false >> +; ie, a == b implies a> b is false, but a>= b is true, and so on >> +define void @testEqTrue(i32 %a, i32 %b) { >> +; CHECK: @testEqTrue >> +; CHECK: icmp eq i32 %a, %b >> +; CHECK: call void @_Z1gi(i32 0) >> +; a == b implies a == b >> +; CHECK-NEXT: call void @_Z1gi(i32 1) >> +; a == b implies a>= b >> +; CHECK-NEXT: call void @_Z1gi(i32 3) >> +; a == b implies a<= b >> +; CHECK-NEXT: call void @_Z1gi(i32 4) >> +; CHECK: ret void >> +entry: >> + %cmp = icmp eq i32 %a, %b >> + br i1 %cmp, label %if.then, label %if.end18 >> + >> +if.then: ; preds = %entry >> + call void @_Z1gi(i32 0) >> + %cmp1 = icmp eq i32 %a, %b >> + br i1 %cmp1, label %if.then2, label %if.end >> + >> +if.then2: ; preds = %if.then >> + call void @_Z1gi(i32 1) >> + br label %if.end >> + >> +if.end: ; preds = %if.then2, %if.then >> + %cmp3 = icmp ne i32 %a, %b >> + br i1 %cmp3, label %if.then4, label %if.end5 >> + >> +if.then4: ; preds = %if.end >> + call void @_Z1gi(i32 2) >> + br label %if.end5 >> + >> +if.end5: ; preds = %if.then4, %if.end >> + %cmp6 = icmp sge i32 %a, %b >> + br i1 %cmp6, label %if.then7, label %if.end8 >> + >> +if.then7: ; preds = %if.end5 >> + call void @_Z1gi(i32 3) >> + br label %if.end8 >> + >> +if.end8: ; preds = %if.then7, %if.end5 >> + %cmp9 = icmp sle i32 %a, %b >> + br i1 %cmp9, label %if.then10, label %if.end11 >> + >> +if.then10: ; preds = %if.end8 >> + call void @_Z1gi(i32 4) >> + br label %if.end11 >> + >> +if.end11: ; preds = %if.then10, %if.end8 >> + %cmp12 = icmp sgt i32 %a, %b >> + br i1 %cmp12, label %if.then13, label %if.end14 >> + >> +if.then13: ; preds = %if.end11 >> + call void @_Z1gi(i32 5) >> + br label %if.end14 >> + >> +if.end14: ; preds = %if.then13, %if.end11 >> + %cmp15 = icmp slt i32 %a, %b >> + br i1 %cmp15, label %if.then16, label %if.end18 >> + >> +if.then16: ; preds = %if.end14 >> + call void @_Z1gi(i32 6) >> + br label %if.end18 >> + >> +if.end18: ; preds = %if.end14, %if.then16, %entry >> + ret void >> +} >> + >> +; Test that when == is false, all 6 comparisons evaluate to true or false >> +; ie, a == b implies a> b is false, but a>= b is true, and so on >> +define void @testEqFalse(i32 %a, i32 %b) { >> +; CHECK: @testEqFalse >> +; CHECK: icmp eq i32 %a, %b >> +; CHECK: call void @_Z1gi(i32 0) >> +; CHECK-NOT: call void @_Z1gi(i32 1) >> +; CHECK-NOT: icmp ne >> +; CHECK: call void @_Z1gi(i32 2) >> +; CHECK: icmp sge >> +; CHECK: call void @_Z1gi(i32 3) >> +; CHECK: icmp sle >> +; CHECK: call void @_Z1gi(i32 4) >> +; CHECK: icmp sgt >> +; CHECK: call void @_Z1gi(i32 5) >> +; CHECK: icmp slt >> +; CHECK: call void @_Z1gi(i32 6) >> +; CHECK: ret void >> +entry: >> + %cmp = icmp eq i32 %a, %b >> + br i1 %cmp, label %if.then, label %if.else >> + >> +if.then: ; preds = %entry >> + call void @_Z1gi(i32 0) >> + br label %if.end18 >> + >> +if.else: >> + %cmp1 = icmp eq i32 %a, %b >> + br i1 %cmp1, label %if.then2, label %if.end >> + >> +if.then2: ; preds = %if.then >> + call void @_Z1gi(i32 1) >> + br label %if.end >> + >> +if.end: ; preds = %if.then2, %if.then >> + %cmp3 = icmp ne i32 %a, %b >> + br i1 %cmp3, label %if.then4, label %if.end5 >> + >> +if.then4: ; preds = %if.end >> + call void @_Z1gi(i32 2) >> + br label %if.end5 >> + >> +if.end5: ; preds = %if.then4, %if.end >> + %cmp6 = icmp sge i32 %a, %b >> + br i1 %cmp6, label %if.then7, label %if.end8 >> + >> +if.then7: ; preds = %if.end5 >> + call void @_Z1gi(i32 3) >> + br label %if.end8 >> + >> +if.end8: ; preds = %if.then7, %if.end5 >> + %cmp9 = icmp sle i32 %a, %b >> + br i1 %cmp9, label %if.then10, label %if.end11 >> + >> +if.then10: ; preds = %if.end8 >> + call void @_Z1gi(i32 4) >> + br label %if.end11 >> + >> +if.end11: ; preds = %if.then10, %if.end8 >> + %cmp12 = icmp sgt i32 %a, %b >> + br i1 %cmp12, label %if.then13, label %if.end14 >> + >> +if.then13: ; preds = %if.end11 >> + call void @_Z1gi(i32 5) >> + br label %if.end14 >> + >> +if.end14: ; preds = %if.then13, %if.end11 >> + %cmp15 = icmp slt i32 %a, %b >> + br i1 %cmp15, label %if.then16, label %if.end18 >> + >> +if.then16: ; preds = %if.end14 >> + call void @_Z1gi(i32 6) >> + br label %if.end18 >> + >> +if.end18: ; preds = %if.end14, %if.then16, %entry >> + ret void >> +} >> + >> +declare void @_Z1gi(i32) >> >> >> _______________________________________________ >> llvm-commits mailing list >> llvm-commits at cs.uiuc.edu >> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From apazos at codeaurora.org Wed Jan 4 15:41:39 2012 From: apazos at codeaurora.org (Ana Pazos) Date: Wed, 4 Jan 2012 13:41:39 -0800 Subject: [llvm-commits] LLVM patch to support ARM fused multiply add/subtract instructions Message-ID: <027a01cccb29$a4709100$ed51b300$@org> Hello folks, Some ARMv7-A processor implementations (e.g, Qualcomm 8960, ARM Cortex-A5) support fused multiply add/subtract instructions (VFMA/VFMS) which have lower latency and greater accuracy than the chained multiply add/subtract instructions (VMLA/VMLS). I have modified LLVM ARM target files to add support for fused multiply add/subtract instructions. A processor definition just needs to add 'FeatureNEONVFP4' to its list of subtarget features in order to enable the generation of fused multiply add/subtract instructions. The patch is attached for your review, if you have interest in merging this change into LLVM. Patch details: fusedMACpatch.diff Changes to ARM-specific files to support fused multiply add/subtract instructions. Associated fused multiply add/subtract instructions with processor subtarget feature 'FeatureNEONVFP4' and with the assembler feature flag 'neon-vfpv4' . fusedMAC.ll Test to check for generated fused multiply accumulate and subtract instructions. failures.txt Failure report from running llvm/test and projects/test-suite on ARM. Thank you, Ana. -- Qualcomm Innovation Center, Inc is a member of Code Aurora Forum -------------- next part -------------- An HTML attachment was scrubbed... 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Name: failures.txt Url: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20120104/3eb89ad0/attachment-0001.txt From benny.kra at googlemail.com Wed Jan 4 15:41:24 2012 From: benny.kra at googlemail.com (Benjamin Kramer) Date: Wed, 04 Jan 2012 21:41:24 -0000 Subject: [llvm-commits] [llvm] r147550 - in /llvm/trunk/include/llvm: Analysis/LoopInfo.h CodeGen/SlotIndexes.h Message-ID: <20120104214124.5F1CA2A6C12C@llvm.org> Author: d0k Date: Wed Jan 4 15:41:24 2012 New Revision: 147550 URL: http://llvm.org/viewvc/llvm-project?rev=147550&view=rev Log: Simplify more DenseMap.find users. Modified: llvm/trunk/include/llvm/Analysis/LoopInfo.h llvm/trunk/include/llvm/CodeGen/SlotIndexes.h Modified: llvm/trunk/include/llvm/Analysis/LoopInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Analysis/LoopInfo.h?rev=147550&r1=147549&r2=147550&view=diff ============================================================================== --- llvm/trunk/include/llvm/Analysis/LoopInfo.h (original) +++ llvm/trunk/include/llvm/Analysis/LoopInfo.h Wed Jan 4 15:41:24 2012 @@ -655,9 +655,7 @@ /// block is in no loop (for example the entry node), null is returned. /// LoopT *getLoopFor(const BlockT *BB) const { - typename DenseMap::const_iterator I= - BBMap.find(const_cast(BB)); - return I != BBMap.end() ? I->second : 0; + return BBMap.lookup(const_cast(BB)); } /// operator[] - same as getLoopFor... @@ -696,9 +694,7 @@ /// the loop hierarchy tree. void changeLoopFor(BlockT *BB, LoopT *L) { if (!L) { - typename DenseMap::iterator I = BBMap.find(BB); - if (I != BBMap.end()) - BBMap.erase(I); + BBMap.erase(BB); return; } BBMap[BB] = L; @@ -755,7 +751,7 @@ } LoopT *ConsiderForLoop(BlockT *BB, DominatorTreeBase &DT) { - if (BBMap.find(BB) != BBMap.end()) return 0;// Haven't processed this node? + if (BBMap.count(BB)) return 0; // Haven't processed this node? std::vector TodoStack; Modified: llvm/trunk/include/llvm/CodeGen/SlotIndexes.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/SlotIndexes.h?rev=147550&r1=147549&r2=147550&view=diff ============================================================================== --- llvm/trunk/include/llvm/CodeGen/SlotIndexes.h (original) +++ llvm/trunk/include/llvm/CodeGen/SlotIndexes.h Wed Jan 4 15:41:24 2012 @@ -488,7 +488,7 @@ /// Returns true if the given machine instr is mapped to an index, /// otherwise returns false. bool hasIndex(const MachineInstr *instr) const { - return (mi2iMap.find(instr) != mi2iMap.end()); + return mi2iMap.count(instr); } /// Returns the base index for the given instruction. From andy.zhang at intel.com Wed Jan 4 16:03:58 2012 From: andy.zhang at intel.com (Zhang, Andy) Date: Wed, 4 Jan 2012 22:03:58 +0000 Subject: [llvm-commits] Intel Atom optimization - use LEA to adjust stack pointer In-Reply-To: <5CED04BC-2514-4235-9364-9FFB13E415EE@2pi.dk> References: <9A83F73AEA08BB46A2799C5D4C16BFED011A38BC09@rrsmsx509.amr.corp.intel.com> <5C9B2DB6AAFD914E864AF9803780B66A7EAC@FMSMSX108.amr.corp.intel.com> <5CED04BC-2514-4235-9364-9FFB13E415EE@2pi.dk> Message-ID: <5C9B2DB6AAFD914E864AF9803780B66A976F@FMSMSX108.amr.corp.intel.com> On Friday, December 23, 2011 11:06 PM, Jakob Stoklund Olesen wrote: > On Dec 23, 2011, at 10:23 AM, Zhang, Andy wrote: > > Hi Andy, > > Please submit the TableGen changes as an independent patch. > > From a quick glance, you also need to make sure you follow LLVM's style > for braces etc. > > if (isSub) > + { > MI->setFlag(MachineInstr::FrameSetup); > - MI->getOperand(3).setIsDead(); // The EFLAGS implicit def is dead. > + } > > Why add braces here? > > /jakob Hi Jakob, I removed the braces from the single-statement if-statement blocks and updated the patch. Do you see any other issues? Regards, Andy -------------- next part -------------- A non-text attachment was scrubbed... Name: lea_sp.diff Type: application/octet-stream Size: 10689 bytes Desc: lea_sp.diff Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20120104/1c07bc14/attachment.obj From joerg at britannica.bec.de Wed Jan 4 16:06:46 2012 From: joerg at britannica.bec.de (Joerg Sonnenberger) Date: Wed, 4 Jan 2012 23:06:46 +0100 Subject: [llvm-commits] [llvm] r147542 - in /llvm/trunk: autoconf/configure.ac cmake/config-ix.cmake configure include/llvm/Config/config.h.cmake include/llvm/Config/config.h.in include/llvm/Config/llvm-config.h.cmake include/llvm/Config/llvm-config.h.in In-Reply-To: References: Message-ID: <20120104220646.GA27691@britannica.bec.de> On Wed, Jan 04, 2012 at 03:14:13PM -0600, Sebastian Pop wrote: > > Strictly speaking, running e.g. i386-linux on x86_64-netbsd is a > > cross-compiler. It can never the less work. > > I am sorry to not see all the details of your example, > could you please give more details? So you have a cross compiler > hosted on x86_64-netbsd and targeting i386-linux. When you run > LLVM as a JIT you would like it to run on the host x86_64-netbsd, right? > Then it also has to produce code for the host x86_64-netbsd, and not > for the target i386-linux, as I'm assuming that the include files are > different than your host OS. No, it doesn't have to run code for x86_64-netbsd. I can build the LLVM libraries for i386-linux, link it, run it and it will work. Sure, I likely have to provide it with Linux compatible header files etc like using cross-compilation in general. My point remains that just because I am cross-compiling doesn't mean I can't execute JIT code. Joerg From benny.kra at googlemail.com Wed Jan 4 16:06:45 2012 From: benny.kra at googlemail.com (Benjamin Kramer) Date: Wed, 04 Jan 2012 22:06:45 -0000 Subject: [llvm-commits] [llvm] r147553 - /llvm/trunk/lib/Target/X86/Disassembler/X86DisassemblerDecoder.c Message-ID: <20120104220645.C7E3D2A6C12C@llvm.org> Author: d0k Date: Wed Jan 4 16:06:45 2012 New Revision: 147553 URL: http://llvm.org/viewvc/llvm-project?rev=147553&view=rev Log: Silence warnings of a mysterious compiler that still defaults to C89. Modified: llvm/trunk/lib/Target/X86/Disassembler/X86DisassemblerDecoder.c Modified: llvm/trunk/lib/Target/X86/Disassembler/X86DisassemblerDecoder.c URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/Disassembler/X86DisassemblerDecoder.c?rev=147553&r1=147552&r2=147553&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/Disassembler/X86DisassemblerDecoder.c (original) +++ llvm/trunk/lib/Target/X86/Disassembler/X86DisassemblerDecoder.c Wed Jan 4 16:06:45 2012 @@ -1502,8 +1502,8 @@ return -1; case ENCODING_IB: if (sawRegImm) { - // Saw a register immediate so don't read again and instead split the - // previous immediate. FIXME: This is a hack + /* Saw a register immediate so don't read again and instead split the + previous immediate. FIXME: This is a hack. */ insn->immediates[insn->numImmediatesConsumed] = insn->immediates[insn->numImmediatesConsumed - 1] & 0xf; ++insn->numImmediatesConsumed; From gohman at apple.com Wed Jan 4 17:01:10 2012 From: gohman at apple.com (Dan Gohman) Date: Wed, 04 Jan 2012 23:01:10 -0000 Subject: [llvm-commits] [llvm] r147560 - in /llvm/trunk: include/llvm/Analysis/ValueTracking.h lib/Analysis/ValueTracking.cpp Message-ID: <20120104230110.3CC2A2A6C12C@llvm.org> Author: djg Date: Wed Jan 4 17:01:09 2012 New Revision: 147560 URL: http://llvm.org/viewvc/llvm-project?rev=147560&view=rev Log: Generalize isSafeToSpeculativelyExecute to work on arbitrary Values, rather than just Instructions, since it's interesting for ConstantExprs too. Modified: llvm/trunk/include/llvm/Analysis/ValueTracking.h llvm/trunk/lib/Analysis/ValueTracking.cpp Modified: llvm/trunk/include/llvm/Analysis/ValueTracking.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Analysis/ValueTracking.h?rev=147560&r1=147559&r2=147560&view=diff ============================================================================== --- llvm/trunk/include/llvm/Analysis/ValueTracking.h (original) +++ llvm/trunk/include/llvm/Analysis/ValueTracking.h Wed Jan 4 17:01:09 2012 @@ -174,7 +174,7 @@ /// the correct dominance relationships for the operands and users hold. /// However, this method can return true for instructions that read memory; /// for such instructions, moving them may change the resulting value. - bool isSafeToSpeculativelyExecute(const Instruction *Inst, + bool isSafeToSpeculativelyExecute(const Value *V, const TargetData *TD = 0); } // end namespace llvm Modified: llvm/trunk/lib/Analysis/ValueTracking.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/ValueTracking.cpp?rev=147560&r1=147559&r2=147560&view=diff ============================================================================== --- llvm/trunk/lib/Analysis/ValueTracking.cpp (original) +++ llvm/trunk/lib/Analysis/ValueTracking.cpp Wed Jan 4 17:01:09 2012 @@ -1879,8 +1879,12 @@ return true; } -bool llvm::isSafeToSpeculativelyExecute(const Instruction *Inst, +bool llvm::isSafeToSpeculativelyExecute(const Value *V, const TargetData *TD) { + const Operator *Inst = dyn_cast(V); + if (!Inst) + return false; + for (unsigned i = 0, e = Inst->getNumOperands(); i != e; ++i) if (Constant *C = dyn_cast(Inst->getOperand(i))) if (C->canTrap()) From anton at korobeynikov.info Wed Jan 4 17:06:28 2012 From: anton at korobeynikov.info (Anton Korobeynikov) Date: Thu, 5 Jan 2012 03:06:28 +0400 Subject: [llvm-commits] LLVM patch to support ARM fused multiply add/subtract instructions In-Reply-To: <027a01cccb29$a4709100$ed51b300$@org> References: <027a01cccb29$a4709100$ed51b300$@org> Message-ID: Hello Ana, > Some ARMv7-A processor implementations ?(e.g, Qualcomm 8960, ARM Cortex-A5) > support fused multiply add/subtract instructions (VFMA/VFMS) which have > lower latency and greater accuracy than the chained multiply add/subtract > instructions (VMLA/VMLS). Patch generally looks ok. However, I'm not sure it's complete wrt build attributes. You're emitting only text version of neon attribute. What's about the .fpu stuff and around ? Look into ARMAsmPrinter.cpp a bit further than your changed lines here. What if our CPU does not support NEON at all, should we emit something like ".fpu vfpv4" ? -- With best regards, Anton Korobeynikov Faculty of Mathematics and Mechanics, Saint Petersburg State University From kledzik at apple.com Wed Jan 4 17:58:18 2012 From: kledzik at apple.com (Nick Kledzik) Date: Wed, 04 Jan 2012 23:58:18 -0000 Subject: [llvm-commits] [lld] r147571 - in /lld/trunk: include/lld/Core/Atom.h include/lld/Core/Reference.h include/lld/Core/UndefinedAtom.h lib/Core/CMakeLists.txt lib/Core/SymbolTable.cpp lib/Core/YamlKeyValues.cpp lib/Core/YamlKeyValues.h lib/Core/YamlReader.cpp lib/Core/YamlWriter.cpp test/auto-hide-coalesce.objtxt test/custom-section.objtxt test/dead-strip-attributes.objtxt test/internal-name-attributes.objtxt test/multiple-def-error.objtxt test/tent-merge.objtxt test/weak-coalesce.objtxt Message-ID: <20120104235818.6FBE42A6C12C@llvm.org> Author: kledzik Date: Wed Jan 4 17:58:17 2012 New Revision: 147571 URL: http://llvm.org/viewvc/llvm-project?rev=147571&view=rev Log: Support more Atom attributes. Add more test cases to lld-core Added: lld/trunk/lib/Core/YamlKeyValues.cpp lld/trunk/lib/Core/YamlKeyValues.h lld/trunk/test/auto-hide-coalesce.objtxt lld/trunk/test/custom-section.objtxt lld/trunk/test/dead-strip-attributes.objtxt lld/trunk/test/internal-name-attributes.objtxt Modified: lld/trunk/include/lld/Core/Atom.h lld/trunk/include/lld/Core/Reference.h lld/trunk/include/lld/Core/UndefinedAtom.h lld/trunk/lib/Core/CMakeLists.txt lld/trunk/lib/Core/SymbolTable.cpp lld/trunk/lib/Core/YamlReader.cpp lld/trunk/lib/Core/YamlWriter.cpp lld/trunk/test/multiple-def-error.objtxt lld/trunk/test/tent-merge.objtxt lld/trunk/test/weak-coalesce.objtxt Modified: lld/trunk/include/lld/Core/Atom.h URL: http://llvm.org/viewvc/llvm-project/lld/trunk/include/lld/Core/Atom.h?rev=147571&r1=147570&r2=147571&view=diff ============================================================================== --- lld/trunk/include/lld/Core/Atom.h (original) +++ lld/trunk/include/lld/Core/Atom.h Wed Jan 4 17:58:17 2012 @@ -336,7 +336,8 @@ , ContentType ct , SectionChoice sc , bool internalName - , bool md + , bool mergeDupes + , bool autoHide , DeadStripKind ds , bool IsThumb , bool IsAlias @@ -344,16 +345,18 @@ : _address(ord) , _alignmentModulus(a.modulus) , _alignmentPowerOf2(a.powerOf2) + , _contentType(ct) , _definition(d) + , _scope(s) + , _sectionChoice(sc) , _internalName(internalName) , _deadStrip(ds) , _mode(modeOrdinal) - , _mergeDuplicates(md) + , _mergeDuplicates(mergeDupes) , _thumb(IsThumb) + , _autoHide(autoHide) , _alias(IsAlias) - , _contentType(ct) - , _scope(s) - , _sectionChoice(sc) {} + {} protected: Modified: lld/trunk/include/lld/Core/Reference.h URL: http://llvm.org/viewvc/llvm-project/lld/trunk/include/lld/Core/Reference.h?rev=147571&r1=147570&r2=147571&view=diff ============================================================================== --- lld/trunk/include/lld/Core/Reference.h (original) +++ lld/trunk/include/lld/Core/Reference.h Wed Jan 4 17:58:17 2012 @@ -10,7 +10,8 @@ #ifndef LLD_CORE_REFERENCES_H_ #define LLD_CORE_REFERENCES_H_ -#include "llvm/Support/DataTypes.h" +#include + namespace lld { Modified: lld/trunk/include/lld/Core/UndefinedAtom.h URL: http://llvm.org/viewvc/llvm-project/lld/trunk/include/lld/Core/UndefinedAtom.h?rev=147571&r1=147570&r2=147571&view=diff ============================================================================== --- lld/trunk/include/lld/Core/UndefinedAtom.h (original) +++ lld/trunk/include/lld/Core/UndefinedAtom.h Wed Jan 4 17:58:17 2012 @@ -28,6 +28,7 @@ , Atom::sectionBasedOnContent , false , false + , false , deadStripNormal , false , false Modified: lld/trunk/lib/Core/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/lld/trunk/lib/Core/CMakeLists.txt?rev=147571&r1=147570&r2=147571&view=diff ============================================================================== --- lld/trunk/lib/Core/CMakeLists.txt (original) +++ lld/trunk/lib/Core/CMakeLists.txt Wed Jan 4 17:58:17 2012 @@ -3,6 +3,7 @@ File.cpp Resolver.cpp SymbolTable.cpp + YamlKeyValues.cpp YamlReader.cpp YamlWriter.cpp ) Modified: lld/trunk/lib/Core/SymbolTable.cpp URL: http://llvm.org/viewvc/llvm-project/lld/trunk/lib/Core/SymbolTable.cpp?rev=147571&r1=147570&r2=147571&view=diff ============================================================================== --- lld/trunk/lib/Core/SymbolTable.cpp (original) +++ lld/trunk/lib/Core/SymbolTable.cpp Wed Jan 4 17:58:17 2012 @@ -84,41 +84,49 @@ llvm::StringRef name = newAtom.name(); const Atom *existing = this->findByName(name); if (existing == NULL) { - // name is not in symbol table yet, add it associate with this atom + // Name is not in symbol table yet, add it associate with this atom. _nameTable[name] = &newAtom; - } else { - // name is already in symbol table and associated with another atom + } + else { + // Name is already in symbol table and associated with another atom. + bool useNew = true; switch (collide(existing->definition(), newAtom.definition())) { case NCR_First: - // using first, just add new to _replacedAtoms - _replacedAtoms[&newAtom] = existing; + useNew = false; break; case NCR_Second: - // using second, update tables - _nameTable[name] = &newAtom; - _replacedAtoms[existing] = &newAtom; + useNew = true; break; case NCR_Dup: if ( existing->mergeDuplicates() && newAtom.mergeDuplicates() ) { - // using existing atom, add new atom to _replacedAtoms - _replacedAtoms[&newAtom] = existing; - } - else { - const Atom& use = _platform.handleMultipleDefinitions(*existing, newAtom); - if ( &use == existing ) { - // using existing atom, add new atom to _replacedAtoms - _replacedAtoms[&newAtom] = existing; + // Both mergeable. Use auto-hide bit as tie breaker + if ( existing->autoHide() != newAtom.autoHide() ) { + // They have different autoHide values, keep non-autohide one + useNew = existing->autoHide(); } else { - // using new atom, update tables - _nameTable[name] = &newAtom; - _replacedAtoms[existing] = &newAtom; + // They have same autoHide, so just keep using existing + useNew = false; } } + else { + const Atom& use = _platform.handleMultipleDefinitions(*existing, newAtom); + useNew = ( &use != existing ); + } break; default: llvm::report_fatal_error("SymbolTable::addByName(): unhandled switch clause"); } + if ( useNew ) { + // Update name table to use new atom. + _nameTable[name] = &newAtom; + // Add existing atom to replacement table. + _replacedAtoms[existing] = &newAtom; + } + else { + // New atom is not being used. Add it to replacement table. + _replacedAtoms[&newAtom] = existing; + } } } Added: lld/trunk/lib/Core/YamlKeyValues.cpp URL: http://llvm.org/viewvc/llvm-project/lld/trunk/lib/Core/YamlKeyValues.cpp?rev=147571&view=auto ============================================================================== --- lld/trunk/lib/Core/YamlKeyValues.cpp (added) +++ lld/trunk/lib/Core/YamlKeyValues.cpp Wed Jan 4 17:58:17 2012 @@ -0,0 +1,330 @@ +//===- Core/YamlKeyValues.cpp - Reads YAML --------------------------------===// +// +// The LLVM Linker +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// + +#include + +#include "YamlKeyValues.h" + +#include "llvm/Support/ErrorHandling.h" + +namespace lld { +namespace yaml { + + +const char* const KeyValues::nameKeyword = "name"; +const char* const KeyValues::scopeKeyword = "scope"; +const char* const KeyValues::definitionKeyword = "definition"; +const char* const KeyValues::contentTypeKeyword = "type"; +const char* const KeyValues::deadStripKindKeyword = "dead-strip"; +const char* const KeyValues::sectionChoiceKeyword = "section-choice"; +const char* const KeyValues::internalNameKeyword = "internal-name"; +const char* const KeyValues::mergeDuplicatesKeyword = "merge-duplicates"; +const char* const KeyValues::autoHideKeyword = "auto-hide"; +const char* const KeyValues::isThumbKeyword = "is-thumb"; +const char* const KeyValues::isAliasKeyword = "is-alias"; +const char* const KeyValues::sectionNameKeyword = "section-name"; +const char* const KeyValues::contentKeyword = "content"; +const char* const KeyValues::sizeKeyword = "size"; + + +const Atom::Scope KeyValues::scopeDefault = Atom::scopeTranslationUnit; +const Atom::Definition KeyValues::definitionDefault = Atom::definitionRegular; +const Atom::ContentType KeyValues::contentTypeDefault = Atom::typeData; +const Atom::DeadStripKind KeyValues::deadStripKindDefault = Atom::deadStripNormal; +const Atom::SectionChoice KeyValues::sectionChoiceDefault = Atom::sectionBasedOnContent; +const bool KeyValues::internalNameDefault = false; +const bool KeyValues::mergeDuplicatesDefault = false; +const bool KeyValues::autoHideDefault = false; +const bool KeyValues::isThumbDefault = false; +const bool KeyValues::isAliasDefault = false; + + +struct ScopeMapping { + const char* string; + Atom::Scope value; +}; + +static const ScopeMapping scopeMappings[] = { + { "global", Atom::scopeGlobal }, + { "hidden", Atom::scopeLinkageUnit }, + { "static", Atom::scopeTranslationUnit }, + { NULL, Atom::scopeGlobal } +}; + +Atom::Scope KeyValues::scope(const char* s) +{ + for (const ScopeMapping* p = scopeMappings; p->string != NULL; ++p) { + if ( strcmp(p->string, s) == 0 ) + return p->value; + } + llvm::report_fatal_error("bad scope value"); +} + +const char* KeyValues::scope(Atom::Scope s) { + for (const ScopeMapping* p = scopeMappings; p->string != NULL; ++p) { + if ( p->value == s ) + return p->string; + } + llvm::report_fatal_error("bad scope value"); +} + + + + + +struct DefinitionMapping { + const char* string; + Atom::Definition value; +}; + +static const DefinitionMapping defMappings[] = { + { "regular", Atom::definitionRegular }, + { "weak", Atom::definitionWeak }, + { "tentative", Atom::definitionTentative }, + { "absolute", Atom::definitionAbsolute }, + { "undefined", Atom::definitionUndefined }, + { "shared-library", Atom::definitionSharedLibrary }, + { NULL, Atom::definitionRegular } +}; + +Atom::Definition KeyValues::definition(const char* s) +{ + for (const DefinitionMapping* p = defMappings; p->string != NULL; ++p) { + if ( strcmp(p->string, s) == 0 ) + return p->value; + } + llvm::report_fatal_error("bad definition value"); +} + +const char* KeyValues::definition(Atom::Definition s) { + for (const DefinitionMapping* p = defMappings; p->string != NULL; ++p) { + if ( p->value == s ) + return p->string; + } + llvm::report_fatal_error("bad definition value"); +} + + + + + +struct ContentTypeMapping { + const char* string; + Atom::ContentType value; +}; + +static const ContentTypeMapping typeMappings[] = { + { "unknown", Atom::typeUnknown }, + { "code", Atom::typeCode }, + { "resolver", Atom::typeResolver }, + { "constant", Atom::typeConstant }, + { "c-string", Atom::typeCString }, + { "utf16-string", Atom::typeUTF16String }, + { "CFI", Atom::typeCFI }, + { "LSDA", Atom::typeLSDA }, + { "literal-4", Atom::typeLiteral4 }, + { "literal-8", Atom::typeLiteral8 }, + { "literal-16", Atom::typeLiteral16 }, + { "data", Atom::typeData }, + { "zero-fill", Atom::typeZeroFill }, + { "cf-string", Atom::typeCFString }, + { "initializer-ptr",Atom::typeInitializerPtr }, + { "terminator-ptr", Atom::typeTerminatorPtr }, + { "c-string-ptr", Atom::typeCStringPtr }, + { "objc1-class", Atom::typeObjC1Class }, + { "objc1-class-ptr",Atom::typeObjCClassPtr }, + { "objc2-cat-ptr", Atom::typeObjC2CategoryList }, + { "tlv-thunk", Atom::typeThunkTLV }, + { "tlv-data", Atom::typeTLVInitialData }, + { "tlv-zero-fill", Atom::typeTLVInitialZeroFill }, + { "tlv-init-ptr", Atom::typeTLVInitializerPtr }, + { NULL, Atom::typeUnknown } +}; + +Atom::ContentType KeyValues::contentType(const char* s) +{ + for (const ContentTypeMapping* p = typeMappings; p->string != NULL; ++p) { + if ( strcmp(p->string, s) == 0 ) + return p->value; + } + llvm::report_fatal_error("bad content type value"); +} + +const char* KeyValues::contentType(Atom::ContentType s) { + for (const ContentTypeMapping* p = typeMappings; p->string != NULL; ++p) { + if ( p->value == s ) + return p->string; + } + llvm::report_fatal_error("bad content type value"); +} + + + + + + + +struct DeadStripMapping { + const char* string; + Atom::DeadStripKind value; +}; + +static const DeadStripMapping deadStripMappings[] = { + { "normal", Atom::deadStripNormal }, + { "never", Atom::deadStripNever }, + { "always", Atom::deadStripAlways }, + { NULL, Atom::deadStripNormal } +}; + +Atom::DeadStripKind KeyValues::deadStripKind(const char* s) +{ + for (const DeadStripMapping* p = deadStripMappings; p->string != NULL; ++p) { + if ( strcmp(p->string, s) == 0 ) + return p->value; + } + llvm::report_fatal_error("bad dead strip value"); +} + +const char* KeyValues::deadStripKind(Atom::DeadStripKind dsk) { + for (const DeadStripMapping* p = deadStripMappings; p->string != NULL; ++p) { + if ( p->value == dsk ) + return p->string; + } + llvm::report_fatal_error("bad dead strip value"); +} + + + + + + +struct SectionChoiceMapping { + const char* string; + Atom::SectionChoice value; +}; + +static const SectionChoiceMapping sectMappings[] = { + { "content", Atom::sectionBasedOnContent }, + { "custom", Atom::sectionCustomPreferred }, + { "custom-required", Atom::sectionCustomRequired }, + { NULL, Atom::sectionBasedOnContent } +}; + +Atom::SectionChoice KeyValues::sectionChoice(const char* s) +{ + for (const SectionChoiceMapping* p = sectMappings; p->string != NULL; ++p) { + if ( strcmp(p->string, s) == 0 ) + return p->value; + } + llvm::report_fatal_error("bad dead strip value"); +} + +const char* KeyValues::sectionChoice(Atom::SectionChoice s) { + for (const SectionChoiceMapping* p = sectMappings; p->string != NULL; ++p) { + if ( p->value == s ) + return p->string; + } + llvm::report_fatal_error("bad dead strip value"); +} + + + + + + + +bool KeyValues::internalName(const char* s) +{ + if ( strcmp(s, "true") == 0 ) + return true; + else if ( strcmp(s, "false") == 0 ) + return false; + llvm::report_fatal_error("bad internal-name value"); +} + +const char* KeyValues::internalName(bool b) { + return b ? "true" : "false"; +} + + + + + + +bool KeyValues::mergeDuplicates(const char* s) +{ + if ( strcmp(s, "true") == 0 ) + return true; + else if ( strcmp(s, "false") == 0 ) + return false; + llvm::report_fatal_error("bad merge-duplicates value"); +} + +const char* KeyValues::mergeDuplicates(bool b) { + return b ? "true" : "false"; +} + + + + + + +bool KeyValues::autoHide(const char* s) +{ + if ( strcmp(s, "true") == 0 ) + return true; + else if ( strcmp(s, "false") == 0 ) + return false; + llvm::report_fatal_error("bad auto-hide value"); +} + +const char* KeyValues::autoHide(bool b) { + return b ? "true" : "false"; +} + + + + + +bool KeyValues::isThumb(const char* s) +{ + if ( strcmp(s, "true") == 0 ) + return true; + else if ( strcmp(s, "false") == 0 ) + return false; + llvm::report_fatal_error("bad is-thumb value"); +} + +const char* KeyValues::isThumb(bool b) { + return b ? "true" : "false"; +} + + + + +bool KeyValues::isAlias(const char* s) +{ + if ( strcmp(s, "true") == 0 ) + return true; + else if ( strcmp(s, "false") == 0 ) + return false; + llvm::report_fatal_error("bad is-alias value"); +} + +const char* KeyValues::isAlias(bool b) { + return b ? "true" : "false"; +} + + + + + + +} // namespace yaml +} // namespace lld Added: lld/trunk/lib/Core/YamlKeyValues.h URL: http://llvm.org/viewvc/llvm-project/lld/trunk/lib/Core/YamlKeyValues.h?rev=147571&view=auto ============================================================================== --- lld/trunk/lib/Core/YamlKeyValues.h (added) +++ lld/trunk/lib/Core/YamlKeyValues.h Wed Jan 4 17:58:17 2012 @@ -0,0 +1,83 @@ +//===- Core/YamlKeyValues.h - Reads YAML ----------------------------------===// +// +// The LLVM Linker +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// + +#ifndef LLD_CORE_YAML_KEY_VALUES_H_ +#define LLD_CORE_YAML_KEY_VALUES_H_ + +#include "lld/Core/Atom.h" + + +namespace lld { +namespace yaml { + +class KeyValues { +public: + static const char* const nameKeyword; + static const char* const sectionNameKeyword; + static const char* const contentKeyword; + static const char* const sizeKeyword; + + + static const char* const scopeKeyword; + static const Atom::Scope scopeDefault; + static Atom::Scope scope(const char*); + static const char* scope(Atom::Scope); + + static const char* const definitionKeyword; + static const Atom::Definition definitionDefault; + static Atom::Definition definition(const char*); + static const char* definition(Atom::Definition); + + static const char* const contentTypeKeyword; + static const Atom::ContentType contentTypeDefault; + static Atom::ContentType contentType(const char*); + static const char* contentType(Atom::ContentType); + + static const char* const deadStripKindKeyword; + static const Atom::DeadStripKind deadStripKindDefault; + static Atom::DeadStripKind deadStripKind(const char*); + static const char* deadStripKind(Atom::DeadStripKind); + + static const char* const sectionChoiceKeyword; + static const Atom::SectionChoice sectionChoiceDefault; + static Atom::SectionChoice sectionChoice(const char*); + static const char* sectionChoice(Atom::SectionChoice); + + static const char* const internalNameKeyword; + static const bool internalNameDefault; + static bool internalName(const char*); + static const char* internalName(bool); + + static const char* const mergeDuplicatesKeyword; + static const bool mergeDuplicatesDefault; + static bool mergeDuplicates(const char*); + static const char* mergeDuplicates(bool); + + static const char* const autoHideKeyword; + static const bool autoHideDefault; + static bool autoHide(const char*); + static const char* autoHide(bool); + + static const char* const isThumbKeyword; + static const bool isThumbDefault; + static bool isThumb(const char*); + static const char* isThumb(bool); + + static const char* const isAliasKeyword; + static const bool isAliasDefault; + static bool isAlias(const char*); + static const char* isAlias(bool); + +}; + +} // namespace yaml +} // namespace lld + +#endif // LLD_CORE_YAML_KEY_VALUES_H_ + Modified: lld/trunk/lib/Core/YamlReader.cpp URL: http://llvm.org/viewvc/llvm-project/lld/trunk/lib/Core/YamlReader.cpp?rev=147571&r1=147570&r2=147571&view=diff ============================================================================== --- lld/trunk/lib/Core/YamlReader.cpp (original) +++ lld/trunk/lib/Core/YamlReader.cpp Wed Jan 4 17:58:17 2012 @@ -7,6 +7,8 @@ // //===----------------------------------------------------------------------===// +#include "YamlKeyValues.h" + #include "lld/Core/YamlReader.h" #include "lld/Core/Atom.h" #include "lld/Core/File.h" @@ -21,10 +23,46 @@ #include -namespace { const llvm::error_code success; } + namespace lld { namespace yaml { + +enum yaml_reader_errors { + success = 0, + unknown_keyword, + illegal_value +}; + +class reader_error_category : public llvm::_do_message { +public: + virtual const char* name() const { + return "lld.yaml.reader"; + } + virtual std::string message(int ev) const; +}; + +const reader_error_category reader_error_category_singleton; + +std::string reader_error_category::message(int ev) const { + switch (ev) { + case success: + return "Success"; + case unknown_keyword: + return "Unknown keyword found in yaml file"; + case illegal_value: + return "Bad value found in yaml file"; + default: + llvm_unreachable("An enumerator of yaml_reader_errors does not have a " + "message defined."); + } +} + +inline llvm::error_code make_error_code(yaml_reader_errors e) { + return llvm::error_code(static_cast(e), reader_error_category_singleton); +} + + class YAML { public: struct Entry { @@ -137,6 +175,7 @@ state = inTriplePeriod; } else if (c == '\n') { // ignore empty lines + depth = 0; } else if (c == '\t') { llvm::report_fatal_error("TAB character found in yaml file"); } else { @@ -176,6 +215,8 @@ state = inValueSequence; } else if (c == ' ') { // eat space + } else if (c == '\t') { + llvm::report_fatal_error("TAB character found in yaml file"); } else { return; } @@ -247,16 +288,20 @@ , SectionChoice sc , bool intn , bool md + , bool ah , DeadStripKind dsk , bool tb , bool al , Alignment a , YAMLFile& f - , const char *n) - : Atom(ord, d, s, ct, sc, intn, md, dsk, tb, al, a) + , const char *n + , const char* sn + , uint64_t sz) + : Atom(ord, d, s, ct, sc, intn, md, ah, dsk, tb, al, a) , _file(f) , _name(n) - , _size(0) + , _sectionName(sn) + , _size(sz) , _refStartIndex(f._lastRefIndex) , _refEndIndex(f._references.size()) { f._lastRefIndex = _refEndIndex; @@ -273,6 +318,10 @@ virtual llvm::StringRef name() const { return _name; } + + virtual llvm::StringRef customSectionName() const { + return _sectionName; + } virtual uint64_t objectAddress() const { return 0; @@ -286,11 +335,12 @@ virtual Reference::iterator referencesBegin() const; virtual Reference::iterator referencesEnd() const; private: - YAMLFile& _file; - const char *_name; - unsigned long _size; - unsigned int _refStartIndex; - unsigned int _refEndIndex; + YAMLFile& _file; + const char * _name; + const char * _sectionName; + unsigned long _size; + unsigned int _refStartIndex; + unsigned int _refEndIndex; }; Reference::iterator YAMLAtom::referencesBegin() const { @@ -310,11 +360,7 @@ YAMLAtomState(); void setName(const char *n); - void setScope(const char *n); - void setType(const char *n); void setAlign2(const char *n); - void setDefinition(const char *n); - void setMergeDuplicates(const char *n); void setFixupKind(const char *n); void setFixupOffset(const char *n); @@ -323,8 +369,8 @@ void makeAtom(YAMLFile&); -private: uint64_t _ordinal; + long long _size; const char *_name; Atom::Alignment _align; Atom::ContentType _type; @@ -333,23 +379,29 @@ Atom::SectionChoice _sectionChoice; bool _internalName; bool _mergeDuplicates; - Atom::DeadStripKind _dontDeadStrip; + Atom::DeadStripKind _deadStrip; bool _thumb; bool _alias; + bool _autoHide; + const char *_sectionName; Reference _ref; }; YAMLAtomState::YAMLAtomState() : _ordinal(0) + , _size(0) , _name(NULL) , _align(0, 0) - , _type(Atom::typeData) - , _scope(Atom::scopeGlobal) - , _internalName(false) - , _mergeDuplicates(false) - , _dontDeadStrip(Atom::deadStripNormal) - , _thumb(false) - , _alias(false) { + , _type(KeyValues::contentTypeDefault) + , _scope(KeyValues::scopeDefault) + , _def(KeyValues::definitionDefault) + , _internalName(KeyValues::internalNameDefault) + , _mergeDuplicates(KeyValues::mergeDuplicatesDefault) + , _deadStrip(KeyValues::deadStripKindDefault) + , _thumb(KeyValues::isThumbDefault) + , _alias(KeyValues::isAliasDefault) + , _autoHide(KeyValues::autoHideDefault) + , _sectionName(NULL) { _ref.target = NULL; _ref.addend = 0; _ref.offsetInAtom = 0; @@ -359,8 +411,9 @@ void YAMLAtomState::makeAtom(YAMLFile& f) { Atom *a = new YAMLAtom(_ordinal, _def, _scope, _type, _sectionChoice, - _internalName, _mergeDuplicates, _dontDeadStrip, - _thumb, _alias, _align, f, _name); + _internalName, _mergeDuplicates, _autoHide, + _deadStrip, _thumb, _alias, _align, f, + _name, _sectionName, _size); f._atoms.push_back(a); ++_ordinal; @@ -369,15 +422,17 @@ _name = NULL; _align.powerOf2 = 0; _align.modulus = 0; - _type = Atom::typeData; - _scope = Atom::scopeGlobal; - _def = Atom::definitionRegular; - _sectionChoice = Atom::sectionBasedOnContent; - _internalName = false; - _mergeDuplicates = false; - _dontDeadStrip = Atom::deadStripNormal; - _thumb = false; - _alias = false; + _type = KeyValues::contentTypeDefault; + _scope = KeyValues::scopeDefault; + _def = KeyValues::definitionDefault; + _sectionChoice = KeyValues::sectionChoiceDefault; + _internalName = KeyValues::internalNameDefault; + _mergeDuplicates = KeyValues::mergeDuplicatesDefault; + _deadStrip = KeyValues::deadStripKindDefault; + _thumb = KeyValues::isThumbDefault; + _alias = KeyValues::isAliasDefault; + _autoHide = KeyValues::autoHideDefault; + _sectionName = NULL; _ref.target = NULL; _ref.addend = 0; _ref.offsetInAtom = 0; @@ -389,29 +444,6 @@ _name = n; } -void YAMLAtomState::setScope(const char *s) { - if (strcmp(s, "global") == 0) - _scope = Atom::scopeGlobal; - else if (strcmp(s, "hidden") == 0) - _scope = Atom::scopeLinkageUnit; - else if (strcmp(s, "static") == 0) - _scope = Atom::scopeTranslationUnit; - else - llvm::report_fatal_error("bad scope value"); -} - -void YAMLAtomState::setType(const char *s) { - if (strcmp(s, "code") == 0) - _type = Atom::typeCode; - else if (strcmp(s, "c-string") == 0) - _type = Atom::typeCString; - else if (strcmp(s, "zero-fill") == 0) - _type = Atom::typeZeroFill; - else if (strcmp(s, "data") == 0) - _type = Atom::typeData; - else - llvm::report_fatal_error("bad type value"); -} void YAMLAtomState::setAlign2(const char *s) { llvm::StringRef str(s); @@ -420,27 +452,6 @@ _align.powerOf2 = static_cast(res); } -void YAMLAtomState::setDefinition(const char *s) { - if (strcmp(s, "regular") == 0) - _def = Atom::definitionRegular; - else if (strcmp(s, "tentative") == 0) - _def = Atom::definitionTentative; - else if (strcmp(s, "weak") == 0) - _def = Atom::definitionWeak; - else if (strcmp(s, "absolute") == 0) - _def = Atom::definitionAbsolute; - else - llvm::report_fatal_error("bad definition value"); -} - -void YAMLAtomState::setMergeDuplicates(const char *s) { - if (strcmp(s, "true") == 0) - _mergeDuplicates = true; - else if (strcmp(s, "false") == 0) - _mergeDuplicates = false; - else - llvm::report_fatal_error("bad merge-duplicates value"); -} void YAMLAtomState::setFixupKind(const char *s) { if (strcmp(s, "pcrel32") == 0) @@ -527,28 +538,76 @@ haveAtom = false; } } - if (strcmp(entry->key, "name") == 0) { + if (strcmp(entry->key, KeyValues::nameKeyword) == 0) { atomState.setName(entry->value); haveAtom = true; - } else if (strcmp(entry->key, "scope") == 0) { - atomState.setScope(entry->value); + } + else if (strcmp(entry->key, KeyValues::internalNameKeyword) == 0) { + atomState._internalName = KeyValues::internalName(entry->value); + haveAtom = true; + } + else if (strcmp(entry->key, KeyValues::definitionKeyword) == 0) { + atomState._def = KeyValues::definition(entry->value); haveAtom = true; - } else if (strcmp(entry->key, "type") == 0) { - atomState.setType(entry->value); + } + else if (strcmp(entry->key, KeyValues::scopeKeyword) == 0) { + atomState._scope = KeyValues::scope(entry->value); haveAtom = true; - } else if (strcmp(entry->key, "align2") == 0) { - atomState.setAlign2(entry->value); + } + else if (strcmp(entry->key, KeyValues::contentTypeKeyword) == 0) { + atomState._type = KeyValues::contentType(entry->value); haveAtom = true; - } else if (strcmp(entry->key, "definition") == 0) { - atomState.setDefinition(entry->value); + } + else if (strcmp(entry->key, KeyValues::deadStripKindKeyword) == 0) { + atomState._deadStrip = KeyValues::deadStripKind(entry->value); haveAtom = true; - } else if (strcmp(entry->key, "merge-duplicates") == 0) { - atomState.setMergeDuplicates(entry->value); + } + else if (strcmp(entry->key, KeyValues::sectionChoiceKeyword) == 0) { + atomState._sectionChoice = KeyValues::sectionChoice(entry->value); + haveAtom = true; + } + else if (strcmp(entry->key, KeyValues::mergeDuplicatesKeyword) == 0) { + atomState._mergeDuplicates = KeyValues::mergeDuplicates(entry->value); haveAtom = true; - } else if (strcmp(entry->key, "fixups") == 0) { + } + else if (strcmp(entry->key, KeyValues::autoHideKeyword) == 0) { + atomState._autoHide = KeyValues::autoHide(entry->value); + haveAtom = true; + } + else if (strcmp(entry->key, KeyValues::isThumbKeyword) == 0) { + atomState._thumb = KeyValues::isThumb(entry->value); + haveAtom = true; + } + else if (strcmp(entry->key, KeyValues::isAliasKeyword) == 0) { + atomState._alias = KeyValues::isAlias(entry->value); + haveAtom = true; + } + else if (strcmp(entry->key, KeyValues::sectionNameKeyword) == 0) { + atomState._sectionName = entry->value; + haveAtom = true; + } + else if (strcmp(entry->key, KeyValues::sizeKeyword) == 0) { + llvm::StringRef val = entry->value; + if ( val.getAsInteger(0, atomState._size) ) + return make_error_code(illegal_value); + haveAtom = true; + } + else if (strcmp(entry->key, KeyValues::contentKeyword) == 0) { + // TO DO: switch to content mode + haveAtom = true; + } + else if (strcmp(entry->key, "align2") == 0) { + atomState.setAlign2(entry->value); + haveAtom = true; + } + else if (strcmp(entry->key, "fixups") == 0) { inFixups = true; } - } else if (depthForFixups == entry->depth) { + else { + return make_error_code(unknown_keyword); + } + } + else if (depthForFixups == entry->depth) { if (entry->beginSequence) { if (haveFixup) { atomState.addFixup(file); @@ -574,7 +633,7 @@ } result.push_back(file); - return success; + return make_error_code(success); } // Modified: lld/trunk/lib/Core/YamlWriter.cpp URL: http://llvm.org/viewvc/llvm-project/lld/trunk/lib/Core/YamlWriter.cpp?rev=147571&r1=147570&r2=147571&view=diff ============================================================================== --- lld/trunk/lib/Core/YamlWriter.cpp (original) +++ lld/trunk/lib/Core/YamlWriter.cpp Wed Jan 4 17:58:17 2012 @@ -7,6 +7,8 @@ // //===----------------------------------------------------------------------===// +#include "YamlKeyValues.h" + #include "lld/Core/YamlWriter.h" #include "lld/Core/Atom.h" #include "lld/Core/File.h" @@ -24,26 +26,121 @@ class Handler : public File::AtomHandler { public: - Handler(llvm::raw_ostream &out) : _out(out) { } + Handler(llvm::raw_ostream &out) : _out(out), _firstAtom(true) { } - virtual void doFile(const class File &) { } + virtual void doFile(const class File &) { _firstAtom = true; } + virtual void doAtom(const class Atom &atom) { - _out << " - name: " << atom.name() << "\n"; + // add blank line between atoms for readability + if ( !_firstAtom ) + _out << "\n"; + _firstAtom = false; + + _out << " - " + << KeyValues::nameKeyword + << ":" + << spacePadding(KeyValues::nameKeyword) + << atom.name() + << "\n"; + + if ( atom.internalName() != KeyValues::internalNameDefault ) { + _out << " " + << KeyValues::internalNameKeyword + << ":" + << spacePadding(KeyValues::internalNameKeyword) + << KeyValues::internalName(atom.internalName()) + << "\n"; + } - if ( atom.internalName() ) - _out << " internal-name: true\n"; - - if ( atom.definition() != Atom::definitionRegular ) - _out << " definition: " << definitionString(atom.definition()) <<"\n"; - - if ( atom.scope() != Atom::scopeTranslationUnit ) - _out << " scope: " << scopeString(atom.scope()) << "\n"; - - _out << " type: " << typeString(atom.contentType()) << "\n"; + if ( atom.definition() != KeyValues::definitionDefault ) { + _out << " " + << KeyValues::definitionKeyword + << ":" + << spacePadding(KeyValues::definitionKeyword) + << KeyValues::definition(atom.definition()) + << "\n"; + } - if ( atom.mergeDuplicates() ) - _out << " merge-duplicates: true\n"; - + if ( atom.scope() != KeyValues::scopeDefault ) { + _out << " " + << KeyValues::scopeKeyword + << ":" + << spacePadding(KeyValues::scopeKeyword) + << KeyValues::scope(atom.scope()) + << "\n"; + } + + if ( atom.contentType() != KeyValues::contentTypeDefault ) { + _out << " " + << KeyValues::contentTypeKeyword + << ":" + << spacePadding(KeyValues::contentTypeKeyword) + << KeyValues::contentType(atom.contentType()) + << "\n"; + } + + if ( atom.deadStrip() != KeyValues::deadStripKindDefault ) { + _out << " " + << KeyValues::deadStripKindKeyword + << ":" + << spacePadding(KeyValues::deadStripKindKeyword) + << KeyValues::deadStripKind(atom.deadStrip()) + << "\n"; + } + + if ( atom.sectionChoice() != KeyValues::sectionChoiceDefault ) { + _out << " " + << KeyValues::sectionChoiceKeyword + << ":" + << spacePadding(KeyValues::sectionChoiceKeyword) + << KeyValues::sectionChoice(atom.sectionChoice()) + << "\n"; + assert( ! atom.customSectionName().empty() ); + _out << " " + << KeyValues::sectionNameKeyword + << ":" + << spacePadding(KeyValues::sectionNameKeyword) + << atom.customSectionName() + << "\n"; + } + + if ( atom.mergeDuplicates() != KeyValues::mergeDuplicatesDefault ) { + _out << " " + << KeyValues::mergeDuplicatesKeyword + << ":" + << spacePadding(KeyValues::mergeDuplicatesKeyword) + << KeyValues::mergeDuplicates(atom.mergeDuplicates()) + << "\n"; + } + + if ( atom.autoHide() != KeyValues::autoHideDefault ) { + _out << " " + << KeyValues::autoHideKeyword + << ":" + << spacePadding(KeyValues::autoHideKeyword) + << KeyValues::autoHide(atom.autoHide()) + << "\n"; + } + + if ( atom.isThumb() != KeyValues::isThumbDefault ) { + _out << " " + << KeyValues::isThumbKeyword + << ":" + << spacePadding(KeyValues::isThumbKeyword) + << KeyValues::isThumb(atom.isThumb()) + << "\n"; + } + + if ( atom.isAlias() != KeyValues::isAliasDefault ) { + _out << " " + << KeyValues::isAliasKeyword + << ":" + << spacePadding(KeyValues::isAliasKeyword) + << KeyValues::isAlias(atom.isAlias()) + << "\n"; + } + + if (atom.referencesBegin() != atom.referencesEnd()) { _out << " fixups:\n"; for (Reference::iterator it = atom.referencesBegin(), @@ -56,49 +153,17 @@ } private: - const char *scopeString(Atom::Scope scope) { - switch (scope) { - case Atom::scopeTranslationUnit: - return "static"; - case Atom::scopeLinkageUnit: - return "hidden"; - case Atom::scopeGlobal: - return "global"; - } - return "???"; + // return a string of the correct number of spaces to align value + const char* spacePadding(const char* key) { + const char* spaces = " "; + assert(strlen(spaces) > strlen(key)); + return &spaces[strlen(key)]; } - const char *typeString(Atom::ContentType type) { - switch (type) { - case Atom::typeCode: - return "code"; - case Atom::typeCString: - return "c-string"; - case Atom::typeZeroFill: - return "zero-fill"; - case Atom::typeData: - return "data"; - default: - return "???"; - } - } - const char *definitionString(Atom::Definition def) { - switch (def) { - case Atom::definitionRegular: - return "regular"; - case Atom::definitionWeak: - return "weak"; - case Atom::definitionTentative: - return "tentative"; - case Atom::definitionAbsolute: - return "absolute"; - default: - return "???"; - } - } - llvm::raw_ostream &_out; + llvm::raw_ostream& _out; + bool _firstAtom; }; void writeObjectText(File &file, llvm::raw_ostream &out) { Added: lld/trunk/test/auto-hide-coalesce.objtxt URL: http://llvm.org/viewvc/llvm-project/lld/trunk/test/auto-hide-coalesce.objtxt?rev=147571&view=auto ============================================================================== --- lld/trunk/test/auto-hide-coalesce.objtxt (added) +++ lld/trunk/test/auto-hide-coalesce.objtxt Wed Jan 4 17:58:17 2012 @@ -0,0 +1,76 @@ +# RUN: lld-core %s | FileCheck %s + +# +# Tests auto-hide bit during coalescing +# + +--- +atoms: + - name: _inlineFunc1 + scope: global + definition: regular + type: code + merge-duplicates: true + auto-hide: true + + - name: _inlineFunc2 + scope: global + definition: regular + type: code + merge-duplicates: true + auto-hide: true + + - name: _inlineFunc3 + scope: global + definition: regular + type: code + merge-duplicates: true + auto-hide: false + + - name: _inlineFunc4 + scope: global + definition: regular + type: code + merge-duplicates: true + auto-hide: false +--- +atoms: + - name: _inlineFunc1 + scope: global + definition: regular + type: code + merge-duplicates: true + auto-hide: true + + - name: _inlineFunc2 + scope: global + definition: regular + type: code + merge-duplicates: true + auto-hide: false + + - name: _inlineFunc3 + scope: global + definition: regular + type: code + merge-duplicates: true + auto-hide: true + + - name: _inlineFunc4 + scope: global + definition: regular + type: code + merge-duplicates: true + auto-hide: false +... + + +# CHECK: name: _inlineFunc1 +# CHECK: auto-hide: true +# CHECK: name: _inlineFunc3 +# CHECK-NOT: auto-hide: true +# CHECK: name: _inlineFunc4 +# CHECK-NOT: auto-hide: true +# CHECK: name: _inlineFunc2 +# CHECK-NOT: auto-hide: true +# CHECK: ... Added: lld/trunk/test/custom-section.objtxt URL: http://llvm.org/viewvc/llvm-project/lld/trunk/test/custom-section.objtxt?rev=147571&view=auto ============================================================================== --- lld/trunk/test/custom-section.objtxt (added) +++ lld/trunk/test/custom-section.objtxt Wed Jan 4 17:58:17 2012 @@ -0,0 +1,34 @@ +# RUN: lld-core %s | FileCheck %s + +# +# Test that custom sections are preserved +# + +--- +atoms: + - name: _foo1 + scope: global + section-choice: content + + - name: _foo2 + scope: global + section-choice: custom + section-name: __foozle + + - name: _foo3 + scope: global + section-choice: custom-required + section-name: __boozle + +... + + +# CHECK: name: _foo1 +# CHECK-NOT: section-name: +# CHECK: name: _foo2 +# CHECK: section-choice: custom +# CHECK: section-name: __foozle +# CHECK: name: _foo3 +# CHECK: section-choice: custom-required +# CHECK: section-name: __boozle +# CHECK: ... Added: lld/trunk/test/dead-strip-attributes.objtxt URL: http://llvm.org/viewvc/llvm-project/lld/trunk/test/dead-strip-attributes.objtxt?rev=147571&view=auto ============================================================================== --- lld/trunk/test/dead-strip-attributes.objtxt (added) +++ lld/trunk/test/dead-strip-attributes.objtxt Wed Jan 4 17:58:17 2012 @@ -0,0 +1,29 @@ +# RUN: lld-core %s | FileCheck %s + +# +# Test that dead strip attributes are preserved +# + +--- +atoms: + - name: _foo1 + dead-strip: normal +--- +atoms: + - name: _foo2 + dead-strip: never +--- +atoms: + - name: _foo3 + dead-strip: always +... + + +# CHECK: name: _foo1 +# CHECK-NOT: dead-strip: never +# CHECK-NOT: dead-strip: always +# CHECK: name: _foo2 +# CHECK: dead-strip: never +# CHECK: name: _foo3 +# CHECK: dead-strip: always +# CHECK: ... Added: lld/trunk/test/internal-name-attributes.objtxt URL: http://llvm.org/viewvc/llvm-project/lld/trunk/test/internal-name-attributes.objtxt?rev=147571&view=auto ============================================================================== --- lld/trunk/test/internal-name-attributes.objtxt (added) +++ lld/trunk/test/internal-name-attributes.objtxt Wed Jan 4 17:58:17 2012 @@ -0,0 +1,27 @@ +# RUN: lld-core %s | FileCheck %s + +# +# Test that internal-name attributes are preserved +# + +--- +atoms: + - name: foo + internal-name: false + - name: L0 + internal-name: true + - name: L1 + internal-name: true + - name: bar +... + + +# CHECK: name: foo +# CHECK-NOT: internal-name: false +# CHECK: name: L0 +# CHECK: internal-name: true +# CHECK: name: L1 +# CHECK: internal-name: true +# CHECK: name: bar +# CHECK-NOT: internal-name: false +# CHECK: ... Modified: lld/trunk/test/multiple-def-error.objtxt URL: http://llvm.org/viewvc/llvm-project/lld/trunk/test/multiple-def-error.objtxt?rev=147571&r1=147570&r2=147571&view=diff ============================================================================== --- lld/trunk/test/multiple-def-error.objtxt (original) +++ lld/trunk/test/multiple-def-error.objtxt Wed Jan 4 17:58:17 2012 @@ -8,11 +8,13 @@ atoms: - name: _foo definition: regular + scope: global type: data --- atoms: - name: _foo definition: regular + scope: global type: data ... Modified: lld/trunk/test/tent-merge.objtxt URL: http://llvm.org/viewvc/llvm-project/lld/trunk/test/tent-merge.objtxt?rev=147571&r1=147570&r2=147571&view=diff ============================================================================== --- lld/trunk/test/tent-merge.objtxt (original) +++ lld/trunk/test/tent-merge.objtxt Wed Jan 4 17:58:17 2012 @@ -9,12 +9,14 @@ atoms: - name: _foo definition: tentative + scope: global type: zero-fill size: 4 --- atoms: - name: _foo definition: regular + scope: global type: data content: [ 00, 00, 00, 00 ] ... Modified: lld/trunk/test/weak-coalesce.objtxt URL: http://llvm.org/viewvc/llvm-project/lld/trunk/test/weak-coalesce.objtxt?rev=147571&r1=147570&r2=147571&view=diff ============================================================================== --- lld/trunk/test/weak-coalesce.objtxt (original) +++ lld/trunk/test/weak-coalesce.objtxt Wed Jan 4 17:58:17 2012 @@ -8,16 +8,19 @@ atoms: - name: _foo definition: weak + scope: global type: data --- atoms: - name: _foo definition: regular + scope: global type: data --- atoms: - name: _foo definition: weak + scope: global type: data ... From stoklund at 2pi.dk Wed Jan 4 18:26:52 2012 From: stoklund at 2pi.dk (Jakob Stoklund Olesen) Date: Thu, 05 Jan 2012 00:26:52 -0000 Subject: [llvm-commits] [llvm] r147578 - /llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp Message-ID: <20120105002652.ACDF72A6C12D@llvm.org> Author: stoklund Date: Wed Jan 4 18:26:52 2012 New Revision: 147578 URL: http://llvm.org/viewvc/llvm-project?rev=147578&view=rev Log: Avoid reserving an ARM base pointer during register allocation. Once register allocation has started the reserved registers are frozen. Fix the ARM canRealignStack() hook to respect the frozen register state. Now the hook returns false if register allocation was started with frame pointer elimination enabled. It also returns false if register allocation started without a reserved base pointer, and stack realignment would require a base pointer. This bug was breaking oggenc on armv6. No test case, an upcoming patch will use this functionality to realign the stack for spill slots when possible. Modified: llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp Modified: llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp?rev=147578&r1=147577&r2=147578&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp Wed Jan 4 18:26:52 2012 @@ -528,13 +528,28 @@ bool ARMBaseRegisterInfo::canRealignStack(const MachineFunction &MF) const { const MachineFrameInfo *MFI = MF.getFrameInfo(); + const MachineRegisterInfo *MRI = &MF.getRegInfo(); const ARMFunctionInfo *AFI = MF.getInfo(); // We can't realign the stack if: // 1. Dynamic stack realignment is explicitly disabled, // 2. This is a Thumb1 function (it's not useful, so we don't bother), or // 3. There are VLAs in the function and the base pointer is disabled. - return (MF.getTarget().Options.RealignStack && !AFI->isThumb1OnlyFunction() && - (!MFI->hasVarSizedObjects() || EnableBasePointer)); + if (!MF.getTarget().Options.RealignStack) + return false; + if (AFI->isThumb1OnlyFunction()) + return false; + // Stack realignment requires a frame pointer. If we already started + // register allocation with frame pointer elimination, it is too late now. + if (!MRI->canReserveReg(FramePtr)) + return false; + // We may also need a base pointer if there are dynamic allocas. + if (!MFI->hasVarSizedObjects()) + return true; + if (!EnableBasePointer) + return false; + // A base pointer is required and allowed. Check that it isn't too late to + // reserve it. + return MRI->canReserveReg(BasePtr); } bool ARMBaseRegisterInfo:: From stoklund at 2pi.dk Wed Jan 4 18:26:49 2012 From: stoklund at 2pi.dk (Jakob Stoklund Olesen) Date: Thu, 05 Jan 2012 00:26:49 -0000 Subject: [llvm-commits] [llvm] r147577 - in /llvm/trunk: docs/ReleaseNotes.html include/llvm/CodeGen/MachineRegisterInfo.h lib/CodeGen/MachineRegisterInfo.cpp lib/CodeGen/RegAllocBasic.cpp lib/CodeGen/RegAllocFast.cpp lib/CodeGen/RegAllocPBQP.cpp Message-ID: <20120105002649.BC0B02A6C12C@llvm.org> Author: stoklund Date: Wed Jan 4 18:26:49 2012 New Revision: 147577 URL: http://llvm.org/viewvc/llvm-project?rev=147577&view=rev Log: Freeze reserved registers before starting register allocation. The register allocators don't currently support adding reserved registers while they are running. Extend the MRI API to keep track of the set of reserved registers when register allocation started. Target hooks like hasFP() and needsStackRealignment() can look at this set to avoid reserving more registers during register allocation. Modified: llvm/trunk/docs/ReleaseNotes.html llvm/trunk/include/llvm/CodeGen/MachineRegisterInfo.h llvm/trunk/lib/CodeGen/MachineRegisterInfo.cpp llvm/trunk/lib/CodeGen/RegAllocBasic.cpp llvm/trunk/lib/CodeGen/RegAllocFast.cpp llvm/trunk/lib/CodeGen/RegAllocPBQP.cpp Modified: llvm/trunk/docs/ReleaseNotes.html URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/ReleaseNotes.html?rev=147577&r1=147576&r2=147577&view=diff ============================================================================== --- llvm/trunk/docs/ReleaseNotes.html (original) +++ llvm/trunk/docs/ReleaseNotes.html Wed Jan 4 18:26:49 2012 @@ -351,6 +351,10 @@ represent combinations of constraints from instructions and sub-registers. The synthetic register classes inherit most of their properties form their closest user-defined super-class. +
  • MachineRegisterInfo now allows the reserved registers to be + frozen when register allocation starts. Target hooks should use the + MRI->canReserveReg(FramePtr) method to avoid accidentally + disabling frame pointer elimination during register allocation.
    • Modified: llvm/trunk/include/llvm/CodeGen/MachineRegisterInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/MachineRegisterInfo.h?rev=147577&r1=147576&r2=147577&view=diff ============================================================================== --- llvm/trunk/include/llvm/CodeGen/MachineRegisterInfo.h (original) +++ llvm/trunk/include/llvm/CodeGen/MachineRegisterInfo.h Wed Jan 4 18:26:49 2012 @@ -57,7 +57,13 @@ /// so that the code generator knows which callee save registers to save and /// for other target specific uses. BitVector UsedPhysRegs; - + + /// ReservedRegs - This is a bit vector of reserved registers. The target + /// may change its mind about which registers should be reserved. This + /// vector is the frozen set of reserved registers when register allocation + /// started. + BitVector ReservedRegs; + /// LiveIns/LiveOuts - Keep track of the physical registers that are /// livein/liveout of the function. Live in values are typically arguments in /// registers, live out values are typically return values in registers. @@ -309,6 +315,37 @@ /// subregisters. That means that if R is used, so are all subregisters. void closePhysRegsUsed(const TargetRegisterInfo&); + + //===--------------------------------------------------------------------===// + // Reserved Register Info + //===--------------------------------------------------------------------===// + // + // The set of reserved registers must be invariant during register + // allocation. For example, the target cannot suddenly decide it needs a + // frame pointer when the register allocator has already used the frame + // pointer register for something else. + // + // These methods can be used by target hooks like hasFP() to avoid changing + // the reserved register set during register allocation. + + /// freezeReservedRegs - Called by the register allocator to freeze the set + /// of reserved registers before allocation begins. + void freezeReservedRegs(const MachineFunction&); + + /// reservedRegsFrozen - Returns true after freezeReservedRegs() was called + /// to ensure the set of reserved registers stays constant. + bool reservedRegsFrozen() const { + return !ReservedRegs.empty(); + } + + /// canReserveReg - Returns true if PhysReg can be used as a reserved + /// register. Any register can be reserved before freezeReservedRegs() is + /// called. + bool canReserveReg(unsigned PhysReg) const { + return !reservedRegsFrozen() || ReservedRegs.test(PhysReg); + } + + //===--------------------------------------------------------------------===// // LiveIn/LiveOut Management //===--------------------------------------------------------------------===// Modified: llvm/trunk/lib/CodeGen/MachineRegisterInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineRegisterInfo.cpp?rev=147577&r1=147576&r2=147577&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/MachineRegisterInfo.cpp (original) +++ llvm/trunk/lib/CodeGen/MachineRegisterInfo.cpp Wed Jan 4 18:26:49 2012 @@ -259,3 +259,7 @@ I.getOperand().getParent()->dump(); } #endif + +void MachineRegisterInfo::freezeReservedRegs(const MachineFunction &MF) { + ReservedRegs = TRI->getReservedRegs(MF); +} Modified: llvm/trunk/lib/CodeGen/RegAllocBasic.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/RegAllocBasic.cpp?rev=147577&r1=147576&r2=147577&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/RegAllocBasic.cpp (original) +++ llvm/trunk/lib/CodeGen/RegAllocBasic.cpp Wed Jan 4 18:26:49 2012 @@ -233,6 +233,7 @@ MRI = &vrm.getRegInfo(); VRM = &vrm; LIS = &lis; + MRI->freezeReservedRegs(vrm.getMachineFunction()); RegClassInfo.runOnMachineFunction(vrm.getMachineFunction()); const unsigned NumRegs = TRI->getNumRegs(); Modified: llvm/trunk/lib/CodeGen/RegAllocFast.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/RegAllocFast.cpp?rev=147577&r1=147576&r2=147577&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/RegAllocFast.cpp (original) +++ llvm/trunk/lib/CodeGen/RegAllocFast.cpp Wed Jan 4 18:26:49 2012 @@ -1047,6 +1047,7 @@ TM = &Fn.getTarget(); TRI = TM->getRegisterInfo(); TII = TM->getInstrInfo(); + MRI->freezeReservedRegs(Fn); RegClassInfo.runOnMachineFunction(Fn); UsedInInstr.resize(TRI->getNumRegs()); Modified: llvm/trunk/lib/CodeGen/RegAllocPBQP.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/RegAllocPBQP.cpp?rev=147577&r1=147576&r2=147577&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/RegAllocPBQP.cpp (original) +++ llvm/trunk/lib/CodeGen/RegAllocPBQP.cpp Wed Jan 4 18:26:49 2012 @@ -619,6 +619,7 @@ vrm = &getAnalysis(); spiller.reset(createInlineSpiller(*this, MF, *vrm)); + mri->freezeReservedRegs(MF); DEBUG(dbgs() << "PBQP Register Allocating for " << mf->getFunction()->getName() << "\n"); From stoklund at 2pi.dk Wed Jan 4 18:26:57 2012 From: stoklund at 2pi.dk (Jakob Stoklund Olesen) Date: Thu, 05 Jan 2012 00:26:57 -0000 Subject: [llvm-commits] [llvm] r147579 - in /llvm/trunk: lib/Target/ARM/ARMBaseInstrInfo.cpp lib/Target/ARM/ARMBaseRegisterInfo.cpp test/CodeGen/ARM/fast-isel-deadcode.ll test/CodeGen/Thumb2/aligned-spill.ll Message-ID: <20120105002657.591912A6C12C@llvm.org> Author: stoklund Date: Wed Jan 4 18:26:57 2012 New Revision: 147579 URL: http://llvm.org/viewvc/llvm-project?rev=147579&view=rev Log: Reapply r146997, "Heed spill slot alignment on ARM." Now that canRealignStack() understands frozen reserved registers, it is safe to use it for aligned spill instructions. It will only return true if the registers reserved at the beginning of register allocation allow for dynamic stack realignment. Modified: llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp llvm/trunk/test/CodeGen/ARM/fast-isel-deadcode.ll llvm/trunk/test/CodeGen/Thumb2/aligned-spill.ll Modified: llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp?rev=147579&r1=147578&r2=147579&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp Wed Jan 4 18:26:57 2012 @@ -765,7 +765,8 @@ break; case 16: if (ARM::QPRRegClass.hasSubClassEq(RC)) { - if (Align >= 16 && getRegisterInfo().needsStackRealignment(MF)) { + // Use aligned spills if the stack can be realigned. + if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) { AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VST1q64Pseudo)) .addFrameIndex(FI).addImm(16) .addReg(SrcReg, getKillRegState(isKill)) @@ -914,7 +915,7 @@ break; case 16: if (ARM::QPRRegClass.hasSubClassEq(RC)) { - if (Align >= 16 && getRegisterInfo().needsStackRealignment(MF)) { + if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) { AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLD1q64Pseudo), DestReg) .addFrameIndex(FI).addImm(16) .addMemOperand(MMO)); Modified: llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp?rev=147579&r1=147578&r2=147579&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp Wed Jan 4 18:26:57 2012 @@ -557,7 +557,7 @@ const MachineFrameInfo *MFI = MF.getFrameInfo(); const Function *F = MF.getFunction(); unsigned StackAlign = MF.getTarget().getFrameLowering()->getStackAlignment(); - bool requiresRealignment = ((MFI->getLocalFrameMaxAlign() > StackAlign) || + bool requiresRealignment = ((MFI->getMaxAlignment() > StackAlign) || F->hasFnAttr(Attribute::StackAlignment)); return requiresRealignment && canRealignStack(MF); Modified: llvm/trunk/test/CodeGen/ARM/fast-isel-deadcode.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/fast-isel-deadcode.ll?rev=147579&r1=147578&r2=147579&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/ARM/fast-isel-deadcode.ll (original) +++ llvm/trunk/test/CodeGen/ARM/fast-isel-deadcode.ll Wed Jan 4 18:26:57 2012 @@ -15,8 +15,7 @@ ; THUMB-NOT: sxtb ; THUMB: movs r0, #0 ; THUMB: movt r0, #0 -; THUMB: add sp, #32 -; THUMb: pop {r7, pc} +; THUMB: pop ret i32 0 } Modified: llvm/trunk/test/CodeGen/Thumb2/aligned-spill.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb2/aligned-spill.ll?rev=147579&r1=147578&r2=147579&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/Thumb2/aligned-spill.ll (original) +++ llvm/trunk/test/CodeGen/Thumb2/aligned-spill.ll Wed Jan 4 18:26:57 2012 @@ -1,4 +1,4 @@ -; DONT: llc < %s -mcpu=cortex-a8 | FileCheck %s +; RUN: llc < %s -mcpu=cortex-a8 | FileCheck %s ; RUN: llc < %s -mcpu=cortex-a8 -align-neon-spills | FileCheck %s --check-prefix=NEON target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:32:64-v128:32:128-a0:0:32-n32-S32" target triple = "thumbv7-apple-ios" From benny.kra at googlemail.com Wed Jan 4 18:43:35 2012 From: benny.kra at googlemail.com (Benjamin Kramer) Date: Thu, 05 Jan 2012 00:43:35 -0000 Subject: [llvm-commits] [llvm] r147580 - in /llvm/trunk/test: CodeGen/X86/avx-shuffle-x86_32.ll CodeGen/X86/cmpxchg16b.ll CodeGen/XCore/2011-08-01-DynamicAllocBug.ll Transforms/InstCombine/icmp.ll Transforms/SimplifyCFG/preserve-branchweights.ll Message-ID: <20120105004335.39BCF2A6C12C@llvm.org> Author: d0k Date: Wed Jan 4 18:43:34 2012 New Revision: 147580 URL: http://llvm.org/viewvc/llvm-project?rev=147580&view=rev Log: FileCheck hygiene. Modified: llvm/trunk/test/CodeGen/X86/avx-shuffle-x86_32.ll llvm/trunk/test/CodeGen/X86/cmpxchg16b.ll llvm/trunk/test/CodeGen/XCore/2011-08-01-DynamicAllocBug.ll llvm/trunk/test/Transforms/InstCombine/icmp.ll llvm/trunk/test/Transforms/SimplifyCFG/preserve-branchweights.ll Modified: llvm/trunk/test/CodeGen/X86/avx-shuffle-x86_32.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx-shuffle-x86_32.ll?rev=147580&r1=147579&r2=147580&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/X86/avx-shuffle-x86_32.ll (original) +++ llvm/trunk/test/CodeGen/X86/avx-shuffle-x86_32.ll Wed Jan 4 18:43:34 2012 @@ -3,6 +3,6 @@ define <4 x i64> @test1(<4 x i64> %a) nounwind { %b = shufflevector <4 x i64> %a, <4 x i64> undef, <4 x i32> ret <4 x i64>%b - ; CHECK test1: + ; CHECK: test1: ; CHECK: vinsertf128 } Modified: llvm/trunk/test/CodeGen/X86/cmpxchg16b.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/cmpxchg16b.ll?rev=147580&r1=147579&r2=147580&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/X86/cmpxchg16b.ll (original) +++ llvm/trunk/test/CodeGen/X86/cmpxchg16b.ll Wed Jan 4 18:43:34 2012 @@ -3,7 +3,7 @@ ; Basic 128-bit cmpxchg define void @t1(i128* nocapture %p) nounwind ssp { entry: -; CHECK movl $1, %ebx +; CHECK: movl $1, %ebx ; CHECK: lock ; CHECK-NEXT: cmpxchg16b %r = cmpxchg i128* %p, i128 0, i128 1 seq_cst Modified: llvm/trunk/test/CodeGen/XCore/2011-08-01-DynamicAllocBug.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/XCore/2011-08-01-DynamicAllocBug.ll?rev=147580&r1=147579&r2=147580&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/XCore/2011-08-01-DynamicAllocBug.ll (original) +++ llvm/trunk/test/CodeGen/XCore/2011-08-01-DynamicAllocBug.ll Wed Jan 4 18:43:34 2012 @@ -16,5 +16,5 @@ ; CHECK: f: ; CHECK: ldaw [[REGISTER:r[0-9]+]], {{r[0-9]+}}[-r1] ; CHECK: set sp, [[REGISTER]] -; CHECK extsp 1 -; CHECK bl g +; CHECK: extsp 1 +; CHECK: bl g Modified: llvm/trunk/test/Transforms/InstCombine/icmp.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstCombine/icmp.ll?rev=147580&r1=147579&r2=147580&view=diff ============================================================================== --- llvm/trunk/test/Transforms/InstCombine/icmp.ll (original) +++ llvm/trunk/test/Transforms/InstCombine/icmp.ll Wed Jan 4 18:43:34 2012 @@ -524,7 +524,7 @@ ; CHECK: @test54 ; CHECK-NEXT: %and = and i8 %a, -64 -; CHECK-NEXT icmp eq i8 %and, -128 +; CHECK-NEXT: icmp eq i8 %and, -128 define i1 @test54(i8 %a) nounwind { %ext = zext i8 %a to i32 %and = and i32 %ext, 192 Modified: llvm/trunk/test/Transforms/SimplifyCFG/preserve-branchweights.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/SimplifyCFG/preserve-branchweights.ll?rev=147580&r1=147579&r2=147580&view=diff ============================================================================== --- llvm/trunk/test/Transforms/SimplifyCFG/preserve-branchweights.ll (original) +++ llvm/trunk/test/Transforms/SimplifyCFG/preserve-branchweights.ll Wed Jan 4 18:43:34 2012 @@ -3,7 +3,7 @@ declare void @helper(i32) define void @test1(i1 %a, i1 %b) { -; CHECK @test1 +; CHECK: @test1 entry: br i1 %a, label %Y, label %X, !prof !0 ; CHECK: br i1 %or.cond, label %Z, label %Y, !prof !0 From kcc at google.com Wed Jan 4 18:44:34 2012 From: kcc at google.com (Kostya Serebryany) Date: Thu, 05 Jan 2012 00:44:34 -0000 Subject: [llvm-commits] [compiler-rt] r147581 - in /compiler-rt/trunk/lib/asan: Makefile.old asan_internal.h asan_linux.cc asan_printf.cc asan_rtl.cc asan_stack.cc asan_thread.cc Message-ID: <20120105004434.625942A6C12C@llvm.org> Author: kcc Date: Wed Jan 4 18:44:33 2012 New Revision: 147581 URL: http://llvm.org/viewvc/llvm-project?rev=147581&view=rev Log: [asan] implement our own /proc/self/maps reader and use it on linux instead of sysinfo.h Modified: compiler-rt/trunk/lib/asan/Makefile.old compiler-rt/trunk/lib/asan/asan_internal.h compiler-rt/trunk/lib/asan/asan_linux.cc compiler-rt/trunk/lib/asan/asan_printf.cc compiler-rt/trunk/lib/asan/asan_rtl.cc compiler-rt/trunk/lib/asan/asan_stack.cc compiler-rt/trunk/lib/asan/asan_thread.cc Modified: compiler-rt/trunk/lib/asan/Makefile.old URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/lib/asan/Makefile.old?rev=147581&r1=147580&r2=147581&view=diff ============================================================================== --- compiler-rt/trunk/lib/asan/Makefile.old (original) +++ compiler-rt/trunk/lib/asan/Makefile.old Wed Jan 4 18:44:33 2012 @@ -264,7 +264,6 @@ $(BIN)/%$(SUFF).o: %.cc $(RTL_HDR) $(MAKEFILE) $(CXX) $(PIE) $(CFLAGS) -fPIC -c -O2 -fno-exceptions -funwind-tables \ -o $@ -g $< -Ithird_party \ - -DASAN_USE_SYSINFO=1 \ -DASAN_NEEDS_SEGV=$(ASAN_NEEDS_SEGV) \ -DASAN_HAS_EXCEPTIONS=$(ASAN_HAS_EXCEPTIONS) \ -DASAN_FLEXIBLE_MAPPING_AND_OFFSET=$(ASAN_FLEXIBLE_MAPPING_AND_OFFSET) \ @@ -272,7 +271,6 @@ $(BIN)/%$(SUFF).o: %.c $(RTL_HDR) $(MAKEFILE) $(CC) $(PIE) $(CFLAGS) -fPIC -c -O2 -o $@ -g $< -Ithird_party \ - -DASAN_USE_SYSINFO=1 \ $(ASAN_FLAGS) ifeq ($(OS),darwin) Modified: compiler-rt/trunk/lib/asan/asan_internal.h URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/lib/asan/asan_internal.h?rev=147581&r1=147580&r2=147581&view=diff ============================================================================== --- compiler-rt/trunk/lib/asan/asan_internal.h (original) +++ compiler-rt/trunk/lib/asan/asan_internal.h Wed Jan 4 18:44:33 2012 @@ -45,8 +45,12 @@ // If set, sysinfo/sysinfo.h will be used to iterate over /proc/maps. #ifndef ASAN_USE_SYSINFO +#ifdef __linux__ +# define ASAN_USE_SYSINFO 0 +#else # define ASAN_USE_SYSINFO 1 #endif +#endif // If set, asan will install its own SEGV signal handler. #ifndef ASAN_NEEDS_SEGV @@ -99,10 +103,18 @@ ssize_t AsanWrite(int fd, const void *buf, size_t count); int AsanClose(int fd); +// Opens the file 'file_name" and reads up to 'max_len' bytes. +// The resulting buffer is mmaped and stored in '*buff'. +// The size of the mmaped region is stored in '*buff_size', +// Returns the number of read bytes or -1 if file can not be opened. +ssize_t ReadFileToBuffer(const char *file_name, char **buff, + size_t *buff_size, size_t max_len); + // asan_printf.cc void RawWrite(const char *buffer); int SNPrint(char *buffer, size_t length, const char *format, ...); void Printf(const char *format, ...); +int SScanf(const char *str, const char *format, ...); void Report(const char *format, ...); // Don't use std::min and std::max, to minimize dependency on libstdc++. Modified: compiler-rt/trunk/lib/asan/asan_linux.cc URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/lib/asan/asan_linux.cc?rev=147581&r1=147580&r2=147581&view=diff ============================================================================== --- compiler-rt/trunk/lib/asan/asan_linux.cc (original) +++ compiler-rt/trunk/lib/asan/asan_linux.cc Wed Jan 4 18:44:33 2012 @@ -13,12 +13,15 @@ //===----------------------------------------------------------------------===// #ifdef __linux__ +#include "asan_interceptors.h" #include "asan_internal.h" +#include "asan_procmaps.h" #include #include #include #include +#include #include extern char _DYNAMIC[]; @@ -96,6 +99,57 @@ return close(fd); } +AsanProcMaps::AsanProcMaps() { + proc_self_maps_buff_len_ = + ReadFileToBuffer("/proc/self/maps", &proc_self_maps_buff_, + &proc_self_maps_buff_mmaped_size_, 1 << 20); + CHECK(proc_self_maps_buff_len_ > 0); + // AsanWrite(2, proc_self_maps_buff_, proc_self_maps_buff_len_); + Reset(); +} + +AsanProcMaps::~AsanProcMaps() { + AsanUnmapOrDie(proc_self_maps_buff_, proc_self_maps_buff_mmaped_size_); +} + +void AsanProcMaps::Reset() { + current_ = proc_self_maps_buff_; +} + +bool AsanProcMaps::Next(uint64_t *start, uint64_t *end, + uint64_t *offset, char filename[], + size_t filename_size) { + char *last = proc_self_maps_buff_ + proc_self_maps_buff_len_; + if (current_ >= last) return false; + int consumed = 0; + char flags[10]; + int major, minor; + uint64_t inode; + char *next_line = (char*)internal_memchr(current_, '\n', last - current_); + if (next_line == NULL) + next_line = last; + if (SScanf(current_, + "%llx-%llx %4s %llx %x:%x %lld %n", + start, end, flags, offset, &major, &minor, + &inode, &consumed) != 7) + return false; + current_ += consumed; + // Skip spaces. + while (current_ < next_line && *current_ == ' ') + current_++; + // Fill in the filename. + size_t i = 0; + while (current_ < next_line) { + if (filename && i < filename_size - 1) + filename[i++] = *current_; + current_++; + } + if (filename && i < filename_size) + filename[i] = 0; + current_ = next_line + 1; + return true; +} + } // namespace __asan #endif // __linux__ Modified: compiler-rt/trunk/lib/asan/asan_printf.cc URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/lib/asan/asan_printf.cc?rev=147581&r1=147580&r2=147581&view=diff ============================================================================== --- compiler-rt/trunk/lib/asan/asan_printf.cc (original) +++ compiler-rt/trunk/lib/asan/asan_printf.cc Wed Jan 4 18:44:33 2012 @@ -18,6 +18,7 @@ #include "asan_interceptors.h" #include +#include namespace __asan { @@ -178,4 +179,12 @@ RawWrite(buffer); } +int SScanf(const char *str, const char *format, ...) { + va_list args; + va_start(args, format); + int res = vsscanf(str, format, args); + va_end(args); + return res; +} + } // namespace __asan Modified: compiler-rt/trunk/lib/asan/asan_rtl.cc URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/lib/asan/asan_rtl.cc?rev=147581&r1=147580&r2=147581&view=diff ============================================================================== --- compiler-rt/trunk/lib/asan/asan_rtl.cc (original) +++ compiler-rt/trunk/lib/asan/asan_rtl.cc Wed Jan 4 18:44:33 2012 @@ -18,6 +18,7 @@ #include "asan_lock.h" #include "asan_mac.h" #include "asan_mapping.h" +#include "asan_procmaps.h" #include "asan_stack.h" #include "asan_stats.h" #include "asan_thread.h" @@ -119,22 +120,19 @@ Printf("\n"); } -// Opens the file 'file_name" and reads up to 'max_len' bytes. -// The resulting buffer is mmaped and stored in '*buff'. -// Returns the number of read bytes or -1 if file can not be opened. -static ssize_t ReadFileToBuffer(const char *file_name, char **buff, - size_t max_len) { +ssize_t ReadFileToBuffer(const char *file_name, char **buff, + size_t *buff_size, size_t max_len) { const size_t kMinFileLen = kPageSize; ssize_t read_len = -1; *buff = 0; - size_t maped_size = 0; + *buff_size = 0; // The files we usually open are not seekable, so try different buffer sizes. for (size_t size = kMinFileLen; size <= max_len; size *= 2) { int fd = AsanOpenReadonly(file_name); if (fd < 0) return -1; - AsanUnmapOrDie(*buff, maped_size); - maped_size = size; + AsanUnmapOrDie(*buff, *buff_size); *buff = (char*)AsanMmapSomewhereOrDie(size, __FUNCTION__); + *buff_size = size; read_len = AsanRead(fd, *buff, size); AsanClose(fd); if (read_len < size) // We've read the whole file. @@ -151,7 +149,9 @@ static bool inited; if (!inited) { inited = true; - len = ReadFileToBuffer("/proc/self/environ", &environ, 1 << 20); + size_t environ_size; + len = ReadFileToBuffer("/proc/self/environ", + &environ, &environ_size, 1 << 20); } if (!environ || len <= 0) return NULL; size_t namelen = internal_strlen(name); Modified: compiler-rt/trunk/lib/asan/asan_stack.cc URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/lib/asan/asan_stack.cc?rev=147581&r1=147580&r2=147581&view=diff ============================================================================== --- compiler-rt/trunk/lib/asan/asan_stack.cc (original) +++ compiler-rt/trunk/lib/asan/asan_stack.cc Wed Jan 4 18:44:33 2012 @@ -13,6 +13,7 @@ //===----------------------------------------------------------------------===// #include "asan_interceptors.h" #include "asan_lock.h" +#include "asan_procmaps.h" #include "asan_stack.h" #include "asan_thread.h" #include "asan_thread_registry.h" @@ -128,9 +129,27 @@ #else // ASAN_USE_SYSINFO void AsanStackTrace::PrintStack(uintptr_t *addr, size_t size) { + AsanProcMaps proc_maps; for (size_t i = 0; i < size && addr[i]; i++) { + proc_maps.Reset(); uintptr_t pc = addr[i]; - Printf(" #%ld 0x%lx\n", i, pc); + uint64_t start, end, offset; + char filename[4096]; + bool found = 0; + int map_idx = 0; + while (proc_maps.Next(&start, &end, &offset, + filename, sizeof(filename))) { + if (pc >= start && pc <= end) { + found = true; + uintptr_t relative_pc = (map_idx == 0) ? pc : (pc - start); + Printf(" #%ld 0x%lx (%s+0x%lx)\n", i, pc, filename, relative_pc); + break; + } + map_idx++; + } + if (!found) { + Printf(" #%ld 0x%lx\n", i, pc); + } } } #endif // ASAN_USE_SYSINFO Modified: compiler-rt/trunk/lib/asan/asan_thread.cc URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/lib/asan/asan_thread.cc?rev=147581&r1=147580&r2=147581&view=diff ============================================================================== --- compiler-rt/trunk/lib/asan/asan_thread.cc (original) +++ compiler-rt/trunk/lib/asan/asan_thread.cc Wed Jan 4 18:44:33 2012 @@ -13,14 +13,11 @@ //===----------------------------------------------------------------------===// #include "asan_allocator.h" #include "asan_interceptors.h" +#include "asan_procmaps.h" #include "asan_thread.h" #include "asan_thread_registry.h" #include "asan_mapping.h" -#if ASAN_USE_SYSINFO == 1 -#include "sysinfo/sysinfo.h" -#endif - #include #include #include @@ -126,17 +123,16 @@ int local; CHECK(AddrIsInStack((uintptr_t)&local)); #else -#if ASAN_USE_SYSINFO == 1 if (tid() == 0) { // This is the main thread. Libpthread may not be initialized yet. struct rlimit rl; CHECK(getrlimit(RLIMIT_STACK, &rl) == 0); // Find the mapping that contains a stack variable. - ProcMapsIterator it(0); - uint64_t start, end; + AsanProcMaps proc_maps; + uint64_t start, end, offset; uint64_t prev_end = 0; - while (it.Next(&start, &end, NULL, NULL, NULL, NULL)) { + while (proc_maps.Next(&start, &end, &offset, NULL, 0)) { if ((uintptr_t)&rl < end) break; prev_end = end; @@ -155,7 +151,6 @@ CHECK(AddrIsInStack((uintptr_t)&rl)); return; } -#endif pthread_attr_t attr; CHECK(pthread_getattr_np(pthread_self(), &attr) == 0); size_t stacksize = 0; From clattner at apple.com Wed Jan 4 18:50:56 2012 From: clattner at apple.com (Chris Lattner) Date: Wed, 04 Jan 2012 16:50:56 -0800 Subject: [llvm-commits] [llvm] r147580 - in /llvm/trunk/test: CodeGen/X86/avx-shuffle-x86_32.ll CodeGen/X86/cmpxchg16b.ll CodeGen/XCore/2011-08-01-DynamicAllocBug.ll Transforms/InstCombine/icmp.ll Transforms/SimplifyCFG/preserve-branchweights.ll In-Reply-To: <20120105004335.39BCF2A6C12C@llvm.org> References: <20120105004335.39BCF2A6C12C@llvm.org> Message-ID: <5AB5E35B-739C-4680-AC18-262C67B1E23C@apple.com> On Jan 4, 2012, at 4:43 PM, Benjamin Kramer wrote: > Author: d0k > Date: Wed Jan 4 18:43:34 2012 > New Revision: 147580 > > URL: http://llvm.org/viewvc/llvm-project?rev=147580&view=rev > Log: > FileCheck hygiene. Should FileCheck output a warning or error when the prefix is seen without a : or -NOT: ? -Chris From dpatel at apple.com Wed Jan 4 18:51:29 2012 From: dpatel at apple.com (Devang Patel) Date: Thu, 05 Jan 2012 00:51:29 -0000 Subject: [llvm-commits] [llvm] r147583 - /llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp Message-ID: <20120105005129.218AF2A6C12C@llvm.org> Author: dpatel Date: Wed Jan 4 18:51:28 2012 New Revision: 147583 URL: http://llvm.org/viewvc/llvm-project?rev=147583&view=rev Log: Do not hard code asm variant number. Modified: llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp Modified: llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp?rev=147583&r1=147582&r2=147583&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp (original) +++ llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp Wed Jan 4 18:51:28 2012 @@ -555,6 +555,9 @@ /// The AsmParser "RegisterPrefix" value. std::string RegisterPrefix; + /// The AsmParser variant number. + int AsmVariantNo; + /// The classes which are needed for matching. std::vector Classes; @@ -643,7 +646,8 @@ void MatchableInfo::Initialize(const AsmMatcherInfo &Info, SmallPtrSet &SingletonRegisters) { // TODO: Eventually support asmparser for Variant != 0. - AsmString = CodeGenInstruction::FlattenAsmStringVariants(AsmString, 0); + AsmString = + CodeGenInstruction::FlattenAsmStringVariants(AsmString, Info.AsmVariantNo); TokenizeAsmString(Info); @@ -1105,7 +1109,8 @@ CodeGenTarget &target, RecordKeeper &records) : Records(records), AsmParser(asmParser), Target(target), - RegisterPrefix(AsmParser->getValueAsString("RegisterPrefix")) { + RegisterPrefix(AsmParser->getValueAsString("RegisterPrefix")), + AsmVariantNo(AsmParser->getValueAsInt("Variant")) { } /// BuildOperandMatchInfo - Build the necessary information to handle user From sabre at nondot.org Wed Jan 4 18:52:52 2012 From: sabre at nondot.org (Chris Lattner) Date: Thu, 05 Jan 2012 00:52:52 -0000 Subject: [llvm-commits] [www] r147584 - in /www/trunk/devmtg/2011-11: Lattner_Kickoff.pdf index.html Message-ID: <20120105005252.CDFAC2A6C12C@llvm.org> Author: lattner Date: Wed Jan 4 18:52:52 2012 New Revision: 147584 URL: http://llvm.org/viewvc/llvm-project?rev=147584&view=rev Log: add slides for the dev meeting kickoff. Added: www/trunk/devmtg/2011-11/Lattner_Kickoff.pdf (with props) Modified: www/trunk/devmtg/2011-11/index.html Added: www/trunk/devmtg/2011-11/Lattner_Kickoff.pdf URL: http://llvm.org/viewvc/llvm-project/www/trunk/devmtg/2011-11/Lattner_Kickoff.pdf?rev=147584&view=auto ============================================================================== Binary file - no diff available. Propchange: www/trunk/devmtg/2011-11/Lattner_Kickoff.pdf ------------------------------------------------------------------------------ svn:mime-type = application/octet-stream Modified: www/trunk/devmtg/2011-11/index.html URL: http://llvm.org/viewvc/llvm-project/www/trunk/devmtg/2011-11/index.html?rev=147584&r1=147583&r2=147584&view=diff ============================================================================== --- www/trunk/devmtg/2011-11/index.html (original) +++ www/trunk/devmtg/2011-11/index.html Wed Jan 4 18:52:52 2012 @@ -49,6 +49,13 @@     + + + + + From atrick at apple.com Wed Jan 4 19:01:02 2012 From: atrick at apple.com (Andrew Trick) Date: Thu, 05 Jan 2012 01:01:02 -0000 Subject: [llvm-commits] [llvm] r147585 - /llvm/trunk/include/llvm/CodeGen/LiveInterval.h Message-ID: <20120105010102.1FE022A6C12C@llvm.org> Author: atrick Date: Wed Jan 4 19:01:01 2012 New Revision: 147585 URL: http://llvm.org/viewvc/llvm-project?rev=147585&view=rev Log: comment cleanup Modified: llvm/trunk/include/llvm/CodeGen/LiveInterval.h Modified: llvm/trunk/include/llvm/CodeGen/LiveInterval.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/LiveInterval.h?rev=147585&r1=147584&r2=147585&view=diff ============================================================================== --- llvm/trunk/include/llvm/CodeGen/LiveInterval.h (original) +++ llvm/trunk/include/llvm/CodeGen/LiveInterval.h Wed Jan 4 19:01:01 2012 @@ -57,7 +57,7 @@ /// The ID number of this value. unsigned id; - /// The index of the defining instruction (if isDefAccurate() returns true). + /// The index of the defining instruction. SlotIndex def; /// VNInfo constructor. From kcc at google.com Wed Jan 4 19:07:28 2012 From: kcc at google.com (Kostya Serebryany) Date: Thu, 05 Jan 2012 01:07:28 -0000 Subject: [llvm-commits] [compiler-rt] r147586 - in /compiler-rt/trunk/lib/asan: asan_linux.cc asan_mac.cc asan_procmaps.h asan_thread.cc Message-ID: <20120105010728.45F4C2A6C12C@llvm.org> Author: kcc Date: Wed Jan 4 19:07:27 2012 New Revision: 147586 URL: http://llvm.org/viewvc/llvm-project?rev=147586&view=rev Log: [asan] move {linux,mac}-specific code from asan_thread.cc to asan_{linux,mac}.cc; also add asan_procmaps.h which I forgot to add on previous commit. Added: compiler-rt/trunk/lib/asan/asan_procmaps.h Modified: compiler-rt/trunk/lib/asan/asan_linux.cc compiler-rt/trunk/lib/asan/asan_mac.cc compiler-rt/trunk/lib/asan/asan_thread.cc Modified: compiler-rt/trunk/lib/asan/asan_linux.cc URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/lib/asan/asan_linux.cc?rev=147586&r1=147585&r2=147586&view=diff ============================================================================== --- compiler-rt/trunk/lib/asan/asan_linux.cc (original) +++ compiler-rt/trunk/lib/asan/asan_linux.cc Wed Jan 4 19:07:27 2012 @@ -16,11 +16,15 @@ #include "asan_interceptors.h" #include "asan_internal.h" #include "asan_procmaps.h" +#include "asan_thread.h" +#include +#include #include #include #include #include +#include #include #include @@ -150,6 +154,54 @@ return true; } +void AsanThread::SetThreadStackTopAndBottom() { + if (tid() == 0) { + // This is the main thread. Libpthread may not be initialized yet. + struct rlimit rl; + CHECK(getrlimit(RLIMIT_STACK, &rl) == 0); + + // Find the mapping that contains a stack variable. + AsanProcMaps proc_maps; + uint64_t start, end, offset; + uint64_t prev_end = 0; + while (proc_maps.Next(&start, &end, &offset, NULL, 0)) { + if ((uintptr_t)&rl < end) + break; + prev_end = end; + } + CHECK((uintptr_t)&rl >= start && (uintptr_t)&rl < end); + + // Get stacksize from rlimit, but clip it so that it does not overlap + // with other mappings. + size_t stacksize = rl.rlim_cur; + if (stacksize > end - prev_end) + stacksize = end - prev_end; + if (stacksize > kMaxThreadStackSize) + stacksize = kMaxThreadStackSize; + stack_top_ = end; + stack_bottom_ = end - stacksize; + CHECK(AddrIsInStack((uintptr_t)&rl)); + return; + } + pthread_attr_t attr; + CHECK(pthread_getattr_np(pthread_self(), &attr) == 0); + size_t stacksize = 0; + void *stackaddr = NULL; + pthread_attr_getstack(&attr, &stackaddr, &stacksize); + pthread_attr_destroy(&attr); + + stack_top_ = (uintptr_t)stackaddr + stacksize; + stack_bottom_ = (uintptr_t)stackaddr; + // When running with unlimited stack size, we still want to set some limit. + // The unlimited stack size is caused by 'ulimit -s unlimited'. + // Also, for some reason, GNU make spawns subrocesses with unlimited stack. + if (stacksize > kMaxThreadStackSize) { + stack_bottom_ = stack_top_ - kMaxThreadStackSize; + } + CHECK(AddrIsInStack((uintptr_t)&attr)); +} + + } // namespace __asan #endif // __linux__ Modified: compiler-rt/trunk/lib/asan/asan_mac.cc URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/lib/asan/asan_mac.cc?rev=147586&r1=147585&r2=147586&view=diff ============================================================================== --- compiler-rt/trunk/lib/asan/asan_mac.cc (original) +++ compiler-rt/trunk/lib/asan/asan_mac.cc Wed Jan 4 19:07:27 2012 @@ -22,6 +22,7 @@ #include "asan_thread_registry.h" #include +#include #include #include @@ -103,6 +104,15 @@ return close(fd); } +void AsanThread::SetThreadStackTopAndBottom() { + size_t stacksize = pthread_get_stacksize_np(pthread_self()); + void *stackaddr = pthread_get_stackaddr_np(pthread_self()); + stack_top_ = (uintptr_t)stackaddr; + stack_bottom_ = stack_top_ - stacksize; + int local; + CHECK(AddrIsInStack((uintptr_t)&local)); +} + // Support for the following functions from libdispatch on Mac OS: // dispatch_async_f() // dispatch_async() Added: compiler-rt/trunk/lib/asan/asan_procmaps.h URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/lib/asan/asan_procmaps.h?rev=147586&view=auto ============================================================================== --- compiler-rt/trunk/lib/asan/asan_procmaps.h (added) +++ compiler-rt/trunk/lib/asan/asan_procmaps.h Wed Jan 4 19:07:27 2012 @@ -0,0 +1,41 @@ +//===-- asan_process.h ------------------------------------------*- C++ -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file is a part of AddressSanitizer, an address sanity checker. +// +// Information about the process mappings. +//===----------------------------------------------------------------------===// +#ifndef ASAN_PROCMAPS_H +#define ASAN_PROCMAPS_H + +#include "asan_internal.h" + +namespace __asan { + +class AsanProcMaps { + public: + AsanProcMaps(); + bool Next(uint64_t *start, uint64_t *end, uint64_t *offset, + char filename[], size_t filename_size); + void Reset(); + ~AsanProcMaps(); + private: +#if defined __linux__ + char *proc_self_maps_buff_; + size_t proc_self_maps_buff_mmaped_size_; + size_t proc_self_maps_buff_len_; + char *current_; +#elif defined __APPLE__ +// FIXME: Mac code goes here +#endif +}; + +} // namespace __asan + +#endif // ASAN_PROCMAPS_H Modified: compiler-rt/trunk/lib/asan/asan_thread.cc URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/lib/asan/asan_thread.cc?rev=147586&r1=147585&r2=147586&view=diff ============================================================================== --- compiler-rt/trunk/lib/asan/asan_thread.cc (original) +++ compiler-rt/trunk/lib/asan/asan_thread.cc Wed Jan 4 19:07:27 2012 @@ -18,8 +18,6 @@ #include "asan_thread_registry.h" #include "asan_mapping.h" -#include -#include #include #include #include @@ -114,60 +112,4 @@ return "UNKNOWN"; } -void AsanThread::SetThreadStackTopAndBottom() { -#ifdef __APPLE__ - size_t stacksize = pthread_get_stacksize_np(pthread_self()); - void *stackaddr = pthread_get_stackaddr_np(pthread_self()); - stack_top_ = (uintptr_t)stackaddr; - stack_bottom_ = stack_top_ - stacksize; - int local; - CHECK(AddrIsInStack((uintptr_t)&local)); -#else - if (tid() == 0) { - // This is the main thread. Libpthread may not be initialized yet. - struct rlimit rl; - CHECK(getrlimit(RLIMIT_STACK, &rl) == 0); - - // Find the mapping that contains a stack variable. - AsanProcMaps proc_maps; - uint64_t start, end, offset; - uint64_t prev_end = 0; - while (proc_maps.Next(&start, &end, &offset, NULL, 0)) { - if ((uintptr_t)&rl < end) - break; - prev_end = end; - } - CHECK((uintptr_t)&rl >= start && (uintptr_t)&rl < end); - - // Get stacksize from rlimit, but clip it so that it does not overlap - // with other mappings. - size_t stacksize = rl.rlim_cur; - if (stacksize > end - prev_end) - stacksize = end - prev_end; - if (stacksize > kMaxThreadStackSize) - stacksize = kMaxThreadStackSize; - stack_top_ = end; - stack_bottom_ = end - stacksize; - CHECK(AddrIsInStack((uintptr_t)&rl)); - return; - } - pthread_attr_t attr; - CHECK(pthread_getattr_np(pthread_self(), &attr) == 0); - size_t stacksize = 0; - void *stackaddr = NULL; - pthread_attr_getstack(&attr, &stackaddr, &stacksize); - pthread_attr_destroy(&attr); - - stack_top_ = (uintptr_t)stackaddr + stacksize; - stack_bottom_ = (uintptr_t)stackaddr; - // When running with unlimited stack size, we still want to set some limit. - // The unlimited stack size is caused by 'ulimit -s unlimited'. - // Also, for some reason, GNU make spawns subrocesses with unlimited stack. - if (stacksize > kMaxThreadStackSize) { - stack_bottom_ = stack_top_ - kMaxThreadStackSize; - } - CHECK(AddrIsInStack((uintptr_t)&attr)); -#endif -} - } // namespace __asan From apazos at codeaurora.org Wed Jan 4 19:42:38 2012 From: apazos at codeaurora.org (Ana Pazos) Date: Wed, 4 Jan 2012 17:42:38 -0800 Subject: [llvm-commits] LLVM patch to support ARM fused multiply add/subtract instructions In-Reply-To: References: <027a01cccb29$a4709100$ed51b300$@org> Message-ID: <029201cccb4b$4eb5e130$ec21a390$@org> Hi Anton, Thanks for pointing that out. Find attached the updated patch that properly sets VFP_arch as vfpv4 if neon is not present. Thanks, Ana. -----Original Message----- From: Anton Korobeynikov [mailto:anton at korobeynikov.info] Sent: Wednesday, January 04, 2012 3:06 PM To: Ana Pazos Cc: llvm-commits at cs.uiuc.edu; rajav at codeaurora.org Subject: Re: [llvm-commits] LLVM patch to support ARM fused multiply add/subtract instructions Hello Ana, > Some ARMv7-A processor implementations (e.g, Qualcomm 8960, ARM Cortex-A5) > support fused multiply add/subtract instructions (VFMA/VFMS) which have > lower latency and greater accuracy than the chained multiply add/subtract > instructions (VMLA/VMLS). Patch generally looks ok. However, I'm not sure it's complete wrt build attributes. You're emitting only text version of neon attribute. What's about the .fpu stuff and around ? Look into ARMAsmPrinter.cpp a bit further than your changed lines here. What if our CPU does not support NEON at all, should we emit something like ".fpu vfpv4" ? -- With best regards, Anton Korobeynikov Faculty of Mathematics and Mechanics, Saint Petersburg State University -------------- next part -------------- A non-text attachment was scrubbed... Name: fusedMACpatch.diff Type: application/octet-stream Size: 20695 bytes Desc: not available Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20120104/db073999/attachment.obj From isanbard at gmail.com Wed Jan 4 20:13:20 2012 From: isanbard at gmail.com (Bill Wendling) Date: Thu, 05 Jan 2012 02:13:20 -0000 Subject: [llvm-commits] [llvm] r147593 - /llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Message-ID: <20120105021321.181722A6C12C@llvm.org> Author: void Date: Wed Jan 4 20:13:20 2012 New Revision: 147593 URL: http://llvm.org/viewvc/llvm-project?rev=147593&view=rev Log: Replace the uint64_t -> double convertion algorithm with one that's more efficient. This small bit of ASM code is sufficient to do what the old algorithm did: movq %rax, %xmm0 punpckldq (c0), %xmm0 // c0: (uint4){ 0x43300000U, 0x45300000U, 0U, 0U } subpd (c1), %xmm0 // c1: (double2){ 0x1.0p52, 0x1.0p52 * 0x1.0p32 } #ifdef __SSE3__ haddpd %xmm0, %xmm0 #else pshufd $0x4e, %xmm0, %xmm1 addpd %xmm1, %xmm0 #endif It's arguably faster. One caveat, the 'haddpd' instruction isn't very fast on all processors. Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=147593&r1=147592&r2=147593&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original) +++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Wed Jan 4 20:13:20 2012 @@ -256,7 +256,7 @@ if (Subtarget->is64Bit()) { setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote); - setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Expand); + setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom); } else if (!TM.Options.UseSoftFloat) { // We have an algorithm for SSE2->double, and we turn this into a // 64-bit FILD followed by conditional FADD for other targets. @@ -7581,38 +7581,17 @@ // LowerUINT_TO_FP_i64 - 64-bit unsigned integer to double expansion. SDValue X86TargetLowering::LowerUINT_TO_FP_i64(SDValue Op, SelectionDAG &DAG) const { - // This algorithm is not obvious. Here it is in C code, more or less: + // This algorithm is not obvious. Here it is what we're trying to output: /* - double uint64_to_double( uint32_t hi, uint32_t lo ) { - static const __m128i exp = { 0x4330000045300000ULL, 0 }; - static const __m128d bias = { 0x1.0p84, 0x1.0p52 }; - - // Copy ints to xmm registers. - __m128i xh = _mm_cvtsi32_si128( hi ); - __m128i xl = _mm_cvtsi32_si128( lo ); - - // Combine into low half of a single xmm register. - __m128i x = _mm_unpacklo_epi32( xh, xl ); - __m128d d; - double sd; - - // Merge in appropriate exponents to give the integer bits the right - // magnitude. - x = _mm_unpacklo_epi32( x, exp ); - - // Subtract away the biases to deal with the IEEE-754 double precision - // implicit 1. - d = _mm_sub_pd( (__m128d) x, bias ); - - // All conversions up to here are exact. The correctly rounded result is - // calculated using the current rounding mode using the following - // horizontal add. - d = _mm_add_sd( d, _mm_unpackhi_pd( d, d ) ); - _mm_store_sd( &sd, d ); // Because we are returning doubles in XMM, this - // store doesn't really need to be here (except - // maybe to zero the other double) - return sd; - } + movq %rax, %xmm0 + punpckldq (c0), %xmm0 // c0: (uint4){ 0x43300000U, 0x45300000U, 0U, 0U } + subpd (c1), %xmm0 // c1: (double2){ 0x1.0p52, 0x1.0p52 * 0x1.0p32 } + #ifdef __SSE3__ + haddpd %xmm0, %xmm0 + #else + pshufd $0x4e, %xmm0, %xmm1 + addpd %xmm1, %xmm0 + #endif */ DebugLoc dl = Op.getDebugLoc(); @@ -7620,8 +7599,8 @@ // Build some magic constants. SmallVector CV0; - CV0.push_back(ConstantInt::get(*Context, APInt(32, 0x45300000))); CV0.push_back(ConstantInt::get(*Context, APInt(32, 0x43300000))); + CV0.push_back(ConstantInt::get(*Context, APInt(32, 0x45300000))); CV0.push_back(ConstantInt::get(*Context, APInt(32, 0))); CV0.push_back(ConstantInt::get(*Context, APInt(32, 0))); Constant *C0 = ConstantVector::get(CV0); @@ -7629,37 +7608,42 @@ SmallVector CV1; CV1.push_back( - ConstantFP::get(*Context, APFloat(APInt(64, 0x4530000000000000ULL)))); - CV1.push_back( ConstantFP::get(*Context, APFloat(APInt(64, 0x4330000000000000ULL)))); + CV1.push_back( + ConstantFP::get(*Context, APFloat(APInt(64, 0x4530000000000000ULL)))); Constant *C1 = ConstantVector::get(CV1); SDValue CPIdx1 = DAG.getConstantPool(C1, getPointerTy(), 16); - SDValue XR1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, - DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, - Op.getOperand(0), - DAG.getIntPtrConstant(1))); - SDValue XR2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, - DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, - Op.getOperand(0), - DAG.getIntPtrConstant(0))); - SDValue Unpck1 = getUnpackl(DAG, dl, MVT::v4i32, XR1, XR2); + // Load the 64-bit value into an XMM register. + SDValue XR1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, + Op.getOperand(0)); SDValue CLod0 = DAG.getLoad(MVT::v4i32, dl, DAG.getEntryNode(), CPIdx0, MachinePointerInfo::getConstantPool(), false, false, false, 16); - SDValue Unpck2 = getUnpackl(DAG, dl, MVT::v4i32, Unpck1, CLod0); - SDValue XR2F = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Unpck2); + SDValue Unpck1 = getUnpackl(DAG, dl, MVT::v4i32, + DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, XR1), + CLod0); + SDValue CLod1 = DAG.getLoad(MVT::v2f64, dl, CLod0.getValue(1), CPIdx1, MachinePointerInfo::getConstantPool(), false, false, false, 16); + SDValue XR2F = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Unpck1); SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, XR2F, CLod1); + SDValue Result; - // Add the halves; easiest way is to swap them into another reg first. - int ShufMask[2] = { 1, -1 }; - SDValue Shuf = DAG.getVectorShuffle(MVT::v2f64, dl, Sub, - DAG.getUNDEF(MVT::v2f64), ShufMask); - SDValue Add = DAG.getNode(ISD::FADD, dl, MVT::v2f64, Shuf, Sub); - return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Add, + if (Subtarget->hasSSE3()) { + // FIXME: The 'haddpd' instruction may be slower than 'movhlps + addsd'. + Result = DAG.getNode(X86ISD::FHADD, dl, MVT::v2f64, Sub, Sub); + } else { + SDValue S2F = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Sub); + SDValue Shuffle = getTargetShuffleNode(X86ISD::PSHUFD, dl, MVT::v4i32, + S2F, 0x4E, DAG); + Result = DAG.getNode(ISD::FADD, dl, MVT::v2f64, + DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Shuffle), + Sub); + } + + return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Result, DAG.getIntPtrConstant(0)); } @@ -7729,6 +7713,8 @@ return LowerUINT_TO_FP_i64(Op, DAG); else if (SrcVT == MVT::i32 && X86ScalarSSEf64) return LowerUINT_TO_FP_i32(Op, DAG); + else if (SrcVT == MVT::i64 && DstVT == MVT::f32) + return SDValue(); // Make a 64-bit buffer, and use it to build an FILD. SDValue StackSlot = DAG.CreateStackTemporary(MVT::i64); From atrick at apple.com Wed Jan 4 20:52:12 2012 From: atrick at apple.com (Andrew Trick) Date: Thu, 05 Jan 2012 02:52:12 -0000 Subject: [llvm-commits] [llvm] r147594 - /llvm/trunk/lib/CodeGen/ScheduleDAGInstrs.cpp Message-ID: <20120105025212.43CDF2A6C12C@llvm.org> Author: atrick Date: Wed Jan 4 20:52:11 2012 New Revision: 147594 URL: http://llvm.org/viewvc/llvm-project?rev=147594&view=rev Log: Minor postra scheduler cleanup. It could result in more precise antidependence latency on ARM in exceedingly rare cases. Modified: llvm/trunk/lib/CodeGen/ScheduleDAGInstrs.cpp Modified: llvm/trunk/lib/CodeGen/ScheduleDAGInstrs.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/ScheduleDAGInstrs.cpp?rev=147594&r1=147593&r2=147594&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/ScheduleDAGInstrs.cpp (original) +++ llvm/trunk/lib/CodeGen/ScheduleDAGInstrs.cpp Wed Jan 4 20:52:11 2012 @@ -260,9 +260,6 @@ assert(TRI->isPhysicalRegister(Reg) && "Virtual register encountered!"); - std::vector &UseList = Uses[Reg]; - // Defs are push in the order they are visited and never reordered. - std::vector &DefList = Defs[Reg]; // Optionally add output and anti dependencies. For anti // dependencies we use a latency of 0 because for a multi-issue // target we want to allow the defining instruction to issue @@ -271,36 +268,33 @@ // there's no cost for reusing registers. SDep::Kind Kind = MO.isUse() ? SDep::Anti : SDep::Output; unsigned AOLatency = (Kind == SDep::Anti) ? 0 : 1; - for (unsigned i = 0, e = DefList.size(); i != e; ++i) { - SUnit *DefSU = DefList[i]; - if (DefSU == &ExitSU) - continue; - if (DefSU != SU && - (Kind != SDep::Output || !MO.isDead() || - !DefSU->getInstr()->registerDefIsDead(Reg))) { - if (Kind == SDep::Anti) - DefSU->addPred(SDep(SU, Kind, 0, /*Reg=*/Reg)); - else { - unsigned AOLat = TII->getOutputLatency(InstrItins, MI, j, - DefSU->getInstr()); - DefSU->addPred(SDep(SU, Kind, AOLat, /*Reg=*/Reg)); - } - } - } - for (const unsigned *Alias = TRI->getAliasSet(Reg); *Alias; ++Alias) { - std::vector &MemDefList = Defs[*Alias]; - for (unsigned i = 0, e = MemDefList.size(); i != e; ++i) { - SUnit *DefSU = MemDefList[i]; + for (const unsigned *Alias = TRI->getOverlaps(Reg); *Alias; ++Alias) { + std::vector &DefList = Defs[*Alias]; + for (unsigned i = 0, e = DefList.size(); i != e; ++i) { + SUnit *DefSU = DefList[i]; if (DefSU == &ExitSU) continue; if (DefSU != SU && (Kind != SDep::Output || !MO.isDead() || - !DefSU->getInstr()->registerDefIsDead(*Alias))) - DefSU->addPred(SDep(SU, Kind, AOLatency, /*Reg=*/ *Alias)); + !DefSU->getInstr()->registerDefIsDead(*Alias))) { + if (Kind == SDep::Anti) + DefSU->addPred(SDep(SU, Kind, 0, /*Reg=*/*Alias)); + else { + unsigned AOLat = TII->getOutputLatency(InstrItins, MI, j, + DefSU->getInstr()); + DefSU->addPred(SDep(SU, Kind, AOLat, /*Reg=*/*Alias)); + } + } } } + // Retrieve the UseList to add data dependencies and update uses. + std::vector &UseList = Uses[Reg]; if (MO.isDef()) { + // Update DefList. Defs are pushed in the order they are visited and + // never reordered. + std::vector &DefList = Defs[Reg]; + // Add any data dependencies. unsigned DataLatency = SU->Latency; for (unsigned i = 0, e = UseList.size(); i != e; ++i) { From jcarter at mips.com Wed Jan 4 22:33:38 2012 From: jcarter at mips.com (Carter, Jack) Date: Thu, 5 Jan 2012 04:33:38 +0000 Subject: [llvm-commits] [Mips] Direct object big endian review and submittal request Message-ID: <86AC779C188FE74F88F6494478B46332E9156D@exchdb03.mips.com> The bigest changes are to endianize the opcode and then the fixups. I am less than thrilled that we have to do this at this level of the compiler and not at a higher level, but that will be a battle for another day. I am also concerned that there seems to be an assumption that the host machine will be little endian. Instead of checking if the target is big or little endian I would have thought we would be asking if it was a different endian or not. Contributers: Jack Carter # # modified: MCTargetDesc/MipsAsmBackend.cpp # modified: MCTargetDesc/MipsMCCodeEmitter.cpp # modified: MCTargetDesc/MipsMCTargetDesc.cpp # modified: MCTargetDesc/MipsMCTargetDesc.h # new : test/MC/Mips/elf-bigendian.ll -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20120105/a11ac3d3/attachment-0001.html -------------- next part -------------- A non-text attachment was scrubbed... Name: big_endian.patch Type: text/x-patch Size: 20063 bytes Desc: big_endian.patch Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20120105/a11ac3d3/attachment-0001.bin From evan.cheng at apple.com Thu Jan 5 01:09:08 2012 From: evan.cheng at apple.com (Evan Cheng) Date: Wed, 04 Jan 2012 23:09:08 -0800 Subject: [llvm-commits] x86 branch sequence optimization in LLVM code gen: please review In-Reply-To: References: <021AD592C708E24FA11FD214489EC9BE0123F25260@hasmsx501.ger.corp.intel.com> <021AD592C708E24FA11FD214489EC9BE0123F95DDF@hasmsx501.ger.corp.intel.com> <90F01864-DEB5-4DEA-B8E2-625EF4449126@apple.com> <021AD592C708E24FA11FD214489EC9BE0123FE98C8@hasmsx501.ger.corp.intel.com> <021AD592C708E24FA11FD214489EC9BE01269D1FA3@hasmsx501.ger.corp.intel.com> Message-ID: Has someone reviewed the updated patch? Evan On Dec 21, 2011, at 8:10 AM, Umansky, Victor wrote: > Replacing patch with a newer one. > Changes: aligned naming policy with that of LLVM. > > Victor > > -----Original Message----- > From: llvm-commits-bounces at cs.uiuc.edu [mailto:llvm-commits-bounces at cs.uiuc.edu] On Behalf Of Umansky, Victor > Sent: Wednesday, December 21, 2011 11:01 > To: Bruno Cardoso Lopes > Cc: llvm-commits at cs.uiuc.edu > Subject: Re: [llvm-commits] x86 branch sequence optimization in LLVM code gen: please review > > Hi Bruno, > > I've updated the patch with additional peephole-optimization patterns and with additional AVX-specific LIT test. > > Can you please review, so that I'll proceed to commit the fixes? > > Best Regards, > Victor > > -----Original Message----- > From: llvm-commits-bounces at cs.uiuc.edu [mailto:llvm-commits-bounces at cs.uiuc.edu] On Behalf Of Umansky, Victor > Sent: Thursday, December 15, 2011 20:09 > To: Bruno Cardoso Lopes > Cc: llvm-commits at cs.uiuc.edu > Subject: Re: [llvm-commits] x86 branch sequence optimization in LLVM code gen: please review > > Hi Bruno, > > Please see attached the patch. > > It incorporates the feedback, and I yet extended it with coverage for more LLVM IR patterns related to usage of ptestz/ptestc LLVM built-ins (tests are also extended). > > Best Regards, > Victor > > > -----Original Message----- > From: Bruno Cardoso Lopes [mailto:bruno.cardoso at gmail.com] > Sent: Friday, December 09, 2011 04:25 > To: Umansky, Victor > Cc: Chad Rosier; Anton Korobeynikov; bruno.cardoso at gmail.com; llvm-commits at cs.uiuc.edu > Subject: Re: [llvm-commits] x86 branch sequence optimization in LLVM code gen: please review > > On Wed, Dec 7, 2011 at 1:03 PM, Umansky, Victor wrote: >> >> Hi Chad, Anton, Bruno, >> >> >> >> Thank you for the suggestion. >> >> >> >> Unfortunately, it won't work in the case of brcond.ll file. >> >> >> >> Indeed I can introduce different "check-prefix" values in order to separate checks for "core2" case from those for "penryn" case. >> >> However, the compilation of all functions in a file will be done unconditionally for both "RUN" cases. And this will inevitably lead to the test failure (in instruction selection) when a function using "ptest" LLVM intrinsic will be processed with "-mcpu=core2" option. >> >> That's why I was not able to include the test cases for "ptest" intrinsic sequence to a file which will be compiled for a pre-Penryn target. >> >> >> >> A solution which does work is to have legacy brcond.ll LIT tests running under "-mcpu=penryn". >> >> I'm attaching the file. >> >> Are you OK with such solution? > > LGTM, please resend the orignal patch with the testcase (both in the same patch file)! Also remove the trailing CRs and generate the diff with "svn diff" under the project root. If you have any question, the docs may help: http://llvm.org/docs/DeveloperPolicy.html#patches > > -- > Bruno Cardoso Lopes > http://www.brunocardoso.cc > --------------------------------------------------------------------- > Intel Israel (74) Limited > > This e-mail and any attachments may contain confidential material for the sole use of the intended recipient(s). Any review or distribution by others is strictly prohibited. If you are not the intended recipient, please contact the sender and delete all copies. > --------------------------------------------------------------------- > Intel Israel (74) Limited > > This e-mail and any attachments may contain confidential material for the sole use of the intended recipient(s). Any review or distribution by others is strictly prohibited. If you are not the intended recipient, please contact the sender and delete all copies. > --------------------------------------------------------------------- > Intel Israel (74) Limited > > This e-mail and any attachments may contain confidential material for > the sole use of the intended recipient(s). Any review or distribution > by others is strictly prohibited. If you are not the intended > recipient, please contact the sender and delete all copies. > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From evan.cheng at apple.com Thu Jan 5 01:12:42 2012 From: evan.cheng at apple.com (Evan Cheng) Date: Wed, 04 Jan 2012 23:12:42 -0800 Subject: [llvm-commits] PATCH: ARM_TARGET1 relocation for C++ global constructors In-Reply-To: <000c01ccbff2$ee95d750$cbc185f0$%molloy@arm.com> References: <000c01ccbff2$ee95d750$cbc185f0$%molloy@arm.com> Message-ID: Has this been reviewed? I'm not sure if this patch is correct for all platforms, e.g. iOS. Jim, Kevin, and Owen, do you guys know? Evan On Dec 21, 2011, at 7:12 AM, James Molloy wrote: > Hi, > > Attached is a patch to cause the relocations for C++ global/static constructor thunks to be outputted properly on ARM. The ABI states that these thunks should have an R_ARM_TARGET1 relocation type applied to them for portability reasons. Currently they?re emitted as normal global variables so get an R_ARM_ABS32. > > I?ve implemented this by creating a new overridable hook, ?EmitXXStructor()?, in the AsmPrinter. For all targets this defaults to EmitGlobalConstant as usual, but ARM overrides it to emit a constant with this specific relocation type. > > Am I OK to commit? > > Cheers, > > James > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20120104/4eeb88ce/attachment.html From evan.cheng at apple.com Thu Jan 5 01:14:55 2012 From: evan.cheng at apple.com (Evan Cheng) Date: Wed, 04 Jan 2012 23:14:55 -0800 Subject: [llvm-commits] JIT/MCJIT::getPointerToNamedFunction() In-Reply-To: <6AE1604EE3EC5F4296C096518C6B77EE1AA4D191F3@mail.accesssoftek.com> References: <6AE1604EE3EC5F4296C096518C6B77EE1AA4D191F3@mail.accesssoftek.com> Message-ID: Eric, can you review the patch? Thanks, Evan On Dec 21, 2011, at 1:47 PM, Danil Malyshev wrote: > ping > > From: Danil Malyshev > Sent: Friday, December 16, 2011 1:02 AM > To: 'llvm-commits at cs.uiuc.edu' > Subject: JIT/MCJIT::getPointerToNamedFunction() > > Hello everyone, > > > Please find attached the patch for review. > It's a small re-factored JIT/MCJIT::getPointerToNamedFunction(), so it could be called with the base class. > > > Regards, > Danil > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20120104/267f827b/attachment.html From victor.umansky at intel.com Thu Jan 5 01:25:21 2012 From: victor.umansky at intel.com (Umansky, Victor) Date: Thu, 5 Jan 2012 07:25:21 +0000 Subject: [llvm-commits] x86 branch sequence optimization in LLVM code gen: please review In-Reply-To: References: <021AD592C708E24FA11FD214489EC9BE0123F25260@hasmsx501.ger.corp.intel.com> <021AD592C708E24FA11FD214489EC9BE0123F95DDF@hasmsx501.ger.corp.intel.com> <90F01864-DEB5-4DEA-B8E2-625EF4449126@apple.com> <021AD592C708E24FA11FD214489EC9BE0123FE98C8@hasmsx501.ger.corp.intel.com> <021AD592C708E24FA11FD214489EC9BE01269D1FA3@hasmsx501.ger.corp.intel.com> Message-ID: No, I haven't received any feedback. Would you? Victor -----Original Message----- From: Evan Cheng [mailto:evan.cheng at apple.com] Sent: Thursday, January 05, 2012 09:09 To: Umansky, Victor Cc: Bruno Cardoso Lopes; llvm-commits at cs.uiuc.edu Subject: Re: [llvm-commits] x86 branch sequence optimization in LLVM code gen: please review Has someone reviewed the updated patch? Evan On Dec 21, 2011, at 8:10 AM, Umansky, Victor wrote: > Replacing patch with a newer one. > Changes: aligned naming policy with that of LLVM. > > Victor > > -----Original Message----- > From: llvm-commits-bounces at cs.uiuc.edu [mailto:llvm-commits-bounces at cs.uiuc.edu] On Behalf Of Umansky, Victor > Sent: Wednesday, December 21, 2011 11:01 > To: Bruno Cardoso Lopes > Cc: llvm-commits at cs.uiuc.edu > Subject: Re: [llvm-commits] x86 branch sequence optimization in LLVM code gen: please review > > Hi Bruno, > > I've updated the patch with additional peephole-optimization patterns and with additional AVX-specific LIT test. > > Can you please review, so that I'll proceed to commit the fixes? > > Best Regards, > Victor > > -----Original Message----- > From: llvm-commits-bounces at cs.uiuc.edu [mailto:llvm-commits-bounces at cs.uiuc.edu] On Behalf Of Umansky, Victor > Sent: Thursday, December 15, 2011 20:09 > To: Bruno Cardoso Lopes > Cc: llvm-commits at cs.uiuc.edu > Subject: Re: [llvm-commits] x86 branch sequence optimization in LLVM code gen: please review > > Hi Bruno, > > Please see attached the patch. > > It incorporates the feedback, and I yet extended it with coverage for more LLVM IR patterns related to usage of ptestz/ptestc LLVM built-ins (tests are also extended). > > Best Regards, > Victor > > > -----Original Message----- > From: Bruno Cardoso Lopes [mailto:bruno.cardoso at gmail.com] > Sent: Friday, December 09, 2011 04:25 > To: Umansky, Victor > Cc: Chad Rosier; Anton Korobeynikov; bruno.cardoso at gmail.com; llvm-commits at cs.uiuc.edu > Subject: Re: [llvm-commits] x86 branch sequence optimization in LLVM code gen: please review > > On Wed, Dec 7, 2011 at 1:03 PM, Umansky, Victor wrote: >> >> Hi Chad, Anton, Bruno, >> >> >> >> Thank you for the suggestion. >> >> >> >> Unfortunately, it won't work in the case of brcond.ll file. >> >> >> >> Indeed I can introduce different "check-prefix" values in order to separate checks for "core2" case from those for "penryn" case. >> >> However, the compilation of all functions in a file will be done unconditionally for both "RUN" cases. And this will inevitably lead to the test failure (in instruction selection) when a function using "ptest" LLVM intrinsic will be processed with "-mcpu=core2" option. >> >> That's why I was not able to include the test cases for "ptest" intrinsic sequence to a file which will be compiled for a pre-Penryn target. >> >> >> >> A solution which does work is to have legacy brcond.ll LIT tests running under "-mcpu=penryn". >> >> I'm attaching the file. >> >> Are you OK with such solution? > > LGTM, please resend the orignal patch with the testcase (both in the same patch file)! Also remove the trailing CRs and generate the diff with "svn diff" under the project root. If you have any question, the docs may help: http://llvm.org/docs/DeveloperPolicy.html#patches > > -- > Bruno Cardoso Lopes > http://www.brunocardoso.cc > --------------------------------------------------------------------- > Intel Israel (74) Limited > > This e-mail and any attachments may contain confidential material for the sole use of the intended recipient(s). Any review or distribution by others is strictly prohibited. If you are not the intended recipient, please contact the sender and delete all copies. > --------------------------------------------------------------------- > Intel Israel (74) Limited > > This e-mail and any attachments may contain confidential material for the sole use of the intended recipient(s). Any review or distribution by others is strictly prohibited. If you are not the intended recipient, please contact the sender and delete all copies. > --------------------------------------------------------------------- > Intel Israel (74) Limited > > This e-mail and any attachments may contain confidential material for > the sole use of the intended recipient(s). Any review or distribution > by others is strictly prohibited. If you are not the intended > recipient, please contact the sender and delete all copies. > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits --------------------------------------------------------------------- Intel Israel (74) Limited This e-mail and any attachments may contain confidential material for the sole use of the intended recipient(s). Any review or distribution by others is strictly prohibited. If you are not the intended recipient, please contact the sender and delete all copies. From evan.cheng at apple.com Thu Jan 5 01:27:03 2012 From: evan.cheng at apple.com (Evan Cheng) Date: Wed, 04 Jan 2012 23:27:03 -0800 Subject: [llvm-commits] [PATCH]fix typo in LegalizeIntegerTypes.cpp In-Reply-To: <042D0278E37F0F40BF8993003DC42910037B11@HASMSX104.ger.corp.intel.com> References: <042D0278E37F0F40BF8993003DC42910037B11@HASMSX104.ger.corp.intel.com> Message-ID: <4C855756-553E-4387-BD29-40C4321EAE11@apple.com> Has this been reviewed / committed? Evan On Dec 25, 2011, at 8:06 AM, Shemer, Anat wrote: > Hi, > > I found the following typo in WidenVector case of PromoteIntRes_BIT_CONVERT method, where the original output value type is used rather than the type after transformation. I found it in a code review so I have no specific test for it. The diff is below. > > Thanks, Anat > > Index: lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp > =================================================================== > --- lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp (revision 147140) > +++ lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp (working copy) > @@ -252,9 +252,9 @@ > return DAG.getNode(ISD::BITCAST, dl, NOutVT, InOp); > } > case TargetLowering::TypeWidenVector: > - if (OutVT.bitsEq(NInVT)) > + if (NOutVT.bitsEq(NInVT)) > // The input is widened to the same size. Convert to the widened value. > - return DAG.getNode(ISD::BITCAST, dl, OutVT, GetWidenedVector(InOp)); > + return DAG.getNode(ISD::BITCAST, dl, NOutVT, GetWidenedVector(InOp)); > } > > return DAG.getNode(ISD::ANY_EXTEND, dl, NOutVT, > > > --------------------------------------------------------------------- > Intel Israel (74) Limited > > This e-mail and any attachments may contain confidential material for > the sole use of the intended recipient(s). Any review or distribution > by others is strictly prohibited. If you are not the intended > recipient, please contact the sender and delete all copies. _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20120104/ed109455/attachment.html From victor.umansky at intel.com Thu Jan 5 01:31:39 2012 From: victor.umansky at intel.com (Umansky, Victor) Date: Thu, 5 Jan 2012 07:31:39 +0000 Subject: [llvm-commits] x86 branch sequence optimization in LLVM code gen: please review References: <021AD592C708E24FA11FD214489EC9BE0123F25260@hasmsx501.ger.corp.intel.com> <021AD592C708E24FA11FD214489EC9BE0123F95DDF@hasmsx501.ger.corp.intel.com> <90F01864-DEB5-4DEA-B8E2-625EF4449126@apple.com> <021AD592C708E24FA11FD214489EC9BE0123FE98C8@hasmsx501.ger.corp.intel.com> <021AD592C708E24FA11FD214489EC9BE01269D1FA3@hasmsx501.ger.corp.intel.com> Message-ID: A correction: Elena Demikhovsky (elena.demikhovsky at intel.com) reviewed the updated patch (face-to-face, in Intel). Victor -----Original Message----- From: Umansky, Victor Sent: Thursday, January 05, 2012 09:25 To: 'Evan Cheng' Cc: Bruno Cardoso Lopes; llvm-commits at cs.uiuc.edu Subject: RE: [llvm-commits] x86 branch sequence optimization in LLVM code gen: please review No, I haven't received any feedback. Would you? Victor -----Original Message----- From: Evan Cheng [mailto:evan.cheng at apple.com] Sent: Thursday, January 05, 2012 09:09 To: Umansky, Victor Cc: Bruno Cardoso Lopes; llvm-commits at cs.uiuc.edu Subject: Re: [llvm-commits] x86 branch sequence optimization in LLVM code gen: please review Has someone reviewed the updated patch? Evan On Dec 21, 2011, at 8:10 AM, Umansky, Victor wrote: > Replacing patch with a newer one. > Changes: aligned naming policy with that of LLVM. > > Victor > > -----Original Message----- > From: llvm-commits-bounces at cs.uiuc.edu [mailto:llvm-commits-bounces at cs.uiuc.edu] On Behalf Of Umansky, Victor > Sent: Wednesday, December 21, 2011 11:01 > To: Bruno Cardoso Lopes > Cc: llvm-commits at cs.uiuc.edu > Subject: Re: [llvm-commits] x86 branch sequence optimization in LLVM code gen: please review > > Hi Bruno, > > I've updated the patch with additional peephole-optimization patterns and with additional AVX-specific LIT test. > > Can you please review, so that I'll proceed to commit the fixes? > > Best Regards, > Victor > > -----Original Message----- > From: llvm-commits-bounces at cs.uiuc.edu [mailto:llvm-commits-bounces at cs.uiuc.edu] On Behalf Of Umansky, Victor > Sent: Thursday, December 15, 2011 20:09 > To: Bruno Cardoso Lopes > Cc: llvm-commits at cs.uiuc.edu > Subject: Re: [llvm-commits] x86 branch sequence optimization in LLVM code gen: please review > > Hi Bruno, > > Please see attached the patch. > > It incorporates the feedback, and I yet extended it with coverage for more LLVM IR patterns related to usage of ptestz/ptestc LLVM built-ins (tests are also extended). > > Best Regards, > Victor > > > -----Original Message----- > From: Bruno Cardoso Lopes [mailto:bruno.cardoso at gmail.com] > Sent: Friday, December 09, 2011 04:25 > To: Umansky, Victor > Cc: Chad Rosier; Anton Korobeynikov; bruno.cardoso at gmail.com; llvm-commits at cs.uiuc.edu > Subject: Re: [llvm-commits] x86 branch sequence optimization in LLVM code gen: please review > > On Wed, Dec 7, 2011 at 1:03 PM, Umansky, Victor wrote: >> >> Hi Chad, Anton, Bruno, >> >> >> >> Thank you for the suggestion. >> >> >> >> Unfortunately, it won't work in the case of brcond.ll file. >> >> >> >> Indeed I can introduce different "check-prefix" values in order to separate checks for "core2" case from those for "penryn" case. >> >> However, the compilation of all functions in a file will be done unconditionally for both "RUN" cases. And this will inevitably lead to the test failure (in instruction selection) when a function using "ptest" LLVM intrinsic will be processed with "-mcpu=core2" option. >> >> That's why I was not able to include the test cases for "ptest" intrinsic sequence to a file which will be compiled for a pre-Penryn target. >> >> >> >> A solution which does work is to have legacy brcond.ll LIT tests running under "-mcpu=penryn". >> >> I'm attaching the file. >> >> Are you OK with such solution? > > LGTM, please resend the orignal patch with the testcase (both in the same patch file)! Also remove the trailing CRs and generate the diff with "svn diff" under the project root. If you have any question, the docs may help: http://llvm.org/docs/DeveloperPolicy.html#patches > > -- > Bruno Cardoso Lopes > http://www.brunocardoso.cc > --------------------------------------------------------------------- > Intel Israel (74) Limited > > This e-mail and any attachments may contain confidential material for the sole use of the intended recipient(s). Any review or distribution by others is strictly prohibited. If you are not the intended recipient, please contact the sender and delete all copies. > --------------------------------------------------------------------- > Intel Israel (74) Limited > > This e-mail and any attachments may contain confidential material for the sole use of the intended recipient(s). Any review or distribution by others is strictly prohibited. If you are not the intended recipient, please contact the sender and delete all copies. > --------------------------------------------------------------------- > Intel Israel (74) Limited > > This e-mail and any attachments may contain confidential material for > the sole use of the intended recipient(s). Any review or distribution > by others is strictly prohibited. If you are not the intended > recipient, please contact the sender and delete all copies. > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits --------------------------------------------------------------------- Intel Israel (74) Limited This e-mail and any attachments may contain confidential material for the sole use of the intended recipient(s). Any review or distribution by others is strictly prohibited. If you are not the intended recipient, please contact the sender and delete all copies. From nadav.rotem at intel.com Thu Jan 5 01:39:24 2012 From: nadav.rotem at intel.com (Rotem, Nadav) Date: Thu, 5 Jan 2012 07:39:24 +0000 Subject: [llvm-commits] [PATCH]fix typo in LegalizeIntegerTypes.cpp In-Reply-To: <4C855756-553E-4387-BD29-40C4321EAE11@apple.com> References: <042D0278E37F0F40BF8993003DC42910037B11@HASMSX104.ger.corp.intel.com> <4C855756-553E-4387-BD29-40C4321EAE11@apple.com> Message-ID: <7DE70FDACDE4CD4887C4278C12A2E305057B86@HASMSX104.ger.corp.intel.com> Yes. I committed it. From: llvm-commits-bounces at cs.uiuc.edu [mailto:llvm-commits-bounces at cs.uiuc.edu] On Behalf Of Evan Cheng Sent: Thursday, January 05, 2012 09:27 To: Shemer, Anat Cc: llvm-commits at cs.uiuc.edu Subject: Re: [llvm-commits] [PATCH]fix typo in LegalizeIntegerTypes.cpp Has this been reviewed / committed? Evan On Dec 25, 2011, at 8:06 AM, Shemer, Anat wrote: Hi, I found the following typo in WidenVector case of PromoteIntRes_BIT_CONVERT method, where the original output value type is used rather than the type after transformation. I found it in a code review so I have no specific test for it. The diff is below. Thanks, Anat Index: lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp =================================================================== --- lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp (revision 147140) +++ lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp (working copy) @@ -252,9 +252,9 @@ return DAG.getNode(ISD::BITCAST, dl, NOutVT, InOp); } case TargetLowering::TypeWidenVector: - if (OutVT.bitsEq(NInVT)) + if (NOutVT.bitsEq(NInVT)) // The input is widened to the same size. Convert to the widened value. - return DAG.getNode(ISD::BITCAST, dl, OutVT, GetWidenedVector(InOp)); + return DAG.getNode(ISD::BITCAST, dl, NOutVT, GetWidenedVector(InOp)); } return DAG.getNode(ISD::ANY_EXTEND, dl, NOutVT, --------------------------------------------------------------------- Intel Israel (74) Limited This e-mail and any attachments may contain confidential material for the sole use of the intended recipient(s). Any review or distribution by others is strictly prohibited. If you are not the intended recipient, please contact the sender and delete all copies. _______________________________________________ llvm-commits mailing list llvm-commits at cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits --------------------------------------------------------------------- Intel Israel (74) Limited This e-mail and any attachments may contain confidential material for the sole use of the intended recipient(s). Any review or distribution by others is strictly prohibited. If you are not the intended recipient, please contact the sender and delete all copies. -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20120105/fd6e474e/attachment.html From evan.cheng at apple.com Thu Jan 5 01:40:13 2012 From: evan.cheng at apple.com (Evan Cheng) Date: Wed, 04 Jan 2012 23:40:13 -0800 Subject: [llvm-commits] X86SSELevel for AVX architecture In-Reply-To: References: Message-ID: <59E3DCF2-4D1D-4BC1-B517-E97288C4B01F@apple.com> On Jan 2, 2012, at 12:25 AM, Craig Topper wrote: > The instruction selection patterns are not ordered correctly to prefer AVX version of instructions over SSE versions. So until the patterns are properly ordered or we make the HasSSE functions specifically check that AVX is not enabled we can't change the code in X86Subtarget. Right. That's why the hack is in X86Subtarget.cpp. I agree with you that the right fix is to change HasSSE predicate to HasSSE && !HasAVX except for instructions which do not have separate AVX variants. Evan > > On Mon, Jan 2, 2012 at 12:18 AM, Demikhovsky, Elena wrote: > I think that ?HasAVX? should always cover ?HasSSE42? and ?HasSSE42orAVX? is redundant in this case. > > And ?HasAVX2? will cover ?HasAVX?. > > I propose to change in X86Subtarget constructor from: > > if (HasAVX) > > X86SSELevel = NoMMXSSE; > > > > to > > if (HasAVX) > > X86SSELevel = SSE42; > > > > - Elena > > From: llvm-commits-bounces at cs.uiuc.edu [mailto:llvm-commits-bounces at cs.uiuc.edu] On Behalf Of Craig Topper > Sent: Sunday, January 01, 2012 21:56 > To: Umansky, Victor > Cc: llvm-commits at cs.uiuc.edu > Subject: Re: [llvm-commits] X86SSELevel for AVX architecture > > > > Missed the CRC32 instructions. They have now been fixed in r147411. > > On Sun, Jan 1, 2012 at 1:44 PM, Craig Topper wrote: > > Fixed sfence, mfence, lfence, clflush, monitor, and mwait in r147409. > > > > On Sun, Jan 1, 2012 at 1:06 PM, Craig Topper wrote: > > This is similar to the fix for the prefetch instruction in r146163. I think the fence instructions and clflush are similarly broken. I'll see if I can find any others and I'll commit a fix. > > On Sun, Jan 1, 2012 at 10:18 AM, Umansky, Victor wrote: > > Hi Evan, > > > > I noticed that in X86Subtarget constructor you set ?X86SSELevel? member of the class as ?NoMMXSSE? in the case when HasAVX member is set to ?true?. > > Effectively that invalidates SSE features for AVX architecture - because hasSSEn() accessors return ?false? when HasAVXn() is ?true?. > > I wonder whether this is the behavior which you?d like to enforce ? as conceptually AVX architecture complements SSE rather than replaces it completely. > > > > I noticed this problem after discovering that LLVM fails to lower ?sse2.fence? intrinsic when generating a code for AVX architecture ? because this intrinsic is conditioned on hasSSE2() being ?true?. > > Is that case was somehow missed from regression testing, or there is another way to lower that intrinsic? > > > > I?d appreciate your clarifications. > > > > Best Regards, > > Victor Umansky > > > > --------------------------------------------------------------------- > Intel Israel (74) Limited > > This e-mail and any attachments may contain confidential material for > the sole use of the intended recipient(s). Any review or distribution > by others is strictly prohibited. If you are not the intended > recipient, please contact the sender and delete all copies. > > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits > > > > > -- > ~Craig > > > > > -- > ~Craig > > > > > -- > ~Craig > > --------------------------------------------------------------------- > Intel Israel (74) Limited > > This e-mail and any attachments may contain confidential material for > the sole use of the intended recipient(s). Any review or distribution > by others is strictly prohibited. If you are not the intended > recipient, please contact the sender and delete all copies. > > > > -- > ~Craig > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20120104/9e6b2d02/attachment.html From evan.cheng at apple.com Thu Jan 5 01:42:23 2012 From: evan.cheng at apple.com (Evan Cheng) Date: Wed, 04 Jan 2012 23:42:23 -0800 Subject: [llvm-commits] [LLVM, SwitchInst, case ranges] Auxiliary patch #1 In-Reply-To: <200871325616668@web103.yandex.ru> References: <4EAA9B5D.802@narod.ru> <4EAA9DE8.80000@free.fr> <485181319805488@web67.yandex.ru> <4EAB079D.6000606@free.fr> <4EB18F12.6060409@narod.ru> <4EB7C319.1000709@narod.ru> <4EDE7D75.704@narod.ru> <4EDFD0F4.1040204@narod.ru> <4EE25B61.9070006@narod.ru> <4EE5C06C.3050705@narod.ru> <333531323974498@web57.yandex.ru> <4EEB9C52.1050301@narod.ru> <4EF37B6B.6000205@narod.ru> <4EFA0748.9080702@narod.ru> <4EFCAA6A.20203@narod.ru> <610731325498362@web6.yandex.ru> <200871325616668@web103.yandex.ru> Message-ID: <5633CF27-DD22-4595-A197-DFFCC56B6342@apple.com> Where is the patch? Can you attach it again? Thanks, Evan On Jan 3, 2012, at 10:51 AM, Stepan Dyatkovskiy wrote: > Ping. > -- > Truly yours, > Stepan Dyatkovskiy > > 02.01.2012, 13:59, "Stepan Dyatkovskiy" : >> Ping again and again :-) >> -Stepan. >> >> 29.12.2011, 21:59, "Stepan Dyatkovskiy" : >> >>> Ping. >>> -Stepan. >>> >>> Stepan Dyatkovskiy wrote: >>>> ping. >>>> Stepan Dyatkovskiy wrote: >>>>> Ping. >>>>> >>>>> Stepan Dyatkovskiy wrote: >>>>>> Ping. >>>>>> >>>>>> -Stepan. > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From evan.cheng at apple.com Thu Jan 5 01:47:57 2012 From: evan.cheng at apple.com (Evan Cheng) Date: Wed, 04 Jan 2012 23:47:57 -0800 Subject: [llvm-commits] x86 branch sequence optimization in LLVM code gen: please review In-Reply-To: References: <021AD592C708E24FA11FD214489EC9BE0123F25260@hasmsx501.ger.corp.intel.com> <021AD592C708E24FA11FD214489EC9BE0123F95DDF@hasmsx501.ger.corp.intel.com> <90F01864-DEB5-4DEA-B8E2-625EF4449126@apple.com> <021AD592C708E24FA11FD214489EC9BE0123FE98C8@hasmsx501.ger.corp.intel.com> <021AD592C708E24FA11FD214489EC9BE01269D1FA3@hasmsx501.ger.corp.intel.com> Message-ID: Minor nit-pick: +// Helper which returns index of constant operand of a two-operand node. +static inline int GetConstOpIndexFor2OpNode(SDValue Op) { + if (dyn_cast(Op.getOperand(0))) + return 0; + else if (dyn_cast(Op.getOperand(1))) + return 1; + else + return -1; +} Please replace dyn_cast with isa. Please also remove the last "else". That's the preferred llvm style. Thanks, Evan On Jan 4, 2012, at 11:31 PM, Umansky, Victor wrote: > A correction: > > Elena Demikhovsky (elena.demikhovsky at intel.com) reviewed the updated patch (face-to-face, in Intel). > > Victor > > -----Original Message----- > From: Umansky, Victor > Sent: Thursday, January 05, 2012 09:25 > To: 'Evan Cheng' > Cc: Bruno Cardoso Lopes; llvm-commits at cs.uiuc.edu > Subject: RE: [llvm-commits] x86 branch sequence optimization in LLVM code gen: please review > > No, I haven't received any feedback. > Would you? > > Victor > > -----Original Message----- > From: Evan Cheng [mailto:evan.cheng at apple.com] > Sent: Thursday, January 05, 2012 09:09 > To: Umansky, Victor > Cc: Bruno Cardoso Lopes; llvm-commits at cs.uiuc.edu > Subject: Re: [llvm-commits] x86 branch sequence optimization in LLVM code gen: please review > > Has someone reviewed the updated patch? > > Evan > > On Dec 21, 2011, at 8:10 AM, Umansky, Victor wrote: > >> Replacing patch with a newer one. >> Changes: aligned naming policy with that of LLVM. >> >> Victor >> >> -----Original Message----- >> From: llvm-commits-bounces at cs.uiuc.edu [mailto:llvm-commits-bounces at cs.uiuc.edu] On Behalf Of Umansky, Victor >> Sent: Wednesday, December 21, 2011 11:01 >> To: Bruno Cardoso Lopes >> Cc: llvm-commits at cs.uiuc.edu >> Subject: Re: [llvm-commits] x86 branch sequence optimization in LLVM code gen: please review >> >> Hi Bruno, >> >> I've updated the patch with additional peephole-optimization patterns and with additional AVX-specific LIT test. >> >> Can you please review, so that I'll proceed to commit the fixes? >> >> Best Regards, >> Victor >> >> -----Original Message----- >> From: llvm-commits-bounces at cs.uiuc.edu [mailto:llvm-commits-bounces at cs.uiuc.edu] On Behalf Of Umansky, Victor >> Sent: Thursday, December 15, 2011 20:09 >> To: Bruno Cardoso Lopes >> Cc: llvm-commits at cs.uiuc.edu >> Subject: Re: [llvm-commits] x86 branch sequence optimization in LLVM code gen: please review >> >> Hi Bruno, >> >> Please see attached the patch. >> >> It incorporates the feedback, and I yet extended it with coverage for more LLVM IR patterns related to usage of ptestz/ptestc LLVM built-ins (tests are also extended). >> >> Best Regards, >> Victor >> >> >> -----Original Message----- >> From: Bruno Cardoso Lopes [mailto:bruno.cardoso at gmail.com] >> Sent: Friday, December 09, 2011 04:25 >> To: Umansky, Victor >> Cc: Chad Rosier; Anton Korobeynikov; bruno.cardoso at gmail.com; llvm-commits at cs.uiuc.edu >> Subject: Re: [llvm-commits] x86 branch sequence optimization in LLVM code gen: please review >> >> On Wed, Dec 7, 2011 at 1:03 PM, Umansky, Victor wrote: >>> >>> Hi Chad, Anton, Bruno, >>> >>> >>> >>> Thank you for the suggestion. >>> >>> >>> >>> Unfortunately, it won't work in the case of brcond.ll file. >>> >>> >>> >>> Indeed I can introduce different "check-prefix" values in order to separate checks for "core2" case from those for "penryn" case. >>> >>> However, the compilation of all functions in a file will be done unconditionally for both "RUN" cases. And this will inevitably lead to the test failure (in instruction selection) when a function using "ptest" LLVM intrinsic will be processed with "-mcpu=core2" option. >>> >>> That's why I was not able to include the test cases for "ptest" intrinsic sequence to a file which will be compiled for a pre-Penryn target. >>> >>> >>> >>> A solution which does work is to have legacy brcond.ll LIT tests running under "-mcpu=penryn". >>> >>> I'm attaching the file. >>> >>> Are you OK with such solution? >> >> LGTM, please resend the orignal patch with the testcase (both in the same patch file)! Also remove the trailing CRs and generate the diff with "svn diff" under the project root. If you have any question, the docs may help: http://llvm.org/docs/DeveloperPolicy.html#patches >> >> -- >> Bruno Cardoso Lopes >> http://www.brunocardoso.cc >> --------------------------------------------------------------------- >> Intel Israel (74) Limited >> >> This e-mail and any attachments may contain confidential material for the sole use of the intended recipient(s). Any review or distribution by others is strictly prohibited. If you are not the intended recipient, please contact the sender and delete all copies. >> --------------------------------------------------------------------- >> Intel Israel (74) Limited >> >> This e-mail and any attachments may contain confidential material for the sole use of the intended recipient(s). Any review or distribution by others is strictly prohibited. If you are not the intended recipient, please contact the sender and delete all copies. >> --------------------------------------------------------------------- >> Intel Israel (74) Limited >> >> This e-mail and any attachments may contain confidential material for >> the sole use of the intended recipient(s). Any review or distribution >> by others is strictly prohibited. If you are not the intended >> recipient, please contact the sender and delete all copies. >> _______________________________________________ >> llvm-commits mailing list >> llvm-commits at cs.uiuc.edu >> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits > > --------------------------------------------------------------------- > Intel Israel (74) Limited > > This e-mail and any attachments may contain confidential material for > the sole use of the intended recipient(s). Any review or distribution > by others is strictly prohibited. If you are not the intended > recipient, please contact the sender and delete all copies. > From james.molloy at arm.com Thu Jan 5 01:56:05 2012 From: james.molloy at arm.com (James Molloy) Date: Thu, 5 Jan 2012 07:56:05 -0000 Subject: [llvm-commits] PATCH: ARM_TARGET1 relocation for C++ global constructors In-Reply-To: References: <000c01ccbff2$ee95d750$cbc185f0$%molloy@arm.com> Message-ID: <001301cccb7f$7a61b2d0$6f251870$@molloy@arm.com> Hi Evan, Has this been reviewed? No, not yet. I was going to ping about it today - I've been away as most of you have for the Christmas vacation. I have no idea on the correct behaviour for iOS, but this is an ELF specific relocation type. Perhaps the TARGET1 fixup should be treated as ARM_ABS32 in the MachO backend? Cheers, James From: Evan Cheng [mailto:evan.cheng at apple.com] Sent: 05 January 2012 07:13 To: James Molloy Cc: llvm-commits at cs.uiuc.edu for LLVM; Jim Grosbach; Owen Anderson; Kevin Enderby Subject: Re: [llvm-commits] PATCH: ARM_TARGET1 relocation for C++ global constructors Has this been reviewed? I'm not sure if this patch is correct for all platforms, e.g. iOS. Jim, Kevin, and Owen, do you guys know? Evan On Dec 21, 2011, at 7:12 AM, James Molloy wrote: Hi, Attached is a patch to cause the relocations for C++ global/static constructor thunks to be outputted properly on ARM. The ABI states that these thunks should have an R_ARM_TARGET1 relocation type applied to them for portability reasons. Currently they're emitted as normal global variables so get an R_ARM_ABS32. I've implemented this by creating a new overridable hook, "EmitXXStructor()", in the AsmPrinter. For all targets this defaults to EmitGlobalConstant as usual, but ARM overrides it to emit a constant with this specific relocation type. Am I OK to commit? Cheers, James _______________________________________________ llvm-commits mailing list llvm-commits at cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20120105/7572f11f/attachment.html From dblaikie at gmail.com Thu Jan 5 02:07:41 2012 From: dblaikie at gmail.com (David Blaikie) Date: Thu, 5 Jan 2012 00:07:41 -0800 Subject: [llvm-commits] x86 branch sequence optimization in LLVM code gen: please review In-Reply-To: References: <021AD592C708E24FA11FD214489EC9BE0123F25260@hasmsx501.ger.corp.intel.com> <021AD592C708E24FA11FD214489EC9BE0123F95DDF@hasmsx501.ger.corp.intel.com> <90F01864-DEB5-4DEA-B8E2-625EF4449126@apple.com> <021AD592C708E24FA11FD214489EC9BE0123FE98C8@hasmsx501.ger.corp.intel.com> <021AD592C708E24FA11FD214489EC9BE01269D1FA3@hasmsx501.ger.corp.intel.com> Message-ID: > Minor nit-pick: Even nitier nit-pick: > > +// Helper which returns index of constant operand of a two-operand node. > +static inline int GetConstOpIndexFor2OpNode(SDValue Op) { > + ?if (dyn_cast(Op.getOperand(0))) > + ? ?return 0; > + ?else if (dyn_cast(Op.getOperand(1))) > + ? ?return 1; > + ?else > + ? ?return -1; > +} > > Please replace dyn_cast with isa. Please also remove the last "else". That's the preferred llvm style. Removing not just the last else, but both elses would be idiomatic of LLVM. - David > Thanks, > > Evan > > On Jan 4, 2012, at 11:31 PM, Umansky, Victor wrote: > >> A correction: >> >> Elena Demikhovsky (elena.demikhovsky at intel.com) reviewed the updated patch (face-to-face, in Intel). >> >> Victor >> >> -----Original Message----- >> From: Umansky, Victor >> Sent: Thursday, January 05, 2012 09:25 >> To: 'Evan Cheng' >> Cc: Bruno Cardoso Lopes; llvm-commits at cs.uiuc.edu >> Subject: RE: [llvm-commits] x86 branch sequence optimization in LLVM code gen: please review >> >> No, I haven't received any feedback. >> Would you? >> >> Victor >> >> -----Original Message----- >> From: Evan Cheng [mailto:evan.cheng at apple.com] >> Sent: Thursday, January 05, 2012 09:09 >> To: Umansky, Victor >> Cc: Bruno Cardoso Lopes; llvm-commits at cs.uiuc.edu >> Subject: Re: [llvm-commits] x86 branch sequence optimization in LLVM code gen: please review >> >> Has someone reviewed the updated patch? >> >> Evan >> >> On Dec 21, 2011, at 8:10 AM, Umansky, Victor wrote: >> >>> Replacing patch with a newer one. >>> Changes: aligned naming policy with that of LLVM. >>> >>> Victor >>> >>> -----Original Message----- >>> From: llvm-commits-bounces at cs.uiuc.edu [mailto:llvm-commits-bounces at cs.uiuc.edu] On Behalf Of Umansky, Victor >>> Sent: Wednesday, December 21, 2011 11:01 >>> To: Bruno Cardoso Lopes >>> Cc: llvm-commits at cs.uiuc.edu >>> Subject: Re: [llvm-commits] x86 branch sequence optimization in LLVM code gen: please review >>> >>> Hi Bruno, >>> >>> I've updated the patch with additional peephole-optimization patterns and with additional AVX-specific LIT test. >>> >>> Can you please review, so that I'll proceed to commit the fixes? >>> >>> Best Regards, >>> ?Victor >>> >>> -----Original Message----- >>> From: llvm-commits-bounces at cs.uiuc.edu [mailto:llvm-commits-bounces at cs.uiuc.edu] On Behalf Of Umansky, Victor >>> Sent: Thursday, December 15, 2011 20:09 >>> To: Bruno Cardoso Lopes >>> Cc: llvm-commits at cs.uiuc.edu >>> Subject: Re: [llvm-commits] x86 branch sequence optimization in LLVM code gen: please review >>> >>> Hi Bruno, >>> >>> Please see attached the patch. >>> >>> It incorporates the feedback, and I yet extended it with coverage for more LLVM IR patterns related to usage of ptestz/ptestc LLVM built-ins (tests are also extended). >>> >>> Best Regards, >>> ?Victor >>> >>> >>> -----Original Message----- >>> From: Bruno Cardoso Lopes [mailto:bruno.cardoso at gmail.com] >>> Sent: Friday, December 09, 2011 04:25 >>> To: Umansky, Victor >>> Cc: Chad Rosier; Anton Korobeynikov; bruno.cardoso at gmail.com; llvm-commits at cs.uiuc.edu >>> Subject: Re: [llvm-commits] x86 branch sequence optimization in LLVM code gen: please review >>> >>> On Wed, Dec 7, 2011 at 1:03 PM, Umansky, Victor wrote: >>>> >>>> Hi Chad, Anton, Bruno, >>>> >>>> >>>> >>>> Thank you for the suggestion. >>>> >>>> >>>> >>>> Unfortunately, it won't work in the case of brcond.ll file. >>>> >>>> >>>> >>>> Indeed I can introduce different "check-prefix" values in order to separate checks for "core2" case from those for "penryn" case. >>>> >>>> However, the compilation of all functions in a file will be done unconditionally for both "RUN" cases. And this will inevitably lead to the test failure (in instruction selection) when a function using "ptest" LLVM intrinsic will be processed with "-mcpu=core2" option. >>>> >>>> That's why I was not able to include the test cases for "ptest" intrinsic sequence to a file which will be compiled for a pre-Penryn target. >>>> >>>> >>>> >>>> A solution which does work is to have legacy brcond.ll LIT tests running under "-mcpu=penryn". >>>> >>>> I'm attaching the file. >>>> >>>> Are you OK with such solution? >>> >>> LGTM, please resend the orignal patch with the testcase (both in the same patch file)! Also remove the trailing CRs and generate the diff with "svn diff" under the project root. If you have any question, the docs may help: http://llvm.org/docs/DeveloperPolicy.html#patches >>> >>> -- >>> Bruno Cardoso Lopes >>> http://www.brunocardoso.cc >>> --------------------------------------------------------------------- >>> Intel Israel (74) Limited >>> >>> This e-mail and any attachments may contain confidential material for the sole use of the intended recipient(s). Any review or distribution by others is strictly prohibited. If you are not the intended recipient, please contact the sender and delete all copies. >>> --------------------------------------------------------------------- >>> Intel Israel (74) Limited >>> >>> This e-mail and any attachments may contain confidential material for the sole use of the intended recipient(s). Any review or distribution by others is strictly prohibited. If you are not the intended recipient, please contact the sender and delete all copies. >>> --------------------------------------------------------------------- >>> Intel Israel (74) Limited >>> >>> This e-mail and any attachments may contain confidential material for >>> the sole use of the intended recipient(s). Any review or distribution >>> by others is strictly prohibited. If you are not the intended >>> recipient, please contact the sender and delete all copies. >>> _______________________________________________ >>> llvm-commits mailing list >>> llvm-commits at cs.uiuc.edu >>> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits >> >> --------------------------------------------------------------------- >> Intel Israel (74) Limited >> >> This e-mail and any attachments may contain confidential material for >> the sole use of the intended recipient(s). Any review or distribution >> by others is strictly prohibited. If you are not the intended >> recipient, please contact the sender and delete all copies. >> > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From nadav.rotem at intel.com Thu Jan 5 02:11:51 2012 From: nadav.rotem at intel.com (Rotem, Nadav) Date: Thu, 5 Jan 2012 08:11:51 +0000 Subject: [llvm-commits] x86 branch sequence optimization in LLVM code gen: please review In-Reply-To: References: <021AD592C708E24FA11FD214489EC9BE0123F25260@hasmsx501.ger.corp.intel.com> <021AD592C708E24FA11FD214489EC9BE0123F95DDF@hasmsx501.ger.corp.intel.com> <90F01864-DEB5-4DEA-B8E2-625EF4449126@apple.com> <021AD592C708E24FA11FD214489EC9BE0123FE98C8@hasmsx501.ger.corp.intel.com> <021AD592C708E24FA11FD214489EC9BE01269D1FA3@hasmsx501.ger.corp.intel.com> Message-ID: <7DE70FDACDE4CD4887C4278C12A2E305057C2C@HASMSX104.ger.corp.intel.com> Evan, I think that PTEST should be optimized by teaching "X86TargetLowering::computeMaskedBitsForTargetNode" that PTEST only sets the lowest bit, and not using a peephole. We will also need to teach "SimplifySetCC" to use "SimplifyDemandedBits". Nadav -----Original Message----- From: llvm-commits-bounces at cs.uiuc.edu [mailto:llvm-commits-bounces at cs.uiuc.edu] On Behalf Of Evan Cheng Sent: Thursday, January 05, 2012 09:48 To: Umansky, Victor Cc: llvm-commits at cs.uiuc.edu Subject: Re: [llvm-commits] x86 branch sequence optimization in LLVM code gen: please review Minor nit-pick: +// Helper which returns index of constant operand of a two-operand node. +static inline int GetConstOpIndexFor2OpNode(SDValue Op) { + if (dyn_cast(Op.getOperand(0))) + return 0; + else if (dyn_cast(Op.getOperand(1))) + return 1; + else + return -1; +} Please replace dyn_cast with isa. Please also remove the last "else". That's the preferred llvm style. Thanks, Evan On Jan 4, 2012, at 11:31 PM, Umansky, Victor wrote: > A correction: > > Elena Demikhovsky (elena.demikhovsky at intel.com) reviewed the updated patch (face-to-face, in Intel). > > Victor > > -----Original Message----- > From: Umansky, Victor > Sent: Thursday, January 05, 2012 09:25 > To: 'Evan Cheng' > Cc: Bruno Cardoso Lopes; llvm-commits at cs.uiuc.edu > Subject: RE: [llvm-commits] x86 branch sequence optimization in LLVM > code gen: please review > > No, I haven't received any feedback. > Would you? > > Victor > > -----Original Message----- > From: Evan Cheng [mailto:evan.cheng at apple.com] > Sent: Thursday, January 05, 2012 09:09 > To: Umansky, Victor > Cc: Bruno Cardoso Lopes; llvm-commits at cs.uiuc.edu > Subject: Re: [llvm-commits] x86 branch sequence optimization in LLVM > code gen: please review > > Has someone reviewed the updated patch? > > Evan > > On Dec 21, 2011, at 8:10 AM, Umansky, Victor wrote: > >> Replacing patch with a newer one. >> Changes: aligned naming policy with that of LLVM. >> >> Victor >> >> -----Original Message----- >> From: llvm-commits-bounces at cs.uiuc.edu >> [mailto:llvm-commits-bounces at cs.uiuc.edu] On Behalf Of Umansky, >> Victor >> Sent: Wednesday, December 21, 2011 11:01 >> To: Bruno Cardoso Lopes >> Cc: llvm-commits at cs.uiuc.edu >> Subject: Re: [llvm-commits] x86 branch sequence optimization in LLVM >> code gen: please review >> >> Hi Bruno, >> >> I've updated the patch with additional peephole-optimization patterns and with additional AVX-specific LIT test. >> >> Can you please review, so that I'll proceed to commit the fixes? >> >> Best Regards, >> Victor >> >> -----Original Message----- >> From: llvm-commits-bounces at cs.uiuc.edu >> [mailto:llvm-commits-bounces at cs.uiuc.edu] On Behalf Of Umansky, >> Victor >> Sent: Thursday, December 15, 2011 20:09 >> To: Bruno Cardoso Lopes >> Cc: llvm-commits at cs.uiuc.edu >> Subject: Re: [llvm-commits] x86 branch sequence optimization in LLVM >> code gen: please review >> >> Hi Bruno, >> >> Please see attached the patch. >> >> It incorporates the feedback, and I yet extended it with coverage for more LLVM IR patterns related to usage of ptestz/ptestc LLVM built-ins (tests are also extended). >> >> Best Regards, >> Victor >> >> >> -----Original Message----- >> From: Bruno Cardoso Lopes [mailto:bruno.cardoso at gmail.com] >> Sent: Friday, December 09, 2011 04:25 >> To: Umansky, Victor >> Cc: Chad Rosier; Anton Korobeynikov; bruno.cardoso at gmail.com; >> llvm-commits at cs.uiuc.edu >> Subject: Re: [llvm-commits] x86 branch sequence optimization in LLVM >> code gen: please review >> >> On Wed, Dec 7, 2011 at 1:03 PM, Umansky, Victor wrote: >>> >>> Hi Chad, Anton, Bruno, >>> >>> >>> >>> Thank you for the suggestion. >>> >>> >>> >>> Unfortunately, it won't work in the case of brcond.ll file. >>> >>> >>> >>> Indeed I can introduce different "check-prefix" values in order to separate checks for "core2" case from those for "penryn" case. >>> >>> However, the compilation of all functions in a file will be done unconditionally for both "RUN" cases. And this will inevitably lead to the test failure (in instruction selection) when a function using "ptest" LLVM intrinsic will be processed with "-mcpu=core2" option. >>> >>> That's why I was not able to include the test cases for "ptest" intrinsic sequence to a file which will be compiled for a pre-Penryn target. >>> >>> >>> >>> A solution which does work is to have legacy brcond.ll LIT tests running under "-mcpu=penryn". >>> >>> I'm attaching the file. >>> >>> Are you OK with such solution? >> >> LGTM, please resend the orignal patch with the testcase (both in the >> same patch file)! Also remove the trailing CRs and generate the diff >> with "svn diff" under the project root. If you have any question, the >> docs may help: http://llvm.org/docs/DeveloperPolicy.html#patches >> >> -- >> Bruno Cardoso Lopes >> http://www.brunocardoso.cc >> --------------------------------------------------------------------- >> Intel Israel (74) Limited >> >> This e-mail and any attachments may contain confidential material for the sole use of the intended recipient(s). Any review or distribution by others is strictly prohibited. If you are not the intended recipient, please contact the sender and delete all copies. >> --------------------------------------------------------------------- >> Intel Israel (74) Limited >> >> This e-mail and any attachments may contain confidential material for the sole use of the intended recipient(s). Any review or distribution by others is strictly prohibited. If you are not the intended recipient, please contact the sender and delete all copies. >> --------------------------------------------------------------------- >> Intel Israel (74) Limited >> >> This e-mail and any attachments may contain confidential material for >> the sole use of the intended recipient(s). Any review or distribution >> by others is strictly prohibited. If you are not the intended >> recipient, please contact the sender and delete all copies. >> _______________________________________________ >> llvm-commits mailing list >> llvm-commits at cs.uiuc.edu >> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits > > --------------------------------------------------------------------- > Intel Israel (74) Limited > > This e-mail and any attachments may contain confidential material for > the sole use of the intended recipient(s). Any review or distribution > by others is strictly prohibited. If you are not the intended > recipient, please contact the sender and delete all copies. > _______________________________________________ llvm-commits mailing list llvm-commits at cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits --------------------------------------------------------------------- Intel Israel (74) Limited This e-mail and any attachments may contain confidential material for the sole use of the intended recipient(s). Any review or distribution by others is strictly prohibited. If you are not the intended recipient, please contact the sender and delete all copies. From victor.umansky at intel.com Thu Jan 5 02:18:56 2012 From: victor.umansky at intel.com (Umansky, Victor) Date: Thu, 5 Jan 2012 08:18:56 +0000 Subject: [llvm-commits] x86 branch sequence optimization in LLVM code gen: please review In-Reply-To: <7DE70FDACDE4CD4887C4278C12A2E305057C2C@HASMSX104.ger.corp.intel.com> References: <021AD592C708E24FA11FD214489EC9BE0123F25260@hasmsx501.ger.corp.intel.com> <021AD592C708E24FA11FD214489EC9BE0123F95DDF@hasmsx501.ger.corp.intel.com> <90F01864-DEB5-4DEA-B8E2-625EF4449126@apple.com> <021AD592C708E24FA11FD214489EC9BE0123FE98C8@hasmsx501.ger.corp.intel.com> <021AD592C708E24FA11FD214489EC9BE01269D1FA3@hasmsx501.ger.corp.intel.com> <7DE70FDACDE4CD4887C4278C12A2E305057C2C@HASMSX104.ger.corp.intel.com> Message-ID: Nadav, The redundant sequence (that which is optimized by this patch) is generated not due to PTEST instruction, but due to ptest* intrinsic functions - whose API is defined as int32 by Intel. Victor -----Original Message----- From: Rotem, Nadav Sent: Thursday, January 05, 2012 10:12 To: Evan Cheng; Umansky, Victor Cc: llvm-commits at cs.uiuc.edu Subject: RE: [llvm-commits] x86 branch sequence optimization in LLVM code gen: please review Evan, I think that PTEST should be optimized by teaching "X86TargetLowering::computeMaskedBitsForTargetNode" that PTEST only sets the lowest bit, and not using a peephole. We will also need to teach "SimplifySetCC" to use "SimplifyDemandedBits". Nadav -----Original Message----- From: llvm-commits-bounces at cs.uiuc.edu [mailto:llvm-commits-bounces at cs.uiuc.edu] On Behalf Of Evan Cheng Sent: Thursday, January 05, 2012 09:48 To: Umansky, Victor Cc: llvm-commits at cs.uiuc.edu Subject: Re: [llvm-commits] x86 branch sequence optimization in LLVM code gen: please review Minor nit-pick: +// Helper which returns index of constant operand of a two-operand node. +static inline int GetConstOpIndexFor2OpNode(SDValue Op) { + if (dyn_cast(Op.getOperand(0))) + return 0; + else if (dyn_cast(Op.getOperand(1))) + return 1; + else + return -1; +} Please replace dyn_cast with isa. Please also remove the last "else". That's the preferred llvm style. Thanks, Evan On Jan 4, 2012, at 11:31 PM, Umansky, Victor wrote: > A correction: > > Elena Demikhovsky (elena.demikhovsky at intel.com) reviewed the updated patch (face-to-face, in Intel). > > Victor > > -----Original Message----- > From: Umansky, Victor > Sent: Thursday, January 05, 2012 09:25 > To: 'Evan Cheng' > Cc: Bruno Cardoso Lopes; llvm-commits at cs.uiuc.edu > Subject: RE: [llvm-commits] x86 branch sequence optimization in LLVM > code gen: please review > > No, I haven't received any feedback. > Would you? > > Victor > > -----Original Message----- > From: Evan Cheng [mailto:evan.cheng at apple.com] > Sent: Thursday, January 05, 2012 09:09 > To: Umansky, Victor > Cc: Bruno Cardoso Lopes; llvm-commits at cs.uiuc.edu > Subject: Re: [llvm-commits] x86 branch sequence optimization in LLVM > code gen: please review > > Has someone reviewed the updated patch? > > Evan > > On Dec 21, 2011, at 8:10 AM, Umansky, Victor wrote: > >> Replacing patch with a newer one. >> Changes: aligned naming policy with that of LLVM. >> >> Victor >> >> -----Original Message----- >> From: llvm-commits-bounces at cs.uiuc.edu >> [mailto:llvm-commits-bounces at cs.uiuc.edu] On Behalf Of Umansky, >> Victor >> Sent: Wednesday, December 21, 2011 11:01 >> To: Bruno Cardoso Lopes >> Cc: llvm-commits at cs.uiuc.edu >> Subject: Re: [llvm-commits] x86 branch sequence optimization in LLVM >> code gen: please review >> >> Hi Bruno, >> >> I've updated the patch with additional peephole-optimization patterns and with additional AVX-specific LIT test. >> >> Can you please review, so that I'll proceed to commit the fixes? >> >> Best Regards, >> Victor >> >> -----Original Message----- >> From: llvm-commits-bounces at cs.uiuc.edu >> [mailto:llvm-commits-bounces at cs.uiuc.edu] On Behalf Of Umansky, >> Victor >> Sent: Thursday, December 15, 2011 20:09 >> To: Bruno Cardoso Lopes >> Cc: llvm-commits at cs.uiuc.edu >> Subject: Re: [llvm-commits] x86 branch sequence optimization in LLVM >> code gen: please review >> >> Hi Bruno, >> >> Please see attached the patch. >> >> It incorporates the feedback, and I yet extended it with coverage for more LLVM IR patterns related to usage of ptestz/ptestc LLVM built-ins (tests are also extended). >> >> Best Regards, >> Victor >> >> >> -----Original Message----- >> From: Bruno Cardoso Lopes [mailto:bruno.cardoso at gmail.com] >> Sent: Friday, December 09, 2011 04:25 >> To: Umansky, Victor >> Cc: Chad Rosier; Anton Korobeynikov; bruno.cardoso at gmail.com; >> llvm-commits at cs.uiuc.edu >> Subject: Re: [llvm-commits] x86 branch sequence optimization in LLVM >> code gen: please review >> >> On Wed, Dec 7, 2011 at 1:03 PM, Umansky, Victor wrote: >>> >>> Hi Chad, Anton, Bruno, >>> >>> >>> >>> Thank you for the suggestion. >>> >>> >>> >>> Unfortunately, it won't work in the case of brcond.ll file. >>> >>> >>> >>> Indeed I can introduce different "check-prefix" values in order to separate checks for "core2" case from those for "penryn" case. >>> >>> However, the compilation of all functions in a file will be done unconditionally for both "RUN" cases. And this will inevitably lead to the test failure (in instruction selection) when a function using "ptest" LLVM intrinsic will be processed with "-mcpu=core2" option. >>> >>> That's why I was not able to include the test cases for "ptest" intrinsic sequence to a file which will be compiled for a pre-Penryn target. >>> >>> >>> >>> A solution which does work is to have legacy brcond.ll LIT tests running under "-mcpu=penryn". >>> >>> I'm attaching the file. >>> >>> Are you OK with such solution? >> >> LGTM, please resend the orignal patch with the testcase (both in the >> same patch file)! Also remove the trailing CRs and generate the diff >> with "svn diff" under the project root. If you have any question, the >> docs may help: http://llvm.org/docs/DeveloperPolicy.html#patches >> >> -- >> Bruno Cardoso Lopes >> http://www.brunocardoso.cc >> --------------------------------------------------------------------- >> Intel Israel (74) Limited >> >> This e-mail and any attachments may contain confidential material for the sole use of the intended recipient(s). Any review or distribution by others is strictly prohibited. If you are not the intended recipient, please contact the sender and delete all copies. >> --------------------------------------------------------------------- >> Intel Israel (74) Limited >> >> This e-mail and any attachments may contain confidential material for the sole use of the intended recipient(s). Any review or distribution by others is strictly prohibited. If you are not the intended recipient, please contact the sender and delete all copies. >> --------------------------------------------------------------------- >> Intel Israel (74) Limited >> >> This e-mail and any attachments may contain confidential material for >> the sole use of the intended recipient(s). Any review or distribution >> by others is strictly prohibited. If you are not the intended >> recipient, please contact the sender and delete all copies. >> _______________________________________________ >> llvm-commits mailing list >> llvm-commits at cs.uiuc.edu >> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits > > --------------------------------------------------------------------- > Intel Israel (74) Limited > > This e-mail and any attachments may contain confidential material for > the sole use of the intended recipient(s). Any review or distribution > by others is strictly prohibited. If you are not the intended > recipient, please contact the sender and delete all copies. > _______________________________________________ llvm-commits mailing list llvm-commits at cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits --------------------------------------------------------------------- Intel Israel (74) Limited This e-mail and any attachments may contain confidential material for the sole use of the intended recipient(s). Any review or distribution by others is strictly prohibited. If you are not the intended recipient, please contact the sender and delete all copies. From baldrick at free.fr Thu Jan 5 02:25:15 2012 From: baldrick at free.fr (Duncan Sands) Date: Thu, 05 Jan 2012 09:25:15 +0100 Subject: [llvm-commits] [llvm] r147560 - in /llvm/trunk: include/llvm/Analysis/ValueTracking.h lib/Analysis/ValueTracking.cpp In-Reply-To: <20120104230110.3CC2A2A6C12C@llvm.org> References: <20120104230110.3CC2A2A6C12C@llvm.org> Message-ID: <4F055E6B.5040909@free.fr> Hi Dan, > Generalize isSafeToSpeculativelyExecute to work on arbitrary > Values, rather than just Instructions, since it's interesting > for ConstantExprs too. since constants are not executed, what does this mean? I notice that all constants results in 'false', i.e. not safe to speculatively execute. Why is that? Ciao, Duncan. > > Modified: > llvm/trunk/include/llvm/Analysis/ValueTracking.h > llvm/trunk/lib/Analysis/ValueTracking.cpp > > Modified: llvm/trunk/include/llvm/Analysis/ValueTracking.h > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Analysis/ValueTracking.h?rev=147560&r1=147559&r2=147560&view=diff > ============================================================================== > --- llvm/trunk/include/llvm/Analysis/ValueTracking.h (original) > +++ llvm/trunk/include/llvm/Analysis/ValueTracking.h Wed Jan 4 17:01:09 2012 > @@ -174,7 +174,7 @@ > /// the correct dominance relationships for the operands and users hold. > /// However, this method can return true for instructions that read memory; > /// for such instructions, moving them may change the resulting value. > - bool isSafeToSpeculativelyExecute(const Instruction *Inst, > + bool isSafeToSpeculativelyExecute(const Value *V, > const TargetData *TD = 0); > > } // end namespace llvm > > Modified: llvm/trunk/lib/Analysis/ValueTracking.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/ValueTracking.cpp?rev=147560&r1=147559&r2=147560&view=diff > ============================================================================== > --- llvm/trunk/lib/Analysis/ValueTracking.cpp (original) > +++ llvm/trunk/lib/Analysis/ValueTracking.cpp Wed Jan 4 17:01:09 2012 > @@ -1879,8 +1879,12 @@ > return true; > } > > -bool llvm::isSafeToSpeculativelyExecute(const Instruction *Inst, > +bool llvm::isSafeToSpeculativelyExecute(const Value *V, > const TargetData *TD) { > + const Operator *Inst = dyn_cast(V); > + if (!Inst) > + return false; > + > for (unsigned i = 0, e = Inst->getNumOperands(); i != e; ++i) > if (Constant *C = dyn_cast(Inst->getOperand(i))) > if (C->canTrap()) > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From eli.bendersky at intel.com Thu Jan 5 02:18:41 2012 From: eli.bendersky at intel.com (Eli Bendersky) Date: Thu, 05 Jan 2012 08:18:41 -0000 Subject: [llvm-commits] [llvm] r147600 - /llvm/trunk/docs/Lexicon.html Message-ID: <20120105081841.9C7932A6C12C@llvm.org> Author: eliben Date: Thu Jan 5 02:18:41 2012 New Revision: 147600 URL: http://llvm.org/viewvc/llvm-project?rev=147600&view=rev Log: test commit (verifyiing commit access) Modified: llvm/trunk/docs/Lexicon.html Modified: llvm/trunk/docs/Lexicon.html URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/Lexicon.html?rev=147600&r1=147599&r2=147600&view=diff ============================================================================== --- llvm/trunk/docs/Lexicon.html (original) +++ llvm/trunk/docs/Lexicon.html Thu Jan 5 02:18:41 2012 @@ -275,7 +275,7 @@ - +
    References: <6AE1604EE3EC5F4296C096518C6B77EE1AA4D191F3@mail.accesssoftek.com> Message-ID: On Jan 4, 2012, at 11:14 PM, Evan Cheng wrote: > Eric, can you review the patch? > Yep. :) >> >> >> Please find attached the patch for review. >> >> It's a small re-factored JIT/MCJIT::getPointerToNamedFunction(), so it could be called with the base class. >> >> Hi Danil, This is fine. Do you need someone to commit it for you? -eric -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20120105/da971ddb/attachment.html From victor.umansky at intel.com Thu Jan 5 02:46:19 2012 From: victor.umansky at intel.com (Victor Umansky) Date: Thu, 05 Jan 2012 08:46:19 -0000 Subject: [llvm-commits] [llvm] r147601 - in /llvm/trunk: lib/Target/X86/X86ISelLowering.cpp lib/Target/X86/X86ISelLowering.h test/CodeGen/X86/avx-brcond.ll test/CodeGen/X86/brcond.ll Message-ID: <20120105084619.C37991BE003@llvm.org> Author: vumansky Date: Thu Jan 5 02:46:19 2012 New Revision: 147601 URL: http://llvm.org/viewvc/llvm-project?rev=147601&view=rev Log: Peephole optimization of ptest-conditioned branch in X86 arch. Performs instruction combining of sequences generated by ptestz/ptestc intrinsics to ptest+jcc pair for SSE and AVX. Testing: passed 'make check' including LIT tests for all sequences being handled (both SSE and AVX) Reviewers: Evan Cheng, David Blaikie, Bruno Lopes, Elena Demikhovsky, Chad Rosier, Anton Korobeynikov Added: llvm/trunk/test/CodeGen/X86/avx-brcond.ll (with props) Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp llvm/trunk/lib/Target/X86/X86ISelLowering.h llvm/trunk/test/CodeGen/X86/brcond.ll Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=147601&r1=147600&r2=147601&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original) +++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Thu Jan 5 02:46:19 2012 @@ -14611,6 +14611,146 @@ return OptimizeConditionalInDecrement(N, DAG); } +// Helper which returns index of constant operand of a two-operand node. +static inline int GetConstOpIndexFor2OpNode(SDValue Op) { + if (isa(Op.getOperand(0))) + return 0; + if (isa(Op.getOperand(1))) + return 1; + return -1; +} + +SDValue X86TargetLowering::PerformBrcondCombine(SDNode* N, SelectionDAG &DAG, + DAGCombinerInfo &DCI) const { + // Simplification of the PTEST-and-BRANCH pattern. + // + // The LLVM IR patterns targeted are: + // %res = call i32 @llvm.x86.(...) + // %one = icmp {ne|eq} i32 %res, {0|1} + // br i1 %one, label %bb1, label %bb2 + // and + // %res = call i32 @llvm.x86.(...) + // %one = trunc i32 %res to i1 + // br i1 %one, label %bb1, label %bb2 + // where is one of: + // sse41.ptestz + // sse41.ptestc + // avx.ptestz.256 + // avx.ptestc.256 + // + // The simplification is in folding of the following SDNode sequence: + // X86ISD::PTEST + // {X86ISD::SETCC | X86ISD::SETCC_CARRY} + // [ISD::ZERO_EXTEND][[[ISD::AND,]ISD::TRUNCATE,]ISD::AND] + // X86ISD::CMP + // X86ISD::BRCOND(cond) + // to the code sequence: + // X86ISD::PTEST + // X86ISD::BRCOND(!cond) + + // The optimization is relevant only once the DAG contains x86 ISA (i.e. after + // operation legalization). + if (DCI.isBeforeLegalize() || DCI.isBeforeLegalizeOps() || DCI.isCalledByLegalizer()) + return SDValue(); + + // Below we iterate through DAG upwards, starting from BRCOND node and finishing + // at PTEST node. We stop the iteration once we cannot find match with any of + // the patterns which we are able to simplify. + + // Indices for constant and variable operands in two-operand nodes + int ConstOpIdx; + unsigned int VarOpIdx; + + // Validate that we're starting from the BRCOND node. + assert(N->getOpcode() == X86ISD::BRCOND && "Should start from conditional branch!"); + // Check that the BRCOND condition is ZF. + if (!isa(N->getOperand(2))) + return SDValue(); + uint64_t BranchCond = N->getConstantOperandVal(2); + if (BranchCond != X86::COND_NE && BranchCond != X86::COND_E) + return SDValue(); + + // 1st step upwards: verify CMP use. + SDValue CmpValue = N->getOperand(3); + if (CmpValue.getOpcode() != X86ISD::CMP) + return SDValue(); + // Check that the CMP comparison is with 0. + if ((ConstOpIdx = GetConstOpIndexFor2OpNode(CmpValue)) == -1) + return SDValue(); + VarOpIdx = (ConstOpIdx == 0)? 1:0; + uint64_t CompareWith = CmpValue.getConstantOperandVal((unsigned int)ConstOpIdx); + if (CompareWith != 0 && CompareWith != 1) + return SDValue(); + + // 2rd step upwards: cover alternative paths between pre-BRCOND CMP and PTEST + // return value analysis. + + SDValue SVOp = CmpValue.getOperand(VarOpIdx); + // Verify optional AND use. + if (SVOp.getOpcode() == ISD::AND) { + // Check that the AND is with 0x1. + if ((ConstOpIdx = GetConstOpIndexFor2OpNode(SVOp)) == -1) + return SDValue(); + VarOpIdx = (ConstOpIdx == 0)? 1:0; + if (SVOp.getConstantOperandVal((unsigned int)ConstOpIdx) != 1) + return SDValue(); + // Step upwards: verify optional TRUNCATE use. + SVOp = SVOp.getOperand(VarOpIdx); + if (SVOp.getOpcode() == ISD::TRUNCATE) { + // Step upwards: verify optional AND or ZERO_EXTEND use. + SVOp = SVOp.getOperand(0); + if (SVOp.getOpcode() == ISD::AND) { + // Check that the AND is with 0x1. + if ((ConstOpIdx = GetConstOpIndexFor2OpNode(SVOp)) == -1) + return SDValue(); + VarOpIdx = (ConstOpIdx == 0)? 1:0; + if (SVOp.getConstantOperandVal((unsigned int)ConstOpIdx) != 1) + return SDValue(); + // Step upwards. + SVOp = SVOp.getOperand(VarOpIdx); + } + } + } + // Verify optional ZERO_EXTEND use + if (SVOp.getOpcode() == ISD::ZERO_EXTEND) { + // Step upwards. + SVOp = SVOp.getOperand(0); + } + + // 3rd step upwards: verify SETCC or SETCC_CARRY use. + unsigned SetCcOP = SVOp.getOpcode(); + if (SetCcOP != X86ISD::SETCC && SetCcOP != X86ISD::SETCC_CARRY) + return SDValue(); + // Check that the SETCC/SETCC_CARRY flag is 'COND_E' (for ptestz) or 'COND_B' (for ptestc) + if ((ConstOpIdx = GetConstOpIndexFor2OpNode(SVOp)) == -1) + return SDValue(); + VarOpIdx = (ConstOpIdx == 0)? 1:0; + uint64_t SetCond = SVOp.getConstantOperandVal((unsigned int)ConstOpIdx); + if (SetCond != X86::COND_E && SetCond != X86::COND_B) + return SDValue(); + + // 4th step upwards: verify PTEST use. + SDValue PtestValue = SVOp.getOperand(VarOpIdx); + if (PtestValue.getOpcode() != X86ISD::PTEST) + return SDValue(); + + // The chain to be folded is recognized. We can fold it now. + + // At first - select the branch condition. + SDValue CC = DAG.getConstant(SetCond, MVT::i8); + if ((CompareWith == 1 && BranchCond == X86::COND_NE) || + (CompareWith == 0 && BranchCond == X86::COND_E)) { + // Invert branch condition. + CC = (SetCond == X86::COND_E? DAG.getConstant(X86::COND_NE, MVT::i8): + DAG.getConstant(X86::COND_AE, MVT::i8)); + } + // Then - update the BRCOND node. + // Resno is set to 0 as X86ISD::BRCOND has single return value. + return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0), N->getOperand(1), + CC, PtestValue), 0); + +} + SDValue X86TargetLowering::PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const { SelectionDAG &DAG = DCI.DAG; @@ -14657,6 +14797,7 @@ case X86ISD::VPERMILP: case X86ISD::VPERM2X128: case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG, DCI,Subtarget); + case X86ISD::BRCOND: return PerformBrcondCombine(N, DAG, DCI); } return SDValue(); Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.h?rev=147601&r1=147600&r2=147601&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86ISelLowering.h (original) +++ llvm/trunk/lib/Target/X86/X86ISelLowering.h Thu Jan 5 02:46:19 2012 @@ -836,6 +836,7 @@ SDValue LowerMEMBARRIER(SDValue Op, SelectionDAG &DAG) const; SDValue LowerATOMIC_FENCE(SDValue Op, SelectionDAG &DAG) const; SDValue LowerSIGN_EXTEND_INREG(SDValue Op, SelectionDAG &DAG) const; + SDValue PerformBrcondCombine(SDNode* N, SelectionDAG &DAG, DAGCombinerInfo &DCI) const; // Utility functions to help LowerVECTOR_SHUFFLE SDValue LowerVECTOR_SHUFFLEv8i16(SDValue Op, SelectionDAG &DAG) const; Added: llvm/trunk/test/CodeGen/X86/avx-brcond.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx-brcond.ll?rev=147601&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/X86/avx-brcond.ll (added) +++ llvm/trunk/test/CodeGen/X86/avx-brcond.ll Thu Jan 5 02:46:19 2012 @@ -0,0 +1,244 @@ +; RUN: llc < %s -mtriple=i386-apple-darwin10 -mcpu=corei7-avx -mattr=+avx | FileCheck %s + +declare i32 @llvm.x86.avx.ptestz.256(<4 x i64> %p1, <4 x i64> %p2) nounwind +declare i32 @llvm.x86.avx.ptestc.256(<4 x i64> %p1, <4 x i64> %p2) nounwind + +define <4 x float> @test1(<4 x i64> %a, <4 x float> %b) nounwind { +entry: +; CHECK: test1: +; CHECK: vptest +; CHECK-NEXT: jne +; CHECK: ret + + %res = call i32 @llvm.x86.avx.ptestz.256(<4 x i64> %a, <4 x i64> %a) nounwind + %one = icmp ne i32 %res, 0 + br i1 %one, label %bb1, label %bb2 + +bb1: + %c = fadd <4 x float> %b, < float 1.000000e+002, float 2.000000e+002, float 3.000000e+002, float 4.000000e+002 > + br label %return + +bb2: + %d = fdiv <4 x float> %b, < float 1.000000e+002, float 2.000000e+002, float 3.000000e+002, float 4.000000e+002 > + br label %return + +return: + %e = phi <4 x float> [%c, %bb1], [%d, %bb2] + ret <4 x float> %e +} + +define <4 x float> @test2(<4 x i64> %a, <4 x float> %b) nounwind { +entry: +; CHECK: test2: +; CHECK: vptest +; CHECK-NEXT: je +; CHECK: ret + + %res = call i32 @llvm.x86.avx.ptestz.256(<4 x i64> %a, <4 x i64> %a) nounwind + %one = icmp eq i32 %res, 0 + br i1 %one, label %bb1, label %bb2 + +bb1: + %c = fadd <4 x float> %b, < float 1.000000e+002, float 2.000000e+002, float 3.000000e+002, float 4.000000e+002 > + br label %return + +bb2: + %d = fdiv <4 x float> %b, < float 1.000000e+002, float 2.000000e+002, float 3.000000e+002, float 4.000000e+002 > + br label %return + +return: + %e = phi <4 x float> [%c, %bb1], [%d, %bb2] + ret <4 x float> %e +} + +define <4 x float> @test3(<4 x i64> %a, <4 x float> %b) nounwind { +entry: +; CHECK: test3: +; CHECK: vptest +; CHECK-NEXT: jne +; CHECK: ret + + %res = call i32 @llvm.x86.avx.ptestz.256(<4 x i64> %a, <4 x i64> %a) nounwind + %one = trunc i32 %res to i1 + br i1 %one, label %bb1, label %bb2 + +bb1: + %c = fadd <4 x float> %b, < float 1.000000e+002, float 2.000000e+002, float 3.000000e+002, float 4.000000e+002 > + br label %return + +bb2: + %d = fdiv <4 x float> %b, < float 1.000000e+002, float 2.000000e+002, float 3.000000e+002, float 4.000000e+002 > + br label %return + +return: + %e = phi <4 x float> [%c, %bb1], [%d, %bb2] + ret <4 x float> %e +} + +define <4 x float> @test4(<4 x i64> %a, <4 x float> %b) nounwind { +entry: +; CHECK: test4: +; CHECK: vptest +; CHECK-NEXT: jae +; CHECK: ret + + %res = call i32 @llvm.x86.avx.ptestc.256(<4 x i64> %a, <4 x i64> %a) nounwind + %one = icmp ne i32 %res, 0 + br i1 %one, label %bb1, label %bb2 + +bb1: + %c = fadd <4 x float> %b, < float 1.000000e+002, float 2.000000e+002, float 3.000000e+002, float 4.000000e+002 > + br label %return + +bb2: + %d = fdiv <4 x float> %b, < float 1.000000e+002, float 2.000000e+002, float 3.000000e+002, float 4.000000e+002 > + br label %return + +return: + %e = phi <4 x float> [%c, %bb1], [%d, %bb2] + ret <4 x float> %e +} + +define <4 x float> @test5(<4 x i64> %a, <4 x float> %b) nounwind { +entry: +; CHECK: test5: +; CHECK: vptest +; CHECK-NEXT: jb +; CHECK: ret + + %res = call i32 @llvm.x86.avx.ptestc.256(<4 x i64> %a, <4 x i64> %a) nounwind + %one = icmp eq i32 %res, 0 + br i1 %one, label %bb1, label %bb2 + +bb1: + %c = fadd <4 x float> %b, < float 1.000000e+002, float 2.000000e+002, float 3.000000e+002, float 4.000000e+002 > + br label %return + +bb2: + %d = fdiv <4 x float> %b, < float 1.000000e+002, float 2.000000e+002, float 3.000000e+002, float 4.000000e+002 > + br label %return + +return: + %e = phi <4 x float> [%c, %bb1], [%d, %bb2] + ret <4 x float> %e +} + +define <4 x float> @test6(<4 x i64> %a, <4 x float> %b) nounwind { +entry: +; CHECK: test6: +; CHECK: vptest +; CHECK-NEXT: jae +; CHECK: ret + + %res = call i32 @llvm.x86.avx.ptestc.256(<4 x i64> %a, <4 x i64> %a) nounwind + %one = trunc i32 %res to i1 + br i1 %one, label %bb1, label %bb2 + +bb1: + %c = fadd <4 x float> %b, < float 1.000000e+002, float 2.000000e+002, float 3.000000e+002, float 4.000000e+002 > + br label %return + +bb2: + %d = fdiv <4 x float> %b, < float 1.000000e+002, float 2.000000e+002, float 3.000000e+002, float 4.000000e+002 > + br label %return + +return: + %e = phi <4 x float> [%c, %bb1], [%d, %bb2] + ret <4 x float> %e +} + +define <4 x float> @test7(<4 x i64> %a, <4 x float> %b) nounwind { +entry: +; CHECK: test7: +; CHECK: vptest +; CHECK-NEXT: jne +; CHECK: ret + + %res = call i32 @llvm.x86.avx.ptestz.256(<4 x i64> %a, <4 x i64> %a) nounwind + %one = icmp eq i32 %res, 1 + br i1 %one, label %bb1, label %bb2 + +bb1: + %c = fadd <4 x float> %b, < float 1.000000e+002, float 2.000000e+002, float 3.000000e+002, float 4.000000e+002 > + br label %return + +bb2: + %d = fdiv <4 x float> %b, < float 1.000000e+002, float 2.000000e+002, float 3.000000e+002, float 4.000000e+002 > + br label %return + +return: + %e = phi <4 x float> [%c, %bb1], [%d, %bb2] + ret <4 x float> %e +} + +define <4 x float> @test8(<4 x i64> %a, <4 x float> %b) nounwind { +entry: +; CHECK: test8: +; CHECK: vptest +; CHECK-NEXT: je +; CHECK: ret + + %res = call i32 @llvm.x86.avx.ptestz.256(<4 x i64> %a, <4 x i64> %a) nounwind + %one = icmp ne i32 %res, 1 + br i1 %one, label %bb1, label %bb2 + +bb1: + %c = fadd <4 x float> %b, < float 1.000000e+002, float 2.000000e+002, float 3.000000e+002, float 4.000000e+002 > + br label %return + +bb2: + %d = fdiv <4 x float> %b, < float 1.000000e+002, float 2.000000e+002, float 3.000000e+002, float 4.000000e+002 > + br label %return + +return: + %e = phi <4 x float> [%c, %bb1], [%d, %bb2] + ret <4 x float> %e +} + +define <4 x float> @test9(<4 x i64> %a, <4 x float> %b) nounwind { +entry: +; CHECK: test9: +; CHECK: vptest +; CHECK-NEXT: jae +; CHECK: ret + + %res = call i32 @llvm.x86.avx.ptestc.256(<4 x i64> %a, <4 x i64> %a) nounwind + %one = icmp eq i32 %res, 1 + br i1 %one, label %bb1, label %bb2 + +bb1: + %c = fadd <4 x float> %b, < float 1.000000e+002, float 2.000000e+002, float 3.000000e+002, float 4.000000e+002 > + br label %return + +bb2: + %d = fdiv <4 x float> %b, < float 1.000000e+002, float 2.000000e+002, float 3.000000e+002, float 4.000000e+002 > + br label %return + +return: + %e = phi <4 x float> [%c, %bb1], [%d, %bb2] + ret <4 x float> %e +} + +define <4 x float> @test10(<4 x i64> %a, <4 x float> %b) nounwind { +entry: +; CHECK: test10: +; CHECK: vptest +; CHECK-NEXT: jb +; CHECK: ret + + %res = call i32 @llvm.x86.avx.ptestc.256(<4 x i64> %a, <4 x i64> %a) nounwind + %one = icmp ne i32 %res, 1 + br i1 %one, label %bb1, label %bb2 + +bb1: + %c = fadd <4 x float> %b, < float 1.000000e+002, float 2.000000e+002, float 3.000000e+002, float 4.000000e+002 > + br label %return + +bb2: + %d = fdiv <4 x float> %b, < float 1.000000e+002, float 2.000000e+002, float 3.000000e+002, float 4.000000e+002 > + br label %return + +return: + %e = phi <4 x float> [%c, %bb1], [%d, %bb2] + ret <4 x float> %e +} Propchange: llvm/trunk/test/CodeGen/X86/avx-brcond.ll ------------------------------------------------------------------------------ svn:executable = * Modified: llvm/trunk/test/CodeGen/X86/brcond.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/brcond.ll?rev=147601&r1=147600&r2=147601&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/X86/brcond.ll (original) +++ llvm/trunk/test/CodeGen/X86/brcond.ll Thu Jan 5 02:46:19 2012 @@ -1,4 +1,5 @@ -; RUN: llc < %s -mtriple=i386-apple-darwin10 -mcpu=core2 | FileCheck %s +; RUN: llc < %s -mtriple=i386-apple-darwin10 -mcpu=penryn | FileCheck %s + ; rdar://7475489 define i32 @test1(i32 %a, i32 %b) nounwind ssp { @@ -106,3 +107,246 @@ %.0 = fptrunc double %.0.in to float ; [#uses=1] ret float %.0 } + +declare i32 @llvm.x86.sse41.ptestz(<4 x float> %p1, <4 x float> %p2) nounwind +declare i32 @llvm.x86.sse41.ptestc(<4 x float> %p1, <4 x float> %p2) nounwind + +define <4 x float> @test5(<4 x float> %a, <4 x float> %b) nounwind { +entry: +; CHECK: test5: +; CHECK: ptest +; CHECK-NEXT: jne +; CHECK: ret + + %res = call i32 @llvm.x86.sse41.ptestz(<4 x float> %a, <4 x float> %a) nounwind + %one = icmp ne i32 %res, 0 + br i1 %one, label %bb1, label %bb2 + +bb1: + %c = fadd <4 x float> %b, < float 1.000000e+002, float 2.000000e+002, float 3.000000e+002, float 4.000000e+002 > + br label %return + +bb2: + %d = fdiv <4 x float> %b, < float 1.000000e+002, float 2.000000e+002, float 3.000000e+002, float 4.000000e+002 > + br label %return + +return: + %e = phi <4 x float> [%c, %bb1], [%d, %bb2] + ret <4 x float> %e +} + +define <4 x float> @test6(<4 x float> %a, <4 x float> %b) nounwind { +entry: +; CHECK: test6: +; CHECK: ptest +; CHECK-NEXT: je +; CHECK: ret + + %res = call i32 @llvm.x86.sse41.ptestz(<4 x float> %a, <4 x float> %a) nounwind + %one = icmp eq i32 %res, 0 + br i1 %one, label %bb1, label %bb2 + +bb1: + %c = fadd <4 x float> %b, < float 1.000000e+002, float 2.000000e+002, float 3.000000e+002, float 4.000000e+002 > + br label %return + +bb2: + %d = fdiv <4 x float> %b, < float 1.000000e+002, float 2.000000e+002, float 3.000000e+002, float 4.000000e+002 > + br label %return + +return: + %e = phi <4 x float> [%c, %bb1], [%d, %bb2] + ret <4 x float> %e +} + +define <4 x float> @test7(<4 x float> %a, <4 x float> %b) nounwind { +entry: +; CHECK: test7: +; CHECK: ptest +; CHECK-NEXT: jne +; CHECK: ret + + %res = call i32 @llvm.x86.sse41.ptestz(<4 x float> %a, <4 x float> %a) nounwind + %one = trunc i32 %res to i1 + br i1 %one, label %bb1, label %bb2 + +bb1: + %c = fadd <4 x float> %b, < float 1.000000e+002, float 2.000000e+002, float 3.000000e+002, float 4.000000e+002 > + br label %return + +bb2: + %d = fdiv <4 x float> %b, < float 1.000000e+002, float 2.000000e+002, float 3.000000e+002, float 4.000000e+002 > + br label %return + +return: + %e = phi <4 x float> [%c, %bb1], [%d, %bb2] + ret <4 x float> %e +} + +define <4 x float> @test8(<4 x float> %a, <4 x float> %b) nounwind { +entry: +; CHECK: test8: +; CHECK: ptest +; CHECK-NEXT: jae +; CHECK: ret + + %res = call i32 @llvm.x86.sse41.ptestc(<4 x float> %a, <4 x float> %a) nounwind + %one = icmp ne i32 %res, 0 + br i1 %one, label %bb1, label %bb2 + +bb1: + %c = fadd <4 x float> %b, < float 1.000000e+002, float 2.000000e+002, float 3.000000e+002, float 4.000000e+002 > + br label %return + +bb2: + %d = fdiv <4 x float> %b, < float 1.000000e+002, float 2.000000e+002, float 3.000000e+002, float 4.000000e+002 > + br label %return + +return: + %e = phi <4 x float> [%c, %bb1], [%d, %bb2] + ret <4 x float> %e +} + +define <4 x float> @test9(<4 x float> %a, <4 x float> %b) nounwind { +entry: +; CHECK: test9: +; CHECK: ptest +; CHECK-NEXT: jb +; CHECK: ret + + %res = call i32 @llvm.x86.sse41.ptestc(<4 x float> %a, <4 x float> %a) nounwind + %one = icmp eq i32 %res, 0 + br i1 %one, label %bb1, label %bb2 + +bb1: + %c = fadd <4 x float> %b, < float 1.000000e+002, float 2.000000e+002, float 3.000000e+002, float 4.000000e+002 > + br label %return + +bb2: + %d = fdiv <4 x float> %b, < float 1.000000e+002, float 2.000000e+002, float 3.000000e+002, float 4.000000e+002 > + br label %return + +return: + %e = phi <4 x float> [%c, %bb1], [%d, %bb2] + ret <4 x float> %e +} + +define <4 x float> @test10(<4 x float> %a, <4 x float> %b) nounwind { +entry: +; CHECK: test10: +; CHECK: ptest +; CHECK-NEXT: jae +; CHECK: ret + + %res = call i32 @llvm.x86.sse41.ptestc(<4 x float> %a, <4 x float> %a) nounwind + %one = trunc i32 %res to i1 + br i1 %one, label %bb1, label %bb2 + +bb1: + %c = fadd <4 x float> %b, < float 1.000000e+002, float 2.000000e+002, float 3.000000e+002, float 4.000000e+002 > + br label %return + +bb2: + %d = fdiv <4 x float> %b, < float 1.000000e+002, float 2.000000e+002, float 3.000000e+002, float 4.000000e+002 > + br label %return + +return: + %e = phi <4 x float> [%c, %bb1], [%d, %bb2] + ret <4 x float> %e +} + +define <4 x float> @test11(<4 x float> %a, <4 x float> %b) nounwind { +entry: +; CHECK: test11: +; CHECK: ptest +; CHECK-NEXT: jne +; CHECK: ret + + %res = call i32 @llvm.x86.sse41.ptestz(<4 x float> %a, <4 x float> %a) nounwind + %one = icmp eq i32 %res, 1 + br i1 %one, label %bb1, label %bb2 + +bb1: + %c = fadd <4 x float> %b, < float 1.000000e+002, float 2.000000e+002, float 3.000000e+002, float 4.000000e+002 > + br label %return + +bb2: + %d = fdiv <4 x float> %b, < float 1.000000e+002, float 2.000000e+002, float 3.000000e+002, float 4.000000e+002 > + br label %return + +return: + %e = phi <4 x float> [%c, %bb1], [%d, %bb2] + ret <4 x float> %e +} + +define <4 x float> @test12(<4 x float> %a, <4 x float> %b) nounwind { +entry: +; CHECK: test12: +; CHECK: ptest +; CHECK-NEXT: je +; CHECK: ret + + %res = call i32 @llvm.x86.sse41.ptestz(<4 x float> %a, <4 x float> %a) nounwind + %one = icmp ne i32 %res, 1 + br i1 %one, label %bb1, label %bb2 + +bb1: + %c = fadd <4 x float> %b, < float 1.000000e+002, float 2.000000e+002, float 3.000000e+002, float 4.000000e+002 > + br label %return + +bb2: + %d = fdiv <4 x float> %b, < float 1.000000e+002, float 2.000000e+002, float 3.000000e+002, float 4.000000e+002 > + br label %return + +return: + %e = phi <4 x float> [%c, %bb1], [%d, %bb2] + ret <4 x float> %e +} + +define <4 x float> @test13(<4 x float> %a, <4 x float> %b) nounwind { +entry: +; CHECK: test13: +; CHECK: ptest +; CHECK-NEXT: jae +; CHECK: ret + + %res = call i32 @llvm.x86.sse41.ptestc(<4 x float> %a, <4 x float> %a) nounwind + %one = icmp eq i32 %res, 1 + br i1 %one, label %bb1, label %bb2 + +bb1: + %c = fadd <4 x float> %b, < float 1.000000e+002, float 2.000000e+002, float 3.000000e+002, float 4.000000e+002 > + br label %return + +bb2: + %d = fdiv <4 x float> %b, < float 1.000000e+002, float 2.000000e+002, float 3.000000e+002, float 4.000000e+002 > + br label %return + +return: + %e = phi <4 x float> [%c, %bb1], [%d, %bb2] + ret <4 x float> %e +} + +define <4 x float> @test14(<4 x float> %a, <4 x float> %b) nounwind { +entry: +; CHECK: test14: +; CHECK: ptest +; CHECK-NEXT: jb +; CHECK: ret + + %res = call i32 @llvm.x86.sse41.ptestc(<4 x float> %a, <4 x float> %a) nounwind + %one = icmp ne i32 %res, 1 + br i1 %one, label %bb1, label %bb2 + +bb1: + %c = fadd <4 x float> %b, < float 1.000000e+002, float 2.000000e+002, float 3.000000e+002, float 4.000000e+002 > + br label %return + +bb2: + %d = fdiv <4 x float> %b, < float 1.000000e+002, float 2.000000e+002, float 3.000000e+002, float 4.000000e+002 > + br label %return + +return: + %e = phi <4 x float> [%c, %bb1], [%d, %bb2] + ret <4 x float> %e +} From tobias at grosser.es Thu Jan 5 02:53:04 2012 From: tobias at grosser.es (Tobias Grosser) Date: Thu, 05 Jan 2012 09:53:04 +0100 Subject: [llvm-commits] [polly] r147543 - in /polly/trunk/www: get_started.html polly.sh In-Reply-To: <20120104201119.1687A2A6C12C@llvm.org> References: <20120104201119.1687A2A6C12C@llvm.org> Message-ID: <4F0564F0.2050904@grosser.es> On 01/04/2012 09:11 PM, Sebastian Pop wrote: > Author: spop > Date: Wed Jan 4 14:11:18 2012 > New Revision: 147543 > > URL: http://llvm.org/viewvc/llvm-project?rev=147543&view=rev > Log: > add polly.sh script Thanks Sebastian Tobi From craig.topper at gmail.com Thu Jan 5 02:56:10 2012 From: craig.topper at gmail.com (Craig Topper) Date: Thu, 05 Jan 2012 08:56:10 -0000 Subject: [llvm-commits] [llvm] r147602 - /llvm/trunk/lib/Target/X86/X86InstrFMA.td Message-ID: <20120105085610.C36F62A6C12C@llvm.org> Author: ctopper Date: Thu Jan 5 02:56:10 2012 New Revision: 147602 URL: http://llvm.org/viewvc/llvm-project?rev=147602&view=rev Log: Mark scalar FMA4 instructions as ignoring the VEX.L bit. Modified: llvm/trunk/lib/Target/X86/X86InstrFMA.td Modified: llvm/trunk/lib/Target/X86/X86InstrFMA.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrFMA.td?rev=147602&r1=147601&r2=147602&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86InstrFMA.td (original) +++ llvm/trunk/lib/Target/X86/X86InstrFMA.td Thu Jan 5 02:56:10 2012 @@ -87,11 +87,11 @@ defm SDr231 : fma3s_rm, VEX_W; } -defm VFMADD : fma3s_forms<0x99, 0xA9, 0xB9, "vfmadd">; -defm VFMSUB : fma3s_forms<0x9B, 0xAB, 0xBB, "vfmsub">; +defm VFMADD : fma3s_forms<0x99, 0xA9, 0xB9, "vfmadd">, VEX_LIG; +defm VFMSUB : fma3s_forms<0x9B, 0xAB, 0xBB, "vfmsub">, VEX_LIG; -defm VFNMADD : fma3s_forms<0x9D, 0xAD, 0xBD, "vfnmadd">; -defm VFNMSUB : fma3s_forms<0x9F, 0xAF, 0xBF, "vfnmsub">; +defm VFNMADD : fma3s_forms<0x9D, 0xAD, 0xBD, "vfnmadd">, VEX_LIG; +defm VFNMSUB : fma3s_forms<0x9F, 0xAF, 0xBF, "vfnmsub">, VEX_LIG; //===----------------------------------------------------------------------===// // FMA4 - AMD 4 operand Fused Multiply-Add instructions From chandlerc at google.com Thu Jan 5 03:15:35 2012 From: chandlerc at google.com (Chandler Carruth) Date: Thu, 5 Jan 2012 01:15:35 -0800 Subject: [llvm-commits] x86 branch sequence optimization in LLVM code gen: please review In-Reply-To: References: <021AD592C708E24FA11FD214489EC9BE0123F25260@hasmsx501.ger.corp.intel.com> <021AD592C708E24FA11FD214489EC9BE0123F95DDF@hasmsx501.ger.corp.intel.com> <90F01864-DEB5-4DEA-B8E2-625EF4449126@apple.com> <021AD592C708E24FA11FD214489EC9BE0123FE98C8@hasmsx501.ger.corp.intel.com> <021AD592C708E24FA11FD214489EC9BE01269D1FA3@hasmsx501.ger.corp.intel.com> <7DE70FDACDE4CD4887C4278C12A2E305057C2C@HASMSX104.ger.corp.intel.com> Message-ID: On Thu, Jan 5, 2012 at 12:18 AM, Umansky, Victor wrote: > Nadav, > > The redundant sequence (that which is optimized by this patch) is > generated not due to PTEST instruction, but due to ptest* intrinsic > functions - whose API is defined as int32 by Intel. I see that you've already committed this, but it still isn't clear to me why we can't do something closer to Nadav's suggestion won't work. Specifically, why do the LLVM intrinsics have to return an i32? No one is ever able to directly call LLVM intrinsics. We can give them any API that is useful. If this instruction really sets a flag rather than returning a value, returning an 'i1' type in the LLVM IR would be much more accurate. The frontend can then manage the lowering from whatever C API is used in the library to the LLVM IR, and the IR optimizers can clean up any redundancies that are there. The reason this is important is that there are many many things which can prevent the pattern you've created a peephole optimization for from actually occurring. If we change something in the rest of the LLVM stack that slightly alters the pattern coming out of the middle-end optimizers, this optimization vanishes. By making the semantics of the instruction more closely modeled by IR (and the resulting DAG), the optimization pipeline will be much cleaner. One example that jumps to mind is what if the icmp in your example ends up feeding into a select rather than a branch. Does your peephole still fire? Do we end up with ptest + cmov? -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20120105/32a18308/attachment.html From victor.umansky at intel.com Thu Jan 5 03:24:56 2012 From: victor.umansky at intel.com (Umansky, Victor) Date: Thu, 5 Jan 2012 09:24:56 +0000 Subject: [llvm-commits] x86 branch sequence optimization in LLVM code gen: please review In-Reply-To: References: <021AD592C708E24FA11FD214489EC9BE0123F25260@hasmsx501.ger.corp.intel.com> <021AD592C708E24FA11FD214489EC9BE0123F95DDF@hasmsx501.ger.corp.intel.com> <90F01864-DEB5-4DEA-B8E2-625EF4449126@apple.com> <021AD592C708E24FA11FD214489EC9BE0123FE98C8@hasmsx501.ger.corp.intel.com> <021AD592C708E24FA11FD214489EC9BE01269D1FA3@hasmsx501.ger.corp.intel.com> <7DE70FDACDE4CD4887C4278C12A2E305057C2C@HASMSX104.ger.corp.intel.com> Message-ID: Answering Chandler?s questions: 1. An 86 intrinsic prototype is defined by Intel together with the corresponding instruction, published in IA32 arch spec and in *intrin.h files. Consequently this prototype is accepted by all compiler providers ? for compatibility reasons. The ptest* intrinsics return i32 type. 2. Of course, ptest-branch combining won?t catch the cases of ptest-select or ptest-cmove. However adding these cases would require very few changes in the code. Victor From: Chandler Carruth [mailto:chandlerc at google.com] Sent: Thursday, January 05, 2012 11:16 To: Umansky, Victor Cc: Rotem, Nadav; Evan Cheng; llvm-commits at cs.uiuc.edu Subject: Re: [llvm-commits] x86 branch sequence optimization in LLVM code gen: please review On Thu, Jan 5, 2012 at 12:18 AM, Umansky, Victor > wrote: Nadav, The redundant sequence (that which is optimized by this patch) is generated not due to PTEST instruction, but due to ptest* intrinsic functions - whose API is defined as int32 by Intel. I see that you've already committed this, but it still isn't clear to me why we can't do something closer to Nadav's suggestion won't work. Specifically, why do the LLVM intrinsics have to return an i32? No one is ever able to directly call LLVM intrinsics. We can give them any API that is useful. If this instruction really sets a flag rather than returning a value, returning an 'i1' type in the LLVM IR would be much more accurate. The frontend can then manage the lowering from whatever C API is used in the library to the LLVM IR, and the IR optimizers can clean up any redundancies that are there. The reason this is important is that there are many many things which can prevent the pattern you've created a peephole optimization for from actually occurring. If we change something in the rest of the LLVM stack that slightly alters the pattern coming out of the middle-end optimizers, this optimization vanishes. By making the semantics of the instruction more closely modeled by IR (and the resulting DAG), the optimization pipeline will be much cleaner. One example that jumps to mind is what if the icmp in your example ends up feeding into a select rather than a branch. Does your peephole still fire? Do we end up with ptest + cmov? --------------------------------------------------------------------- Intel Israel (74) Limited This e-mail and any attachments may contain confidential material for the sole use of the intended recipient(s). Any review or distribution by others is strictly prohibited. If you are not the intended recipient, please contact the sender and delete all copies. -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20120105/c22fc5bb/attachment-0001.html From chandlerc at google.com Thu Jan 5 03:44:50 2012 From: chandlerc at google.com (Chandler Carruth) Date: Thu, 5 Jan 2012 01:44:50 -0800 Subject: [llvm-commits] x86 branch sequence optimization in LLVM code gen: please review In-Reply-To: References: <021AD592C708E24FA11FD214489EC9BE0123F25260@hasmsx501.ger.corp.intel.com> <021AD592C708E24FA11FD214489EC9BE0123F95DDF@hasmsx501.ger.corp.intel.com> <90F01864-DEB5-4DEA-B8E2-625EF4449126@apple.com> <021AD592C708E24FA11FD214489EC9BE0123FE98C8@hasmsx501.ger.corp.intel.com> <021AD592C708E24FA11FD214489EC9BE01269D1FA3@hasmsx501.ger.corp.intel.com> <7DE70FDACDE4CD4887C4278C12A2E305057C2C@HASMSX104.ger.corp.intel.com> Message-ID: On Thu, Jan 5, 2012 at 1:24 AM, Umansky, Victor wrote: > Answering Chandler?s questions:**** > > **1. **An 86 intrinsic prototype is defined by Intel together with > the corresponding instruction, published in IA32 arch spec and in *intrin.h > files. Consequently this prototype is accepted by all compiler providers ? > for compatibility reasons. The ptest* intrinsics return i32 type. > I don't think we're talking about the same thing. There are two things called intrinsics here, and they're getting improperly conflated. 1) Intel (and other vendors) provide C intrinsics for accessing particular functionality in *intrin.h header files. This include _mm_testz_si128, and all kinds of others. They are *C* functions provided and implemented as part of the *C* compiler though. That's important. 2) LLVM defines LLVM intrinsic functions as part of the LLVM IR: http://llvm.org/docs/LangRef.html#intrinsics and include/llvm/IntrinsicsX86.td are relevant for these. These are *not* C functions, and they cannot be called from C code directly. They are not a publicly visible interface. Frontends such as Clang implement #1 by (roughly) emitting code which uses the intrinsics defined in #2. Currently LLVM (#2) has intrinsics for PTEST which return an 'i32' even though the semantics of that instruction are best described by returning an 'i1' which can then directly be used in a 'br' instruction or a 'select' instruction. I'm suggesting changing *LLVM*'s intrinsic (#2) to return an 'i1'. The frontend can then emit any adaptive logic necessary when lowering the interface of #1 (which remains the same, returning 'int') to code using LLVM's newly adapted intrinsics. Even if this requires "extra" or "redundant" IR, this should be optimized away *at the IR* level to preserve the generality of those optimizations, and because frankly optimizations on the IR are much easier to implement and maintain. -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20120105/a58cf579/attachment.html From victor.umansky at intel.com Thu Jan 5 03:53:03 2012 From: victor.umansky at intel.com (Umansky, Victor) Date: Thu, 5 Jan 2012 09:53:03 +0000 Subject: [llvm-commits] x86 branch sequence optimization in LLVM code gen: please review In-Reply-To: References: <021AD592C708E24FA11FD214489EC9BE0123F25260@hasmsx501.ger.corp.intel.com> <021AD592C708E24FA11FD214489EC9BE0123F95DDF@hasmsx501.ger.corp.intel.com> <90F01864-DEB5-4DEA-B8E2-625EF4449126@apple.com> <021AD592C708E24FA11FD214489EC9BE0123FE98C8@hasmsx501.ger.corp.intel.com> <021AD592C708E24FA11FD214489EC9BE01269D1FA3@hasmsx501.ger.corp.intel.com> <7DE70FDACDE4CD4887C4278C12A2E305057C2C@HASMSX104.ger.corp.intel.com> Message-ID: Well, if it would be possible to change LLVM intrinsic prototype ? then you?re right, no instruction combining were required. However until this will be done in LLVM spec ? the optimization is in place. From: Chandler Carruth [mailto:chandlerc at google.com] Sent: Thursday, January 05, 2012 11:45 To: Umansky, Victor Cc: Rotem, Nadav; Evan Cheng; llvm-commits at cs.uiuc.edu Subject: Re: [llvm-commits] x86 branch sequence optimization in LLVM code gen: please review On Thu, Jan 5, 2012 at 1:24 AM, Umansky, Victor > wrote: Answering Chandler?s questions: 1. An 86 intrinsic prototype is defined by Intel together with the corresponding instruction, published in IA32 arch spec and in *intrin.h files. Consequently this prototype is accepted by all compiler providers ? for compatibility reasons. The ptest* intrinsics return i32 type. I don't think we're talking about the same thing. There are two things called intrinsics here, and they're getting improperly conflated. 1) Intel (and other vendors) provide C intrinsics for accessing particular functionality in *intrin.h header files. This include _mm_testz_si128, and all kinds of others. They are *C* functions provided and implemented as part of the *C* compiler though. That's important. 2) LLVM defines LLVM intrinsic functions as part of the LLVM IR: http://llvm.org/docs/LangRef.html#intrinsics and include/llvm/IntrinsicsX86.td are relevant for these. These are *not* C functions, and they cannot be called from C code directly. They are not a publicly visible interface. Frontends such as Clang implement #1 by (roughly) emitting code which uses the intrinsics defined in #2. Currently LLVM (#2) has intrinsics for PTEST which return an 'i32' even though the semantics of that instruction are best described by returning an 'i1' which can then directly be used in a 'br' instruction or a 'select' instruction. I'm suggesting changing *LLVM*'s intrinsic (#2) to return an 'i1'. The frontend can then emit any adaptive logic necessary when lowering the interface of #1 (which remains the same, returning 'int') to code using LLVM's newly adapted intrinsics. Even if this requires "extra" or "redundant" IR, this should be optimized away *at the IR* level to preserve the generality of those optimizations, and because frankly optimizations on the IR are much easier to implement and maintain. --------------------------------------------------------------------- Intel Israel (74) Limited This e-mail and any attachments may contain confidential material for the sole use of the intended recipient(s). Any review or distribution by others is strictly prohibited. If you are not the intended recipient, please contact the sender and delete all copies. -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20120105/d492630d/attachment.html From chandlerc at google.com Thu Jan 5 04:01:27 2012 From: chandlerc at google.com (Chandler Carruth) Date: Thu, 5 Jan 2012 02:01:27 -0800 Subject: [llvm-commits] x86 branch sequence optimization in LLVM code gen: please review In-Reply-To: References: <021AD592C708E24FA11FD214489EC9BE0123F25260@hasmsx501.ger.corp.intel.com> <021AD592C708E24FA11FD214489EC9BE0123F95DDF@hasmsx501.ger.corp.intel.com> <90F01864-DEB5-4DEA-B8E2-625EF4449126@apple.com> <021AD592C708E24FA11FD214489EC9BE0123FE98C8@hasmsx501.ger.corp.intel.com> <021AD592C708E24FA11FD214489EC9BE01269D1FA3@hasmsx501.ger.corp.intel.com> <7DE70FDACDE4CD4887C4278C12A2E305057C2C@HASMSX104.ger.corp.intel.com> Message-ID: On Thu, Jan 5, 2012 at 1:53 AM, Umansky, Victor wrote: > Well, if it would be possible to change LLVM intrinsic prototype ? then > you?re right, no instruction combining were required.**** > > However until this will be done in LLVM spec ? the optimization is in > place. > There is no spec, it is a change to LLVM's intrinsics, you can post a patch to do this to this mailing list. =] You need to change the intrinsic definition, update any code that reasons about that intrinsic, add auto-upgrade logic to upgrade old IR inputs from the old intrinsic to the new intrinsic, and teach the frontends to emit the new one. It's a fair amount of code, but none of it hard. Please don't leave bad code checked into the codegen layer. We need to fix this the correct way if/when we find the correct way to fix it. Thus far, updating the LLVM intrinsics is looking very promising. -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20120105/f8bcb955/attachment.html From chandlerc at gmail.com Thu Jan 5 05:05:47 2012 From: chandlerc at gmail.com (Chandler Carruth) Date: Thu, 05 Jan 2012 11:05:47 -0000 Subject: [llvm-commits] [llvm] r147603 - /llvm/trunk/test/CodeGen/X86/shift-folding.ll Message-ID: <20120105110547.BEFD72A6C12C@llvm.org> Author: chandlerc Date: Thu Jan 5 05:05:47 2012 New Revision: 147603 URL: http://llvm.org/viewvc/llvm-project?rev=147603&view=rev Log: Cleanup and FileCheck-ize a test. Modified: llvm/trunk/test/CodeGen/X86/shift-folding.ll Modified: llvm/trunk/test/CodeGen/X86/shift-folding.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/shift-folding.ll?rev=147603&r1=147602&r2=147603&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/X86/shift-folding.ll (original) +++ llvm/trunk/test/CodeGen/X86/shift-folding.ll Thu Jan 5 05:05:47 2012 @@ -1,27 +1,49 @@ -; RUN: llc < %s -march=x86 | \ -; RUN: grep {s\[ah\]\[rl\]l} | count 1 +; RUN: llc < %s -march=x86 | FileCheck %s -define i32* @test1(i32* %P, i32 %X) nounwind { - %Y = lshr i32 %X, 2 ; [#uses=1] - %gep.upgrd.1 = zext i32 %Y to i64 ; [#uses=1] - %P2 = getelementptr i32* %P, i64 %gep.upgrd.1 ; [#uses=1] - ret i32* %P2 +define i32* @test1(i32* %P, i32 %X) { +; CHECK: test1: +; CHECK-NOT: shrl +; CHECK-NOT: shll +; CHECK: ret + +entry: + %Y = lshr i32 %X, 2 + %gep.upgrd.1 = zext i32 %Y to i64 + %P2 = getelementptr i32* %P, i64 %gep.upgrd.1 + ret i32* %P2 } -define i32* @test2(i32* %P, i32 %X) nounwind { - %Y = shl i32 %X, 2 ; [#uses=1] - %gep.upgrd.2 = zext i32 %Y to i64 ; [#uses=1] - %P2 = getelementptr i32* %P, i64 %gep.upgrd.2 ; [#uses=1] - ret i32* %P2 +define i32* @test2(i32* %P, i32 %X) { +; CHECK: test2: +; CHECK: shll $4 +; CHECK-NOT: shll +; CHECK: ret + +entry: + %Y = shl i32 %X, 2 + %gep.upgrd.2 = zext i32 %Y to i64 + %P2 = getelementptr i32* %P, i64 %gep.upgrd.2 + ret i32* %P2 } -define i32* @test3(i32* %P, i32 %X) nounwind { - %Y = ashr i32 %X, 2 ; [#uses=1] - %P2 = getelementptr i32* %P, i32 %Y ; [#uses=1] - ret i32* %P2 +define i32* @test3(i32* %P, i32 %X) { +; CHECK: test3: +; CHECK-NOT: shrl +; CHECK-NOT: shll +; CHECK: ret + +entry: + %Y = ashr i32 %X, 2 + %P2 = getelementptr i32* %P, i32 %Y + ret i32* %P2 } -define fastcc i32 @test4(i32* %d) nounwind { +define fastcc i32 @test4(i32* %d) { +; CHECK: test4: +; CHECK-NOT: shrl +; CHECK: ret + +entry: %tmp4 = load i32* %d %tmp512 = lshr i32 %tmp4, 24 ret i32 %tmp512 From chandlerc at gmail.com Thu Jan 5 05:05:55 2012 From: chandlerc at gmail.com (Chandler Carruth) Date: Thu, 05 Jan 2012 11:05:55 -0000 Subject: [llvm-commits] [llvm] r147604 - in /llvm/trunk: lib/CodeGen/SelectionDAG/DAGCombiner.cpp test/CodeGen/X86/shift-folding.ll Message-ID: <20120105110555.72F5F2A6C12C@llvm.org> Author: chandlerc Date: Thu Jan 5 05:05:55 2012 New Revision: 147604 URL: http://llvm.org/viewvc/llvm-project?rev=147604&view=rev Log: Prevent a DAGCombine from firing where there are two uses of a combined-away node and the result of the combine isn't substantially smaller than the input, it's just canonicalized. This is the first part of a significant (7%) performance gain for Snappy's hot decompression loop. Modified: llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp llvm/trunk/test/CodeGen/X86/shift-folding.ll Modified: llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp?rev=147604&r1=147603&r2=147604&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Thu Jan 5 05:05:55 2012 @@ -3331,7 +3331,9 @@ // fold (shl (srl x, c1), c2) -> (and (shl x, (sub c2, c1), MASK) or // (and (srl x, (sub c1, c2), MASK) - if (N1C && N0.getOpcode() == ISD::SRL && + // Only fold this if the inner shift has no other uses -- if it does, folding + // this will increase the total number of instructions. + if (N1C && N0.getOpcode() == ISD::SRL && N0.hasOneUse() && N0.getOperand(1).getOpcode() == ISD::Constant) { uint64_t c1 = cast(N0.getOperand(1))->getZExtValue(); if (c1 < VT.getSizeInBits()) { Modified: llvm/trunk/test/CodeGen/X86/shift-folding.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/shift-folding.ll?rev=147604&r1=147603&r2=147604&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/X86/shift-folding.ll (original) +++ llvm/trunk/test/CodeGen/X86/shift-folding.ll Thu Jan 5 05:05:55 2012 @@ -48,3 +48,23 @@ %tmp512 = lshr i32 %tmp4, 24 ret i32 %tmp512 } + +define i64 @test5(i16 %i, i32* %arr) { +; Ensure that we don't fold away shifts which have multiple uses, as they are +; just re-introduced for the second use. +; CHECK: test5: +; CHECK-NOT: shrl +; CHECK: shrl $11 +; CHECK-NOT: shrl +; CHECK: ret + +entry: + %i.zext = zext i16 %i to i32 + %index = lshr i32 %i.zext, 11 + %index.zext = zext i32 %index to i64 + %val.ptr = getelementptr inbounds i32* %arr, i64 %index.zext + %val = load i32* %val.ptr + %val.zext = zext i32 %val to i64 + %sum = add i64 %val.zext, %index.zext + ret i64 %sum +} From chandlerc at gmail.com Thu Jan 5 05:25:47 2012 From: chandlerc at gmail.com (Chandler Carruth) Date: Thu, 05 Jan 2012 11:25:47 -0000 Subject: [llvm-commits] [llvm] r147605 - /llvm/trunk/lib/CodeGen/ScheduleDAGInstrs.cpp Message-ID: <20120105112547.AACFD2A6C12C@llvm.org> Author: chandlerc Date: Thu Jan 5 05:25:47 2012 New Revision: 147605 URL: http://llvm.org/viewvc/llvm-project?rev=147605&view=rev Log: Remove an unused variable. Modified: llvm/trunk/lib/CodeGen/ScheduleDAGInstrs.cpp Modified: llvm/trunk/lib/CodeGen/ScheduleDAGInstrs.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/ScheduleDAGInstrs.cpp?rev=147605&r1=147604&r2=147605&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/ScheduleDAGInstrs.cpp (original) +++ llvm/trunk/lib/CodeGen/ScheduleDAGInstrs.cpp Thu Jan 5 05:25:47 2012 @@ -267,7 +267,6 @@ // TODO: Using a latency of 1 here for output dependencies assumes // there's no cost for reusing registers. SDep::Kind Kind = MO.isUse() ? SDep::Anti : SDep::Output; - unsigned AOLatency = (Kind == SDep::Anti) ? 0 : 1; for (const unsigned *Alias = TRI->getOverlaps(Reg); *Alias; ++Alias) { std::vector &DefList = Defs[*Alias]; for (unsigned i = 0, e = DefList.size(); i != e; ++i) { From stpworld at narod.ru Thu Jan 5 05:40:51 2012 From: stpworld at narod.ru (Stepan Dyatkovskiy) Date: Thu, 05 Jan 2012 15:40:51 +0400 Subject: [llvm-commits] [LLVM, SwitchInst, case ranges] Auxiliary patch #1 In-Reply-To: <5633CF27-DD22-4595-A197-DFFCC56B6342@apple.com> References: <4EAA9B5D.802@narod.ru> <4EAA9DE8.80000@free.fr> <485181319805488@web67.yandex.ru> <4EAB079D.6000606@free.fr> <4EB18F12.6060409@narod.ru> <4EB7C319.1000709@narod.ru> <4EDE7D75.704@narod.ru> <4EDFD0F4.1040204@narod.ru> <4EE25B61.9070006@narod.ru> <4EE5C06C.3050705@narod.ru> <333531323974498@web57.yandex.ru> <4EEB9C52.1050301@narod.ru> <4EF37B6B.6000205@narod.ru> <4EFA0748.9080702@narod.ru> <4EFCAA6A.20203@narod.ru> <610731325498362@web6.yandex.ru> <200871325616668@web103.yandex.ru> <5633CF27-DD22-4595-A197-DFFCC56B6342@apple.com> Message-ID: <4F058C43.7020908@narod.ru> Of course. Two patches. The first one extends APInt. The second one extends SmallSet. -Stepan. Evan Cheng wrote: > Where is the patch? Can you attach it again? > > Thanks, > > Evan > > On Jan 3, 2012, at 10:51 AM, Stepan Dyatkovskiy wrote: > >> Ping. >> -- >> Truly yours, >> Stepan Dyatkovskiy >> >> 02.01.2012, 13:59, "Stepan Dyatkovskiy": >>> Ping again and again :-) >>> -Stepan. >>> >>> 29.12.2011, 21:59, "Stepan Dyatkovskiy": >>> >>>> Ping. >>>> -Stepan. >>>> >>>> Stepan Dyatkovskiy wrote: >>>>> ping. >>>>> Stepan Dyatkovskiy wrote: >>>>>> Ping. >>>>>> >>>>>> Stepan Dyatkovskiy wrote: >>>>>>> Ping. >>>>>>> >>>>>>> -Stepan. >> _______________________________________________ >> llvm-commits mailing list >> llvm-commits at cs.uiuc.edu >> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits > -------------- next part -------------- A non-text attachment was scrubbed... Name: cr-apint.patch Type: text/x-patch Size: 2201 bytes Desc: not available Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20120105/ef32f72c/attachment.bin -------------- next part -------------- A non-text attachment was scrubbed... Name: cr-smallset.patch Type: text/x-patch Size: 826 bytes Desc: not available Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20120105/ef32f72c/attachment-0001.bin From baldrick at free.fr Thu Jan 5 05:56:44 2012 From: baldrick at free.fr (Duncan Sands) Date: Thu, 05 Jan 2012 12:56:44 +0100 Subject: [llvm-commits] [LLVM, SwitchInst, case ranges] Auxiliary patch #1 In-Reply-To: <4F058C43.7020908@narod.ru> References: <4EAA9B5D.802@narod.ru> <4EAA9DE8.80000@free.fr> <485181319805488@web67.yandex.ru> <4EAB079D.6000606@free.fr> <4EB18F12.6060409@narod.ru> <4EB7C319.1000709@narod.ru> <4EDE7D75.704@narod.ru> <4EDFD0F4.1040204@narod.ru> <4EE25B61.9070006@narod.ru> <4EE5C06C.3050705@narod.ru> <333531323974498@web57.yandex.ru> <4EEB9C52.1050301@narod.ru> <4EF37B6B.6000205@narod.ru> <4EFA0748.9080702@narod.ru> <4EFCAA6A.20203@narod.ru> <610731325498362@web6.yandex.ru> <200871325616668@web103.yandex.ru> <5633CF27-DD22-4595-A197-DFFCC56B6342@apple.com> <4F058C43.7020908@narod.ru> Message-ID: <4F058FFC.50708@free.fr> Hi Stepan, > Of course. Two patches. The first one extends APInt. The second one extends > SmallSet. what's the point of adding an "initialized" field to APInt? If you need such a concept you can always introduce your own type wrapping APInt which consists of a pair: an APInt and an "initialized" field. Also, why is that change bundled in with the unrelated ULess struct? And what's that struct for? Ciao, Duncan. > > -Stepan. > > Evan Cheng wrote: >> Where is the patch? Can you attach it again? >> >> Thanks, >> >> Evan >> >> On Jan 3, 2012, at 10:51 AM, Stepan Dyatkovskiy wrote: >> >>> Ping. >>> -- >>> Truly yours, >>> Stepan Dyatkovskiy >>> >>> 02.01.2012, 13:59, "Stepan Dyatkovskiy": >>>> Ping again and again :-) >>>> -Stepan. >>>> >>>> 29.12.2011, 21:59, "Stepan Dyatkovskiy": >>>> >>>>> Ping. >>>>> -Stepan. >>>>> >>>>> Stepan Dyatkovskiy wrote: >>>>>> ping. >>>>>> Stepan Dyatkovskiy wrote: >>>>>>> Ping. >>>>>>> >>>>>>> Stepan Dyatkovskiy wrote: >>>>>>>> Ping. >>>>>>>> >>>>>>>> -Stepan. >>> _______________________________________________ >>> llvm-commits mailing list >>> llvm-commits at cs.uiuc.edu >>> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits >> > > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From benny.kra at googlemail.com Thu Jan 5 06:38:11 2012 From: benny.kra at googlemail.com (Benjamin Kramer) Date: Thu, 5 Jan 2012 13:38:11 +0100 Subject: [llvm-commits] [llvm] r147580 - in /llvm/trunk/test: CodeGen/X86/avx-shuffle-x86_32.ll CodeGen/X86/cmpxchg16b.ll CodeGen/XCore/2011-08-01-DynamicAllocBug.ll Transforms/InstCombine/icmp.ll Transforms/SimplifyCFG/preserve-branchweights.ll In-Reply-To: <5AB5E35B-739C-4680-AC18-262C67B1E23C@apple.com> References: <20120105004335.39BCF2A6C12C@llvm.org> <5AB5E35B-739C-4680-AC18-262C67B1E23C@apple.com> Message-ID: On 05.01.2012, at 01:50, Chris Lattner wrote: > > On Jan 4, 2012, at 4:43 PM, Benjamin Kramer wrote: > >> Author: d0k >> Date: Wed Jan 4 18:43:34 2012 >> New Revision: 147580 >> >> URL: http://llvm.org/viewvc/llvm-project?rev=147580&view=rev >> Log: >> FileCheck hygiene. > > Should FileCheck output a warning or error when the prefix is seen without a : or -NOT: ? This sounds like a good idea, but it's not really feasible. We don't want to warn for a stray CHECK somewhere in the text (e.g. "-check-prefix=CHECK" in a RUN line). It would require teaching FileCheck about line beginnings, which would in turn require teaching FileCheck about comments in our various input formats. Also this mistakes come in various flavors, for example: - Missing : (the most common one) - Wrong capitalization (ChECK, CHEck) - Other typos (CHEKC, CHEK, CHECK;) A better idea would be to add some kind of linter to lit which can also match other best practices but is allowed to produce false positives. I'm not annoyed enough to implement that at the moment though. - Ben From baldrick at free.fr Thu Jan 5 07:12:07 2012 From: baldrick at free.fr (Duncan Sands) Date: Thu, 05 Jan 2012 13:12:07 -0000 Subject: [llvm-commits] [dragonegg] r147606 - /dragonegg/trunk/TODO Message-ID: <20120105131207.4B5C12A6C12C@llvm.org> Author: baldrick Date: Thu Jan 5 07:12:06 2012 New Revision: 147606 URL: http://llvm.org/viewvc/llvm-project?rev=147606&view=rev Log: Add item about GEP indices. Modified: dragonegg/trunk/TODO Modified: dragonegg/trunk/TODO URL: http://llvm.org/viewvc/llvm-project/dragonegg/trunk/TODO?rev=147606&r1=147605&r2=147606&view=diff ============================================================================== --- dragonegg/trunk/TODO (original) +++ dragonegg/trunk/TODO Thu Jan 5 07:12:06 2012 @@ -60,6 +60,11 @@ Code quality ------------ +Consider not extending GEP indices to "pointer type" since GEP indices can have +any integer type now (except for struct GEP's - there the type must be i32). +Note that GEP indices are implicitly sign extended, so unsigned indices still +need to be explicitly zero extended to pointer size (is this always done now?). + Clarify and extend the distinction between gimple registers and "the rest", the rest being mostly references. From baldrick at free.fr Thu Jan 5 10:13:08 2012 From: baldrick at free.fr (Duncan Sands) Date: Thu, 05 Jan 2012 17:13:08 +0100 Subject: [llvm-commits] [llvm] r146822 - in /llvm/trunk: lib/Transforms/Utils/SimplifyCFG.cpp test/Transforms/SimplifyCFG/PredictNestedBranch.ll In-Reply-To: <0AF83E0A-B4E5-4678-B9E4-D19280A04A0B@apple.com> References: <20111217063238.57E6C2A6C12C@llvm.org> <4F04BADA.5090403@free.fr> <0AF83E0A-B4E5-4678-B9E4-D19280A04A0B@apple.com> Message-ID: <4F05CC14.3000607@free.fr> Hi Peter, > I would assume that boosting GVN and replacing all a's with b's in your example, even if not constant would be a good thing. We might then only have one of them live at a time for example. I've attached the patch. As I'm mentioned I'm not sure this is worth doing for the small improvements it gives (and it can increase register pressure). > The code in SimplifyCFG is slightly more general in that it can handle other conditions like knowing that 'a< b' means that 'a> b' is false and other such combinations. The CorrelatedValuePropagation pass should also be capable of getting this, at least with the second attached patch applied. Unfortunately it doesn't (I'm not sure why - I never had much luck getting this pass to do anything useful). Ciao, Duncan. > > Thanks, > Pete > > On Jan 4, 2012, at 12:47 PM, Duncan Sands wrote: > >> Hi Peter, >> >>> SimplifyCFG now predicts some conditional branches to true or false depending on previous branch on same comparison operands. >>> >>> For example, >>> >>> if (a == b) { >>> if (a> b) // this is false >> >> if b is a constant then GVN will replace all instances of a with b in the >> if block, resulting in "if (b> b)" which will then be simplified to false. >> The GVN code could easily be taught to also handle the case in which b is not >> a constant. In fact that's how I first did it, but it didn't result in >> many improvements, so I didn't think it was worth the (small) compile time >> cost and so I committed the "constant b only" version instead. It would be >> easy to resurrect it. It only does something useful when the original >> condition is == (or !=), but since it would replace a by b everywhere in the >> block it can simplify all kinds of things in the block. What do you think - >> worth boosting the GVN code? >> >> Ciao, Duncan. >> >>> >>> Fixes some of the issues on >>> >>> Added: >>> llvm/trunk/test/Transforms/SimplifyCFG/PredictNestedBranch.ll >>> Modified: >>> llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp >>> >>> Modified: llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp >>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp?rev=146822&r1=146821&r2=146822&view=diff >>> ============================================================================== >>> --- llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp (original) >>> +++ llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp Sat Dec 17 00:32:38 2011 >>> @@ -12,6 +12,7 @@ >>> //===----------------------------------------------------------------------===// >>> >>> #define DEBUG_TYPE "simplifycfg" >>> +#include "llvm/Transforms/Utils/CmpInstAnalysis.h" >>> #include "llvm/Transforms/Utils/Local.h" >>> #include "llvm/Constants.h" >>> #include "llvm/Instructions.h" >>> @@ -1702,6 +1703,47 @@ >>> } >>> } >>> >>> + // Treat "if (cond1) { if (cond2) {} }" as "cond1& cond2" and fold. >>> + // This gives us the value of what cond2 is given cond1 is already known to >>> + // be true. >>> + if (ICmpInst *LHS = dyn_cast(PBI->getCondition())) { >>> + if (ICmpInst *RHS = dyn_cast(BI->getCondition())) { >>> + ICmpInst::Predicate LHSCC = LHS->getPredicate(), >>> + RHSCC = RHS->getPredicate(); >>> + if (PredicatesFoldable(LHSCC, RHSCC)) { >>> + if (LHS->getOperand(0) == RHS->getOperand(1)&& >>> + LHS->getOperand(1) == RHS->getOperand(0)) >>> + LHS->swapOperands(); >>> + if (LHS->getOperand(0) == RHS->getOperand(0)&& >>> + LHS->getOperand(1) == RHS->getOperand(1)&& >>> + BB->getSinglePredecessor()) { >>> + Value *Op0 = LHS->getOperand(0), *Op1 = LHS->getOperand(1); >>> + bool CondIsTrue = PBI->getSuccessor(0) == BB; >>> + unsigned LHSCode = getICmpCode(LHS, !CondIsTrue); >>> + unsigned RHSCode = getICmpCode(RHS); >>> + unsigned Code = LHSCode& RHSCode; >>> + >>> + Value *ConstantCondition = NULL; >>> + // If the resultant code is the same as the LHS code then as that >>> + // code is known to be true we can make RHS now be true. >>> + if (Code == LHSCode) >>> + ConstantCondition = ConstantInt::get( >>> + CmpInst::makeCmpResultType(LHS->getType()), 1); >>> + else { >>> + bool isSigned = LHS->isSigned() || RHS->isSigned(); >>> + CmpInst::Predicate IgnoredNewPred; >>> + ConstantCondition = getICmpValue(isSigned, Code, Op0, Op1, >>> + IgnoredNewPred); >>> + } >>> + if (ConstantCondition) { >>> + RHS->replaceAllUsesWith(ConstantCondition); >>> + return true; >>> + } >>> + } >>> + } >>> + } >>> + } >>> + >>> // If this is a conditional branch in an empty block, and if any >>> // predecessors is a conditional branch to one of our destinations, >>> // fold the conditions into logical ops and one cond br. >>> >>> Added: llvm/trunk/test/Transforms/SimplifyCFG/PredictNestedBranch.ll >>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/SimplifyCFG/PredictNestedBranch.ll?rev=146822&view=auto >>> ============================================================================== >>> --- llvm/trunk/test/Transforms/SimplifyCFG/PredictNestedBranch.ll (added) >>> +++ llvm/trunk/test/Transforms/SimplifyCFG/PredictNestedBranch.ll Sat Dec 17 00:32:38 2011 >>> @@ -0,0 +1,152 @@ >>> + >>> +; RUN: opt< %s -simplifycfg -dce -S | FileCheck %s >>> + >>> +; Test that when == is true, all 6 comparisons evaluate to true or false >>> +; ie, a == b implies a> b is false, but a>= b is true, and so on >>> +define void @testEqTrue(i32 %a, i32 %b) { >>> +; CHECK: @testEqTrue >>> +; CHECK: icmp eq i32 %a, %b >>> +; CHECK: call void @_Z1gi(i32 0) >>> +; a == b implies a == b >>> +; CHECK-NEXT: call void @_Z1gi(i32 1) >>> +; a == b implies a>= b >>> +; CHECK-NEXT: call void @_Z1gi(i32 3) >>> +; a == b implies a<= b >>> +; CHECK-NEXT: call void @_Z1gi(i32 4) >>> +; CHECK: ret void >>> +entry: >>> + %cmp = icmp eq i32 %a, %b >>> + br i1 %cmp, label %if.then, label %if.end18 >>> + >>> +if.then: ; preds = %entry >>> + call void @_Z1gi(i32 0) >>> + %cmp1 = icmp eq i32 %a, %b >>> + br i1 %cmp1, label %if.then2, label %if.end >>> + >>> +if.then2: ; preds = %if.then >>> + call void @_Z1gi(i32 1) >>> + br label %if.end >>> + >>> +if.end: ; preds = %if.then2, %if.then >>> + %cmp3 = icmp ne i32 %a, %b >>> + br i1 %cmp3, label %if.then4, label %if.end5 >>> + >>> +if.then4: ; preds = %if.end >>> + call void @_Z1gi(i32 2) >>> + br label %if.end5 >>> + >>> +if.end5: ; preds = %if.then4, %if.end >>> + %cmp6 = icmp sge i32 %a, %b >>> + br i1 %cmp6, label %if.then7, label %if.end8 >>> + >>> +if.then7: ; preds = %if.end5 >>> + call void @_Z1gi(i32 3) >>> + br label %if.end8 >>> + >>> +if.end8: ; preds = %if.then7, %if.end5 >>> + %cmp9 = icmp sle i32 %a, %b >>> + br i1 %cmp9, label %if.then10, label %if.end11 >>> + >>> +if.then10: ; preds = %if.end8 >>> + call void @_Z1gi(i32 4) >>> + br label %if.end11 >>> + >>> +if.end11: ; preds = %if.then10, %if.end8 >>> + %cmp12 = icmp sgt i32 %a, %b >>> + br i1 %cmp12, label %if.then13, label %if.end14 >>> + >>> +if.then13: ; preds = %if.end11 >>> + call void @_Z1gi(i32 5) >>> + br label %if.end14 >>> + >>> +if.end14: ; preds = %if.then13, %if.end11 >>> + %cmp15 = icmp slt i32 %a, %b >>> + br i1 %cmp15, label %if.then16, label %if.end18 >>> + >>> +if.then16: ; preds = %if.end14 >>> + call void @_Z1gi(i32 6) >>> + br label %if.end18 >>> + >>> +if.end18: ; preds = %if.end14, %if.then16, %entry >>> + ret void >>> +} >>> + >>> +; Test that when == is false, all 6 comparisons evaluate to true or false >>> +; ie, a == b implies a> b is false, but a>= b is true, and so on >>> +define void @testEqFalse(i32 %a, i32 %b) { >>> +; CHECK: @testEqFalse >>> +; CHECK: icmp eq i32 %a, %b >>> +; CHECK: call void @_Z1gi(i32 0) >>> +; CHECK-NOT: call void @_Z1gi(i32 1) >>> +; CHECK-NOT: icmp ne >>> +; CHECK: call void @_Z1gi(i32 2) >>> +; CHECK: icmp sge >>> +; CHECK: call void @_Z1gi(i32 3) >>> +; CHECK: icmp sle >>> +; CHECK: call void @_Z1gi(i32 4) >>> +; CHECK: icmp sgt >>> +; CHECK: call void @_Z1gi(i32 5) >>> +; CHECK: icmp slt >>> +; CHECK: call void @_Z1gi(i32 6) >>> +; CHECK: ret void >>> +entry: >>> + %cmp = icmp eq i32 %a, %b >>> + br i1 %cmp, label %if.then, label %if.else >>> + >>> +if.then: ; preds = %entry >>> + call void @_Z1gi(i32 0) >>> + br label %if.end18 >>> + >>> +if.else: >>> + %cmp1 = icmp eq i32 %a, %b >>> + br i1 %cmp1, label %if.then2, label %if.end >>> + >>> +if.then2: ; preds = %if.then >>> + call void @_Z1gi(i32 1) >>> + br label %if.end >>> + >>> +if.end: ; preds = %if.then2, %if.then >>> + %cmp3 = icmp ne i32 %a, %b >>> + br i1 %cmp3, label %if.then4, label %if.end5 >>> + >>> +if.then4: ; preds = %if.end >>> + call void @_Z1gi(i32 2) >>> + br label %if.end5 >>> + >>> +if.end5: ; preds = %if.then4, %if.end >>> + %cmp6 = icmp sge i32 %a, %b >>> + br i1 %cmp6, label %if.then7, label %if.end8 >>> + >>> +if.then7: ; preds = %if.end5 >>> + call void @_Z1gi(i32 3) >>> + br label %if.end8 >>> + >>> +if.end8: ; preds = %if.then7, %if.end5 >>> + %cmp9 = icmp sle i32 %a, %b >>> + br i1 %cmp9, label %if.then10, label %if.end11 >>> + >>> +if.then10: ; preds = %if.end8 >>> + call void @_Z1gi(i32 4) >>> + br label %if.end11 >>> + >>> +if.end11: ; preds = %if.then10, %if.end8 >>> + %cmp12 = icmp sgt i32 %a, %b >>> + br i1 %cmp12, label %if.then13, label %if.end14 >>> + >>> +if.then13: ; preds = %if.end11 >>> + call void @_Z1gi(i32 5) >>> + br label %if.end14 >>> + >>> +if.end14: ; preds = %if.then13, %if.end11 >>> + %cmp15 = icmp slt i32 %a, %b >>> + br i1 %cmp15, label %if.then16, label %if.end18 >>> + >>> +if.then16: ; preds = %if.end14 >>> + call void @_Z1gi(i32 6) >>> + br label %if.end18 >>> + >>> +if.end18: ; preds = %if.end14, %if.then16, %entry >>> + ret void >>> +} >>> + >>> +declare void @_Z1gi(i32) >>> >>> >>> _______________________________________________ >>> llvm-commits mailing list >>> llvm-commits at cs.uiuc.edu >>> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits >> >> _______________________________________________ >> llvm-commits mailing list >> llvm-commits at cs.uiuc.edu >> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits > -------------- next part -------------- A non-text attachment was scrubbed... Name: gvn.eqprop.diff Type: text/x-patch Size: 3262 bytes Desc: not available Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20120105/c6331405/attachment.bin -------------- next part -------------- A non-text attachment was scrubbed... Name: corvalprop.diff Type: text/x-patch Size: 1555 bytes Desc: not available Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20120105/c6331405/attachment-0001.bin From rafael.espindola at gmail.com Thu Jan 5 11:19:20 2012 From: rafael.espindola at gmail.com (=?ISO-8859-1?Q?Rafael_=C1vila_de_Esp=EDndola?=) Date: Thu, 05 Jan 2012 12:19:20 -0500 Subject: [llvm-commits] [Mips] Direct object big endian review and submittal request In-Reply-To: <86AC779C188FE74F88F6494478B46332E9156D@exchdb03.mips.com> References: <86AC779C188FE74F88F6494478B46332E9156D@exchdb03.mips.com> Message-ID: <4F05DB98.1050103@gmail.com> I hope to take a look a this week. Just a quick comment first: -; CHECK: ('r_type', 0x2b) -; CHECK: ('r_type', 0x2c) -; CHECK: ('r_type', 0x2d) +; CHECK: ('r_type', 0x{{[0]*}}2b) +; CHECK: ('r_type', 0x{{[0]*}}2c) +; CHECK: ('r_type', 0x{{[0]*}}2d) Why is this needed? The elf-dump script should be printing the value with the correct number of bits (8 on 32 ELF and 32 on 64 bit ELF). Is the script not doing the right thing for big endian ELF files? Cheers, Rafael From clattner at apple.com Thu Jan 5 11:29:44 2012 From: clattner at apple.com (Chris Lattner) Date: Thu, 05 Jan 2012 09:29:44 -0800 Subject: [llvm-commits] [llvm] r147580 - in /llvm/trunk/test: CodeGen/X86/avx-shuffle-x86_32.ll CodeGen/X86/cmpxchg16b.ll CodeGen/XCore/2011-08-01-DynamicAllocBug.ll Transforms/InstCombine/icmp.ll Transforms/SimplifyCFG/preserve-branchweights.ll In-Reply-To: References: <20120105004335.39BCF2A6C12C@llvm.org> <5AB5E35B-739C-4680-AC18-262C67B1E23C@apple.com> Message-ID: On Jan 5, 2012, at 4:38 AM, Benjamin Kramer wrote: > On 05.01.2012, at 01:50, Chris Lattner wrote: > On Jan 4, 2012, at 4:43 PM, Benjamin Kramer wrote: >> >>> Author: d0k >>> Date: Wed Jan 4 18:43:34 2012 >>> New Revision: 147580 >>> >>> URL: http://llvm.org/viewvc/llvm-project?rev=147580&view=rev >>> Log: >>> FileCheck hygiene. >> >> Should FileCheck output a warning or error when the prefix is seen without a : or -NOT: ? > > This sounds like a good idea, but it's not really feasible. We don't want to warn for a stray CHECK somewhere in the text (e.g. "-check-prefix=CHECK" in a RUN line). It would require teaching FileCheck about line beginnings, which would in turn require teaching FileCheck about comments in our various input formats. > > Also this mistakes come in various flavors, for example: > - Missing : (the most common one) > - Wrong capitalization (ChECK, CHEck) > - Other typos (CHEKC, CHEK, CHECK;) Ah, yeah, all good points. > A better idea would be to add some kind of linter to lit which can also match other best practices but is allowed to produce false positives. I'm not annoyed enough to implement that at the moment though. Yep, doesn't seem high priority. Thanks Benjamin! -Chris From clattner at apple.com Thu Jan 5 11:36:27 2012 From: clattner at apple.com (Chris Lattner) Date: Thu, 05 Jan 2012 09:36:27 -0800 Subject: [llvm-commits] [llvm] r147560 - in /llvm/trunk: include/llvm/Analysis/ValueTracking.h lib/Analysis/ValueTracking.cpp In-Reply-To: <4F055E6B.5040909@free.fr> References: <20120104230110.3CC2A2A6C12C@llvm.org> <4F055E6B.5040909@free.fr> Message-ID: <25EBF8BB-A657-4477-B4B5-715C0E9EBBF2@apple.com> On Jan 5, 2012, at 12:25 AM, Duncan Sands wrote: > Hi Dan, > >> Generalize isSafeToSpeculativelyExecute to work on arbitrary >> Values, rather than just Instructions, since it's interesting >> for ConstantExprs too. > > since constants are not executed, what does this mean? I notice that all > constants results in 'false', i.e. not safe to speculatively execute. Why > is that? Constant expressions can potentially trap (e.g. divide with a RHS that turns out to be zero). This is why they have the canTrap() method. This is annoying and should be fixed someday, but until then this is a reasonable thing to do. The dyncast to Operator handles both instructions and constantexprs. -Chris > > Ciao, Duncan. > >> >> Modified: >> llvm/trunk/include/llvm/Analysis/ValueTracking.h >> llvm/trunk/lib/Analysis/ValueTracking.cpp >> >> Modified: llvm/trunk/include/llvm/Analysis/ValueTracking.h >> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Analysis/ValueTracking.h?rev=147560&r1=147559&r2=147560&view=diff >> ============================================================================== >> --- llvm/trunk/include/llvm/Analysis/ValueTracking.h (original) >> +++ llvm/trunk/include/llvm/Analysis/ValueTracking.h Wed Jan 4 17:01:09 2012 >> @@ -174,7 +174,7 @@ >> /// the correct dominance relationships for the operands and users hold. >> /// However, this method can return true for instructions that read memory; >> /// for such instructions, moving them may change the resulting value. >> - bool isSafeToSpeculativelyExecute(const Instruction *Inst, >> + bool isSafeToSpeculativelyExecute(const Value *V, >> const TargetData *TD = 0); >> >> } // end namespace llvm >> >> Modified: llvm/trunk/lib/Analysis/ValueTracking.cpp >> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/ValueTracking.cpp?rev=147560&r1=147559&r2=147560&view=diff >> ============================================================================== >> --- llvm/trunk/lib/Analysis/ValueTracking.cpp (original) >> +++ llvm/trunk/lib/Analysis/ValueTracking.cpp Wed Jan 4 17:01:09 2012 >> @@ -1879,8 +1879,12 @@ >> return true; >> } >> >> -bool llvm::isSafeToSpeculativelyExecute(const Instruction *Inst, >> +bool llvm::isSafeToSpeculativelyExecute(const Value *V, >> const TargetData *TD) { >> + const Operator *Inst = dyn_cast(V); >> + if (!Inst) >> + return false; >> + >> for (unsigned i = 0, e = Inst->getNumOperands(); i != e; ++i) >> if (Constant *C = dyn_cast(Inst->getOperand(i))) >> if (C->canTrap()) >> >> >> _______________________________________________ >> llvm-commits mailing list >> llvm-commits at cs.uiuc.edu >> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From sabre at nondot.org Thu Jan 5 11:35:07 2012 From: sabre at nondot.org (Chris Lattner) Date: Thu, 05 Jan 2012 17:35:07 -0000 Subject: [llvm-commits] [llvm] r147607 - /llvm/trunk/include/llvm/ADT/SmallSet.h Message-ID: <20120105173507.C2DC82A6C12C@llvm.org> Author: lattner Date: Thu Jan 5 11:35:07 2012 New Revision: 147607 URL: http://llvm.org/viewvc/llvm-project?rev=147607&view=rev Log: allow clients of SmallSet to specify their own comparison function for the set. Patch by Stepan Dyatkovskiy! Modified: llvm/trunk/include/llvm/ADT/SmallSet.h Modified: llvm/trunk/include/llvm/ADT/SmallSet.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/ADT/SmallSet.h?rev=147607&r1=147606&r2=147607&view=diff ============================================================================== --- llvm/trunk/include/llvm/ADT/SmallSet.h (original) +++ llvm/trunk/include/llvm/ADT/SmallSet.h Thu Jan 5 11:35:07 2012 @@ -27,13 +27,13 @@ /// /// Note that this set does not provide a way to iterate over members in the /// set. -template +template > class SmallSet { /// Use a SmallVector to hold the elements here (even though it will never /// reach its 'large' stage) to avoid calling the default ctors of elements /// we will never use. SmallVector Vector; - std::set Set; + std::set Set; typedef typename SmallVector::const_iterator VIterator; typedef typename SmallVector::iterator mutable_iterator; public: From clattner at apple.com Thu Jan 5 11:39:18 2012 From: clattner at apple.com (Chris Lattner) Date: Thu, 05 Jan 2012 09:39:18 -0800 Subject: [llvm-commits] [LLVM, SwitchInst, case ranges] Auxiliary patch #1 In-Reply-To: <4F058C43.7020908@narod.ru> References: <4EAA9B5D.802@narod.ru> <4EAA9DE8.80000@free.fr> <485181319805488@web67.yandex.ru> <4EAB079D.6000606@free.fr> <4EB18F12.6060409@narod.ru> <4EB7C319.1000709@narod.ru> <4EDE7D75.704@narod.ru> <4EDFD0F4.1040204@narod.ru> <4EE25B61.9070006@narod.ru> <4EE5C06C.3050705@narod.ru> <333531323974498@web57.yandex.ru> <4EEB9C52.1050301@narod.ru> <4EF37B6B.6000205@narod.ru> <4EFA0748.9080702@narod.ru> <4EFCAA6A.20203@narod.ru> <610731325498362@web6.yandex.ru> <200871325616668@web103.yandex.ru> <5633CF27-DD22-4595-A197-DFFCC56B6342@apple.com> <4F058C43.7020908@narod.ru> Message-ID: <6F0FECE5-F12D-4F5E-890B-385AADCB563B@apple.com> On Jan 5, 2012, at 3:40 AM, Stepan Dyatkovskiy wrote: > Of course. Two patches. The first one extends APInt. The second one extends SmallSet. I committed the SmallSet patch for you in r147607. As Duncan points out up-thread, adding an 'initialized' field to APInt isn't appropriate. -Chris > > -Stepan. > > Evan Cheng wrote: >> Where is the patch? Can you attach it again? >> >> Thanks, >> >> Evan >> >> On Jan 3, 2012, at 10:51 AM, Stepan Dyatkovskiy wrote: >> >>> Ping. >>> -- >>> Truly yours, >>> Stepan Dyatkovskiy >>> >>> 02.01.2012, 13:59, "Stepan Dyatkovskiy": >>>> Ping again and again :-) >>>> -Stepan. >>>> >>>> 29.12.2011, 21:59, "Stepan Dyatkovskiy": >>>> >>>>> Ping. >>>>> -Stepan. >>>>> >>>>> Stepan Dyatkovskiy wrote: >>>>>> ping. >>>>>> Stepan Dyatkovskiy wrote: >>>>>>> Ping. >>>>>>> >>>>>>> Stepan Dyatkovskiy wrote: >>>>>>>> Ping. >>>>>>>> >>>>>>>> -Stepan. >>> _______________________________________________ >>> llvm-commits mailing list >>> llvm-commits at cs.uiuc.edu >>> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits >> > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From STPWORLD at narod.ru Thu Jan 5 11:43:45 2012 From: STPWORLD at narod.ru (Stepan Dyatkovskiy) Date: Thu, 05 Jan 2012 21:43:45 +0400 Subject: [llvm-commits] [LLVM, SwitchInst, case ranges] Auxiliary patch #1 In-Reply-To: <6F0FECE5-F12D-4F5E-890B-385AADCB563B@apple.com> References: <4EAA9B5D.802@narod.ru> <4EAA9DE8.80000@free.fr> <485181319805488@web67.yandex.ru> <4EAB079D.6000606@free.fr> <4EB18F12.6060409@narod.ru> <4EB7C319.1000709@narod.ru> <4EDE7D75.704@narod.ru> <4EDFD0F4.1040204@narod.ru> <4EE25B61.9070006@narod.ru> <4EE5C06C.3050705@narod.ru> <333531323974498@web57.yandex.ru> <4EEB9C52.1050301@narod.ru> <4EF37B6B.6000205@narod.ru> <4EFA0748.9080702@narod.ru> <4EFCAA6A.20203@narod.ru> <610731325498362@web6.yandex.ru> <200871325616668@web103.yandex.ru> <5633CF27-DD22-4595-A197-DFFCC56B6342@apple.com> <4F058C43.7020908@narod.ru> <6F0FECE5-F12D-4F5E-890B-385AADCB563B@apple.com> Message-ID: <989681325785425@web41.yandex.ru> Due to case-ranges feature (PR1255), we want to replace switch cases type: from ConstantInt to APInt. Of course it may be some new type, call it APIntEx. We need "less" comparison for this type, since we need to sort it sometimes. And it also should support initialized property. I think that two this features will be useful for APInt itself. But of course it is possible to create new type. So, your suggestions. APIntEx for case values? -Stepan. 05.01.2012, 21:39, "Chris Lattner" : > On Jan 5, 2012, at 3:40 AM, Stepan Dyatkovskiy wrote: > >> ?Of course. Two patches. The first one extends APInt. The second one extends SmallSet. > > I committed the SmallSet patch for you in r147607. ?As Duncan points out up-thread, adding an 'initialized' field to APInt isn't appropriate. > > -Chris > >> ?-Stepan. >> >> ?Evan Cheng wrote: >>> ?Where is the patch? Can you attach it again? >>> >>> ?Thanks, >>> >>> ?Evan >>> >>> ?On Jan 3, 2012, at 10:51 AM, Stepan Dyatkovskiy wrote: >>>> ?Ping. >>>> ?-- >>>> ?Truly yours, >>>> ?Stepan Dyatkovskiy >>>> >>>> ?02.01.2012, 13:59, "Stepan Dyatkovskiy": >>>>> ?Ping again and again :-) >>>>> ?-Stepan. >>>>> >>>>> ?29.12.2011, 21:59, "Stepan Dyatkovskiy": >>>>>> ??Ping. >>>>>> ??-Stepan. >>>>>> >>>>>> ??Stepan Dyatkovskiy wrote: >>>>>>> ???ping. >>>>>>> ???Stepan Dyatkovskiy wrote: >>>>>>>> ???Ping. >>>>>>>> >>>>>>>> ???Stepan Dyatkovskiy wrote: >>>>>>>>> ???Ping. >>>>>>>>> >>>>>>>>> ???-Stepan. >>>> ?_______________________________________________ >>>> ?llvm-commits mailing list >>>> ?llvm-commits at cs.uiuc.edu >>>> ?http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits >> ?_______________________________________________ >> ?llvm-commits mailing list >> ?llvm-commits at cs.uiuc.edu >> ?http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From clattner at apple.com Thu Jan 5 11:43:56 2012 From: clattner at apple.com (Chris Lattner) Date: Thu, 05 Jan 2012 09:43:56 -0800 Subject: [llvm-commits] [LLVM, SwitchInst, case ranges] Auxiliary patch #1 In-Reply-To: <4EAF980A.4010206@free.fr> References: <4EAA9B5D.802@narod.ru> <4EAA9DE8.80000@free.fr> <485181319805488@web67.yandex.ru> <4EAB079D.6000606@free.fr> <4EAF980A.4010206@free.fr> Message-ID: On Oct 31, 2011, at 11:56 PM, Duncan Sands wrote: > Hi Anton, > >>> be the opposite: they might make switches harder to work with and reason about >>> for no advantage. Which is it? Do you have an example where case ranges would >>> result in better code, or make it easier to produce better code? >> I think the typical example is some code which produces large >> switches. In the frontend we >> won't emit such large switches and end with explicit comparisons instead. >> >> Do you have some example of this from Ada world? I believe I saw >> something like this in Polyhedron, but I'm not sure. > > this happens all the time with Ada, for example with ranges like "all negative > numbers". Currently the front-end emits explicit compares and branches for the > big ranges (more than 64 cases), and a switch for the rest. If LLVM switches > had ranges, would LLVM produce better code for this kind of thing? I haven't had a chance to look at Stepan's patch, but FWIW I'm generally supportive of the idea. One problem that this solves is that our current modeling of switches causes us to have critical edges from the switch for trivial cases. For example: switch (x) { case 4: case 5: stuff will have two CFG edges from the switch, both going to the same block (so it has multiple predecessors). Various code that splits this critical edge end up producing really really bad code. If we modeled that as one edge in the CFG, many similar problems would disappear. -Chris From clattner at apple.com Thu Jan 5 12:01:12 2012 From: clattner at apple.com (Chris Lattner) Date: Thu, 05 Jan 2012 10:01:12 -0800 Subject: [llvm-commits] [llvm] r147431 - in /llvm/trunk/unittests: Bitcode/ Bitcode/BitReaderTest.cpp Bitcode/Makefile CMakeLists.txt Makefile VMCore/Makefile VMCore/pr11677.cpp In-Reply-To: <4F0391C0.1040403@gmail.com> References: <20120102091948.9C2891BE003@llvm.org> <1F59E691-F155-4C99-9E6F-F68F3D5EE070@apple.com> <4F0391C0.1040403@gmail.com> Message-ID: On Jan 3, 2012, at 3:39 PM, Rafael ?vila de Esp?ndola wrote: >> Why not write this as an LTO test in llvm/test/Linker then? >> > > I was only able to make this particular manifestation of the bug show up > with the C lto api or by emulating what it was doing. What is needed is > running the verifier before the function is materialized. > > I wrote a unit test because I could not reproduce it with the tools in > the repository, and depending on an external tool (gold) would be bad. > > An option that I considered was changing opt to (optionally?) use the > lazy bitcode reader. With that I think this test could become just > > llvm-as %s -o %t.bc > opt -verify %t.bc > > Would that be better? At this point, I think that keeping the existing unittest is the right way to go (or just remove it). I don't think spending more time on testing of this trivial fix is worth it :) Thanks Rafael, -Chris From enderby at apple.com Thu Jan 5 12:14:43 2012 From: enderby at apple.com (Kevin Enderby) Date: Thu, 05 Jan 2012 10:14:43 -0800 Subject: [llvm-commits] PATCH: ARM_TARGET1 relocation for C++ global constructors In-Reply-To: References: <000c01ccbff2$ee95d750$cbc185f0$%molloy@arm.com> Message-ID: I've looked at the patch but I don't know this area. I think it may have to wait for Jim to say if it is correct for all platforms. Kev On Jan 4, 2012, at 11:12 PM, Evan Cheng wrote: > Has this been reviewed? > > I'm not sure if this patch is correct for all platforms, e.g. iOS. Jim, Kevin, and Owen, do you guys know? > > Evan > > On Dec 21, 2011, at 7:12 AM, James Molloy wrote: > >> Hi, >> >> Attached is a patch to cause the relocations for C++ global/static constructor thunks to be outputted properly on ARM. The ABI states that these thunks should have an R_ARM_TARGET1 relocation type applied to them for portability reasons. Currently they?re emitted as normal global variables so get an R_ARM_ABS32. >> >> I?ve implemented this by creating a new overridable hook, ?EmitXXStructor()?, in the AsmPrinter. For all targets this defaults to EmitGlobalConstant as usual, but ARM overrides it to emit a constant with this specific relocation type. >> >> Am I OK to commit? >> >> Cheers, >> >> James >> _______________________________________________ >> llvm-commits mailing list >> llvm-commits at cs.uiuc.edu >> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits > -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20120105/221e49a9/attachment.html From baldrick at free.fr Thu Jan 5 12:17:25 2012 From: baldrick at free.fr (Duncan Sands) Date: Thu, 05 Jan 2012 19:17:25 +0100 Subject: [llvm-commits] [LLVM, SwitchInst, case ranges] Auxiliary patch #1 In-Reply-To: <989681325785425@web41.yandex.ru> References: <4EAA9B5D.802@narod.ru> <4EAA9DE8.80000@free.fr> <485181319805488@web67.yandex.ru> <4EAB079D.6000606@free.fr> <4EB18F12.6060409@narod.ru> <4EB7C319.1000709@narod.ru> <4EDE7D75.704@narod.ru> <4EDFD0F4.1040204@narod.ru> <4EE25B61.9070006@narod.ru> <4EE5C06C.3050705@narod.ru> <333531323974498@web57.yandex.ru> <4EEB9C52.1050301@narod.ru> <4EF37B6B.6000205@narod.ru> <4EFA0748.9080702@narod.ru> <4EFCAA6A.20203@narod.ru> <610731325498362@web6.yandex.ru> <200871325616668@web103.yandex.ru> <5633CF27-DD22-4595-A197-DFFCC56B6342@apple.com> <4F058C43.7020908@narod.ru> <6F0FECE5-F12D-4F5E-890B-385AADCB563B@apple.com> <989681325785425@web41.yandex.ru> Message-ID: <4F05E935.5000604@free.fr> Hi Stepan, > Due to case-ranges feature (PR1255), we want to replace switch cases type: from ConstantInt to APInt. Of course it may be some new type, call it APIntEx. We need "less" comparison for this type, since we need to sort it sometimes. And it also should support initialized property. I think that two this features will be useful for APInt itself. But of course it is possible to create new type. So, your suggestions. APIntEx for case values? are you considering switch values to be unsigned? In C they are signed, while in Ada they can be either. As a result you can get signed or unsigned case ranges coming out of dragonegg. Better to use wrapping ranges (like in LLVM's ConstantRange abstraction) for which there is no difference between signed and unsigned... I'm not sure why you think you need "initialized" APInt's for case ranges... As for the ULess struct, I reckon that would be better off in the file that uses it. Ciao, Duncan. > > -Stepan. > > 05.01.2012, 21:39, "Chris Lattner": >> On Jan 5, 2012, at 3:40 AM, Stepan Dyatkovskiy wrote: >> >>> Of course. Two patches. The first one extends APInt. The second one extends SmallSet. >> >> I committed the SmallSet patch for you in r147607. As Duncan points out up-thread, adding an 'initialized' field to APInt isn't appropriate. >> >> -Chris >> >>> -Stepan. >>> >>> Evan Cheng wrote: >>>> Where is the patch? Can you attach it again? >>>> >>>> Thanks, >>>> >>>> Evan >>>> >>>> On Jan 3, 2012, at 10:51 AM, Stepan Dyatkovskiy wrote: >>>>> Ping. >>>>> -- >>>>> Truly yours, >>>>> Stepan Dyatkovskiy >>>>> >>>>> 02.01.2012, 13:59, "Stepan Dyatkovskiy": >>>>>> Ping again and again :-) >>>>>> -Stepan. >>>>>> >>>>>> 29.12.2011, 21:59, "Stepan Dyatkovskiy": >>>>>>> Ping. >>>>>>> -Stepan. >>>>>>> >>>>>>> Stepan Dyatkovskiy wrote: >>>>>>>> ping. >>>>>>>> Stepan Dyatkovskiy wrote: >>>>>>>>> Ping. >>>>>>>>> >>>>>>>>> Stepan Dyatkovskiy wrote: >>>>>>>>>> Ping. >>>>>>>>>> >>>>>>>>>> -Stepan. >>>>> _______________________________________________ >>>>> llvm-commits mailing list >>>>> llvm-commits at cs.uiuc.edu >>>>> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits >>> _______________________________________________ >>> llvm-commits mailing list >>> llvm-commits at cs.uiuc.edu >>> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits >> >> _______________________________________________ >> llvm-commits mailing list >> llvm-commits at cs.uiuc.edu >> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From spop at codeaurora.org Thu Jan 5 12:27:24 2012 From: spop at codeaurora.org (Sebastian Pop) Date: Thu, 5 Jan 2012 12:27:24 -0600 Subject: [llvm-commits] [llvm] r147542 - in /llvm/trunk: autoconf/configure.ac cmake/config-ix.cmake configure include/llvm/Config/config.h.cmake include/llvm/Config/config.h.in include/llvm/Config/llvm-config.h.cmake include/llvm/Config/llvm-config.h.in In-Reply-To: <20120104220646.GA27691@britannica.bec.de> References: <20120104220646.GA27691@britannica.bec.de> Message-ID: On Wed, Jan 4, 2012 at 4:06 PM, Joerg Sonnenberger wrote: > On Wed, Jan 04, 2012 at 03:14:13PM -0600, Sebastian Pop wrote: >> > Strictly speaking, running e.g. i386-linux on x86_64-netbsd is a >> > cross-compiler. It can never the less work. >> >> I am sorry to not see all the details of your example, >> could you please give more details? ?So you have a cross compiler >> hosted on x86_64-netbsd and targeting i386-linux. ?When you run >> LLVM as a JIT you would like it to run on the host x86_64-netbsd, right? >> Then it also has to produce code for the host x86_64-netbsd, and not >> for the target i386-linux, as I'm assuming that the include files are >> different than your host OS. > > No, it doesn't have to run code for x86_64-netbsd. I can build the LLVM > libraries for i386-linux, link it, run it and it will work. Sure, I > likely have to provide it with Linux compatible header files etc like > using cross-compilation in general. My point remains that just because I > am cross-compiling doesn't mean I can't execute JIT code. Thanks for your explanations: I agree with your comments, and I am reverting the patch that I committed. I still seem to have a problem with the definition of what a JIT is: for me a JIT is a compiler that generates, then executes the code on the same machine on which the JIT compiler runs. This is the reason why I was thinking that in the case of a JIT, the compiler should produce code for the host. After thinking a bit more about your comment I can see that it is possible to configure llvm in a cross-compiler setting intentionally to have the JIT producing code for a target different than the host. Thanks again for your review, Sebastian -- Qualcomm Innovation Center, Inc is a member of Code Aurora Forum From peter_cooper at apple.com Thu Jan 5 12:27:51 2012 From: peter_cooper at apple.com (Peter Cooper) Date: Thu, 05 Jan 2012 10:27:51 -0800 Subject: [llvm-commits] [llvm] r146822 - in /llvm/trunk: lib/Transforms/Utils/SimplifyCFG.cpp test/Transforms/SimplifyCFG/PredictNestedBranch.ll In-Reply-To: <4F05CC14.3000607@free.fr> References: <20111217063238.57E6C2A6C12C@llvm.org> <4F04BADA.5090403@free.fr> <0AF83E0A-B4E5-4678-B9E4-D19280A04A0B@apple.com> <4F05CC14.3000607@free.fr> Message-ID: <0ABA28A5-2E14-4707-8B41-6EB9551E3698@apple.com> Hi Duncan Thanks for this. I might not have time to try it out to measure performance for a few days but i'll let you know what i find when i do get time. Thanks, Pete On Jan 5, 2012, at 8:13 AM, Duncan Sands wrote: > Hi Peter, > >> I would assume that boosting GVN and replacing all a's with b's in your example, even if not constant would be a good thing. We might then only have one of them live at a time for example. > > I've attached the patch. As I'm mentioned I'm not sure this is worth doing for > the small improvements it gives (and it can increase register pressure). > >> The code in SimplifyCFG is slightly more general in that it can handle other conditions like knowing that 'a< b' means that 'a> b' is false and other such combinations. > > The CorrelatedValuePropagation pass should also be capable of getting this, > at least with the second attached patch applied. Unfortunately it doesn't > (I'm not sure why - I never had much luck getting this pass to do anything > useful). > > Ciao, Duncan. > >> >> Thanks, >> Pete >> >> On Jan 4, 2012, at 12:47 PM, Duncan Sands wrote: >> >>> Hi Peter, >>> >>>> SimplifyCFG now predicts some conditional branches to true or false depending on previous branch on same comparison operands. >>>> >>>> For example, >>>> >>>> if (a == b) { >>>> if (a> b) // this is false >>> >>> if b is a constant then GVN will replace all instances of a with b in the >>> if block, resulting in "if (b> b)" which will then be simplified to false. >>> The GVN code could easily be taught to also handle the case in which b is not >>> a constant. In fact that's how I first did it, but it didn't result in >>> many improvements, so I didn't think it was worth the (small) compile time >>> cost and so I committed the "constant b only" version instead. It would be >>> easy to resurrect it. It only does something useful when the original >>> condition is == (or !=), but since it would replace a by b everywhere in the >>> block it can simplify all kinds of things in the block. What do you think - >>> worth boosting the GVN code? >>> >>> Ciao, Duncan. >>> >>>> >>>> Fixes some of the issues on >>>> >>>> Added: >>>> llvm/trunk/test/Transforms/SimplifyCFG/PredictNestedBranch.ll >>>> Modified: >>>> llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp >>>> >>>> Modified: llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp >>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp?rev=146822&r1=146821&r2=146822&view=diff >>>> ============================================================================== >>>> --- llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp (original) >>>> +++ llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp Sat Dec 17 00:32:38 2011 >>>> @@ -12,6 +12,7 @@ >>>> //===----------------------------------------------------------------------===// >>>> >>>> #define DEBUG_TYPE "simplifycfg" >>>> +#include "llvm/Transforms/Utils/CmpInstAnalysis.h" >>>> #include "llvm/Transforms/Utils/Local.h" >>>> #include "llvm/Constants.h" >>>> #include "llvm/Instructions.h" >>>> @@ -1702,6 +1703,47 @@ >>>> } >>>> } >>>> >>>> + // Treat "if (cond1) { if (cond2) {} }" as "cond1& cond2" and fold. >>>> + // This gives us the value of what cond2 is given cond1 is already known to >>>> + // be true. >>>> + if (ICmpInst *LHS = dyn_cast(PBI->getCondition())) { >>>> + if (ICmpInst *RHS = dyn_cast(BI->getCondition())) { >>>> + ICmpInst::Predicate LHSCC = LHS->getPredicate(), >>>> + RHSCC = RHS->getPredicate(); >>>> + if (PredicatesFoldable(LHSCC, RHSCC)) { >>>> + if (LHS->getOperand(0) == RHS->getOperand(1)&& >>>> + LHS->getOperand(1) == RHS->getOperand(0)) >>>> + LHS->swapOperands(); >>>> + if (LHS->getOperand(0) == RHS->getOperand(0)&& >>>> + LHS->getOperand(1) == RHS->getOperand(1)&& >>>> + BB->getSinglePredecessor()) { >>>> + Value *Op0 = LHS->getOperand(0), *Op1 = LHS->getOperand(1); >>>> + bool CondIsTrue = PBI->getSuccessor(0) == BB; >>>> + unsigned LHSCode = getICmpCode(LHS, !CondIsTrue); >>>> + unsigned RHSCode = getICmpCode(RHS); >>>> + unsigned Code = LHSCode& RHSCode; >>>> + >>>> + Value *ConstantCondition = NULL; >>>> + // If the resultant code is the same as the LHS code then as that >>>> + // code is known to be true we can make RHS now be true. >>>> + if (Code == LHSCode) >>>> + ConstantCondition = ConstantInt::get( >>>> + CmpInst::makeCmpResultType(LHS->getType()), 1); >>>> + else { >>>> + bool isSigned = LHS->isSigned() || RHS->isSigned(); >>>> + CmpInst::Predicate IgnoredNewPred; >>>> + ConstantCondition = getICmpValue(isSigned, Code, Op0, Op1, >>>> + IgnoredNewPred); >>>> + } >>>> + if (ConstantCondition) { >>>> + RHS->replaceAllUsesWith(ConstantCondition); >>>> + return true; >>>> + } >>>> + } >>>> + } >>>> + } >>>> + } >>>> + >>>> // If this is a conditional branch in an empty block, and if any >>>> // predecessors is a conditional branch to one of our destinations, >>>> // fold the conditions into logical ops and one cond br. >>>> >>>> Added: llvm/trunk/test/Transforms/SimplifyCFG/PredictNestedBranch.ll >>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/SimplifyCFG/PredictNestedBranch.ll?rev=146822&view=auto >>>> ============================================================================== >>>> --- llvm/trunk/test/Transforms/SimplifyCFG/PredictNestedBranch.ll (added) >>>> +++ llvm/trunk/test/Transforms/SimplifyCFG/PredictNestedBranch.ll Sat Dec 17 00:32:38 2011 >>>> @@ -0,0 +1,152 @@ >>>> + >>>> +; RUN: opt< %s -simplifycfg -dce -S | FileCheck %s >>>> + >>>> +; Test that when == is true, all 6 comparisons evaluate to true or false >>>> +; ie, a == b implies a> b is false, but a>= b is true, and so on >>>> +define void @testEqTrue(i32 %a, i32 %b) { >>>> +; CHECK: @testEqTrue >>>> +; CHECK: icmp eq i32 %a, %b >>>> +; CHECK: call void @_Z1gi(i32 0) >>>> +; a == b implies a == b >>>> +; CHECK-NEXT: call void @_Z1gi(i32 1) >>>> +; a == b implies a>= b >>>> +; CHECK-NEXT: call void @_Z1gi(i32 3) >>>> +; a == b implies a<= b >>>> +; CHECK-NEXT: call void @_Z1gi(i32 4) >>>> +; CHECK: ret void >>>> +entry: >>>> + %cmp = icmp eq i32 %a, %b >>>> + br i1 %cmp, label %if.then, label %if.end18 >>>> + >>>> +if.then: ; preds = %entry >>>> + call void @_Z1gi(i32 0) >>>> + %cmp1 = icmp eq i32 %a, %b >>>> + br i1 %cmp1, label %if.then2, label %if.end >>>> + >>>> +if.then2: ; preds = %if.then >>>> + call void @_Z1gi(i32 1) >>>> + br label %if.end >>>> + >>>> +if.end: ; preds = %if.then2, %if.then >>>> + %cmp3 = icmp ne i32 %a, %b >>>> + br i1 %cmp3, label %if.then4, label %if.end5 >>>> + >>>> +if.then4: ; preds = %if.end >>>> + call void @_Z1gi(i32 2) >>>> + br label %if.end5 >>>> + >>>> +if.end5: ; preds = %if.then4, %if.end >>>> + %cmp6 = icmp sge i32 %a, %b >>>> + br i1 %cmp6, label %if.then7, label %if.end8 >>>> + >>>> +if.then7: ; preds = %if.end5 >>>> + call void @_Z1gi(i32 3) >>>> + br label %if.end8 >>>> + >>>> +if.end8: ; preds = %if.then7, %if.end5 >>>> + %cmp9 = icmp sle i32 %a, %b >>>> + br i1 %cmp9, label %if.then10, label %if.end11 >>>> + >>>> +if.then10: ; preds = %if.end8 >>>> + call void @_Z1gi(i32 4) >>>> + br label %if.end11 >>>> + >>>> +if.end11: ; preds = %if.then10, %if.end8 >>>> + %cmp12 = icmp sgt i32 %a, %b >>>> + br i1 %cmp12, label %if.then13, label %if.end14 >>>> + >>>> +if.then13: ; preds = %if.end11 >>>> + call void @_Z1gi(i32 5) >>>> + br label %if.end14 >>>> + >>>> +if.end14: ; preds = %if.then13, %if.end11 >>>> + %cmp15 = icmp slt i32 %a, %b >>>> + br i1 %cmp15, label %if.then16, label %if.end18 >>>> + >>>> +if.then16: ; preds = %if.end14 >>>> + call void @_Z1gi(i32 6) >>>> + br label %if.end18 >>>> + >>>> +if.end18: ; preds = %if.end14, %if.then16, %entry >>>> + ret void >>>> +} >>>> + >>>> +; Test that when == is false, all 6 comparisons evaluate to true or false >>>> +; ie, a == b implies a> b is false, but a>= b is true, and so on >>>> +define void @testEqFalse(i32 %a, i32 %b) { >>>> +; CHECK: @testEqFalse >>>> +; CHECK: icmp eq i32 %a, %b >>>> +; CHECK: call void @_Z1gi(i32 0) >>>> +; CHECK-NOT: call void @_Z1gi(i32 1) >>>> +; CHECK-NOT: icmp ne >>>> +; CHECK: call void @_Z1gi(i32 2) >>>> +; CHECK: icmp sge >>>> +; CHECK: call void @_Z1gi(i32 3) >>>> +; CHECK: icmp sle >>>> +; CHECK: call void @_Z1gi(i32 4) >>>> +; CHECK: icmp sgt >>>> +; CHECK: call void @_Z1gi(i32 5) >>>> +; CHECK: icmp slt >>>> +; CHECK: call void @_Z1gi(i32 6) >>>> +; CHECK: ret void >>>> +entry: >>>> + %cmp = icmp eq i32 %a, %b >>>> + br i1 %cmp, label %if.then, label %if.else >>>> + >>>> +if.then: ; preds = %entry >>>> + call void @_Z1gi(i32 0) >>>> + br label %if.end18 >>>> + >>>> +if.else: >>>> + %cmp1 = icmp eq i32 %a, %b >>>> + br i1 %cmp1, label %if.then2, label %if.end >>>> + >>>> +if.then2: ; preds = %if.then >>>> + call void @_Z1gi(i32 1) >>>> + br label %if.end >>>> + >>>> +if.end: ; preds = %if.then2, %if.then >>>> + %cmp3 = icmp ne i32 %a, %b >>>> + br i1 %cmp3, label %if.then4, label %if.end5 >>>> + >>>> +if.then4: ; preds = %if.end >>>> + call void @_Z1gi(i32 2) >>>> + br label %if.end5 >>>> + >>>> +if.end5: ; preds = %if.then4, %if.end >>>> + %cmp6 = icmp sge i32 %a, %b >>>> + br i1 %cmp6, label %if.then7, label %if.end8 >>>> + >>>> +if.then7: ; preds = %if.end5 >>>> + call void @_Z1gi(i32 3) >>>> + br label %if.end8 >>>> + >>>> +if.end8: ; preds = %if.then7, %if.end5 >>>> + %cmp9 = icmp sle i32 %a, %b >>>> + br i1 %cmp9, label %if.then10, label %if.end11 >>>> + >>>> +if.then10: ; preds = %if.end8 >>>> + call void @_Z1gi(i32 4) >>>> + br label %if.end11 >>>> + >>>> +if.end11: ; preds = %if.then10, %if.end8 >>>> + %cmp12 = icmp sgt i32 %a, %b >>>> + br i1 %cmp12, label %if.then13, label %if.end14 >>>> + >>>> +if.then13: ; preds = %if.end11 >>>> + call void @_Z1gi(i32 5) >>>> + br label %if.end14 >>>> + >>>> +if.end14: ; preds = %if.then13, %if.end11 >>>> + %cmp15 = icmp slt i32 %a, %b >>>> + br i1 %cmp15, label %if.then16, label %if.end18 >>>> + >>>> +if.then16: ; preds = %if.end14 >>>> + call void @_Z1gi(i32 6) >>>> + br label %if.end18 >>>> + >>>> +if.end18: ; preds = %if.end14, %if.then16, %entry >>>> + ret void >>>> +} >>>> + >>>> +declare void @_Z1gi(i32) >>>> >>>> >>>> _______________________________________________ >>>> llvm-commits mailing list >>>> llvm-commits at cs.uiuc.edu >>>> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits >>> >>> _______________________________________________ >>> llvm-commits mailing list >>> llvm-commits at cs.uiuc.edu >>> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits >> > > From clattner at apple.com Thu Jan 5 12:27:57 2012 From: clattner at apple.com (Chris Lattner) Date: Thu, 05 Jan 2012 10:27:57 -0800 Subject: [llvm-commits] [LLVM, SwitchInst, case ranges] Auxiliary patch #1 In-Reply-To: <989681325785425@web41.yandex.ru> References: <4EAA9B5D.802@narod.ru> <4EAA9DE8.80000@free.fr> <485181319805488@web67.yandex.ru> <4EAB079D.6000606@free.fr> <4EB18F12.6060409@narod.ru> <4EB7C319.1000709@narod.ru> <4EDE7D75.704@narod.ru> <4EDFD0F4.1040204@narod.ru> <4EE25B61.9070006@narod.ru> <4EE5C06C.3050705@narod.ru> <333531323974498@web57.yandex.ru> <4EEB9C52.1050301@narod.ru> <4EF37B6B.6000205@narod.ru> <4EFA0748.9080702@narod.ru> <4EFCAA6A.20203@narod.ru> <610731325498362@web6.yandex.ru> <200871325616668@web103.yandex.ru> <5633CF27-DD22-4595-A197-DFFCC56B6342@apple.com> <4F058C43.7020908@narod.ru> <6F0FECE5-F12D-4F5E-890B-385AADCB563B@apple.com> <989681325785425@web41.yandex.ru> Message-ID: <9DD2B823-1EC4-4A2B-BF52-73DDC8A6B923@apple.com> Hi Stephan, I'm sorry for being distracted and not getting back to you about this earlier. On Jan 5, 2012, at 9:43 AM, Stepan Dyatkovskiy wrote: > Due to case-ranges feature (PR1255), we want to replace switch cases type: from ConstantInt to APInt. Of course it may be some new type, call it APIntEx. We need "less" comparison for this type, since we need to sort it sometimes. And it also should support initialized property. I think that two this features will be useful for APInt itself. But of course it is possible to create new type. So, your suggestions. APIntEx for case values? Lets discuss the design of this feature before we finalize on an implementation. PR1255 is really about two different things: 1) implementing support for GCC-style case ranges which may make Fortran and Ada support better. 2) making it easier to canonicalize switches in the optimizer, eliminating the critical edge problem. I'm personally mostly interested in #2 :), but I'll admit that it makes things a bit more complex. If we were only interested in solving #1, we'd want to have a [start,end] range value for each edge out of a switch. However, this isn't enough to solve #2, because we'd really like to be able to canonicalize switches that have arbitrarily different values going to the same block (assuming all phi values match). For example, I'd really like to have one CFG edge for: switch (x) case 4: case 17: case 97: just like we should only have one edge for: switch (x) case 4...1000: Doing this would allow simplifycfg to build this canonical form, and reduce some bad cases we get with switches. If you're willing to agree that this is important, then we have to figure out how to represent this. Despite the pushback I gave in PR1255, perhaps representing these things as constants really is the best way to go (but SwitchInst should have good accessors to dig into this). >From a syntax perspective, I think that something like this would make sense (though it would be better if the default label could also be merged into one of the cases): switch i32 %val, label %otherwise [ i32 0, label %onzero i32 4 .. 1000, label %onrange i32 1, i32 1004, i32 4000 ... 5000, label %onstuff ] Given a structure like this, I revise my stance and think that it would be easiest to represent this with a ConstantArray, and maybe even represent the ranges as ConstantVectors or something. What do you think? -Chris From spop at codeaurora.org Thu Jan 5 12:28:46 2012 From: spop at codeaurora.org (Sebastian Pop) Date: Thu, 05 Jan 2012 18:28:46 -0000 Subject: [llvm-commits] [llvm] r147608 - in /llvm/trunk: autoconf/configure.ac cmake/config-ix.cmake configure include/llvm/Config/config.h.cmake include/llvm/Config/config.h.in include/llvm/Config/llvm-config.h.cmake include/llvm/Config/llvm-config.h.in include/llvm/Support/Host.h lib/Support/CommandLine.cpp lib/Support/TargetRegistry.cpp lib/Support/Unix/Host.inc lib/Support/Windows/Host.inc projects/sample/autoconf/configure.ac projects/sample/configure Message-ID: <20120105182846.DAC402A6C12C@llvm.org> Author: spop Date: Thu Jan 5 12:28:46 2012 New Revision: 147608 URL: http://llvm.org/viewvc/llvm-project?rev=147608&view=rev Log: revert r147542 after comments from Joerg Sonnenberger Modified: llvm/trunk/autoconf/configure.ac llvm/trunk/cmake/config-ix.cmake llvm/trunk/configure llvm/trunk/include/llvm/Config/config.h.cmake llvm/trunk/include/llvm/Config/config.h.in llvm/trunk/include/llvm/Config/llvm-config.h.cmake llvm/trunk/include/llvm/Config/llvm-config.h.in llvm/trunk/include/llvm/Support/Host.h llvm/trunk/lib/Support/CommandLine.cpp llvm/trunk/lib/Support/TargetRegistry.cpp llvm/trunk/lib/Support/Unix/Host.inc llvm/trunk/lib/Support/Windows/Host.inc llvm/trunk/projects/sample/autoconf/configure.ac llvm/trunk/projects/sample/configure Modified: llvm/trunk/autoconf/configure.ac URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/autoconf/configure.ac?rev=147608&r1=147607&r2=147608&view=diff ============================================================================== --- llvm/trunk/autoconf/configure.ac (original) +++ llvm/trunk/autoconf/configure.ac Thu Jan 5 12:28:46 2012 @@ -1484,8 +1484,6 @@ [Installation directory for man pages]) AC_DEFINE_UNQUOTED(LLVM_CONFIGTIME, "$LLVM_CONFIGTIME", [Time at which LLVM was configured]) -AC_DEFINE_UNQUOTED(LLVM_HOST_TRIPLE, "$host", - [Host triple LLVM will run on]) AC_DEFINE_UNQUOTED(LLVM_DEFAULT_TARGET_TRIPLE, "$target", [Target triple LLVM will generate code for by default]) Modified: llvm/trunk/cmake/config-ix.cmake URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/cmake/config-ix.cmake?rev=147608&r1=147607&r2=147608&view=diff ============================================================================== --- llvm/trunk/cmake/config-ix.cmake (original) +++ llvm/trunk/cmake/config-ix.cmake Thu Jan 5 12:28:46 2012 @@ -288,16 +288,13 @@ check_cxx_compiler_flag("-Wno-variadic-macros" SUPPORTS_NO_VARIADIC_MACROS_FLAG) include(GetTargetTriple) -get_target_triple(LLVM_HOST_TRIPLE) get_target_triple(LLVM_DEFAULT_TARGET_TRIPLE) -set(HOST_TRIPLE "${LLVM_HOST_TRIPLE}") set(TARGET_TRIPLE "${LLVM_DEFAULT_TARGET_TRIPLE}") # Determine the native architecture. string(TOLOWER "${LLVM_TARGET_ARCH}" LLVM_NATIVE_ARCH) if( LLVM_NATIVE_ARCH STREQUAL "host" ) - string(REGEX MATCH "^[^-]*" LLVM_NATIVE_ARCH ${LLVM_HOST_TRIPLE}) string(REGEX MATCH "^[^-]*" LLVM_NATIVE_ARCH ${LLVM_DEFAULT_TARGET_TRIPLE}) endif () Modified: llvm/trunk/configure URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/configure?rev=147608&r1=147607&r2=147608&view=diff ============================================================================== --- llvm/trunk/configure (original) +++ llvm/trunk/configure Thu Jan 5 12:28:46 2012 @@ -20913,11 +20913,6 @@ cat >>confdefs.h <<_ACEOF -#define LLVM_HOST_TRIPLE "$host" -_ACEOF - - -cat >>confdefs.h <<_ACEOF #define LLVM_DEFAULT_TARGET_TRIPLE "$target" _ACEOF Modified: llvm/trunk/include/llvm/Config/config.h.cmake URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Config/config.h.cmake?rev=147608&r1=147607&r2=147608&view=diff ============================================================================== --- llvm/trunk/include/llvm/Config/config.h.cmake (original) +++ llvm/trunk/include/llvm/Config/config.h.cmake Thu Jan 5 12:28:46 2012 @@ -560,9 +560,6 @@ /* Has gcc/MSVC atomic intrinsics */ #cmakedefine01 LLVM_HAS_ATOMICS -/* Host triple LLVM will run on */ -#cmakedefine LLVM_HOST_TRIPLE "${LLVM_HOST_TRIPLE}" - /* Installation directory for include files */ #cmakedefine LLVM_INCLUDEDIR "${LLVM_INCLUDEDIR}" Modified: llvm/trunk/include/llvm/Config/config.h.in URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Config/config.h.in?rev=147608&r1=147607&r2=147608&view=diff ============================================================================== --- llvm/trunk/include/llvm/Config/config.h.in (original) +++ llvm/trunk/include/llvm/Config/config.h.in Thu Jan 5 12:28:46 2012 @@ -558,9 +558,6 @@ /* Has gcc/MSVC atomic intrinsics */ #undef LLVM_HAS_ATOMICS -/* Host triple LLVM will run on */ -#undef LLVM_HOST_TRIPLE - /* Installation directory for include files */ #undef LLVM_INCLUDEDIR Modified: llvm/trunk/include/llvm/Config/llvm-config.h.cmake URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Config/llvm-config.h.cmake?rev=147608&r1=147607&r2=147608&view=diff ============================================================================== --- llvm/trunk/include/llvm/Config/llvm-config.h.cmake (original) +++ llvm/trunk/include/llvm/Config/llvm-config.h.cmake Thu Jan 5 12:28:46 2012 @@ -40,9 +40,6 @@ /* Has gcc/MSVC atomic intrinsics */ #cmakedefine01 LLVM_HAS_ATOMICS -/* Host triple LLVM will run on */ -#cmakedefine LLVM_HOST_TRIPLE "${LLVM_HOST_TRIPLE}" - /* Installation directory for include files */ #cmakedefine LLVM_INCLUDEDIR "${LLVM_INCLUDEDIR}" Modified: llvm/trunk/include/llvm/Config/llvm-config.h.in URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Config/llvm-config.h.in?rev=147608&r1=147607&r2=147608&view=diff ============================================================================== --- llvm/trunk/include/llvm/Config/llvm-config.h.in (original) +++ llvm/trunk/include/llvm/Config/llvm-config.h.in Thu Jan 5 12:28:46 2012 @@ -40,9 +40,6 @@ /* Has gcc/MSVC atomic intrinsics */ #undef LLVM_HAS_ATOMICS -/* Host triple LLVM will run on */ -#undef LLVM_HOST_TRIPLE - /* Installation directory for include files */ #undef LLVM_INCLUDEDIR Modified: llvm/trunk/include/llvm/Support/Host.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Support/Host.h?rev=147608&r1=147607&r2=147608&view=diff ============================================================================== --- llvm/trunk/include/llvm/Support/Host.h (original) +++ llvm/trunk/include/llvm/Support/Host.h Thu Jan 5 12:28:46 2012 @@ -33,14 +33,6 @@ return !isLittleEndianHost(); } - /// getHostTriple() - Return the host where the compiler will be running. - /// - /// The host triple is a string in the format of: - /// CPU_TYPE-VENDOR-OPERATING_SYSTEM - /// or - /// CPU_TYPE-VENDOR-KERNEL-OPERATING_SYSTEM - std::string getHostTriple(); - /// getDefaultTargetTriple() - Return the default target triple the compiler /// has been configured to produce code for. /// Modified: llvm/trunk/lib/Support/CommandLine.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Support/CommandLine.cpp?rev=147608&r1=147607&r2=147608&view=diff ============================================================================== --- llvm/trunk/lib/Support/CommandLine.cpp (original) +++ llvm/trunk/lib/Support/CommandLine.cpp Thu Jan 5 12:28:46 2012 @@ -1373,7 +1373,6 @@ << " Built " << __DATE__ << " (" << __TIME__ << ").\n" #endif << " Default target: " << sys::getDefaultTargetTriple() << '\n' - << " Host: " << sys::getHostTriple() << '\n' << " Host CPU: " << CPU << '\n'; } void operator=(bool OptionWasSpecified) { Modified: llvm/trunk/lib/Support/TargetRegistry.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Support/TargetRegistry.cpp?rev=147608&r1=147607&r2=147608&view=diff ============================================================================== --- llvm/trunk/lib/Support/TargetRegistry.cpp (original) +++ llvm/trunk/lib/Support/TargetRegistry.cpp Thu Jan 5 12:28:46 2012 @@ -84,7 +84,7 @@ } const Target *TargetRegistry::getClosestTargetForJIT(std::string &Error) { - const Target *TheTarget = lookupTarget(sys::getHostTriple(), Error); + const Target *TheTarget = lookupTarget(sys::getDefaultTargetTriple(), Error); if (TheTarget && !TheTarget->hasJIT()) { Error = "No JIT compatible target available for this host"; Modified: llvm/trunk/lib/Support/Unix/Host.inc URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Support/Unix/Host.inc?rev=147608&r1=147607&r2=147608&view=diff ============================================================================== --- llvm/trunk/lib/Support/Unix/Host.inc (original) +++ llvm/trunk/lib/Support/Unix/Host.inc Thu Jan 5 12:28:46 2012 @@ -35,9 +35,13 @@ return info.release; } -std::string getTriple(StringRef &TripleString) { - std::pair ArchSplit = TripleString.split('-'); +std::string sys::getDefaultTargetTriple() { + StringRef TargetTripleString(LLVM_DEFAULT_TARGET_TRIPLE); + std::pair ArchSplit = TargetTripleString.split('-'); + + // Normalize the arch, since the target triple may not actually match the target. std::string Arch = ArchSplit.first; + std::string Triple(Arch); Triple += '-'; Triple += ArchSplit.second; @@ -57,13 +61,3 @@ return Triple; } - -std::string sys::getDefaultTargetTriple() { - StringRef TargetTripleString(LLVM_DEFAULT_TARGET_TRIPLE); - return getTriple(TargetTripleString); -} - -std::string sys::getHostTriple() { - StringRef HostTripleString(LLVM_HOST_TRIPLE); - return getTriple(HostTripleString); -} Modified: llvm/trunk/lib/Support/Windows/Host.inc URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Support/Windows/Host.inc?rev=147608&r1=147607&r2=147608&view=diff ============================================================================== --- llvm/trunk/lib/Support/Windows/Host.inc (original) +++ llvm/trunk/lib/Support/Windows/Host.inc Thu Jan 5 12:28:46 2012 @@ -20,7 +20,3 @@ std::string sys::getDefaultTargetTriple() { return LLVM_DEFAULT_TARGET_TRIPLE; } - -std::string sys::getHostTriple() { - return LLVM_HOST_TRIPLE; -} Modified: llvm/trunk/projects/sample/autoconf/configure.ac URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/projects/sample/autoconf/configure.ac?rev=147608&r1=147607&r2=147608&view=diff ============================================================================== --- llvm/trunk/projects/sample/autoconf/configure.ac (original) +++ llvm/trunk/projects/sample/autoconf/configure.ac Thu Jan 5 12:28:46 2012 @@ -1390,8 +1390,6 @@ [Installation directory for man pages]) AC_DEFINE_UNQUOTED(LLVM_CONFIGTIME, "$LLVM_CONFIGTIME", [Time at which LLVM was configured]) -AC_DEFINE_UNQUOTED(LLVM_HOST_TRIPLE, "$host", - [Host triple LLVM will run on]) AC_DEFINE_UNQUOTED(LLVM_DEFAULT_TARGET_TRIPLE, "$target", [Target triple LLVM will generate code for by default]) Modified: llvm/trunk/projects/sample/configure URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/projects/sample/configure?rev=147608&r1=147607&r2=147608&view=diff ============================================================================== --- llvm/trunk/projects/sample/configure (original) +++ llvm/trunk/projects/sample/configure Thu Jan 5 12:28:46 2012 @@ -8854,7 +8854,7 @@ shlibpath_var=LD_LIBRARY_PATH ;; -freebsd1.*) +freebsd1*) dynamic_linker=no ;; @@ -8877,7 +8877,7 @@ objformat=`/usr/bin/objformat` else case $host_os in - freebsd[123].*) objformat=aout ;; + freebsd[123]*) objformat=aout ;; *) objformat=elf ;; esac fi @@ -8895,7 +8895,7 @@ esac shlibpath_var=LD_LIBRARY_PATH case $host_os in - freebsd2.*) + freebsd2*) shlibpath_overrides_runpath=yes ;; freebsd3.[01]* | freebsdelf3.[01]*) @@ -10409,7 +10409,7 @@ lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2 lt_status=$lt_dlunknown cat > conftest.$ac_ext <>confdefs.h <<_ACEOF -#define LLVM_HOST_TRIPLE "$host" -_ACEOF - - -cat >>confdefs.h <<_ACEOF #define LLVM_DEFAULT_TARGET_TRIPLE "$target" _ACEOF From clattner at apple.com Thu Jan 5 12:41:03 2012 From: clattner at apple.com (Chris Lattner) Date: Thu, 05 Jan 2012 10:41:03 -0800 Subject: [llvm-commits] [pr11697][patch] Implement linking of symbols with different visibilities In-Reply-To: <4F03BFDB.1000504@gmail.com> References: <4F03BFDB.1000504@gmail.com> Message-ID: On Jan 3, 2012, at 6:56 PM, Rafael ?vila de Esp?ndola wrote: > The LLVM IL linker currently refuses to link symbols if the visibilities > are different. This causes problems when using LTO and > -fvisibility-inlines-hidden. This makes perfect sense to me, please commit! One request: please rename your operator< overload to specific though, instead of abusing "<" :) -Chris > > This patch implements the rules of the System V Application Binary > Interface (http://sco.com/developers/gabi/2009-10-26/ch4.symtab.html), > so that we get consistent behavior with and without LTO. > > This does mean that when using -fvisibility-inlines-hidden, if we have > an explicit template instantiation definition in a library(.so), then > every use of an inline method of that class must see an explicit > template instantiation declaration or we can end up with a hidden symbol > in the library. I think this is OK because: > > * That is already the case when *not* doing LTO and using gold (the gnu > bfd linker is not conformant with the spec). > > * -fvisibility-inlines-hidden already breaks the standard a bit (pointer > comparisons), so saying that it requires explicit template instantiation > declaratios when a definition is used is not too bad. > > * As Eli pointed out on IRC, LTO supersedes -fvisibility-inlines-hidden. > At the IL level we differentiate weak_odr and linkonce_odr. All that we > need is for the link to still work if someone ends up using both LTO and > -fvisibility-inlines-hidden. > > Thanks a lot to Eli and Ian for the comments and pointers. > > Cheers, > Rafael > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From STPWORLD at narod.ru Thu Jan 5 13:17:39 2012 From: STPWORLD at narod.ru (Stepan Dyatkovskiy) Date: Thu, 05 Jan 2012 23:17:39 +0400 Subject: [llvm-commits] [LLVM, SwitchInst, case ranges] Auxiliary patch #1 In-Reply-To: <9DD2B823-1EC4-4A2B-BF52-73DDC8A6B923@apple.com> References: <4EAA9B5D.802@narod.ru> <4EAA9DE8.80000@free.fr> <485181319805488@web67.yandex.ru> <4EAB079D.6000606@free.fr> <4EB18F12.6060409@narod.ru> <4EB7C319.1000709@narod.ru> <4EDE7D75.704@narod.ru> <4EDFD0F4.1040204@narod.ru> <4EE25B61.9070006@narod.ru> <4EE5C06C.3050705@narod.ru> <333531323974498@web57.yandex.ru> <4EEB9C52.1050301@narod.ru> <4EF37B6B.6000205@narod.ru> <4EFA0748.9080702@narod.ru> <4EFCAA6A.20203@narod.ru> <610731325498362@web6.yandex.ru> <200871325616668@web103.yandex.ru> <5633CF27-DD22-4595-A197-DFFCC56B6342@apple.com> <4F058C43.7020908@narod.ru> <6F0FECE5-F12D-4F5E-890B-385AADCB563B@apple.com> <989681325785425@web41.yandex.ru> <9DD2B823-1EC4-4A2B-BF52-73DDC8A6B923@apple.com> Message-ID: <30291325791059@web135.yandex.ru> > If we were only interested in solving #1, we'd want to have a [start,end] range value for each edge out of a switch. ?However, this isn't enough to solve #2... I think solving #2 solves #1 too. After analysing code I saw that it is more profitable to use case-ranges internal representation. > Given a structure like this, I revise my stance and think that it would be easiest to represent this with a ConstantArray, and maybe even represent the ranges as ConstantVectors or something. > > What do you think? I think that ConstantArray is fine. But what the difference for our case between ConstantArray and ConstantVector? Low level implementation? IMHO the main point is that it is inherited from Constant and will stored in LLVMContext. How it will stored in operands collection? -Stepan. From STPWORLD at narod.ru Thu Jan 5 13:30:16 2012 From: STPWORLD at narod.ru (Stepan Dyatkovskiy) Date: Thu, 05 Jan 2012 23:30:16 +0400 Subject: [llvm-commits] Auxiliary patch #1 In-Reply-To: <30291325791059@web135.yandex.ru> References: <4EAA9B5D.802@narod.ru> <4EAA9DE8.80000@free.fr> <485181319805488@web67.yandex.ru> <4EAB079D.6000606@free.fr> <4EB18F12.6060409@narod.ru> <4EB7C319.1000709@narod.ru> <4EDE7D75.704@narod.ru> <4EDFD0F4.1040204@narod.ru> <4EE25B61.9070006@narod.ru> <4EE5C06C.3050705@narod.ru> <333531323974498@web57.yandex.ru> <4EEB9C52.1050301@narod.ru> <4EF37B6B.6000205@narod.ru> <4EFA0748.9080702@narod.ru> <4EFCAA6A.20203@narod.ru> <610731325498362@web6.yandex.ru> <200871325616668@web103.yandex.ru> <5633CF27-DD22-4595-A197-DFFCC56B6342@apple.com> <4F058C43.7020908@narod.ru> <6F0FECE5-F12D-4F5E-890B-385AADCB563B@apple.com> <989681325785425@web41.yandex.ru> <9DD2B823-1EC4-4A2B-BF52-73DDC8A6B923@apple.com> <30291325791059@web135.yandex.ru> Message-ID: <552601325791816@web14.yandex.ru> 05.01.2012, 23:17, "Stepan Dyatkovskiy" : >> ?If we were only interested in solving #1, we'd want to have a [start,end] range value for each edge out of a switch. ?However, this isn't enough to solve #2... > > I think solving #2 solves #1 too. After analysing code I saw that it is more profitable to use case-ranges internal representation. > >> ?Given a structure like this, I revise my stance and think that it would be easiest to represent this with a ConstantArray, and maybe even represent the ranges as ConstantVectors or something. >> >> ?What do you think? > > I think that ConstantArray is fine. But what the difference for our case between ConstantArray and ConstantVector? Low level implementation? IMHO the main point is that it is inherited from Constant and will stored in LLVMContext. How it will stored in operands collection? The last one is not a principle. Here we just should hide getOperand and getSuccessor methods (it is low level methods isn't it?). We should replace code fragments like CaseValue = SI->getOperand(SomeIndex); // We use User methods keeping SwitchInst format in mind. CaseSuccessor = SI->getSuccessor(SomeIndex2); // We use TerminatorInst methods keeping what each successor means in mind. with CaseValue = SI->getCaseValue(SomeCaseValueIndex); Successor = SI->getCaseSuccessor(SomeSuccessorIndex); From jcarter at mips.com Thu Jan 5 13:46:25 2012 From: jcarter at mips.com (Carter, Jack) Date: Thu, 5 Jan 2012 19:46:25 +0000 Subject: [llvm-commits] [Mips] Direct object big endian review and submittal request (Rafael ?vila de Esp?ndola) Message-ID: <86AC779C188FE74F88F6494478B46332E91AA6@exchdb03.mips.com> Rafael, I slipped this in. It doesn't have anything to do with bigendian. It is an existing test case for direct object tls support that checks relocation records. Evidently elf-dump changed to pad out with zeros causing this check to fail. The test case update uses regular expressions to zero or more padded zeros. Jack ********************************************** -; CHECK: ('r_type', 0x2b) -; CHECK: ('r_type', 0x2c) -; CHECK: ('r_type', 0x2d) +; CHECK: ('r_type', 0x{{[0]*}}2b) +; CHECK: ('r_type', 0x{{[0]*}}2c) +; CHECK: ('r_type', 0x{{[0]*}}2d) Why is this needed? The elf-dump script should be printing the value with the correct number of bits (8 on 32 ELF and 32 on 64 bit ELF). Is the script not doing the right thing for big endian ELF files? Cheers, Rafael -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20120105/ff556862/attachment.html From clattner at apple.com Thu Jan 5 14:58:14 2012 From: clattner at apple.com (Chris Lattner) Date: Thu, 05 Jan 2012 12:58:14 -0800 Subject: [llvm-commits] [LLVM, SwitchInst, case ranges] Auxiliary patch #1 In-Reply-To: <30291325791059@web135.yandex.ru> References: <4EAA9B5D.802@narod.ru> <4EAA9DE8.80000@free.fr> <485181319805488@web67.yandex.ru> <4EAB079D.6000606@free.fr> <4EB18F12.6060409@narod.ru> <4EB7C319.1000709@narod.ru> <4EDE7D75.704@narod.ru> <4EDFD0F4.1040204@narod.ru> <4EE25B61.9070006@narod.ru> <4EE5C06C.3050705@narod.ru> <333531323974498@web57.yandex.ru> <4EEB9C52.1050301@narod.ru> <4EF37B6B.6000205@narod.ru> <4EFA0748.9080702@narod.ru> <4EFCAA6A.20203@narod.ru> <610731325498362@web6.yandex.ru> <200871325616668@web103.yandex.ru> <5633CF27-DD22-4595-A197-DFFCC56B6342@apple.com> <4F058C43.7020908@narod.ru> <6F0FECE5-F12D-4F5E-890B-385AADCB563B@apple.com> <989681325785425@web41.yandex.ru> <9DD2B823-1EC4-4A2B-BF52-73DDC8A6B923@apple.com> <30291325791059@web135.yandex.ru> Message-ID: <4DD01E8C-836C-43EA-BDE4-329A223E2EB3@apple.com> On Jan 5, 2012, at 11:17 AM, Stepan Dyatkovskiy wrote: >> If we were only interested in solving #1, we'd want to have a [start,end] range value for each edge out of a switch. However, this isn't enough to solve #2... > I think solving #2 solves #1 too. After analysing code I saw that it is more profitable to use case-ranges internal representation. > >> Given a structure like this, I revise my stance and think that it would be easiest to represent this with a ConstantArray, and maybe even represent the ranges as ConstantVectors or something. >> >> What do you think? > I think that ConstantArray is fine. But what the difference for our case between ConstantArray and ConstantVector? Low level implementation? IMHO the main point is that it is inherited from Constant and will stored in LLVMContext. How it will stored in operands collection? My half-baked thought was that we could store 1, 4...7, 12 as [1, <4, 7>, 12], just to distinguish ranges from pairs of scalar values. > The last one is not a principle. Here we just should hide getOperand and getSuccessor methods (it is low level methods isn't it?). We should replace code fragments like > CaseValue = SI->getOperand(SomeIndex); // We use User methods keeping SwitchInst format in mind. > CaseSuccessor = SI->getSuccessor(SomeIndex2); // We use TerminatorInst methods keeping what each successor means in mind. > with > CaseValue = SI->getCaseValue(SomeCaseValueIndex); > Successor = SI->getCaseSuccessor(SomeSuccessorIndex); I may not be understanding what you mean, but I think that getting rid of getOperand() (hiding it in SwitchInst) makes sense. getSuccessor() still needs to exist though. -Chris From dmalyshev at accesssoftek.com Thu Jan 5 15:16:14 2012 From: dmalyshev at accesssoftek.com (Danil Malyshev) Date: Thu, 05 Jan 2012 21:16:14 -0000 Subject: [llvm-commits] [llvm] r147610 - in /llvm/trunk: include/llvm/ExecutionEngine/ExecutionEngine.h lib/ExecutionEngine/Interpreter/Interpreter.h lib/ExecutionEngine/JIT/JIT.h lib/ExecutionEngine/MCJIT/MCJIT.h Message-ID: <20120105211614.7C8562A6C12C@llvm.org> Author: danil Date: Thu Jan 5 15:16:14 2012 New Revision: 147610 URL: http://llvm.org/viewvc/llvm-project?rev=147610&view=rev Log: A small re-factored JIT/MCJIT::getPointerToNamedFunction(), so it could be called with the base class. Modified: llvm/trunk/include/llvm/ExecutionEngine/ExecutionEngine.h llvm/trunk/lib/ExecutionEngine/Interpreter/Interpreter.h llvm/trunk/lib/ExecutionEngine/JIT/JIT.h llvm/trunk/lib/ExecutionEngine/MCJIT/MCJIT.h Modified: llvm/trunk/include/llvm/ExecutionEngine/ExecutionEngine.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/ExecutionEngine/ExecutionEngine.h?rev=147610&r1=147609&r2=147610&view=diff ============================================================================== --- llvm/trunk/include/llvm/ExecutionEngine/ExecutionEngine.h (original) +++ llvm/trunk/include/llvm/ExecutionEngine/ExecutionEngine.h Thu Jan 5 15:16:14 2012 @@ -228,6 +228,17 @@ virtual GenericValue runFunction(Function *F, const std::vector &ArgValues) = 0; + /// getPointerToNamedFunction - This method returns the address of the + /// specified function by using the dlsym function call. As such it is only + /// useful for resolving library symbols, not code generated symbols. + /// + /// If AbortOnFailure is false and no function with the given name is + /// found, this function silently returns a null pointer. Otherwise, + /// it prints a message to stderr and aborts. + /// + virtual void *getPointerToNamedFunction(const std::string &Name, + bool AbortOnFailure = true) = 0; + /// runStaticConstructorsDestructors - This method is used to execute all of /// the static constructors or destructors for a program. /// Modified: llvm/trunk/lib/ExecutionEngine/Interpreter/Interpreter.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/ExecutionEngine/Interpreter/Interpreter.h?rev=147610&r1=147609&r2=147610&view=diff ============================================================================== --- llvm/trunk/lib/ExecutionEngine/Interpreter/Interpreter.h (original) +++ llvm/trunk/lib/ExecutionEngine/Interpreter/Interpreter.h Thu Jan 5 15:16:14 2012 @@ -115,6 +115,12 @@ virtual GenericValue runFunction(Function *F, const std::vector &ArgValues); + virtual void *getPointerToNamedFunction(const std::string &Name, + bool AbortOnFailure = true) { + // FIXME: not implemented. + return 0; + }; + /// recompileAndRelinkFunction - For the interpreter, functions are always /// up-to-date. /// Modified: llvm/trunk/lib/ExecutionEngine/JIT/JIT.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/ExecutionEngine/JIT/JIT.h?rev=147610&r1=147609&r2=147610&view=diff ============================================================================== --- llvm/trunk/lib/ExecutionEngine/JIT/JIT.h (original) +++ llvm/trunk/lib/ExecutionEngine/JIT/JIT.h Thu Jan 5 15:16:14 2012 @@ -124,8 +124,8 @@ /// found, this function silently returns a null pointer. Otherwise, /// it prints a message to stderr and aborts. /// - void *getPointerToNamedFunction(const std::string &Name, - bool AbortOnFailure = true); + virtual void *getPointerToNamedFunction(const std::string &Name, + bool AbortOnFailure = true); // CompilationCallback - Invoked the first time that a call site is found, // which causes lazy compilation of the target function. Modified: llvm/trunk/lib/ExecutionEngine/MCJIT/MCJIT.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/ExecutionEngine/MCJIT/MCJIT.h?rev=147610&r1=147609&r2=147610&view=diff ============================================================================== --- llvm/trunk/lib/ExecutionEngine/MCJIT/MCJIT.h (original) +++ llvm/trunk/lib/ExecutionEngine/MCJIT/MCJIT.h Thu Jan 5 15:16:14 2012 @@ -65,8 +65,8 @@ /// found, this function silently returns a null pointer. Otherwise, /// it prints a message to stderr and aborts. /// - void *getPointerToNamedFunction(const std::string &Name, - bool AbortOnFailure = true); + virtual void *getPointerToNamedFunction(const std::string &Name, + bool AbortOnFailure = true); /// @} /// @name (Private) Registration Interfaces /// @{ From dmalyshev at accesssoftek.com Thu Jan 5 15:22:06 2012 From: dmalyshev at accesssoftek.com (Danil Malyshev) Date: Thu, 5 Jan 2012 13:22:06 -0800 Subject: [llvm-commits] JIT/MCJIT::getPointerToNamedFunction() In-Reply-To: References: <6AE1604EE3EC5F4296C096518C6B77EE1AA4D191F3@mail.accesssoftek.com> Message-ID: <6AE1604EE3EC5F4296C096518C6B77EE1AA4EA6140@mail.accesssoftek.com> Hello, Thank you, Eric! Committed at 147610. Regards, Danil ________________________________ From: Eric Christopher [mailto:echristo at apple.com] Sent: Thursday, January 05, 2012 12:35 PM To: Danil Malyshev Cc: Commit Messages and Patches for LLVM; Evan Cheng Subject: Re: [llvm-commits] JIT/MCJIT::getPointerToNamedFunction() On Jan 4, 2012, at 11:14 PM, Evan Cheng wrote: Eric, can you review the patch? Yep. :) Please find attached the patch for review. It's a small re-factored JIT/MCJIT::getPointerToNamedFunction(), so it could be called with the base class. Hi Danil, This is fine. Do you need someone to commit it for you? -eric -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20120105/adc6edd4/attachment-0001.html From mcrosier at apple.com Thu Jan 5 15:21:43 2012 From: mcrosier at apple.com (Chad Rosier) Date: Thu, 05 Jan 2012 21:21:43 -0000 Subject: [llvm-commits] [test-suite] r147611 - /test-suite/trunk/External/SPEC/CINT2006/464.h264ref/Makefile Message-ID: <20120105212143.1A1292A6C12C@llvm.org> Author: mcrosier Date: Thu Jan 5 15:21:42 2012 New Revision: 147611 URL: http://llvm.org/viewvc/llvm-project?rev=147611&view=rev Log: Bump 464.h264ref run-time limit. This appears to have failed on our ARMv7 -O0 nightly tester due to exceeding this cap. rdar://10650337 Modified: test-suite/trunk/External/SPEC/CINT2006/464.h264ref/Makefile Modified: test-suite/trunk/External/SPEC/CINT2006/464.h264ref/Makefile URL: http://llvm.org/viewvc/llvm-project/test-suite/trunk/External/SPEC/CINT2006/464.h264ref/Makefile?rev=147611&r1=147610&r2=147611&view=diff ============================================================================== --- test-suite/trunk/External/SPEC/CINT2006/464.h264ref/Makefile (original) +++ test-suite/trunk/External/SPEC/CINT2006/464.h264ref/Makefile Thu Jan 5 15:21:42 2012 @@ -7,7 +7,7 @@ LEVEL = ../../../.. # This test can take more than the default 500s timeout at -O0. -RUNTIMELIMIT:=750 +RUNTIMELIMIT:=850 include ../../Makefile.spec2006 From rafael.espindola at gmail.com Thu Jan 5 16:07:43 2012 From: rafael.espindola at gmail.com (Rafael Espindola) Date: Thu, 05 Jan 2012 22:07:43 -0000 Subject: [llvm-commits] [llvm] r147615 - in /llvm/trunk/lib: CodeGen/CMakeLists.txt CodeGen/ELF.h CodeGen/ELFCodeEmitter.cpp CodeGen/ELFCodeEmitter.h CodeGen/ELFWriter.cpp CodeGen/ELFWriter.h ExecutionEngine/JIT/CMakeLists.txt ExecutionEngine/JIT/JITDebugRegisterer.cpp ExecutionEngine/JIT/JITDebugRegisterer.h ExecutionEngine/JIT/JITEmitter.cpp Message-ID: <20120105220743.A30331BE003@llvm.org> Author: rafael Date: Thu Jan 5 16:07:43 2012 New Revision: 147615 URL: http://llvm.org/viewvc/llvm-project?rev=147615&view=rev Log: Remove the old ELF writer. Removed: llvm/trunk/lib/CodeGen/ELF.h llvm/trunk/lib/CodeGen/ELFCodeEmitter.cpp llvm/trunk/lib/CodeGen/ELFCodeEmitter.h llvm/trunk/lib/CodeGen/ELFWriter.cpp llvm/trunk/lib/CodeGen/ELFWriter.h llvm/trunk/lib/ExecutionEngine/JIT/JITDebugRegisterer.cpp llvm/trunk/lib/ExecutionEngine/JIT/JITDebugRegisterer.h Modified: llvm/trunk/lib/CodeGen/CMakeLists.txt llvm/trunk/lib/ExecutionEngine/JIT/CMakeLists.txt llvm/trunk/lib/ExecutionEngine/JIT/JITEmitter.cpp Modified: llvm/trunk/lib/CodeGen/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/CMakeLists.txt?rev=147615&r1=147614&r2=147615&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/CMakeLists.txt (original) +++ llvm/trunk/lib/CodeGen/CMakeLists.txt Thu Jan 5 16:07:43 2012 @@ -12,8 +12,6 @@ DFAPacketizer.cpp DwarfEHPrepare.cpp EdgeBundles.cpp - ELFCodeEmitter.cpp - ELFWriter.cpp ExecutionDepsFix.cpp ExpandISelPseudos.cpp ExpandPostRAPseudos.cpp Removed: llvm/trunk/lib/CodeGen/ELF.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/ELF.h?rev=147614&view=auto ============================================================================== --- llvm/trunk/lib/CodeGen/ELF.h (original) +++ llvm/trunk/lib/CodeGen/ELF.h (removed) @@ -1,227 +0,0 @@ -//===-- lib/CodeGen/ELF.h - ELF constants and data structures ---*- C++ -*-===// -// -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. -// -//===----------------------------------------------------------------------===// -// -// This header contains common, non-processor-specific data structures and -// constants for the ELF file format. -// -// The details of the ELF32 bits in this file are largely based on the Tool -// Interface Standard (TIS) Executable and Linking Format (ELF) Specification -// Version 1.2, May 1995. The ELF64 is based on HP/Intel definition of the -// ELF-64 object file format document, Version 1.5 Draft 2 May 27, 1998 -// -//===----------------------------------------------------------------------===// - -#ifndef CODEGEN_ELF_H -#define CODEGEN_ELF_H - -#include "llvm/CodeGen/BinaryObject.h" -#include "llvm/CodeGen/MachineRelocation.h" -#include "llvm/Support/ELF.h" -#include "llvm/Support/DataTypes.h" - -namespace llvm { - class GlobalValue; - - /// ELFSym - This struct contains information about each symbol that is - /// added to logical symbol table for the module. This is eventually - /// turned into a real symbol table in the file. - struct ELFSym { - - // ELF symbols are related to llvm ones by being one of the two llvm - // types, for the other ones (section, file, func) a null pointer is - // assumed by default. - union { - const GlobalValue *GV; // If this is a pointer to a GV - const char *Ext; // If this is a pointer to a named symbol - } Source; - - // Describes from which source type this ELF symbol comes from, - // they can be GlobalValue, ExternalSymbol or neither. - enum { - isGV, // The Source.GV field is valid. - isExtSym, // The Source.ExtSym field is valid. - isOther // Not a GlobalValue or External Symbol - }; - unsigned SourceType; - - bool isGlobalValue() const { return SourceType == isGV; } - bool isExternalSym() const { return SourceType == isExtSym; } - - // getGlobalValue - If this is a global value which originated the - // elf symbol, return a reference to it. - const GlobalValue *getGlobalValue() const { - assert(SourceType == isGV && "This is not a global value"); - return Source.GV; - } - - // getExternalSym - If this is an external symbol which originated the - // elf symbol, return a reference to it. - const char *getExternalSymbol() const { - assert(SourceType == isExtSym && "This is not an external symbol"); - return Source.Ext; - } - - // getGV - From a global value return a elf symbol to represent it - static ELFSym *getGV(const GlobalValue *GV, unsigned Bind, - unsigned Type, unsigned Visibility) { - ELFSym *Sym = new ELFSym(); - Sym->Source.GV = GV; - Sym->setBind(Bind); - Sym->setType(Type); - Sym->setVisibility(Visibility); - Sym->SourceType = isGV; - return Sym; - } - - // getExtSym - Create and return an elf symbol to represent an - // external symbol - static ELFSym *getExtSym(const char *Ext) { - ELFSym *Sym = new ELFSym(); - Sym->Source.Ext = Ext; - Sym->setBind(ELF::STB_GLOBAL); - Sym->setType(ELF::STT_NOTYPE); - Sym->setVisibility(ELF::STV_DEFAULT); - Sym->SourceType = isExtSym; - return Sym; - } - - // getSectionSym - Returns a elf symbol to represent an elf section - static ELFSym *getSectionSym() { - ELFSym *Sym = new ELFSym(); - Sym->setBind(ELF::STB_LOCAL); - Sym->setType(ELF::STT_SECTION); - Sym->setVisibility(ELF::STV_DEFAULT); - Sym->SourceType = isOther; - return Sym; - } - - // getFileSym - Returns a elf symbol to represent the module identifier - static ELFSym *getFileSym() { - ELFSym *Sym = new ELFSym(); - Sym->setBind(ELF::STB_LOCAL); - Sym->setType(ELF::STT_FILE); - Sym->setVisibility(ELF::STV_DEFAULT); - Sym->SectionIdx = 0xfff1; // ELFSection::SHN_ABS; - Sym->SourceType = isOther; - return Sym; - } - - // getUndefGV - Returns a STT_NOTYPE symbol - static ELFSym *getUndefGV(const GlobalValue *GV, unsigned Bind) { - ELFSym *Sym = new ELFSym(); - Sym->Source.GV = GV; - Sym->setBind(Bind); - Sym->setType(ELF::STT_NOTYPE); - Sym->setVisibility(ELF::STV_DEFAULT); - Sym->SectionIdx = 0; //ELFSection::SHN_UNDEF; - Sym->SourceType = isGV; - return Sym; - } - - // ELF specific fields - unsigned NameIdx; // Index in .strtab of name, once emitted. - uint64_t Value; - unsigned Size; - uint8_t Info; - uint8_t Other; - unsigned short SectionIdx; - - // Symbol index into the Symbol table - unsigned SymTabIdx; - - ELFSym() : SourceType(isOther), NameIdx(0), Value(0), - Size(0), Info(0), Other(ELF::STV_DEFAULT), SectionIdx(0), - SymTabIdx(0) {} - - unsigned getBind() const { return (Info >> 4) & 0xf; } - unsigned getType() const { return Info & 0xf; } - bool isLocalBind() const { return getBind() == ELF::STB_LOCAL; } - bool isFileType() const { return getType() == ELF::STT_FILE; } - - void setBind(unsigned X) { - assert(X == (X & 0xF) && "Bind value out of range!"); - Info = (Info & 0x0F) | (X << 4); - } - - void setType(unsigned X) { - assert(X == (X & 0xF) && "Type value out of range!"); - Info = (Info & 0xF0) | X; - } - - void setVisibility(unsigned V) { - assert(V == (V & 0x3) && "Visibility value out of range!"); - Other = V; - } - }; - - /// ELFSection - This struct contains information about each section that is - /// emitted to the file. This is eventually turned into the section header - /// table at the end of the file. - class ELFSection : public BinaryObject { - public: - // ELF specific fields - unsigned NameIdx; // sh_name - .shstrtab idx of name, once emitted. - unsigned Type; // sh_type - Section contents & semantics - unsigned Flags; // sh_flags - Section flags. - uint64_t Addr; // sh_addr - The mem addr this section is in. - unsigned Offset; // sh_offset - Offset from the file start - unsigned Size; // sh_size - The section size. - unsigned Link; // sh_link - Section header table index link. - unsigned Info; // sh_info - Auxiliary information. - unsigned Align; // sh_addralign - Alignment of section. - unsigned EntSize; // sh_entsize - Size of entries in the section e - - /// SectionIdx - The number of the section in the Section Table. - unsigned short SectionIdx; - - /// Sym - The symbol to represent this section if it has one. - ELFSym *Sym; - - /// getSymIndex - Returns the symbol table index of the symbol - /// representing this section. - unsigned getSymbolTableIndex() const { - assert(Sym && "section not present in the symbol table"); - return Sym->SymTabIdx; - } - - ELFSection(const std::string &name, bool isLittleEndian, bool is64Bit) - : BinaryObject(name, isLittleEndian, is64Bit), Type(0), Flags(0), Addr(0), - Offset(0), Size(0), Link(0), Info(0), Align(0), EntSize(0), Sym(0) {} - }; - - /// ELFRelocation - This class contains all the information necessary to - /// to generate any 32-bit or 64-bit ELF relocation entry. - class ELFRelocation { - uint64_t r_offset; // offset in the section of the object this applies to - uint32_t r_symidx; // symbol table index of the symbol to use - uint32_t r_type; // machine specific relocation type - int64_t r_add; // explicit relocation addend - bool r_rela; // if true then the addend is part of the entry - // otherwise the addend is at the location specified - // by r_offset - public: - uint64_t getInfo(bool is64Bit) const { - if (is64Bit) - return ((uint64_t)r_symidx << 32) + ((uint64_t)r_type & 0xFFFFFFFFL); - else - return (r_symidx << 8) + (r_type & 0xFFL); - } - - uint64_t getOffset() const { return r_offset; } - int64_t getAddend() const { return r_add; } - - ELFRelocation(uint64_t off, uint32_t sym, uint32_t type, - bool rela = true, int64_t addend = 0) : - r_offset(off), r_symidx(sym), r_type(type), - r_add(addend), r_rela(rela) {} - }; - -} // end namespace llvm - -#endif Removed: llvm/trunk/lib/CodeGen/ELFCodeEmitter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/ELFCodeEmitter.cpp?rev=147614&view=auto ============================================================================== --- llvm/trunk/lib/CodeGen/ELFCodeEmitter.cpp (original) +++ llvm/trunk/lib/CodeGen/ELFCodeEmitter.cpp (removed) @@ -1,205 +0,0 @@ -//===-- lib/CodeGen/ELFCodeEmitter.cpp ------------------------------------===// -// -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. -// -//===----------------------------------------------------------------------===// - -#define DEBUG_TYPE "elfce" - -#include "ELF.h" -#include "ELFWriter.h" -#include "ELFCodeEmitter.h" -#include "llvm/Constants.h" -#include "llvm/DerivedTypes.h" -#include "llvm/Function.h" -#include "llvm/CodeGen/BinaryObject.h" -#include "llvm/CodeGen/MachineConstantPool.h" -#include "llvm/CodeGen/MachineFunction.h" -#include "llvm/CodeGen/MachineJumpTableInfo.h" -#include "llvm/CodeGen/MachineRelocation.h" -#include "llvm/Target/TargetData.h" -#include "llvm/Target/TargetELFWriterInfo.h" -#include "llvm/Target/TargetMachine.h" -#include "llvm/MC/MCAsmInfo.h" -#include "llvm/Support/Debug.h" -#include "llvm/Support/ErrorHandling.h" -#include "llvm/Support/raw_ostream.h" - -//===----------------------------------------------------------------------===// -// ELFCodeEmitter Implementation -//===----------------------------------------------------------------------===// - -namespace llvm { - -/// startFunction - This callback is invoked when a new machine function is -/// about to be emitted. -void ELFCodeEmitter::startFunction(MachineFunction &MF) { - DEBUG(dbgs() << "processing function: " - << MF.getFunction()->getName() << "\n"); - - // Get the ELF Section that this function belongs in. - ES = &EW.getTextSection(MF.getFunction()); - - // Set the desired binary object to be used by the code emitters - setBinaryObject(ES); - - // Get the function alignment in bytes - unsigned Align = (1 << MF.getAlignment()); - - // The function must start on its required alignment - ES->emitAlignment(Align); - - // Update the section alignment if needed. - ES->Align = std::max(ES->Align, Align); - - // Record the function start offset - FnStartOff = ES->getCurrentPCOffset(); - - // Emit constant pool and jump tables to their appropriate sections. - // They need to be emitted before the function because in some targets - // the later may reference JT or CP entry address. - emitConstantPool(MF.getConstantPool()); - if (MF.getJumpTableInfo()) - emitJumpTables(MF.getJumpTableInfo()); -} - -/// finishFunction - This callback is invoked after the function is completely -/// finished. -bool ELFCodeEmitter::finishFunction(MachineFunction &MF) { - // Add a symbol to represent the function. - const Function *F = MF.getFunction(); - ELFSym *FnSym = ELFSym::getGV(F, EW.getGlobalELFBinding(F), ELF::STT_FUNC, - EW.getGlobalELFVisibility(F)); - FnSym->SectionIdx = ES->SectionIdx; - FnSym->Size = ES->getCurrentPCOffset()-FnStartOff; - EW.AddPendingGlobalSymbol(F, true); - - // Offset from start of Section - FnSym->Value = FnStartOff; - - if (!F->hasPrivateLinkage()) - EW.SymbolList.push_back(FnSym); - - // Patch up Jump Table Section relocations to use the real MBBs offsets - // now that the MBB label offsets inside the function are known. - if (MF.getJumpTableInfo()) { - ELFSection &JTSection = EW.getJumpTableSection(); - for (std::vector::iterator MRI = JTRelocations.begin(), - MRE = JTRelocations.end(); MRI != MRE; ++MRI) { - MachineRelocation &MR = *MRI; - uintptr_t MBBOffset = getMachineBasicBlockAddress(MR.getBasicBlock()); - MR.setResultPointer((void*)MBBOffset); - MR.setConstantVal(ES->SectionIdx); - JTSection.addRelocation(MR); - } - } - - // If we have emitted any relocations to function-specific objects such as - // basic blocks, constant pools entries, or jump tables, record their - // addresses now so that we can rewrite them with the correct addresses later - for (unsigned i = 0, e = Relocations.size(); i != e; ++i) { - MachineRelocation &MR = Relocations[i]; - intptr_t Addr; - if (MR.isGlobalValue()) { - EW.AddPendingGlobalSymbol(MR.getGlobalValue()); - } else if (MR.isExternalSymbol()) { - EW.AddPendingExternalSymbol(MR.getExternalSymbol()); - } else if (MR.isBasicBlock()) { - Addr = getMachineBasicBlockAddress(MR.getBasicBlock()); - MR.setConstantVal(ES->SectionIdx); - MR.setResultPointer((void*)Addr); - } else if (MR.isConstantPoolIndex()) { - Addr = getConstantPoolEntryAddress(MR.getConstantPoolIndex()); - MR.setConstantVal(CPSections[MR.getConstantPoolIndex()]); - MR.setResultPointer((void*)Addr); - } else if (MR.isJumpTableIndex()) { - ELFSection &JTSection = EW.getJumpTableSection(); - Addr = getJumpTableEntryAddress(MR.getJumpTableIndex()); - MR.setConstantVal(JTSection.SectionIdx); - MR.setResultPointer((void*)Addr); - } else { - llvm_unreachable("Unhandled relocation type"); - } - ES->addRelocation(MR); - } - - // Clear per-function data structures. - JTRelocations.clear(); - Relocations.clear(); - CPLocations.clear(); - CPSections.clear(); - JTLocations.clear(); - MBBLocations.clear(); - return false; -} - -/// emitConstantPool - For each constant pool entry, figure out which section -/// the constant should live in and emit the constant -void ELFCodeEmitter::emitConstantPool(MachineConstantPool *MCP) { - const std::vector &CP = MCP->getConstants(); - if (CP.empty()) return; - - // TODO: handle PIC codegen - assert(TM.getRelocationModel() != Reloc::PIC_ && - "PIC codegen not yet handled for elf constant pools!"); - - for (unsigned i = 0, e = CP.size(); i != e; ++i) { - MachineConstantPoolEntry CPE = CP[i]; - - // Record the constant pool location and the section index - ELFSection &CstPool = EW.getConstantPoolSection(CPE); - CPLocations.push_back(CstPool.size()); - CPSections.push_back(CstPool.SectionIdx); - - if (CPE.isMachineConstantPoolEntry()) - assert(0 && "CPE.isMachineConstantPoolEntry not supported yet"); - - // Emit the constant to constant pool section - EW.EmitGlobalConstant(CPE.Val.ConstVal, CstPool); - } -} - -/// emitJumpTables - Emit all the jump tables for a given jump table info -/// record to the appropriate section. -void ELFCodeEmitter::emitJumpTables(MachineJumpTableInfo *MJTI) { - const std::vector &JT = MJTI->getJumpTables(); - if (JT.empty()) return; - - // FIXME: handle PIC codegen - assert(TM.getRelocationModel() != Reloc::PIC_ && - "PIC codegen not yet handled for elf jump tables!"); - - const TargetELFWriterInfo *TEW = TM.getELFWriterInfo(); - unsigned EntrySize = 4; //MJTI->getEntrySize(); - - // Get the ELF Section to emit the jump table - ELFSection &JTSection = EW.getJumpTableSection(); - - // For each JT, record its offset from the start of the section - for (unsigned i = 0, e = JT.size(); i != e; ++i) { - const std::vector &MBBs = JT[i].MBBs; - - // Record JT 'i' offset in the JT section - JTLocations.push_back(JTSection.size()); - - // Each MBB entry in the Jump table section has a relocation entry - // against the current text section. - for (unsigned mi = 0, me = MBBs.size(); mi != me; ++mi) { - unsigned MachineRelTy = TEW->getAbsoluteLabelMachineRelTy(); - MachineRelocation MR = - MachineRelocation::getBB(JTSection.size(), MachineRelTy, MBBs[mi]); - - // Add the relocation to the Jump Table section - JTRelocations.push_back(MR); - - // Output placeholder for MBB in the JT section - for (unsigned s=0; s < EntrySize; ++s) - JTSection.emitByte(0); - } - } -} - -} // end namespace llvm Removed: llvm/trunk/lib/CodeGen/ELFCodeEmitter.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/ELFCodeEmitter.h?rev=147614&view=auto ============================================================================== --- llvm/trunk/lib/CodeGen/ELFCodeEmitter.h (original) +++ llvm/trunk/lib/CodeGen/ELFCodeEmitter.h (removed) @@ -1,78 +0,0 @@ -//===-- lib/CodeGen/ELFCodeEmitter.h ----------------------------*- C++ -*-===// -// -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. -// -//===----------------------------------------------------------------------===// - -#ifndef ELFCODEEMITTER_H -#define ELFCODEEMITTER_H - -#include "llvm/CodeGen/ObjectCodeEmitter.h" -#include - -namespace llvm { - class ELFWriter; - class ELFSection; - - /// ELFCodeEmitter - This class is used by the ELFWriter to - /// emit the code for functions to the ELF file. - class ELFCodeEmitter : public ObjectCodeEmitter { - ELFWriter &EW; - - /// Target machine description - TargetMachine &TM; - - /// Section containing code for functions - ELFSection *ES; - - /// Relocations - Record relocations needed by the current function - std::vector Relocations; - - /// JTRelocations - Record relocations needed by the relocation - /// section. - std::vector JTRelocations; - - /// FnStartPtr - Function offset from the beginning of ELFSection 'ES' - uintptr_t FnStartOff; - public: - explicit ELFCodeEmitter(ELFWriter &ew) : EW(ew), TM(EW.TM) {} - - /// addRelocation - Register new relocations for this function - void addRelocation(const MachineRelocation &MR) { - Relocations.push_back(MR); - } - - /// emitConstantPool - For each constant pool entry, figure out which - /// section the constant should live in and emit data to it - void emitConstantPool(MachineConstantPool *MCP); - - /// emitJumpTables - Emit all the jump tables for a given jump table - /// info and record them to the appropriate section. - void emitJumpTables(MachineJumpTableInfo *MJTI); - - void startFunction(MachineFunction &F); - bool finishFunction(MachineFunction &F); - - /// emitLabel - Emits a label - virtual void emitLabel(MCSymbol *Label) { - assert(0 && "emitLabel not implemented"); - } - - /// getLabelAddress - Return the address of the specified LabelID, - /// only usable after the LabelID has been emitted. - virtual uintptr_t getLabelAddress(MCSymbol *Label) const { - assert(0 && "getLabelAddress not implemented"); - return 0; - } - - virtual void setModuleInfo(llvm::MachineModuleInfo* MMI) {} - -}; // end class ELFCodeEmitter - -} // end namespace llvm - -#endif - Removed: llvm/trunk/lib/CodeGen/ELFWriter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/ELFWriter.cpp?rev=147614&view=auto ============================================================================== --- llvm/trunk/lib/CodeGen/ELFWriter.cpp (original) +++ llvm/trunk/lib/CodeGen/ELFWriter.cpp (removed) @@ -1,1105 +0,0 @@ -//===-- ELFWriter.cpp - Target-independent ELF Writer code ----------------===// -// -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. -// -//===----------------------------------------------------------------------===// -// -// This file implements the target-independent ELF writer. This file writes out -// the ELF file in the following order: -// -// #1. ELF Header -// #2. '.text' section -// #3. '.data' section -// #4. '.bss' section (conceptual position in file) -// ... -// #X. '.shstrtab' section -// #Y. Section Table -// -// The entries in the section table are laid out as: -// #0. Null entry [required] -// #1. ".text" entry - the program code -// #2. ".data" entry - global variables with initializers. [ if needed ] -// #3. ".bss" entry - global variables without initializers. [ if needed ] -// ... -// #N. ".shstrtab" entry - String table for the section names. -// -//===----------------------------------------------------------------------===// - -#define DEBUG_TYPE "elfwriter" -#include "ELF.h" -#include "ELFWriter.h" -#include "ELFCodeEmitter.h" -#include "llvm/Constants.h" -#include "llvm/Module.h" -#include "llvm/PassManager.h" -#include "llvm/DerivedTypes.h" -#include "llvm/CodeGen/BinaryObject.h" -#include "llvm/CodeGen/MachineCodeEmitter.h" -#include "llvm/CodeGen/ObjectCodeEmitter.h" -#include "llvm/CodeGen/MachineCodeEmitter.h" -#include "llvm/CodeGen/MachineConstantPool.h" -#include "llvm/MC/MCContext.h" -#include "llvm/MC/MCSectionELF.h" -#include "llvm/MC/MCAsmInfo.h" -#include "llvm/Target/Mangler.h" -#include "llvm/Target/TargetData.h" -#include "llvm/Target/TargetELFWriterInfo.h" -#include "llvm/Target/TargetLowering.h" -#include "llvm/Target/TargetLoweringObjectFile.h" -#include "llvm/Target/TargetMachine.h" -#include "llvm/Target/TargetRegisterInfo.h" -#include "llvm/Support/Debug.h" -#include "llvm/Support/ErrorHandling.h" -#include "llvm/Support/raw_ostream.h" -#include "llvm/ADT/SmallString.h" -using namespace llvm; - -char ELFWriter::ID = 0; - -//===----------------------------------------------------------------------===// -// ELFWriter Implementation -//===----------------------------------------------------------------------===// - -ELFWriter::ELFWriter(raw_ostream &o, TargetMachine &tm) - : MachineFunctionPass(ID), O(o), TM(tm), - OutContext(*new MCContext(*TM.getMCAsmInfo(), *TM.getRegisterInfo(), - &TM.getTargetLowering()->getObjFileLowering())), - TLOF(TM.getTargetLowering()->getObjFileLowering()), - is64Bit(TM.getTargetData()->getPointerSizeInBits() == 64), - isLittleEndian(TM.getTargetData()->isLittleEndian()), - ElfHdr(isLittleEndian, is64Bit) { - - MAI = TM.getMCAsmInfo(); - TEW = TM.getELFWriterInfo(); - - // Create the object code emitter object for this target. - ElfCE = new ELFCodeEmitter(*this); - - // Initial number of sections - NumSections = 0; -} - -ELFWriter::~ELFWriter() { - delete ElfCE; - delete &OutContext; - - while(!SymbolList.empty()) { - delete SymbolList.back(); - SymbolList.pop_back(); - } - - while(!PrivateSyms.empty()) { - delete PrivateSyms.back(); - PrivateSyms.pop_back(); - } - - while(!SectionList.empty()) { - delete SectionList.back(); - SectionList.pop_back(); - } - - // Release the name mangler object. - delete Mang; Mang = 0; -} - -// doInitialization - Emit the file header and all of the global variables for -// the module to the ELF file. -bool ELFWriter::doInitialization(Module &M) { - // Initialize TargetLoweringObjectFile. - const_cast(TLOF).Initialize(OutContext, TM); - - Mang = new Mangler(OutContext, *TM.getTargetData()); - - // ELF Header - // ---------- - // Fields e_shnum e_shstrndx are only known after all section have - // been emitted. They locations in the ouput buffer are recorded so - // to be patched up later. - // - // Note - // ---- - // emitWord method behaves differently for ELF32 and ELF64, writing - // 4 bytes in the former and 8 in the last for *_off and *_addr elf types - - ElfHdr.emitByte(0x7f); // e_ident[EI_MAG0] - ElfHdr.emitByte('E'); // e_ident[EI_MAG1] - ElfHdr.emitByte('L'); // e_ident[EI_MAG2] - ElfHdr.emitByte('F'); // e_ident[EI_MAG3] - - ElfHdr.emitByte(TEW->getEIClass()); // e_ident[EI_CLASS] - ElfHdr.emitByte(TEW->getEIData()); // e_ident[EI_DATA] - ElfHdr.emitByte(ELF::EV_CURRENT); // e_ident[EI_VERSION] - ElfHdr.emitAlignment(16); // e_ident[EI_NIDENT-EI_PAD] - - ElfHdr.emitWord16(ELF::ET_REL); // e_type - ElfHdr.emitWord16(TEW->getEMachine()); // e_machine = target - ElfHdr.emitWord32(ELF::EV_CURRENT); // e_version - ElfHdr.emitWord(0); // e_entry, no entry point in .o file - ElfHdr.emitWord(0); // e_phoff, no program header for .o - ELFHdr_e_shoff_Offset = ElfHdr.size(); - ElfHdr.emitWord(0); // e_shoff = sec hdr table off in bytes - ElfHdr.emitWord32(TEW->getEFlags()); // e_flags = whatever the target wants - ElfHdr.emitWord16(TEW->getHdrSize()); // e_ehsize = ELF header size - ElfHdr.emitWord16(0); // e_phentsize = prog header entry size - ElfHdr.emitWord16(0); // e_phnum = # prog header entries = 0 - - // e_shentsize = Section header entry size - ElfHdr.emitWord16(TEW->getSHdrSize()); - - // e_shnum = # of section header ents - ELFHdr_e_shnum_Offset = ElfHdr.size(); - ElfHdr.emitWord16(0); // Placeholder - - // e_shstrndx = Section # of '.shstrtab' - ELFHdr_e_shstrndx_Offset = ElfHdr.size(); - ElfHdr.emitWord16(0); // Placeholder - - // Add the null section, which is required to be first in the file. - getNullSection(); - - // The first entry in the symtab is the null symbol and the second - // is a local symbol containing the module/file name - SymbolList.push_back(new ELFSym()); - SymbolList.push_back(ELFSym::getFileSym()); - - return false; -} - -// AddPendingGlobalSymbol - Add a global to be processed and to -// the global symbol lookup, use a zero index because the table -// index will be determined later. -void ELFWriter::AddPendingGlobalSymbol(const GlobalValue *GV, - bool AddToLookup /* = false */) { - PendingGlobals.insert(GV); - if (AddToLookup) - GblSymLookup[GV] = 0; -} - -// AddPendingExternalSymbol - Add the external to be processed -// and to the external symbol lookup, use a zero index because -// the symbol table index will be determined later. -void ELFWriter::AddPendingExternalSymbol(const char *External) { - PendingExternals.insert(External); - ExtSymLookup[External] = 0; -} - -ELFSection &ELFWriter::getDataSection() { - const MCSectionELF *Data = (const MCSectionELF *)TLOF.getDataSection(); - return getSection(Data->getSectionName(), Data->getType(), - Data->getFlags(), 4); -} - -ELFSection &ELFWriter::getBSSSection() { - const MCSectionELF *BSS = (const MCSectionELF *)TLOF.getBSSSection(); - return getSection(BSS->getSectionName(), BSS->getType(), BSS->getFlags(), 4); -} - -// getCtorSection - Get the static constructor section -ELFSection &ELFWriter::getCtorSection() { - const MCSectionELF *Ctor = (const MCSectionELF *)TLOF.getStaticCtorSection(); - return getSection(Ctor->getSectionName(), Ctor->getType(), Ctor->getFlags()); -} - -// getDtorSection - Get the static destructor section -ELFSection &ELFWriter::getDtorSection() { - const MCSectionELF *Dtor = (const MCSectionELF *)TLOF.getStaticDtorSection(); - return getSection(Dtor->getSectionName(), Dtor->getType(), Dtor->getFlags()); -} - -// getTextSection - Get the text section for the specified function -ELFSection &ELFWriter::getTextSection(const Function *F) { - const MCSectionELF *Text = - (const MCSectionELF *)TLOF.SectionForGlobal(F, Mang, TM); - return getSection(Text->getSectionName(), Text->getType(), Text->getFlags()); -} - -// getJumpTableSection - Get a read only section for constants when -// emitting jump tables. TODO: add PIC support -ELFSection &ELFWriter::getJumpTableSection() { - const MCSectionELF *JT = - (const MCSectionELF *)TLOF.getSectionForConstant(SectionKind::getReadOnly()); - return getSection(JT->getSectionName(), JT->getType(), JT->getFlags(), - TM.getTargetData()->getPointerABIAlignment()); -} - -// getConstantPoolSection - Get a constant pool section based on the machine -// constant pool entry type and relocation info. -ELFSection &ELFWriter::getConstantPoolSection(MachineConstantPoolEntry &CPE) { - SectionKind Kind; - switch (CPE.getRelocationInfo()) { - default: llvm_unreachable("Unknown section kind"); - case 2: Kind = SectionKind::getReadOnlyWithRel(); break; - case 1: - Kind = SectionKind::getReadOnlyWithRelLocal(); - break; - case 0: - switch (TM.getTargetData()->getTypeAllocSize(CPE.getType())) { - case 4: Kind = SectionKind::getMergeableConst4(); break; - case 8: Kind = SectionKind::getMergeableConst8(); break; - case 16: Kind = SectionKind::getMergeableConst16(); break; - default: Kind = SectionKind::getMergeableConst(); break; - } - } - - const MCSectionELF *CPSect = - (const MCSectionELF *)TLOF.getSectionForConstant(Kind); - return getSection(CPSect->getSectionName(), CPSect->getType(), - CPSect->getFlags(), CPE.getAlignment()); -} - -// getRelocSection - Return the relocation section of section 'S'. 'RelA' -// is true if the relocation section contains entries with addends. -ELFSection &ELFWriter::getRelocSection(ELFSection &S) { - unsigned SectionType = TEW->hasRelocationAddend() ? - ELF::SHT_RELA : ELF::SHT_REL; - - std::string SectionName(".rel"); - if (TEW->hasRelocationAddend()) - SectionName.append("a"); - SectionName.append(S.getName()); - - return getSection(SectionName, SectionType, 0, TEW->getPrefELFAlignment()); -} - -// getGlobalELFVisibility - Returns the ELF specific visibility type -unsigned ELFWriter::getGlobalELFVisibility(const GlobalValue *GV) { - switch (GV->getVisibility()) { - default: - llvm_unreachable("unknown visibility type"); - case GlobalValue::DefaultVisibility: - return ELF::STV_DEFAULT; - case GlobalValue::HiddenVisibility: - return ELF::STV_HIDDEN; - case GlobalValue::ProtectedVisibility: - return ELF::STV_PROTECTED; - } - return 0; -} - -// getGlobalELFBinding - Returns the ELF specific binding type -unsigned ELFWriter::getGlobalELFBinding(const GlobalValue *GV) { - if (GV->hasInternalLinkage()) - return ELF::STB_LOCAL; - - if (GV->isWeakForLinker() && !GV->hasCommonLinkage()) - return ELF::STB_WEAK; - - return ELF::STB_GLOBAL; -} - -// getGlobalELFType - Returns the ELF specific type for a global -unsigned ELFWriter::getGlobalELFType(const GlobalValue *GV) { - if (GV->isDeclaration()) - return ELF::STT_NOTYPE; - - if (isa(GV)) - return ELF::STT_FUNC; - - return ELF::STT_OBJECT; -} - -// IsELFUndefSym - True if the global value must be marked as a symbol -// which points to a SHN_UNDEF section. This means that the symbol has -// no definition on the module. -static bool IsELFUndefSym(const GlobalValue *GV) { - return GV->isDeclaration() || (isa(GV)); -} - -// AddToSymbolList - Update the symbol lookup and If the symbol is -// private add it to PrivateSyms list, otherwise to SymbolList. -void ELFWriter::AddToSymbolList(ELFSym *GblSym) { - assert(GblSym->isGlobalValue() && "Symbol must be a global value"); - - const GlobalValue *GV = GblSym->getGlobalValue(); - if (GV->hasPrivateLinkage()) { - // For a private symbols, keep track of the index inside - // the private list since it will never go to the symbol - // table and won't be patched up later. - PrivateSyms.push_back(GblSym); - GblSymLookup[GV] = PrivateSyms.size()-1; - } else { - // Non private symbol are left with zero indices until - // they are patched up during the symbol table emition - // (where the indicies are created). - SymbolList.push_back(GblSym); - GblSymLookup[GV] = 0; - } -} - -/// HasCommonSymbols - True if this section holds common symbols, this is -/// indicated on the ELF object file by a symbol with SHN_COMMON section -/// header index. -static bool HasCommonSymbols(const MCSectionELF &S) { - // FIXME: this is wrong, a common symbol can be in .data for example. - if (StringRef(S.getSectionName()).startswith(".gnu.linkonce.")) - return true; - - return false; -} - - -// EmitGlobal - Choose the right section for global and emit it -void ELFWriter::EmitGlobal(const GlobalValue *GV) { - - // Check if the referenced symbol is already emitted - if (GblSymLookup.find(GV) != GblSymLookup.end()) - return; - - // Handle ELF Bind, Visibility and Type for the current symbol - unsigned SymBind = getGlobalELFBinding(GV); - unsigned SymType = getGlobalELFType(GV); - bool IsUndefSym = IsELFUndefSym(GV); - - ELFSym *GblSym = IsUndefSym ? ELFSym::getUndefGV(GV, SymBind) - : ELFSym::getGV(GV, SymBind, SymType, getGlobalELFVisibility(GV)); - - if (!IsUndefSym) { - assert(isa(GV) && "GV not a global variable!"); - const GlobalVariable *GVar = dyn_cast(GV); - - // Handle special llvm globals - if (EmitSpecialLLVMGlobal(GVar)) - return; - - // Get the ELF section where this global belongs from TLOF - const MCSectionELF *S = - (const MCSectionELF *)TLOF.SectionForGlobal(GV, Mang, TM); - ELFSection &ES = - getSection(S->getSectionName(), S->getType(), S->getFlags()); - SectionKind Kind = S->getKind(); - - // The symbol align should update the section alignment if needed - const TargetData *TD = TM.getTargetData(); - unsigned Align = TD->getPreferredAlignment(GVar); - unsigned Size = TD->getTypeAllocSize(GVar->getInitializer()->getType()); - GblSym->Size = Size; - - if (HasCommonSymbols(*S)) { // Symbol must go to a common section - GblSym->SectionIdx = ELF::SHN_COMMON; - - // A new linkonce section is created for each global in the - // common section, the default alignment is 1 and the symbol - // value contains its alignment. - ES.Align = 1; - GblSym->Value = Align; - - } else if (Kind.isBSS() || Kind.isThreadBSS()) { // Symbol goes to BSS. - GblSym->SectionIdx = ES.SectionIdx; - - // Update the size with alignment and the next object can - // start in the right offset in the section - if (Align) ES.Size = (ES.Size + Align-1) & ~(Align-1); - ES.Align = std::max(ES.Align, Align); - - // GblSym->Value should contain the virtual offset inside the section. - // Virtual because the BSS space is not allocated on ELF objects - GblSym->Value = ES.Size; - ES.Size += Size; - - } else { // The symbol must go to some kind of data section - GblSym->SectionIdx = ES.SectionIdx; - - // GblSym->Value should contain the symbol offset inside the section, - // and all symbols should start on their required alignment boundary - ES.Align = std::max(ES.Align, Align); - ES.emitAlignment(Align); - GblSym->Value = ES.size(); - - // Emit the global to the data section 'ES' - EmitGlobalConstant(GVar->getInitializer(), ES); - } - } - - AddToSymbolList(GblSym); -} - -void ELFWriter::EmitGlobalConstantStruct(const ConstantStruct *CVS, - ELFSection &GblS) { - - // Print the fields in successive locations. Pad to align if needed! - const TargetData *TD = TM.getTargetData(); - unsigned Size = TD->getTypeAllocSize(CVS->getType()); - const StructLayout *cvsLayout = TD->getStructLayout(CVS->getType()); - uint64_t sizeSoFar = 0; - for (unsigned i = 0, e = CVS->getNumOperands(); i != e; ++i) { - const Constant* field = CVS->getOperand(i); - - // Check if padding is needed and insert one or more 0s. - uint64_t fieldSize = TD->getTypeAllocSize(field->getType()); - uint64_t padSize = ((i == e-1 ? Size : cvsLayout->getElementOffset(i+1)) - - cvsLayout->getElementOffset(i)) - fieldSize; - sizeSoFar += fieldSize + padSize; - - // Now print the actual field value. - EmitGlobalConstant(field, GblS); - - // Insert padding - this may include padding to increase the size of the - // current field up to the ABI size (if the struct is not packed) as well - // as padding to ensure that the next field starts at the right offset. - GblS.emitZeros(padSize); - } - assert(sizeSoFar == cvsLayout->getSizeInBytes() && - "Layout of constant struct may be incorrect!"); -} - -void ELFWriter::EmitGlobalConstant(const Constant *CV, ELFSection &GblS) { - const TargetData *TD = TM.getTargetData(); - unsigned Size = TD->getTypeAllocSize(CV->getType()); - - if (const ConstantArray *CVA = dyn_cast(CV)) { - for (unsigned i = 0, e = CVA->getNumOperands(); i != e; ++i) - EmitGlobalConstant(CVA->getOperand(i), GblS); - return; - } else if (isa(CV)) { - GblS.emitZeros(Size); - return; - } else if (const ConstantStruct *CVS = dyn_cast(CV)) { - EmitGlobalConstantStruct(CVS, GblS); - return; - } else if (const ConstantFP *CFP = dyn_cast(CV)) { - APInt Val = CFP->getValueAPF().bitcastToAPInt(); - if (CFP->getType()->isDoubleTy()) - GblS.emitWord64(Val.getZExtValue()); - else if (CFP->getType()->isFloatTy()) - GblS.emitWord32(Val.getZExtValue()); - else if (CFP->getType()->isX86_FP80Ty()) { - unsigned PadSize = TD->getTypeAllocSize(CFP->getType())- - TD->getTypeStoreSize(CFP->getType()); - GblS.emitWordFP80(Val.getRawData(), PadSize); - } else if (CFP->getType()->isPPC_FP128Ty()) - llvm_unreachable("PPC_FP128Ty global emission not implemented"); - return; - } else if (const ConstantInt *CI = dyn_cast(CV)) { - if (Size == 1) - GblS.emitByte(CI->getZExtValue()); - else if (Size == 2) - GblS.emitWord16(CI->getZExtValue()); - else if (Size == 4) - GblS.emitWord32(CI->getZExtValue()); - else - EmitGlobalConstantLargeInt(CI, GblS); - return; - } else if (const ConstantVector *CP = dyn_cast(CV)) { - VectorType *PTy = CP->getType(); - for (unsigned I = 0, E = PTy->getNumElements(); I < E; ++I) - EmitGlobalConstant(CP->getOperand(I), GblS); - return; - } else if (const ConstantExpr *CE = dyn_cast(CV)) { - // Resolve a constant expression which returns a (Constant, Offset) - // pair. If 'Res.first' is a GlobalValue, emit a relocation with - // the offset 'Res.second', otherwise emit a global constant like - // it is always done for not contant expression types. - CstExprResTy Res = ResolveConstantExpr(CE); - const Constant *Op = Res.first; - - if (isa(Op)) - EmitGlobalDataRelocation(cast(Op), - TD->getTypeAllocSize(Op->getType()), - GblS, Res.second); - else - EmitGlobalConstant(Op, GblS); - - return; - } else if (CV->getType()->getTypeID() == Type::PointerTyID) { - // Fill the data entry with zeros or emit a relocation entry - if (isa(CV)) - GblS.emitZeros(Size); - else - EmitGlobalDataRelocation(cast(CV), - Size, GblS); - return; - } else if (const GlobalValue *GV = dyn_cast(CV)) { - // This is a constant address for a global variable or function and - // therefore must be referenced using a relocation entry. - EmitGlobalDataRelocation(GV, Size, GblS); - return; - } - - std::string msg; - raw_string_ostream ErrorMsg(msg); - ErrorMsg << "Constant unimp for type: " << *CV->getType(); - report_fatal_error(ErrorMsg.str()); -} - -// ResolveConstantExpr - Resolve the constant expression until it stop -// yielding other constant expressions. -CstExprResTy ELFWriter::ResolveConstantExpr(const Constant *CV) { - const TargetData *TD = TM.getTargetData(); - - // There ins't constant expression inside others anymore - if (!isa(CV)) - return std::make_pair(CV, 0); - - const ConstantExpr *CE = dyn_cast(CV); - switch (CE->getOpcode()) { - case Instruction::BitCast: - return ResolveConstantExpr(CE->getOperand(0)); - - case Instruction::GetElementPtr: { - const Constant *ptrVal = CE->getOperand(0); - SmallVector idxVec(CE->op_begin()+1, CE->op_end()); - int64_t Offset = TD->getIndexedOffset(ptrVal->getType(), idxVec); - return std::make_pair(ptrVal, Offset); - } - case Instruction::IntToPtr: { - Constant *Op = CE->getOperand(0); - Op = ConstantExpr::getIntegerCast(Op, TD->getIntPtrType(CV->getContext()), - false/*ZExt*/); - return ResolveConstantExpr(Op); - } - case Instruction::PtrToInt: { - Constant *Op = CE->getOperand(0); - Type *Ty = CE->getType(); - - // We can emit the pointer value into this slot if the slot is an - // integer slot greater or equal to the size of the pointer. - if (TD->getTypeAllocSize(Ty) == TD->getTypeAllocSize(Op->getType())) - return ResolveConstantExpr(Op); - - llvm_unreachable("Integer size less then pointer size"); - } - case Instruction::Add: - case Instruction::Sub: { - // Only handle cases where there's a constant expression with GlobalValue - // as first operand and ConstantInt as second, which are the cases we can - // solve direclty using a relocation entry. GlobalValue=Op0, CstInt=Op1 - // 1) Instruction::Add => (global) + CstInt - // 2) Instruction::Sub => (global) + -CstInt - const Constant *Op0 = CE->getOperand(0); - const Constant *Op1 = CE->getOperand(1); - assert(isa(Op1) && "Op1 must be a ConstantInt"); - - CstExprResTy Res = ResolveConstantExpr(Op0); - assert(isa(Res.first) && "Op0 must be a GlobalValue"); - - const APInt &RHS = cast(Op1)->getValue(); - switch (CE->getOpcode()) { - case Instruction::Add: - return std::make_pair(Res.first, RHS.getSExtValue()); - case Instruction::Sub: - return std::make_pair(Res.first, (-RHS).getSExtValue()); - } - } - } - - report_fatal_error(CE->getOpcodeName() + - StringRef(": Unsupported ConstantExpr type")); - - return std::make_pair(CV, 0); // silence warning -} - -void ELFWriter::EmitGlobalDataRelocation(const GlobalValue *GV, unsigned Size, - ELFSection &GblS, int64_t Offset) { - // Create the relocation entry for the global value - MachineRelocation MR = - MachineRelocation::getGV(GblS.getCurrentPCOffset(), - TEW->getAbsoluteLabelMachineRelTy(), - const_cast(GV), - Offset); - - // Fill the data entry with zeros - GblS.emitZeros(Size); - - // Add the relocation entry for the current data section - GblS.addRelocation(MR); -} - -void ELFWriter::EmitGlobalConstantLargeInt(const ConstantInt *CI, - ELFSection &S) { - const TargetData *TD = TM.getTargetData(); - unsigned BitWidth = CI->getBitWidth(); - assert(isPowerOf2_32(BitWidth) && - "Non-power-of-2-sized integers not handled!"); - - const uint64_t *RawData = CI->getValue().getRawData(); - uint64_t Val = 0; - for (unsigned i = 0, e = BitWidth / 64; i != e; ++i) { - Val = (TD->isBigEndian()) ? RawData[e - i - 1] : RawData[i]; - S.emitWord64(Val); - } -} - -/// EmitSpecialLLVMGlobal - Check to see if the specified global is a -/// special global used by LLVM. If so, emit it and return true, otherwise -/// do nothing and return false. -bool ELFWriter::EmitSpecialLLVMGlobal(const GlobalVariable *GV) { - if (GV->getName() == "llvm.used") - llvm_unreachable("not implemented yet"); - - // Ignore debug and non-emitted data. This handles llvm.compiler.used. - if (GV->getSection() == "llvm.metadata" || - GV->hasAvailableExternallyLinkage()) - return true; - - if (!GV->hasAppendingLinkage()) return false; - - assert(GV->hasInitializer() && "Not a special LLVM global!"); - - const TargetData *TD = TM.getTargetData(); - unsigned Align = TD->getPointerPrefAlignment(); - if (GV->getName() == "llvm.global_ctors") { - ELFSection &Ctor = getCtorSection(); - Ctor.emitAlignment(Align); - EmitXXStructorList(GV->getInitializer(), Ctor); - return true; - } - - if (GV->getName() == "llvm.global_dtors") { - ELFSection &Dtor = getDtorSection(); - Dtor.emitAlignment(Align); - EmitXXStructorList(GV->getInitializer(), Dtor); - return true; - } - - return false; -} - -/// EmitXXStructorList - Emit the ctor or dtor list. This just emits out the -/// function pointers, ignoring the init priority. -void ELFWriter::EmitXXStructorList(const Constant *List, ELFSection &Xtor) { - // Should be an array of '{ i32, void ()* }' structs. The first value is the - // init priority, which we ignore. - if (List->isNullValue()) return; - const ConstantArray *InitList = cast(List); - for (unsigned i = 0, e = InitList->getNumOperands(); i != e; ++i) { - if (InitList->getOperand(i)->isNullValue()) - continue; - ConstantStruct *CS = cast(InitList->getOperand(i)); - - if (CS->getOperand(1)->isNullValue()) - continue; - - // Emit the function pointer. - EmitGlobalConstant(CS->getOperand(1), Xtor); - } -} - -bool ELFWriter::runOnMachineFunction(MachineFunction &MF) { - // Nothing to do here, this is all done through the ElfCE object above. - return false; -} - -/// doFinalization - Now that the module has been completely processed, emit -/// the ELF file to 'O'. -bool ELFWriter::doFinalization(Module &M) { - // Emit .data section placeholder - getDataSection(); - - // Emit .bss section placeholder - getBSSSection(); - - // Build and emit data, bss and "common" sections. - for (Module::global_iterator I = M.global_begin(), E = M.global_end(); - I != E; ++I) - EmitGlobal(I); - - // Emit all pending globals - for (PendingGblsIter I = PendingGlobals.begin(), E = PendingGlobals.end(); - I != E; ++I) - EmitGlobal(*I); - - // Emit all pending externals - for (PendingExtsIter I = PendingExternals.begin(), E = PendingExternals.end(); - I != E; ++I) - SymbolList.push_back(ELFSym::getExtSym(*I)); - - // Emit a symbol for each section created until now, skip null section - for (unsigned i = 1, e = SectionList.size(); i < e; ++i) { - ELFSection &ES = *SectionList[i]; - ELFSym *SectionSym = ELFSym::getSectionSym(); - SectionSym->SectionIdx = ES.SectionIdx; - SymbolList.push_back(SectionSym); - ES.Sym = SymbolList.back(); - } - - // Emit string table - EmitStringTable(M.getModuleIdentifier()); - - // Emit the symbol table now, if non-empty. - EmitSymbolTable(); - - // Emit the relocation sections. - EmitRelocations(); - - // Emit the sections string table. - EmitSectionTableStringTable(); - - // Dump the sections and section table to the .o file. - OutputSectionsAndSectionTable(); - - return false; -} - -// RelocateField - Patch relocatable field with 'Offset' in 'BO' -// using a 'Value' of known 'Size' -void ELFWriter::RelocateField(BinaryObject &BO, uint32_t Offset, - int64_t Value, unsigned Size) { - if (Size == 32) - BO.fixWord32(Value, Offset); - else if (Size == 64) - BO.fixWord64(Value, Offset); - else - llvm_unreachable("don't know howto patch relocatable field"); -} - -/// EmitRelocations - Emit relocations -void ELFWriter::EmitRelocations() { - - // True if the target uses the relocation entry to hold the addend, - // otherwise the addend is written directly to the relocatable field. - bool HasRelA = TEW->hasRelocationAddend(); - - // Create Relocation sections for each section which needs it. - for (unsigned i=0, e=SectionList.size(); i != e; ++i) { - ELFSection &S = *SectionList[i]; - - // This section does not have relocations - if (!S.hasRelocations()) continue; - ELFSection &RelSec = getRelocSection(S); - - // 'Link' - Section hdr idx of the associated symbol table - // 'Info' - Section hdr idx of the section to which the relocation applies - ELFSection &SymTab = getSymbolTableSection(); - RelSec.Link = SymTab.SectionIdx; - RelSec.Info = S.SectionIdx; - RelSec.EntSize = TEW->getRelocationEntrySize(); - - // Get the relocations from Section - std::vector Relos = S.getRelocations(); - for (std::vector::iterator MRI = Relos.begin(), - MRE = Relos.end(); MRI != MRE; ++MRI) { - MachineRelocation &MR = *MRI; - - // Relocatable field offset from the section start - unsigned RelOffset = MR.getMachineCodeOffset(); - - // Symbol index in the symbol table - unsigned SymIdx = 0; - - // Target specific relocation field type and size - unsigned RelType = TEW->getRelocationType(MR.getRelocationType()); - unsigned RelTySize = TEW->getRelocationTySize(RelType); - int64_t Addend = 0; - - // There are several machine relocations types, and each one of - // them needs a different approach to retrieve the symbol table index. - if (MR.isGlobalValue()) { - const GlobalValue *G = MR.getGlobalValue(); - int64_t GlobalOffset = MR.getConstantVal(); - SymIdx = GblSymLookup[G]; - if (G->hasPrivateLinkage()) { - // If the target uses a section offset in the relocation: - // SymIdx + Addend = section sym for global + section offset - unsigned SectionIdx = PrivateSyms[SymIdx]->SectionIdx; - Addend = PrivateSyms[SymIdx]->Value + GlobalOffset; - SymIdx = SectionList[SectionIdx]->getSymbolTableIndex(); - } else { - Addend = TEW->getDefaultAddendForRelTy(RelType, GlobalOffset); - } - } else if (MR.isExternalSymbol()) { - const char *ExtSym = MR.getExternalSymbol(); - SymIdx = ExtSymLookup[ExtSym]; - Addend = TEW->getDefaultAddendForRelTy(RelType); - } else { - // Get the symbol index for the section symbol - unsigned SectionIdx = MR.getConstantVal(); - SymIdx = SectionList[SectionIdx]->getSymbolTableIndex(); - - // The symbol offset inside the section - int64_t SymOffset = (int64_t)MR.getResultPointer(); - - // For pc relative relocations where symbols are defined in the same - // section they are referenced, ignore the relocation entry and patch - // the relocatable field with the symbol offset directly. - if (S.SectionIdx == SectionIdx && TEW->isPCRelativeRel(RelType)) { - int64_t Value = TEW->computeRelocation(SymOffset, RelOffset, RelType); - RelocateField(S, RelOffset, Value, RelTySize); - continue; - } - - Addend = TEW->getDefaultAddendForRelTy(RelType, SymOffset); - } - - // The target without addend on the relocation symbol must be - // patched in the relocation place itself to contain the addend - // otherwise write zeros to make sure there is no garbage there - RelocateField(S, RelOffset, HasRelA ? 0 : Addend, RelTySize); - - // Get the relocation entry and emit to the relocation section - ELFRelocation Rel(RelOffset, SymIdx, RelType, HasRelA, Addend); - EmitRelocation(RelSec, Rel, HasRelA); - } - } -} - -/// EmitRelocation - Write relocation 'Rel' to the relocation section 'Rel' -void ELFWriter::EmitRelocation(BinaryObject &RelSec, ELFRelocation &Rel, - bool HasRelA) { - RelSec.emitWord(Rel.getOffset()); - RelSec.emitWord(Rel.getInfo(is64Bit)); - if (HasRelA) - RelSec.emitWord(Rel.getAddend()); -} - -/// EmitSymbol - Write symbol 'Sym' to the symbol table 'SymbolTable' -void ELFWriter::EmitSymbol(BinaryObject &SymbolTable, ELFSym &Sym) { - if (is64Bit) { - SymbolTable.emitWord32(Sym.NameIdx); - SymbolTable.emitByte(Sym.Info); - SymbolTable.emitByte(Sym.Other); - SymbolTable.emitWord16(Sym.SectionIdx); - SymbolTable.emitWord64(Sym.Value); - SymbolTable.emitWord64(Sym.Size); - } else { - SymbolTable.emitWord32(Sym.NameIdx); - SymbolTable.emitWord32(Sym.Value); - SymbolTable.emitWord32(Sym.Size); - SymbolTable.emitByte(Sym.Info); - SymbolTable.emitByte(Sym.Other); - SymbolTable.emitWord16(Sym.SectionIdx); - } -} - -/// EmitSectionHeader - Write section 'Section' header in 'SHdrTab' -/// Section Header Table -void ELFWriter::EmitSectionHeader(BinaryObject &SHdrTab, - const ELFSection &SHdr) { - SHdrTab.emitWord32(SHdr.NameIdx); - SHdrTab.emitWord32(SHdr.Type); - if (is64Bit) { - SHdrTab.emitWord64(SHdr.Flags); - SHdrTab.emitWord(SHdr.Addr); - SHdrTab.emitWord(SHdr.Offset); - SHdrTab.emitWord64(SHdr.Size); - SHdrTab.emitWord32(SHdr.Link); - SHdrTab.emitWord32(SHdr.Info); - SHdrTab.emitWord64(SHdr.Align); - SHdrTab.emitWord64(SHdr.EntSize); - } else { - SHdrTab.emitWord32(SHdr.Flags); - SHdrTab.emitWord(SHdr.Addr); - SHdrTab.emitWord(SHdr.Offset); - SHdrTab.emitWord32(SHdr.Size); - SHdrTab.emitWord32(SHdr.Link); - SHdrTab.emitWord32(SHdr.Info); - SHdrTab.emitWord32(SHdr.Align); - SHdrTab.emitWord32(SHdr.EntSize); - } -} - -/// EmitStringTable - If the current symbol table is non-empty, emit the string -/// table for it -void ELFWriter::EmitStringTable(const std::string &ModuleName) { - if (!SymbolList.size()) return; // Empty symbol table. - ELFSection &StrTab = getStringTableSection(); - - // Set the zero'th symbol to a null byte, as required. - StrTab.emitByte(0); - - // Walk on the symbol list and write symbol names into the string table. - unsigned Index = 1; - for (ELFSymIter I=SymbolList.begin(), E=SymbolList.end(); I != E; ++I) { - ELFSym &Sym = *(*I); - - std::string Name; - if (Sym.isGlobalValue()) { - SmallString<40> NameStr; - Mang->getNameWithPrefix(NameStr, Sym.getGlobalValue(), false); - Name.append(NameStr.begin(), NameStr.end()); - } else if (Sym.isExternalSym()) - Name.append(Sym.getExternalSymbol()); - else if (Sym.isFileType()) - Name.append(ModuleName); - - if (Name.empty()) { - Sym.NameIdx = 0; - } else { - Sym.NameIdx = Index; - StrTab.emitString(Name); - - // Keep track of the number of bytes emitted to this section. - Index += Name.size()+1; - } - } - assert(Index == StrTab.size()); - StrTab.Size = Index; -} - -// SortSymbols - On the symbol table local symbols must come before -// all other symbols with non-local bindings. The return value is -// the position of the first non local symbol. -unsigned ELFWriter::SortSymbols() { - unsigned FirstNonLocalSymbol; - std::vector LocalSyms, OtherSyms; - - for (ELFSymIter I=SymbolList.begin(), E=SymbolList.end(); I != E; ++I) { - if ((*I)->isLocalBind()) - LocalSyms.push_back(*I); - else - OtherSyms.push_back(*I); - } - SymbolList.clear(); - FirstNonLocalSymbol = LocalSyms.size(); - - for (unsigned i = 0; i < FirstNonLocalSymbol; ++i) - SymbolList.push_back(LocalSyms[i]); - - for (ELFSymIter I=OtherSyms.begin(), E=OtherSyms.end(); I != E; ++I) - SymbolList.push_back(*I); - - LocalSyms.clear(); - OtherSyms.clear(); - - return FirstNonLocalSymbol; -} - -/// EmitSymbolTable - Emit the symbol table itself. -void ELFWriter::EmitSymbolTable() { - if (!SymbolList.size()) return; // Empty symbol table. - - // Now that we have emitted the string table and know the offset into the - // string table of each symbol, emit the symbol table itself. - ELFSection &SymTab = getSymbolTableSection(); - SymTab.Align = TEW->getPrefELFAlignment(); - - // Section Index of .strtab. - SymTab.Link = getStringTableSection().SectionIdx; - - // Size of each symtab entry. - SymTab.EntSize = TEW->getSymTabEntrySize(); - - // Reorder the symbol table with local symbols first! - unsigned FirstNonLocalSymbol = SortSymbols(); - - // Emit all the symbols to the symbol table. - for (unsigned i = 0, e = SymbolList.size(); i < e; ++i) { - ELFSym &Sym = *SymbolList[i]; - - // Emit symbol to the symbol table - EmitSymbol(SymTab, Sym); - - // Record the symbol table index for each symbol - if (Sym.isGlobalValue()) - GblSymLookup[Sym.getGlobalValue()] = i; - else if (Sym.isExternalSym()) - ExtSymLookup[Sym.getExternalSymbol()] = i; - - // Keep track on the symbol index into the symbol table - Sym.SymTabIdx = i; - } - - // One greater than the symbol table index of the last local symbol - SymTab.Info = FirstNonLocalSymbol; - SymTab.Size = SymTab.size(); -} - -/// EmitSectionTableStringTable - This method adds and emits a section for the -/// ELF Section Table string table: the string table that holds all of the -/// section names. -void ELFWriter::EmitSectionTableStringTable() { - // First step: add the section for the string table to the list of sections: - ELFSection &SHStrTab = getSectionHeaderStringTableSection(); - - // Now that we know which section number is the .shstrtab section, update the - // e_shstrndx entry in the ELF header. - ElfHdr.fixWord16(SHStrTab.SectionIdx, ELFHdr_e_shstrndx_Offset); - - // Set the NameIdx of each section in the string table and emit the bytes for - // the string table. - unsigned Index = 0; - - for (ELFSectionIter I=SectionList.begin(), E=SectionList.end(); I != E; ++I) { - ELFSection &S = *(*I); - // Set the index into the table. Note if we have lots of entries with - // common suffixes, we could memoize them here if we cared. - S.NameIdx = Index; - SHStrTab.emitString(S.getName()); - - // Keep track of the number of bytes emitted to this section. - Index += S.getName().size()+1; - } - - // Set the size of .shstrtab now that we know what it is. - assert(Index == SHStrTab.size()); - SHStrTab.Size = Index; -} - -/// OutputSectionsAndSectionTable - Now that we have constructed the file header -/// and all of the sections, emit these to the ostream destination and emit the -/// SectionTable. -void ELFWriter::OutputSectionsAndSectionTable() { - // Pass #1: Compute the file offset for each section. - size_t FileOff = ElfHdr.size(); // File header first. - - // Adjust alignment of all section if needed, skip the null section. - for (unsigned i=1, e=SectionList.size(); i < e; ++i) { - ELFSection &ES = *SectionList[i]; - if (!ES.size()) { - ES.Offset = FileOff; - continue; - } - - // Update Section size - if (!ES.Size) - ES.Size = ES.size(); - - // Align FileOff to whatever the alignment restrictions of the section are. - if (ES.Align) - FileOff = (FileOff+ES.Align-1) & ~(ES.Align-1); - - ES.Offset = FileOff; - FileOff += ES.Size; - } - - // Align Section Header. - unsigned TableAlign = TEW->getPrefELFAlignment(); - FileOff = (FileOff+TableAlign-1) & ~(TableAlign-1); - - // Now that we know where all of the sections will be emitted, set the e_shnum - // entry in the ELF header. - ElfHdr.fixWord16(NumSections, ELFHdr_e_shnum_Offset); - - // Now that we know the offset in the file of the section table, update the - // e_shoff address in the ELF header. - ElfHdr.fixWord(FileOff, ELFHdr_e_shoff_Offset); - - // Now that we know all of the data in the file header, emit it and all of the - // sections! - O.write((char *)&ElfHdr.getData()[0], ElfHdr.size()); - FileOff = ElfHdr.size(); - - // Section Header Table blob - BinaryObject SHdrTable(isLittleEndian, is64Bit); - - // Emit all of sections to the file and build the section header table. - for (ELFSectionIter I=SectionList.begin(), E=SectionList.end(); I != E; ++I) { - ELFSection &S = *(*I); - DEBUG(dbgs() << "SectionIdx: " << S.SectionIdx << ", Name: " << S.getName() - << ", Size: " << S.Size << ", Offset: " << S.Offset - << ", SectionData Size: " << S.size() << "\n"); - - // Align FileOff to whatever the alignment restrictions of the section are. - if (S.size()) { - if (S.Align) { - for (size_t NewFileOff = (FileOff+S.Align-1) & ~(S.Align-1); - FileOff != NewFileOff; ++FileOff) - O << (char)0xAB; - } - O.write((char *)&S.getData()[0], S.Size); - FileOff += S.Size; - } - - EmitSectionHeader(SHdrTable, S); - } - - // Align output for the section table. - for (size_t NewFileOff = (FileOff+TableAlign-1) & ~(TableAlign-1); - FileOff != NewFileOff; ++FileOff) - O << (char)0xAB; - - // Emit the section table itself. - O.write((char *)&SHdrTable.getData()[0], SHdrTable.size()); -} Removed: llvm/trunk/lib/CodeGen/ELFWriter.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/ELFWriter.h?rev=147614&view=auto ============================================================================== --- llvm/trunk/lib/CodeGen/ELFWriter.h (original) +++ llvm/trunk/lib/CodeGen/ELFWriter.h (removed) @@ -1,251 +0,0 @@ -//===-- ELFWriter.h - Target-independent ELF writer support -----*- C++ -*-===// -// -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. -// -//===----------------------------------------------------------------------===// -// -// This file defines the ELFWriter class. -// -//===----------------------------------------------------------------------===// - -#ifndef ELFWRITER_H -#define ELFWRITER_H - -#include "llvm/ADT/SetVector.h" -#include "llvm/CodeGen/MachineFunctionPass.h" -#include - -namespace llvm { - class BinaryObject; - class Constant; - class ConstantInt; - class ConstantStruct; - class ELFCodeEmitter; - class ELFRelocation; - class ELFSection; - struct ELFSym; - class GlobalVariable; - class JITDebugRegisterer; - class Mangler; - class MachineCodeEmitter; - class MachineConstantPoolEntry; - class ObjectCodeEmitter; - class MCAsmInfo; - class TargetELFWriterInfo; - class TargetLoweringObjectFile; - class raw_ostream; - class SectionKind; - class MCContext; - class TargetMachine; - - typedef std::vector::iterator ELFSymIter; - typedef std::vector::iterator ELFSectionIter; - typedef SetVector::const_iterator PendingGblsIter; - typedef SetVector::const_iterator PendingExtsIter; - typedef std::pair CstExprResTy; - - /// ELFWriter - This class implements the common target-independent code for - /// writing ELF files. Targets should derive a class from this to - /// parameterize the output format. - /// - class ELFWriter : public MachineFunctionPass { - friend class ELFCodeEmitter; - friend class JITDebugRegisterer; - public: - static char ID; - - /// Return the ELFCodeEmitter as an instance of ObjectCodeEmitter - ObjectCodeEmitter *getObjectCodeEmitter() { - return reinterpret_cast(ElfCE); - } - - ELFWriter(raw_ostream &O, TargetMachine &TM); - ~ELFWriter(); - - protected: - /// Output stream to send the resultant object file to. - raw_ostream &O; - - /// Target machine description. - TargetMachine &TM; - - /// Context object for machine code objects. - MCContext &OutContext; - - /// Target Elf Writer description. - const TargetELFWriterInfo *TEW; - - /// Mang - The object used to perform name mangling for this module. - Mangler *Mang; - - /// MCE - The MachineCodeEmitter object that we are exposing to emit machine - /// code for functions to the .o file. - ELFCodeEmitter *ElfCE; - - /// TLOF - Target Lowering Object File, provide section names for globals - /// and other object file specific stuff - const TargetLoweringObjectFile &TLOF; - - /// MAI - Target Asm Info, provide information about section names for - /// globals and other target specific stuff. - const MCAsmInfo *MAI; - - //===------------------------------------------------------------------===// - // Properties inferred automatically from the target machine. - //===------------------------------------------------------------------===// - - /// is64Bit/isLittleEndian - This information is inferred from the target - /// machine directly, indicating whether to emit a 32- or 64-bit ELF file. - bool is64Bit, isLittleEndian; - - /// doInitialization - Emit the file header and all of the global variables - /// for the module to the ELF file. - bool doInitialization(Module &M); - bool runOnMachineFunction(MachineFunction &MF); - - /// doFinalization - Now that the module has been completely processed, emit - /// the ELF file to 'O'. - bool doFinalization(Module &M); - - private: - /// Blob containing the Elf header - BinaryObject ElfHdr; - - /// SectionList - This is the list of sections that we have emitted to the - /// file. Once the file has been completely built, the section header table - /// is constructed from this info. - std::vector SectionList; - unsigned NumSections; // Always = SectionList.size() - - /// SectionLookup - This is a mapping from section name to section number in - /// the SectionList. Used to quickly gather the Section Index from MAI names - std::map SectionLookup; - - /// PendingGlobals - Globals not processed as symbols yet. - SetVector PendingGlobals; - - /// GblSymLookup - This is a mapping from global value to a symbol index - /// in the symbol table or private symbols list. This is useful since reloc - /// symbol references must be quickly mapped to their indices on the lists. - std::map GblSymLookup; - - /// PendingExternals - Externals not processed as symbols yet. - SetVector PendingExternals; - - /// ExtSymLookup - This is a mapping from externals to a symbol index - /// in the symbol table list. This is useful since reloc symbol references - /// must be quickly mapped to their symbol table indices. - std::map ExtSymLookup; - - /// SymbolList - This is the list of symbols emitted to the symbol table. - /// When the SymbolList is finally built, local symbols must be placed in - /// the beginning while non-locals at the end. - std::vector SymbolList; - - /// PrivateSyms - Record private symbols, every symbol here must never be - /// present in the SymbolList. - std::vector PrivateSyms; - - /// getSection - Return the section with the specified name, creating a new - /// section if one does not already exist. - ELFSection &getSection(const std::string &Name, unsigned Type, - unsigned Flags = 0, unsigned Align = 0) { - ELFSection *&SN = SectionLookup[Name]; - if (SN) return *SN; - - SectionList.push_back(new ELFSection(Name, isLittleEndian, is64Bit)); - SN = SectionList.back(); - SN->SectionIdx = NumSections++; - SN->Type = Type; - SN->Flags = Flags; - SN->Link = ELF::SHN_UNDEF; - SN->Align = Align; - return *SN; - } - - ELFSection &getNonExecStackSection() { - return getSection(".note.GNU-stack", ELF::SHT_PROGBITS, 0, 1); - } - - ELFSection &getSymbolTableSection() { - return getSection(".symtab", ELF::SHT_SYMTAB, 0); - } - - ELFSection &getStringTableSection() { - return getSection(".strtab", ELF::SHT_STRTAB, 0, 1); - } - - ELFSection &getSectionHeaderStringTableSection() { - return getSection(".shstrtab", ELF::SHT_STRTAB, 0, 1); - } - - ELFSection &getNullSection() { - return getSection("", ELF::SHT_NULL, 0); - } - - ELFSection &getDataSection(); - ELFSection &getBSSSection(); - ELFSection &getCtorSection(); - ELFSection &getDtorSection(); - ELFSection &getJumpTableSection(); - ELFSection &getConstantPoolSection(MachineConstantPoolEntry &CPE); - ELFSection &getTextSection(const Function *F); - ELFSection &getRelocSection(ELFSection &S); - - // Helpers for obtaining ELF specific info. - unsigned getGlobalELFBinding(const GlobalValue *GV); - unsigned getGlobalELFType(const GlobalValue *GV); - unsigned getGlobalELFVisibility(const GlobalValue *GV); - - // AddPendingGlobalSymbol - Add a global to be processed and to - // the global symbol lookup, use a zero index because the table - // index will be determined later. - void AddPendingGlobalSymbol(const GlobalValue *GV, - bool AddToLookup = false); - - // AddPendingExternalSymbol - Add the external to be processed - // and to the external symbol lookup, use a zero index because - // the symbol table index will be determined later. - void AddPendingExternalSymbol(const char *External); - - // AddToSymbolList - Update the symbol lookup and If the symbol is - // private add it to PrivateSyms list, otherwise to SymbolList. - void AddToSymbolList(ELFSym *GblSym); - - // As we complete the ELF file, we need to update fields in the ELF header - // (e.g. the location of the section table). These members keep track of - // the offset in ELFHeader of these various pieces to update and other - // locations in the file. - unsigned ELFHdr_e_shoff_Offset; // e_shoff in ELF header. - unsigned ELFHdr_e_shstrndx_Offset; // e_shstrndx in ELF header. - unsigned ELFHdr_e_shnum_Offset; // e_shnum in ELF header. - - private: - void EmitGlobal(const GlobalValue *GV); - void EmitGlobalConstant(const Constant *C, ELFSection &GblS); - void EmitGlobalConstantStruct(const ConstantStruct *CVS, - ELFSection &GblS); - void EmitGlobalConstantLargeInt(const ConstantInt *CI, ELFSection &S); - void EmitGlobalDataRelocation(const GlobalValue *GV, unsigned Size, - ELFSection &GblS, int64_t Offset = 0); - bool EmitSpecialLLVMGlobal(const GlobalVariable *GV); - void EmitXXStructorList(const Constant *List, ELFSection &Xtor); - void EmitRelocations(); - void EmitRelocation(BinaryObject &RelSec, ELFRelocation &Rel, bool HasRelA); - void EmitSectionHeader(BinaryObject &SHdrTab, const ELFSection &SHdr); - void EmitSectionTableStringTable(); - void EmitSymbol(BinaryObject &SymbolTable, ELFSym &Sym); - void EmitSymbolTable(); - void EmitStringTable(const std::string &ModuleName); - void OutputSectionsAndSectionTable(); - void RelocateField(BinaryObject &BO, uint32_t Offset, int64_t Value, - unsigned Size); - unsigned SortSymbols(); - CstExprResTy ResolveConstantExpr(const Constant *CV); - }; -} - -#endif Modified: llvm/trunk/lib/ExecutionEngine/JIT/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/ExecutionEngine/JIT/CMakeLists.txt?rev=147615&r1=147614&r2=147615&view=diff ============================================================================== --- llvm/trunk/lib/ExecutionEngine/JIT/CMakeLists.txt (original) +++ llvm/trunk/lib/ExecutionEngine/JIT/CMakeLists.txt Thu Jan 5 16:07:43 2012 @@ -4,7 +4,6 @@ add_llvm_library(LLVMJIT Intercept.cpp JIT.cpp - JITDebugRegisterer.cpp JITDwarfEmitter.cpp JITEmitter.cpp JITMemoryManager.cpp Removed: llvm/trunk/lib/ExecutionEngine/JIT/JITDebugRegisterer.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/ExecutionEngine/JIT/JITDebugRegisterer.cpp?rev=147614&view=auto ============================================================================== --- llvm/trunk/lib/ExecutionEngine/JIT/JITDebugRegisterer.cpp (original) +++ llvm/trunk/lib/ExecutionEngine/JIT/JITDebugRegisterer.cpp (removed) @@ -1,211 +0,0 @@ -//===-- JITDebugRegisterer.cpp - Register debug symbols for JIT -----------===// -// -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. -// -//===----------------------------------------------------------------------===// -// -// This file defines a JITDebugRegisterer object that is used by the JIT to -// register debug info with debuggers like GDB. -// -//===----------------------------------------------------------------------===// - -#include "JITDebugRegisterer.h" -#include "../../CodeGen/ELF.h" -#include "../../CodeGen/ELFWriter.h" -#include "llvm/LLVMContext.h" -#include "llvm/Function.h" -#include "llvm/Module.h" -#include "llvm/Target/TargetMachine.h" -#include "llvm/Target/TargetOptions.h" -#include "llvm/ADT/DenseMap.h" -#include "llvm/ADT/OwningPtr.h" -#include "llvm/Support/Compiler.h" -#include "llvm/Support/MutexGuard.h" -#include "llvm/Support/raw_ostream.h" -#include "llvm/Support/Mutex.h" -#include - -namespace llvm { - -// This must be kept in sync with gdb/gdb/jit.h . -extern "C" { - - // Debuggers puts a breakpoint in this function. - LLVM_ATTRIBUTE_NOINLINE void __jit_debug_register_code() { } - - // We put information about the JITed function in this global, which the - // debugger reads. Make sure to specify the version statically, because the - // debugger checks the version before we can set it during runtime. - struct jit_descriptor __jit_debug_descriptor = { 1, 0, 0, 0 }; - -} - -namespace { - - /// JITDebugLock - Used to serialize all code registration events, since they - /// modify global variables. - sys::Mutex JITDebugLock; - -} - -JITDebugRegisterer::JITDebugRegisterer(TargetMachine &tm) : TM(tm), FnMap() { } - -JITDebugRegisterer::~JITDebugRegisterer() { - // Free all ELF memory. - for (RegisteredFunctionsMap::iterator I = FnMap.begin(), E = FnMap.end(); - I != E; ++I) { - // Call the private method that doesn't update the map so our iterator - // doesn't break. - UnregisterFunctionInternal(I); - } - FnMap.clear(); -} - -std::string JITDebugRegisterer::MakeELF(const Function *F, DebugInfo &I) { - // Stack allocate an empty module with an empty LLVMContext for the ELFWriter - // API. We don't use the real module because then the ELFWriter would write - // out unnecessary GlobalValues during finalization. - LLVMContext Context; - Module M("", Context); - - // Make a buffer for the ELF in memory. - std::string Buffer; - raw_string_ostream O(Buffer); - ELFWriter EW(O, TM); - EW.doInitialization(M); - - // Copy the binary into the .text section. This isn't necessary, but it's - // useful to be able to disassemble the ELF by hand. - ELFSection &Text = EW.getTextSection(const_cast(F)); - Text.Addr = (uint64_t)I.FnStart; - // TODO: We could eliminate this copy if we somehow used a pointer/size pair - // instead of a vector. - Text.getData().assign(I.FnStart, I.FnEnd); - - // Copy the exception handling call frame information into the .eh_frame - // section. This allows GDB to get a good stack trace, particularly on - // linux x86_64. Mark this as a PROGBITS section that needs to be loaded - // into memory at runtime. - ELFSection &EH = EW.getSection(".eh_frame", ELF::SHT_PROGBITS, - ELF::SHF_ALLOC); - // Pointers in the DWARF EH info are all relative to the EH frame start, - // which is stored here. - EH.Addr = (uint64_t)I.EhStart; - // TODO: We could eliminate this copy if we somehow used a pointer/size pair - // instead of a vector. - EH.getData().assign(I.EhStart, I.EhEnd); - - // Add this single function to the symbol table, so the debugger prints the - // name instead of '???'. We give the symbol default global visibility. - ELFSym *FnSym = ELFSym::getGV(F, - ELF::STB_GLOBAL, - ELF::STT_FUNC, - ELF::STV_DEFAULT); - FnSym->SectionIdx = Text.SectionIdx; - FnSym->Size = I.FnEnd - I.FnStart; - FnSym->Value = 0; // Offset from start of section. - EW.SymbolList.push_back(FnSym); - - EW.doFinalization(M); - O.flush(); - - // When trying to debug why GDB isn't getting the debug info right, it's - // awfully helpful to write the object file to disk so that it can be - // inspected with readelf and objdump. - if (TM.Options.JITEmitDebugInfoToDisk) { - std::string Filename; - raw_string_ostream O2(Filename); - O2 << "/tmp/llvm_function_" << I.FnStart << "_" << F->getName() << ".o"; - O2.flush(); - std::string Errors; - raw_fd_ostream O3(Filename.c_str(), Errors); - O3 << Buffer; - O3.close(); - } - - return Buffer; -} - -void JITDebugRegisterer::RegisterFunction(const Function *F, DebugInfo &I) { - // TODO: Support non-ELF platforms. - if (!TM.getELFWriterInfo()) - return; - - std::string Buffer = MakeELF(F, I); - - jit_code_entry *JITCodeEntry = new jit_code_entry(); - JITCodeEntry->symfile_addr = Buffer.c_str(); - JITCodeEntry->symfile_size = Buffer.size(); - - // Add a mapping from F to the entry and buffer, so we can delete this - // info later. - FnMap[F] = std::make_pair(Buffer, JITCodeEntry); - - // Acquire the lock and do the registration. - { - MutexGuard locked(JITDebugLock); - __jit_debug_descriptor.action_flag = JIT_REGISTER_FN; - - // Insert this entry at the head of the list. - JITCodeEntry->prev_entry = NULL; - jit_code_entry *NextEntry = __jit_debug_descriptor.first_entry; - JITCodeEntry->next_entry = NextEntry; - if (NextEntry != NULL) { - NextEntry->prev_entry = JITCodeEntry; - } - __jit_debug_descriptor.first_entry = JITCodeEntry; - __jit_debug_descriptor.relevant_entry = JITCodeEntry; - __jit_debug_register_code(); - } -} - -void JITDebugRegisterer::UnregisterFunctionInternal( - RegisteredFunctionsMap::iterator I) { - jit_code_entry *&JITCodeEntry = I->second.second; - - // Acquire the lock and do the unregistration. - { - MutexGuard locked(JITDebugLock); - __jit_debug_descriptor.action_flag = JIT_UNREGISTER_FN; - - // Remove the jit_code_entry from the linked list. - jit_code_entry *PrevEntry = JITCodeEntry->prev_entry; - jit_code_entry *NextEntry = JITCodeEntry->next_entry; - if (NextEntry) { - NextEntry->prev_entry = PrevEntry; - } - if (PrevEntry) { - PrevEntry->next_entry = NextEntry; - } else { - assert(__jit_debug_descriptor.first_entry == JITCodeEntry); - __jit_debug_descriptor.first_entry = NextEntry; - } - - // Tell GDB which entry we removed, and unregister the code. - __jit_debug_descriptor.relevant_entry = JITCodeEntry; - __jit_debug_register_code(); - } - - delete JITCodeEntry; - JITCodeEntry = NULL; - - // Free the ELF file in memory. - std::string &Buffer = I->second.first; - Buffer.clear(); -} - -void JITDebugRegisterer::UnregisterFunction(const Function *F) { - // TODO: Support non-ELF platforms. - if (!TM.getELFWriterInfo()) - return; - - RegisteredFunctionsMap::iterator I = FnMap.find(F); - if (I == FnMap.end()) return; - UnregisterFunctionInternal(I); - FnMap.erase(I); -} - -} // end namespace llvm Removed: llvm/trunk/lib/ExecutionEngine/JIT/JITDebugRegisterer.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/ExecutionEngine/JIT/JITDebugRegisterer.h?rev=147614&view=auto ============================================================================== --- llvm/trunk/lib/ExecutionEngine/JIT/JITDebugRegisterer.h (original) +++ llvm/trunk/lib/ExecutionEngine/JIT/JITDebugRegisterer.h (removed) @@ -1,116 +0,0 @@ -//===-- JITDebugRegisterer.h - Register debug symbols for JIT -------------===// -// -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. -// -//===----------------------------------------------------------------------===// -// -// This file defines a JITDebugRegisterer object that is used by the JIT to -// register debug info with debuggers like GDB. -// -//===----------------------------------------------------------------------===// - -#ifndef LLVM_EXECUTION_ENGINE_JIT_DEBUGREGISTERER_H -#define LLVM_EXECUTION_ENGINE_JIT_DEBUGREGISTERER_H - -#include "llvm/ADT/DenseMap.h" -#include "llvm/Support/DataTypes.h" -#include - -// This must be kept in sync with gdb/gdb/jit.h . -extern "C" { - - typedef enum { - JIT_NOACTION = 0, - JIT_REGISTER_FN, - JIT_UNREGISTER_FN - } jit_actions_t; - - struct jit_code_entry { - struct jit_code_entry *next_entry; - struct jit_code_entry *prev_entry; - const char *symfile_addr; - uint64_t symfile_size; - }; - - struct jit_descriptor { - uint32_t version; - // This should be jit_actions_t, but we want to be specific about the - // bit-width. - uint32_t action_flag; - struct jit_code_entry *relevant_entry; - struct jit_code_entry *first_entry; - }; - -} - -namespace llvm { - -class ELFSection; -class Function; -class TargetMachine; - - -/// This class encapsulates information we want to send to the debugger. -/// -struct DebugInfo { - uint8_t *FnStart; - uint8_t *FnEnd; - uint8_t *EhStart; - uint8_t *EhEnd; - - DebugInfo() : FnStart(0), FnEnd(0), EhStart(0), EhEnd(0) {} -}; - -typedef DenseMap< const Function*, std::pair > - RegisteredFunctionsMap; - -/// This class registers debug info for JITed code with an attached debugger. -/// Without proper debug info, GDB can't do things like source level debugging -/// or even produce a proper stack trace on linux-x86_64. To use this class, -/// whenever a function is JITed, create a DebugInfo struct and pass it to the -/// RegisterFunction method. The method will then do whatever is necessary to -/// inform the debugger about the JITed function. -class JITDebugRegisterer { - - TargetMachine &TM; - - /// FnMap - A map of functions that have been registered to the associated - /// temporary files. Used for cleanup. - RegisteredFunctionsMap FnMap; - - /// MakeELF - Builds the ELF file in memory and returns a std::string that - /// contains the ELF. - std::string MakeELF(const Function *F, DebugInfo &I); - -public: - JITDebugRegisterer(TargetMachine &tm); - - /// ~JITDebugRegisterer - Unregisters all code and frees symbol files. - /// - ~JITDebugRegisterer(); - - /// RegisterFunction - Register debug info for the given function with an - /// attached debugger. Clients must call UnregisterFunction on all - /// registered functions before deleting them to free the associated symbol - /// file and unregister it from the debugger. - void RegisterFunction(const Function *F, DebugInfo &I); - - /// UnregisterFunction - Unregister the debug info for the given function - /// from the debugger and free associated memory. - void UnregisterFunction(const Function *F); - -private: - /// UnregisterFunctionInternal - Unregister the debug info for the given - /// function from the debugger and delete any temporary files. The private - /// version of this method does not remove the function from FnMap so that it - /// can be called while iterating over FnMap. - void UnregisterFunctionInternal(RegisteredFunctionsMap::iterator I); - -}; - -} // end namespace llvm - -#endif // LLVM_EXECUTION_ENGINE_JIT_DEBUGREGISTERER_H Modified: llvm/trunk/lib/ExecutionEngine/JIT/JITEmitter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/ExecutionEngine/JIT/JITEmitter.cpp?rev=147615&r1=147614&r2=147615&view=diff ============================================================================== --- llvm/trunk/lib/ExecutionEngine/JIT/JITEmitter.cpp (original) +++ llvm/trunk/lib/ExecutionEngine/JIT/JITEmitter.cpp Thu Jan 5 16:07:43 2012 @@ -14,7 +14,6 @@ #define DEBUG_TYPE "jit" #include "JIT.h" -#include "JITDebugRegisterer.h" #include "JITDwarfEmitter.h" #include "llvm/ADT/OwningPtr.h" #include "llvm/Constants.h" @@ -324,9 +323,6 @@ /// DE - The dwarf emitter for the jit. OwningPtr DE; - /// DR - The debug registerer for the jit. - OwningPtr DR; - /// LabelLocations - This vector is a mapping from Label ID's to their /// address. DenseMap LabelLocations; @@ -364,26 +360,20 @@ bool JITExceptionHandling; - bool JITEmitDebugInfo; - public: JITEmitter(JIT &jit, JITMemoryManager *JMM, TargetMachine &TM) : SizeEstimate(0), Resolver(jit, *this), MMI(0), CurFn(0), EmittedFunctions(this), TheJIT(&jit), - JITExceptionHandling(TM.Options.JITExceptionHandling), - JITEmitDebugInfo(TM.Options.JITEmitDebugInfo) { + JITExceptionHandling(TM.Options.JITExceptionHandling) { MemMgr = JMM ? JMM : JITMemoryManager::CreateDefaultMemManager(); if (jit.getJITInfo().needsGOT()) { MemMgr->AllocateGOT(); DEBUG(dbgs() << "JIT is managing a GOT\n"); } - if (JITExceptionHandling || JITEmitDebugInfo) { + if (JITExceptionHandling) { DE.reset(new JITDwarfEmitter(jit)); } - if (JITEmitDebugInfo) { - DR.reset(new JITDebugRegisterer(TM)); - } } ~JITEmitter() { delete MemMgr; @@ -974,7 +964,7 @@ } }); - if (JITExceptionHandling || JITEmitDebugInfo) { + if (JITExceptionHandling) { uintptr_t ActualSize = 0; SavedBufferBegin = BufferBegin; SavedBufferEnd = BufferEnd; @@ -989,7 +979,6 @@ EhStart); MemMgr->endExceptionTable(F.getFunction(), BufferBegin, CurBufferPtr, FrameRegister); - uint8_t *EhEnd = CurBufferPtr; BufferBegin = SavedBufferBegin; BufferEnd = SavedBufferEnd; CurBufferPtr = SavedCurBufferPtr; @@ -997,15 +986,6 @@ if (JITExceptionHandling) { TheJIT->RegisterTable(F.getFunction(), FrameRegister); } - - if (JITEmitDebugInfo) { - DebugInfo I; - I.FnStart = FnStart; - I.FnEnd = FnEnd; - I.EhStart = EhStart; - I.EhEnd = EhEnd; - DR->RegisterFunction(F.getFunction(), I); - } } if (MMI) @@ -1046,10 +1026,6 @@ if (JITExceptionHandling) { TheJIT->DeregisterTable(F); } - - if (JITEmitDebugInfo) { - DR->UnregisterFunction(F); - } } From nicholas at mxc.ca Thu Jan 5 16:21:46 2012 From: nicholas at mxc.ca (Nick Lewycky) Date: Thu, 05 Jan 2012 22:21:46 -0000 Subject: [llvm-commits] [llvm] r147616 - /llvm/trunk/lib/Transforms/IPO/FunctionAttrs.cpp Message-ID: <20120105222146.34F7A2A6C12C@llvm.org> Author: nicholas Date: Thu Jan 5 16:21:45 2012 New Revision: 147616 URL: http://llvm.org/viewvc/llvm-project?rev=147616&view=rev Log: SCCCaptured is trivially false on entry to this loop and not modified inside it. Eliminate the dead test for it on each loop iteration. No functionality change. Modified: llvm/trunk/lib/Transforms/IPO/FunctionAttrs.cpp Modified: llvm/trunk/lib/Transforms/IPO/FunctionAttrs.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/IPO/FunctionAttrs.cpp?rev=147616&r1=147615&r2=147616&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/IPO/FunctionAttrs.cpp (original) +++ llvm/trunk/lib/Transforms/IPO/FunctionAttrs.cpp Thu Jan 5 16:21:45 2012 @@ -461,7 +461,7 @@ } if (SCCCaptured) continue; - for (unsigned i = 0, e = ArgumentSCC.size(); i != e && !SCCCaptured; ++i) { + for (unsigned i = 0, e = ArgumentSCC.size(); i != e; ++i) { Argument *A = ArgumentSCC[i]->Definition; A->addAttr(Attribute::NoCapture); ++NumNoCapture; From benny.kra at googlemail.com Thu Jan 5 16:31:37 2012 From: benny.kra at googlemail.com (Benjamin Kramer) Date: Thu, 05 Jan 2012 22:31:37 -0000 Subject: [llvm-commits] [llvm] r147618 - in /llvm/trunk: include/llvm/CodeGen/BinaryObject.h include/llvm/CodeGen/ObjectCodeEmitter.h lib/CodeGen/CMakeLists.txt lib/CodeGen/ObjectCodeEmitter.cpp Message-ID: <20120105223137.72CB81BE003@llvm.org> Author: d0k Date: Thu Jan 5 16:31:37 2012 New Revision: 147618 URL: http://llvm.org/viewvc/llvm-project?rev=147618&view=rev Log: Kill ObjectCodeEmitter and BinaryObject, they were unused and superseded by MC. Removed: llvm/trunk/include/llvm/CodeGen/BinaryObject.h llvm/trunk/include/llvm/CodeGen/ObjectCodeEmitter.h llvm/trunk/lib/CodeGen/ObjectCodeEmitter.cpp Modified: llvm/trunk/lib/CodeGen/CMakeLists.txt Removed: llvm/trunk/include/llvm/CodeGen/BinaryObject.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/BinaryObject.h?rev=147617&view=auto ============================================================================== --- llvm/trunk/include/llvm/CodeGen/BinaryObject.h (original) +++ llvm/trunk/include/llvm/CodeGen/BinaryObject.h (removed) @@ -1,353 +0,0 @@ -//===-- llvm/CodeGen/BinaryObject.h - Binary Object. -----------*- C++ -*-===// -// -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. -// -//===----------------------------------------------------------------------===// -// -// This file defines a Binary Object Aka. "blob" for holding data from code -// generators, ready for data to the object module code writters. -// -//===----------------------------------------------------------------------===// - -#ifndef LLVM_CODEGEN_BINARYOBJECT_H -#define LLVM_CODEGEN_BINARYOBJECT_H - -#include "llvm/CodeGen/MachineRelocation.h" -#include "llvm/Support/DataTypes.h" - -#include -#include - -namespace llvm { - -typedef std::vector BinaryData; - -class BinaryObject { -protected: - std::string Name; - bool IsLittleEndian; - bool Is64Bit; - BinaryData Data; - std::vector Relocations; - -public: - /// Constructors and destructor - BinaryObject() {} - - BinaryObject(bool isLittleEndian, bool is64Bit) - : IsLittleEndian(isLittleEndian), Is64Bit(is64Bit) {} - - BinaryObject(const std::string &name, bool isLittleEndian, bool is64Bit) - : Name(name), IsLittleEndian(isLittleEndian), Is64Bit(is64Bit) {} - - ~BinaryObject() {} - - /// getName - get name of BinaryObject - inline std::string getName() const { return Name; } - - /// get size of binary data - size_t size() const { - return Data.size(); - } - - /// get binary data - BinaryData& getData() { - return Data; - } - - /// get machine relocations - const std::vector& getRelocations() const { - return Relocations; - } - - /// hasRelocations - Return true if 'Relocations' is not empty - bool hasRelocations() const { - return !Relocations.empty(); - } - - /// emitZeros - This callback is invoked to emit a arbitrary number - /// of zero bytes to the data stream. - inline void emitZeros(unsigned Size) { - for (unsigned i=0; i < Size; ++i) - emitByte(0); - } - - /// emitByte - This callback is invoked when a byte needs to be - /// written to the data stream. - inline void emitByte(uint8_t B) { - Data.push_back(B); - } - - /// emitWord16 - This callback is invoked when a 16-bit word needs to be - /// written to the data stream in correct endian format and correct size. - inline void emitWord16(uint16_t W) { - if (IsLittleEndian) - emitWord16LE(W); - else - emitWord16BE(W); - } - - /// emitWord16LE - This callback is invoked when a 16-bit word needs to be - /// written to the data stream in correct endian format and correct size. - inline void emitWord16LE(uint16_t W) { - Data.push_back((uint8_t)(W >> 0)); - Data.push_back((uint8_t)(W >> 8)); - } - - /// emitWord16BE - This callback is invoked when a 16-bit word needs to be - /// written to the data stream in correct endian format and correct size. - inline void emitWord16BE(uint16_t W) { - Data.push_back((uint8_t)(W >> 8)); - Data.push_back((uint8_t)(W >> 0)); - } - - /// emitWord - This callback is invoked when a word needs to be - /// written to the data stream in correct endian format and correct size. - inline void emitWord(uint64_t W) { - if (!Is64Bit) - emitWord32(W); - else - emitWord64(W); - } - - /// emitWord32 - This callback is invoked when a 32-bit word needs to be - /// written to the data stream in correct endian format. - inline void emitWord32(uint32_t W) { - if (IsLittleEndian) - emitWordLE(W); - else - emitWordBE(W); - } - - /// emitWord64 - This callback is invoked when a 32-bit word needs to be - /// written to the data stream in correct endian format. - inline void emitWord64(uint64_t W) { - if (IsLittleEndian) - emitDWordLE(W); - else - emitDWordBE(W); - } - - /// emitWord64 - This callback is invoked when a x86_fp80 needs to be - /// written to the data stream in correct endian format. - inline void emitWordFP80(const uint64_t *W, unsigned PadSize) { - if (IsLittleEndian) { - emitWord64(W[0]); - emitWord16(W[1]); - } else { - emitWord16(W[1]); - emitWord64(W[0]); - } - emitZeros(PadSize); - } - - /// emitWordLE - This callback is invoked when a 32-bit word needs to be - /// written to the data stream in little-endian format. - inline void emitWordLE(uint32_t W) { - Data.push_back((uint8_t)(W >> 0)); - Data.push_back((uint8_t)(W >> 8)); - Data.push_back((uint8_t)(W >> 16)); - Data.push_back((uint8_t)(W >> 24)); - } - - /// emitWordBE - This callback is invoked when a 32-bit word needs to be - /// written to the data stream in big-endian format. - /// - inline void emitWordBE(uint32_t W) { - Data.push_back((uint8_t)(W >> 24)); - Data.push_back((uint8_t)(W >> 16)); - Data.push_back((uint8_t)(W >> 8)); - Data.push_back((uint8_t)(W >> 0)); - } - - /// emitDWordLE - This callback is invoked when a 64-bit word needs to be - /// written to the data stream in little-endian format. - inline void emitDWordLE(uint64_t W) { - Data.push_back((uint8_t)(W >> 0)); - Data.push_back((uint8_t)(W >> 8)); - Data.push_back((uint8_t)(W >> 16)); - Data.push_back((uint8_t)(W >> 24)); - Data.push_back((uint8_t)(W >> 32)); - Data.push_back((uint8_t)(W >> 40)); - Data.push_back((uint8_t)(W >> 48)); - Data.push_back((uint8_t)(W >> 56)); - } - - /// emitDWordBE - This callback is invoked when a 64-bit word needs to be - /// written to the data stream in big-endian format. - inline void emitDWordBE(uint64_t W) { - Data.push_back((uint8_t)(W >> 56)); - Data.push_back((uint8_t)(W >> 48)); - Data.push_back((uint8_t)(W >> 40)); - Data.push_back((uint8_t)(W >> 32)); - Data.push_back((uint8_t)(W >> 24)); - Data.push_back((uint8_t)(W >> 16)); - Data.push_back((uint8_t)(W >> 8)); - Data.push_back((uint8_t)(W >> 0)); - } - - /// fixByte - This callback is invoked when a byte needs to be - /// fixup the buffer. - inline void fixByte(uint8_t B, uint32_t offset) { - Data[offset] = B; - } - - /// fixWord16 - This callback is invoked when a 16-bit word needs to - /// fixup the data stream in correct endian format. - inline void fixWord16(uint16_t W, uint32_t offset) { - if (IsLittleEndian) - fixWord16LE(W, offset); - else - fixWord16BE(W, offset); - } - - /// emitWord16LE - This callback is invoked when a 16-bit word needs to - /// fixup the data stream in little endian format. - inline void fixWord16LE(uint16_t W, uint32_t offset) { - Data[offset] = (uint8_t)(W >> 0); - Data[++offset] = (uint8_t)(W >> 8); - } - - /// fixWord16BE - This callback is invoked when a 16-bit word needs to - /// fixup data stream in big endian format. - inline void fixWord16BE(uint16_t W, uint32_t offset) { - Data[offset] = (uint8_t)(W >> 8); - Data[++offset] = (uint8_t)(W >> 0); - } - - /// emitWord - This callback is invoked when a word needs to - /// fixup the data in correct endian format and correct size. - inline void fixWord(uint64_t W, uint32_t offset) { - if (!Is64Bit) - fixWord32(W, offset); - else - fixWord64(W, offset); - } - - /// fixWord32 - This callback is invoked when a 32-bit word needs to - /// fixup the data in correct endian format. - inline void fixWord32(uint32_t W, uint32_t offset) { - if (IsLittleEndian) - fixWord32LE(W, offset); - else - fixWord32BE(W, offset); - } - - /// fixWord32LE - This callback is invoked when a 32-bit word needs to - /// fixup the data in little endian format. - inline void fixWord32LE(uint32_t W, uint32_t offset) { - Data[offset] = (uint8_t)(W >> 0); - Data[++offset] = (uint8_t)(W >> 8); - Data[++offset] = (uint8_t)(W >> 16); - Data[++offset] = (uint8_t)(W >> 24); - } - - /// fixWord32BE - This callback is invoked when a 32-bit word needs to - /// fixup the data in big endian format. - inline void fixWord32BE(uint32_t W, uint32_t offset) { - Data[offset] = (uint8_t)(W >> 24); - Data[++offset] = (uint8_t)(W >> 16); - Data[++offset] = (uint8_t)(W >> 8); - Data[++offset] = (uint8_t)(W >> 0); - } - - /// fixWord64 - This callback is invoked when a 64-bit word needs to - /// fixup the data in correct endian format. - inline void fixWord64(uint64_t W, uint32_t offset) { - if (IsLittleEndian) - fixWord64LE(W, offset); - else - fixWord64BE(W, offset); - } - - /// fixWord64BE - This callback is invoked when a 64-bit word needs to - /// fixup the data in little endian format. - inline void fixWord64LE(uint64_t W, uint32_t offset) { - Data[offset] = (uint8_t)(W >> 0); - Data[++offset] = (uint8_t)(W >> 8); - Data[++offset] = (uint8_t)(W >> 16); - Data[++offset] = (uint8_t)(W >> 24); - Data[++offset] = (uint8_t)(W >> 32); - Data[++offset] = (uint8_t)(W >> 40); - Data[++offset] = (uint8_t)(W >> 48); - Data[++offset] = (uint8_t)(W >> 56); - } - - /// fixWord64BE - This callback is invoked when a 64-bit word needs to - /// fixup the data in big endian format. - inline void fixWord64BE(uint64_t W, uint32_t offset) { - Data[offset] = (uint8_t)(W >> 56); - Data[++offset] = (uint8_t)(W >> 48); - Data[++offset] = (uint8_t)(W >> 40); - Data[++offset] = (uint8_t)(W >> 32); - Data[++offset] = (uint8_t)(W >> 24); - Data[++offset] = (uint8_t)(W >> 16); - Data[++offset] = (uint8_t)(W >> 8); - Data[++offset] = (uint8_t)(W >> 0); - } - - /// emitAlignment - Pad the data to the specified alignment. - void emitAlignment(unsigned Alignment, uint8_t fill = 0) { - if (Alignment <= 1) return; - unsigned PadSize = -Data.size() & (Alignment-1); - for (unsigned i = 0; i>= 7; - if (Value) Byte |= 0x80; - emitByte(Byte); - } while (Value); - } - - /// emitSLEB128Bytes - This callback is invoked when a SLEB128 needs to be - /// written to the data stream. - void emitSLEB128Bytes(int64_t Value) { - int Sign = Value >> (8 * sizeof(Value) - 1); - bool IsMore; - - do { - uint8_t Byte = (uint8_t)(Value & 0x7f); - Value >>= 7; - IsMore = Value != Sign || ((Byte ^ Sign) & 0x40) != 0; - if (IsMore) Byte |= 0x80; - emitByte(Byte); - } while (IsMore); - } - - /// emitString - This callback is invoked when a String needs to be - /// written to the data stream. - void emitString(const std::string &String) { - for (unsigned i = 0, N = static_cast(String.size()); i MBBLocations; - - /// LabelLocations - This vector is a mapping from Label ID's to their - /// address. - std::vector LabelLocations; - - /// CPLocations - This is a map of constant pool indices to offsets from the - /// start of the section for that constant pool index. - std::vector CPLocations; - - /// CPSections - This is a map of constant pool indices to the Section - /// containing the constant pool entry for that index. - std::vector CPSections; - - /// JTLocations - This is a map of jump table indices to offsets from the - /// start of the section for that jump table index. - std::vector JTLocations; - -public: - ObjectCodeEmitter(); - ObjectCodeEmitter(BinaryObject *bo); - virtual ~ObjectCodeEmitter(); - - /// setBinaryObject - set the BinaryObject we are writting to - void setBinaryObject(BinaryObject *bo); - - /// emitByte - This callback is invoked when a byte needs to be - /// written to the data stream, without buffer overflow testing. - void emitByte(uint8_t B); - - /// emitWordLE - This callback is invoked when a 32-bit word needs to be - /// written to the data stream in little-endian format. - void emitWordLE(uint32_t W); - - /// emitWordBE - This callback is invoked when a 32-bit word needs to be - /// written to the data stream in big-endian format. - void emitWordBE(uint32_t W); - - /// emitDWordLE - This callback is invoked when a 64-bit word needs to be - /// written to the data stream in little-endian format. - void emitDWordLE(uint64_t W); - - /// emitDWordBE - This callback is invoked when a 64-bit word needs to be - /// written to the data stream in big-endian format. - void emitDWordBE(uint64_t W); - - /// emitAlignment - Move the CurBufferPtr pointer up to the specified - /// alignment (saturated to BufferEnd of course). - void emitAlignment(unsigned Alignment = 0, uint8_t fill = 0); - - /// emitULEB128Bytes - This callback is invoked when a ULEB128 needs to be - /// written to the data stream. - void emitULEB128Bytes(uint64_t Value); - - /// emitSLEB128Bytes - This callback is invoked when a SLEB128 needs to be - /// written to the data stream. - void emitSLEB128Bytes(uint64_t Value); - - /// emitString - This callback is invoked when a String needs to be - /// written to the data stream. - void emitString(const std::string &String); - - /// getCurrentPCValue - This returns the address that the next emitted byte - /// will be output to. - uintptr_t getCurrentPCValue() const; - - /// getCurrentPCOffset - Return the offset from the start of the emitted - /// buffer that we are currently writing to. - uintptr_t getCurrentPCOffset() const; - - /// addRelocation - Whenever a relocatable address is needed, it should be - /// noted with this interface. - void addRelocation(const MachineRelocation& relocation); - - /// earlyResolveAddresses - True if the code emitter can use symbol addresses - /// during code emission time. The JIT is capable of doing this because it - /// creates jump tables or constant pools in memory on the fly while the - /// object code emitters rely on a linker to have real addresses and should - /// use relocations instead. - bool earlyResolveAddresses() const { return false; } - - /// startFunction - This callback is invoked when the specified function is - /// about to be code generated. This initializes the BufferBegin/End/Ptr - /// fields. - virtual void startFunction(MachineFunction &F) = 0; - - /// finishFunction - This callback is invoked when the specified function has - /// finished code generation. If a buffer overflow has occurred, this method - /// returns true (the callee is required to try again), otherwise it returns - /// false. - virtual bool finishFunction(MachineFunction &F) = 0; - - /// StartMachineBasicBlock - This should be called by the target when a new - /// basic block is about to be emitted. This way the MCE knows where the - /// start of the block is, and can implement getMachineBasicBlockAddress. - virtual void StartMachineBasicBlock(MachineBasicBlock *MBB); - - /// getMachineBasicBlockAddress - Return the address of the specified - /// MachineBasicBlock, only usable after the label for the MBB has been - /// emitted. - virtual uintptr_t getMachineBasicBlockAddress(MachineBasicBlock *MBB) const; - - /// emitJumpTables - Emit all the jump tables for a given jump table info - /// record to the appropriate section. - virtual void emitJumpTables(MachineJumpTableInfo *MJTI) = 0; - - /// getJumpTableEntryAddress - Return the address of the jump table with index - /// 'Index' in the function that last called initJumpTableInfo. - virtual uintptr_t getJumpTableEntryAddress(unsigned Index) const; - - /// emitConstantPool - For each constant pool entry, figure out which section - /// the constant should live in, allocate space for it, and emit it to the - /// Section data buffer. - virtual void emitConstantPool(MachineConstantPool *MCP) = 0; - - /// getConstantPoolEntryAddress - Return the address of the 'Index' entry in - /// the constant pool that was last emitted with the emitConstantPool method. - virtual uintptr_t getConstantPoolEntryAddress(unsigned Index) const; - - /// getConstantPoolEntrySection - Return the section of the 'Index' entry in - /// the constant pool that was last emitted with the emitConstantPool method. - virtual uintptr_t getConstantPoolEntrySection(unsigned Index) const; - - /// Specifies the MachineModuleInfo object. This is used for exception handling - /// purposes. - virtual void setModuleInfo(MachineModuleInfo* Info) = 0; - // to be implemented or depreciated with MachineModuleInfo - -}; // end class ObjectCodeEmitter - -} // end namespace llvm - -#endif - Modified: llvm/trunk/lib/CodeGen/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/CMakeLists.txt?rev=147618&r1=147617&r2=147618&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/CMakeLists.txt (original) +++ llvm/trunk/lib/CodeGen/CMakeLists.txt Thu Jan 5 16:31:37 2012 @@ -58,7 +58,6 @@ MachineSSAUpdater.cpp MachineSink.cpp MachineVerifier.cpp - ObjectCodeEmitter.cpp OcamlGC.cpp OptimizePHIs.cpp PHIElimination.cpp Removed: llvm/trunk/lib/CodeGen/ObjectCodeEmitter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/ObjectCodeEmitter.cpp?rev=147617&view=auto ============================================================================== --- llvm/trunk/lib/CodeGen/ObjectCodeEmitter.cpp (original) +++ llvm/trunk/lib/CodeGen/ObjectCodeEmitter.cpp (removed) @@ -1,141 +0,0 @@ -//===-- llvm/CodeGen/ObjectCodeEmitter.cpp -------------------- -*- C++ -*-===// -// -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. -// -//===----------------------------------------------------------------------===// - -#include "llvm/CodeGen/BinaryObject.h" -#include "llvm/CodeGen/MachineBasicBlock.h" -#include "llvm/CodeGen/MachineRelocation.h" -#include "llvm/CodeGen/ObjectCodeEmitter.h" - -//===----------------------------------------------------------------------===// -// ObjectCodeEmitter Implementation -//===----------------------------------------------------------------------===// - -namespace llvm { - -ObjectCodeEmitter::ObjectCodeEmitter() : BO(0) {} -ObjectCodeEmitter::ObjectCodeEmitter(BinaryObject *bo) : BO(bo) {} -ObjectCodeEmitter::~ObjectCodeEmitter() {} - -/// setBinaryObject - set the BinaryObject we are writting to -void ObjectCodeEmitter::setBinaryObject(BinaryObject *bo) { BO = bo; } - -/// emitByte - This callback is invoked when a byte needs to be -/// written to the data stream, without buffer overflow testing. -void ObjectCodeEmitter::emitByte(uint8_t B) { - BO->emitByte(B); -} - -/// emitWordLE - This callback is invoked when a 32-bit word needs to be -/// written to the data stream in little-endian format. -void ObjectCodeEmitter::emitWordLE(uint32_t W) { - BO->emitWordLE(W); -} - -/// emitWordBE - This callback is invoked when a 32-bit word needs to be -/// written to the data stream in big-endian format. -void ObjectCodeEmitter::emitWordBE(uint32_t W) { - BO->emitWordBE(W); -} - -/// emitDWordLE - This callback is invoked when a 64-bit word needs to be -/// written to the data stream in little-endian format. -void ObjectCodeEmitter::emitDWordLE(uint64_t W) { - BO->emitDWordLE(W); -} - -/// emitDWordBE - This callback is invoked when a 64-bit word needs to be -/// written to the data stream in big-endian format. -void ObjectCodeEmitter::emitDWordBE(uint64_t W) { - BO->emitDWordBE(W); -} - -/// emitAlignment - Align 'BO' to the necessary alignment boundary. -void ObjectCodeEmitter::emitAlignment(unsigned Alignment /* 0 */, - uint8_t fill /* 0 */) { - BO->emitAlignment(Alignment, fill); -} - -/// emitULEB128Bytes - This callback is invoked when a ULEB128 needs to be -/// written to the data stream. -void ObjectCodeEmitter::emitULEB128Bytes(uint64_t Value) { - BO->emitULEB128Bytes(Value); -} - -/// emitSLEB128Bytes - This callback is invoked when a SLEB128 needs to be -/// written to the data stream. -void ObjectCodeEmitter::emitSLEB128Bytes(uint64_t Value) { - BO->emitSLEB128Bytes(Value); -} - -/// emitString - This callback is invoked when a String needs to be -/// written to the data stream. -void ObjectCodeEmitter::emitString(const std::string &String) { - BO->emitString(String); -} - -/// getCurrentPCValue - This returns the address that the next emitted byte -/// will be output to. -uintptr_t ObjectCodeEmitter::getCurrentPCValue() const { - return BO->getCurrentPCOffset(); -} - -/// getCurrentPCOffset - Return the offset from the start of the emitted -/// buffer that we are currently writing to. -uintptr_t ObjectCodeEmitter::getCurrentPCOffset() const { - return BO->getCurrentPCOffset(); -} - -/// addRelocation - Whenever a relocatable address is needed, it should be -/// noted with this interface. -void ObjectCodeEmitter::addRelocation(const MachineRelocation& relocation) { - BO->addRelocation(relocation); -} - -/// StartMachineBasicBlock - This should be called by the target when a new -/// basic block is about to be emitted. This way the MCE knows where the -/// start of the block is, and can implement getMachineBasicBlockAddress. -void ObjectCodeEmitter::StartMachineBasicBlock(MachineBasicBlock *MBB) { - if (MBBLocations.size() <= (unsigned)MBB->getNumber()) - MBBLocations.resize((MBB->getNumber()+1)*2); - MBBLocations[MBB->getNumber()] = getCurrentPCOffset(); -} - -/// getMachineBasicBlockAddress - Return the address of the specified -/// MachineBasicBlock, only usable after the label for the MBB has been -/// emitted. -uintptr_t -ObjectCodeEmitter::getMachineBasicBlockAddress(MachineBasicBlock *MBB) const { - assert(MBBLocations.size() > (unsigned)MBB->getNumber() && - MBBLocations[MBB->getNumber()] && "MBB not emitted!"); - return MBBLocations[MBB->getNumber()]; -} - -/// getJumpTableEntryAddress - Return the address of the jump table with index -/// 'Index' in the function that last called initJumpTableInfo. -uintptr_t ObjectCodeEmitter::getJumpTableEntryAddress(unsigned Index) const { - assert(JTLocations.size() > Index && "JT not emitted!"); - return JTLocations[Index]; -} - -/// getConstantPoolEntryAddress - Return the address of the 'Index' entry in -/// the constant pool that was last emitted with the emitConstantPool method. -uintptr_t ObjectCodeEmitter::getConstantPoolEntryAddress(unsigned Index) const { - assert(CPLocations.size() > Index && "CP not emitted!"); - return CPLocations[Index]; -} - -/// getConstantPoolEntrySection - Return the section of the 'Index' entry in -/// the constant pool that was last emitted with the emitConstantPool method. -uintptr_t ObjectCodeEmitter::getConstantPoolEntrySection(unsigned Index) const { - assert(CPSections.size() > Index && "CP not emitted!"); - return CPSections[Index]; -} - -} // end namespace llvm - From gohman at apple.com Thu Jan 5 16:54:35 2012 From: gohman at apple.com (Dan Gohman) Date: Thu, 05 Jan 2012 22:54:35 -0000 Subject: [llvm-commits] [llvm] r147623 - in /llvm/trunk: lib/Transforms/Utils/SimplifyCFG.cpp test/Transforms/SimplifyCFG/SpeculativeExec.ll Message-ID: <20120105225435.63C8C2A6C12C@llvm.org> Author: djg Date: Thu Jan 5 16:54:35 2012 New Revision: 147623 URL: http://llvm.org/viewvc/llvm-project?rev=147623&view=rev Log: Revert r56315. When the instruction to speculate is a load, this code can incorrectly move the load across a store. This never happens in practice today, but only because the current heuristics accidentally preclude it. Modified: llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp llvm/trunk/test/Transforms/SimplifyCFG/SpeculativeExec.ll Modified: llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp?rev=147623&r1=147622&r2=147623&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp (original) +++ llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp Thu Jan 5 16:54:35 2012 @@ -1063,32 +1063,8 @@ return false; } - // If we get here, we can hoist the instruction. Try to place it - // before the icmp instruction preceding the conditional branch. - BasicBlock::iterator InsertPos = BI; - if (InsertPos != BIParent->begin()) - --InsertPos; - // Skip debug info between condition and branch. - while (InsertPos != BIParent->begin() && isa(InsertPos)) - --InsertPos; - if (InsertPos == BrCond && !isa(BrCond)) { - SmallPtrSet BB1Insns; - for(BasicBlock::iterator BB1I = BB1->begin(), BB1E = BB1->end(); - BB1I != BB1E; ++BB1I) - BB1Insns.insert(BB1I); - for(Value::use_iterator UI = BrCond->use_begin(), UE = BrCond->use_end(); - UI != UE; ++UI) { - Instruction *Use = cast(*UI); - if (!BB1Insns.count(Use)) continue; - - // If BrCond uses the instruction that place it just before - // branch instruction. - InsertPos = BI; - break; - } - } else - InsertPos = BI; - BIParent->getInstList().splice(InsertPos, BB1->getInstList(), HInst); + // If we get here, we can hoist the instruction. + BIParent->getInstList().splice(BI, BB1->getInstList(), HInst); // Create a select whose true value is the speculatively executed value and // false value is the previously determined FalseV. Modified: llvm/trunk/test/Transforms/SimplifyCFG/SpeculativeExec.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/SimplifyCFG/SpeculativeExec.ll?rev=147623&r1=147622&r2=147623&view=diff ============================================================================== --- llvm/trunk/test/Transforms/SimplifyCFG/SpeculativeExec.ll (original) +++ llvm/trunk/test/Transforms/SimplifyCFG/SpeculativeExec.ll Thu Jan 5 16:54:35 2012 @@ -13,8 +13,8 @@ %tmp2 = icmp sgt i32 %c, 1 br i1 %tmp2, label %bb2, label %bb3 ; CHECK: bb1: -; CHECK-NEXT: add i32 %a, 1 ; CHECK-NEXT: icmp sgt i32 %c, 1 +; CHECK-NEXT: add i32 %a, 1 ; CHECK-NEXT: select i1 %tmp2, i32 %tmp3, i32 %a ; CHECK-NEXT: br label %bb3 From rafael.espindola at gmail.com Thu Jan 5 17:02:01 2012 From: rafael.espindola at gmail.com (Rafael Espindola) Date: Thu, 05 Jan 2012 23:02:01 -0000 Subject: [llvm-commits] [llvm] r147624 - in /llvm/trunk: lib/Linker/LinkModules.cpp test/Linker/visibility1.ll test/Linker/visibility2.ll Message-ID: <20120105230201.AE88F2A6C12C@llvm.org> Author: rafael Date: Thu Jan 5 17:02:01 2012 New Revision: 147624 URL: http://llvm.org/viewvc/llvm-project?rev=147624&view=rev Log: Link symbols with different visibilities according to the rules in the System V Application Binary Interface. This lets us use -fvisibility-inlines-hidden with LTO. Fixes PR11697. Added: llvm/trunk/test/Linker/visibility1.ll llvm/trunk/test/Linker/visibility2.ll Modified: llvm/trunk/lib/Linker/LinkModules.cpp Modified: llvm/trunk/lib/Linker/LinkModules.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Linker/LinkModules.cpp?rev=147624&r1=147623&r2=147624&view=diff ============================================================================== --- llvm/trunk/lib/Linker/LinkModules.cpp (original) +++ llvm/trunk/lib/Linker/LinkModules.cpp Thu Jan 5 17:02:01 2012 @@ -17,6 +17,7 @@ #include "llvm/Instructions.h" #include "llvm/Module.h" #include "llvm/ADT/SmallPtrSet.h" +#include "llvm/ADT/Optional.h" #include "llvm/Support/raw_ostream.h" #include "llvm/Support/Path.h" #include "llvm/Transforms/Utils/Cloning.h" @@ -379,7 +380,9 @@ /// getLinkageResult - This analyzes the two global values and determines /// what the result will look like in the destination module. bool getLinkageResult(GlobalValue *Dest, const GlobalValue *Src, - GlobalValue::LinkageTypes <, bool &LinkFromSrc); + GlobalValue::LinkageTypes <, + GlobalValue::VisibilityTypes &Vis, + bool &LinkFromSrc); /// getLinkedToGlobal - Given a global in the source module, return the /// global in the destination module that is being linked to, if any. @@ -451,15 +454,27 @@ forceRenaming(DestGV, SrcGV->getName()); } +static bool isLessConstraining(GlobalValue::VisibilityTypes a, + GlobalValue::VisibilityTypes b) { + if (a == GlobalValue::HiddenVisibility) + return false; + if (b == GlobalValue::HiddenVisibility) + return true; + if (a == GlobalValue::ProtectedVisibility) + return false; + if (b == GlobalValue::ProtectedVisibility) + return true; + return false; +} + /// getLinkageResult - This analyzes the two global values and determines what /// the result will look like in the destination module. In particular, it -/// computes the resultant linkage type, computes whether the global in the -/// source should be copied over to the destination (replacing the existing -/// one), and computes whether this linkage is an error or not. It also performs -/// visibility checks: we cannot link together two symbols with different -/// visibilities. +/// computes the resultant linkage type and visibility, computes whether the +/// global in the source should be copied over to the destination (replacing +/// the existing one), and computes whether this linkage is an error or not. bool ModuleLinker::getLinkageResult(GlobalValue *Dest, const GlobalValue *Src, - GlobalValue::LinkageTypes <, + GlobalValue::LinkageTypes <, + GlobalValue::VisibilityTypes &Vis, bool &LinkFromSrc) { assert(Dest && "Must have two globals being queried"); assert(!Src->hasLocalLinkage() && @@ -521,13 +536,10 @@ "': symbol multiply defined!"); } - // Check visibility - if (Src->getVisibility() != Dest->getVisibility() && - !SrcIsDeclaration && !DestIsDeclaration && - !Src->hasAvailableExternallyLinkage() && - !Dest->hasAvailableExternallyLinkage()) - return emitError("Linking globals named '" + Src->getName() + - "': symbols have different visibilities!"); + // Compute the visibility. We follow the rules in the System V Application + // Binary Interface. + Vis = isLessConstraining(Src->getVisibility(), Dest->getVisibility()) ? + Dest->getVisibility() : Src->getVisibility(); return false; } @@ -665,6 +677,7 @@ /// merge them into the dest module. bool ModuleLinker::linkGlobalProto(GlobalVariable *SGV) { GlobalValue *DGV = getLinkedToGlobal(SGV); + llvm::Optional NewVisibility; if (DGV) { // Concatenation of appending linkage variables is magic and handled later. @@ -674,9 +687,11 @@ // Determine whether linkage of these two globals follows the source // module's definition or the destination module's definition. GlobalValue::LinkageTypes NewLinkage = GlobalValue::InternalLinkage; + GlobalValue::VisibilityTypes NV; bool LinkFromSrc = false; - if (getLinkageResult(DGV, SGV, NewLinkage, LinkFromSrc)) + if (getLinkageResult(DGV, SGV, NewLinkage, NV, LinkFromSrc)) return true; + NewVisibility = NV; // If we're not linking from the source, then keep the definition that we // have. @@ -686,9 +701,10 @@ if (DGVar->isDeclaration() && SGV->isConstant() && !DGVar->isConstant()) DGVar->setConstant(true); - // Set calculated linkage. + // Set calculated linkage and visibility. DGV->setLinkage(NewLinkage); - + DGV->setVisibility(*NewVisibility); + // Make sure to remember this mapping. ValueMap[SGV] = ConstantExpr::getBitCast(DGV,TypeMap.get(SGV->getType())); @@ -711,6 +727,8 @@ SGV->getType()->getAddressSpace()); // Propagate alignment, visibility and section info. CopyGVAttributes(NewDGV, SGV); + if (NewVisibility) + NewDGV->setVisibility(*NewVisibility); if (DGV) { DGV->replaceAllUsesWith(ConstantExpr::getBitCast(NewDGV, DGV->getType())); @@ -726,17 +744,21 @@ /// destination module if needed, setting up mapping information. bool ModuleLinker::linkFunctionProto(Function *SF) { GlobalValue *DGV = getLinkedToGlobal(SF); + llvm::Optional NewVisibility; if (DGV) { GlobalValue::LinkageTypes NewLinkage = GlobalValue::InternalLinkage; bool LinkFromSrc = false; - if (getLinkageResult(DGV, SF, NewLinkage, LinkFromSrc)) + GlobalValue::VisibilityTypes NV; + if (getLinkageResult(DGV, SF, NewLinkage, NV, LinkFromSrc)) return true; - + NewVisibility = NV; + if (!LinkFromSrc) { // Set calculated linkage DGV->setLinkage(NewLinkage); - + DGV->setVisibility(*NewVisibility); + // Make sure to remember this mapping. ValueMap[SF] = ConstantExpr::getBitCast(DGV, TypeMap.get(SF->getType())); @@ -753,6 +775,8 @@ Function *NewDF = Function::Create(TypeMap.get(SF->getFunctionType()), SF->getLinkage(), SF->getName(), DstM); CopyGVAttributes(NewDF, SF); + if (NewVisibility) + NewDF->setVisibility(*NewVisibility); if (DGV) { // Any uses of DF need to change to NewDF, with cast. @@ -775,17 +799,21 @@ /// source module. bool ModuleLinker::linkAliasProto(GlobalAlias *SGA) { GlobalValue *DGV = getLinkedToGlobal(SGA); - + llvm::Optional NewVisibility; + if (DGV) { GlobalValue::LinkageTypes NewLinkage = GlobalValue::InternalLinkage; + GlobalValue::VisibilityTypes NV; bool LinkFromSrc = false; - if (getLinkageResult(DGV, SGA, NewLinkage, LinkFromSrc)) + if (getLinkageResult(DGV, SGA, NewLinkage, NV, LinkFromSrc)) return true; - + NewVisibility = NV; + if (!LinkFromSrc) { // Set calculated linkage. DGV->setLinkage(NewLinkage); - + DGV->setVisibility(*NewVisibility); + // Make sure to remember this mapping. ValueMap[SGA] = ConstantExpr::getBitCast(DGV,TypeMap.get(SGA->getType())); @@ -802,6 +830,8 @@ SGA->getLinkage(), SGA->getName(), /*aliasee*/0, DstM); CopyGVAttributes(NewDA, SGA); + if (NewVisibility) + NewDA->setVisibility(*NewVisibility); if (DGV) { // Any uses of DGV need to change to NewDA, with cast. Added: llvm/trunk/test/Linker/visibility1.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Linker/visibility1.ll?rev=147624&view=auto ============================================================================== --- llvm/trunk/test/Linker/visibility1.ll (added) +++ llvm/trunk/test/Linker/visibility1.ll Thu Jan 5 17:02:01 2012 @@ -0,0 +1,46 @@ +; RUN: llvm-link %s %p/visibility2.ll -S | FileCheck %s +; RUN: llvm-link %p/visibility2.ll %s -S | FileCheck %s + +; The values in this file are strong, the ones in visibility2.ll are weak, +; but we should still get the visibility from them. + +; Variables +; CHECK: @v1 = hidden global i32 0 + at v1 = global i32 0 + +; CHECK: @v2 = protected global i32 0 + at v2 = global i32 0 + +; CHECK: @v3 = hidden global i32 0 + at v3 = protected global i32 0 + + +; Aliases +; CHECK: @a1 = hidden alias i32* @v1 + at a1 = alias i32* @v1 + +; CHECK: @a2 = protected alias i32* @v2 + at a2 = alias i32* @v2 + +; CHECK: @a3 = hidden alias i32* @v3 + at a3 = protected alias i32* @v3 + + +; Functions +; CHECK: define hidden void @f1() +define void @f1() { +entry: + ret void +} + +; CHECK: define protected void @f2() +define void @f2() { +entry: + ret void +} + +; CHECK: define hidden void @f3() +define protected void @f3() { +entry: + ret void +} Added: llvm/trunk/test/Linker/visibility2.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Linker/visibility2.ll?rev=147624&view=auto ============================================================================== --- llvm/trunk/test/Linker/visibility2.ll (added) +++ llvm/trunk/test/Linker/visibility2.ll Thu Jan 5 17:02:01 2012 @@ -0,0 +1,27 @@ +; This file is used by visibility1.ll, so it doesn't actually do anything itself +; +; RUN: true + +; Variables + at v1 = weak hidden global i32 0 + at v2 = weak protected global i32 0 + at v3 = weak hidden global i32 0 + +; Aliases + at a1 = hidden alias weak i32* @v1 + at a2 = protected alias weak i32* @v2 + at a3 = hidden alias weak i32* @v3 + +; Functions +define weak hidden void @f1() { +entry: + ret void +} +define weak protected void @f2() { +entry: + ret void +} +define weak hidden void @f3() { +entry: + ret void +} From eli.friedman at gmail.com Thu Jan 5 17:03:32 2012 From: eli.friedman at gmail.com (Eli Friedman) Date: Thu, 05 Jan 2012 23:03:32 -0000 Subject: [llvm-commits] [llvm] r147625 - in /llvm/trunk: lib/Transforms/IPO/GlobalOpt.cpp test/Transforms/GlobalOpt/ctor-list-opt-constexpr.ll Message-ID: <20120105230332.E5A2D2A6C12C@llvm.org> Author: efriedma Date: Thu Jan 5 17:03:32 2012 New Revision: 147625 URL: http://llvm.org/viewvc/llvm-project?rev=147625&view=rev Log: PR11705, part 2: globalopt shouldn't put inttoptr/ptrtoint operations into global initializers if there's an implied extension or truncation. Modified: llvm/trunk/lib/Transforms/IPO/GlobalOpt.cpp llvm/trunk/test/Transforms/GlobalOpt/ctor-list-opt-constexpr.ll Modified: llvm/trunk/lib/Transforms/IPO/GlobalOpt.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/IPO/GlobalOpt.cpp?rev=147625&r1=147624&r2=147625&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/IPO/GlobalOpt.cpp (original) +++ llvm/trunk/lib/Transforms/IPO/GlobalOpt.cpp Thu Jan 5 17:03:32 2012 @@ -2069,7 +2069,8 @@ static inline bool isSimpleEnoughValueToCommit(Constant *C, - SmallPtrSet &SimpleConstants); + SmallPtrSet &SimpleConstants, + const TargetData *TD); /// isSimpleEnoughValueToCommit - Return true if the specified constant can be @@ -2081,7 +2082,8 @@ /// in SimpleConstants to avoid having to rescan the same constants all the /// time. static bool isSimpleEnoughValueToCommitHelper(Constant *C, - SmallPtrSet &SimpleConstants) { + SmallPtrSet &SimpleConstants, + const TargetData *TD) { // Simple integer, undef, constant aggregate zero, global addresses, etc are // all supported. if (C->getNumOperands() == 0 || isa(C) || @@ -2093,7 +2095,7 @@ isa(C)) { for (unsigned i = 0, e = C->getNumOperands(); i != e; ++i) { Constant *Op = cast(C->getOperand(i)); - if (!isSimpleEnoughValueToCommit(Op, SimpleConstants)) + if (!isSimpleEnoughValueToCommit(Op, SimpleConstants, TD)) return false; } return true; @@ -2105,34 +2107,42 @@ ConstantExpr *CE = cast(C); switch (CE->getOpcode()) { case Instruction::BitCast: + // Bitcast is fine if the casted value is fine. + return isSimpleEnoughValueToCommit(CE->getOperand(0), SimpleConstants, TD); + case Instruction::IntToPtr: case Instruction::PtrToInt: - // These casts are always fine if the casted value is. - return isSimpleEnoughValueToCommit(CE->getOperand(0), SimpleConstants); + // int <=> ptr is fine if the int type is the same size as the + // pointer type. + if (!TD || TD->getTypeSizeInBits(CE->getType()) != + TD->getTypeSizeInBits(CE->getOperand(0)->getType())) + return false; + return isSimpleEnoughValueToCommit(CE->getOperand(0), SimpleConstants, TD); // GEP is fine if it is simple + constant offset. case Instruction::GetElementPtr: for (unsigned i = 1, e = CE->getNumOperands(); i != e; ++i) if (!isa(CE->getOperand(i))) return false; - return isSimpleEnoughValueToCommit(CE->getOperand(0), SimpleConstants); + return isSimpleEnoughValueToCommit(CE->getOperand(0), SimpleConstants, TD); case Instruction::Add: // We allow simple+cst. if (!isa(CE->getOperand(1))) return false; - return isSimpleEnoughValueToCommit(CE->getOperand(0), SimpleConstants); + return isSimpleEnoughValueToCommit(CE->getOperand(0), SimpleConstants, TD); } return false; } static inline bool isSimpleEnoughValueToCommit(Constant *C, - SmallPtrSet &SimpleConstants) { + SmallPtrSet &SimpleConstants, + const TargetData *TD) { // If we already checked this constant, we win. if (!SimpleConstants.insert(C)) return true; // Check the constant. - return isSimpleEnoughValueToCommitHelper(C, SimpleConstants); + return isSimpleEnoughValueToCommitHelper(C, SimpleConstants, TD); } @@ -2353,7 +2363,7 @@ // If this might be too difficult for the backend to handle (e.g. the addr // of one global variable divided by another) then we can't commit it. - if (!isSimpleEnoughValueToCommit(Val, SimpleConstants)) + if (!isSimpleEnoughValueToCommit(Val, SimpleConstants, TD)) return false; if (ConstantExpr *CE = dyn_cast(Ptr)) Modified: llvm/trunk/test/Transforms/GlobalOpt/ctor-list-opt-constexpr.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/GlobalOpt/ctor-list-opt-constexpr.ll?rev=147625&r1=147624&r2=147625&view=diff ============================================================================== --- llvm/trunk/test/Transforms/GlobalOpt/ctor-list-opt-constexpr.ll (original) +++ llvm/trunk/test/Transforms/GlobalOpt/ctor-list-opt-constexpr.ll Thu Jan 5 17:03:32 2012 @@ -4,20 +4,31 @@ %0 = type { i32, void ()* } %struct.foo = type { i32* } +%struct.bar = type { i128 } @G = global i32 0, align 4 @H = global i32 0, align 4 @X = global %struct.foo zeroinitializer, align 8 - at llvm.global_ctors = appending global [1 x %0] [%0 { i32 65535, void ()* @init }] + at X2 = global %struct.bar zeroinitializer, align 8 + at llvm.global_ctors = appending global [2 x %0] [%0 { i32 65535, void ()* @init1 }, %0 { i32 65535, void ()* @init2 }] ; PR8710 - GlobalOpt shouldn't change the global's initializer to have this ; arbitrary constant expression, the code generator can't handle it. -define internal void @init() { +define internal void @init1() { entry: %tmp = getelementptr inbounds %struct.foo* @X, i32 0, i32 0 store i32* inttoptr (i64 sdiv (i64 ptrtoint (i32* @G to i64), i64 ptrtoint (i32* @H to i64)) to i32*), i32** %tmp, align 8 ret void } - -; CHECK: @init +; CHECK: @init1 ; CHECK: store i32* + +; PR11705 - ptrtoint isn't safe in general in global initializers. +define internal void @init2() { +entry: + %tmp = getelementptr inbounds %struct.bar* @X2, i32 0, i32 0 + store i128 ptrtoint (i32* @G to i128), i128* %tmp, align 16 + ret void +} +; CHECK: @init2 +; CHECK: store i128 From kcc at google.com Thu Jan 5 17:50:34 2012 From: kcc at google.com (Kostya Serebryany) Date: Thu, 05 Jan 2012 23:50:34 -0000 Subject: [llvm-commits] [compiler-rt] r147628 - in /compiler-rt/trunk/lib/asan: asan_linux.cc asan_procmaps.h asan_stack.cc Message-ID: <20120105235034.DBF392A6C12C@llvm.org> Author: kcc Date: Thu Jan 5 17:50:34 2012 New Revision: 147628 URL: http://llvm.org/viewvc/llvm-project?rev=147628&view=rev Log: [asan] use dl_iterate_phdr for pre-symbolization on linux instead of parsing /proc/self/maps Modified: compiler-rt/trunk/lib/asan/asan_linux.cc compiler-rt/trunk/lib/asan/asan_procmaps.h compiler-rt/trunk/lib/asan/asan_stack.cc Modified: compiler-rt/trunk/lib/asan/asan_linux.cc URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/lib/asan/asan_linux.cc?rev=147628&r1=147627&r2=147628&view=diff ============================================================================== --- compiler-rt/trunk/lib/asan/asan_linux.cc (original) +++ compiler-rt/trunk/lib/asan/asan_linux.cc Thu Jan 5 17:50:34 2012 @@ -24,17 +24,16 @@ #include #include #include +#include #include #include #include -extern char _DYNAMIC[]; - namespace __asan { void *AsanDoesNotSupportStaticLinkage() { // This will fail to link with -static. - return &_DYNAMIC; + return &_DYNAMIC; // defined in link.h } static void *asan_mmap(void *addr, size_t length, int prot, int flags, @@ -120,20 +119,20 @@ current_ = proc_self_maps_buff_; } -bool AsanProcMaps::Next(uint64_t *start, uint64_t *end, - uint64_t *offset, char filename[], +bool AsanProcMaps::Next(uintptr_t *start, uintptr_t *end, + uintptr_t *offset, char filename[], size_t filename_size) { char *last = proc_self_maps_buff_ + proc_self_maps_buff_len_; if (current_ >= last) return false; int consumed = 0; char flags[10]; int major, minor; - uint64_t inode; + uintptr_t inode; char *next_line = (char*)internal_memchr(current_, '\n', last - current_); if (next_line == NULL) next_line = last; if (SScanf(current_, - "%llx-%llx %4s %llx %x:%x %lld %n", + "%lx-%lx %4s %lx %x:%x %ld %n", start, end, flags, offset, &major, &minor, &inode, &consumed) != 7) return false; @@ -154,6 +153,50 @@ return true; } +struct DlIterateData { + int count; + uintptr_t addr; + uintptr_t offset; + char *filename; + size_t filename_size; +}; + +static int dl_iterate_phdr_callback(struct dl_phdr_info *info, + size_t size, void *raw_data) { + DlIterateData *data = (DlIterateData*)raw_data; + int count = data->count++; + if (info->dlpi_addr > data->addr) + return 0; + if (count == 0) { + // The first item (the main executable) does not have a so name, + // but we can just read it from /proc/self/exe. + ssize_t path_len = readlink("/proc/self/exe", + data->filename, data->filename_size - 1); + data->filename[path_len] = 0; + } else { + CHECK(info->dlpi_name); + real_strncpy(data->filename, info->dlpi_name, data->filename_size); + } + data->offset = data->addr - info->dlpi_addr; + return 1; +} + +// Gets the object name and the offset using dl_iterate_phdr. +bool AsanProcMaps::GetObjectNameAndOffset(uintptr_t addr, uintptr_t *offset, + char filename[], + size_t filename_size) { + DlIterateData data; + data.count = 0; + data.addr = addr; + data.filename = filename; + data.filename_size = filename_size; + if (dl_iterate_phdr(dl_iterate_phdr_callback, &data)) { + *offset = data.offset; + return true; + } + return false; +} + void AsanThread::SetThreadStackTopAndBottom() { if (tid() == 0) { // This is the main thread. Libpthread may not be initialized yet. @@ -162,8 +205,8 @@ // Find the mapping that contains a stack variable. AsanProcMaps proc_maps; - uint64_t start, end, offset; - uint64_t prev_end = 0; + uintptr_t start, end, offset; + uintptr_t prev_end = 0; while (proc_maps.Next(&start, &end, &offset, NULL, 0)) { if ((uintptr_t)&rl < end) break; Modified: compiler-rt/trunk/lib/asan/asan_procmaps.h URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/lib/asan/asan_procmaps.h?rev=147628&r1=147627&r2=147628&view=diff ============================================================================== --- compiler-rt/trunk/lib/asan/asan_procmaps.h (original) +++ compiler-rt/trunk/lib/asan/asan_procmaps.h Thu Jan 5 17:50:34 2012 @@ -21,9 +21,13 @@ class AsanProcMaps { public: AsanProcMaps(); - bool Next(uint64_t *start, uint64_t *end, uint64_t *offset, + bool Next(uintptr_t *start, uintptr_t *end, uintptr_t *offset, char filename[], size_t filename_size); void Reset(); + // Gets the object file name and the offset in that object for a given + // address 'addr'. Returns true on success. + bool GetObjectNameAndOffset(uintptr_t addr, uintptr_t *offset, + char filename[], size_t filename_size); ~AsanProcMaps(); private: #if defined __linux__ Modified: compiler-rt/trunk/lib/asan/asan_stack.cc URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/lib/asan/asan_stack.cc?rev=147628&r1=147627&r2=147628&view=diff ============================================================================== --- compiler-rt/trunk/lib/asan/asan_stack.cc (original) +++ compiler-rt/trunk/lib/asan/asan_stack.cc Thu Jan 5 17:50:34 2012 @@ -133,21 +133,12 @@ for (size_t i = 0; i < size && addr[i]; i++) { proc_maps.Reset(); uintptr_t pc = addr[i]; - uint64_t start, end, offset; + uintptr_t offset; char filename[4096]; - bool found = 0; - int map_idx = 0; - while (proc_maps.Next(&start, &end, &offset, - filename, sizeof(filename))) { - if (pc >= start && pc <= end) { - found = true; - uintptr_t relative_pc = (map_idx == 0) ? pc : (pc - start); - Printf(" #%ld 0x%lx (%s+0x%lx)\n", i, pc, filename, relative_pc); - break; - } - map_idx++; - } - if (!found) { + if (proc_maps.GetObjectNameAndOffset(pc, &offset, + filename, sizeof(filename))) { + Printf(" #%ld 0x%lx (%s+0x%lx)\n", i, pc, filename, offset); + } else { Printf(" #%ld 0x%lx\n", i, pc); } } From gohman at apple.com Thu Jan 5 17:58:57 2012 From: gohman at apple.com (Dan Gohman) Date: Thu, 05 Jan 2012 23:58:57 -0000 Subject: [llvm-commits] [llvm] r147630 - in /llvm/trunk: lib/Transforms/Utils/SimplifyCFG.cpp test/Transforms/SimplifyCFG/2009-01-19-UnconditionalTrappingConstantExpr.ll test/Transforms/SimplifyCFG/multiple-phis.ll test/Transforms/SimplifyCFG/select-gep.ll test/Transforms/SimplifyCFG/switch-masked-bits.ll test/Transforms/SimplifyCFG/switch-on-const-select.ll Message-ID: <20120105235857.59F032A6C12C@llvm.org> Author: djg Date: Thu Jan 5 17:58:56 2012 New Revision: 147630 URL: http://llvm.org/viewvc/llvm-project?rev=147630&view=rev Log: Fix SpeculativelyExecuteBB to either speculate all or none of the phis present in the bottom of the CFG triangle, as the transformation isn't ever valuable if the branch can't be eliminated. Also, unify some heuristics between SimplifyCFG's multiple if-converters, for consistency. This fixes rdar://10627242. Added: llvm/trunk/test/Transforms/SimplifyCFG/multiple-phis.ll Modified: llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp llvm/trunk/test/Transforms/SimplifyCFG/2009-01-19-UnconditionalTrappingConstantExpr.ll llvm/trunk/test/Transforms/SimplifyCFG/select-gep.ll llvm/trunk/test/Transforms/SimplifyCFG/switch-masked-bits.ll llvm/trunk/test/Transforms/SimplifyCFG/switch-on-const-select.ll Modified: llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp?rev=147630&r1=147629&r2=147630&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp (original) +++ llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp Thu Jan 5 17:58:56 2012 @@ -20,12 +20,14 @@ #include "llvm/IntrinsicInst.h" #include "llvm/LLVMContext.h" #include "llvm/Metadata.h" +#include "llvm/Operator.h" #include "llvm/Type.h" #include "llvm/Analysis/InstructionSimplify.h" #include "llvm/Analysis/ValueTracking.h" #include "llvm/Target/TargetData.h" #include "llvm/Transforms/Utils/BasicBlockUtils.h" #include "llvm/ADT/DenseMap.h" +#include "llvm/ADT/SetVector.h" #include "llvm/ADT/SmallVector.h" #include "llvm/ADT/SmallPtrSet.h" #include "llvm/ADT/Statistic.h" @@ -207,6 +209,42 @@ return BI->getCondition(); } +/// ComputeSpeculuationCost - Compute an abstract "cost" of speculating the +/// given instruction, which is assumed to be safe to speculate. 1 means +/// cheap, 2 means less cheap, and UINT_MAX means prohibitively expensive. +static unsigned ComputeSpeculationCost(const User *I) { + assert(isSafeToSpeculativelyExecute(I) && + "Instruction is not safe to speculatively execute!"); + switch (Operator::getOpcode(I)) { + default: + // In doubt, be conservative. + return UINT_MAX; + case Instruction::GetElementPtr: + // GEPs are cheap if all indices are constant. + if (!cast(I)->hasAllConstantIndices()) + return UINT_MAX; + return 1; + case Instruction::Load: + case Instruction::Add: + case Instruction::Sub: + case Instruction::And: + case Instruction::Or: + case Instruction::Xor: + case Instruction::Shl: + case Instruction::LShr: + case Instruction::AShr: + case Instruction::ICmp: + case Instruction::Trunc: + case Instruction::ZExt: + case Instruction::SExt: + return 1; // These are all cheap. + + case Instruction::Call: + case Instruction::Select: + return 2; + } +} + /// DominatesMergePoint - If we have a merge point of an "if condition" as /// accepted above, return true if the specified value dominates the block. We /// don't handle the true generality of domination here, just a special case @@ -262,44 +300,7 @@ if (!isSafeToSpeculativelyExecute(I)) return false; - unsigned Cost = 0; - - switch (I->getOpcode()) { - default: return false; // Cannot hoist this out safely. - case Instruction::Load: - // We have to check to make sure there are no instructions before the - // load in its basic block, as we are going to hoist the load out to its - // predecessor. - if (PBB->getFirstNonPHIOrDbg() != I) - return false; - Cost = 1; - break; - case Instruction::GetElementPtr: - // GEPs are cheap if all indices are constant. - if (!cast(I)->hasAllConstantIndices()) - return false; - Cost = 1; - break; - case Instruction::Add: - case Instruction::Sub: - case Instruction::And: - case Instruction::Or: - case Instruction::Xor: - case Instruction::Shl: - case Instruction::LShr: - case Instruction::AShr: - case Instruction::ICmp: - case Instruction::Trunc: - case Instruction::ZExt: - case Instruction::SExt: - Cost = 1; - break; // These are all cheap and non-trapping instructions. - - case Instruction::Call: - case Instruction::Select: - Cost = 2; - break; - } + unsigned Cost = ComputeSpeculationCost(I); if (Cost > CostRemaining) return false; @@ -954,6 +955,20 @@ /// and an BB2 and the only successor of BB1 is BB2, hoist simple code /// (for now, restricted to a single instruction that's side effect free) from /// the BB1 into the branch block to speculatively execute it. +/// +/// Turn +/// BB: +/// %t1 = icmp +/// br i1 %t1, label %BB1, label %BB2 +/// BB1: +/// %t3 = add %t2, c +/// br label BB2 +/// BB2: +/// => +/// BB: +/// %t1 = icmp +/// %t4 = add %t2, c +/// %t3 = select i1 %t1, %t2, %t3 static bool SpeculativelyExecuteBB(BranchInst *BI, BasicBlock *BB1) { // Only speculatively execution a single instruction (not counting the // terminator) for now. @@ -970,8 +985,29 @@ return false; HInst = I; } - if (!HInst) - return false; + + BasicBlock *BIParent = BI->getParent(); + + // Check the instruction to be hoisted, if there is one. + if (HInst) { + // Don't hoist the instruction if it's unsafe or expensive. + if (!isSafeToSpeculativelyExecute(HInst)) + return false; + if (ComputeSpeculationCost(HInst) > PHINodeFoldingThreshold) + return false; + + // Do not hoist the instruction if any of its operands are defined but not + // used in this BB. The transformation will prevent the operand from + // being sunk into the use block. + for (User::op_iterator i = HInst->op_begin(), e = HInst->op_end(); + i != e; ++i) { + Instruction *OpI = dyn_cast(*i); + if (OpI && OpI->getParent() == BIParent && + !OpI->mayHaveSideEffects() && + !OpI->isUsedInBasicBlock(BIParent)) + return false; + } + } // Be conservative for now. FP select instruction can often be expensive. Value *BrCond = BI->getCondition(); @@ -986,106 +1022,78 @@ Invert = true; } - // Turn - // BB: - // %t1 = icmp - // br i1 %t1, label %BB1, label %BB2 - // BB1: - // %t3 = add %t2, c - // br label BB2 - // BB2: - // => - // BB: - // %t1 = icmp - // %t4 = add %t2, c - // %t3 = select i1 %t1, %t2, %t3 - switch (HInst->getOpcode()) { - default: return false; // Not safe / profitable to hoist. - case Instruction::Add: - case Instruction::Sub: - // Not worth doing for vector ops. - if (HInst->getType()->isVectorTy()) - return false; - break; - case Instruction::And: - case Instruction::Or: - case Instruction::Xor: - case Instruction::Shl: - case Instruction::LShr: - case Instruction::AShr: - // Don't mess with vector operations. - if (HInst->getType()->isVectorTy()) - return false; - break; // These are all cheap and non-trapping instructions. - } - - // If the instruction is obviously dead, don't try to predicate it. - if (HInst->use_empty()) { - HInst->eraseFromParent(); - return true; + // Collect interesting PHIs, and scan for hazards. + SmallSetVector, 4> PHIs; + BasicBlock *BB2 = BB1->getTerminator()->getSuccessor(0); + for (BasicBlock::iterator I = BB2->begin(); + PHINode *PN = dyn_cast(I); ++I) { + Value *BB1V = PN->getIncomingValueForBlock(BB1); + Value *BIParentV = PN->getIncomingValueForBlock(BIParent); + + // Skip PHIs which are trivial. + if (BB1V == BIParentV) + continue; + + // Check for saftey. + if (ConstantExpr *CE = dyn_cast(BB1V)) { + // An unfolded ConstantExpr could end up getting expanded into + // Instructions. Don't speculate this and another instruction at + // the same time. + if (HInst) + return false; + if (!isSafeToSpeculativelyExecute(CE)) + return false; + if (ComputeSpeculationCost(CE) > PHINodeFoldingThreshold) + return false; + } + + // Ok, we may insert a select for this PHI. + PHIs.insert(std::make_pair(BB1V, BIParentV)); } - // Can we speculatively execute the instruction? And what is the value - // if the condition is false? Consider the phi uses, if the incoming value - // from the "if" block are all the same V, then V is the value of the - // select if the condition is false. - BasicBlock *BIParent = BI->getParent(); - SmallVector PHIUses; - Value *FalseV = NULL; + // If there are no PHIs to process, bail early. This helps ensure idempotence + // as well. + if (PHIs.empty()) + return false; - BasicBlock *BB2 = BB1->getTerminator()->getSuccessor(0); - for (Value::use_iterator UI = HInst->use_begin(), E = HInst->use_end(); - UI != E; ++UI) { - // Ignore any user that is not a PHI node in BB2. These can only occur in - // unreachable blocks, because they would not be dominated by the instr. - PHINode *PN = dyn_cast(*UI); - if (!PN || PN->getParent() != BB2) - return false; - PHIUses.push_back(PN); - - Value *PHIV = PN->getIncomingValueForBlock(BIParent); - if (!FalseV) - FalseV = PHIV; - else if (FalseV != PHIV) - return false; // Inconsistent value when condition is false. - } - - assert(FalseV && "Must have at least one user, and it must be a PHI"); - - // Do not hoist the instruction if any of its operands are defined but not - // used in this BB. The transformation will prevent the operand from - // being sunk into the use block. - for (User::op_iterator i = HInst->op_begin(), e = HInst->op_end(); - i != e; ++i) { - Instruction *OpI = dyn_cast(*i); - if (OpI && OpI->getParent() == BIParent && - !OpI->isUsedInBasicBlock(BIParent)) - return false; - } + // If we get here, we can hoist the instruction and if-convert. + DEBUG(dbgs() << "SPECULATIVELY EXECUTING BB" << *BB1 << "\n";); - // If we get here, we can hoist the instruction. - BIParent->getInstList().splice(BI, BB1->getInstList(), HInst); + // Hoist the instruction. + if (HInst) + BIParent->getInstList().splice(BI, BB1->getInstList(), HInst); - // Create a select whose true value is the speculatively executed value and - // false value is the previously determined FalseV. + // Insert selects and rewrite the PHI operands. IRBuilder Builder(BI); - SelectInst *SI; - if (Invert) - SI = cast - (Builder.CreateSelect(BrCond, FalseV, HInst, - FalseV->getName() + "." + HInst->getName())); - else - SI = cast - (Builder.CreateSelect(BrCond, HInst, FalseV, - HInst->getName() + "." + FalseV->getName())); - - // Make the PHI node use the select for all incoming values for "then" and - // "if" blocks. - for (unsigned i = 0, e = PHIUses.size(); i != e; ++i) { - PHINode *PN = PHIUses[i]; - for (unsigned j = 0, ee = PN->getNumIncomingValues(); j != ee; ++j) - if (PN->getIncomingBlock(j) == BB1 || PN->getIncomingBlock(j) == BIParent) - PN->setIncomingValue(j, SI); + for (unsigned i = 0, e = PHIs.size(); i != e; ++i) { + Value *TrueV = PHIs[i].first; + Value *FalseV = PHIs[i].second; + + // Create a select whose true value is the speculatively executed value and + // false value is the previously determined FalseV. + SelectInst *SI; + if (Invert) + SI = cast + (Builder.CreateSelect(BrCond, FalseV, TrueV, + FalseV->getName() + "." + TrueV->getName())); + else + SI = cast + (Builder.CreateSelect(BrCond, TrueV, FalseV, + TrueV->getName() + "." + FalseV->getName())); + + // Make the PHI node use the select for all incoming values for "then" and + // "if" blocks. + for (BasicBlock::iterator I = BB2->begin(); + PHINode *PN = dyn_cast(I); ++I) { + unsigned BB1I = PN->getBasicBlockIndex(BB1); + unsigned BIParentI = PN->getBasicBlockIndex(BIParent); + Value *BB1V = PN->getIncomingValue(BB1I); + Value *BIParentV = PN->getIncomingValue(BIParentI); + if (TrueV == BB1V && FalseV == BIParentV) { + PN->setIncomingValue(BB1I, SI); + PN->setIncomingValue(BIParentI, SI); + } + } } ++NumSpeculations; @@ -2772,6 +2780,12 @@ if (SimplifyBranchOnICmpChain(BI, TD, Builder)) return true; + // If this basic block is ONLY a compare and a branch, and if a predecessor + // branches to us and one of our successors, fold the comparison into the + // predecessor and use logical operations to pick the right destination. + if (FoldBranchToCommonDest(BI)) + return SimplifyCFG(BB) | true; + // We have a conditional branch to two blocks that are only reachable // from BI. We know that the condbr dominates the two blocks, so see if // there is any identical code in the "then" and "else" blocks. If so, we @@ -2806,12 +2820,6 @@ if (FoldCondBranchOnPHI(BI, TD)) return SimplifyCFG(BB) | true; - // If this basic block is ONLY a compare and a branch, and if a predecessor - // branches to us and one of our successors, fold the comparison into the - // predecessor and use logical operations to pick the right destination. - if (FoldBranchToCommonDest(BI)) - return SimplifyCFG(BB) | true; - // Scan predecessor blocks for conditional branches. for (pred_iterator PI = pred_begin(BB), E = pred_end(BB); PI != E; ++PI) if (BranchInst *PBI = dyn_cast((*PI)->getTerminator())) Modified: llvm/trunk/test/Transforms/SimplifyCFG/2009-01-19-UnconditionalTrappingConstantExpr.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/SimplifyCFG/2009-01-19-UnconditionalTrappingConstantExpr.ll?rev=147630&r1=147629&r2=147630&view=diff ============================================================================== --- llvm/trunk/test/Transforms/SimplifyCFG/2009-01-19-UnconditionalTrappingConstantExpr.ll (original) +++ llvm/trunk/test/Transforms/SimplifyCFG/2009-01-19-UnconditionalTrappingConstantExpr.ll Thu Jan 5 17:58:56 2012 @@ -1,9 +1,14 @@ -; RUN: opt < %s -simplifycfg -S | grep {br i1 } | count 4 +; RUN: opt < %s -simplifycfg -S | FileCheck %s ; PR3354 ; Do not merge bb1 into the entry block, it might trap. @G = extern_weak global i32 +; CHECK: @test( +; CHECK: br i1 %tmp25 +; CHECK: bb1: +; CHECK: sdiv + define i32 @test(i32 %tmp21, i32 %tmp24) { %tmp25 = icmp sle i32 %tmp21, %tmp24 br i1 %tmp25, label %bb2, label %bb1 @@ -18,6 +23,11 @@ ret i32 927 } +; CHECK: @test2( +; CHECK: br i1 %tmp34 +; CHECK: bb5: +; CHECK: sdiv + define i32 @test2(i32 %tmp21, i32 %tmp24, i1 %tmp34) { br i1 %tmp34, label %bb5, label %bb6 Added: llvm/trunk/test/Transforms/SimplifyCFG/multiple-phis.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/SimplifyCFG/multiple-phis.ll?rev=147630&view=auto ============================================================================== --- llvm/trunk/test/Transforms/SimplifyCFG/multiple-phis.ll (added) +++ llvm/trunk/test/Transforms/SimplifyCFG/multiple-phis.ll Thu Jan 5 17:58:56 2012 @@ -0,0 +1,39 @@ +; RUN: opt -simplifycfg -S < %s | FileCheck %s + +; It's not worthwhile to if-convert one of the phi nodes and leave +; the other behind, because that still requires a branch. If +; SimplifyCFG if-converts one of the phis, it should do both. + +; CHECK: %div.high.addr.0 = select i1 %cmp1, i32 %div, i32 %high.addr.0 +; CHECK-NEXT: %low.0.add2 = select i1 %cmp1, i32 %low.0, i32 %add2 +; CHECK-NEXT: br label %while.cond + +define i32 @upper_bound(i32* %r, i32 %high, i32 %k) nounwind { +entry: + br label %while.cond + +while.cond: ; preds = %if.then, %if.else, %entry + %high.addr.0 = phi i32 [ %high, %entry ], [ %div, %if.then ], [ %high.addr.0, %if.else ] + %low.0 = phi i32 [ 0, %entry ], [ %low.0, %if.then ], [ %add2, %if.else ] + %cmp = icmp ult i32 %low.0, %high.addr.0 + br i1 %cmp, label %while.body, label %while.end + +while.body: ; preds = %while.cond + %add = add i32 %low.0, %high.addr.0 + %div = udiv i32 %add, 2 + %idxprom = zext i32 %div to i64 + %arrayidx = getelementptr inbounds i32* %r, i64 %idxprom + %0 = load i32* %arrayidx + %cmp1 = icmp ult i32 %k, %0 + br i1 %cmp1, label %if.then, label %if.else + +if.then: ; preds = %while.body + br label %while.cond + +if.else: ; preds = %while.body + %add2 = add i32 %div, 1 + br label %while.cond + +while.end: ; preds = %while.cond + ret i32 %low.0 +} Modified: llvm/trunk/test/Transforms/SimplifyCFG/select-gep.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/SimplifyCFG/select-gep.ll?rev=147630&r1=147629&r2=147630&view=diff ============================================================================== --- llvm/trunk/test/Transforms/SimplifyCFG/select-gep.ll (original) +++ llvm/trunk/test/Transforms/SimplifyCFG/select-gep.ll Thu Jan 5 17:58:56 2012 @@ -35,6 +35,6 @@ ret i8* %x.addr ; CHECK: @test2 -; CHECK: %x.addr = select i1 %cmp, i8* %incdec.ptr, i8* %y -; CHECK: ret i8* %x.addr +; CHECK: %incdec.ptr.y = select i1 %cmp, i8* %incdec.ptr, i8* %y +; CHECK: ret i8* %incdec.ptr.y } Modified: llvm/trunk/test/Transforms/SimplifyCFG/switch-masked-bits.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/SimplifyCFG/switch-masked-bits.ll?rev=147630&r1=147629&r2=147630&view=diff ============================================================================== --- llvm/trunk/test/Transforms/SimplifyCFG/switch-masked-bits.ll (original) +++ llvm/trunk/test/Transforms/SimplifyCFG/switch-masked-bits.ll Thu Jan 5 17:58:56 2012 @@ -15,8 +15,8 @@ ret i32 5 ; CHECK: @test1 ; CHECK: %cond = icmp eq i32 %i, 24 -; CHECK: %merge = select i1 %cond, i32 5, i32 0 -; CHECK: ret i32 %merge +; CHECK: %. = select i1 %cond, i32 5, i32 0 +; CHECK: ret i32 %. } Modified: llvm/trunk/test/Transforms/SimplifyCFG/switch-on-const-select.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/SimplifyCFG/switch-on-const-select.ll?rev=147630&r1=147629&r2=147630&view=diff ============================================================================== --- llvm/trunk/test/Transforms/SimplifyCFG/switch-on-const-select.ll (original) +++ llvm/trunk/test/Transforms/SimplifyCFG/switch-on-const-select.ll Thu Jan 5 17:58:56 2012 @@ -115,7 +115,7 @@ cont: ; CHECK: %lt = icmp slt i64 %x, %y %lt = icmp slt i64 %x, %y -; CHECK-NEXT: br i1 %lt, label %a, label %r +; CHECK-NEXT: select i1 %lt, i32 -1, i32 1 %qux = select i1 %lt, i32 0, i32 2 switch i32 %qux, label %bees [ i32 0, label %a From rafael.espindola at gmail.com Thu Jan 5 17:59:42 2012 From: rafael.espindola at gmail.com (Rafael Espindola) Date: Thu, 05 Jan 2012 23:59:42 -0000 Subject: [llvm-commits] [compiler-rt] r147632 - in /compiler-rt/trunk: lib/int_endianness.h test/Unit/endianness.h Message-ID: <20120105235942.871142A6C12C@llvm.org> Author: rafael Date: Thu Jan 5 17:59:42 2012 New Revision: 147632 URL: http://llvm.org/viewvc/llvm-project?rev=147632&view=rev Log: Fix build on minix. Patch by Ben Gras! Modified: compiler-rt/trunk/lib/int_endianness.h compiler-rt/trunk/test/Unit/endianness.h Modified: compiler-rt/trunk/lib/int_endianness.h URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/lib/int_endianness.h?rev=147632&r1=147631&r2=147632&view=diff ============================================================================== --- compiler-rt/trunk/lib/int_endianness.h (original) +++ compiler-rt/trunk/lib/int_endianness.h Thu Jan 5 17:59:42 2012 @@ -31,7 +31,7 @@ /* .. */ -#if defined(__FreeBSD__) || defined(__NetBSD__) || defined(__OpenBSD__) || defined(__DragonFly__) +#if defined(__FreeBSD__) || defined(__NetBSD__) || defined(__OpenBSD__) || defined(__DragonFly__) || defined(__minix) #include #if _BYTE_ORDER == _BIG_ENDIAN Modified: compiler-rt/trunk/test/Unit/endianness.h URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/test/Unit/endianness.h?rev=147632&r1=147631&r2=147632&view=diff ============================================================================== --- compiler-rt/trunk/test/Unit/endianness.h (original) +++ compiler-rt/trunk/test/Unit/endianness.h Thu Jan 5 17:59:42 2012 @@ -36,7 +36,7 @@ /* .. */ -#if defined(__FreeBSD__) || defined(__NetBSD__) || defined(__OpenBSD__) || defined(__DragonflyBSD__) +#if defined(__FreeBSD__) || defined(__NetBSD__) || defined(__OpenBSD__) || defined(__DragonflyBSD__) || defined(__minix) #include #if _BYTE_ORDER == _BIG_ENDIAN From rafael.espindola at gmail.com Thu Jan 5 18:05:05 2012 From: rafael.espindola at gmail.com (=?ISO-8859-1?Q?Rafael_=C1vila_de_Esp=EDndola?=) Date: Thu, 05 Jan 2012 19:05:05 -0500 Subject: [llvm-commits] [LLVMdev] [PATCH] [compiler-rt] Minix (w.r.t. svn r147606) In-Reply-To: References: Message-ID: <4F063AB1.7060105@gmail.com> On 05/01/12 09:07 AM, ben gras wrote: > Dear all, > > I hope this is the right list :). I'd like to submit the attached patch > for committing. We normally use llvm-commits for patches, but that is fine. I committed it as 147632. > The attached patch are the only required changes to make the latest > compiler-rt build and pass tests (except for 2 currently ignored > tests..) on Minix. > Thanks, Rafael From kcc at google.com Thu Jan 5 20:12:25 2012 From: kcc at google.com (Kostya Serebryany) Date: Fri, 06 Jan 2012 02:12:25 -0000 Subject: [llvm-commits] [compiler-rt] r147647 - in /compiler-rt/trunk/lib/asan: asan_allocator.cc asan_internal.h asan_linux.cc asan_mac.cc asan_rtl.cc Message-ID: <20120106021225.CB4DF2A6C12C@llvm.org> Author: kcc Date: Thu Jan 5 20:12:25 2012 New Revision: 147647 URL: http://llvm.org/viewvc/llvm-project?rev=147647&view=rev Log: [asan] move more stuff to OS-specific files Modified: compiler-rt/trunk/lib/asan/asan_allocator.cc compiler-rt/trunk/lib/asan/asan_internal.h compiler-rt/trunk/lib/asan/asan_linux.cc compiler-rt/trunk/lib/asan/asan_mac.cc compiler-rt/trunk/lib/asan/asan_rtl.cc Modified: compiler-rt/trunk/lib/asan/asan_allocator.cc URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/lib/asan/asan_allocator.cc?rev=147647&r1=147646&r2=147647&view=diff ============================================================================== --- compiler-rt/trunk/lib/asan/asan_allocator.cc (original) +++ compiler-rt/trunk/lib/asan/asan_allocator.cc Thu Jan 5 20:12:25 2012 @@ -35,10 +35,6 @@ #include "asan_thread.h" #include "asan_thread_registry.h" -#include -#include -#include - namespace __asan { #define REDZONE FLAG_redzone Modified: compiler-rt/trunk/lib/asan/asan_internal.h URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/lib/asan/asan_internal.h?rev=147647&r1=147646&r2=147647&view=diff ============================================================================== --- compiler-rt/trunk/lib/asan/asan_internal.h (original) +++ compiler-rt/trunk/lib/asan/asan_internal.h Thu Jan 5 20:12:25 2012 @@ -99,6 +99,8 @@ void *AsanMmapSomewhereOrDie(size_t size, const char *where); void AsanUnmapOrDie(void *ptr, size_t size); +void AsanDisableCoreDumper(); + ssize_t AsanRead(int fd, void *buf, size_t count); ssize_t AsanWrite(int fd, const void *buf, size_t count); int AsanClose(int fd); Modified: compiler-rt/trunk/lib/asan/asan_linux.cc URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/lib/asan/asan_linux.cc?rev=147647&r1=147646&r2=147647&view=diff ============================================================================== --- compiler-rt/trunk/lib/asan/asan_linux.cc (original) +++ compiler-rt/trunk/lib/asan/asan_linux.cc Thu Jan 5 20:12:25 2012 @@ -244,6 +244,12 @@ CHECK(AddrIsInStack((uintptr_t)&attr)); } +void AsanDisableCoreDumper() { + struct rlimit nocore; + nocore.rlim_cur = 0; + nocore.rlim_max = 0; + setrlimit(RLIMIT_CORE, &nocore); +} } // namespace __asan Modified: compiler-rt/trunk/lib/asan/asan_mac.cc URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/lib/asan/asan_mac.cc?rev=147647&r1=147646&r2=147647&view=diff ============================================================================== --- compiler-rt/trunk/lib/asan/asan_mac.cc (original) +++ compiler-rt/trunk/lib/asan/asan_mac.cc Thu Jan 5 20:12:25 2012 @@ -22,6 +22,7 @@ #include "asan_thread_registry.h" #include +#include #include #include #include @@ -113,6 +114,13 @@ CHECK(AddrIsInStack((uintptr_t)&local)); } +void AsanDisableCoreDumper() { + struct rlimit nocore; + nocore.rlim_cur = 0; + nocore.rlim_max = 0; + setrlimit(RLIMIT_CORE, &nocore); +} + // Support for the following functions from libdispatch on Mac OS: // dispatch_async_f() // dispatch_async() Modified: compiler-rt/trunk/lib/asan/asan_rtl.cc URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/lib/asan/asan_rtl.cc?rev=147647&r1=147646&r2=147647&view=diff ============================================================================== --- compiler-rt/trunk/lib/asan/asan_rtl.cc (original) +++ compiler-rt/trunk/lib/asan/asan_rtl.cc Thu Jan 5 20:12:25 2012 @@ -26,7 +26,6 @@ #include #include -#include #include #include #include @@ -40,9 +39,6 @@ #ifndef ANDROID #include #endif -#include -#include -#include // must not include on Linux namespace __asan { @@ -775,10 +771,7 @@ if (__WORDSIZE == 64) { // Disable core dumper -- it makes little sense to dump 16T+ core. - struct rlimit nocore; - nocore.rlim_cur = 0; - nocore.rlim_max = 0; - setrlimit(RLIMIT_CORE, &nocore); + AsanDisableCoreDumper(); } { From echristo at apple.com Thu Jan 5 22:35:24 2012 From: echristo at apple.com (Eric Christopher) Date: Fri, 06 Jan 2012 04:35:24 -0000 Subject: [llvm-commits] [llvm] r147651 - in /llvm/trunk/lib/CodeGen/AsmPrinter: DwarfAccelTable.cpp DwarfAccelTable.h DwarfCompileUnit.cpp DwarfCompileUnit.h DwarfDebug.cpp Message-ID: <20120106043524.3BF6B2A6C12C@llvm.org> Author: echristo Date: Thu Jan 5 22:35:23 2012 New Revision: 147651 URL: http://llvm.org/viewvc/llvm-project?rev=147651&view=rev Log: As part of the ongoing work in finalizing the accelerator tables, extend the debug type accelerator tables to contain the tag and a flag stating whether or not a compound type is a complete type. rdar://10652330 Modified: llvm/trunk/lib/CodeGen/AsmPrinter/DwarfAccelTable.cpp llvm/trunk/lib/CodeGen/AsmPrinter/DwarfAccelTable.h llvm/trunk/lib/CodeGen/AsmPrinter/DwarfCompileUnit.cpp llvm/trunk/lib/CodeGen/AsmPrinter/DwarfCompileUnit.h llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp Modified: llvm/trunk/lib/CodeGen/AsmPrinter/DwarfAccelTable.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/DwarfAccelTable.cpp?rev=147651&r1=147650&r2=147651&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/AsmPrinter/DwarfAccelTable.cpp (original) +++ llvm/trunk/lib/CodeGen/AsmPrinter/DwarfAccelTable.cpp Thu Jan 5 22:35:23 2012 @@ -42,16 +42,22 @@ HeaderData(atom) { } +// The length of the header data is always going to be 4 + 4 + 4*NumAtoms. +DwarfAccelTable::DwarfAccelTable(std::vector &atomList) : + Header(8 + (atomList.size() * 4)), + HeaderData(atomList) { +} + DwarfAccelTable::~DwarfAccelTable() { - for (size_t i = 0, e = Data.size() ; i < e; ++i) + for (size_t i = 0, e = Data.size(); i < e; ++i) delete Data[i]; } -void DwarfAccelTable::AddName(StringRef Name, DIE* die) { +void DwarfAccelTable::AddName(StringRef Name, DIE* die, char Flags) { // If the string is in the list already then add this die to the list // otherwise add a new one. - DIEArray &DIEs = Entries[Name]; - DIEs.push_back(die); + DataArray &DIEs = Entries[Name]; + DIEs.push_back(new HashDataContents(die, Flags)); } void DwarfAccelTable::ComputeBucketCount(void) { @@ -76,15 +82,16 @@ namespace { // DIESorter - comparison predicate that sorts DIEs by their offset. struct DIESorter { - bool operator()(DIE *A, DIE *B) const { - return A->getOffset() < B->getOffset(); + bool operator()(const struct DwarfAccelTable::HashDataContents *A, + const struct DwarfAccelTable::HashDataContents *B) const { + return A->Die->getOffset() < B->Die->getOffset(); } }; } void DwarfAccelTable::FinalizeTable(AsmPrinter *Asm, const char *Prefix) { // Create the individual hash data outputs. - for (StringMap::iterator + for (StringMap::iterator EI = Entries.begin(), EE = Entries.end(); EI != EE; ++EI) { struct HashData *Entry = new HashData((*EI).getKeyData()); @@ -93,10 +100,10 @@ (*EI).second.erase(std::unique((*EI).second.begin(), (*EI).second.end()), (*EI).second.end()); - for (DIEArray::const_iterator DI = (*EI).second.begin(), + for (DataArray::const_iterator DI = (*EI).second.begin(), DE = (*EI).second.end(); DI != DE; ++DI) - Entry->addOffset((*DI)->getOffset()); + Entry->addData((*DI)); Data.push_back(Entry); } @@ -202,11 +209,18 @@ Asm->EmitSectionOffset(D->getStringPoolEntry((*HI)->Str), D->getStringPool()); Asm->OutStreamer.AddComment("Num DIEs"); - Asm->EmitInt32((*HI)->DIEOffsets.size()); - for (std::vector::const_iterator - DI = (*HI)->DIEOffsets.begin(), DE = (*HI)->DIEOffsets.end(); + Asm->EmitInt32((*HI)->Data.size()); + for (std::vector::const_iterator + DI = (*HI)->Data.begin(), DE = (*HI)->Data.end(); DI != DE; ++DI) { - Asm->EmitInt32((*DI)); + // Emit the DIE offset + Asm->EmitInt32((*DI)->Die->getOffset()); + // If we have multiple Atoms emit that info too. + // FIXME: A bit of a hack, we either emit only one atom or all info. + if (HeaderData.Atoms.size() > 1) { + Asm->EmitInt16((*DI)->Die->getTag()); + Asm->EmitInt8((*DI)->Flags); + } } // Emit a 0 to terminate the data unless we have a hash collision. if (PrevHash != (*HI)->HashValue) @@ -242,10 +256,10 @@ HeaderData.print(O); O << "Entries: \n"; - for (StringMap::const_iterator + for (StringMap::const_iterator EI = Entries.begin(), EE = Entries.end(); EI != EE; ++EI) { O << "Name: " << (*EI).getKeyData() << "\n"; - for (DIEArray::const_iterator DI = (*EI).second.begin(), + for (DataArray::const_iterator DI = (*EI).second.begin(), DE = (*EI).second.end(); DI != DE; ++DI) (*DI)->print(O); Modified: llvm/trunk/lib/CodeGen/AsmPrinter/DwarfAccelTable.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/DwarfAccelTable.h?rev=147651&r1=147650&r2=147651&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/AsmPrinter/DwarfAccelTable.h (original) +++ llvm/trunk/lib/CodeGen/AsmPrinter/DwarfAccelTable.h Thu Jan 5 22:35:23 2012 @@ -22,6 +22,7 @@ #include "llvm/Support/ErrorHandling.h" #include "llvm/Support/Format.h" #include "llvm/Support/FormattedStream.h" +#include "DIE.h" #include #include @@ -134,6 +135,14 @@ eAtomTypeTypeFlags = 5u // Flags from enum TypeFlags }; + enum TypeFlags { + eTypeFlagClassMask = 0x0000000fu, + + // Always set for C++, only set for ObjC if this is the + // @implementation for a class. + eTypeFlagClassIsImplementation = ( 1u << 1 ) + }; + // Make these public so that they can be used as a general interface to // the class. struct Atom { @@ -144,7 +153,7 @@ static const char * AtomTypeString(enum AtomType); #ifndef NDEBUG void print(raw_ostream &O) { - O << "Type: " << dwarf::TagString(type) << "\n" + O << "Type: " << AtomTypeString(type) << "\n" << "Form: " << dwarf::FormEncodingString(form) << "\n"; } void dump() { @@ -159,6 +168,13 @@ uint32_t die_offset_base; std::vector Atoms; + TableHeaderData(std::vector &AtomList, + uint32_t offset = 0) : + die_offset_base(offset) { + for (size_t i = 0, e = AtomList.size(); i != e; ++i) + Atoms.push_back(AtomList[i]); + } + TableHeaderData(DwarfAccelTable::Atom Atom, uint32_t offset = 0) : die_offset_base(offset) { Atoms.push_back(Atom); @@ -184,15 +200,32 @@ // uint32_t str_offset // uint32_t hash_data_count // HashData[hash_data_count] +public: + struct HashDataContents { + DIE *Die; // Offsets + char Flags; // Specific flags to output + + HashDataContents(DIE *D, char Flags) : + Die(D), + Flags(Flags) { }; + #ifndef NDEBUG + void print(raw_ostream &O) const { + O << " Offset: " << Die->getOffset() << "\n"; + O << " Tag: " << dwarf::TagString(Die->getTag()) << "\n"; + O << " Flags: " << Flags << "\n"; + } + #endif + }; +private: struct HashData { StringRef Str; uint32_t HashValue; MCSymbol *Sym; - std::vector DIEOffsets; // offsets + std::vector Data; // offsets HashData(StringRef S) : Str(S) { HashValue = DwarfAccelTable::HashDJB(S); } - void addOffset(uint32_t off) { DIEOffsets.push_back(off); } + void addData(struct HashDataContents *Datum) { Data.push_back(Datum); } #ifndef NDEBUG void print(raw_ostream &O) { O << "Name: " << Str << "\n"; @@ -201,8 +234,11 @@ if (Sym) Sym->print(O); else O << ""; O << "\n"; - for (size_t i = 0; i < DIEOffsets.size(); i++) - O << " Offset: " << DIEOffsets[i] << "\n"; + for (size_t i = 0; i < Data.size(); i++) { + O << " Offset: " << Data[i]->Die->getOffset() << "\n"; + O << " Tag: " << dwarf::TagString(Data[i]->Die->getTag()) << "\n"; + O << " Flags: " << Data[i]->Flags << "\n"; + } } void dump() { print(dbgs()); @@ -226,8 +262,8 @@ std::vector Data; // String Data - typedef std::vector DIEArray; - typedef StringMap StringEntries; + typedef std::vector DataArray; + typedef StringMap StringEntries; StringEntries Entries; // Buckets/Hashes/Offsets @@ -238,9 +274,10 @@ // Public Implementation public: - DwarfAccelTable(DwarfAccelTable::Atom Atom); + DwarfAccelTable(DwarfAccelTable::Atom); + DwarfAccelTable(std::vector &); ~DwarfAccelTable(); - void AddName(StringRef, DIE*); + void AddName(StringRef, DIE*, char = 0); void FinalizeTable(AsmPrinter *, const char *); void Emit(AsmPrinter *, MCSymbol *, DwarfDebug *); #ifndef NDEBUG Modified: llvm/trunk/lib/CodeGen/AsmPrinter/DwarfCompileUnit.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/DwarfCompileUnit.cpp?rev=147651&r1=147650&r2=147651&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/AsmPrinter/DwarfCompileUnit.cpp (original) +++ llvm/trunk/lib/CodeGen/AsmPrinter/DwarfCompileUnit.cpp Thu Jan 5 22:35:23 2012 @@ -13,6 +13,7 @@ #define DEBUG_TYPE "dwarfdebug" +#include "DwarfAccelTable.h" #include "DwarfCompileUnit.h" #include "DwarfDebug.h" #include "llvm/Constants.h" @@ -608,8 +609,20 @@ } // If this is a named finished type then include it in the list of types // for the accelerator tables. - if (!Ty.getName().empty() && !Ty.isForwardDecl()) - addAccelType(Ty.getName(), TyDIE); + if (!Ty.getName().empty() && !Ty.isForwardDecl()) { + bool IsImplementation = 0; + if (Ty.isCompositeType()) { + DICompositeType CT(Ty); + IsImplementation = (CT.getRunTimeLang() == 0) || + CT.isObjcClassComplete();; + } + + addAccelType(Ty.getName(), + std::make_pair(TyDIE, + (IsImplementation ? + DwarfAccelTable::eTypeFlagClassIsImplementation : + 0))); + } addToContextOwner(TyDIE, Ty.getContext()); return TyDIE; Modified: llvm/trunk/lib/CodeGen/AsmPrinter/DwarfCompileUnit.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/DwarfCompileUnit.h?rev=147651&r1=147650&r2=147651&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/AsmPrinter/DwarfCompileUnit.h (original) +++ llvm/trunk/lib/CodeGen/AsmPrinter/DwarfCompileUnit.h Thu Jan 5 22:35:23 2012 @@ -65,7 +65,7 @@ StringMap > AccelNames; StringMap > AccelObjC; StringMap > AccelNamespace; - StringMap > AccelTypes; + StringMap > > AccelTypes; /// DIEBlocks - A list of all the DIEBlocks in use. std::vector DIEBlocks; @@ -93,7 +93,8 @@ const StringMap > &getAccelNamespace() const { return AccelNamespace; } - const StringMap > &getAccelTypes() const { + const StringMap > > + &getAccelTypes() const { return AccelTypes; } @@ -119,8 +120,8 @@ std::vector &DIEs = AccelNamespace[Name]; DIEs.push_back(Die); } - void addAccelType(StringRef Name, DIE *Die) { - std::vector &DIEs = AccelTypes[Name]; + void addAccelType(StringRef Name, std::pair Die) { + std::vector > &DIEs = AccelTypes[Name]; DIEs.push_back(Die); } Modified: llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp?rev=147651&r1=147650&r2=147651&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp (original) +++ llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp Thu Jan 5 22:35:23 2012 @@ -1844,19 +1844,26 @@ /// emitAccelTypes() - Emit type dies into a hashed accelerator table. void DwarfDebug::emitAccelTypes() { - DwarfAccelTable AT(DwarfAccelTable::Atom(DwarfAccelTable::eAtomTypeDIEOffset, - dwarf::DW_FORM_data4)); + std::vector Atoms; + Atoms.push_back(DwarfAccelTable::Atom(DwarfAccelTable::eAtomTypeDIEOffset, + dwarf::DW_FORM_data4)); + Atoms.push_back(DwarfAccelTable::Atom(DwarfAccelTable::eAtomTypeTag, + dwarf::DW_FORM_data2)); + Atoms.push_back(DwarfAccelTable::Atom(DwarfAccelTable::eAtomTypeTypeFlags, + dwarf::DW_FORM_data1)); + DwarfAccelTable AT(Atoms); for (DenseMap::iterator I = CUMap.begin(), E = CUMap.end(); I != E; ++I) { CompileUnit *TheCU = I->second; - const StringMap > &Names = TheCU->getAccelTypes(); - for (StringMap >::const_iterator + const StringMap > > &Names + = TheCU->getAccelTypes(); + for (StringMap > >::const_iterator GI = Names.begin(), GE = Names.end(); GI != GE; ++GI) { const char *Name = GI->getKeyData(); - std::vector Entities = GI->second; - for (std::vector::const_iterator DI = Entities.begin(), - DE= Entities.end(); DI !=DE; ++DI) - AT.AddName(Name, (*DI)); + std::vector > Entities = GI->second; + for (std::vector >::const_iterator DI + = Entities.begin(), DE = Entities.end(); DI !=DE; ++DI) + AT.AddName(Name, (*DI).first, (*DI).second); } } From banderson at mozilla.com Thu Jan 5 17:54:21 2012 From: banderson at mozilla.com (Brian Anderson) Date: Thu, 05 Jan 2012 15:54:21 -0800 (PST) Subject: [llvm-commits] [PATCH] Segmented stack fixes, support for Mac, Win32, FreeBSD In-Reply-To: Message-ID: <15219a20-6492-46b9-804e-7b198c586ca7@zimbra1.shared.sjc1.mozilla.com> This series provides fixes to segmented stacks and adds support for x86 32-bit and 64-bit Mac, 32-bit Win32 and 64-bit FreeBSD. It builds on the __morestack mechanism implemented for Linux by gcc and LLVM. For each platform I had to pick a slot in the TCB to store the stack boundary. This is a difficult decision since that is precious real estate. On Win32 I am using the pvArbitrary slot, which is reserved for application use. On FreeBSD it uses tcb_spare. On Mac I have provisionally picked slot 90, which appears to already be reserved for JavaScript Core. I welcome any suggestions for a better location to store the stack boundary. The new operating systems only support frames of static size, as that is all that is needed by the Rust language. Regards, Brian Anderson -------------- next part -------------- A non-text attachment was scrubbed... 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Name: 0007-Support-segmented-stacks-on-win32.patch Type: text/x-patch Size: 3190 bytes Desc: not available Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20120105/9281d4ed/attachment-0017.bin -------------- next part -------------- A non-text attachment was scrubbed... Name: 0008-Support-segmented-stacks-on-64-bit-FreeBSD.patch Type: text/x-patch Size: 2276 bytes Desc: not available Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20120105/9281d4ed/attachment-0018.bin -------------- next part -------------- A non-text attachment was scrubbed... Name: 0009-Add-tests-for-mac-segmented-stacks.patch Type: text/x-patch Size: 9968 bytes Desc: not available Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20120105/9281d4ed/attachment-0019.bin -------------- next part -------------- A non-text attachment was scrubbed... Name: 0010-Add-tests-for-win32-segmented-stacks.patch Type: text/x-patch Size: 3224 bytes Desc: not available Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20120105/9281d4ed/attachment-0020.bin -------------- next part -------------- A non-text attachment was scrubbed... Name: 0011-Add-tests-for-FreeBSD-segmented-stacks.patch Type: text/x-patch Size: 3459 bytes Desc: not available Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20120105/9281d4ed/attachment-0021.bin From evan.cheng at apple.com Fri Jan 6 01:21:46 2012 From: evan.cheng at apple.com (Evan Cheng) Date: Thu, 05 Jan 2012 23:21:46 -0800 Subject: [llvm-commits] x86 branch sequence optimization in LLVM code gen: please review In-Reply-To: References: <021AD592C708E24FA11FD214489EC9BE0123F25260@hasmsx501.ger.corp.intel.com> <021AD592C708E24FA11FD214489EC9BE0123F95DDF@hasmsx501.ger.corp.intel.com> <90F01864-DEB5-4DEA-B8E2-625EF4449126@apple.com> <021AD592C708E24FA11FD214489EC9BE0123FE98C8@hasmsx501.ger.corp.intel.com> <021AD592C708E24FA11FD214489EC9BE01269D1FA3@hasmsx501.ger.corp.intel.com> <7DE70FDACDE4CD4887C4278C12A2E305057C2C@HASMSX104.ger.corp.intel.com> Message-ID: <590783A1-ADAE-4CD2-B249-958B85693164@apple.com> On Jan 5, 2012, at 2:01 AM, Chandler Carruth wrote: > On Thu, Jan 5, 2012 at 1:53 AM, Umansky, Victor wrote: > Well, if it would be possible to change LLVM intrinsic prototype ? then you?re right, no instruction combining were required. > > However until this will be done in LLVM spec ? the optimization is in place. > > > There is no spec, it is a change to LLVM's intrinsics, you can post a patch to do this to this mailing list. =] You need to change the intrinsic definition, update any code that reasons about that intrinsic, add auto-upgrade logic to upgrade old IR inputs from the old intrinsic to the new intrinsic, and teach the frontends to emit the new one. It's a fair amount of code, but none of it hard. > > Please don't leave bad code checked into the codegen layer. We need to fix this the correct way if/when we find the correct way to fix it. Thus far, updating the LLVM intrinsics is looking very promising. I agree with Chandler. Victor, can you follow his suggestion and fix this properly? Sorry, I didn't think it through when I was reviewing the patch. Evan -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20120105/f35cb79f/attachment.html From eli.bendersky at intel.com Fri Jan 6 01:49:17 2012 From: eli.bendersky at intel.com (Eli Bendersky) Date: Fri, 06 Jan 2012 07:49:17 -0000 Subject: [llvm-commits] [llvm] r147654 - /llvm/trunk/lib/ExecutionEngine/RuntimeDyld/RuntimeDyldMachO.cpp Message-ID: <20120106074917.4AE722A6C12C@llvm.org> Author: eliben Date: Fri Jan 6 01:49:17 2012 New Revision: 147654 URL: http://llvm.org/viewvc/llvm-project?rev=147654&view=rev Log: Fix typo in string Modified: llvm/trunk/lib/ExecutionEngine/RuntimeDyld/RuntimeDyldMachO.cpp Modified: llvm/trunk/lib/ExecutionEngine/RuntimeDyld/RuntimeDyldMachO.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/ExecutionEngine/RuntimeDyld/RuntimeDyldMachO.cpp?rev=147654&r1=147653&r2=147654&view=diff ============================================================================== --- llvm/trunk/lib/ExecutionEngine/RuntimeDyld/RuntimeDyldMachO.cpp (original) +++ llvm/trunk/lib/ExecutionEngine/RuntimeDyld/RuntimeDyldMachO.cpp Fri Jan 6 01:49:17 2012 @@ -451,7 +451,7 @@ if (!SymtabLCI) return Error("no symbol table found in object"); if (!SegmentLCI) - return Error("no symbol table found in object"); + return Error("no segments found in object"); // Read and register the symbol table data. InMemoryStruct SymtabLC; From STPWORLD at narod.ru Fri Jan 6 03:02:33 2012 From: STPWORLD at narod.ru (Stepan Dyatkovskiy) Date: Fri, 06 Jan 2012 13:02:33 +0400 Subject: [llvm-commits] [LLVM, SwitchInst, case ranges] Auxiliary patch #1 In-Reply-To: <4DD01E8C-836C-43EA-BDE4-329A223E2EB3@apple.com> References: <4EAA9B5D.802@narod.ru> <4EAA9DE8.80000@free.fr> <485181319805488@web67.yandex.ru> <4EAB079D.6000606@free.fr> <4EB18F12.6060409@narod.ru> <4EB7C319.1000709@narod.ru> <4EDE7D75.704@narod.ru> <4EDFD0F4.1040204@narod.ru> <4EE25B61.9070006@narod.ru> <4EE5C06C.3050705@narod.ru> <333531323974498@web57.yandex.ru> <4EEB9C52.1050301@narod.ru> <4EF37B6B.6000205@narod.ru> <4EFA0748.9080702@narod.ru> <4EFCAA6A.20203@narod.ru> <610731325498362@web6.yandex.ru> <200871325616668@web103.yandex.ru> <5633CF27-DD22-4595-A197-DFFCC56B6342@apple.com> <4F058C43.7020908@narod.ru> <6F0FECE5-F12D-4F5E-890B-385AADCB563B@apple.com> <989681325785425@web41.yandex.ru> <9DD2B823-1EC4-4A2B-BF52-73DDC8A6B923@apple.com> <30291325791059@web135.yandex.ru> <4DD01E8C-836C-43EA-BDE4-329A223E2EB3@apple.com> Message-ID: <790551325840553@web126.yandex.ru> > My half-baked thought was that we could store 1, 4...7, 12 ?as [1, <4, 7>, 12], just to distinguish ranges from pairs of scalar values. May be ConstantStruct? Something like this: struct { // 0-level struct represents set of values and ranges. unsigned v1 = 1; struct { // 1-level struct represents ranges, and must have two fields only: "low" and "high". unsigned low = 4; unsigned high = 7; } v2; unsigned v3 = 12; } >> ?CaseValue = SI->getOperand(SomeIndex); // We use User methods keeping SwitchInst format in mind. >> ?CaseSuccessor = SI->getSuccessor(SomeIndex2); // We use TerminatorInst methods keeping what each successor means in mind. >> ?with >> ?CaseValue = SI->getCaseValue(SomeCaseValueIndex); >> ?Successor = SI->getCaseSuccessor(SomeSuccessorIndex); > > I may not be understanding what you mean, but I think that getting rid of getOperand() (hiding it in SwitchInst) makes sense. ?getSuccessor() still needs to exist though. Now 0-case value is not a case value instead. It is a Condition. The same with successors. Zero-indexed successor is default destination (not a case successor). We store items with different types and roles in single collection. I propose totally separate this terms on SwitchInst level: to use getCondition() if you need condition, use getDefaultDest() for default destination. Use getCaseValue only for resolving some case value. So getCaseValue(0) means that I need first case value (not condition) and getCaseSuccessor(0) means that I need successors for first case value (not default dest). Ideally, developer that uses SwitchInst should know nothing about internal operators format. -Stepan. From daniel at zuster.org Fri Jan 6 09:14:54 2012 From: daniel at zuster.org (Daniel Dunbar) Date: Fri, 06 Jan 2012 15:14:54 -0000 Subject: [llvm-commits] [zorg] r147656 - in /zorg/trunk/lnt/lnt/server: reporting/runs.py ui/views.py Message-ID: <20120106151455.06E472A6C12F@llvm.org> Author: ddunbar Date: Fri Jan 6 09:14:54 2012 New Revision: 147656 URL: http://llvm.org/viewvc/llvm-project?rev=147656&view=rev Log: [lnt/v0.4] lnt.server.reporting: Fix the url in v4 email reports. Modified: zorg/trunk/lnt/lnt/server/reporting/runs.py zorg/trunk/lnt/lnt/server/ui/views.py Modified: zorg/trunk/lnt/lnt/server/reporting/runs.py URL: http://llvm.org/viewvc/llvm-project/zorg/trunk/lnt/lnt/server/reporting/runs.py?rev=147656&r1=147655&r2=147656&view=diff ============================================================================== --- zorg/trunk/lnt/lnt/server/reporting/runs.py (original) +++ zorg/trunk/lnt/lnt/server/reporting/runs.py Fri Jan 6 09:14:54 2012 @@ -114,7 +114,7 @@ if baseurl[-1] == '/': baseurl = baseurl[:-1] - report_url = """%s/%d""" % (baseurl, run.id) + report_url = """%s/v4/nt/%d""" % (baseurl, run.id) print >>report, report_url print >>report, """Nickname: %s:%d""" % (machine.name, machine.id) if 'name' in machine_parameters: Modified: zorg/trunk/lnt/lnt/server/ui/views.py URL: http://llvm.org/viewvc/llvm-project/zorg/trunk/lnt/lnt/server/ui/views.py?rev=147656&r1=147655&r2=147656&view=diff ============================================================================== --- zorg/trunk/lnt/lnt/server/ui/views.py (original) +++ zorg/trunk/lnt/lnt/server/ui/views.py Fri Jan 6 09:14:54 2012 @@ -14,7 +14,7 @@ from flask import url_for from lnt.db import perfdb -from lnt.server.ui.globals import v4_url_for +from lnt.server.ui.globals import db_url_for, v4_url_for frontend = flask.Module(__name__) @@ -648,7 +648,7 @@ _, _, html_report = NTEmailReport.getReport( result=None, db=db, run=run, - baseurl=v4_url_for('v4_overview', _external=True), + baseurl=db_url_for('index', _external=True), was_added=True, will_commit=True, only_html_body=False) return make_response(html_report) @@ -663,7 +663,7 @@ _, text_report, _ = NTEmailReport.getReport( result=None, db=db, run=run, - baseurl=v4_url_for('v4_overview', _external=True), + baseurl=db_url_for('index', _external=True), was_added=True, will_commit=True, only_html_body=True) response = make_response(text_report) @@ -718,7 +718,7 @@ # webapp UI to be easy to correlate with the email reports. _, text_report, html_report = NTEmailReport.getReport( result=None, db=db, run=run, - baseurl=v4_url_for('v4_overview', _external=True), + baseurl=db_url_for('index', _external=True), was_added=True, will_commit=True, only_html_body=True) return render_template("v4_run.html", ts=ts, run=run, compare_to=compare_to, From kcc at google.com Fri Jan 6 12:02:04 2012 From: kcc at google.com (Kostya Serebryany) Date: Fri, 06 Jan 2012 18:02:04 -0000 Subject: [llvm-commits] [compiler-rt] r147665 - in /compiler-rt/trunk/lib/asan: Makefile.old asan_rtl.cc Message-ID: <20120106180204.8D4912A6C12F@llvm.org> Author: kcc Date: Fri Jan 6 12:02:04 2012 New Revision: 147665 URL: http://llvm.org/viewvc/llvm-project?rev=147665&view=rev Log: [asan] cleanup: remove the SIGILL-related code (rt part) Modified: compiler-rt/trunk/lib/asan/Makefile.old compiler-rt/trunk/lib/asan/asan_rtl.cc Modified: compiler-rt/trunk/lib/asan/Makefile.old URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/lib/asan/Makefile.old?rev=147665&r1=147664&r2=147665&view=diff ============================================================================== --- compiler-rt/trunk/lib/asan/Makefile.old (original) +++ compiler-rt/trunk/lib/asan/Makefile.old Fri Jan 6 12:02:04 2012 @@ -77,7 +77,6 @@ ASAN_STACK=1 ASAN_GLOBALS=1 -ASAN_USE_CALL=1 ASAN_SCALE=0 # default will be used ASAN_OFFSET=-1 #default will be used ASAN_UAR=0 @@ -140,7 +139,6 @@ $(BLACKLIST) \ -mllvm -asan-stack=$(ASAN_STACK) \ -mllvm -asan-globals=$(ASAN_GLOBALS) \ - -mllvm -asan-use-call=$(ASAN_USE_CALL) \ -mllvm -asan-mapping-scale=$(ASAN_SCALE) \ -mllvm -asan-mapping-offset-log=$(ASAN_OFFSET) \ -mllvm -asan-use-after-return=$(ASAN_UAR) \ Modified: compiler-rt/trunk/lib/asan/asan_rtl.cc URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/lib/asan/asan_rtl.cc?rev=147665&r1=147664&r2=147665&view=diff ============================================================================== --- compiler-rt/trunk/lib/asan/asan_rtl.cc (original) +++ compiler-rt/trunk/lib/asan/asan_rtl.cc Fri Jan 6 12:02:04 2012 @@ -60,7 +60,6 @@ uintptr_t FLAG_large_malloc; bool FLAG_lazy_shadow; bool FLAG_handle_segv; -bool FLAG_handle_sigill; bool FLAG_replace_str; bool FLAG_replace_intrin; bool FLAG_replace_cfallocator; // Used on Mac only. @@ -335,23 +334,6 @@ ShowStatsAndAbort(); } -static void ASAN_OnSIGILL(int, siginfo_t *siginfo, void *context) { - // Write the first message using the bullet-proof write. - if (12 != AsanWrite(2, "ASAN:SIGILL\n", 12)) ASAN_DIE; - uintptr_t pc, sp, bp, ax; - GetPcSpBpAx(context, &pc, &sp, &bp, &ax); - - uintptr_t addr = ax; - - uint8_t *insn = (uint8_t*)pc; - CHECK(insn[0] == 0x0f && insn[1] == 0x0b); // ud2 - unsigned access_size_and_type = insn[2] - 0x50; - CHECK(access_size_and_type < 16); - bool is_write = access_size_and_type & 8; - int access_size = 1 << (access_size_and_type & 7); - __asan_report_error(pc, bp, sp, addr, is_write, access_size); -} - // exported functions #define ASAN_REPORT_ERROR(type, is_write, size) \ extern "C" void __asan_report_ ## type ## size(uintptr_t addr) \ @@ -465,7 +447,6 @@ } static bool MySignal(int signum) { - if (FLAG_handle_sigill && signum == SIGILL) return true; if (FLAG_handle_segv && signum == SIGSEGV) return true; #ifdef __APPLE__ if (FLAG_handle_segv && signum == SIGBUS) return true; @@ -692,7 +673,6 @@ FLAG_report_globals = IntFlagValue(options, "report_globals=", 1); FLAG_lazy_shadow = IntFlagValue(options, "lazy_shadow=", 0); FLAG_handle_segv = IntFlagValue(options, "handle_segv=", ASAN_NEEDS_SEGV); - FLAG_handle_sigill = IntFlagValue(options, "handle_sigill=", 0); FLAG_symbolize = IntFlagValue(options, "symbolize=", 1); FLAG_demangle = IntFlagValue(options, "demangle=", 1); FLAG_debug = IntFlagValue(options, "debug=", 0); @@ -743,7 +723,6 @@ MaybeInstallSigaction(SIGSEGV, ASAN_OnSIGSEGV); MaybeInstallSigaction(SIGBUS, ASAN_OnSIGSEGV); - MaybeInstallSigaction(SIGILL, ASAN_OnSIGILL); if (FLAG_v) { Printf("|| `[%p, %p]` || HighMem ||\n", kHighMemBeg, kHighMemEnd); From kcc at google.com Fri Jan 6 12:09:22 2012 From: kcc at google.com (Kostya Serebryany) Date: Fri, 06 Jan 2012 18:09:22 -0000 Subject: [llvm-commits] [llvm] r147667 - /llvm/trunk/lib/Transforms/Instrumentation/AddressSanitizer.cpp Message-ID: <20120106180922.3B21A2A6C12F@llvm.org> Author: kcc Date: Fri Jan 6 12:09:21 2012 New Revision: 147667 URL: http://llvm.org/viewvc/llvm-project?rev=147667&view=rev Log: [asan] cleanup: remove the SIGILL-related code (compiler part) Modified: llvm/trunk/lib/Transforms/Instrumentation/AddressSanitizer.cpp Modified: llvm/trunk/lib/Transforms/Instrumentation/AddressSanitizer.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Instrumentation/AddressSanitizer.cpp?rev=147667&r1=147666&r2=147667&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Instrumentation/AddressSanitizer.cpp (original) +++ llvm/trunk/lib/Transforms/Instrumentation/AddressSanitizer.cpp Fri Jan 6 12:09:21 2012 @@ -22,7 +22,6 @@ #include "llvm/ADT/SmallVector.h" #include "llvm/ADT/StringExtras.h" #include "llvm/Function.h" -#include "llvm/InlineAsm.h" #include "llvm/IntrinsicInst.h" #include "llvm/LLVMContext.h" #include "llvm/Module.h" @@ -93,9 +92,6 @@ static cl::opt ClBlackListFile("asan-blacklist", cl::desc("File containing the list of functions to ignore " "during instrumentation"), cl::Hidden); -static cl::opt ClUseCall("asan-use-call", - cl::desc("Use function call to generate a crash"), cl::Hidden, - cl::init(true)); // These flags allow to change the shadow mapping. // The shadow mapping looks like @@ -332,70 +328,14 @@ Instruction *AddressSanitizer::generateCrashCode( IRBuilder<> &IRB, Value *Addr, bool IsWrite, uint32_t TypeSize) { - - if (ClUseCall) { - // Here we use a call instead of arch-specific asm to report an error. - // This is almost always slower (because the codegen needs to generate - // prologue/epilogue for otherwise leaf functions) and generates more code. - // This mode could be useful if we can not use SIGILL for some reason. - // - // IsWrite and TypeSize are encoded in the function name. - std::string FunctionName = std::string(kAsanReportErrorTemplate) + - (IsWrite ? "store" : "load") + itostr(TypeSize / 8); - Value *ReportWarningFunc = CurrentModule->getOrInsertFunction( - FunctionName, IRB.getVoidTy(), IntptrTy, NULL); - CallInst *Call = IRB.CreateCall(ReportWarningFunc, Addr); - Call->setDoesNotReturn(); - return Call; - } - - uint32_t LogOfSizeInBytes = CountTrailingZeros_32(TypeSize / 8); - assert(8U * (1 << LogOfSizeInBytes) == TypeSize); - uint8_t TelltaleValue = IsWrite * 8 + LogOfSizeInBytes; - assert(TelltaleValue < 16); - - // Move the failing address to %rax/%eax - FunctionType *Fn1Ty = FunctionType::get( - IRB.getVoidTy(), ArrayRef(IntptrTy), false); - const char *MovStr = LongSize == 32 - ? "mov $0, %eax" : "mov $0, %rax"; - Value *AsmMov = InlineAsm::get( - Fn1Ty, StringRef(MovStr), StringRef("r"), true); - IRB.CreateCall(AsmMov, Addr); - - // crash with ud2; could use int3, but it is less friendly to gdb. - // after ud2 put a 1-byte instruction that encodes the access type and size. - - const char *TelltaleInsns[16] = { - "push %eax", // 0x50 - "push %ecx", // 0x51 - "push %edx", // 0x52 - "push %ebx", // 0x53 - "push %esp", // 0x54 - "push %ebp", // 0x55 - "push %esi", // 0x56 - "push %edi", // 0x57 - "pop %eax", // 0x58 - "pop %ecx", // 0x59 - "pop %edx", // 0x5a - "pop %ebx", // 0x5b - "pop %esp", // 0x5c - "pop %ebp", // 0x5d - "pop %esi", // 0x5e - "pop %edi" // 0x5f - }; - - std::string AsmStr = "ud2;"; - AsmStr += TelltaleInsns[TelltaleValue]; - Value *MyAsm = InlineAsm::get(FunctionType::get(Type::getVoidTy(*C), false), - StringRef(AsmStr), StringRef(""), true); - CallInst *AsmCall = IRB.CreateCall(MyAsm); - - // This saves us one jump, but triggers a bug in RA (or somewhere else): - // while building 483.xalancbmk the compiler goes into infinite loop in - // llvm::SpillPlacement::iterate() / RAGreedy::growRegion - // AsmCall->setDoesNotReturn(); - return AsmCall; + // IsWrite and TypeSize are encoded in the function name. + std::string FunctionName = std::string(kAsanReportErrorTemplate) + + (IsWrite ? "store" : "load") + itostr(TypeSize / 8); + Value *ReportWarningFunc = CurrentModule->getOrInsertFunction( + FunctionName, IRB.getVoidTy(), IntptrTy, NULL); + CallInst *Call = IRB.CreateCall(ReportWarningFunc, Addr); + Call->setDoesNotReturn(); + return Call; } void AddressSanitizer::instrumentAddress(Instruction *OrigIns, From clattner at apple.com Fri Jan 6 13:08:19 2012 From: clattner at apple.com (Chris Lattner) Date: Fri, 06 Jan 2012 11:08:19 -0800 Subject: [llvm-commits] [PATCH] Segmented stack fixes, support for Mac, Win32, FreeBSD In-Reply-To: <15219a20-6492-46b9-804e-7b198c586ca7@zimbra1.shared.sjc1.mozilla.com> References: <15219a20-6492-46b9-804e-7b198c586ca7@zimbra1.shared.sjc1.mozilla.com> Message-ID: <8A7D4C4F-14BB-49F3-914E-252C66F0D24E@apple.com> On Jan 5, 2012, at 3:54 PM, Brian Anderson wrote: > This series provides fixes to segmented stacks and adds support for x86 32-bit and 64-bit Mac, 32-bit Win32 and 64-bit FreeBSD. It builds on the __morestack mechanism implemented for Linux by gcc and LLVM. > > For each platform I had to pick a slot in the TCB to store the stack boundary. This is a difficult decision since that is precious real estate. On Win32 I am using the pvArbitrary slot, which is reserved for application use. On FreeBSD it uses tcb_spare. > > On Mac I have provisionally picked slot 90, which appears to already be reserved for JavaScript Core. I welcome any suggestions for a better location to store the stack boundary. > > The new operating systems only support frames of static size, as that is all that is needed by the Rust language. I did a brief scan of the patches and they seem reasonable to me. If Rafael has reviewed them in depth, then I'm ok with them. Using a slot reserved for JS Core seems grungy, but I don't have a better suggestion and we can always change it in the future if there is a problem. -Chris > > Regards, > Brian Anderson > > <0001-Explicitly-set-the-scale-to-1-on-some-segstack-prolo.patch><0002-Use-unsigned-comparison-in-segmented-stack-prologue.patch><0003-Generate-the-segmented-stack-prologue-differently-fo.patch><0004-Split-segmented-stacks-tests-into-tests-for-static-a.patch><0005-Support-segmented-stacks-on-mac.patch><0006-Make-segmented-stack-prologues-work-with-fastcc-on-3.patch><0007-Support-segmented-stacks-on-win32.patch><0008-Support-segmented-stacks-on-64-bit-FreeBSD.patch><0009-Add-tests-for-mac-segmented-stacks.patch><0010-Add-tests-for-win32-segmented-stacks.patch><0011-Add-tests-for-FreeBSD-segmented-stacks.patch>_______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From kcc at google.com Fri Jan 6 13:11:10 2012 From: kcc at google.com (Kostya Serebryany) Date: Fri, 06 Jan 2012 19:11:10 -0000 Subject: [llvm-commits] [compiler-rt] r147671 - in /compiler-rt/trunk/lib/asan: asan_internal.h asan_linux.cc asan_mac.cc asan_rtl.cc Message-ID
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