[llvm-commits] [llvm] r149548 - in /llvm/trunk: lib/Target/X86/X86ISelLowering.cpp test/CodeGen/X86/shl-i64.ll
nadav.rotem at intel.com
Fri Feb 3 05:11:05 CST 2012
A few weeks ago when I worked on a DAGCombine optimization I ran into the following problem. I accidently created a vector shift with a scalar shift amount. I wanted to address the problem by adding an assertion in DAG.getNode that checks that the shift amount is vector iff the first operand is a vector; However, I noticed that the cell backend has patterns that match scalar shift count for vectors.
From: llvm-commits-bounces at cs.uiuc.edu [mailto:llvm-commits-bounces at cs.uiuc.edu] On Behalf Of Duncan Sands
Sent: Friday, February 03, 2012 10:44
To: llvm-commits at cs.uiuc.edu
Subject: Re: [llvm-commits] [llvm] r149548 - in /llvm/trunk: lib/Target/X86/X86ISelLowering.cpp test/CodeGen/X86/shl-i64.ll
Hi, it looks like the shift amount has illegal type. Probably you should open a bug report about this.
> No, I don't see why this would behave differently on ppc vs x86. We are prevent generate an illegal i64 extract element.
> -- Mon Ping
> On Feb 2, 2012, at 3:53 AM, NAKAMURA Takumi wrote:
>> 2012/2/2 Mon P Wang<wangmp at apple.com>:
>>> Author: wangmp
>>> Date: Wed Feb 1 16:15:20 2012
>>> New Revision: 149548
>>> URL: http://llvm.org/viewvc/llvm-project?rev=149548&view=rev
>>> Avoid creating an extract element to an illegal type after LegalizeTypes has run.
>> It crashes on ppc32-linux. Any idea?
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