[LLVMdev] The live interval of write-only registers
sabre at nondot.org
Mon Dec 12 23:51:57 CST 2005
On Tue, 13 Dec 2005, Tzu-Chien Chiu wrote:
> 2005/12/13, Chris Lattner <sabre at nondot.org>:
>>> For example, this a code snippet for the file generated by the TableGen tool:
>>> Somewhere in my code, I have to write:
>>> unsigned opcode = MI->getOpcode(); // MachineInstr*
>>> if (CMPfaaaa == opcode ||
>>> CMPfaaar == opcode ||
>>> CMPfaara == opcode ||
>> Where do you have to write this code?
> Some machine idioms and instruction combining passes.
Ok, in that case, I suggest either writing helper functions that
encapsulate these predicates (e.g. is_op0_r) or modifying tablegen to
produce them for you. Do you have any other suggestions or ideas?
More information about the LLVMdev