[LLVMdev] Question about porting LLVM - code selection without assembler feature

Lu Mitnick king19880326 at gmail.com
Sat Jan 22 01:09:54 CST 2011


Hello all,

I am adding a new target into LLVM. However there is a assembler for that
target and I just want LLVM to generate assembly. I read the document
"Writing an LLVM Backend". I am wondering to know whether I can ignore the
Inst field in the following example:

class InstSP<dag outs, dag ins, string asmstr, list<dag> pattern> :
Instruction {

  field bits<32> Inst;
  let Namespace = "SP";
  bits<2> op;
  let Inst{31-30} = op;
  dag OutOperandList = outs;
  dag InOperandList = ins;
  let AsmString   = asmstr;
  let Pattern = pattern;
}

And define the instruction class of ported target as:

class Instxxx<dag outs, dag ins, string asmstr, list<dag> pattern> :
Instruction {

  let Namespace = "xxx";
  dag OutOperandList = outs;
  dag InOperandList = ins;
  let AsmString   = asmstr;
  let Pattern = pattern;
}

Second, I have read the documentation of "TableGen Fundamentals" and
"The LLVM Target Independent Code Generator". But I don't know how to
fill the dag filed of instruction. like [(store IntRegs:$src,
ADDRrr:$addr)] of the following example:

def STrr  : F3_1< 3, 0b000100, (outs), (ins MEMrr:$addr, IntRegs:$src),

               "st $src, [$addr]", [(store IntRegs:$src, ADDRrr:$addr)]>;


Would anyone mind to tell me where to find the documentation of the
dag in Independent Code Generator??


thanks a lot


yi-hong
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