[LLVMdev] Possible missed optimization?
borja.ferav at gmail.com
Sat Mar 26 15:04:30 CDT 2011
Hello Jakob, thanks for the reply. The three regclasses involved here are
all subsets from each other and aren't disjoint. These are the basic
descriptions of the regclasses involved to show what i mean:
DREGS: R31R30, R29R28 down to R1R0 (16 regs)
DLDREGS: R31R30, R29R28 down to R17R16 (8 regs)
PTRREGS: R31R30, R29R28, R27R26 (3 regs)
All classes intersect each other giving as a result the smaller class:
DREGSxDLDREGS=DLDREGS / DLDREGSxPTRREGS=PTRREGS, etc. That's why i think the
coalescer should work since the regclasses overlap completely.
-------------- next part --------------
An HTML attachment was scrubbed...
More information about the LLVMdev