[LLVMdev] Possible missed optimization?

[Borja Ferrer]

Hello Jakob, thanks for the reply. The three regclasses involved here are
all subsets from each other and aren't disjoint. These are the basic
descriptions of the regclasses involved to show what i mean:

DREGS: R31R30, R29R28 down to R1R0         (16 regs)
DLDREGS: R31R30, R29R28 down to R17R16  (8 regs)
PTRREGS: R31R30, R29R28, R27R26             (3 regs)

All classes intersect each other giving as a result the smaller class:
DREGSxDLDREGS=DLDREGS / DLDREGSxPTRREGS=PTRREGS, etc. That's why i think the
coalescer should work since the regclasses overlap completely.
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