[LLVMdev] Marking machineinstructions that are spills generated by register allocation
Jakob Stoklund Olesen
stoklund at 2pi.dk
Thu Sep 29 09:39:36 CDT 2011
On Sep 29, 2011, at 2:19 AM, Heikki Kultala wrote:
> Our TCE backend (which is not in the official llvm repo) benefits
> greatly from information that which memory load/store is a spill
> generated by register allocation.
> These spill memory operation can never alias with other memory
> operations, and our own instruction scheduler can optimize much better
> with better alias information.
This information is available from the instruction's memory operands.
See EmitComments() in lib/CodeGen/AsmPrinter/AsmPrinter.cpp.
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