[LLVMdev] Pattern matching in a SelectionDAG

Matthias Berndt matthias.berndt at studserv.uni-leipzig.de
Tue Jan 17 20:36:19 CST 2012


I'm trying to write an LLVM backend using LLVM's retargetable code 
generator, and I'm confused about how the SelectionDAG works. Let me give 
you an example from the SPARC backend (as this is what is often mentioned 
in the documentation). This is how the "branch always" instruction is 

def BA   : BranchSP<0b1000, (ins brtarget:$dst),
                      "ba $dst",
                      [(br bb:$dst)]>;

The pattern that is to be matched is simply (br bb: $dst). Based on this, I 
would have expected the pattern for an add instruction to look somehow like 
this: (add IntRegs:$b, IntRegs:$c). But in reality, it looks like this:
(set IntRegs:$dst, (add IntRegs:$b, IntRegs:$c))
What is this "set" thing all about? It doesn't seem to be a node in the 
graph, as the pattern is also matched in a graph in which the add node's 
ancestor is, say, a mul node. So what is it?


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